[net-next-2.6.git] / drivers / net / sfc / mtd.c

/****************************************************************************
 * Driver for Solarflare Solarstorm network controllers and boards
 * Copyright 2005-2006 Fen Systems Ltd.
 * Copyright 2006-2009 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */

#include <linux/bitops.h>
#include <linux/module.h>
#include <linux/mtd/mtd.h>
#include <linux/delay.h>
#include <linux/rtnetlink.h>

#define EFX_DRIVER_NAME "sfc_mtd"
#include "net_driver.h"
#include "spi.h"
#include "efx.h"
#include "nic.h"
#include "mcdi.h"
#include "mcdi_pcol.h"

#define EFX_SPI_VERIFY_BUF_LEN 16

struct efx_mtd_partition {
	struct mtd_info mtd;
	union {
		struct {
			bool updating;
			u8 nvram_type;
			u16 fw_subtype;
		} mcdi;
		size_t offset;
	};
	const char *type_name;
	char name[IFNAMSIZ + 20];
};

struct efx_mtd_ops {
	int (*read)(struct mtd_info *mtd, loff_t start, size_t len,
		    size_t *retlen, u8 *buffer);
	int (*erase)(struct mtd_info *mtd, loff_t start, size_t len);
	int (*write)(struct mtd_info *mtd, loff_t start, size_t len,
		     size_t *retlen, const u8 *buffer);
	int (*sync)(struct mtd_info *mtd);
};

struct efx_mtd {
	struct list_head node;
	struct efx_nic *efx;
	const struct efx_spi_device *spi;
	const char *name;
	const struct efx_mtd_ops *ops;
	size_t n_parts;
	struct efx_mtd_partition part[0];
};

#define efx_for_each_partition(part, efx_mtd)			\
	for ((part) = &(efx_mtd)->part[0];			\
	     (part) != &(efx_mtd)->part[(efx_mtd)->n_parts];	\
	     (part)++)

#define to_efx_mtd_partition(mtd)				\
	container_of(mtd, struct efx_mtd_partition, mtd)

static int falcon_mtd_probe(struct efx_nic *efx);
static int siena_mtd_probe(struct efx_nic *efx);

/* SPI utilities */

static int efx_spi_slow_wait(struct efx_mtd *efx_mtd, bool uninterruptible)
{
	const struct efx_spi_device *spi = efx_mtd->spi;
	struct efx_nic *efx = efx_mtd->efx;
	u8 status;
	int rc, i;

	/* Wait up to 4s for flash/EEPROM to finish a slow operation. */
	for (i = 0; i < 40; i++) {
		__set_current_state(uninterruptible ?
				    TASK_UNINTERRUPTIBLE : TASK_INTERRUPTIBLE);
		schedule_timeout(HZ / 10);
		rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
				    &status, sizeof(status));
		if (rc)
			return rc;
		if (!(status & SPI_STATUS_NRDY))
			return 0;
		if (signal_pending(current))
			return -EINTR;
	}
	EFX_ERR(efx, "timed out waiting for %s\n", efx_mtd->name);
	return -ETIMEDOUT;
}

static int
efx_spi_unlock(struct efx_nic *efx, const struct efx_spi_device *spi)
{
	const u8 unlock_mask = (SPI_STATUS_BP2 | SPI_STATUS_BP1 |
				SPI_STATUS_BP0);
	u8 status;
	int rc;

	rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
			    &status, sizeof(status));
	if (rc)
		return rc;

	if (!(status & unlock_mask))
		return 0; /* already unlocked */

	rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
	if (rc)
		return rc;
	rc = falcon_spi_cmd(efx, spi, SPI_SST_EWSR, -1, NULL, NULL, 0);
	if (rc)
		return rc;

	status &= ~unlock_mask;
	rc = falcon_spi_cmd(efx, spi, SPI_WRSR, -1, &status,
			    NULL, sizeof(status));
	if (rc)
		return rc;
	rc = falcon_spi_wait_write(efx, spi);
	if (rc)
		return rc;

	return 0;
}

static int efx_spi_erase(struct efx_mtd *efx_mtd, loff_t start, size_t len)
{
	const struct efx_spi_device *spi = efx_mtd->spi;
	struct efx_nic *efx = efx_mtd->efx;
	unsigned pos, block_len;
	u8 empty[EFX_SPI_VERIFY_BUF_LEN];
	u8 buffer[EFX_SPI_VERIFY_BUF_LEN];
	int rc;

	if (len != spi->erase_size)
		return -EINVAL;

	if (spi->erase_command == 0)
		return -EOPNOTSUPP;

	rc = efx_spi_unlock(efx, spi);
	if (rc)
		return rc;
	rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
	if (rc)
		return rc;
	rc = falcon_spi_cmd(efx, spi, spi->erase_command, start, NULL,
			    NULL, 0);
	if (rc)
		return rc;
	rc = efx_spi_slow_wait(efx_mtd, false);

	/* Verify the entire region has been wiped */
	memset(empty, 0xff, sizeof(empty));
	for (pos = 0; pos < len; pos += block_len) {
		block_len = min(len - pos, sizeof(buffer));
		rc = falcon_spi_read(efx, spi, start + pos, block_len,
				     NULL, buffer);
		if (rc)
			return rc;
		if (memcmp(empty, buffer, block_len))
			return -EIO;

		/* Avoid locking up the system */
		cond_resched();
		if (signal_pending(current))
			return -EINTR;
	}

	return rc;
}

/* MTD interface */

static int efx_mtd_erase(struct mtd_info *mtd, struct erase_info *erase)
{
	struct efx_mtd *efx_mtd = mtd->priv;
	int rc;

	rc = efx_mtd->ops->erase(mtd, erase->addr, erase->len);
	if (rc == 0) {
		erase->state = MTD_ERASE_DONE;
	} else {
		erase->state = MTD_ERASE_FAILED;
		erase->fail_addr = 0xffffffff;
	}
	mtd_erase_callback(erase);
	return rc;
}

static void efx_mtd_sync(struct mtd_info *mtd)
{
	struct efx_mtd *efx_mtd = mtd->priv;
	struct efx_nic *efx = efx_mtd->efx;
	int rc;

	rc = efx_mtd->ops->sync(mtd);
	if (rc)
		EFX_ERR(efx, "%s sync failed (%d)\n", efx_mtd->name, rc);
}

static void efx_mtd_remove_partition(struct efx_mtd_partition *part)
{
	int rc;

	for (;;) {
		rc = del_mtd_device(&part->mtd);
		if (rc != -EBUSY)
			break;
		ssleep(1);
	}
	WARN_ON(rc);
}

static void efx_mtd_remove_device(struct efx_mtd *efx_mtd)
{
	struct efx_mtd_partition *part;

	efx_for_each_partition(part, efx_mtd)
		efx_mtd_remove_partition(part);
	list_del(&efx_mtd->node);
	kfree(efx_mtd);
}

static void efx_mtd_rename_device(struct efx_mtd *efx_mtd)
{
	struct efx_mtd_partition *part;

	efx_for_each_partition(part, efx_mtd)
		if (efx_nic_rev(efx_mtd->efx) >= EFX_REV_SIENA_A0)
			snprintf(part->name, sizeof(part->name),
				 "%s %s:%02x", efx_mtd->efx->name,
				 part->type_name, part->mcdi.fw_subtype);
		else
			snprintf(part->name, sizeof(part->name),
				 "%s %s", efx_mtd->efx->name,
				 part->type_name);
}

static int efx_mtd_probe_device(struct efx_nic *efx, struct efx_mtd *efx_mtd)
{
	struct efx_mtd_partition *part;

	efx_mtd->efx = efx;

	efx_mtd_rename_device(efx_mtd);

	efx_for_each_partition(part, efx_mtd) {
		part->mtd.writesize = 1;

		part->mtd.owner = THIS_MODULE;
		part->mtd.priv = efx_mtd;
		part->mtd.name = part->name;
		part->mtd.erase = efx_mtd_erase;
		part->mtd.read = efx_mtd->ops->read;
		part->mtd.write = efx_mtd->ops->write;
		part->mtd.sync = efx_mtd_sync;

		if (add_mtd_device(&part->mtd))
			goto fail;
	}

	list_add(&efx_mtd->node, &efx->mtd_list);
	return 0;

fail:
	while (part != &efx_mtd->part[0]) {
		--part;
		efx_mtd_remove_partition(part);
	}
	/* add_mtd_device() returns 1 if the MTD table is full */
	return -ENOMEM;
}

void efx_mtd_remove(struct efx_nic *efx)
{
	struct efx_mtd *efx_mtd, *next;

	WARN_ON(efx_dev_registered(efx));

	list_for_each_entry_safe(efx_mtd, next, &efx->mtd_list, node)
		efx_mtd_remove_device(efx_mtd);
}

void efx_mtd_rename(struct efx_nic *efx)
{
	struct efx_mtd *efx_mtd;

	ASSERT_RTNL();

	list_for_each_entry(efx_mtd, &efx->mtd_list, node)
		efx_mtd_rename_device(efx_mtd);
}

int efx_mtd_probe(struct efx_nic *efx)
{
	if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
		return siena_mtd_probe(efx);
	else
		return falcon_mtd_probe(efx);
}

/* Implementation of MTD operations for Falcon */

static int falcon_mtd_read(struct mtd_info *mtd, loff_t start,
			   size_t len, size_t *retlen, u8 *buffer)
{
	struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
	struct efx_mtd *efx_mtd = mtd->priv;
	const struct efx_spi_device *spi = efx_mtd->spi;
	struct efx_nic *efx = efx_mtd->efx;
	int rc;

	rc = mutex_lock_interruptible(&efx->spi_lock);
	if (rc)
		return rc;
	rc = falcon_spi_read(efx, spi, part->offset + start, len,
			     retlen, buffer);
	mutex_unlock(&efx->spi_lock);
	return rc;
}

static int falcon_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
{
	struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
	struct efx_mtd *efx_mtd = mtd->priv;
	struct efx_nic *efx = efx_mtd->efx;
	int rc;

	rc = mutex_lock_interruptible(&efx->spi_lock);
	if (rc)
		return rc;
	rc = efx_spi_erase(efx_mtd, part->offset + start, len);
	mutex_unlock(&efx->spi_lock);
	return rc;
}

static int falcon_mtd_write(struct mtd_info *mtd, loff_t start,
			    size_t len, size_t *retlen, const u8 *buffer)
{
	struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
	struct efx_mtd *efx_mtd = mtd->priv;
	const struct efx_spi_device *spi = efx_mtd->spi;
	struct efx_nic *efx = efx_mtd->efx;
	int rc;

	rc = mutex_lock_interruptible(&efx->spi_lock);
	if (rc)
		return rc;
	rc = falcon_spi_write(efx, spi, part->offset + start, len,
			      retlen, buffer);
	mutex_unlock(&efx->spi_lock);
	return rc;
}

static int falcon_mtd_sync(struct mtd_info *mtd)
{
	struct efx_mtd *efx_mtd = mtd->priv;
	struct efx_nic *efx = efx_mtd->efx;
	int rc;

	mutex_lock(&efx->spi_lock);
	rc = efx_spi_slow_wait(efx_mtd, true);
	mutex_unlock(&efx->spi_lock);
	return rc;
}

static struct efx_mtd_ops falcon_mtd_ops = {
	.read	= falcon_mtd_read,
	.erase	= falcon_mtd_erase,
	.write	= falcon_mtd_write,
	.sync	= falcon_mtd_sync,
};

static int falcon_mtd_probe(struct efx_nic *efx)
{
	struct efx_spi_device *spi = efx->spi_flash;
	struct efx_mtd *efx_mtd;
	int rc;

	ASSERT_RTNL();

	if (!spi || spi->size <= FALCON_FLASH_BOOTCODE_START)
		return -ENODEV;

	efx_mtd = kzalloc(sizeof(*efx_mtd) + sizeof(efx_mtd->part[0]),
			  GFP_KERNEL);
	if (!efx_mtd)
		return -ENOMEM;

	efx_mtd->spi = spi;
	efx_mtd->name = "flash";
	efx_mtd->ops = &falcon_mtd_ops;

	efx_mtd->n_parts = 1;
	efx_mtd->part[0].mtd.type = MTD_NORFLASH;
	efx_mtd->part[0].mtd.flags = MTD_CAP_NORFLASH;
	efx_mtd->part[0].mtd.size = spi->size - FALCON_FLASH_BOOTCODE_START;
	efx_mtd->part[0].mtd.erasesize = spi->erase_size;
	efx_mtd->part[0].offset = FALCON_FLASH_BOOTCODE_START;
	efx_mtd->part[0].type_name = "sfc_flash_bootrom";

	rc = efx_mtd_probe_device(efx, efx_mtd);
	if (rc)
		kfree(efx_mtd);
	return rc;
}

/* Implementation of MTD operations for Siena */

static int siena_mtd_read(struct mtd_info *mtd, loff_t start,
			  size_t len, size_t *retlen, u8 *buffer)
{
	struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
	struct efx_mtd *efx_mtd = mtd->priv;
	struct efx_nic *efx = efx_mtd->efx;
	loff_t offset = start;
	loff_t end = min_t(loff_t, start + len, mtd->size);
	size_t chunk;
	int rc = 0;

	while (offset < end) {
		chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX);
		rc = efx_mcdi_nvram_read(efx, part->mcdi.nvram_type, offset,
					 buffer, chunk);
		if (rc)
			goto out;
		offset += chunk;
		buffer += chunk;
	}
out:
	*retlen = offset - start;
	return rc;
}

static int siena_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
{
	struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
	struct efx_mtd *efx_mtd = mtd->priv;
	struct efx_nic *efx = efx_mtd->efx;
	loff_t offset = start & ~((loff_t)(mtd->erasesize - 1));
	loff_t end = min_t(loff_t, start + len, mtd->size);
	size_t chunk = part->mtd.erasesize;
	int rc = 0;

	if (!part->mcdi.updating) {
		rc = efx_mcdi_nvram_update_start(efx, part->mcdi.nvram_type);
		if (rc)
			goto out;
		part->mcdi.updating = 1;
	}

	/* The MCDI interface can in fact do multiple erase blocks at once;
	 * but erasing may be slow, so we make multiple calls here to avoid
	 * tripping the MCDI RPC timeout. */
	while (offset < end) {
		rc = efx_mcdi_nvram_erase(efx, part->mcdi.nvram_type, offset,
					  chunk);
		if (rc)
			goto out;
		offset += chunk;
	}
out:
	return rc;
}

static int siena_mtd_write(struct mtd_info *mtd, loff_t start,
			   size_t len, size_t *retlen, const u8 *buffer)
{
	struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
	struct efx_mtd *efx_mtd = mtd->priv;
	struct efx_nic *efx = efx_mtd->efx;
	loff_t offset = start;
	loff_t end = min_t(loff_t, start + len, mtd->size);
	size_t chunk;
	int rc = 0;

	if (!part->mcdi.updating) {
		rc = efx_mcdi_nvram_update_start(efx, part->mcdi.nvram_type);
		if (rc)
			goto out;
		part->mcdi.updating = 1;
	}

	while (offset < end) {
		chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX);
		rc = efx_mcdi_nvram_write(efx, part->mcdi.nvram_type, offset,
					  buffer, chunk);
		if (rc)
			goto out;
		offset += chunk;
		buffer += chunk;
	}
out:
	*retlen = offset - start;
	return rc;
}

static int siena_mtd_sync(struct mtd_info *mtd)
{
	struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
	struct efx_mtd *efx_mtd = mtd->priv;
	struct efx_nic *efx = efx_mtd->efx;
	int rc = 0;

	if (part->mcdi.updating) {
		part->mcdi.updating = 0;
		rc = efx_mcdi_nvram_update_finish(efx, part->mcdi.nvram_type);
	}

	return rc;
}

static struct efx_mtd_ops siena_mtd_ops = {
	.read	= siena_mtd_read,
	.erase	= siena_mtd_erase,
	.write	= siena_mtd_write,
	.sync	= siena_mtd_sync,
};

struct siena_nvram_type_info {
	int port;
	const char *name;
};

static struct siena_nvram_type_info siena_nvram_types[] = {
	[MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO]	= { 0, "sfc_dummy_phy" },
	[MC_CMD_NVRAM_TYPE_MC_FW]		= { 0, "sfc_mcfw" },
	[MC_CMD_NVRAM_TYPE_MC_FW_BACKUP]	= { 0, "sfc_mcfw_backup" },
	[MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0]	= { 0, "sfc_static_cfg" },
	[MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1]	= { 1, "sfc_static_cfg" },
	[MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0]	= { 0, "sfc_dynamic_cfg" },
	[MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1]	= { 1, "sfc_dynamic_cfg" },
	[MC_CMD_NVRAM_TYPE_EXP_ROM]		= { 0, "sfc_exp_rom" },
	[MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0]	= { 0, "sfc_exp_rom_cfg" },
	[MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1]	= { 1, "sfc_exp_rom_cfg" },
	[MC_CMD_NVRAM_TYPE_PHY_PORT0]		= { 0, "sfc_phy_fw" },
	[MC_CMD_NVRAM_TYPE_PHY_PORT1]		= { 1, "sfc_phy_fw" },
};

static int siena_mtd_probe_partition(struct efx_nic *efx,
				     struct efx_mtd *efx_mtd,
				     unsigned int part_id,
				     unsigned int type)
{
	struct efx_mtd_partition *part = &efx_mtd->part[part_id];
	struct siena_nvram_type_info *info;
	size_t size, erase_size;
	bool protected;
	int rc;

	if (type >= ARRAY_SIZE(siena_nvram_types))
		return -ENODEV;

	info = &siena_nvram_types[type];

	if (info->port != efx_port_num(efx))
		return -ENODEV;

	rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
	if (rc)
		return rc;
	if (protected)
		return -ENODEV; /* hide it */

	part->mcdi.nvram_type = type;
	part->type_name = info->name;

	part->mtd.type = MTD_NORFLASH;
	part->mtd.flags = MTD_CAP_NORFLASH;
	part->mtd.size = size;
	part->mtd.erasesize = erase_size;

	return 0;
}

static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
				     struct efx_mtd *efx_mtd)
{
	struct efx_mtd_partition *part;
	uint16_t fw_subtype_list[MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN /
				 sizeof(uint16_t)];
	int rc;

	rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list);
	if (rc)
		return rc;

	efx_for_each_partition(part, efx_mtd)
		part->mcdi.fw_subtype = fw_subtype_list[part->mcdi.nvram_type];

	return 0;
}

static int siena_mtd_probe(struct efx_nic *efx)
{
	struct efx_mtd *efx_mtd;
	int rc = -ENODEV;
	u32 nvram_types;
	unsigned int type;

	ASSERT_RTNL();

	rc = efx_mcdi_nvram_types(efx, &nvram_types);
	if (rc)
		return rc;

	efx_mtd = kzalloc(sizeof(*efx_mtd) +
			  hweight32(nvram_types) * sizeof(efx_mtd->part[0]),
			  GFP_KERNEL);
	if (!efx_mtd)
		return -ENOMEM;

	efx_mtd->name = "Siena NVRAM manager";

	efx_mtd->ops = &siena_mtd_ops;

	type = 0;
	efx_mtd->n_parts = 0;

	while (nvram_types != 0) {
		if (nvram_types & 1) {
			rc = siena_mtd_probe_partition(efx, efx_mtd,
						       efx_mtd->n_parts, type);
			if (rc == 0)
				efx_mtd->n_parts++;
			else if (rc != -ENODEV)
				goto fail;
		}
		type++;
		nvram_types >>= 1;
	}

	rc = siena_mtd_get_fw_subtypes(efx, efx_mtd);
	if (rc)
		goto fail;

	rc = efx_mtd_probe_device(efx, efx_mtd);
fail:
	if (rc)
		kfree(efx_mtd);
	return rc;
}
Commit	Line	Data
f4150724 BH	1	/****************************************************************************
	2	* Driver for Solarflare Solarstorm network controllers and boards
	3	* Copyright 2005-2006 Fen Systems Ltd.
906bb26c	4	* Copyright 2006-2009 Solarflare Communications Inc.
f4150724 BH	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published
	8	* by the Free Software Foundation, incorporated herein by reference.
	9	*/
	10
8880f4ec	11	#include <linux/bitops.h>
f4150724 BH	12	#include <linux/module.h>
	13	#include <linux/mtd/mtd.h>
	14	#include <linux/delay.h>
76884835	15	#include <linux/rtnetlink.h>
f4150724 BH	16
	17	#define EFX_DRIVER_NAME "sfc_mtd"
	18	#include "net_driver.h"
	19	#include "spi.h"
ff2ef902	20	#include "efx.h"
744093c9	21	#include "nic.h"
8880f4ec BH	22	#include "mcdi.h"
8880f4ec BH	23	#include "mcdi_pcol.h"
f4150724 BH	24
	25	#define EFX_SPI_VERIFY_BUF_LEN 16
	26
76884835	27	struct efx_mtd_partition {
f4150724	28	struct mtd_info mtd;
8880f4ec BH	29	union {
	30	struct {
	31	bool updating;
	32	u8 nvram_type;
	33	u16 fw_subtype;
	34	} mcdi;
	35	size_t offset;
	36	};
76884835	37	const char *type_name;
f4150724 BH	38	char name[IFNAMSIZ + 20];
	39	};
	40
76884835 BH	41	struct efx_mtd_ops {
	42	int (read)(struct mtd_info mtd, loff_t start, size_t len,
	43	size_t retlen, u8 buffer);
	44	int (erase)(struct mtd_info mtd, loff_t start, size_t len);
	45	int (write)(struct mtd_info mtd, loff_t start, size_t len,
	46	size_t retlen, const u8 buffer);
	47	int (sync)(struct mtd_info mtd);
	48	};
	49
	50	struct efx_mtd {
	51	struct list_head node;
	52	struct efx_nic *efx;
	53	const struct efx_spi_device *spi;
	54	const char *name;
	55	const struct efx_mtd_ops *ops;
	56	size_t n_parts;
	57	struct efx_mtd_partition part[0];
	58	};
	59
	60	#define efx_for_each_partition(part, efx_mtd) \
	61	for ((part) = &(efx_mtd)->part[0]; \
	62	(part) != &(efx_mtd)->part[(efx_mtd)->n_parts]; \
	63	(part)++)
	64
	65	#define to_efx_mtd_partition(mtd) \
	66	container_of(mtd, struct efx_mtd_partition, mtd)
	67
	68	static int falcon_mtd_probe(struct efx_nic *efx);
8880f4ec	69	static int siena_mtd_probe(struct efx_nic *efx);
76884835	70
f4150724 BH	71	/* SPI utilities */
	72
	73	static int efx_spi_slow_wait(struct efx_mtd *efx_mtd, bool uninterruptible)
	74	{
	75	const struct efx_spi_device *spi = efx_mtd->spi;
76884835	76	struct efx_nic *efx = efx_mtd->efx;
f4150724 BH	77	u8 status;
	78	int rc, i;
	79
	80	/* Wait up to 4s for flash/EEPROM to finish a slow operation. */
	81	for (i = 0; i < 40; i++) {
	82	__set_current_state(uninterruptible ?
	83	TASK_UNINTERRUPTIBLE : TASK_INTERRUPTIBLE);
	84	schedule_timeout(HZ / 10);
76884835	85	rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
f4150724 BH	86	&status, sizeof(status));
	87	if (rc)
	88	return rc;
	89	if (!(status & SPI_STATUS_NRDY))
	90	return 0;
	91	if (signal_pending(current))
	92	return -EINTR;
	93	}
	94	EFX_ERR(efx, "timed out waiting for %s\n", efx_mtd->name);
	95	return -ETIMEDOUT;
	96	}
	97
76884835 BH	98	static int
76884835 BH	99	efx_spi_unlock(struct efx_nic efx, const struct efx_spi_device spi)
f4150724 BH	100	{
	101	const u8 unlock_mask = (SPI_STATUS_BP2 \| SPI_STATUS_BP1 \|
	102	SPI_STATUS_BP0);
	103	u8 status;
	104	int rc;
	105
76884835 BH	106	rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
76884835 BH	107	&status, sizeof(status));
f4150724 BH	108	if (rc)
	109	return rc;
	110
	111	if (!(status & unlock_mask))
	112	return 0; /* already unlocked */
	113
76884835	114	rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
f4150724 BH	115	if (rc)
f4150724 BH	116	return rc;
76884835	117	rc = falcon_spi_cmd(efx, spi, SPI_SST_EWSR, -1, NULL, NULL, 0);
f4150724 BH	118	if (rc)
	119	return rc;
	120
	121	status &= ~unlock_mask;
76884835 BH	122	rc = falcon_spi_cmd(efx, spi, SPI_WRSR, -1, &status,
76884835 BH	123	NULL, sizeof(status));
f4150724 BH	124	if (rc)
f4150724 BH	125	return rc;
76884835	126	rc = falcon_spi_wait_write(efx, spi);
f4150724 BH	127	if (rc)
	128	return rc;
	129
	130	return 0;
	131	}
	132
	133	static int efx_spi_erase(struct efx_mtd *efx_mtd, loff_t start, size_t len)
	134	{
	135	const struct efx_spi_device *spi = efx_mtd->spi;
76884835	136	struct efx_nic *efx = efx_mtd->efx;
f4150724 BH	137	unsigned pos, block_len;
	138	u8 empty[EFX_SPI_VERIFY_BUF_LEN];
	139	u8 buffer[EFX_SPI_VERIFY_BUF_LEN];
	140	int rc;
	141
	142	if (len != spi->erase_size)
	143	return -EINVAL;
	144
	145	if (spi->erase_command == 0)
	146	return -EOPNOTSUPP;
	147
76884835	148	rc = efx_spi_unlock(efx, spi);
f4150724 BH	149	if (rc)
f4150724 BH	150	return rc;
76884835	151	rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
f4150724 BH	152	if (rc)
f4150724 BH	153	return rc;
76884835 BH	154	rc = falcon_spi_cmd(efx, spi, spi->erase_command, start, NULL,
76884835 BH	155	NULL, 0);
f4150724 BH	156	if (rc)
	157	return rc;
	158	rc = efx_spi_slow_wait(efx_mtd, false);
	159
	160	/* Verify the entire region has been wiped */
	161	memset(empty, 0xff, sizeof(empty));
	162	for (pos = 0; pos < len; pos += block_len) {
	163	block_len = min(len - pos, sizeof(buffer));
76884835 BH	164	rc = falcon_spi_read(efx, spi, start + pos, block_len,
76884835 BH	165	NULL, buffer);
f4150724 BH	166	if (rc)
	167	return rc;
	168	if (memcmp(empty, buffer, block_len))
	169	return -EIO;
	170
	171	/* Avoid locking up the system */
	172	cond_resched();
	173	if (signal_pending(current))
	174	return -EINTR;
	175	}
	176
	177	return rc;
	178	}
	179
	180	/* MTD interface */
	181
76884835 BH	182	static int efx_mtd_erase(struct mtd_info mtd, struct erase_info erase)
	183	{
	184	struct efx_mtd *efx_mtd = mtd->priv;
	185	int rc;
	186
	187	rc = efx_mtd->ops->erase(mtd, erase->addr, erase->len);
	188	if (rc == 0) {
	189	erase->state = MTD_ERASE_DONE;
	190	} else {
	191	erase->state = MTD_ERASE_FAILED;
	192	erase->fail_addr = 0xffffffff;
	193	}
	194	mtd_erase_callback(erase);
	195	return rc;
	196	}
	197
	198	static void efx_mtd_sync(struct mtd_info *mtd)
	199	{
	200	struct efx_mtd *efx_mtd = mtd->priv;
	201	struct efx_nic *efx = efx_mtd->efx;
	202	int rc;
	203
	204	rc = efx_mtd->ops->sync(mtd);
	205	if (rc)
	206	EFX_ERR(efx, "%s sync failed (%d)\n", efx_mtd->name, rc);
	207	}
	208
	209	static void efx_mtd_remove_partition(struct efx_mtd_partition *part)
	210	{
	211	int rc;
	212
	213	for (;;) {
	214	rc = del_mtd_device(&part->mtd);
	215	if (rc != -EBUSY)
	216	break;
	217	ssleep(1);
	218	}
	219	WARN_ON(rc);
	220	}
	221
	222	static void efx_mtd_remove_device(struct efx_mtd *efx_mtd)
	223	{
	224	struct efx_mtd_partition *part;
	225
	226	efx_for_each_partition(part, efx_mtd)
	227	efx_mtd_remove_partition(part);
	228	list_del(&efx_mtd->node);
	229	kfree(efx_mtd);
	230	}
	231
	232	static void efx_mtd_rename_device(struct efx_mtd *efx_mtd)
	233	{
	234	struct efx_mtd_partition *part;
	235
	236	efx_for_each_partition(part, efx_mtd)
8880f4ec BH	237	if (efx_nic_rev(efx_mtd->efx) >= EFX_REV_SIENA_A0)
	238	snprintf(part->name, sizeof(part->name),
	239	"%s %s:%02x", efx_mtd->efx->name,
	240	part->type_name, part->mcdi.fw_subtype);
	241	else
	242	snprintf(part->name, sizeof(part->name),
	243	"%s %s", efx_mtd->efx->name,
	244	part->type_name);
76884835 BH	245	}
	246
	247	static int efx_mtd_probe_device(struct efx_nic efx, struct efx_mtd efx_mtd)
	248	{
	249	struct efx_mtd_partition *part;
	250
	251	efx_mtd->efx = efx;
	252
	253	efx_mtd_rename_device(efx_mtd);
	254
	255	efx_for_each_partition(part, efx_mtd) {
	256	part->mtd.writesize = 1;
	257
	258	part->mtd.owner = THIS_MODULE;
	259	part->mtd.priv = efx_mtd;
	260	part->mtd.name = part->name;
	261	part->mtd.erase = efx_mtd_erase;
	262	part->mtd.read = efx_mtd->ops->read;
	263	part->mtd.write = efx_mtd->ops->write;
	264	part->mtd.sync = efx_mtd_sync;
	265
	266	if (add_mtd_device(&part->mtd))
	267	goto fail;
	268	}
	269
	270	list_add(&efx_mtd->node, &efx->mtd_list);
	271	return 0;
	272
	273	fail:
	274	while (part != &efx_mtd->part[0]) {
	275	--part;
	276	efx_mtd_remove_partition(part);
	277	}
	278	/* add_mtd_device() returns 1 if the MTD table is full */
	279	return -ENOMEM;
	280	}
	281
	282	void efx_mtd_remove(struct efx_nic *efx)
f4150724	283	{
76884835 BH	284	struct efx_mtd efx_mtd, next;
	285
	286	WARN_ON(efx_dev_registered(efx));
	287
	288	list_for_each_entry_safe(efx_mtd, next, &efx->mtd_list, node)
	289	efx_mtd_remove_device(efx_mtd);
	290	}
	291
	292	void efx_mtd_rename(struct efx_nic *efx)
	293	{
	294	struct efx_mtd *efx_mtd;
	295
	296	ASSERT_RTNL();
	297
	298	list_for_each_entry(efx_mtd, &efx->mtd_list, node)
	299	efx_mtd_rename_device(efx_mtd);
	300	}
	301
	302	int efx_mtd_probe(struct efx_nic *efx)
	303	{
8880f4ec BH	304	if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
	305	return siena_mtd_probe(efx);
	306	else
	307	return falcon_mtd_probe(efx);
76884835 BH	308	}
	309
	310	/* Implementation of MTD operations for Falcon */
	311
	312	static int falcon_mtd_read(struct mtd_info *mtd, loff_t start,
	313	size_t len, size_t retlen, u8 buffer)
	314	{
	315	struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
f4150724 BH	316	struct efx_mtd *efx_mtd = mtd->priv;
f4150724 BH	317	const struct efx_spi_device *spi = efx_mtd->spi;
76884835	318	struct efx_nic *efx = efx_mtd->efx;
f4150724 BH	319	int rc;
	320
	321	rc = mutex_lock_interruptible(&efx->spi_lock);
	322	if (rc)
	323	return rc;
76884835 BH	324	rc = falcon_spi_read(efx, spi, part->offset + start, len,
76884835 BH	325	retlen, buffer);
f4150724 BH	326	mutex_unlock(&efx->spi_lock);
	327	return rc;
	328	}
	329
76884835	330	static int falcon_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
f4150724	331	{
76884835	332	struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
f4150724	333	struct efx_mtd *efx_mtd = mtd->priv;
76884835	334	struct efx_nic *efx = efx_mtd->efx;
f4150724 BH	335	int rc;
	336
	337	rc = mutex_lock_interruptible(&efx->spi_lock);
	338	if (rc)
	339	return rc;
76884835	340	rc = efx_spi_erase(efx_mtd, part->offset + start, len);
f4150724	341	mutex_unlock(&efx->spi_lock);
f4150724 BH	342	return rc;
	343	}
	344
76884835 BH	345	static int falcon_mtd_write(struct mtd_info *mtd, loff_t start,
76884835 BH	346	size_t len, size_t retlen, const u8 buffer)
f4150724	347	{
76884835	348	struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
f4150724 BH	349	struct efx_mtd *efx_mtd = mtd->priv;
f4150724 BH	350	const struct efx_spi_device *spi = efx_mtd->spi;
76884835	351	struct efx_nic *efx = efx_mtd->efx;
f4150724 BH	352	int rc;
	353
	354	rc = mutex_lock_interruptible(&efx->spi_lock);
	355	if (rc)
	356	return rc;
76884835 BH	357	rc = falcon_spi_write(efx, spi, part->offset + start, len,
76884835 BH	358	retlen, buffer);
f4150724 BH	359	mutex_unlock(&efx->spi_lock);
	360	return rc;
	361	}
	362
76884835	363	static int falcon_mtd_sync(struct mtd_info *mtd)
f4150724 BH	364	{
f4150724 BH	365	struct efx_mtd *efx_mtd = mtd->priv;
76884835	366	struct efx_nic *efx = efx_mtd->efx;
f4150724 BH	367	int rc;
	368
	369	mutex_lock(&efx->spi_lock);
	370	rc = efx_spi_slow_wait(efx_mtd, true);
	371	mutex_unlock(&efx->spi_lock);
76884835	372	return rc;
f4150724 BH	373	}
f4150724 BH	374
76884835 BH	375	static struct efx_mtd_ops falcon_mtd_ops = {
	376	.read = falcon_mtd_read,
	377	.erase = falcon_mtd_erase,
	378	.write = falcon_mtd_write,
	379	.sync = falcon_mtd_sync,
	380	};
f4150724	381
76884835	382	static int falcon_mtd_probe(struct efx_nic *efx)
f4150724 BH	383	{
	384	struct efx_spi_device *spi = efx->spi_flash;
	385	struct efx_mtd *efx_mtd;
76884835 BH	386	int rc;
	387
	388	ASSERT_RTNL();
f4150724 BH	389
	390	if (!spi \|\| spi->size <= FALCON_FLASH_BOOTCODE_START)
	391	return -ENODEV;
	392
76884835 BH	393	efx_mtd = kzalloc(sizeof(*efx_mtd) + sizeof(efx_mtd->part[0]),
76884835 BH	394	GFP_KERNEL);
f4150724 BH	395	if (!efx_mtd)
	396	return -ENOMEM;
	397
	398	efx_mtd->spi = spi;
76884835 BH	399	efx_mtd->name = "flash";
	400	efx_mtd->ops = &falcon_mtd_ops;
	401
	402	efx_mtd->n_parts = 1;
	403	efx_mtd->part[0].mtd.type = MTD_NORFLASH;
	404	efx_mtd->part[0].mtd.flags = MTD_CAP_NORFLASH;
	405	efx_mtd->part[0].mtd.size = spi->size - FALCON_FLASH_BOOTCODE_START;
	406	efx_mtd->part[0].mtd.erasesize = spi->erase_size;
	407	efx_mtd->part[0].offset = FALCON_FLASH_BOOTCODE_START;
	408	efx_mtd->part[0].type_name = "sfc_flash_bootrom";
	409
	410	rc = efx_mtd_probe_device(efx, efx_mtd);
	411	if (rc)
f4150724	412	kfree(efx_mtd);
76884835	413	return rc;
f4150724	414	}
8880f4ec BH	415
	416	/* Implementation of MTD operations for Siena */
	417
	418	static int siena_mtd_read(struct mtd_info *mtd, loff_t start,
	419	size_t len, size_t retlen, u8 buffer)
	420	{
	421	struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
	422	struct efx_mtd *efx_mtd = mtd->priv;
	423	struct efx_nic *efx = efx_mtd->efx;
	424	loff_t offset = start;
	425	loff_t end = min_t(loff_t, start + len, mtd->size);
	426	size_t chunk;
	427	int rc = 0;
	428
	429	while (offset < end) {
5a27e86b	430	chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX);
8880f4ec BH	431	rc = efx_mcdi_nvram_read(efx, part->mcdi.nvram_type, offset,
	432	buffer, chunk);
	433	if (rc)
	434	goto out;
	435	offset += chunk;
	436	buffer += chunk;
	437	}
	438	out:
	439	*retlen = offset - start;
	440	return rc;
	441	}
	442
	443	static int siena_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
	444	{
	445	struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
	446	struct efx_mtd *efx_mtd = mtd->priv;
	447	struct efx_nic *efx = efx_mtd->efx;
	448	loff_t offset = start & ~((loff_t)(mtd->erasesize - 1));
	449	loff_t end = min_t(loff_t, start + len, mtd->size);
	450	size_t chunk = part->mtd.erasesize;
	451	int rc = 0;
	452
	453	if (!part->mcdi.updating) {
	454	rc = efx_mcdi_nvram_update_start(efx, part->mcdi.nvram_type);
	455	if (rc)
	456	goto out;
	457	part->mcdi.updating = 1;
	458	}
	459
	460	/* The MCDI interface can in fact do multiple erase blocks at once;
	461	* but erasing may be slow, so we make multiple calls here to avoid
	462	* tripping the MCDI RPC timeout. */
	463	while (offset < end) {
	464	rc = efx_mcdi_nvram_erase(efx, part->mcdi.nvram_type, offset,
	465	chunk);
	466	if (rc)
	467	goto out;
	468	offset += chunk;
	469	}
	470	out:
	471	return rc;
	472	}
	473
	474	static int siena_mtd_write(struct mtd_info *mtd, loff_t start,
	475	size_t len, size_t retlen, const u8 buffer)
	476	{
	477	struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
	478	struct efx_mtd *efx_mtd = mtd->priv;
	479	struct efx_nic *efx = efx_mtd->efx;
	480	loff_t offset = start;
	481	loff_t end = min_t(loff_t, start + len, mtd->size);
	482	size_t chunk;
	483	int rc = 0;
	484
	485	if (!part->mcdi.updating) {
	486	rc = efx_mcdi_nvram_update_start(efx, part->mcdi.nvram_type);
	487	if (rc)
	488	goto out;
	489	part->mcdi.updating = 1;
	490	}
	491
	492	while (offset < end) {
5a27e86b	493	chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX);
8880f4ec BH	494	rc = efx_mcdi_nvram_write(efx, part->mcdi.nvram_type, offset,
	495	buffer, chunk);
	496	if (rc)
	497	goto out;
	498	offset += chunk;
	499	buffer += chunk;
	500	}
	501	out:
	502	*retlen = offset - start;
	503	return rc;
	504	}
	505
	506	static int siena_mtd_sync(struct mtd_info *mtd)
	507	{
	508	struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
	509	struct efx_mtd *efx_mtd = mtd->priv;
	510	struct efx_nic *efx = efx_mtd->efx;
	511	int rc = 0;
	512
	513	if (part->mcdi.updating) {
	514	part->mcdi.updating = 0;
	515	rc = efx_mcdi_nvram_update_finish(efx, part->mcdi.nvram_type);
	516	}
	517
	518	return rc;
	519	}
	520
	521	static struct efx_mtd_ops siena_mtd_ops = {
	522	.read = siena_mtd_read,
	523	.erase = siena_mtd_erase,
	524	.write = siena_mtd_write,
	525	.sync = siena_mtd_sync,
	526	};
	527
	528	struct siena_nvram_type_info {
	529	int port;
	530	const char *name;
	531	};
	532
	533	static struct siena_nvram_type_info siena_nvram_types[] = {
	534	[MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" },
	535	[MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" },
	536	[MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" },
	537	[MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" },
	538	[MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" },
	539	[MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" },
	540	[MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" },
	541	[MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" },
	542	[MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" },
	543	[MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" },
	544	[MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" },
	545	[MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" },
	546	};
	547
	548	static int siena_mtd_probe_partition(struct efx_nic *efx,
	549	struct efx_mtd *efx_mtd,
	550	unsigned int part_id,
	551	unsigned int type)
	552	{
	553	struct efx_mtd_partition *part = &efx_mtd->part[part_id];
	554	struct siena_nvram_type_info *info;
	555	size_t size, erase_size;
	556	bool protected;
	557	int rc;
558
559	if (type >= ARRAY_SIZE(siena_nvram_types))
560	return -ENODEV;
561
562	info = &siena_nvram_types[type];
563
564	if (info->port != efx_port_num(efx))
565	return -ENODEV;
566
567	rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
568	if (rc)
569	return rc;
570	if (protected)
571	return -ENODEV; /* hide it */
572
573	part->mcdi.nvram_type = type;
574	part->type_name = info->name;
575
576	part->mtd.type = MTD_NORFLASH;
577	part->mtd.flags = MTD_CAP_NORFLASH;
578	part->mtd.size = size;
579	part->mtd.erasesize = erase_size;
580
581	return 0;
582	}
583
584	static int siena_mtd_get_fw_subtypes(struct efx_nic *efx,
585	struct efx_mtd *efx_mtd)
586	{
587	struct efx_mtd_partition *part;
588	uint16_t fw_subtype_list[MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN /
589	sizeof(uint16_t)];
590	int rc;
591
592	rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list);
593	if (rc)
594	return rc;
595
596	efx_for_each_partition(part, efx_mtd)
597	part->mcdi.fw_subtype = fw_subtype_list[part->mcdi.nvram_type];
598
599	return 0;
600	}
601
602	static int siena_mtd_probe(struct efx_nic *efx)
603	{
604	struct efx_mtd *efx_mtd;
605	int rc = -ENODEV;
606	u32 nvram_types;
607	unsigned int type;
608
609	ASSERT_RTNL();
610
611	rc = efx_mcdi_nvram_types(efx, &nvram_types);
612	if (rc)
613	return rc;
614
615	efx_mtd = kzalloc(sizeof(*efx_mtd) +
616	hweight32(nvram_types) * sizeof(efx_mtd->part[0]),
617	GFP_KERNEL);
618	if (!efx_mtd)
619	return -ENOMEM;
620
621	efx_mtd->name = "Siena NVRAM manager";
622
623	efx_mtd->ops = &siena_mtd_ops;
624
625	type = 0;
626	efx_mtd->n_parts = 0;
627
628	while (nvram_types != 0) {
629	if (nvram_types & 1) {
630	rc = siena_mtd_probe_partition(efx, efx_mtd,
631	efx_mtd->n_parts, type);
632	if (rc == 0)
633	efx_mtd->n_parts++;
634	else if (rc != -ENODEV)
635	goto fail;
636	}
637	type++;
638	nvram_types >>= 1;
639	}
640
641	rc = siena_mtd_get_fw_subtypes(efx, efx_mtd);
642	if (rc)
643	goto fail;
644
645	rc = efx_mtd_probe_device(efx, efx_mtd);
646	fail:
647	if (rc)
648	kfree(efx_mtd);
649	return rc;
650	}
651