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f4150724 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
906bb26c | 4 | * Copyright 2006-2009 Solarflare Communications Inc. |
f4150724 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
8880f4ec | 11 | #include <linux/bitops.h> |
f4150724 BH |
12 | #include <linux/module.h> |
13 | #include <linux/mtd/mtd.h> | |
14 | #include <linux/delay.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
76884835 | 16 | #include <linux/rtnetlink.h> |
f4150724 BH |
17 | |
18 | #define EFX_DRIVER_NAME "sfc_mtd" | |
19 | #include "net_driver.h" | |
20 | #include "spi.h" | |
ff2ef902 | 21 | #include "efx.h" |
744093c9 | 22 | #include "nic.h" |
8880f4ec BH |
23 | #include "mcdi.h" |
24 | #include "mcdi_pcol.h" | |
f4150724 BH |
25 | |
26 | #define EFX_SPI_VERIFY_BUF_LEN 16 | |
27 | ||
76884835 | 28 | struct efx_mtd_partition { |
f4150724 | 29 | struct mtd_info mtd; |
8880f4ec BH |
30 | union { |
31 | struct { | |
32 | bool updating; | |
33 | u8 nvram_type; | |
34 | u16 fw_subtype; | |
35 | } mcdi; | |
36 | size_t offset; | |
37 | }; | |
76884835 | 38 | const char *type_name; |
f4150724 BH |
39 | char name[IFNAMSIZ + 20]; |
40 | }; | |
41 | ||
76884835 BH |
42 | struct efx_mtd_ops { |
43 | int (*read)(struct mtd_info *mtd, loff_t start, size_t len, | |
44 | size_t *retlen, u8 *buffer); | |
45 | int (*erase)(struct mtd_info *mtd, loff_t start, size_t len); | |
46 | int (*write)(struct mtd_info *mtd, loff_t start, size_t len, | |
47 | size_t *retlen, const u8 *buffer); | |
48 | int (*sync)(struct mtd_info *mtd); | |
49 | }; | |
50 | ||
51 | struct efx_mtd { | |
52 | struct list_head node; | |
53 | struct efx_nic *efx; | |
54 | const struct efx_spi_device *spi; | |
55 | const char *name; | |
56 | const struct efx_mtd_ops *ops; | |
57 | size_t n_parts; | |
58 | struct efx_mtd_partition part[0]; | |
59 | }; | |
60 | ||
61 | #define efx_for_each_partition(part, efx_mtd) \ | |
62 | for ((part) = &(efx_mtd)->part[0]; \ | |
63 | (part) != &(efx_mtd)->part[(efx_mtd)->n_parts]; \ | |
64 | (part)++) | |
65 | ||
66 | #define to_efx_mtd_partition(mtd) \ | |
67 | container_of(mtd, struct efx_mtd_partition, mtd) | |
68 | ||
69 | static int falcon_mtd_probe(struct efx_nic *efx); | |
8880f4ec | 70 | static int siena_mtd_probe(struct efx_nic *efx); |
76884835 | 71 | |
f4150724 BH |
72 | /* SPI utilities */ |
73 | ||
74 | static int efx_spi_slow_wait(struct efx_mtd *efx_mtd, bool uninterruptible) | |
75 | { | |
76 | const struct efx_spi_device *spi = efx_mtd->spi; | |
76884835 | 77 | struct efx_nic *efx = efx_mtd->efx; |
f4150724 BH |
78 | u8 status; |
79 | int rc, i; | |
80 | ||
81 | /* Wait up to 4s for flash/EEPROM to finish a slow operation. */ | |
82 | for (i = 0; i < 40; i++) { | |
83 | __set_current_state(uninterruptible ? | |
84 | TASK_UNINTERRUPTIBLE : TASK_INTERRUPTIBLE); | |
85 | schedule_timeout(HZ / 10); | |
76884835 | 86 | rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL, |
f4150724 BH |
87 | &status, sizeof(status)); |
88 | if (rc) | |
89 | return rc; | |
90 | if (!(status & SPI_STATUS_NRDY)) | |
91 | return 0; | |
92 | if (signal_pending(current)) | |
93 | return -EINTR; | |
94 | } | |
95 | EFX_ERR(efx, "timed out waiting for %s\n", efx_mtd->name); | |
96 | return -ETIMEDOUT; | |
97 | } | |
98 | ||
76884835 BH |
99 | static int |
100 | efx_spi_unlock(struct efx_nic *efx, const struct efx_spi_device *spi) | |
f4150724 BH |
101 | { |
102 | const u8 unlock_mask = (SPI_STATUS_BP2 | SPI_STATUS_BP1 | | |
103 | SPI_STATUS_BP0); | |
104 | u8 status; | |
105 | int rc; | |
106 | ||
76884835 BH |
107 | rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL, |
108 | &status, sizeof(status)); | |
f4150724 BH |
109 | if (rc) |
110 | return rc; | |
111 | ||
112 | if (!(status & unlock_mask)) | |
113 | return 0; /* already unlocked */ | |
114 | ||
76884835 | 115 | rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0); |
f4150724 BH |
116 | if (rc) |
117 | return rc; | |
76884835 | 118 | rc = falcon_spi_cmd(efx, spi, SPI_SST_EWSR, -1, NULL, NULL, 0); |
f4150724 BH |
119 | if (rc) |
120 | return rc; | |
121 | ||
122 | status &= ~unlock_mask; | |
76884835 BH |
123 | rc = falcon_spi_cmd(efx, spi, SPI_WRSR, -1, &status, |
124 | NULL, sizeof(status)); | |
f4150724 BH |
125 | if (rc) |
126 | return rc; | |
76884835 | 127 | rc = falcon_spi_wait_write(efx, spi); |
f4150724 BH |
128 | if (rc) |
129 | return rc; | |
130 | ||
131 | return 0; | |
132 | } | |
133 | ||
134 | static int efx_spi_erase(struct efx_mtd *efx_mtd, loff_t start, size_t len) | |
135 | { | |
136 | const struct efx_spi_device *spi = efx_mtd->spi; | |
76884835 | 137 | struct efx_nic *efx = efx_mtd->efx; |
f4150724 BH |
138 | unsigned pos, block_len; |
139 | u8 empty[EFX_SPI_VERIFY_BUF_LEN]; | |
140 | u8 buffer[EFX_SPI_VERIFY_BUF_LEN]; | |
141 | int rc; | |
142 | ||
143 | if (len != spi->erase_size) | |
144 | return -EINVAL; | |
145 | ||
146 | if (spi->erase_command == 0) | |
147 | return -EOPNOTSUPP; | |
148 | ||
76884835 | 149 | rc = efx_spi_unlock(efx, spi); |
f4150724 BH |
150 | if (rc) |
151 | return rc; | |
76884835 | 152 | rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0); |
f4150724 BH |
153 | if (rc) |
154 | return rc; | |
76884835 BH |
155 | rc = falcon_spi_cmd(efx, spi, spi->erase_command, start, NULL, |
156 | NULL, 0); | |
f4150724 BH |
157 | if (rc) |
158 | return rc; | |
159 | rc = efx_spi_slow_wait(efx_mtd, false); | |
160 | ||
161 | /* Verify the entire region has been wiped */ | |
162 | memset(empty, 0xff, sizeof(empty)); | |
163 | for (pos = 0; pos < len; pos += block_len) { | |
164 | block_len = min(len - pos, sizeof(buffer)); | |
76884835 BH |
165 | rc = falcon_spi_read(efx, spi, start + pos, block_len, |
166 | NULL, buffer); | |
f4150724 BH |
167 | if (rc) |
168 | return rc; | |
169 | if (memcmp(empty, buffer, block_len)) | |
170 | return -EIO; | |
171 | ||
172 | /* Avoid locking up the system */ | |
173 | cond_resched(); | |
174 | if (signal_pending(current)) | |
175 | return -EINTR; | |
176 | } | |
177 | ||
178 | return rc; | |
179 | } | |
180 | ||
181 | /* MTD interface */ | |
182 | ||
76884835 BH |
183 | static int efx_mtd_erase(struct mtd_info *mtd, struct erase_info *erase) |
184 | { | |
185 | struct efx_mtd *efx_mtd = mtd->priv; | |
186 | int rc; | |
187 | ||
188 | rc = efx_mtd->ops->erase(mtd, erase->addr, erase->len); | |
189 | if (rc == 0) { | |
190 | erase->state = MTD_ERASE_DONE; | |
191 | } else { | |
192 | erase->state = MTD_ERASE_FAILED; | |
193 | erase->fail_addr = 0xffffffff; | |
194 | } | |
195 | mtd_erase_callback(erase); | |
196 | return rc; | |
197 | } | |
198 | ||
199 | static void efx_mtd_sync(struct mtd_info *mtd) | |
200 | { | |
201 | struct efx_mtd *efx_mtd = mtd->priv; | |
202 | struct efx_nic *efx = efx_mtd->efx; | |
203 | int rc; | |
204 | ||
205 | rc = efx_mtd->ops->sync(mtd); | |
206 | if (rc) | |
207 | EFX_ERR(efx, "%s sync failed (%d)\n", efx_mtd->name, rc); | |
208 | } | |
209 | ||
210 | static void efx_mtd_remove_partition(struct efx_mtd_partition *part) | |
211 | { | |
212 | int rc; | |
213 | ||
214 | for (;;) { | |
215 | rc = del_mtd_device(&part->mtd); | |
216 | if (rc != -EBUSY) | |
217 | break; | |
218 | ssleep(1); | |
219 | } | |
220 | WARN_ON(rc); | |
221 | } | |
222 | ||
223 | static void efx_mtd_remove_device(struct efx_mtd *efx_mtd) | |
224 | { | |
225 | struct efx_mtd_partition *part; | |
226 | ||
227 | efx_for_each_partition(part, efx_mtd) | |
228 | efx_mtd_remove_partition(part); | |
229 | list_del(&efx_mtd->node); | |
230 | kfree(efx_mtd); | |
231 | } | |
232 | ||
233 | static void efx_mtd_rename_device(struct efx_mtd *efx_mtd) | |
234 | { | |
235 | struct efx_mtd_partition *part; | |
236 | ||
237 | efx_for_each_partition(part, efx_mtd) | |
8880f4ec BH |
238 | if (efx_nic_rev(efx_mtd->efx) >= EFX_REV_SIENA_A0) |
239 | snprintf(part->name, sizeof(part->name), | |
240 | "%s %s:%02x", efx_mtd->efx->name, | |
241 | part->type_name, part->mcdi.fw_subtype); | |
242 | else | |
243 | snprintf(part->name, sizeof(part->name), | |
244 | "%s %s", efx_mtd->efx->name, | |
245 | part->type_name); | |
76884835 BH |
246 | } |
247 | ||
248 | static int efx_mtd_probe_device(struct efx_nic *efx, struct efx_mtd *efx_mtd) | |
249 | { | |
250 | struct efx_mtd_partition *part; | |
251 | ||
252 | efx_mtd->efx = efx; | |
253 | ||
254 | efx_mtd_rename_device(efx_mtd); | |
255 | ||
256 | efx_for_each_partition(part, efx_mtd) { | |
257 | part->mtd.writesize = 1; | |
258 | ||
259 | part->mtd.owner = THIS_MODULE; | |
260 | part->mtd.priv = efx_mtd; | |
261 | part->mtd.name = part->name; | |
262 | part->mtd.erase = efx_mtd_erase; | |
263 | part->mtd.read = efx_mtd->ops->read; | |
264 | part->mtd.write = efx_mtd->ops->write; | |
265 | part->mtd.sync = efx_mtd_sync; | |
266 | ||
267 | if (add_mtd_device(&part->mtd)) | |
268 | goto fail; | |
269 | } | |
270 | ||
271 | list_add(&efx_mtd->node, &efx->mtd_list); | |
272 | return 0; | |
273 | ||
274 | fail: | |
275 | while (part != &efx_mtd->part[0]) { | |
276 | --part; | |
277 | efx_mtd_remove_partition(part); | |
278 | } | |
279 | /* add_mtd_device() returns 1 if the MTD table is full */ | |
280 | return -ENOMEM; | |
281 | } | |
282 | ||
283 | void efx_mtd_remove(struct efx_nic *efx) | |
f4150724 | 284 | { |
76884835 BH |
285 | struct efx_mtd *efx_mtd, *next; |
286 | ||
287 | WARN_ON(efx_dev_registered(efx)); | |
288 | ||
289 | list_for_each_entry_safe(efx_mtd, next, &efx->mtd_list, node) | |
290 | efx_mtd_remove_device(efx_mtd); | |
291 | } | |
292 | ||
293 | void efx_mtd_rename(struct efx_nic *efx) | |
294 | { | |
295 | struct efx_mtd *efx_mtd; | |
296 | ||
297 | ASSERT_RTNL(); | |
298 | ||
299 | list_for_each_entry(efx_mtd, &efx->mtd_list, node) | |
300 | efx_mtd_rename_device(efx_mtd); | |
301 | } | |
302 | ||
303 | int efx_mtd_probe(struct efx_nic *efx) | |
304 | { | |
8880f4ec BH |
305 | if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) |
306 | return siena_mtd_probe(efx); | |
307 | else | |
308 | return falcon_mtd_probe(efx); | |
76884835 BH |
309 | } |
310 | ||
311 | /* Implementation of MTD operations for Falcon */ | |
312 | ||
313 | static int falcon_mtd_read(struct mtd_info *mtd, loff_t start, | |
314 | size_t len, size_t *retlen, u8 *buffer) | |
315 | { | |
316 | struct efx_mtd_partition *part = to_efx_mtd_partition(mtd); | |
f4150724 BH |
317 | struct efx_mtd *efx_mtd = mtd->priv; |
318 | const struct efx_spi_device *spi = efx_mtd->spi; | |
76884835 | 319 | struct efx_nic *efx = efx_mtd->efx; |
f4150724 BH |
320 | int rc; |
321 | ||
322 | rc = mutex_lock_interruptible(&efx->spi_lock); | |
323 | if (rc) | |
324 | return rc; | |
76884835 BH |
325 | rc = falcon_spi_read(efx, spi, part->offset + start, len, |
326 | retlen, buffer); | |
f4150724 BH |
327 | mutex_unlock(&efx->spi_lock); |
328 | return rc; | |
329 | } | |
330 | ||
76884835 | 331 | static int falcon_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len) |
f4150724 | 332 | { |
76884835 | 333 | struct efx_mtd_partition *part = to_efx_mtd_partition(mtd); |
f4150724 | 334 | struct efx_mtd *efx_mtd = mtd->priv; |
76884835 | 335 | struct efx_nic *efx = efx_mtd->efx; |
f4150724 BH |
336 | int rc; |
337 | ||
338 | rc = mutex_lock_interruptible(&efx->spi_lock); | |
339 | if (rc) | |
340 | return rc; | |
76884835 | 341 | rc = efx_spi_erase(efx_mtd, part->offset + start, len); |
f4150724 | 342 | mutex_unlock(&efx->spi_lock); |
f4150724 BH |
343 | return rc; |
344 | } | |
345 | ||
76884835 BH |
346 | static int falcon_mtd_write(struct mtd_info *mtd, loff_t start, |
347 | size_t len, size_t *retlen, const u8 *buffer) | |
f4150724 | 348 | { |
76884835 | 349 | struct efx_mtd_partition *part = to_efx_mtd_partition(mtd); |
f4150724 BH |
350 | struct efx_mtd *efx_mtd = mtd->priv; |
351 | const struct efx_spi_device *spi = efx_mtd->spi; | |
76884835 | 352 | struct efx_nic *efx = efx_mtd->efx; |
f4150724 BH |
353 | int rc; |
354 | ||
355 | rc = mutex_lock_interruptible(&efx->spi_lock); | |
356 | if (rc) | |
357 | return rc; | |
76884835 BH |
358 | rc = falcon_spi_write(efx, spi, part->offset + start, len, |
359 | retlen, buffer); | |
f4150724 BH |
360 | mutex_unlock(&efx->spi_lock); |
361 | return rc; | |
362 | } | |
363 | ||
76884835 | 364 | static int falcon_mtd_sync(struct mtd_info *mtd) |
f4150724 BH |
365 | { |
366 | struct efx_mtd *efx_mtd = mtd->priv; | |
76884835 | 367 | struct efx_nic *efx = efx_mtd->efx; |
f4150724 BH |
368 | int rc; |
369 | ||
370 | mutex_lock(&efx->spi_lock); | |
371 | rc = efx_spi_slow_wait(efx_mtd, true); | |
372 | mutex_unlock(&efx->spi_lock); | |
76884835 | 373 | return rc; |
f4150724 BH |
374 | } |
375 | ||
76884835 BH |
376 | static struct efx_mtd_ops falcon_mtd_ops = { |
377 | .read = falcon_mtd_read, | |
378 | .erase = falcon_mtd_erase, | |
379 | .write = falcon_mtd_write, | |
380 | .sync = falcon_mtd_sync, | |
381 | }; | |
f4150724 | 382 | |
76884835 | 383 | static int falcon_mtd_probe(struct efx_nic *efx) |
f4150724 BH |
384 | { |
385 | struct efx_spi_device *spi = efx->spi_flash; | |
386 | struct efx_mtd *efx_mtd; | |
76884835 BH |
387 | int rc; |
388 | ||
389 | ASSERT_RTNL(); | |
f4150724 BH |
390 | |
391 | if (!spi || spi->size <= FALCON_FLASH_BOOTCODE_START) | |
392 | return -ENODEV; | |
393 | ||
76884835 BH |
394 | efx_mtd = kzalloc(sizeof(*efx_mtd) + sizeof(efx_mtd->part[0]), |
395 | GFP_KERNEL); | |
f4150724 BH |
396 | if (!efx_mtd) |
397 | return -ENOMEM; | |
398 | ||
399 | efx_mtd->spi = spi; | |
76884835 BH |
400 | efx_mtd->name = "flash"; |
401 | efx_mtd->ops = &falcon_mtd_ops; | |
402 | ||
403 | efx_mtd->n_parts = 1; | |
404 | efx_mtd->part[0].mtd.type = MTD_NORFLASH; | |
405 | efx_mtd->part[0].mtd.flags = MTD_CAP_NORFLASH; | |
406 | efx_mtd->part[0].mtd.size = spi->size - FALCON_FLASH_BOOTCODE_START; | |
407 | efx_mtd->part[0].mtd.erasesize = spi->erase_size; | |
408 | efx_mtd->part[0].offset = FALCON_FLASH_BOOTCODE_START; | |
409 | efx_mtd->part[0].type_name = "sfc_flash_bootrom"; | |
410 | ||
411 | rc = efx_mtd_probe_device(efx, efx_mtd); | |
412 | if (rc) | |
f4150724 | 413 | kfree(efx_mtd); |
76884835 | 414 | return rc; |
f4150724 | 415 | } |
8880f4ec BH |
416 | |
417 | /* Implementation of MTD operations for Siena */ | |
418 | ||
419 | static int siena_mtd_read(struct mtd_info *mtd, loff_t start, | |
420 | size_t len, size_t *retlen, u8 *buffer) | |
421 | { | |
422 | struct efx_mtd_partition *part = to_efx_mtd_partition(mtd); | |
423 | struct efx_mtd *efx_mtd = mtd->priv; | |
424 | struct efx_nic *efx = efx_mtd->efx; | |
425 | loff_t offset = start; | |
426 | loff_t end = min_t(loff_t, start + len, mtd->size); | |
427 | size_t chunk; | |
428 | int rc = 0; | |
429 | ||
430 | while (offset < end) { | |
5a27e86b | 431 | chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX); |
8880f4ec BH |
432 | rc = efx_mcdi_nvram_read(efx, part->mcdi.nvram_type, offset, |
433 | buffer, chunk); | |
434 | if (rc) | |
435 | goto out; | |
436 | offset += chunk; | |
437 | buffer += chunk; | |
438 | } | |
439 | out: | |
440 | *retlen = offset - start; | |
441 | return rc; | |
442 | } | |
443 | ||
444 | static int siena_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len) | |
445 | { | |
446 | struct efx_mtd_partition *part = to_efx_mtd_partition(mtd); | |
447 | struct efx_mtd *efx_mtd = mtd->priv; | |
448 | struct efx_nic *efx = efx_mtd->efx; | |
449 | loff_t offset = start & ~((loff_t)(mtd->erasesize - 1)); | |
450 | loff_t end = min_t(loff_t, start + len, mtd->size); | |
451 | size_t chunk = part->mtd.erasesize; | |
452 | int rc = 0; | |
453 | ||
454 | if (!part->mcdi.updating) { | |
455 | rc = efx_mcdi_nvram_update_start(efx, part->mcdi.nvram_type); | |
456 | if (rc) | |
457 | goto out; | |
458 | part->mcdi.updating = 1; | |
459 | } | |
460 | ||
461 | /* The MCDI interface can in fact do multiple erase blocks at once; | |
462 | * but erasing may be slow, so we make multiple calls here to avoid | |
463 | * tripping the MCDI RPC timeout. */ | |
464 | while (offset < end) { | |
465 | rc = efx_mcdi_nvram_erase(efx, part->mcdi.nvram_type, offset, | |
466 | chunk); | |
467 | if (rc) | |
468 | goto out; | |
469 | offset += chunk; | |
470 | } | |
471 | out: | |
472 | return rc; | |
473 | } | |
474 | ||
475 | static int siena_mtd_write(struct mtd_info *mtd, loff_t start, | |
476 | size_t len, size_t *retlen, const u8 *buffer) | |
477 | { | |
478 | struct efx_mtd_partition *part = to_efx_mtd_partition(mtd); | |
479 | struct efx_mtd *efx_mtd = mtd->priv; | |
480 | struct efx_nic *efx = efx_mtd->efx; | |
481 | loff_t offset = start; | |
482 | loff_t end = min_t(loff_t, start + len, mtd->size); | |
483 | size_t chunk; | |
484 | int rc = 0; | |
485 | ||
486 | if (!part->mcdi.updating) { | |
487 | rc = efx_mcdi_nvram_update_start(efx, part->mcdi.nvram_type); | |
488 | if (rc) | |
489 | goto out; | |
490 | part->mcdi.updating = 1; | |
491 | } | |
492 | ||
493 | while (offset < end) { | |
5a27e86b | 494 | chunk = min_t(size_t, end - offset, EFX_MCDI_NVRAM_LEN_MAX); |
8880f4ec BH |
495 | rc = efx_mcdi_nvram_write(efx, part->mcdi.nvram_type, offset, |
496 | buffer, chunk); | |
497 | if (rc) | |
498 | goto out; | |
499 | offset += chunk; | |
500 | buffer += chunk; | |
501 | } | |
502 | out: | |
503 | *retlen = offset - start; | |
504 | return rc; | |
505 | } | |
506 | ||
507 | static int siena_mtd_sync(struct mtd_info *mtd) | |
508 | { | |
509 | struct efx_mtd_partition *part = to_efx_mtd_partition(mtd); | |
510 | struct efx_mtd *efx_mtd = mtd->priv; | |
511 | struct efx_nic *efx = efx_mtd->efx; | |
512 | int rc = 0; | |
513 | ||
514 | if (part->mcdi.updating) { | |
515 | part->mcdi.updating = 0; | |
516 | rc = efx_mcdi_nvram_update_finish(efx, part->mcdi.nvram_type); | |
517 | } | |
518 | ||
519 | return rc; | |
520 | } | |
521 | ||
522 | static struct efx_mtd_ops siena_mtd_ops = { | |
523 | .read = siena_mtd_read, | |
524 | .erase = siena_mtd_erase, | |
525 | .write = siena_mtd_write, | |
526 | .sync = siena_mtd_sync, | |
527 | }; | |
528 | ||
529 | struct siena_nvram_type_info { | |
530 | int port; | |
531 | const char *name; | |
532 | }; | |
533 | ||
534 | static struct siena_nvram_type_info siena_nvram_types[] = { | |
535 | [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" }, | |
536 | [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" }, | |
537 | [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" }, | |
538 | [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" }, | |
539 | [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" }, | |
540 | [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" }, | |
541 | [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" }, | |
542 | [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" }, | |
543 | [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" }, | |
544 | [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" }, | |
545 | [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" }, | |
546 | [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" }, | |
547 | }; | |
548 | ||
549 | static int siena_mtd_probe_partition(struct efx_nic *efx, | |
550 | struct efx_mtd *efx_mtd, | |
551 | unsigned int part_id, | |
552 | unsigned int type) | |
553 | { | |
554 | struct efx_mtd_partition *part = &efx_mtd->part[part_id]; | |
555 | struct siena_nvram_type_info *info; | |
556 | size_t size, erase_size; | |
557 | bool protected; | |
558 | int rc; | |
559 | ||
560 | if (type >= ARRAY_SIZE(siena_nvram_types)) | |
561 | return -ENODEV; | |
562 | ||
563 | info = &siena_nvram_types[type]; | |
564 | ||
565 | if (info->port != efx_port_num(efx)) | |
566 | return -ENODEV; | |
567 | ||
568 | rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); | |
569 | if (rc) | |
570 | return rc; | |
571 | if (protected) | |
572 | return -ENODEV; /* hide it */ | |
573 | ||
574 | part->mcdi.nvram_type = type; | |
575 | part->type_name = info->name; | |
576 | ||
577 | part->mtd.type = MTD_NORFLASH; | |
578 | part->mtd.flags = MTD_CAP_NORFLASH; | |
579 | part->mtd.size = size; | |
580 | part->mtd.erasesize = erase_size; | |
581 | ||
582 | return 0; | |
583 | } | |
584 | ||
585 | static int siena_mtd_get_fw_subtypes(struct efx_nic *efx, | |
586 | struct efx_mtd *efx_mtd) | |
587 | { | |
588 | struct efx_mtd_partition *part; | |
589 | uint16_t fw_subtype_list[MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN / | |
590 | sizeof(uint16_t)]; | |
591 | int rc; | |
592 | ||
593 | rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list); | |
594 | if (rc) | |
595 | return rc; | |
596 | ||
597 | efx_for_each_partition(part, efx_mtd) | |
598 | part->mcdi.fw_subtype = fw_subtype_list[part->mcdi.nvram_type]; | |
599 | ||
600 | return 0; | |
601 | } | |
602 | ||
603 | static int siena_mtd_probe(struct efx_nic *efx) | |
604 | { | |
605 | struct efx_mtd *efx_mtd; | |
606 | int rc = -ENODEV; | |
607 | u32 nvram_types; | |
608 | unsigned int type; | |
609 | ||
610 | ASSERT_RTNL(); | |
611 | ||
612 | rc = efx_mcdi_nvram_types(efx, &nvram_types); | |
613 | if (rc) | |
614 | return rc; | |
615 | ||
616 | efx_mtd = kzalloc(sizeof(*efx_mtd) + | |
617 | hweight32(nvram_types) * sizeof(efx_mtd->part[0]), | |
618 | GFP_KERNEL); | |
619 | if (!efx_mtd) | |
620 | return -ENOMEM; | |
621 | ||
622 | efx_mtd->name = "Siena NVRAM manager"; | |
623 | ||
624 | efx_mtd->ops = &siena_mtd_ops; | |
625 | ||
626 | type = 0; | |
627 | efx_mtd->n_parts = 0; | |
628 | ||
629 | while (nvram_types != 0) { | |
630 | if (nvram_types & 1) { | |
631 | rc = siena_mtd_probe_partition(efx, efx_mtd, | |
632 | efx_mtd->n_parts, type); | |
633 | if (rc == 0) | |
634 | efx_mtd->n_parts++; | |
635 | else if (rc != -ENODEV) | |
636 | goto fail; | |
637 | } | |
638 | type++; | |
639 | nvram_types >>= 1; | |
640 | } | |
641 | ||
642 | rc = siena_mtd_get_fw_subtypes(efx, efx_mtd); | |
643 | if (rc) | |
644 | goto fail; | |
645 | ||
646 | rc = efx_mtd_probe_device(efx, efx_mtd); | |
647 | fail: | |
648 | if (rc) | |
649 | kfree(efx_mtd); | |
650 | return rc; | |
651 | } | |
652 |