[net-next-2.6.git] / drivers / net / sfc / falcon_xmac.c

/****************************************************************************
 * Driver for Solarflare Solarstorm network controllers and boards
 * Copyright 2005-2006 Fen Systems Ltd.
 * Copyright 2006-2008 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */

#include <linux/delay.h>
#include "net_driver.h"
#include "efx.h"
#include "falcon.h"
#include "regs.h"
#include "io.h"
#include "mac.h"
#include "mdio_10g.h"
#include "phy.h"
#include "workarounds.h"

/**************************************************************************
 *
 * MAC operations
 *
 *************************************************************************/

/* Configure the XAUI driver that is an output from Falcon */
static void falcon_setup_xaui(struct efx_nic *efx)
{
	efx_oword_t sdctl, txdrv;

	/* Move the XAUI into low power, unless there is no PHY, in
	 * which case the XAUI will have to drive a cable. */
	if (efx->phy_type == PHY_TYPE_NONE)
		return;

	efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
	efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);

	EFX_POPULATE_OWORD_8(txdrv,
			     FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
			     FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,
			     FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,
			     FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,
			     FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,
			     FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
			     FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
			     FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
	efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
}

int falcon_reset_xaui(struct efx_nic *efx)
{
	struct falcon_nic_data *nic_data = efx->nic_data;
	efx_oword_t reg;
	int count;

	/* Don't fetch MAC statistics over an XMAC reset */
	WARN_ON(nic_data->stats_disable_count == 0);

	/* Start reset sequence */
	EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
	efx_writeo(efx, &reg, FR_AB_XX_PWR_RST);

	/* Wait up to 10 ms for completion, then reinitialise */
	for (count = 0; count < 1000; count++) {
		efx_reado(efx, &reg, FR_AB_XX_PWR_RST);
		if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
		    EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
			falcon_setup_xaui(efx);
			return 0;
		}
		udelay(10);
	}
	EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n");
	return -ETIMEDOUT;
}

static void falcon_mask_status_intr(struct efx_nic *efx, bool enable)
{
	efx_oword_t reg;

	if ((efx_nic_rev(efx) != EFX_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx))
		return;

	/* We expect xgmii faults if the wireside link is up */
	if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up)
		return;

	/* We can only use this interrupt to signal the negative edge of
	 * xaui_align [we have to poll the positive edge]. */
	if (efx->xmac_poll_required)
		return;

	/* Flush the ISR */
	if (enable)
		efx_reado(efx, &reg, FR_AB_XM_MGT_INT_MSK);

	EFX_POPULATE_OWORD_2(reg,
			     FRF_AB_XM_MSK_RMTFLT, !enable,
			     FRF_AB_XM_MSK_LCLFLT, !enable);
	efx_writeo(efx, &reg, FR_AB_XM_MGT_INT_MASK);
}

/* Get status of XAUI link */
static bool falcon_xaui_link_ok(struct efx_nic *efx)
{
	efx_oword_t reg;
	bool align_done, link_ok = false;
	int sync_status;

	if (LOOPBACK_INTERNAL(efx))
		return true;

	/* Read link status */
	efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);

	align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
	sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
	if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))
		link_ok = true;

	/* Clear link status ready for next read */
	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
	efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);

	/* If the link is up, then check the phy side of the xaui link */
	if (efx->link_state.up && link_ok)
		if (efx->mdio.mmds & (1 << MDIO_MMD_PHYXS))
			link_ok = efx_mdio_phyxgxs_lane_sync(efx);

	return link_ok;
}

void falcon_reconfigure_xmac_core(struct efx_nic *efx)
{
	unsigned int max_frame_len;
	efx_oword_t reg;
	bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);
	bool tx_fc = !!(efx->link_state.fc & EFX_FC_TX);

	/* Configure MAC  - cut-thru mode is hard wired on */
	EFX_POPULATE_OWORD_3(reg,
			     FRF_AB_XM_RX_JUMBO_MODE, 1,
			     FRF_AB_XM_TX_STAT_EN, 1,
			     FRF_AB_XM_RX_STAT_EN, 1);
	efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);

	/* Configure TX */
	EFX_POPULATE_OWORD_6(reg,
			     FRF_AB_XM_TXEN, 1,
			     FRF_AB_XM_TX_PRMBL, 1,
			     FRF_AB_XM_AUTO_PAD, 1,
			     FRF_AB_XM_TXCRC, 1,
			     FRF_AB_XM_FCNTL, tx_fc,
			     FRF_AB_XM_IPG, 0x3);
	efx_writeo(efx, &reg, FR_AB_XM_TX_CFG);

	/* Configure RX */
	EFX_POPULATE_OWORD_5(reg,
			     FRF_AB_XM_RXEN, 1,
			     FRF_AB_XM_AUTO_DEPAD, 0,
			     FRF_AB_XM_ACPT_ALL_MCAST, 1,
			     FRF_AB_XM_ACPT_ALL_UCAST, efx->promiscuous,
			     FRF_AB_XM_PASS_CRC_ERR, 1);
	efx_writeo(efx, &reg, FR_AB_XM_RX_CFG);

	/* Set frame length */
	max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
	EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
	efx_writeo(efx, &reg, FR_AB_XM_RX_PARAM);
	EFX_POPULATE_OWORD_2(reg,
			     FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
			     FRF_AB_XM_TX_JUMBO_MODE, 1);
	efx_writeo(efx, &reg, FR_AB_XM_TX_PARAM);

	EFX_POPULATE_OWORD_2(reg,
			     FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
			     FRF_AB_XM_DIS_FCNTL, !rx_fc);
	efx_writeo(efx, &reg, FR_AB_XM_FC);

	/* Set MAC address */
	memcpy(&reg, &efx->net_dev->dev_addr[0], 4);
	efx_writeo(efx, &reg, FR_AB_XM_ADR_LO);
	memcpy(&reg, &efx->net_dev->dev_addr[4], 2);
	efx_writeo(efx, &reg, FR_AB_XM_ADR_HI);
}

static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
{
	efx_oword_t reg;
	bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
	bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
	bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);

	/* XGXS block is flaky and will need to be reset if moving
	 * into our out of XGMII, XGXS or XAUI loopbacks. */
	if (EFX_WORKAROUND_5147(efx)) {
		bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
		bool reset_xgxs;

		efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
		old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
		old_xgmii_loopback =
			EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);

		efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
		old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);

		/* The PHY driver may have turned XAUI off */
		reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
			      (xaui_loopback != old_xaui_loopback) ||
			      (xgmii_loopback != old_xgmii_loopback));

		if (reset_xgxs)
			falcon_reset_xaui(efx);
	}

	efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
			    (xgxs_loopback || xaui_loopback) ?
			    FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
	efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);

	efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
	efx_writeo(efx, &reg, FR_AB_XX_SD_CTL);
}


/* Try to bring up the Falcon side of the Falcon-Phy XAUI link */
static bool falcon_check_xaui_link_up(struct efx_nic *efx, int tries)
{
	bool mac_up = falcon_xaui_link_ok(efx);

	if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS ||
	    efx_phy_mode_disabled(efx->phy_mode))
		/* XAUI link is expected to be down */
		return mac_up;

	falcon_stop_nic_stats(efx);

	while (!mac_up && tries) {
		EFX_LOG(efx, "bashing xaui\n");
		falcon_reset_xaui(efx);
		udelay(200);

		mac_up = falcon_xaui_link_ok(efx);
		--tries;
	}

	falcon_start_nic_stats(efx);

	return mac_up;
}

static bool falcon_xmac_check_fault(struct efx_nic *efx)
{
	return !falcon_check_xaui_link_up(efx, 5);
}

static int falcon_reconfigure_xmac(struct efx_nic *efx)
{
	falcon_mask_status_intr(efx, false);

	falcon_reconfigure_xgxs_core(efx);
	falcon_reconfigure_xmac_core(efx);

	falcon_reconfigure_mac_wrapper(efx);

	efx->xmac_poll_required = !falcon_check_xaui_link_up(efx, 5);
	falcon_mask_status_intr(efx, true);

	return 0;
}

static void falcon_update_stats_xmac(struct efx_nic *efx)
{
	struct efx_mac_stats *mac_stats = &efx->mac_stats;

	/* Update MAC stats from DMAed values */
	FALCON_STAT(efx, XgRxOctets, rx_bytes);
	FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
	FALCON_STAT(efx, XgRxPkts, rx_packets);
	FALCON_STAT(efx, XgRxPktsOK, rx_good);
	FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
	FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
	FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
	FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
	FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
	FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
	FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
	FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
	FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
	FALCON_STAT(efx, XgRxAlignError, rx_align_error);
	FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
	FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
	FALCON_STAT(efx, XgRxControlPkts, rx_control);
	FALCON_STAT(efx, XgRxPausePkts, rx_pause);
	FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
	FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
	FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
	FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
	FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
	FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
	FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
	FALCON_STAT(efx, XgRxLengthError, rx_length_error);
	FALCON_STAT(efx, XgTxPkts, tx_packets);
	FALCON_STAT(efx, XgTxOctets, tx_bytes);
	FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
	FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
	FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
	FALCON_STAT(efx, XgTxControlPkts, tx_control);
	FALCON_STAT(efx, XgTxPausePkts, tx_pause);
	FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
	FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
	FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
	FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
	FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
	FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
	FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
	FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
	FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
	FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
	FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
	FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);

	/* Update derived statistics */
	mac_stats->tx_good_bytes =
		(mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
		 mac_stats->tx_control * 64);
	mac_stats->rx_bad_bytes =
		(mac_stats->rx_bytes - mac_stats->rx_good_bytes -
		 mac_stats->rx_control * 64);
}

void falcon_poll_xmac(struct efx_nic *efx)
{
	if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up ||
	    !efx->xmac_poll_required)
		return;

	falcon_mask_status_intr(efx, false);
	efx->xmac_poll_required = !falcon_check_xaui_link_up(efx, 1);
	falcon_mask_status_intr(efx, true);
}

struct efx_mac_operations falcon_xmac_operations = {
	.reconfigure	= falcon_reconfigure_xmac,
	.update_stats	= falcon_update_stats_xmac,
	.check_fault	= falcon_xmac_check_fault,
};
Commit	Line	Data
8ceee660 BH	1	/****************************************************************************
	2	* Driver for Solarflare Solarstorm network controllers and boards
	3	* Copyright 2005-2006 Fen Systems Ltd.
	4	* Copyright 2006-2008 Solarflare Communications Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published
	8	* by the Free Software Foundation, incorporated herein by reference.
	9	*/
	10
	11	#include <linux/delay.h>
	12	#include "net_driver.h"
	13	#include "efx.h"
	14	#include "falcon.h"
3e6c4538	15	#include "regs.h"
12d00cad	16	#include "io.h"
8ceee660	17	#include "mac.h"
8ceee660 BH	18	#include "mdio_10g.h"
8ceee660 BH	19	#include "phy.h"
8ceee660 BH	20	#include "workarounds.h"
8ceee660 BH	21
8ceee660 BH	22	/**************************************************************************
	23	*
	24	* MAC operations
	25	*
	26	*************************************************************************/
8ceee660 BH	27
	28	/* Configure the XAUI driver that is an output from Falcon */
	29	static void falcon_setup_xaui(struct efx_nic *efx)
	30	{
c1e5fcc9	31	efx_oword_t sdctl, txdrv;
8ceee660 BH	32
	33	/* Move the XAUI into low power, unless there is no PHY, in
	34	* which case the XAUI will have to drive a cable. */
	35	if (efx->phy_type == PHY_TYPE_NONE)
	36	return;
	37
12d00cad	38	efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
3e6c4538 BH	39	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
	40	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
	41	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
	42	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
	43	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
	44	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
	45	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
	46	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
12d00cad	47	efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);
c1e5fcc9 BH	48
c1e5fcc9 BH	49	EFX_POPULATE_OWORD_8(txdrv,
3e6c4538 BH	50	FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
	51	FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,
	52	FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,
	53	FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,
	54	FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,
	55	FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
	56	FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
	57	FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
12d00cad	58	efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
8ceee660 BH	59	}
8ceee660 BH	60
ef08af03	61	int falcon_reset_xaui(struct efx_nic *efx)
8ceee660	62	{
55edc6e6	63	struct falcon_nic_data *nic_data = efx->nic_data;
c1e5fcc9	64	efx_oword_t reg;
8ceee660 BH	65	int count;
8ceee660 BH	66
55edc6e6 BH	67	/* Don't fetch MAC statistics over an XMAC reset */
	68	WARN_ON(nic_data->stats_disable_count == 0);
	69
d4ec09ac	70	/* Start reset sequence */
80cb9a0f	71	EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
12d00cad	72	efx_writeo(efx, &reg, FR_AB_XX_PWR_RST);
8ceee660	73
d4ec09ac BH	74	/* Wait up to 10 ms for completion, then reinitialise */
d4ec09ac BH	75	for (count = 0; count < 1000; count++) {
12d00cad	76	efx_reado(efx, &reg, FR_AB_XX_PWR_RST);
3e6c4538 BH	77	if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
3e6c4538 BH	78	EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
8ceee660 BH	79	falcon_setup_xaui(efx);
	80	return 0;
	81	}
	82	udelay(10);
	83	}
	84	EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n");
	85	return -ETIMEDOUT;
	86	}
	87
177dfcd8	88	static void falcon_mask_status_intr(struct efx_nic *efx, bool enable)
8ceee660	89	{
c1e5fcc9	90	efx_oword_t reg;
8ceee660	91
daeda630	92	if ((efx_nic_rev(efx) != EFX_REV_FALCON_B0) \|\| LOOPBACK_INTERNAL(efx))
177dfcd8	93	return;
8ceee660	94
177dfcd8	95	/* We expect xgmii faults if the wireside link is up */
eb50c0d6	96	if (!EFX_WORKAROUND_5147(efx) \|\| !efx->link_state.up)
177dfcd8	97	return;
8ceee660	98
177dfcd8 BH	99	/* We can only use this interrupt to signal the negative edge of
177dfcd8 BH	100	* xaui_align [we have to poll the positive edge]. */
9007b9fa	101	if (efx->xmac_poll_required)
8ceee660 BH	102	return;
	103
	104	/* Flush the ISR */
	105	if (enable)
12d00cad	106	efx_reado(efx, &reg, FR_AB_XM_MGT_INT_MSK);
8ceee660	107
c1e5fcc9	108	EFX_POPULATE_OWORD_2(reg,
3e6c4538 BH	109	FRF_AB_XM_MSK_RMTFLT, !enable,
3e6c4538 BH	110	FRF_AB_XM_MSK_LCLFLT, !enable);
12d00cad	111	efx_writeo(efx, &reg, FR_AB_XM_MGT_INT_MASK);
8ceee660 BH	112	}
8ceee660 BH	113
177dfcd8	114	/* Get status of XAUI link */
d3245b28	115	static bool falcon_xaui_link_ok(struct efx_nic *efx)
8ceee660	116	{
c1e5fcc9	117	efx_oword_t reg;
dc8cfa55 BH	118	bool align_done, link_ok = false;
dc8cfa55 BH	119	int sync_status;
8ceee660	120
3273c2e8	121	if (LOOPBACK_INTERNAL(efx))
dc8cfa55	122	return true;
3273c2e8	123
8ceee660	124	/* Read link status */
12d00cad	125	efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
8ceee660	126
3e6c4538 BH	127	align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
	128	sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
	129	if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))
dc8cfa55	130	link_ok = true;
8ceee660 BH	131
8ceee660 BH	132	/* Clear link status ready for next read */
3e6c4538 BH	133	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
	134	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
	135	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
12d00cad	136	efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
8ceee660	137
177dfcd8	138	/* If the link is up, then check the phy side of the xaui link */
eb50c0d6	139	if (efx->link_state.up && link_ok)
c1c4f453	140	if (efx->mdio.mmds & (1 << MDIO_MMD_PHYXS))
68e7f45e	141	link_ok = efx_mdio_phyxgxs_lane_sync(efx);
8ceee660 BH	142
	143	return link_ok;
	144	}
	145
d3245b28	146	void falcon_reconfigure_xmac_core(struct efx_nic *efx)
8ceee660 BH	147	{
8ceee660 BH	148	unsigned int max_frame_len;
c1e5fcc9	149	efx_oword_t reg;
eb50c0d6	150	bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);
4b0d29dc	151	bool tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
8ceee660 BH	152
8ceee660 BH	153	/* Configure MAC - cut-thru mode is hard wired on */
80cb9a0f	154	EFX_POPULATE_OWORD_3(reg,
3e6c4538 BH	155	FRF_AB_XM_RX_JUMBO_MODE, 1,
	156	FRF_AB_XM_TX_STAT_EN, 1,
	157	FRF_AB_XM_RX_STAT_EN, 1);
12d00cad	158	efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
8ceee660 BH	159
8ceee660 BH	160	/* Configure TX */
80cb9a0f	161	EFX_POPULATE_OWORD_6(reg,
3e6c4538 BH	162	FRF_AB_XM_TXEN, 1,
	163	FRF_AB_XM_TX_PRMBL, 1,
	164	FRF_AB_XM_AUTO_PAD, 1,
	165	FRF_AB_XM_TXCRC, 1,
4b0d29dc	166	FRF_AB_XM_FCNTL, tx_fc,
3e6c4538	167	FRF_AB_XM_IPG, 0x3);
12d00cad	168	efx_writeo(efx, &reg, FR_AB_XM_TX_CFG);
8ceee660 BH	169
8ceee660 BH	170	/* Configure RX */
80cb9a0f	171	EFX_POPULATE_OWORD_5(reg,
3e6c4538 BH	172	FRF_AB_XM_RXEN, 1,
	173	FRF_AB_XM_AUTO_DEPAD, 0,
	174	FRF_AB_XM_ACPT_ALL_MCAST, 1,
	175	FRF_AB_XM_ACPT_ALL_UCAST, efx->promiscuous,
	176	FRF_AB_XM_PASS_CRC_ERR, 1);
12d00cad	177	efx_writeo(efx, &reg, FR_AB_XM_RX_CFG);
8ceee660 BH	178
	179	/* Set frame length */
	180	max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
80cb9a0f	181	EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
12d00cad	182	efx_writeo(efx, &reg, FR_AB_XM_RX_PARAM);
80cb9a0f	183	EFX_POPULATE_OWORD_2(reg,
3e6c4538 BH	184	FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
3e6c4538 BH	185	FRF_AB_XM_TX_JUMBO_MODE, 1);
12d00cad	186	efx_writeo(efx, &reg, FR_AB_XM_TX_PARAM);
8ceee660	187
80cb9a0f	188	EFX_POPULATE_OWORD_2(reg,
3e6c4538 BH	189	FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
3e6c4538 BH	190	FRF_AB_XM_DIS_FCNTL, !rx_fc);
12d00cad	191	efx_writeo(efx, &reg, FR_AB_XM_FC);
8ceee660 BH	192
8ceee660 BH	193	/* Set MAC address */
3e6c4538	194	memcpy(&reg, &efx->net_dev->dev_addr[0], 4);
12d00cad	195	efx_writeo(efx, &reg, FR_AB_XM_ADR_LO);
3e6c4538	196	memcpy(&reg, &efx->net_dev->dev_addr[4], 2);
12d00cad	197	efx_writeo(efx, &reg, FR_AB_XM_ADR_HI);
8ceee660 BH	198	}
8ceee660 BH	199
3273c2e8 BH	200	static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
3273c2e8 BH	201	{
c1e5fcc9	202	efx_oword_t reg;
dc8cfa55 BH	203	bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
	204	bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
	205	bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
3273c2e8 BH	206
	207	/* XGXS block is flaky and will need to be reset if moving
	208	* into our out of XGMII, XGXS or XAUI loopbacks. */
	209	if (EFX_WORKAROUND_5147(efx)) {
dc8cfa55 BH	210	bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
dc8cfa55 BH	211	bool reset_xgxs;
3273c2e8	212
12d00cad	213	efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
3e6c4538 BH	214	old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
	215	old_xgmii_loopback =
	216	EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);
3273c2e8	217
12d00cad	218	efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
3e6c4538	219	old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);
3273c2e8 BH	220
	221	/* The PHY driver may have turned XAUI off */
	222	reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) \|\|
	223	(xaui_loopback != old_xaui_loopback) \|\|
	224	(xgmii_loopback != old_xgmii_loopback));
8c8661e4 BH	225
	226	if (reset_xgxs)
	227	falcon_reset_xaui(efx);
3273c2e8 BH	228	}
3273c2e8 BH	229
12d00cad	230	efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
3e6c4538	231	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
3273c2e8	232	(xgxs_loopback \|\| xaui_loopback) ?
3e6c4538 BH	233	FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
	234	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
	235	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
12d00cad	236	efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
3e6c4538	237
12d00cad	238	efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
3e6c4538 BH	239	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
	240	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
	241	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
	242	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
12d00cad	243	efx_writeo(efx, &reg, FR_AB_XX_SD_CTL);
3273c2e8 BH	244	}
	245
	246
9007b9fa BH	247	/* Try to bring up the Falcon side of the Falcon-Phy XAUI link */
9007b9fa BH	248	static bool falcon_check_xaui_link_up(struct efx_nic *efx, int tries)
8ceee660	249	{
9007b9fa	250	bool mac_up = falcon_xaui_link_ok(efx);
8ceee660	251
e58f69f4	252	if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS \|\|
f8b87c17	253	efx_phy_mode_disabled(efx->phy_mode))
177dfcd8	254	/* XAUI link is expected to be down */
9007b9fa	255	return mac_up;
8ceee660	256
55edc6e6 BH	257	falcon_stop_nic_stats(efx);
55edc6e6 BH	258
9007b9fa	259	while (!mac_up && tries) {
177dfcd8	260	EFX_LOG(efx, "bashing xaui\n");
91ad757c	261	falcon_reset_xaui(efx);
8ceee660	262	udelay(200);
8ceee660	263
9007b9fa	264	mac_up = falcon_xaui_link_ok(efx);
177dfcd8 BH	265	--tries;
177dfcd8 BH	266	}
55edc6e6 BH	267
55edc6e6 BH	268	falcon_start_nic_stats(efx);
9007b9fa BH	269
	270	return mac_up;
	271	}
	272
	273	static bool falcon_xmac_check_fault(struct efx_nic *efx)
	274	{
	275	return !falcon_check_xaui_link_up(efx, 5);
8ceee660 BH	276	}
8ceee660 BH	277
d3245b28	278	static int falcon_reconfigure_xmac(struct efx_nic *efx)
8ceee660	279	{
dc8cfa55	280	falcon_mask_status_intr(efx, false);
8ceee660	281
3273c2e8	282	falcon_reconfigure_xgxs_core(efx);
8ceee660	283	falcon_reconfigure_xmac_core(efx);
3273c2e8	284
8ceee660 BH	285	falcon_reconfigure_mac_wrapper(efx);
8ceee660 BH	286
9007b9fa	287	efx->xmac_poll_required = !falcon_check_xaui_link_up(efx, 5);
177dfcd8	288	falcon_mask_status_intr(efx, true);
d3245b28 BH	289
d3245b28 BH	290	return 0;
8ceee660 BH	291	}
8ceee660 BH	292
177dfcd8	293	static void falcon_update_stats_xmac(struct efx_nic *efx)
8ceee660 BH	294	{
8ceee660 BH	295	struct efx_mac_stats *mac_stats = &efx->mac_stats;
8ceee660 BH	296
	297	/* Update MAC stats from DMAed values */
	298	FALCON_STAT(efx, XgRxOctets, rx_bytes);
	299	FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
	300	FALCON_STAT(efx, XgRxPkts, rx_packets);
	301	FALCON_STAT(efx, XgRxPktsOK, rx_good);
	302	FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
	303	FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
	304	FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
	305	FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
	306	FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
	307	FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
	308	FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
	309	FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
	310	FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
	311	FALCON_STAT(efx, XgRxAlignError, rx_align_error);
	312	FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
	313	FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
	314	FALCON_STAT(efx, XgRxControlPkts, rx_control);
	315	FALCON_STAT(efx, XgRxPausePkts, rx_pause);
	316	FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
	317	FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
	318	FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
	319	FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
	320	FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
	321	FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
	322	FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
	323	FALCON_STAT(efx, XgRxLengthError, rx_length_error);
	324	FALCON_STAT(efx, XgTxPkts, tx_packets);
	325	FALCON_STAT(efx, XgTxOctets, tx_bytes);
	326	FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
	327	FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
	328	FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
	329	FALCON_STAT(efx, XgTxControlPkts, tx_control);
	330	FALCON_STAT(efx, XgTxPausePkts, tx_pause);
	331	FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
	332	FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
	333	FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
	334	FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
	335	FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
	336	FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
	337	FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
	338	FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
	339	FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
	340	FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
	341	FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
	342	FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
	343
	344	/* Update derived statistics */
	345	mac_stats->tx_good_bytes =
c264361d BH	346	(mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
c264361d BH	347	mac_stats->tx_control * 64);
8ceee660	348	mac_stats->rx_bad_bytes =
c264361d BH	349	(mac_stats->rx_bytes - mac_stats->rx_good_bytes -
c264361d BH	350	mac_stats->rx_control * 64);
8ceee660 BH	351	}
8ceee660 BH	352
9007b9fa	353	void falcon_poll_xmac(struct efx_nic *efx)
766ca0fa	354	{
9007b9fa BH	355	if (!EFX_WORKAROUND_5147(efx) \|\| !efx->link_state.up \|\|
9007b9fa BH	356	!efx->xmac_poll_required)
766ca0fa	357	return;
3273c2e8	358
dc8cfa55	359	falcon_mask_status_intr(efx, false);
9007b9fa	360	efx->xmac_poll_required = !falcon_check_xaui_link_up(efx, 1);
766ca0fa	361	falcon_mask_status_intr(efx, true);
8ceee660 BH	362	}
8ceee660 BH	363
177dfcd8 BH	364	struct efx_mac_operations falcon_xmac_operations = {
	365	.reconfigure = falcon_reconfigure_xmac,
	366	.update_stats = falcon_update_stats_xmac,
9007b9fa	367	.check_fault = falcon_xmac_check_fault,
177dfcd8	368	};