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1da177e4 LT |
1 | /************************************************************************ |
2 | * s2io.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC | |
3 | * Copyright(c) 2002-2005 Neterion Inc. | |
4 | ||
5 | * This software may be used and distributed according to the terms of | |
6 | * the GNU General Public License (GPL), incorporated herein by reference. | |
7 | * Drivers based on or derived from this code fall under the GPL and must | |
8 | * retain the authorship, copyright and license notice. This file is not | |
9 | * a complete program and may only be used when the entire operating | |
10 | * system is licensed under the GPL. | |
11 | * See the file COPYING in this distribution for more information. | |
12 | ************************************************************************/ | |
13 | #ifndef _S2IO_H | |
14 | #define _S2IO_H | |
15 | ||
fe113638 K |
16 | /* Enable 2 buffer mode by default for SGI system */ |
17 | #ifdef CONFIG_IA64_SGI_SN2 | |
18 | #define CONFIG_2BUFF_MODE | |
19 | #endif | |
20 | ||
1da177e4 LT |
21 | #define TBD 0 |
22 | #define BIT(loc) (0x8000000000000000ULL >> (loc)) | |
23 | #define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz)) | |
24 | #define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff) | |
25 | ||
26 | #ifndef BOOL | |
27 | #define BOOL int | |
28 | #endif | |
29 | ||
30 | #ifndef TRUE | |
31 | #define TRUE 1 | |
32 | #define FALSE 0 | |
33 | #endif | |
34 | ||
35 | #undef SUCCESS | |
36 | #define SUCCESS 0 | |
37 | #define FAILURE -1 | |
38 | ||
20346722 K |
39 | /* Maximum time to flicker LED when asked to identify NIC using ethtool */ |
40 | #define MAX_FLICKER_TIME 60000 /* 60 Secs */ | |
41 | ||
1da177e4 LT |
42 | /* Maximum outstanding splits to be configured into xena. */ |
43 | typedef enum xena_max_outstanding_splits { | |
44 | XENA_ONE_SPLIT_TRANSACTION = 0, | |
45 | XENA_TWO_SPLIT_TRANSACTION = 1, | |
46 | XENA_THREE_SPLIT_TRANSACTION = 2, | |
47 | XENA_FOUR_SPLIT_TRANSACTION = 3, | |
48 | XENA_EIGHT_SPLIT_TRANSACTION = 4, | |
49 | XENA_TWELVE_SPLIT_TRANSACTION = 5, | |
50 | XENA_SIXTEEN_SPLIT_TRANSACTION = 6, | |
51 | XENA_THIRTYTWO_SPLIT_TRANSACTION = 7 | |
52 | } xena_max_outstanding_splits; | |
53 | #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4) | |
54 | ||
55 | /* OS concerned variables and constants */ | |
20346722 K |
56 | #define WATCH_DOG_TIMEOUT 15*HZ |
57 | #define EFILL 0x1234 | |
58 | #define ALIGN_SIZE 127 | |
59 | #define PCIX_COMMAND_REGISTER 0x62 | |
1da177e4 LT |
60 | |
61 | /* | |
62 | * Debug related variables. | |
63 | */ | |
64 | /* different debug levels. */ | |
65 | #define ERR_DBG 0 | |
66 | #define INIT_DBG 1 | |
67 | #define INFO_DBG 2 | |
68 | #define TX_DBG 3 | |
69 | #define INTR_DBG 4 | |
70 | ||
71 | /* Global variable that defines the present debug level of the driver. */ | |
20346722 | 72 | int debug_level = ERR_DBG; /* Default level. */ |
1da177e4 LT |
73 | |
74 | /* DEBUG message print. */ | |
75 | #define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args) | |
76 | ||
77 | /* Protocol assist features of the NIC */ | |
78 | #define L3_CKSUM_OK 0xFFFF | |
79 | #define L4_CKSUM_OK 0xFFFF | |
80 | #define S2IO_JUMBO_SIZE 9600 | |
81 | ||
20346722 K |
82 | /* Driver statistics maintained by driver */ |
83 | typedef struct { | |
84 | unsigned long long single_ecc_errs; | |
85 | unsigned long long double_ecc_errs; | |
86 | } swStat_t; | |
87 | ||
1da177e4 LT |
88 | /* The statistics block of Xena */ |
89 | typedef struct stat_block { | |
90 | /* Tx MAC statistics counters. */ | |
91 | u32 tmac_data_octets; | |
92 | u32 tmac_frms; | |
93 | u64 tmac_drop_frms; | |
94 | u32 tmac_bcst_frms; | |
95 | u32 tmac_mcst_frms; | |
96 | u64 tmac_pause_ctrl_frms; | |
97 | u32 tmac_ucst_frms; | |
98 | u32 tmac_ttl_octets; | |
99 | u32 tmac_any_err_frms; | |
100 | u32 tmac_nucst_frms; | |
101 | u64 tmac_ttl_less_fb_octets; | |
102 | u64 tmac_vld_ip_octets; | |
103 | u32 tmac_drop_ip; | |
104 | u32 tmac_vld_ip; | |
105 | u32 tmac_rst_tcp; | |
106 | u32 tmac_icmp; | |
107 | u64 tmac_tcp; | |
108 | u32 reserved_0; | |
109 | u32 tmac_udp; | |
110 | ||
111 | /* Rx MAC Statistics counters. */ | |
112 | u32 rmac_data_octets; | |
113 | u32 rmac_vld_frms; | |
114 | u64 rmac_fcs_err_frms; | |
115 | u64 rmac_drop_frms; | |
116 | u32 rmac_vld_bcst_frms; | |
117 | u32 rmac_vld_mcst_frms; | |
118 | u32 rmac_out_rng_len_err_frms; | |
119 | u32 rmac_in_rng_len_err_frms; | |
120 | u64 rmac_long_frms; | |
121 | u64 rmac_pause_ctrl_frms; | |
122 | u64 rmac_unsup_ctrl_frms; | |
123 | u32 rmac_accepted_ucst_frms; | |
124 | u32 rmac_ttl_octets; | |
125 | u32 rmac_discarded_frms; | |
126 | u32 rmac_accepted_nucst_frms; | |
127 | u32 reserved_1; | |
128 | u32 rmac_drop_events; | |
129 | u64 rmac_ttl_less_fb_octets; | |
130 | u64 rmac_ttl_frms; | |
131 | u64 reserved_2; | |
132 | u32 rmac_usized_frms; | |
133 | u32 reserved_3; | |
134 | u32 rmac_frag_frms; | |
135 | u32 rmac_osized_frms; | |
136 | u32 reserved_4; | |
137 | u32 rmac_jabber_frms; | |
138 | u64 rmac_ttl_64_frms; | |
139 | u64 rmac_ttl_65_127_frms; | |
140 | u64 reserved_5; | |
141 | u64 rmac_ttl_128_255_frms; | |
142 | u64 rmac_ttl_256_511_frms; | |
143 | u64 reserved_6; | |
144 | u64 rmac_ttl_512_1023_frms; | |
145 | u64 rmac_ttl_1024_1518_frms; | |
146 | u32 rmac_ip; | |
147 | u32 reserved_7; | |
148 | u64 rmac_ip_octets; | |
149 | u32 rmac_drop_ip; | |
150 | u32 rmac_hdr_err_ip; | |
151 | u32 reserved_8; | |
152 | u32 rmac_icmp; | |
153 | u64 rmac_tcp; | |
154 | u32 rmac_err_drp_udp; | |
155 | u32 rmac_udp; | |
156 | u64 rmac_xgmii_err_sym; | |
157 | u64 rmac_frms_q0; | |
158 | u64 rmac_frms_q1; | |
159 | u64 rmac_frms_q2; | |
160 | u64 rmac_frms_q3; | |
161 | u64 rmac_frms_q4; | |
162 | u64 rmac_frms_q5; | |
163 | u64 rmac_frms_q6; | |
164 | u64 rmac_frms_q7; | |
165 | u16 rmac_full_q3; | |
166 | u16 rmac_full_q2; | |
167 | u16 rmac_full_q1; | |
168 | u16 rmac_full_q0; | |
169 | u16 rmac_full_q7; | |
170 | u16 rmac_full_q6; | |
171 | u16 rmac_full_q5; | |
172 | u16 rmac_full_q4; | |
173 | u32 reserved_9; | |
174 | u32 rmac_pause_cnt; | |
175 | u64 rmac_xgmii_data_err_cnt; | |
176 | u64 rmac_xgmii_ctrl_err_cnt; | |
177 | u32 rmac_err_tcp; | |
178 | u32 rmac_accepted_ip; | |
179 | ||
180 | /* PCI/PCI-X Read transaction statistics. */ | |
181 | u32 new_rd_req_cnt; | |
182 | u32 rd_req_cnt; | |
183 | u32 rd_rtry_cnt; | |
184 | u32 new_rd_req_rtry_cnt; | |
185 | ||
186 | /* PCI/PCI-X Write/Read transaction statistics. */ | |
187 | u32 wr_req_cnt; | |
188 | u32 wr_rtry_rd_ack_cnt; | |
189 | u32 new_wr_req_rtry_cnt; | |
190 | u32 new_wr_req_cnt; | |
191 | u32 wr_disc_cnt; | |
192 | u32 wr_rtry_cnt; | |
193 | ||
194 | /* PCI/PCI-X Write / DMA Transaction statistics. */ | |
195 | u32 txp_wr_cnt; | |
196 | u32 rd_rtry_wr_ack_cnt; | |
197 | u32 txd_wr_cnt; | |
198 | u32 txd_rd_cnt; | |
199 | u32 rxd_wr_cnt; | |
200 | u32 rxd_rd_cnt; | |
201 | u32 rxf_wr_cnt; | |
202 | u32 txf_rd_cnt; | |
7ba013ac K |
203 | |
204 | /* Software statistics maintained by driver */ | |
205 | swStat_t sw_stat; | |
1da177e4 LT |
206 | } StatInfo_t; |
207 | ||
20346722 K |
208 | /* |
209 | * Structures representing different init time configuration | |
1da177e4 LT |
210 | * parameters of the NIC. |
211 | */ | |
212 | ||
20346722 K |
213 | #define MAX_TX_FIFOS 8 |
214 | #define MAX_RX_RINGS 8 | |
215 | ||
216 | /* FIFO mappings for all possible number of fifos configured */ | |
217 | int fifo_map[][MAX_TX_FIFOS] = { | |
218 | {0, 0, 0, 0, 0, 0, 0, 0}, | |
219 | {0, 0, 0, 0, 1, 1, 1, 1}, | |
220 | {0, 0, 0, 1, 1, 1, 2, 2}, | |
221 | {0, 0, 1, 1, 2, 2, 3, 3}, | |
222 | {0, 0, 1, 1, 2, 2, 3, 4}, | |
223 | {0, 0, 1, 1, 2, 3, 4, 5}, | |
224 | {0, 0, 1, 2, 3, 4, 5, 6}, | |
225 | {0, 1, 2, 3, 4, 5, 6, 7}, | |
226 | }; | |
227 | ||
1da177e4 LT |
228 | /* Maintains Per FIFO related information. */ |
229 | typedef struct tx_fifo_config { | |
230 | #define MAX_AVAILABLE_TXDS 8192 | |
231 | u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */ | |
232 | /* Priority definition */ | |
233 | #define TX_FIFO_PRI_0 0 /*Highest */ | |
234 | #define TX_FIFO_PRI_1 1 | |
235 | #define TX_FIFO_PRI_2 2 | |
236 | #define TX_FIFO_PRI_3 3 | |
237 | #define TX_FIFO_PRI_4 4 | |
238 | #define TX_FIFO_PRI_5 5 | |
239 | #define TX_FIFO_PRI_6 6 | |
240 | #define TX_FIFO_PRI_7 7 /*lowest */ | |
241 | u8 fifo_priority; /* specifies pointer level for FIFO */ | |
242 | /* user should not set twos fifos with same pri */ | |
243 | u8 f_no_snoop; | |
244 | #define NO_SNOOP_TXD 0x01 | |
245 | #define NO_SNOOP_TXD_BUFFER 0x02 | |
246 | } tx_fifo_config_t; | |
247 | ||
248 | ||
249 | /* Maintains per Ring related information */ | |
250 | typedef struct rx_ring_config { | |
251 | u32 num_rxd; /*No of RxDs per Rx Ring */ | |
252 | #define RX_RING_PRI_0 0 /* highest */ | |
253 | #define RX_RING_PRI_1 1 | |
254 | #define RX_RING_PRI_2 2 | |
255 | #define RX_RING_PRI_3 3 | |
256 | #define RX_RING_PRI_4 4 | |
257 | #define RX_RING_PRI_5 5 | |
258 | #define RX_RING_PRI_6 6 | |
259 | #define RX_RING_PRI_7 7 /* lowest */ | |
260 | ||
261 | u8 ring_priority; /*Specifies service priority of ring */ | |
262 | /* OSM should not set any two rings with same priority */ | |
263 | u8 ring_org; /*Organization of ring */ | |
264 | #define RING_ORG_BUFF1 0x01 | |
265 | #define RX_RING_ORG_BUFF3 0x03 | |
266 | #define RX_RING_ORG_BUFF5 0x05 | |
267 | ||
268 | u8 f_no_snoop; | |
269 | #define NO_SNOOP_RXD 0x01 | |
270 | #define NO_SNOOP_RXD_BUFFER 0x02 | |
271 | } rx_ring_config_t; | |
272 | ||
20346722 K |
273 | /* This structure provides contains values of the tunable parameters |
274 | * of the H/W | |
1da177e4 LT |
275 | */ |
276 | struct config_param { | |
277 | /* Tx Side */ | |
278 | u32 tx_fifo_num; /*Number of Tx FIFOs */ | |
1da177e4 | 279 | |
20346722 | 280 | u8 fifo_mapping[MAX_TX_FIFOS]; |
1da177e4 LT |
281 | tx_fifo_config_t tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */ |
282 | u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */ | |
283 | u64 tx_intr_type; | |
284 | /* Specifies if Tx Intr is UTILZ or PER_LIST type. */ | |
285 | ||
286 | /* Rx Side */ | |
287 | u32 rx_ring_num; /*Number of receive rings */ | |
1da177e4 LT |
288 | #define MAX_RX_BLOCKS_PER_RING 150 |
289 | ||
290 | rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */ | |
291 | ||
292 | #define HEADER_ETHERNET_II_802_3_SIZE 14 | |
293 | #define HEADER_802_2_SIZE 3 | |
294 | #define HEADER_SNAP_SIZE 5 | |
295 | #define HEADER_VLAN_SIZE 4 | |
296 | ||
297 | #define MIN_MTU 46 | |
298 | #define MAX_PYLD 1500 | |
299 | #define MAX_MTU (MAX_PYLD+18) | |
300 | #define MAX_MTU_VLAN (MAX_PYLD+22) | |
301 | #define MAX_PYLD_JUMBO 9600 | |
302 | #define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18) | |
303 | #define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22) | |
20346722 | 304 | u16 bus_speed; |
1da177e4 LT |
305 | }; |
306 | ||
307 | /* Structure representing MAC Addrs */ | |
308 | typedef struct mac_addr { | |
309 | u8 mac_addr[ETH_ALEN]; | |
310 | } macaddr_t; | |
311 | ||
312 | /* Structure that represent every FIFO element in the BAR1 | |
20346722 | 313 | * Address location. |
1da177e4 LT |
314 | */ |
315 | typedef struct _TxFIFO_element { | |
316 | u64 TxDL_Pointer; | |
317 | ||
318 | u64 List_Control; | |
319 | #define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8) | |
320 | #define TX_FIFO_FIRST_LIST BIT(14) | |
321 | #define TX_FIFO_LAST_LIST BIT(15) | |
322 | #define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2) | |
323 | #define TX_FIFO_SPECIAL_FUNC BIT(23) | |
324 | #define TX_FIFO_DS_NO_SNOOP BIT(31) | |
325 | #define TX_FIFO_BUFF_NO_SNOOP BIT(30) | |
326 | } TxFIFO_element_t; | |
327 | ||
328 | /* Tx descriptor structure */ | |
329 | typedef struct _TxD { | |
330 | u64 Control_1; | |
331 | /* bit mask */ | |
332 | #define TXD_LIST_OWN_XENA BIT(7) | |
333 | #define TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15)) | |
334 | #define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE)) | |
335 | #define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12) | |
336 | #define TXD_GATHER_CODE (BIT(22) | BIT(23)) | |
337 | #define TXD_GATHER_CODE_FIRST BIT(22) | |
338 | #define TXD_GATHER_CODE_LAST BIT(23) | |
339 | #define TXD_TCP_LSO_EN BIT(30) | |
340 | #define TXD_UDP_COF_EN BIT(31) | |
341 | #define TXD_TCP_LSO_MSS(val) vBIT(val,34,14) | |
342 | #define TXD_BUFFER0_SIZE(val) vBIT(val,48,16) | |
343 | ||
344 | u64 Control_2; | |
345 | #define TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7)) | |
346 | #define TXD_TX_CKO_IPV4_EN BIT(5) | |
347 | #define TXD_TX_CKO_TCP_EN BIT(6) | |
348 | #define TXD_TX_CKO_UDP_EN BIT(7) | |
349 | #define TXD_VLAN_ENABLE BIT(15) | |
350 | #define TXD_VLAN_TAG(val) vBIT(val,16,16) | |
351 | #define TXD_INT_NUMBER(val) vBIT(val,34,6) | |
352 | #define TXD_INT_TYPE_PER_LIST BIT(47) | |
353 | #define TXD_INT_TYPE_UTILZ BIT(46) | |
354 | #define TXD_SET_MARKER vBIT(0x6,0,4) | |
355 | ||
356 | u64 Buffer_Pointer; | |
357 | u64 Host_Control; /* reserved for host */ | |
358 | } TxD_t; | |
359 | ||
360 | /* Structure to hold the phy and virt addr of every TxDL. */ | |
361 | typedef struct list_info_hold { | |
362 | dma_addr_t list_phy_addr; | |
363 | void *list_virt_addr; | |
364 | } list_info_hold_t; | |
365 | ||
366 | /* Rx descriptor structure */ | |
367 | typedef struct _RxD_t { | |
368 | u64 Host_Control; /* reserved for host */ | |
369 | u64 Control_1; | |
370 | #define RXD_OWN_XENA BIT(7) | |
371 | #define RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15)) | |
372 | #define RXD_FRAME_PROTO vBIT(0xFFFF,24,8) | |
373 | #define RXD_FRAME_PROTO_IPV4 BIT(27) | |
374 | #define RXD_FRAME_PROTO_IPV6 BIT(28) | |
20346722 | 375 | #define RXD_FRAME_IP_FRAG BIT(29) |
1da177e4 LT |
376 | #define RXD_FRAME_PROTO_TCP BIT(30) |
377 | #define RXD_FRAME_PROTO_UDP BIT(31) | |
378 | #define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP) | |
379 | #define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF) | |
380 | #define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF) | |
381 | ||
382 | u64 Control_2; | |
5e25b9dd K |
383 | #define THE_RXD_MARK 0x3 |
384 | #define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2) | |
385 | #define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62) | |
386 | ||
1da177e4 | 387 | #ifndef CONFIG_2BUFF_MODE |
20346722 K |
388 | #define MASK_BUFFER0_SIZE vBIT(0x3FFF,2,14) |
389 | #define SET_BUFFER0_SIZE(val) vBIT(val,2,14) | |
1da177e4 | 390 | #else |
20346722 | 391 | #define MASK_BUFFER0_SIZE vBIT(0xFF,2,14) |
1da177e4 LT |
392 | #define MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16) |
393 | #define MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16) | |
394 | #define SET_BUFFER0_SIZE(val) vBIT(val,8,8) | |
395 | #define SET_BUFFER1_SIZE(val) vBIT(val,16,16) | |
396 | #define SET_BUFFER2_SIZE(val) vBIT(val,32,16) | |
397 | #endif | |
398 | ||
399 | #define MASK_VLAN_TAG vBIT(0xFFFF,48,16) | |
400 | #define SET_VLAN_TAG(val) vBIT(val,48,16) | |
401 | #define SET_NUM_TAG(val) vBIT(val,16,32) | |
402 | ||
403 | #ifndef CONFIG_2BUFF_MODE | |
20346722 | 404 | #define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0x3FFF,2,14))) |
1da177e4 LT |
405 | #else |
406 | #define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \ | |
407 | >> 48) | |
408 | #define RXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) \ | |
409 | >> 32) | |
410 | #define RXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) \ | |
411 | >> 16) | |
412 | #define BUF0_LEN 40 | |
413 | #define BUF1_LEN 1 | |
414 | #endif | |
415 | ||
416 | u64 Buffer0_ptr; | |
417 | #ifdef CONFIG_2BUFF_MODE | |
418 | u64 Buffer1_ptr; | |
419 | u64 Buffer2_ptr; | |
420 | #endif | |
421 | } RxD_t; | |
422 | ||
20346722 | 423 | /* Structure that represents the Rx descriptor block which contains |
1da177e4 LT |
424 | * 128 Rx descriptors. |
425 | */ | |
426 | #ifndef CONFIG_2BUFF_MODE | |
427 | typedef struct _RxD_block { | |
428 | #define MAX_RXDS_PER_BLOCK 127 | |
429 | RxD_t rxd[MAX_RXDS_PER_BLOCK]; | |
430 | ||
431 | u64 reserved_0; | |
432 | #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL | |
20346722 | 433 | u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last |
1da177e4 LT |
434 | * Rxd in this blk */ |
435 | u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */ | |
436 | u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch | |
20346722 | 437 | * the upper 32 bits should |
1da177e4 LT |
438 | * be 0 */ |
439 | } RxD_block_t; | |
440 | #else | |
441 | typedef struct _RxD_block { | |
442 | #define MAX_RXDS_PER_BLOCK 85 | |
443 | RxD_t rxd[MAX_RXDS_PER_BLOCK]; | |
444 | ||
445 | #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL | |
20346722 | 446 | u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd |
1da177e4 LT |
447 | * in this blk */ |
448 | u64 pNext_RxD_Blk_physical; /* Phy ponter to next blk. */ | |
449 | } RxD_block_t; | |
450 | #define SIZE_OF_BLOCK 4096 | |
451 | ||
20346722 | 452 | /* Structure to hold virtual addresses of Buf0 and Buf1 in |
1da177e4 LT |
453 | * 2buf mode. */ |
454 | typedef struct bufAdd { | |
455 | void *ba_0_org; | |
456 | void *ba_1_org; | |
457 | void *ba_0; | |
458 | void *ba_1; | |
459 | } buffAdd_t; | |
460 | #endif | |
461 | ||
462 | /* Structure which stores all the MAC control parameters */ | |
463 | ||
20346722 K |
464 | /* This structure stores the offset of the RxD in the ring |
465 | * from which the Rx Interrupt processor can start picking | |
1da177e4 LT |
466 | * up the RxDs for processing. |
467 | */ | |
468 | typedef struct _rx_curr_get_info_t { | |
469 | u32 block_index; | |
470 | u32 offset; | |
471 | u32 ring_len; | |
472 | } rx_curr_get_info_t; | |
473 | ||
474 | typedef rx_curr_get_info_t rx_curr_put_info_t; | |
475 | ||
476 | /* This structure stores the offset of the TxDl in the FIFO | |
20346722 | 477 | * from which the Tx Interrupt processor can start picking |
1da177e4 LT |
478 | * up the TxDLs for send complete interrupt processing. |
479 | */ | |
480 | typedef struct { | |
481 | u32 offset; | |
482 | u32 fifo_len; | |
483 | } tx_curr_get_info_t; | |
484 | ||
485 | typedef tx_curr_get_info_t tx_curr_put_info_t; | |
486 | ||
20346722 K |
487 | /* Structure that holds the Phy and virt addresses of the Blocks */ |
488 | typedef struct rx_block_info { | |
489 | RxD_t *block_virt_addr; | |
490 | dma_addr_t block_dma_addr; | |
491 | } rx_block_info_t; | |
492 | ||
493 | /* pre declaration of the nic structure */ | |
494 | typedef struct s2io_nic nic_t; | |
495 | ||
496 | /* Ring specific structure */ | |
497 | typedef struct ring_info { | |
498 | /* The ring number */ | |
499 | int ring_no; | |
500 | ||
501 | /* | |
502 | * Place holders for the virtual and physical addresses of | |
503 | * all the Rx Blocks | |
504 | */ | |
505 | rx_block_info_t rx_blocks[MAX_RX_BLOCKS_PER_RING]; | |
506 | int block_count; | |
507 | int pkt_cnt; | |
508 | ||
509 | /* | |
510 | * Put pointer info which indictes which RxD has to be replenished | |
1da177e4 LT |
511 | * with a new buffer. |
512 | */ | |
20346722 | 513 | rx_curr_put_info_t rx_curr_put_info; |
1da177e4 | 514 | |
20346722 K |
515 | /* |
516 | * Get pointer info which indictes which is the last RxD that was | |
1da177e4 LT |
517 | * processed by the driver. |
518 | */ | |
20346722 | 519 | rx_curr_get_info_t rx_curr_get_info; |
1da177e4 | 520 | |
20346722 K |
521 | #ifndef CONFIG_S2IO_NAPI |
522 | /* Index to the absolute position of the put pointer of Rx ring */ | |
523 | int put_pos; | |
524 | #endif | |
525 | ||
526 | #ifdef CONFIG_2BUFF_MODE | |
527 | /* Buffer Address store. */ | |
528 | buffAdd_t **ba; | |
529 | #endif | |
530 | nic_t *nic; | |
531 | } ring_info_t; | |
1da177e4 | 532 | |
20346722 K |
533 | /* Fifo specific structure */ |
534 | typedef struct fifo_info { | |
535 | /* FIFO number */ | |
536 | int fifo_no; | |
537 | ||
538 | /* Maximum TxDs per TxDL */ | |
539 | int max_txds; | |
540 | ||
541 | /* Place holder of all the TX List's Phy and Virt addresses. */ | |
542 | list_info_hold_t *list_info; | |
543 | ||
544 | /* | |
545 | * Current offset within the tx FIFO where driver would write | |
546 | * new Tx frame | |
547 | */ | |
548 | tx_curr_put_info_t tx_curr_put_info; | |
549 | ||
550 | /* | |
551 | * Current offset within tx FIFO from where the driver would start freeing | |
552 | * the buffers | |
553 | */ | |
554 | tx_curr_get_info_t tx_curr_get_info; | |
555 | ||
556 | nic_t *nic; | |
557 | }fifo_info_t; | |
558 | ||
559 | /* Infomation related to the Tx and Rx FIFOs and Rings of Xena | |
560 | * is maintained in this structure. | |
561 | */ | |
562 | typedef struct mac_info { | |
1da177e4 LT |
563 | /* tx side stuff */ |
564 | /* logical pointer of start of each Tx FIFO */ | |
565 | TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS]; | |
566 | ||
20346722 K |
567 | /* Fifo specific structure */ |
568 | fifo_info_t fifos[MAX_TX_FIFOS]; | |
569 | ||
570 | /* rx side stuff */ | |
571 | /* Ring specific structure */ | |
572 | ring_info_t rings[MAX_RX_RINGS]; | |
573 | ||
574 | u16 rmac_pause_time; | |
575 | u16 mc_pause_threshold_q0q3; | |
576 | u16 mc_pause_threshold_q4q7; | |
1da177e4 LT |
577 | |
578 | void *stats_mem; /* orignal pointer to allocated mem */ | |
579 | dma_addr_t stats_mem_phy; /* Physical address of the stat block */ | |
580 | u32 stats_mem_sz; | |
581 | StatInfo_t *stats_info; /* Logical address of the stat block */ | |
582 | } mac_info_t; | |
583 | ||
584 | /* structure representing the user defined MAC addresses */ | |
585 | typedef struct { | |
586 | char addr[ETH_ALEN]; | |
587 | int usage_cnt; | |
588 | } usr_addr_t; | |
589 | ||
1da177e4 LT |
590 | /* Default Tunable parameters of the NIC. */ |
591 | #define DEFAULT_FIFO_LEN 4096 | |
592 | #define SMALL_RXD_CNT 30 * (MAX_RXDS_PER_BLOCK+1) | |
593 | #define LARGE_RXD_CNT 100 * (MAX_RXDS_PER_BLOCK+1) | |
594 | #define SMALL_BLK_CNT 30 | |
595 | #define LARGE_BLK_CNT 100 | |
596 | ||
597 | /* Structure representing one instance of the NIC */ | |
20346722 K |
598 | struct s2io_nic { |
599 | #ifdef CONFIG_S2IO_NAPI | |
600 | /* | |
601 | * Count of packets to be processed in a given iteration, it will be indicated | |
602 | * by the quota field of the device structure when NAPI is enabled. | |
603 | */ | |
604 | int pkts_to_process; | |
605 | #endif | |
606 | struct net_device *dev; | |
607 | mac_info_t mac_control; | |
608 | struct config_param config; | |
609 | struct pci_dev *pdev; | |
610 | void __iomem *bar0; | |
611 | void __iomem *bar1; | |
1da177e4 LT |
612 | #define MAX_MAC_SUPPORTED 16 |
613 | #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED | |
614 | ||
615 | macaddr_t def_mac_addr[MAX_MAC_SUPPORTED]; | |
616 | macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED]; | |
617 | ||
618 | struct net_device_stats stats; | |
1da177e4 LT |
619 | int high_dma_flag; |
620 | int device_close_flag; | |
621 | int device_enabled_once; | |
622 | ||
20346722 | 623 | char name[50]; |
1da177e4 LT |
624 | struct tasklet_struct task; |
625 | volatile unsigned long tasklet_status; | |
1da177e4 | 626 | |
25fff88e K |
627 | /* Timer that handles I/O errors/exceptions */ |
628 | struct timer_list alarm_timer; | |
629 | ||
20346722 K |
630 | /* Space to back up the PCI config space */ |
631 | u32 config_space[256 / sizeof(u32)]; | |
632 | ||
1da177e4 LT |
633 | atomic_t rx_bufs_left[MAX_RX_RINGS]; |
634 | ||
635 | spinlock_t tx_lock; | |
636 | #ifndef CONFIG_S2IO_NAPI | |
637 | spinlock_t put_lock; | |
638 | #endif | |
639 | ||
640 | #define PROMISC 1 | |
641 | #define ALL_MULTI 2 | |
642 | ||
643 | #define MAX_ADDRS_SUPPORTED 64 | |
644 | u16 usr_addr_count; | |
645 | u16 mc_addr_count; | |
646 | usr_addr_t usr_addrs[MAX_ADDRS_SUPPORTED]; | |
647 | ||
648 | u16 m_cast_flg; | |
649 | u16 all_multi_pos; | |
650 | u16 promisc_flg; | |
651 | ||
652 | u16 tx_pkt_count; | |
653 | u16 rx_pkt_count; | |
654 | u16 tx_err_count; | |
655 | u16 rx_err_count; | |
656 | ||
1da177e4 LT |
657 | /* Id timer, used to blink NIC to physically identify NIC. */ |
658 | struct timer_list id_timer; | |
659 | ||
660 | /* Restart timer, used to restart NIC if the device is stuck and | |
20346722 | 661 | * a schedule task that will set the correct Link state once the |
1da177e4 LT |
662 | * NIC's PHY has stabilized after a state change. |
663 | */ | |
664 | #ifdef INIT_TQUEUE | |
665 | struct tq_struct rst_timer_task; | |
666 | struct tq_struct set_link_task; | |
667 | #else | |
668 | struct work_struct rst_timer_task; | |
669 | struct work_struct set_link_task; | |
670 | #endif | |
671 | ||
20346722 | 672 | /* Flag that can be used to turn on or turn off the Rx checksum |
1da177e4 LT |
673 | * offload feature. |
674 | */ | |
675 | int rx_csum; | |
676 | ||
20346722 | 677 | /* after blink, the adapter must be restored with original |
1da177e4 LT |
678 | * values. |
679 | */ | |
680 | u64 adapt_ctrl_org; | |
681 | ||
682 | /* Last known link state. */ | |
683 | u16 last_link_state; | |
684 | #define LINK_DOWN 1 | |
685 | #define LINK_UP 2 | |
686 | ||
1da177e4 LT |
687 | int task_flag; |
688 | #define CARD_DOWN 1 | |
689 | #define CARD_UP 2 | |
690 | atomic_t card_state; | |
691 | volatile unsigned long link_state; | |
7ba013ac K |
692 | spinlock_t rx_lock; |
693 | atomic_t isr_cnt; | |
20346722 | 694 | }; |
1da177e4 LT |
695 | |
696 | #define RESET_ERROR 1; | |
697 | #define CMD_ERROR 2; | |
698 | ||
699 | /* OS related system calls */ | |
700 | #ifndef readq | |
701 | static inline u64 readq(void __iomem *addr) | |
702 | { | |
20346722 K |
703 | u64 ret = 0; |
704 | ret = readl(addr + 4); | |
705 | (u64) ret <<= 32; | |
706 | (u64) ret |= readl(addr); | |
1da177e4 LT |
707 | |
708 | return ret; | |
709 | } | |
710 | #endif | |
711 | ||
712 | #ifndef writeq | |
713 | static inline void writeq(u64 val, void __iomem *addr) | |
714 | { | |
715 | writel((u32) (val), addr); | |
716 | writel((u32) (val >> 32), (addr + 4)); | |
717 | } | |
718 | ||
20346722 | 719 | /* In 32 bit modes, some registers have to be written in a |
1da177e4 | 720 | * particular order to expect correct hardware operation. The |
20346722 K |
721 | * macro SPECIAL_REG_WRITE is used to perform such ordered |
722 | * writes. Defines UF (Upper First) and LF (Lower First) will | |
1da177e4 LT |
723 | * be used to specify the required write order. |
724 | */ | |
725 | #define UF 1 | |
726 | #define LF 2 | |
727 | static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order) | |
728 | { | |
729 | if (order == LF) { | |
730 | writel((u32) (val), addr); | |
731 | writel((u32) (val >> 32), (addr + 4)); | |
732 | } else { | |
733 | writel((u32) (val >> 32), (addr + 4)); | |
734 | writel((u32) (val), addr); | |
735 | } | |
736 | } | |
737 | #else | |
738 | #define SPECIAL_REG_WRITE(val, addr, dummy) writeq(val, addr) | |
739 | #endif | |
740 | ||
741 | /* Interrupt related values of Xena */ | |
742 | ||
743 | #define ENABLE_INTRS 1 | |
744 | #define DISABLE_INTRS 2 | |
745 | ||
746 | /* Highest level interrupt blocks */ | |
747 | #define TX_PIC_INTR (0x0001<<0) | |
748 | #define TX_DMA_INTR (0x0001<<1) | |
749 | #define TX_MAC_INTR (0x0001<<2) | |
750 | #define TX_XGXS_INTR (0x0001<<3) | |
751 | #define TX_TRAFFIC_INTR (0x0001<<4) | |
752 | #define RX_PIC_INTR (0x0001<<5) | |
753 | #define RX_DMA_INTR (0x0001<<6) | |
754 | #define RX_MAC_INTR (0x0001<<7) | |
755 | #define RX_XGXS_INTR (0x0001<<8) | |
756 | #define RX_TRAFFIC_INTR (0x0001<<9) | |
757 | #define MC_INTR (0x0001<<10) | |
758 | #define ENA_ALL_INTRS ( TX_PIC_INTR | \ | |
759 | TX_DMA_INTR | \ | |
760 | TX_MAC_INTR | \ | |
761 | TX_XGXS_INTR | \ | |
762 | TX_TRAFFIC_INTR | \ | |
763 | RX_PIC_INTR | \ | |
764 | RX_DMA_INTR | \ | |
765 | RX_MAC_INTR | \ | |
766 | RX_XGXS_INTR | \ | |
767 | RX_TRAFFIC_INTR | \ | |
768 | MC_INTR ) | |
769 | ||
770 | /* Interrupt masks for the general interrupt mask register */ | |
771 | #define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL | |
772 | ||
773 | #define TXPIC_INT_M BIT(0) | |
774 | #define TXDMA_INT_M BIT(1) | |
775 | #define TXMAC_INT_M BIT(2) | |
776 | #define TXXGXS_INT_M BIT(3) | |
777 | #define TXTRAFFIC_INT_M BIT(8) | |
778 | #define PIC_RX_INT_M BIT(32) | |
779 | #define RXDMA_INT_M BIT(33) | |
780 | #define RXMAC_INT_M BIT(34) | |
781 | #define MC_INT_M BIT(35) | |
782 | #define RXXGXS_INT_M BIT(36) | |
783 | #define RXTRAFFIC_INT_M BIT(40) | |
784 | ||
785 | /* PIC level Interrupts TODO*/ | |
786 | ||
787 | /* DMA level Inressupts */ | |
788 | #define TXDMA_PFC_INT_M BIT(0) | |
789 | #define TXDMA_PCC_INT_M BIT(2) | |
790 | ||
791 | /* PFC block interrupts */ | |
792 | #define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */ | |
793 | ||
794 | /* PCC block interrupts. */ | |
795 | #define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate | |
796 | PCC_FB_ECC Error. */ | |
797 | ||
20346722 | 798 | #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG) |
1da177e4 LT |
799 | /* |
800 | * Prototype declaration. | |
801 | */ | |
802 | static int __devinit s2io_init_nic(struct pci_dev *pdev, | |
803 | const struct pci_device_id *pre); | |
804 | static void __devexit s2io_rem_nic(struct pci_dev *pdev); | |
805 | static int init_shared_mem(struct s2io_nic *sp); | |
806 | static void free_shared_mem(struct s2io_nic *sp); | |
807 | static int init_nic(struct s2io_nic *nic); | |
20346722 K |
808 | static void rx_intr_handler(ring_info_t *ring_data); |
809 | static void tx_intr_handler(fifo_info_t *fifo_data); | |
1da177e4 LT |
810 | static void alarm_intr_handler(struct s2io_nic *sp); |
811 | ||
812 | static int s2io_starter(void); | |
20346722 | 813 | void s2io_closer(void); |
1da177e4 LT |
814 | static void s2io_tx_watchdog(struct net_device *dev); |
815 | static void s2io_tasklet(unsigned long dev_addr); | |
816 | static void s2io_set_multicast(struct net_device *dev); | |
20346722 K |
817 | static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp); |
818 | void s2io_link(nic_t * sp, int link); | |
819 | void s2io_reset(nic_t * sp); | |
820 | #if defined(CONFIG_S2IO_NAPI) | |
1da177e4 LT |
821 | static int s2io_poll(struct net_device *dev, int *budget); |
822 | #endif | |
823 | static void s2io_init_pci(nic_t * sp); | |
20346722 | 824 | int s2io_set_mac_addr(struct net_device *dev, u8 * addr); |
25fff88e | 825 | static void s2io_alarm_handle(unsigned long data); |
1da177e4 | 826 | static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs); |
20346722 | 827 | static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag); |
1da177e4 LT |
828 | static struct ethtool_ops netdev_ethtool_ops; |
829 | static void s2io_set_link(unsigned long data); | |
20346722 K |
830 | int s2io_set_swapper(nic_t * sp); |
831 | static void s2io_card_down(nic_t *nic); | |
832 | static int s2io_card_up(nic_t *nic); | |
833 | int get_xena_rev_id(struct pci_dev *pdev); | |
1da177e4 | 834 | #endif /* _S2IO_H */ |