]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/s2io.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
S2IO: Removing 3 buffer mode support from the driver
[net-next-2.6.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
1da177e4
LT		 4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722
K		 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4
LT		 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
9dc737a7 29 *
20346722
K		 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7
AR		 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 1(MSI), 2(MSI_X). Default value is '0(INTA)'
41 * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
1da177e4
LT		 53 ************************************************************************/
54
1da177e4
LT		 55#include <linux/module.h>
56#include <linux/types.h>
57#include <linux/errno.h>
58#include <linux/ioport.h>
59#include <linux/pci.h>
1e7f0bd8 60#include <linux/dma-mapping.h>
1da177e4
LT		 61#include <linux/kernel.h>
62#include <linux/netdevice.h>
63#include <linux/etherdevice.h>
64#include <linux/skbuff.h>
65#include <linux/init.h>
66#include <linux/delay.h>
67#include <linux/stddef.h>
68#include <linux/ioctl.h>
69#include <linux/timex.h>
1da177e4 70#include <linux/ethtool.h>
1da177e4 71#include <linux/workqueue.h>
be3a6b02 72#include <linux/if_vlan.h>
7d3d0439
RA		 73#include <linux/ip.h>
74#include <linux/tcp.h>
75#include <net/tcp.h>
1da177e4 76
1da177e4
LT		 77#include <asm/system.h>
78#include <asm/uaccess.h>
20346722 79#include <asm/io.h>
fe931395 80#include <asm/div64.h>
330ce0de 81#include <asm/irq.h>
1da177e4
LT		 82
83/* local include */
84#include "s2io.h"
85#include "s2io-regs.h"
86
491976b2 87#define DRV_VERSION "2.0.23.1"
6c1792f4 88
1da177e4 89/* S2io Driver name & version. */
20346722 90static char s2io_driver_name[] = "Neterion";
6c1792f4 91static char s2io_driver_version[] = DRV_VERSION;
1da177e4 92
6d517a27
VP		 93static int rxd_size[2] = {32,48};
94static int rxd_count[2] = {127,85};
da6971d8 95
1ee6dd77 96static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd
K		 97{
98 int ret;
99
100 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
101 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
102
103 return ret;
104}
105
20346722 106/*
1da177e4
LT		 107 * Cards with following subsystem_id have a link state indication
108 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
109 * macro below identifies these cards given the subsystem_id.
110 */
541ae68f
K		 111#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
112 (dev_type == XFRAME_I_DEVICE) ? \
113 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
114 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 115
116#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
117 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
118#define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
119#define PANIC 1
120#define LOW 2
1ee6dd77 121static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
1da177e4 122{
1ee6dd77 123 struct mac_info *mac_control;
20346722
K		 124
125 mac_control = &sp->mac_control;
863c11a9
AR		 126 if (rxb_size <= rxd_count[sp->rxd_mode])
127 return PANIC;
128 else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
129 return LOW;
130 return 0;
1da177e4
LT		 131}
132
133/* Ethtool related variables and Macros. */
134static char s2io_gstrings[][ETH_GSTRING_LEN] = {
135 "Register test\t(offline)",
136 "Eeprom test\t(offline)",
137 "Link test\t(online)",
138 "RLDRAM test\t(offline)",
139 "BIST Test\t(offline)"
140};
141
fa1f0cb3 142static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 143 {"tmac_frms"},
144 {"tmac_data_octets"},
145 {"tmac_drop_frms"},
146 {"tmac_mcst_frms"},
147 {"tmac_bcst_frms"},
148 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 149 {"tmac_ttl_octets"},
150 {"tmac_ucst_frms"},
151 {"tmac_nucst_frms"},
1da177e4 152 {"tmac_any_err_frms"},
bd1034f0 153 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 154 {"tmac_vld_ip_octets"},
155 {"tmac_vld_ip"},
156 {"tmac_drop_ip"},
157 {"tmac_icmp"},
158 {"tmac_rst_tcp"},
159 {"tmac_tcp"},
160 {"tmac_udp"},
161 {"rmac_vld_frms"},
162 {"rmac_data_octets"},
163 {"rmac_fcs_err_frms"},
164 {"rmac_drop_frms"},
165 {"rmac_vld_mcst_frms"},
166 {"rmac_vld_bcst_frms"},
167 {"rmac_in_rng_len_err_frms"},
bd1034f0 168 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 169 {"rmac_long_frms"},
170 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 171 {"rmac_unsup_ctrl_frms"},
172 {"rmac_ttl_octets"},
173 {"rmac_accepted_ucst_frms"},
174 {"rmac_accepted_nucst_frms"},
1da177e4 175 {"rmac_discarded_frms"},
bd1034f0
AR		 176 {"rmac_drop_events"},
177 {"rmac_ttl_less_fb_octets"},
178 {"rmac_ttl_frms"},
1da177e4
LT		 179 {"rmac_usized_frms"},
180 {"rmac_osized_frms"},
181 {"rmac_frag_frms"},
182 {"rmac_jabber_frms"},
bd1034f0
AR		 183 {"rmac_ttl_64_frms"},
184 {"rmac_ttl_65_127_frms"},
185 {"rmac_ttl_128_255_frms"},
186 {"rmac_ttl_256_511_frms"},
187 {"rmac_ttl_512_1023_frms"},
188 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 189 {"rmac_ip"},
190 {"rmac_ip_octets"},
191 {"rmac_hdr_err_ip"},
192 {"rmac_drop_ip"},
193 {"rmac_icmp"},
194 {"rmac_tcp"},
195 {"rmac_udp"},
196 {"rmac_err_drp_udp"},
bd1034f0
AR		 197 {"rmac_xgmii_err_sym"},
198 {"rmac_frms_q0"},
199 {"rmac_frms_q1"},
200 {"rmac_frms_q2"},
201 {"rmac_frms_q3"},
202 {"rmac_frms_q4"},
203 {"rmac_frms_q5"},
204 {"rmac_frms_q6"},
205 {"rmac_frms_q7"},
206 {"rmac_full_q0"},
207 {"rmac_full_q1"},
208 {"rmac_full_q2"},
209 {"rmac_full_q3"},
210 {"rmac_full_q4"},
211 {"rmac_full_q5"},
212 {"rmac_full_q6"},
213 {"rmac_full_q7"},
1da177e4 214 {"rmac_pause_cnt"},
bd1034f0
AR		 215 {"rmac_xgmii_data_err_cnt"},
216 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 217 {"rmac_accepted_ip"},
218 {"rmac_err_tcp"},
bd1034f0
AR		 219 {"rd_req_cnt"},
220 {"new_rd_req_cnt"},
221 {"new_rd_req_rtry_cnt"},
222 {"rd_rtry_cnt"},
223 {"wr_rtry_rd_ack_cnt"},
224 {"wr_req_cnt"},
225 {"new_wr_req_cnt"},
226 {"new_wr_req_rtry_cnt"},
227 {"wr_rtry_cnt"},
228 {"wr_disc_cnt"},
229 {"rd_rtry_wr_ack_cnt"},
230 {"txp_wr_cnt"},
231 {"txd_rd_cnt"},
232 {"txd_wr_cnt"},
233 {"rxd_rd_cnt"},
234 {"rxd_wr_cnt"},
235 {"txf_rd_cnt"},
fa1f0cb3
SS		 236 {"rxf_wr_cnt"}
237};
238
239static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 240 {"rmac_ttl_1519_4095_frms"},
241 {"rmac_ttl_4096_8191_frms"},
242 {"rmac_ttl_8192_max_frms"},
243 {"rmac_ttl_gt_max_frms"},
244 {"rmac_osized_alt_frms"},
245 {"rmac_jabber_alt_frms"},
246 {"rmac_gt_max_alt_frms"},
247 {"rmac_vlan_frms"},
248 {"rmac_len_discard"},
249 {"rmac_fcs_discard"},
250 {"rmac_pf_discard"},
251 {"rmac_da_discard"},
252 {"rmac_red_discard"},
253 {"rmac_rts_discard"},
254 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 255 {"link_fault_cnt"}
256};
257
258static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac
K		 259 {"\n DRIVER STATISTICS"},
260 {"single_bit_ecc_errs"},
261 {"double_bit_ecc_errs"},
bd1034f0
AR		 262 {"parity_err_cnt"},
263 {"serious_err_cnt"},
264 {"soft_reset_cnt"},
265 {"fifo_full_cnt"},
266 {"ring_full_cnt"},
267 ("alarm_transceiver_temp_high"),
268 ("alarm_transceiver_temp_low"),
269 ("alarm_laser_bias_current_high"),
270 ("alarm_laser_bias_current_low"),
271 ("alarm_laser_output_power_high"),
272 ("alarm_laser_output_power_low"),
273 ("warn_transceiver_temp_high"),
274 ("warn_transceiver_temp_low"),
275 ("warn_laser_bias_current_high"),
276 ("warn_laser_bias_current_low"),
277 ("warn_laser_output_power_high"),
278 ("warn_laser_output_power_low"),
7d3d0439
RA		 279 ("lro_aggregated_pkts"),
280 ("lro_flush_both_count"),
281 ("lro_out_of_sequence_pkts"),
282 ("lro_flush_due_to_max_pkts"),
283 ("lro_avg_aggr_pkts"),
c53d4945 284 ("mem_alloc_fail_cnt"),
491976b2
SH		 285 ("watchdog_timer_cnt"),
286 ("mem_allocated"),
287 ("mem_freed"),
288 ("link_up_cnt"),
289 ("link_down_cnt"),
290 ("link_up_time"),
291 ("link_down_time"),
292 ("tx_tcode_buf_abort_cnt"),
293 ("tx_tcode_desc_abort_cnt"),
294 ("tx_tcode_parity_err_cnt"),
295 ("tx_tcode_link_loss_cnt"),
296 ("tx_tcode_list_proc_err_cnt"),
297 ("rx_tcode_parity_err_cnt"),
298 ("rx_tcode_abort_cnt"),
299 ("rx_tcode_parity_abort_cnt"),
300 ("rx_tcode_rda_fail_cnt"),
301 ("rx_tcode_unkn_prot_cnt"),
302 ("rx_tcode_fcs_err_cnt"),
303 ("rx_tcode_buf_size_err_cnt"),
304 ("rx_tcode_rxd_corrupt_cnt"),
305 ("rx_tcode_unkn_err_cnt")
1da177e4
LT		 306};
307
fa1f0cb3
SS		 308#define S2IO_XENA_STAT_LEN sizeof(ethtool_xena_stats_keys)/ ETH_GSTRING_LEN
309#define S2IO_ENHANCED_STAT_LEN sizeof(ethtool_enhanced_stats_keys)/ \
310 ETH_GSTRING_LEN
311#define S2IO_DRIVER_STAT_LEN sizeof(ethtool_driver_stats_keys)/ ETH_GSTRING_LEN
312
313#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
314#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
315
316#define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
317#define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
1da177e4
LT		 318
319#define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
320#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
321
25fff88e
K		 322#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
323 init_timer(&timer); \
324 timer.function = handle; \
325 timer.data = (unsigned long) arg; \
326 mod_timer(&timer, (jiffies + exp)) \
327
be3a6b02
K		 328/* Add the vlan */
329static void s2io_vlan_rx_register(struct net_device *dev,
330 struct vlan_group *grp)
331{
1ee6dd77 332 struct s2io_nic *nic = dev->priv;
be3a6b02
K		 333 unsigned long flags;
334
335 spin_lock_irqsave(&nic->tx_lock, flags);
336 nic->vlgrp = grp;
337 spin_unlock_irqrestore(&nic->tx_lock, flags);
338}
339
926930b2 340/* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
7b490343 341static int vlan_strip_flag;
926930b2 342
20346722 343/*
1da177e4
LT		 344 * Constants to be programmed into the Xena's registers, to configure
345 * the XAUI.
346 */
347
1da177e4 348#define END_SIGN 0x0
f71e1309 349static const u64 herc_act_dtx_cfg[] = {
541ae68f 350 /* Set address */
e960fc5c 351 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 352 /* Write data */
e960fc5c 353 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f
K		 354 /* Set address */
355 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
356 /* Write data */
357 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
358 /* Set address */
e960fc5c 359 0x801205150D440000ULL, 0x801205150D4400E0ULL,
360 /* Write data */
361 0x801205150D440004ULL, 0x801205150D4400E4ULL,
362 /* Set address */
541ae68f
K		 363 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
364 /* Write data */
365 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
366 /* Done */
367 END_SIGN
368};
369
f71e1309 370static const u64 xena_dtx_cfg[] = {
c92ca04b 371 /* Set address */
1da177e4 372 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 373 /* Write data */
374 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
375 /* Set address */
376 0x8001051500000000ULL, 0x80010515000000E0ULL,
377 /* Write data */
378 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
379 /* Set address */
1da177e4 380 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 381 /* Write data */
382 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 383 END_SIGN
384};
385
20346722 386/*
1da177e4
LT		 387 * Constants for Fixing the MacAddress problem seen mostly on
388 * Alpha machines.
389 */
f71e1309 390static const u64 fix_mac[] = {
1da177e4
LT		 391 0x0060000000000000ULL, 0x0060600000000000ULL,
392 0x0040600000000000ULL, 0x0000600000000000ULL,
393 0x0020600000000000ULL, 0x0060600000000000ULL,
394 0x0020600000000000ULL, 0x0060600000000000ULL,
395 0x0020600000000000ULL, 0x0060600000000000ULL,
396 0x0020600000000000ULL, 0x0060600000000000ULL,
397 0x0020600000000000ULL, 0x0060600000000000ULL,
398 0x0020600000000000ULL, 0x0060600000000000ULL,
399 0x0020600000000000ULL, 0x0060600000000000ULL,
400 0x0020600000000000ULL, 0x0060600000000000ULL,
401 0x0020600000000000ULL, 0x0060600000000000ULL,
402 0x0020600000000000ULL, 0x0060600000000000ULL,
403 0x0020600000000000ULL, 0x0000600000000000ULL,
404 0x0040600000000000ULL, 0x0060600000000000ULL,
405 END_SIGN
406};
407
b41477f3
AR		 408MODULE_LICENSE("GPL");
409MODULE_VERSION(DRV_VERSION);
410
411
1da177e4 412/* Module Loadable parameters. */
b41477f3
AR		 413S2IO_PARM_INT(tx_fifo_num, 1);
414S2IO_PARM_INT(rx_ring_num, 1);
415
416
417S2IO_PARM_INT(rx_ring_mode, 1);
418S2IO_PARM_INT(use_continuous_tx_intrs, 1);
419S2IO_PARM_INT(rmac_pause_time, 0x100);
420S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
421S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
422S2IO_PARM_INT(shared_splits, 0);
423S2IO_PARM_INT(tmac_util_period, 5);
424S2IO_PARM_INT(rmac_util_period, 5);
425S2IO_PARM_INT(bimodal, 0);
426S2IO_PARM_INT(l3l4hdr_size, 128);
303bcb4b 427/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 428S2IO_PARM_INT(rxsync_frequency, 3);
cc6e7c44 429/* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
b41477f3 430S2IO_PARM_INT(intr_type, 0);
7d3d0439 431/* Large receive offload feature */
b41477f3 432S2IO_PARM_INT(lro, 0);
7d3d0439
RA		 433/* Max pkts to be aggregated by LRO at one time. If not specified,
434 * aggregation happens until we hit max IP pkt size(64K)
435 */
b41477f3 436S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 437S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 438
439S2IO_PARM_INT(napi, 1);
440S2IO_PARM_INT(ufo, 0);
926930b2 441S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 442
443static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
444 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
445static unsigned int rx_ring_sz[MAX_RX_RINGS] =
446 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
447static unsigned int rts_frm_len[MAX_RX_RINGS] =
448 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
449
450module_param_array(tx_fifo_len, uint, NULL, 0);
451module_param_array(rx_ring_sz, uint, NULL, 0);
452module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 453
20346722 454/*
1da177e4 455 * S2IO device table.
20346722 456 * This table lists all the devices that this driver supports.
1da177e4
LT		 457 */
458static struct pci_device_id s2io_tbl[] __devinitdata = {
459 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
460 PCI_ANY_ID, PCI_ANY_ID},
461 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
462 PCI_ANY_ID, PCI_ANY_ID},
463 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
20346722
K		 464 PCI_ANY_ID, PCI_ANY_ID},
465 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
466 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 467 {0,}
468};
469
470MODULE_DEVICE_TABLE(pci, s2io_tbl);
471
d796fdb7
LV		 472static struct pci_error_handlers s2io_err_handler = {
473 .error_detected = s2io_io_error_detected,
474 .slot_reset = s2io_io_slot_reset,
475 .resume = s2io_io_resume,
476};
477
1da177e4
LT		 478static struct pci_driver s2io_driver = {
479 .name = "S2IO",
480 .id_table = s2io_tbl,
481 .probe = s2io_init_nic,
482 .remove = __devexit_p(s2io_rem_nic),
d796fdb7 483 .err_handler = &s2io_err_handler,
1da177e4
LT		 484};
485
486/* A simplifier macro used both by init and free shared_mem Fns(). */
487#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
488
489/**
490 * init_shared_mem - Allocation and Initialization of Memory
491 * @nic: Device private variable.
20346722
K		 492 * Description: The function allocates all the memory areas shared
493 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 494 * Rx descriptors and the statistics block.
495 */
496
497static int init_shared_mem(struct s2io_nic *nic)
498{
499 u32 size;
500 void *tmp_v_addr, *tmp_v_addr_next;
501 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 502 struct RxD_block *pre_rxd_blk = NULL;
372cc597 503 int i, j, blk_cnt;
1da177e4
LT		 504 int lst_size, lst_per_page;
505 struct net_device *dev = nic->dev;
8ae418cf 506 unsigned long tmp;
1ee6dd77 507 struct buffAdd *ba;
1da177e4 508
1ee6dd77 509 struct mac_info *mac_control;
1da177e4 510 struct config_param *config;
491976b2 511 unsigned long long mem_allocated = 0;
1da177e4
LT		 512
513 mac_control = &nic->mac_control;
514 config = &nic->config;
515
516
517 /* Allocation and initialization of TXDLs in FIOFs */
518 size = 0;
519 for (i = 0; i < config->tx_fifo_num; i++) {
520 size += config->tx_cfg[i].fifo_len;
521 }
522 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 523 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
0b1f7ebe 524 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
b41477f3 525 return -EINVAL;
1da177e4
LT		 526 }
527
1ee6dd77 528 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 529 lst_per_page = PAGE_SIZE / lst_size;
530
531 for (i = 0; i < config->tx_fifo_num; i++) {
532 int fifo_len = config->tx_cfg[i].fifo_len;
1ee6dd77 533 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
20346722
K		 534 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
535 GFP_KERNEL);
536 if (!mac_control->fifos[i].list_info) {
0c61ed5f 537 DBG_PRINT(INFO_DBG,
1da177e4
LT		 538 "Malloc failed for list_info\n");
539 return -ENOMEM;
540 }
491976b2 541 mem_allocated += list_holder_size;
20346722 542 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
1da177e4
LT		 543 }
544 for (i = 0; i < config->tx_fifo_num; i++) {
545 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
546 lst_per_page);
20346722
K		 547 mac_control->fifos[i].tx_curr_put_info.offset = 0;
548 mac_control->fifos[i].tx_curr_put_info.fifo_len =
1da177e4 549 config->tx_cfg[i].fifo_len - 1;
20346722
K		 550 mac_control->fifos[i].tx_curr_get_info.offset = 0;
551 mac_control->fifos[i].tx_curr_get_info.fifo_len =
1da177e4 552 config->tx_cfg[i].fifo_len - 1;
20346722
K		 553 mac_control->fifos[i].fifo_no = i;
554 mac_control->fifos[i].nic = nic;
fed5eccd 555 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
20346722 556
1da177e4
LT		 557 for (j = 0; j < page_num; j++) {
558 int k = 0;
559 dma_addr_t tmp_p;
560 void *tmp_v;
561 tmp_v = pci_alloc_consistent(nic->pdev,
562 PAGE_SIZE, &tmp_p);
563 if (!tmp_v) {
0c61ed5f 564 DBG_PRINT(INFO_DBG,
1da177e4 565 "pci_alloc_consistent ");
0c61ed5f 566 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
1da177e4
LT		 567 return -ENOMEM;
568 }
776bd20f 569 /* If we got a zero DMA address(can happen on
570 * certain platforms like PPC), reallocate.
571 * Store virtual address of page we don't want,
572 * to be freed later.
573 */
574 if (!tmp_p) {
575 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 576 DBG_PRINT(INIT_DBG,
776bd20f 577 "%s: Zero DMA address for TxDL. ", dev->name);
6aa20a22 578 DBG_PRINT(INIT_DBG,
6b4d617d 579 "Virtual address %p\n", tmp_v);
776bd20f 580 tmp_v = pci_alloc_consistent(nic->pdev,
581 PAGE_SIZE, &tmp_p);
582 if (!tmp_v) {
0c61ed5f 583 DBG_PRINT(INFO_DBG,
776bd20f 584 "pci_alloc_consistent ");
0c61ed5f 585 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
776bd20f 586 return -ENOMEM;
587 }
491976b2 588 mem_allocated += PAGE_SIZE;
776bd20f 589 }
1da177e4
LT		 590 while (k < lst_per_page) {
591 int l = (j * lst_per_page) + k;
592 if (l == config->tx_cfg[i].fifo_len)
20346722
K		 593 break;
594 mac_control->fifos[i].list_info[l].list_virt_addr =
1da177e4 595 tmp_v + (k * lst_size);
20346722 596 mac_control->fifos[i].list_info[l].list_phy_addr =
1da177e4
LT		 597 tmp_p + (k * lst_size);
598 k++;
599 }
600 }
601 }
1da177e4 602
4384247b 603 nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
fed5eccd
AR		 604 if (!nic->ufo_in_band_v)
605 return -ENOMEM;
491976b2 606 mem_allocated += (size * sizeof(u64));
fed5eccd 607
1da177e4
LT		 608 /* Allocation and initialization of RXDs in Rings */
609 size = 0;
610 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 611 if (config->rx_cfg[i].num_rxd %
612 (rxd_count[nic->rxd_mode] + 1)) {
1da177e4
LT		 613 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
614 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
615 i);
616 DBG_PRINT(ERR_DBG, "RxDs per Block");
617 return FAILURE;
618 }
619 size += config->rx_cfg[i].num_rxd;
20346722 620 mac_control->rings[i].block_count =
da6971d8
AR		 621 config->rx_cfg[i].num_rxd /
622 (rxd_count[nic->rxd_mode] + 1 );
623 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
624 mac_control->rings[i].block_count;
1da177e4 625 }
da6971d8 626 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 627 size = (size * (sizeof(struct RxD1)));
da6971d8 628 else
1ee6dd77 629 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 630
631 for (i = 0; i < config->rx_ring_num; i++) {
20346722
K		 632 mac_control->rings[i].rx_curr_get_info.block_index = 0;
633 mac_control->rings[i].rx_curr_get_info.offset = 0;
634 mac_control->rings[i].rx_curr_get_info.ring_len =
1da177e4 635 config->rx_cfg[i].num_rxd - 1;
20346722
K		 636 mac_control->rings[i].rx_curr_put_info.block_index = 0;
637 mac_control->rings[i].rx_curr_put_info.offset = 0;
638 mac_control->rings[i].rx_curr_put_info.ring_len =
1da177e4 639 config->rx_cfg[i].num_rxd - 1;
20346722
K		 640 mac_control->rings[i].nic = nic;
641 mac_control->rings[i].ring_no = i;
642
da6971d8
AR		 643 blk_cnt = config->rx_cfg[i].num_rxd /
644 (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 645 /* Allocating all the Rx blocks */
646 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 647 struct rx_block_info *rx_blocks;
da6971d8
AR		 648 int l;
649
650 rx_blocks = &mac_control->rings[i].rx_blocks[j];
651 size = SIZE_OF_BLOCK; //size is always page size
1da177e4
LT		 652 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
653 &tmp_p_addr);
654 if (tmp_v_addr == NULL) {
655 /*
20346722
K		 656 * In case of failure, free_shared_mem()
657 * is called, which should free any
658 * memory that was alloced till the
1da177e4
LT		 659 * failure happened.
660 */
da6971d8 661 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 662 return -ENOMEM;
663 }
491976b2 664 mem_allocated += size;
1da177e4 665 memset(tmp_v_addr, 0, size);
da6971d8
AR		 666 rx_blocks->block_virt_addr = tmp_v_addr;
667 rx_blocks->block_dma_addr = tmp_p_addr;
1ee6dd77 668 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
da6971d8
AR		 669 rxd_count[nic->rxd_mode],
670 GFP_KERNEL);
372cc597
SS		 671 if (!rx_blocks->rxds)
672 return -ENOMEM;
491976b2
SH		 673 mem_allocated +=
674 (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
da6971d8
AR		 675 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
676 rx_blocks->rxds[l].virt_addr =
677 rx_blocks->block_virt_addr +
678 (rxd_size[nic->rxd_mode] * l);
679 rx_blocks->rxds[l].dma_addr =
680 rx_blocks->block_dma_addr +
681 (rxd_size[nic->rxd_mode] * l);
682 }
1da177e4
LT		 683 }
684 /* Interlinking all Rx Blocks */
685 for (j = 0; j < blk_cnt; j++) {
20346722
K		 686 tmp_v_addr =
687 mac_control->rings[i].rx_blocks[j].block_virt_addr;
1da177e4 688 tmp_v_addr_next =
20346722 689 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4 690 blk_cnt].block_virt_addr;
20346722
K		 691 tmp_p_addr =
692 mac_control->rings[i].rx_blocks[j].block_dma_addr;
1da177e4 693 tmp_p_addr_next =
20346722 694 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4
LT		 695 blk_cnt].block_dma_addr;
696
1ee6dd77 697 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
1da177e4
LT		 698 pre_rxd_blk->reserved_2_pNext_RxD_block =
699 (unsigned long) tmp_v_addr_next;
1da177e4
LT		 700 pre_rxd_blk->pNext_RxD_Blk_physical =
701 (u64) tmp_p_addr_next;
702 }
703 }
6d517a27 704 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 705 /*
706 * Allocation of Storages for buffer addresses in 2BUFF mode
707 * and the buffers as well.
708 */
709 for (i = 0; i < config->rx_ring_num; i++) {
710 blk_cnt = config->rx_cfg[i].num_rxd /
711 (rxd_count[nic->rxd_mode]+ 1);
712 mac_control->rings[i].ba =
1ee6dd77 713 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
1da177e4 714 GFP_KERNEL);
da6971d8 715 if (!mac_control->rings[i].ba)
1da177e4 716 return -ENOMEM;
491976b2 717 mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
da6971d8
AR		 718 for (j = 0; j < blk_cnt; j++) {
719 int k = 0;
720 mac_control->rings[i].ba[j] =
1ee6dd77 721 kmalloc((sizeof(struct buffAdd) *
da6971d8
AR		 722 (rxd_count[nic->rxd_mode] + 1)),
723 GFP_KERNEL);
724 if (!mac_control->rings[i].ba[j])
1da177e4 725 return -ENOMEM;
491976b2
SH		 726 mem_allocated += (sizeof(struct buffAdd) * \
727 (rxd_count[nic->rxd_mode] + 1));
da6971d8
AR		 728 while (k != rxd_count[nic->rxd_mode]) {
729 ba = &mac_control->rings[i].ba[j][k];
730
731 ba->ba_0_org = (void *) kmalloc
732 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
733 if (!ba->ba_0_org)
734 return -ENOMEM;
491976b2
SH		 735 mem_allocated +=
736 (BUF0_LEN + ALIGN_SIZE);
da6971d8
AR		 737 tmp = (unsigned long)ba->ba_0_org;
738 tmp += ALIGN_SIZE;
739 tmp &= ~((unsigned long) ALIGN_SIZE);
740 ba->ba_0 = (void *) tmp;
741
742 ba->ba_1_org = (void *) kmalloc
743 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
744 if (!ba->ba_1_org)
745 return -ENOMEM;
491976b2
SH		 746 mem_allocated
747 += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 748 tmp = (unsigned long) ba->ba_1_org;
749 tmp += ALIGN_SIZE;
750 tmp &= ~((unsigned long) ALIGN_SIZE);
751 ba->ba_1 = (void *) tmp;
752 k++;
753 }
1da177e4
LT		 754 }
755 }
756 }
1da177e4
LT		 757
758 /* Allocation and initialization of Statistics block */
1ee6dd77 759 size = sizeof(struct stat_block);
1da177e4
LT		 760 mac_control->stats_mem = pci_alloc_consistent
761 (nic->pdev, size, &mac_control->stats_mem_phy);
762
763 if (!mac_control->stats_mem) {
20346722
K		 764 /*
765 * In case of failure, free_shared_mem() is called, which
766 * should free any memory that was alloced till the
1da177e4
LT		 767 * failure happened.
768 */
769 return -ENOMEM;
770 }
491976b2 771 mem_allocated += size;
1da177e4
LT		 772 mac_control->stats_mem_sz = size;
773
774 tmp_v_addr = mac_control->stats_mem;
1ee6dd77 775 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
1da177e4 776 memset(tmp_v_addr, 0, size);
1da177e4
LT		 777 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
778 (unsigned long long) tmp_p_addr);
491976b2 779 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 780 return SUCCESS;
781}
782
20346722
K		 783/**
784 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 785 * @nic: Device private variable.
786 * Description: This function is to free all memory locations allocated by
787 * the init_shared_mem() function and return it to the kernel.
788 */
789
790static void free_shared_mem(struct s2io_nic *nic)
791{
792 int i, j, blk_cnt, size;
491976b2 793 u32 ufo_size = 0;
1da177e4
LT		 794 void *tmp_v_addr;
795 dma_addr_t tmp_p_addr;
1ee6dd77 796 struct mac_info *mac_control;
1da177e4
LT		 797 struct config_param *config;
798 int lst_size, lst_per_page;
8910b49f 799 struct net_device *dev;
491976b2 800 int page_num = 0;
1da177e4
LT		 801
802 if (!nic)
803 return;
804
8910b49f
MG		 805 dev = nic->dev;
806
1da177e4
LT		 807 mac_control = &nic->mac_control;
808 config = &nic->config;
809
1ee6dd77 810 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 811 lst_per_page = PAGE_SIZE / lst_size;
812
813 for (i = 0; i < config->tx_fifo_num; i++) {
491976b2
SH		 814 ufo_size += config->tx_cfg[i].fifo_len;
815 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
816 lst_per_page);
1da177e4
LT		 817 for (j = 0; j < page_num; j++) {
818 int mem_blks = (j * lst_per_page);
776bd20f 819 if (!mac_control->fifos[i].list_info)
6aa20a22 820 return;
776bd20f 821 if (!mac_control->fifos[i].list_info[mem_blks].
822 list_virt_addr)
1da177e4
LT		 823 break;
824 pci_free_consistent(nic->pdev, PAGE_SIZE,
20346722
K		 825 mac_control->fifos[i].
826 list_info[mem_blks].
1da177e4 827 list_virt_addr,
20346722
K		 828 mac_control->fifos[i].
829 list_info[mem_blks].
1da177e4 830 list_phy_addr);
491976b2
SH		 831 nic->mac_control.stats_info->sw_stat.mem_freed
832 += PAGE_SIZE;
1da177e4 833 }
776bd20f 834 /* If we got a zero DMA address during allocation,
835 * free the page now
836 */
837 if (mac_control->zerodma_virt_addr) {
838 pci_free_consistent(nic->pdev, PAGE_SIZE,
839 mac_control->zerodma_virt_addr,
840 (dma_addr_t)0);
6aa20a22 841 DBG_PRINT(INIT_DBG,
6b4d617d
AM		 842 "%s: Freeing TxDL with zero DMA addr. ",
843 dev->name);
844 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
845 mac_control->zerodma_virt_addr);
491976b2
SH		 846 nic->mac_control.stats_info->sw_stat.mem_freed
847 += PAGE_SIZE;
776bd20f 848 }
20346722 849 kfree(mac_control->fifos[i].list_info);
491976b2
SH		 850 nic->mac_control.stats_info->sw_stat.mem_freed +=
851 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
1da177e4
LT		 852 }
853
1da177e4 854 size = SIZE_OF_BLOCK;
1da177e4 855 for (i = 0; i < config->rx_ring_num; i++) {
20346722 856 blk_cnt = mac_control->rings[i].block_count;
1da177e4 857 for (j = 0; j < blk_cnt; j++) {
20346722
K		 858 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
859 block_virt_addr;
860 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
861 block_dma_addr;
1da177e4
LT		 862 if (tmp_v_addr == NULL)
863 break;
864 pci_free_consistent(nic->pdev, size,
865 tmp_v_addr, tmp_p_addr);
491976b2 866 nic->mac_control.stats_info->sw_stat.mem_freed += size;
da6971d8 867 kfree(mac_control->rings[i].rx_blocks[j].rxds);
491976b2
SH		 868 nic->mac_control.stats_info->sw_stat.mem_freed +=
869 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1da177e4
LT		 870 }
871 }
872
6d517a27 873 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 874 /* Freeing buffer storage addresses in 2BUFF mode. */
875 for (i = 0; i < config->rx_ring_num; i++) {
876 blk_cnt = config->rx_cfg[i].num_rxd /
877 (rxd_count[nic->rxd_mode] + 1);
878 for (j = 0; j < blk_cnt; j++) {
879 int k = 0;
880 if (!mac_control->rings[i].ba[j])
881 continue;
882 while (k != rxd_count[nic->rxd_mode]) {
1ee6dd77 883 struct buffAdd *ba =
da6971d8
AR		 884 &mac_control->rings[i].ba[j][k];
885 kfree(ba->ba_0_org);
491976b2
SH		 886 nic->mac_control.stats_info->sw_stat.\
887 mem_freed += (BUF0_LEN + ALIGN_SIZE);
da6971d8 888 kfree(ba->ba_1_org);
491976b2
SH		 889 nic->mac_control.stats_info->sw_stat.\
890 mem_freed += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 891 k++;
892 }
893 kfree(mac_control->rings[i].ba[j]);
491976b2
SH		 894 nic->mac_control.stats_info->sw_stat.mem_freed += (sizeof(struct buffAdd) *
895 (rxd_count[nic->rxd_mode] + 1));
1da177e4 896 }
da6971d8 897 kfree(mac_control->rings[i].ba);
491976b2
SH		 898 nic->mac_control.stats_info->sw_stat.mem_freed +=
899 (sizeof(struct buffAdd *) * blk_cnt);
1da177e4 900 }
1da177e4 901 }
1da177e4
LT		 902
903 if (mac_control->stats_mem) {
904 pci_free_consistent(nic->pdev,
905 mac_control->stats_mem_sz,
906 mac_control->stats_mem,
907 mac_control->stats_mem_phy);
491976b2
SH		 908 nic->mac_control.stats_info->sw_stat.mem_freed +=
909 mac_control->stats_mem_sz;
1da177e4 910 }
491976b2 911 if (nic->ufo_in_band_v) {
fed5eccd 912 kfree(nic->ufo_in_band_v);
491976b2
SH		 913 nic->mac_control.stats_info->sw_stat.mem_freed
914 += (ufo_size * sizeof(u64));
915 }
1da177e4
LT		 916}
917
541ae68f
K		 918/**
919 * s2io_verify_pci_mode -
920 */
921
1ee6dd77 922static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 923{
1ee6dd77 924 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 925 register u64 val64 = 0;
926 int mode;
927
928 val64 = readq(&bar0->pci_mode);
929 mode = (u8)GET_PCI_MODE(val64);
930
931 if ( val64 & PCI_MODE_UNKNOWN_MODE)
932 return -1; /* Unknown PCI mode */
933 return mode;
934}
935
c92ca04b
AR		 936#define NEC_VENID 0x1033
937#define NEC_DEVID 0x0125
938static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
939{
940 struct pci_dev *tdev = NULL;
26d36b64
AC		 941 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
942 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
c92ca04b 943 if (tdev->bus == s2io_pdev->bus->parent)
26d36b64 944 pci_dev_put(tdev);
c92ca04b
AR		 945 return 1;
946 }
947 }
948 return 0;
949}
541ae68f 950
7b32a312 951static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f
K		 952/**
953 * s2io_print_pci_mode -
954 */
1ee6dd77 955static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 956{
1ee6dd77 957 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 958 register u64 val64 = 0;
959 int mode;
960 struct config_param *config = &nic->config;
961
962 val64 = readq(&bar0->pci_mode);
963 mode = (u8)GET_PCI_MODE(val64);
964
965 if ( val64 & PCI_MODE_UNKNOWN_MODE)
966 return -1; /* Unknown PCI mode */
967
c92ca04b
AR		 968 config->bus_speed = bus_speed[mode];
969
970 if (s2io_on_nec_bridge(nic->pdev)) {
971 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
972 nic->dev->name);
973 return mode;
974 }
975
541ae68f
K		 976 if (val64 & PCI_MODE_32_BITS) {
977 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
978 } else {
979 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
980 }
981
982 switch(mode) {
983 case PCI_MODE_PCI_33:
984 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
541ae68f
K		 985 break;
986 case PCI_MODE_PCI_66:
987 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
541ae68f
K		 988 break;
989 case PCI_MODE_PCIX_M1_66:
990 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
541ae68f
K		 991 break;
992 case PCI_MODE_PCIX_M1_100:
993 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
541ae68f
K		 994 break;
995 case PCI_MODE_PCIX_M1_133:
996 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
541ae68f
K		 997 break;
998 case PCI_MODE_PCIX_M2_66:
999 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
541ae68f
K		 1000 break;
1001 case PCI_MODE_PCIX_M2_100:
1002 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
541ae68f
K		 1003 break;
1004 case PCI_MODE_PCIX_M2_133:
1005 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
541ae68f
K		 1006 break;
1007 default:
1008 return -1; /* Unsupported bus speed */
1009 }
1010
1011 return mode;
1012}
1013
20346722
K		 1014/**
1015 * init_nic - Initialization of hardware
1da177e4 1016 * @nic: device peivate variable
20346722
K		 1017 * Description: The function sequentially configures every block
1018 * of the H/W from their reset values.
1019 * Return Value: SUCCESS on success and
1da177e4
LT		 1020 * '-1' on failure (endian settings incorrect).
1021 */
1022
1023static int init_nic(struct s2io_nic *nic)
1024{
1ee6dd77 1025 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1026 struct net_device *dev = nic->dev;
1027 register u64 val64 = 0;
1028 void __iomem *add;
1029 u32 time;
1030 int i, j;
1ee6dd77 1031 struct mac_info *mac_control;
1da177e4 1032 struct config_param *config;
c92ca04b 1033 int dtx_cnt = 0;
1da177e4 1034 unsigned long long mem_share;
20346722 1035 int mem_size;
1da177e4
LT		 1036
1037 mac_control = &nic->mac_control;
1038 config = &nic->config;
1039
5e25b9dd 1040 /* to set the swapper controle on the card */
20346722 1041 if(s2io_set_swapper(nic)) {
1da177e4
LT		 1042 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1043 return -1;
1044 }
1045
541ae68f
K		 1046 /*
1047 * Herc requires EOI to be removed from reset before XGXS, so..
1048 */
1049 if (nic->device_type & XFRAME_II_DEVICE) {
1050 val64 = 0xA500000000ULL;
1051 writeq(val64, &bar0->sw_reset);
1052 msleep(500);
1053 val64 = readq(&bar0->sw_reset);
1054 }
1055
1da177e4
LT		 1056 /* Remove XGXS from reset state */
1057 val64 = 0;
1058 writeq(val64, &bar0->sw_reset);
1da177e4 1059 msleep(500);
20346722 1060 val64 = readq(&bar0->sw_reset);
1da177e4
LT		 1061
1062 /* Enable Receiving broadcasts */
1063 add = &bar0->mac_cfg;
1064 val64 = readq(&bar0->mac_cfg);
1065 val64 |= MAC_RMAC_BCAST_ENABLE;
1066 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1067 writel((u32) val64, add);
1068 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1069 writel((u32) (val64 >> 32), (add + 4));
1070
1071 /* Read registers in all blocks */
1072 val64 = readq(&bar0->mac_int_mask);
1073 val64 = readq(&bar0->mc_int_mask);
1074 val64 = readq(&bar0->xgxs_int_mask);
1075
1076 /* Set MTU */
1077 val64 = dev->mtu;
1078 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1079
541ae68f
K		 1080 if (nic->device_type & XFRAME_II_DEVICE) {
1081 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1082 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1083 &bar0->dtx_control, UF);
541ae68f
K		 1084 if (dtx_cnt & 0x1)
1085 msleep(1); /* Necessary!! */
1da177e4
LT		 1086 dtx_cnt++;
1087 }
541ae68f 1088 } else {
c92ca04b
AR		 1089 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1090 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1091 &bar0->dtx_control, UF);
1092 val64 = readq(&bar0->dtx_control);
1093 dtx_cnt++;
1da177e4
LT		 1094 }
1095 }
1096
1097 /* Tx DMA Initialization */
1098 val64 = 0;
1099 writeq(val64, &bar0->tx_fifo_partition_0);
1100 writeq(val64, &bar0->tx_fifo_partition_1);
1101 writeq(val64, &bar0->tx_fifo_partition_2);
1102 writeq(val64, &bar0->tx_fifo_partition_3);
1103
1104
1105 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1106 val64 |=
1107 vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1108 13) | vBIT(config->tx_cfg[i].fifo_priority,
1109 ((i * 32) + 5), 3);
1110
1111 if (i == (config->tx_fifo_num - 1)) {
1112 if (i % 2 == 0)
1113 i++;
1114 }
1115
1116 switch (i) {
1117 case 1:
1118 writeq(val64, &bar0->tx_fifo_partition_0);
1119 val64 = 0;
1120 break;
1121 case 3:
1122 writeq(val64, &bar0->tx_fifo_partition_1);
1123 val64 = 0;
1124 break;
1125 case 5:
1126 writeq(val64, &bar0->tx_fifo_partition_2);
1127 val64 = 0;
1128 break;
1129 case 7:
1130 writeq(val64, &bar0->tx_fifo_partition_3);
1131 break;
1132 }
1133 }
1134
5e25b9dd
K		 1135 /*
1136 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1137 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1138 */
541ae68f 1139 if ((nic->device_type == XFRAME_I_DEVICE) &&
44c10138 1140 (nic->pdev->revision < 4))
5e25b9dd
K		 1141 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1142
1da177e4
LT		 1143 val64 = readq(&bar0->tx_fifo_partition_0);
1144 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1145 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1146
20346722
K		 1147 /*
1148 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1149 * integrity checking.
1150 */
1151 val64 = readq(&bar0->tx_pa_cfg);
1152 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1153 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1154 writeq(val64, &bar0->tx_pa_cfg);
1155
1156 /* Rx DMA intialization. */
1157 val64 = 0;
1158 for (i = 0; i < config->rx_ring_num; i++) {
1159 val64 |=
1160 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1161 3);
1162 }
1163 writeq(val64, &bar0->rx_queue_priority);
1164
20346722
K		 1165 /*
1166 * Allocating equal share of memory to all the
1da177e4
LT		 1167 * configured Rings.
1168 */
1169 val64 = 0;
541ae68f
K		 1170 if (nic->device_type & XFRAME_II_DEVICE)
1171 mem_size = 32;
1172 else
1173 mem_size = 64;
1174
1da177e4
LT		 1175 for (i = 0; i < config->rx_ring_num; i++) {
1176 switch (i) {
1177 case 0:
20346722
K		 1178 mem_share = (mem_size / config->rx_ring_num +
1179 mem_size % config->rx_ring_num);
1da177e4
LT		 1180 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1181 continue;
1182 case 1:
20346722 1183 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1184 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1185 continue;
1186 case 2:
20346722 1187 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1188 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1189 continue;
1190 case 3:
20346722 1191 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1192 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1193 continue;
1194 case 4:
20346722 1195 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1196 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1197 continue;
1198 case 5:
20346722 1199 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1200 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1201 continue;
1202 case 6:
20346722 1203 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1204 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1205 continue;
1206 case 7:
20346722 1207 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1208 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1209 continue;
1210 }
1211 }
1212 writeq(val64, &bar0->rx_queue_cfg);
1213
20346722 1214 /*
5e25b9dd
K		 1215 * Filling Tx round robin registers
1216 * as per the number of FIFOs
1da177e4 1217 */
5e25b9dd
K		 1218 switch (config->tx_fifo_num) {
1219 case 1:
1220 val64 = 0x0000000000000000ULL;
1221 writeq(val64, &bar0->tx_w_round_robin_0);
1222 writeq(val64, &bar0->tx_w_round_robin_1);
1223 writeq(val64, &bar0->tx_w_round_robin_2);
1224 writeq(val64, &bar0->tx_w_round_robin_3);
1225 writeq(val64, &bar0->tx_w_round_robin_4);
1226 break;
1227 case 2:
1228 val64 = 0x0000010000010000ULL;
1229 writeq(val64, &bar0->tx_w_round_robin_0);
1230 val64 = 0x0100000100000100ULL;
1231 writeq(val64, &bar0->tx_w_round_robin_1);
1232 val64 = 0x0001000001000001ULL;
1233 writeq(val64, &bar0->tx_w_round_robin_2);
1234 val64 = 0x0000010000010000ULL;
1235 writeq(val64, &bar0->tx_w_round_robin_3);
1236 val64 = 0x0100000000000000ULL;
1237 writeq(val64, &bar0->tx_w_round_robin_4);
1238 break;
1239 case 3:
1240 val64 = 0x0001000102000001ULL;
1241 writeq(val64, &bar0->tx_w_round_robin_0);
1242 val64 = 0x0001020000010001ULL;
1243 writeq(val64, &bar0->tx_w_round_robin_1);
1244 val64 = 0x0200000100010200ULL;
1245 writeq(val64, &bar0->tx_w_round_robin_2);
1246 val64 = 0x0001000102000001ULL;
1247 writeq(val64, &bar0->tx_w_round_robin_3);
1248 val64 = 0x0001020000000000ULL;
1249 writeq(val64, &bar0->tx_w_round_robin_4);
1250 break;
1251 case 4:
1252 val64 = 0x0001020300010200ULL;
1253 writeq(val64, &bar0->tx_w_round_robin_0);
1254 val64 = 0x0100000102030001ULL;
1255 writeq(val64, &bar0->tx_w_round_robin_1);
1256 val64 = 0x0200010000010203ULL;
1257 writeq(val64, &bar0->tx_w_round_robin_2);
1258 val64 = 0x0001020001000001ULL;
1259 writeq(val64, &bar0->tx_w_round_robin_3);
1260 val64 = 0x0203000100000000ULL;
1261 writeq(val64, &bar0->tx_w_round_robin_4);
1262 break;
1263 case 5:
1264 val64 = 0x0001000203000102ULL;
1265 writeq(val64, &bar0->tx_w_round_robin_0);
1266 val64 = 0x0001020001030004ULL;
1267 writeq(val64, &bar0->tx_w_round_robin_1);
1268 val64 = 0x0001000203000102ULL;
1269 writeq(val64, &bar0->tx_w_round_robin_2);
1270 val64 = 0x0001020001030004ULL;
1271 writeq(val64, &bar0->tx_w_round_robin_3);
1272 val64 = 0x0001000000000000ULL;
1273 writeq(val64, &bar0->tx_w_round_robin_4);
1274 break;
1275 case 6:
1276 val64 = 0x0001020304000102ULL;
1277 writeq(val64, &bar0->tx_w_round_robin_0);
1278 val64 = 0x0304050001020001ULL;
1279 writeq(val64, &bar0->tx_w_round_robin_1);
1280 val64 = 0x0203000100000102ULL;
1281 writeq(val64, &bar0->tx_w_round_robin_2);
1282 val64 = 0x0304000102030405ULL;
1283 writeq(val64, &bar0->tx_w_round_robin_3);
1284 val64 = 0x0001000200000000ULL;
1285 writeq(val64, &bar0->tx_w_round_robin_4);
1286 break;
1287 case 7:
1288 val64 = 0x0001020001020300ULL;
1289 writeq(val64, &bar0->tx_w_round_robin_0);
1290 val64 = 0x0102030400010203ULL;
1291 writeq(val64, &bar0->tx_w_round_robin_1);
1292 val64 = 0x0405060001020001ULL;
1293 writeq(val64, &bar0->tx_w_round_robin_2);
1294 val64 = 0x0304050000010200ULL;
1295 writeq(val64, &bar0->tx_w_round_robin_3);
1296 val64 = 0x0102030000000000ULL;
1297 writeq(val64, &bar0->tx_w_round_robin_4);
1298 break;
1299 case 8:
1300 val64 = 0x0001020300040105ULL;
1301 writeq(val64, &bar0->tx_w_round_robin_0);
1302 val64 = 0x0200030106000204ULL;
1303 writeq(val64, &bar0->tx_w_round_robin_1);
1304 val64 = 0x0103000502010007ULL;
1305 writeq(val64, &bar0->tx_w_round_robin_2);
1306 val64 = 0x0304010002060500ULL;
1307 writeq(val64, &bar0->tx_w_round_robin_3);
1308 val64 = 0x0103020400000000ULL;
1309 writeq(val64, &bar0->tx_w_round_robin_4);
1310 break;
1311 }
1312
b41477f3 1313 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1314 val64 = readq(&bar0->tx_fifo_partition_0);
1315 val64 |= (TX_FIFO_PARTITION_EN);
1316 writeq(val64, &bar0->tx_fifo_partition_0);
1317
5e25b9dd
K		 1318 /* Filling the Rx round robin registers as per the
1319 * number of Rings and steering based on QoS.
1320 */
1321 switch (config->rx_ring_num) {
1322 case 1:
1323 val64 = 0x8080808080808080ULL;
1324 writeq(val64, &bar0->rts_qos_steering);
1325 break;
1326 case 2:
1327 val64 = 0x0000010000010000ULL;
1328 writeq(val64, &bar0->rx_w_round_robin_0);
1329 val64 = 0x0100000100000100ULL;
1330 writeq(val64, &bar0->rx_w_round_robin_1);
1331 val64 = 0x0001000001000001ULL;
1332 writeq(val64, &bar0->rx_w_round_robin_2);
1333 val64 = 0x0000010000010000ULL;
1334 writeq(val64, &bar0->rx_w_round_robin_3);
1335 val64 = 0x0100000000000000ULL;
1336 writeq(val64, &bar0->rx_w_round_robin_4);
1337
1338 val64 = 0x8080808040404040ULL;
1339 writeq(val64, &bar0->rts_qos_steering);
1340 break;
1341 case 3:
1342 val64 = 0x0001000102000001ULL;
1343 writeq(val64, &bar0->rx_w_round_robin_0);
1344 val64 = 0x0001020000010001ULL;
1345 writeq(val64, &bar0->rx_w_round_robin_1);
1346 val64 = 0x0200000100010200ULL;
1347 writeq(val64, &bar0->rx_w_round_robin_2);
1348 val64 = 0x0001000102000001ULL;
1349 writeq(val64, &bar0->rx_w_round_robin_3);
1350 val64 = 0x0001020000000000ULL;
1351 writeq(val64, &bar0->rx_w_round_robin_4);
1352
1353 val64 = 0x8080804040402020ULL;
1354 writeq(val64, &bar0->rts_qos_steering);
1355 break;
1356 case 4:
1357 val64 = 0x0001020300010200ULL;
1358 writeq(val64, &bar0->rx_w_round_robin_0);
1359 val64 = 0x0100000102030001ULL;
1360 writeq(val64, &bar0->rx_w_round_robin_1);
1361 val64 = 0x0200010000010203ULL;
1362 writeq(val64, &bar0->rx_w_round_robin_2);
6aa20a22 1363 val64 = 0x0001020001000001ULL;
5e25b9dd
K		 1364 writeq(val64, &bar0->rx_w_round_robin_3);
1365 val64 = 0x0203000100000000ULL;
1366 writeq(val64, &bar0->rx_w_round_robin_4);
1367
1368 val64 = 0x8080404020201010ULL;
1369 writeq(val64, &bar0->rts_qos_steering);
1370 break;
1371 case 5:
1372 val64 = 0x0001000203000102ULL;
1373 writeq(val64, &bar0->rx_w_round_robin_0);
1374 val64 = 0x0001020001030004ULL;
1375 writeq(val64, &bar0->rx_w_round_robin_1);
1376 val64 = 0x0001000203000102ULL;
1377 writeq(val64, &bar0->rx_w_round_robin_2);
1378 val64 = 0x0001020001030004ULL;
1379 writeq(val64, &bar0->rx_w_round_robin_3);
1380 val64 = 0x0001000000000000ULL;
1381 writeq(val64, &bar0->rx_w_round_robin_4);
1382
1383 val64 = 0x8080404020201008ULL;
1384 writeq(val64, &bar0->rts_qos_steering);
1385 break;
1386 case 6:
1387 val64 = 0x0001020304000102ULL;
1388 writeq(val64, &bar0->rx_w_round_robin_0);
1389 val64 = 0x0304050001020001ULL;
1390 writeq(val64, &bar0->rx_w_round_robin_1);
1391 val64 = 0x0203000100000102ULL;
1392 writeq(val64, &bar0->rx_w_round_robin_2);
1393 val64 = 0x0304000102030405ULL;
1394 writeq(val64, &bar0->rx_w_round_robin_3);
1395 val64 = 0x0001000200000000ULL;
1396 writeq(val64, &bar0->rx_w_round_robin_4);
1397
1398 val64 = 0x8080404020100804ULL;
1399 writeq(val64, &bar0->rts_qos_steering);
1400 break;
1401 case 7:
1402 val64 = 0x0001020001020300ULL;
1403 writeq(val64, &bar0->rx_w_round_robin_0);
1404 val64 = 0x0102030400010203ULL;
1405 writeq(val64, &bar0->rx_w_round_robin_1);
1406 val64 = 0x0405060001020001ULL;
1407 writeq(val64, &bar0->rx_w_round_robin_2);
1408 val64 = 0x0304050000010200ULL;
1409 writeq(val64, &bar0->rx_w_round_robin_3);
1410 val64 = 0x0102030000000000ULL;
1411 writeq(val64, &bar0->rx_w_round_robin_4);
1412
1413 val64 = 0x8080402010080402ULL;
1414 writeq(val64, &bar0->rts_qos_steering);
1415 break;
1416 case 8:
1417 val64 = 0x0001020300040105ULL;
1418 writeq(val64, &bar0->rx_w_round_robin_0);
1419 val64 = 0x0200030106000204ULL;
1420 writeq(val64, &bar0->rx_w_round_robin_1);
1421 val64 = 0x0103000502010007ULL;
1422 writeq(val64, &bar0->rx_w_round_robin_2);
1423 val64 = 0x0304010002060500ULL;
1424 writeq(val64, &bar0->rx_w_round_robin_3);
1425 val64 = 0x0103020400000000ULL;
1426 writeq(val64, &bar0->rx_w_round_robin_4);
1427
1428 val64 = 0x8040201008040201ULL;
1429 writeq(val64, &bar0->rts_qos_steering);
1430 break;
1431 }
1da177e4
LT		 1432
1433 /* UDP Fix */
1434 val64 = 0;
20346722 1435 for (i = 0; i < 8; i++)
1da177e4
LT		 1436 writeq(val64, &bar0->rts_frm_len_n[i]);
1437
5e25b9dd
K		 1438 /* Set the default rts frame length for the rings configured */
1439 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1440 for (i = 0 ; i < config->rx_ring_num ; i++)
1441 writeq(val64, &bar0->rts_frm_len_n[i]);
1442
1443 /* Set the frame length for the configured rings
1444 * desired by the user
1445 */
1446 for (i = 0; i < config->rx_ring_num; i++) {
1447 /* If rts_frm_len[i] == 0 then it is assumed that user not
1448 * specified frame length steering.
1449 * If the user provides the frame length then program
1450 * the rts_frm_len register for those values or else
1451 * leave it as it is.
1452 */
1453 if (rts_frm_len[i] != 0) {
1454 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1455 &bar0->rts_frm_len_n[i]);
1456 }
1457 }
926930b2 1458
9fc93a41
SS		 1459 /* Disable differentiated services steering logic */
1460 for (i = 0; i < 64; i++) {
1461 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1462 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1463 dev->name);
1464 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1465 return FAILURE;
1466 }
1467 }
1468
20346722 1469 /* Program statistics memory */
1da177e4 1470 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1471
541ae68f
K		 1472 if (nic->device_type == XFRAME_II_DEVICE) {
1473 val64 = STAT_BC(0x320);
1474 writeq(val64, &bar0->stat_byte_cnt);
1475 }
1476
20346722 1477 /*
1da177e4
LT		 1478 * Initializing the sampling rate for the device to calculate the
1479 * bandwidth utilization.
1480 */
1481 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1482 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1483 writeq(val64, &bar0->mac_link_util);
1484
1485
20346722
K		 1486 /*
1487 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1488 * Scheme.
1489 */
20346722
K		 1490 /*
1491 * TTI Initialization. Default Tx timer gets us about
1da177e4
LT		 1492 * 250 interrupts per sec. Continuous interrupts are enabled
1493 * by default.
1494 */
541ae68f
K		 1495 if (nic->device_type == XFRAME_II_DEVICE) {
1496 int count = (nic->config.bus_speed * 125)/2;
1497 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1498 } else {
1499
1500 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1501 }
1502 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1da177e4 1503 TTI_DATA1_MEM_TX_URNG_B(0x10) |
5e25b9dd 1504 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
541ae68f
K		 1505 if (use_continuous_tx_intrs)
1506 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1da177e4
LT		 1507 writeq(val64, &bar0->tti_data1_mem);
1508
1509 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1510 TTI_DATA2_MEM_TX_UFC_B(0x20) |
19a60522 1511 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1da177e4
LT		 1512 writeq(val64, &bar0->tti_data2_mem);
1513
1514 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1515 writeq(val64, &bar0->tti_command_mem);
1516
20346722 1517 /*
1da177e4
LT		 1518 * Once the operation completes, the Strobe bit of the command
1519 * register will be reset. We poll for this particular condition
1520 * We wait for a maximum of 500ms for the operation to complete,
1521 * if it's not complete by then we return error.
1522 */
1523 time = 0;
1524 while (TRUE) {
1525 val64 = readq(&bar0->tti_command_mem);
1526 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1527 break;
1528 }
1529 if (time > 10) {
1530 DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1531 dev->name);
1532 return -1;
1533 }
1534 msleep(50);
1535 time++;
1536 }
1537
b6e3f982
K		 1538 if (nic->config.bimodal) {
1539 int k = 0;
1540 for (k = 0; k < config->rx_ring_num; k++) {
1541 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1542 val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1543 writeq(val64, &bar0->tti_command_mem);
541ae68f 1544
541ae68f 1545 /*
b6e3f982
K		 1546 * Once the operation completes, the Strobe bit of the command
1547 * register will be reset. We poll for this particular condition
1548 * We wait for a maximum of 500ms for the operation to complete,
1549 * if it's not complete by then we return error.
1550 */
1551 time = 0;
1552 while (TRUE) {
1553 val64 = readq(&bar0->tti_command_mem);
1554 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1555 break;
1556 }
1557 if (time > 10) {
1558 DBG_PRINT(ERR_DBG,
1559 "%s: TTI init Failed\n",
1560 dev->name);
1561 return -1;
1562 }
1563 time++;
1564 msleep(50);
1565 }
1566 }
541ae68f 1567 } else {
1da177e4 1568
b6e3f982
K		 1569 /* RTI Initialization */
1570 if (nic->device_type == XFRAME_II_DEVICE) {
1571 /*
1572 * Programmed to generate Apprx 500 Intrs per
1573 * second
1574 */
1575 int count = (nic->config.bus_speed * 125)/4;
1576 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1577 } else {
1578 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1579 }
1580 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1581 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1582 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1da177e4 1583
b6e3f982 1584 writeq(val64, &bar0->rti_data1_mem);
1da177e4 1585
b6e3f982 1586 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
cc6e7c44
RA		 1587 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1588 if (nic->intr_type == MSI_X)
1589 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1590 RTI_DATA2_MEM_RX_UFC_D(0x40));
1591 else
1592 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1593 RTI_DATA2_MEM_RX_UFC_D(0x80));
b6e3f982 1594 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1595
b6e3f982
K		 1596 for (i = 0; i < config->rx_ring_num; i++) {
1597 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1598 | RTI_CMD_MEM_OFFSET(i);
1599 writeq(val64, &bar0->rti_command_mem);
1600
1601 /*
1602 * Once the operation completes, the Strobe bit of the
1603 * command register will be reset. We poll for this
1604 * particular condition. We wait for a maximum of 500ms
1605 * for the operation to complete, if it's not complete
1606 * by then we return error.
1607 */
1608 time = 0;
1609 while (TRUE) {
1610 val64 = readq(&bar0->rti_command_mem);
1611 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1612 break;
1613 }
1614 if (time > 10) {
1615 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1616 dev->name);
1617 return -1;
1618 }
1619 time++;
1620 msleep(50);
1621 }
1da177e4 1622 }
1da177e4
LT		 1623 }
1624
20346722
K		 1625 /*
1626 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1627 * the 8 Queues on Rx side.
1628 */
1629 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1630 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1631
1632 /* Disable RMAC PAD STRIPPING */
509a2671 1633 add = &bar0->mac_cfg;
1da177e4
LT		 1634 val64 = readq(&bar0->mac_cfg);
1635 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1636 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1637 writel((u32) (val64), add);
1638 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1639 writel((u32) (val64 >> 32), (add + 4));
1640 val64 = readq(&bar0->mac_cfg);
1641
7d3d0439
RA		 1642 /* Enable FCS stripping by adapter */
1643 add = &bar0->mac_cfg;
1644 val64 = readq(&bar0->mac_cfg);
1645 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1646 if (nic->device_type == XFRAME_II_DEVICE)
1647 writeq(val64, &bar0->mac_cfg);
1648 else {
1649 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1650 writel((u32) (val64), add);
1651 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1652 writel((u32) (val64 >> 32), (add + 4));
1653 }
1654
20346722
K		 1655 /*
1656 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1657 * generated by xena.
1658 */
1659 val64 = readq(&bar0->rmac_pause_cfg);
1660 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1661 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1662 writeq(val64, &bar0->rmac_pause_cfg);
1663
20346722 1664 /*
1da177e4
LT		 1665 * Set the Threshold Limit for Generating the pause frame
1666 * If the amount of data in any Queue exceeds ratio of
1667 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1668 * pause frame is generated
1669 */
1670 val64 = 0;
1671 for (i = 0; i < 4; i++) {
1672 val64 |=
1673 (((u64) 0xFF00 | nic->mac_control.
1674 mc_pause_threshold_q0q3)
1675 << (i * 2 * 8));
1676 }
1677 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1678
1679 val64 = 0;
1680 for (i = 0; i < 4; i++) {
1681 val64 |=
1682 (((u64) 0xFF00 | nic->mac_control.
1683 mc_pause_threshold_q4q7)
1684 << (i * 2 * 8));
1685 }
1686 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1687
20346722
K		 1688 /*
1689 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1690 * exceeded the limit pointed by shared_splits
1691 */
1692 val64 = readq(&bar0->pic_control);
1693 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1694 writeq(val64, &bar0->pic_control);
1695
863c11a9
AR		 1696 if (nic->config.bus_speed == 266) {
1697 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1698 writeq(0x0, &bar0->read_retry_delay);
1699 writeq(0x0, &bar0->write_retry_delay);
1700 }
1701
541ae68f
K		 1702 /*
1703 * Programming the Herc to split every write transaction
1704 * that does not start on an ADB to reduce disconnects.
1705 */
1706 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1707 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1708 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1709 writeq(val64, &bar0->misc_control);
1710 val64 = readq(&bar0->pic_control2);
1711 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1712 writeq(val64, &bar0->pic_control2);
541ae68f 1713 }
c92ca04b
AR		 1714 if (strstr(nic->product_name, "CX4")) {
1715 val64 = TMAC_AVG_IPG(0x17);
1716 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d
K		 1717 }
1718
1da177e4
LT		 1719 return SUCCESS;
1720}
a371a07d
K		 1721#define LINK_UP_DOWN_INTERRUPT 1
1722#define MAC_RMAC_ERR_TIMER 2
1723
1ee6dd77 1724static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d 1725{
cc6e7c44
RA		 1726 if (nic->intr_type != INTA)
1727 return MAC_RMAC_ERR_TIMER;
a371a07d
K		 1728 if (nic->device_type == XFRAME_II_DEVICE)
1729 return LINK_UP_DOWN_INTERRUPT;
1730 else
1731 return MAC_RMAC_ERR_TIMER;
1732}
1da177e4 1733
20346722
K		 1734/**
1735 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 1736 * @nic: device private variable,
1737 * @mask: A mask indicating which Intr block must be modified and,
1738 * @flag: A flag indicating whether to enable or disable the Intrs.
1739 * Description: This function will either disable or enable the interrupts
20346722
K		 1740 * depending on the flag argument. The mask argument can be used to
1741 * enable/disable any Intr block.
1da177e4
LT		 1742 * Return Value: NONE.
1743 */
1744
1745static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1746{
1ee6dd77 1747 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1748 register u64 val64 = 0, temp64 = 0;
1749
1750 /* Top level interrupt classification */
1751 /* PIC Interrupts */
1752 if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1753 /* Enable PIC Intrs in the general intr mask register */
a113ae06 1754 val64 = TXPIC_INT_M;
1da177e4
LT		 1755 if (flag == ENABLE_INTRS) {
1756 temp64 = readq(&bar0->general_int_mask);
1757 temp64 &= ~((u64) val64);
1758 writeq(temp64, &bar0->general_int_mask);
20346722 1759 /*
a371a07d 1760 * If Hercules adapter enable GPIO otherwise
b41477f3 1761 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722
K		 1762 * interrupts for now.
1763 * TODO
1da177e4 1764 */
a371a07d
K		 1765 if (s2io_link_fault_indication(nic) ==
1766 LINK_UP_DOWN_INTERRUPT ) {
1767 temp64 = readq(&bar0->pic_int_mask);
1768 temp64 &= ~((u64) PIC_INT_GPIO);
1769 writeq(temp64, &bar0->pic_int_mask);
1770 temp64 = readq(&bar0->gpio_int_mask);
1771 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1772 writeq(temp64, &bar0->gpio_int_mask);
1773 } else {
1774 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1775 }
20346722 1776 /*
1da177e4
LT		 1777 * No MSI Support is available presently, so TTI and
1778 * RTI interrupts are also disabled.
1779 */
1780 } else if (flag == DISABLE_INTRS) {
20346722
K		 1781 /*
1782 * Disable PIC Intrs in the general
1783 * intr mask register
1da177e4
LT		 1784 */
1785 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1786 temp64 = readq(&bar0->general_int_mask);
1787 val64 |= temp64;
1788 writeq(val64, &bar0->general_int_mask);
1789 }
1790 }
1791
1da177e4
LT		 1792 /* MAC Interrupts */
1793 /* Enabling/Disabling MAC interrupts */
1794 if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1795 val64 = TXMAC_INT_M | RXMAC_INT_M;
1796 if (flag == ENABLE_INTRS) {
1797 temp64 = readq(&bar0->general_int_mask);
1798 temp64 &= ~((u64) val64);
1799 writeq(temp64, &bar0->general_int_mask);
20346722
K		 1800 /*
1801 * All MAC block error interrupts are disabled for now
1da177e4
LT		 1802 * TODO
1803 */
1da177e4 1804 } else if (flag == DISABLE_INTRS) {
20346722
K		 1805 /*
1806 * Disable MAC Intrs in the general intr mask register
1da177e4
LT		 1807 */
1808 writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1809 writeq(DISABLE_ALL_INTRS,
1810 &bar0->mac_rmac_err_mask);
1811
1812 temp64 = readq(&bar0->general_int_mask);
1813 val64 |= temp64;
1814 writeq(val64, &bar0->general_int_mask);
1815 }
1816 }
1817
1da177e4
LT		 1818 /* Tx traffic interrupts */
1819 if (mask & TX_TRAFFIC_INTR) {
1820 val64 = TXTRAFFIC_INT_M;
1821 if (flag == ENABLE_INTRS) {
1822 temp64 = readq(&bar0->general_int_mask);
1823 temp64 &= ~((u64) val64);
1824 writeq(temp64, &bar0->general_int_mask);
20346722 1825 /*
1da177e4 1826 * Enable all the Tx side interrupts
20346722 1827 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 1828 */
1829 writeq(0x0, &bar0->tx_traffic_mask);
1830 } else if (flag == DISABLE_INTRS) {
20346722
K		 1831 /*
1832 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 1833 * register.
1834 */
1835 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1836 temp64 = readq(&bar0->general_int_mask);
1837 val64 |= temp64;
1838 writeq(val64, &bar0->general_int_mask);
1839 }
1840 }
1841
1842 /* Rx traffic interrupts */
1843 if (mask & RX_TRAFFIC_INTR) {
1844 val64 = RXTRAFFIC_INT_M;
1845 if (flag == ENABLE_INTRS) {
1846 temp64 = readq(&bar0->general_int_mask);
1847 temp64 &= ~((u64) val64);
1848 writeq(temp64, &bar0->general_int_mask);
1849 /* writing 0 Enables all 8 RX interrupt levels */
1850 writeq(0x0, &bar0->rx_traffic_mask);
1851 } else if (flag == DISABLE_INTRS) {
20346722
K		 1852 /*
1853 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 1854 * register.
1855 */
1856 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1857 temp64 = readq(&bar0->general_int_mask);
1858 val64 |= temp64;
1859 writeq(val64, &bar0->general_int_mask);
1860 }
1861 }
1862}
1863
19a60522
SS		 1864/**
1865 * verify_pcc_quiescent- Checks for PCC quiescent state
1866 * Return: 1 If PCC is quiescence
1867 * 0 If PCC is not quiescence
1868 */
1ee6dd77 1869static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 1870{
19a60522 1871 int ret = 0, herc;
1ee6dd77 1872 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 1873 u64 val64 = readq(&bar0->adapter_status);
1874
1875 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722
K		 1876
1877 if (flag == FALSE) {
44c10138 1878 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 1879 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 1880 ret = 1;
19a60522
SS		 1881 } else {
1882 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 1883 ret = 1;
20346722
K		 1884 }
1885 } else {
44c10138 1886 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 1887 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 1888 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 1889 ret = 1;
5e25b9dd
K		 1890 } else {
1891 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 1892 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 1893 ret = 1;
20346722
K		 1894 }
1895 }
1896
1897 return ret;
1898}
1899/**
1900 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 1901 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 1902 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 1903 * differs and the calling function passes the input argument flag to
1904 * indicate this.
20346722 1905 * Return: 1 If xena is quiescence
1da177e4
LT		 1906 * 0 If Xena is not quiescence
1907 */
1908
1ee6dd77 1909static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 1910{
19a60522 1911 int mode;
1ee6dd77 1912 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 1913 u64 val64 = readq(&bar0->adapter_status);
1914 mode = s2io_verify_pci_mode(sp);
1da177e4 1915
19a60522
SS		 1916 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
1917 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
1918 return 0;
1919 }
1920 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
1921 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
1922 return 0;
1923 }
1924 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
1925 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
1926 return 0;
1927 }
1928 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
1929 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
1930 return 0;
1931 }
1932 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
1933 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
1934 return 0;
1935 }
1936 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
1937 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
1938 return 0;
1939 }
1940 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
1941 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
1942 return 0;
1943 }
1944 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
1945 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
1946 return 0;
1da177e4
LT		 1947 }
1948
19a60522
SS		 1949 /*
1950 * In PCI 33 mode, the P_PLL is not used, and therefore,
1951 * the the P_PLL_LOCK bit in the adapter_status register will
1952 * not be asserted.
1953 */
1954 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
1955 sp->device_type == XFRAME_II_DEVICE && mode !=
1956 PCI_MODE_PCI_33) {
1957 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
1958 return 0;
1959 }
1960 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1961 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1962 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
1963 return 0;
1964 }
1965 return 1;
1da177e4
LT		 1966}
1967
1968/**
1969 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
1970 * @sp: Pointer to device specifc structure
20346722 1971 * Description :
1da177e4
LT		 1972 * New procedure to clear mac address reading problems on Alpha platforms
1973 *
1974 */
1975
1ee6dd77 1976static void fix_mac_address(struct s2io_nic * sp)
1da177e4 1977{
1ee6dd77 1978 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 1979 u64 val64;
1980 int i = 0;
1981
1982 while (fix_mac[i] != END_SIGN) {
1983 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 1984 udelay(10);
1da177e4
LT		 1985 val64 = readq(&bar0->gpio_control);
1986 }
1987}
1988
1989/**
20346722 1990 * start_nic - Turns the device on
1da177e4 1991 * @nic : device private variable.
20346722
K		 1992 * Description:
1993 * This function actually turns the device on. Before this function is
1994 * called,all Registers are configured from their reset states
1995 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 1996 * calling this function, the device interrupts are cleared and the NIC is
1997 * literally switched on by writing into the adapter control register.
20346722 1998 * Return Value:
1da177e4
LT		 1999 * SUCCESS on success and -1 on failure.
2000 */
2001
2002static int start_nic(struct s2io_nic *nic)
2003{
1ee6dd77 2004 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2005 struct net_device *dev = nic->dev;
2006 register u64 val64 = 0;
20346722 2007 u16 subid, i;
1ee6dd77 2008 struct mac_info *mac_control;
1da177e4
LT		 2009 struct config_param *config;
2010
2011 mac_control = &nic->mac_control;
2012 config = &nic->config;
2013
2014 /* PRC Initialization and configuration */
2015 for (i = 0; i < config->rx_ring_num; i++) {
20346722 2016 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1da177e4
LT		 2017 &bar0->prc_rxd0_n[i]);
2018
2019 val64 = readq(&bar0->prc_ctrl_n[i]);
b6e3f982
K		 2020 if (nic->config.bimodal)
2021 val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
da6971d8
AR		 2022 if (nic->rxd_mode == RXD_MODE_1)
2023 val64 |= PRC_CTRL_RC_ENABLED;
2024 else
2025 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2026 if (nic->device_type == XFRAME_II_DEVICE)
2027 val64 |= PRC_CTRL_GROUP_READS;
2028 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2029 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2030 writeq(val64, &bar0->prc_ctrl_n[i]);
2031 }
2032
da6971d8
AR		 2033 if (nic->rxd_mode == RXD_MODE_3B) {
2034 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2035 val64 = readq(&bar0->rx_pa_cfg);
2036 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2037 writeq(val64, &bar0->rx_pa_cfg);
2038 }
1da177e4 2039
926930b2
SS		 2040 if (vlan_tag_strip == 0) {
2041 val64 = readq(&bar0->rx_pa_cfg);
2042 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2043 writeq(val64, &bar0->rx_pa_cfg);
2044 vlan_strip_flag = 0;
2045 }
2046
20346722 2047 /*
1da177e4
LT		 2048 * Enabling MC-RLDRAM. After enabling the device, we timeout
2049 * for around 100ms, which is approximately the time required
2050 * for the device to be ready for operation.
2051 */
2052 val64 = readq(&bar0->mc_rldram_mrs);
2053 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2054 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2055 val64 = readq(&bar0->mc_rldram_mrs);
2056
20346722 2057 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2058
2059 /* Enabling ECC Protection. */
2060 val64 = readq(&bar0->adapter_control);
2061 val64 &= ~ADAPTER_ECC_EN;
2062 writeq(val64, &bar0->adapter_control);
2063
20346722
K		 2064 /*
2065 * Clearing any possible Link state change interrupts that
1da177e4
LT		 2066 * could have popped up just before Enabling the card.
2067 */
2068 val64 = readq(&bar0->mac_rmac_err_reg);
2069 if (val64)
2070 writeq(val64, &bar0->mac_rmac_err_reg);
2071
20346722
K		 2072 /*
2073 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2074 * it.
2075 */
2076 val64 = readq(&bar0->adapter_status);
19a60522 2077 if (!verify_xena_quiescence(nic)) {
1da177e4
LT		 2078 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2079 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2080 (unsigned long long) val64);
2081 return FAILURE;
2082 }
2083
20346722 2084 /*
1da177e4 2085 * With some switches, link might be already up at this point.
20346722
K		 2086 * Because of this weird behavior, when we enable laser,
2087 * we may not get link. We need to handle this. We cannot
2088 * figure out which switch is misbehaving. So we are forced to
2089 * make a global change.
1da177e4
LT		 2090 */
2091
2092 /* Enabling Laser. */
2093 val64 = readq(&bar0->adapter_control);
2094 val64 |= ADAPTER_EOI_TX_ON;
2095 writeq(val64, &bar0->adapter_control);
2096
c92ca04b
AR		 2097 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2098 /*
2099 * Dont see link state interrupts initally on some switches,
2100 * so directly scheduling the link state task here.
2101 */
2102 schedule_work(&nic->set_link_task);
2103 }
1da177e4
LT		 2104 /* SXE-002: Initialize link and activity LED */
2105 subid = nic->pdev->subsystem_device;
541ae68f
K		 2106 if (((subid & 0xFF) >= 0x07) &&
2107 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2108 val64 = readq(&bar0->gpio_control);
2109 val64 |= 0x0000800000000000ULL;
2110 writeq(val64, &bar0->gpio_control);
2111 val64 = 0x0411040400000000ULL;
509a2671 2112 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2113 }
2114
1da177e4
LT		 2115 return SUCCESS;
2116}
fed5eccd
AR		 2117/**
2118 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2119 */
1ee6dd77
RB		 2120static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2121 TxD *txdlp, int get_off)
fed5eccd 2122{
1ee6dd77 2123 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2124 struct sk_buff *skb;
1ee6dd77 2125 struct TxD *txds;
fed5eccd
AR		 2126 u16 j, frg_cnt;
2127
2128 txds = txdlp;
26b7625c 2129 if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
fed5eccd
AR		 2130 pci_unmap_single(nic->pdev, (dma_addr_t)
2131 txds->Buffer_Pointer, sizeof(u64),
2132 PCI_DMA_TODEVICE);
2133 txds++;
2134 }
2135
2136 skb = (struct sk_buff *) ((unsigned long)
2137 txds->Host_Control);
2138 if (!skb) {
1ee6dd77 2139 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2140 return NULL;
2141 }
2142 pci_unmap_single(nic->pdev, (dma_addr_t)
2143 txds->Buffer_Pointer,
2144 skb->len - skb->data_len,
2145 PCI_DMA_TODEVICE);
2146 frg_cnt = skb_shinfo(skb)->nr_frags;
2147 if (frg_cnt) {
2148 txds++;
2149 for (j = 0; j < frg_cnt; j++, txds++) {
2150 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2151 if (!txds->Buffer_Pointer)
2152 break;
6aa20a22 2153 pci_unmap_page(nic->pdev, (dma_addr_t)
fed5eccd
AR		 2154 txds->Buffer_Pointer,
2155 frag->size, PCI_DMA_TODEVICE);
2156 }
2157 }
1ee6dd77 2158 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2159 return(skb);
2160}
1da177e4 2161
20346722
K		 2162/**
2163 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2164 * @nic : device private variable.
20346722 2165 * Description:
1da177e4 2166 * Free all queued Tx buffers.
20346722 2167 * Return Value: void
1da177e4
LT		 2168*/
2169
2170static void free_tx_buffers(struct s2io_nic *nic)
2171{
2172 struct net_device *dev = nic->dev;
2173 struct sk_buff *skb;
1ee6dd77 2174 struct TxD *txdp;
1da177e4 2175 int i, j;
1ee6dd77 2176 struct mac_info *mac_control;
1da177e4 2177 struct config_param *config;
fed5eccd 2178 int cnt = 0;
1da177e4
LT		 2179
2180 mac_control = &nic->mac_control;
2181 config = &nic->config;
2182
2183 for (i = 0; i < config->tx_fifo_num; i++) {
2184 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
491976b2
SH		 2185 txdp = (struct TxD *) \
2186 mac_control->fifos[i].list_info[j].list_virt_addr;
fed5eccd
AR		 2187 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2188 if (skb) {
491976b2
SH		 2189 nic->mac_control.stats_info->sw_stat.mem_freed
2190 += skb->truesize;
fed5eccd
AR		 2191 dev_kfree_skb(skb);
2192 cnt++;
1da177e4 2193 }
1da177e4
LT		 2194 }
2195 DBG_PRINT(INTR_DBG,
2196 "%s:forcibly freeing %d skbs on FIFO%d\n",
2197 dev->name, cnt, i);
20346722
K		 2198 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2199 mac_control->fifos[i].tx_curr_put_info.offset = 0;
1da177e4
LT		 2200 }
2201}
2202
20346722
K		 2203/**
2204 * stop_nic - To stop the nic
1da177e4 2205 * @nic ; device private variable.
20346722
K		 2206 * Description:
2207 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2208 * function does. This function is called to stop the device.
2209 * Return Value:
2210 * void.
2211 */
2212
2213static void stop_nic(struct s2io_nic *nic)
2214{
1ee6dd77 2215 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2216 register u64 val64 = 0;
5d3213cc 2217 u16 interruptible;
1ee6dd77 2218 struct mac_info *mac_control;
1da177e4
LT		 2219 struct config_param *config;
2220
2221 mac_control = &nic->mac_control;
2222 config = &nic->config;
2223
2224 /* Disable all interrupts */
e960fc5c 2225 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
a371a07d
K		 2226 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2227 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
1da177e4
LT		 2228 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2229
5d3213cc
AR		 2230 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2231 val64 = readq(&bar0->adapter_control);
2232 val64 &= ~(ADAPTER_CNTL_EN);
2233 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2234}
2235
20346722
K		 2236/**
2237 * fill_rx_buffers - Allocates the Rx side skbs
1da177e4 2238 * @nic: device private variable
20346722
K		 2239 * @ring_no: ring number
2240 * Description:
1da177e4
LT		 2241 * The function allocates Rx side skbs and puts the physical
2242 * address of these buffers into the RxD buffer pointers, so that the NIC
2243 * can DMA the received frame into these locations.
2244 * The NIC supports 3 receive modes, viz
2245 * 1. single buffer,
2246 * 2. three buffer and
2247 * 3. Five buffer modes.
20346722
K		 2248 * Each mode defines how many fragments the received frame will be split
2249 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2250 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2251 * is split into 3 fragments. As of now only single buffer mode is
2252 * supported.
2253 * Return Value:
2254 * SUCCESS on success or an appropriate -ve value on failure.
2255 */
2256
ac1f60db 2257static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1da177e4
LT		 2258{
2259 struct net_device *dev = nic->dev;
2260 struct sk_buff *skb;
1ee6dd77 2261 struct RxD_t *rxdp;
1da177e4 2262 int off, off1, size, block_no, block_no1;
1da177e4 2263 u32 alloc_tab = 0;
20346722 2264 u32 alloc_cnt;
1ee6dd77 2265 struct mac_info *mac_control;
1da177e4 2266 struct config_param *config;
20346722 2267 u64 tmp;
1ee6dd77 2268 struct buffAdd *ba;
1da177e4 2269 unsigned long flags;
1ee6dd77 2270 struct RxD_t *first_rxdp = NULL;
363dc367 2271 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
6d517a27
VP		 2272 struct RxD1 *rxdp1;
2273 struct RxD3 *rxdp3;
1da177e4
LT		 2274
2275 mac_control = &nic->mac_control;
2276 config = &nic->config;
20346722
K		 2277 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2278 atomic_read(&nic->rx_bufs_left[ring_no]);
1da177e4 2279
5d3213cc 2280 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
863c11a9 2281 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
1da177e4 2282 while (alloc_tab < alloc_cnt) {
20346722 2283 block_no = mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2284 block_index;
20346722 2285 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
1da177e4 2286
da6971d8
AR		 2287 rxdp = mac_control->rings[ring_no].
2288 rx_blocks[block_no].rxds[off].virt_addr;
2289
2290 if ((block_no == block_no1) && (off == off1) &&
2291 (rxdp->Host_Control)) {
2292 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2293 dev->name);
1da177e4
LT		 2294 DBG_PRINT(INTR_DBG, " info equated\n");
2295 goto end;
2296 }
da6971d8 2297 if (off && (off == rxd_count[nic->rxd_mode])) {
20346722 2298 mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2299 block_index++;
da6971d8
AR		 2300 if (mac_control->rings[ring_no].rx_curr_put_info.
2301 block_index == mac_control->rings[ring_no].
2302 block_count)
2303 mac_control->rings[ring_no].rx_curr_put_info.
2304 block_index = 0;
2305 block_no = mac_control->rings[ring_no].
2306 rx_curr_put_info.block_index;
2307 if (off == rxd_count[nic->rxd_mode])
2308 off = 0;
20346722 2309 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8
AR		 2310 offset = off;
2311 rxdp = mac_control->rings[ring_no].
2312 rx_blocks[block_no].block_virt_addr;
1da177e4
LT		 2313 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2314 dev->name, rxdp);
2315 }
db874e65
SS		 2316 if(!napi) {
2317 spin_lock_irqsave(&nic->put_lock, flags);
2318 mac_control->rings[ring_no].put_pos =
2319 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2320 spin_unlock_irqrestore(&nic->put_lock, flags);
2321 } else {
2322 mac_control->rings[ring_no].put_pos =
2323 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2324 }
da6971d8 2325 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
6d517a27 2326 ((nic->rxd_mode == RXD_MODE_3B) &&
da6971d8 2327 (rxdp->Control_2 & BIT(0)))) {
20346722 2328 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8 2329 offset = off;
1da177e4
LT		 2330 goto end;
2331 }
da6971d8
AR		 2332 /* calculate size of skb based on ring mode */
2333 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2334 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2335 if (nic->rxd_mode == RXD_MODE_1)
2336 size += NET_IP_ALIGN;
da6971d8 2337 else
6d517a27 2338 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2339
da6971d8
AR		 2340 /* allocate skb */
2341 skb = dev_alloc_skb(size);
2342 if(!skb) {
0c61ed5f
RV		 2343 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
2344 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
303bcb4b
K		 2345 if (first_rxdp) {
2346 wmb();
2347 first_rxdp->Control_1 |= RXD_OWN_XENA;
2348 }
c53d4945
SH		 2349 nic->mac_control.stats_info->sw_stat. \
2350 mem_alloc_fail_cnt++;
da6971d8
AR		 2351 return -ENOMEM ;
2352 }
491976b2
SH		 2353 nic->mac_control.stats_info->sw_stat.mem_allocated
2354 += skb->truesize;
da6971d8
AR		 2355 if (nic->rxd_mode == RXD_MODE_1) {
2356 /* 1 buffer mode - normal operation mode */
6d517a27 2357 rxdp1 = (struct RxD1*)rxdp;
1ee6dd77 2358 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2359 skb_reserve(skb, NET_IP_ALIGN);
6d517a27 2360 rxdp1->Buffer0_ptr = pci_map_single
863c11a9
AR		 2361 (nic->pdev, skb->data, size - NET_IP_ALIGN,
2362 PCI_DMA_FROMDEVICE);
491976b2
SH		 2363 rxdp->Control_2 =
2364 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
da6971d8 2365
6d517a27 2366 } else if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8 2367 /*
6d517a27
VP		 2368 * 2 buffer mode -
2369 * 2 buffer mode provides 128
da6971d8 2370 * byte aligned receive buffers.
da6971d8
AR		 2371 */
2372
6d517a27 2373 rxdp3 = (struct RxD3*)rxdp;
491976b2 2374 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2375 Buffer0_ptr = rxdp3->Buffer0_ptr;
2376 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2377 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2378 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2379 rxdp3->Buffer0_ptr = Buffer0_ptr;
2380 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2381
da6971d8
AR		 2382 ba = &mac_control->rings[ring_no].ba[block_no][off];
2383 skb_reserve(skb, BUF0_LEN);
2384 tmp = (u64)(unsigned long) skb->data;
2385 tmp += ALIGN_SIZE;
2386 tmp &= ~ALIGN_SIZE;
2387 skb->data = (void *) (unsigned long)tmp;
27a884dc 2388 skb_reset_tail_pointer(skb);
da6971d8 2389
6d517a27
VP		 2390 if (!(rxdp3->Buffer0_ptr))
2391 rxdp3->Buffer0_ptr =
75c30b13 2392 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
da6971d8 2393 PCI_DMA_FROMDEVICE);
75c30b13
AR		 2394 else
2395 pci_dma_sync_single_for_device(nic->pdev,
6d517a27 2396 (dma_addr_t) rxdp3->Buffer0_ptr,
75c30b13 2397 BUF0_LEN, PCI_DMA_FROMDEVICE);
da6971d8
AR		 2398 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2399 if (nic->rxd_mode == RXD_MODE_3B) {
2400 /* Two buffer mode */
2401
2402 /*
6aa20a22 2403 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2404 * L4 payload
2405 */
6d517a27 2406 rxdp3->Buffer2_ptr = pci_map_single
da6971d8
AR		 2407 (nic->pdev, skb->data, dev->mtu + 4,
2408 PCI_DMA_FROMDEVICE);
2409
75c30b13 2410 /* Buffer-1 will be dummy buffer. Not used */
6d517a27
VP		 2411 if (!(rxdp3->Buffer1_ptr)) {
2412 rxdp3->Buffer1_ptr =
6aa20a22 2413 pci_map_single(nic->pdev,
75c30b13
AR		 2414 ba->ba_1, BUF1_LEN,
2415 PCI_DMA_FROMDEVICE);
2416 }
da6971d8
AR		 2417 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2418 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2419 (dev->mtu + 4);
da6971d8
AR		 2420 }
2421 rxdp->Control_2 |= BIT(0);
1da177e4 2422 }
1da177e4 2423 rxdp->Host_Control = (unsigned long) (skb);
303bcb4b
K		 2424 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2425 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2426 off++;
da6971d8
AR		 2427 if (off == (rxd_count[nic->rxd_mode] + 1))
2428 off = 0;
20346722 2429 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
20346722 2430
da6971d8 2431 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b
K		 2432 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2433 if (first_rxdp) {
2434 wmb();
2435 first_rxdp->Control_1 |= RXD_OWN_XENA;
2436 }
2437 first_rxdp = rxdp;
2438 }
1da177e4
LT		 2439 atomic_inc(&nic->rx_bufs_left[ring_no]);
2440 alloc_tab++;
2441 }
2442
2443 end:
303bcb4b
K		 2444 /* Transfer ownership of first descriptor to adapter just before
2445 * exiting. Before that, use memory barrier so that ownership
2446 * and other fields are seen by adapter correctly.
2447 */
2448 if (first_rxdp) {
2449 wmb();
2450 first_rxdp->Control_1 |= RXD_OWN_XENA;
2451 }
2452
1da177e4
LT		 2453 return SUCCESS;
2454}
2455
da6971d8
AR		 2456static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2457{
2458 struct net_device *dev = sp->dev;
2459 int j;
2460 struct sk_buff *skb;
1ee6dd77
RB		 2461 struct RxD_t *rxdp;
2462 struct mac_info *mac_control;
2463 struct buffAdd *ba;
6d517a27
VP		 2464 struct RxD1 *rxdp1;
2465 struct RxD3 *rxdp3;
da6971d8
AR		 2466
2467 mac_control = &sp->mac_control;
2468 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2469 rxdp = mac_control->rings[ring_no].
2470 rx_blocks[blk].rxds[j].virt_addr;
2471 skb = (struct sk_buff *)
2472 ((unsigned long) rxdp->Host_Control);
2473 if (!skb) {
2474 continue;
2475 }
2476 if (sp->rxd_mode == RXD_MODE_1) {
6d517a27 2477 rxdp1 = (struct RxD1*)rxdp;
da6971d8 2478 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2479 rxdp1->Buffer0_ptr,
2480 dev->mtu +
2481 HEADER_ETHERNET_II_802_3_SIZE
2482 + HEADER_802_2_SIZE +
2483 HEADER_SNAP_SIZE,
2484 PCI_DMA_FROMDEVICE);
1ee6dd77 2485 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2486 } else if(sp->rxd_mode == RXD_MODE_3B) {
6d517a27 2487 rxdp3 = (struct RxD3*)rxdp;
da6971d8
AR		 2488 ba = &mac_control->rings[ring_no].
2489 ba[blk][j];
2490 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2491 rxdp3->Buffer0_ptr,
2492 BUF0_LEN,
da6971d8
AR		 2493 PCI_DMA_FROMDEVICE);
2494 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2495 rxdp3->Buffer1_ptr,
2496 BUF1_LEN,
da6971d8
AR		 2497 PCI_DMA_FROMDEVICE);
2498 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2499 rxdp3->Buffer2_ptr,
2500 dev->mtu + 4,
da6971d8 2501 PCI_DMA_FROMDEVICE);
1ee6dd77 2502 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2503 }
491976b2 2504 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
da6971d8
AR		 2505 dev_kfree_skb(skb);
2506 atomic_dec(&sp->rx_bufs_left[ring_no]);
2507 }
2508}
2509
1da177e4 2510/**
20346722 2511 * free_rx_buffers - Frees all Rx buffers
1da177e4 2512 * @sp: device private variable.
20346722 2513 * Description:
1da177e4
LT		 2514 * This function will free all Rx buffers allocated by host.
2515 * Return Value:
2516 * NONE.
2517 */
2518
2519static void free_rx_buffers(struct s2io_nic *sp)
2520{
2521 struct net_device *dev = sp->dev;
da6971d8 2522 int i, blk = 0, buf_cnt = 0;
1ee6dd77 2523 struct mac_info *mac_control;
1da177e4 2524 struct config_param *config;
1da177e4
LT		 2525
2526 mac_control = &sp->mac_control;
2527 config = &sp->config;
2528
2529 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 2530 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2531 free_rxd_blk(sp,i,blk);
1da177e4 2532
20346722
K		 2533 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2534 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2535 mac_control->rings[i].rx_curr_put_info.offset = 0;
2536 mac_control->rings[i].rx_curr_get_info.offset = 0;
1da177e4
LT		 2537 atomic_set(&sp->rx_bufs_left[i], 0);
2538 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2539 dev->name, buf_cnt, i);
2540 }
2541}
2542
2543/**
2544 * s2io_poll - Rx interrupt handler for NAPI support
2545 * @dev : pointer to the device structure.
20346722 2546 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2547 * during one pass through the 'Poll" function.
2548 * Description:
2549 * Comes into picture only if NAPI support has been incorporated. It does
2550 * the same thing that rx_intr_handler does, but not in a interrupt context
2551 * also It will process only a given number of packets.
2552 * Return value:
2553 * 0 on success and 1 if there are No Rx packets to be processed.
2554 */
2555
1da177e4
LT		 2556static int s2io_poll(struct net_device *dev, int *budget)
2557{
1ee6dd77 2558 struct s2io_nic *nic = dev->priv;
20346722 2559 int pkt_cnt = 0, org_pkts_to_process;
1ee6dd77 2560 struct mac_info *mac_control;
1da177e4 2561 struct config_param *config;
1ee6dd77 2562 struct XENA_dev_config __iomem *bar0 = nic->bar0;
20346722 2563 int i;
1da177e4 2564
7ba013ac 2565 atomic_inc(&nic->isr_cnt);
1da177e4
LT		 2566 mac_control = &nic->mac_control;
2567 config = &nic->config;
2568
20346722
K		 2569 nic->pkts_to_process = *budget;
2570 if (nic->pkts_to_process > dev->quota)
2571 nic->pkts_to_process = dev->quota;
2572 org_pkts_to_process = nic->pkts_to_process;
1da177e4 2573
19a60522
SS		 2574 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2575 readl(&bar0->rx_traffic_int);
1da177e4
LT		 2576
2577 for (i = 0; i < config->rx_ring_num; i++) {
20346722
K		 2578 rx_intr_handler(&mac_control->rings[i]);
2579 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2580 if (!nic->pkts_to_process) {
2581 /* Quota for the current iteration has been met */
2582 goto no_rx;
1da177e4 2583 }
1da177e4
LT		 2584 }
2585 if (!pkt_cnt)
2586 pkt_cnt = 1;
2587
2588 dev->quota -= pkt_cnt;
2589 *budget -= pkt_cnt;
2590 netif_rx_complete(dev);
2591
2592 for (i = 0; i < config->rx_ring_num; i++) {
2593 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2594 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2595 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
1da177e4
LT		 2596 break;
2597 }
2598 }
2599 /* Re enable the Rx interrupts. */
c92ca04b 2600 writeq(0x0, &bar0->rx_traffic_mask);
19a60522 2601 readl(&bar0->rx_traffic_mask);
7ba013ac 2602 atomic_dec(&nic->isr_cnt);
1da177e4
LT		 2603 return 0;
2604
20346722 2605no_rx:
1da177e4
LT		 2606 dev->quota -= pkt_cnt;
2607 *budget -= pkt_cnt;
2608
2609 for (i = 0; i < config->rx_ring_num; i++) {
2610 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2611 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2612 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
1da177e4
LT		 2613 break;
2614 }
2615 }
7ba013ac 2616 atomic_dec(&nic->isr_cnt);
1da177e4
LT		 2617 return 1;
2618}
20346722 2619
b41477f3 2620#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2621/**
b41477f3 2622 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2623 * @dev : pointer to the device structure.
2624 * Description:
b41477f3
AR		 2625 * This function will be called by upper layer to check for events on the
2626 * interface in situations where interrupts are disabled. It is used for
2627 * specific in-kernel networking tasks, such as remote consoles and kernel
2628 * debugging over the network (example netdump in RedHat).
612eff0e 2629 */
612eff0e
BH		 2630static void s2io_netpoll(struct net_device *dev)
2631{
1ee6dd77
RB		 2632 struct s2io_nic *nic = dev->priv;
2633 struct mac_info *mac_control;
612eff0e 2634 struct config_param *config;
1ee6dd77 2635 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2636 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e
BH		 2637 int i;
2638
d796fdb7
LV		 2639 if (pci_channel_offline(nic->pdev))
2640 return;
2641
612eff0e
BH		 2642 disable_irq(dev->irq);
2643
2644 atomic_inc(&nic->isr_cnt);
2645 mac_control = &nic->mac_control;
2646 config = &nic->config;
2647
612eff0e 2648 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2649 writeq(val64, &bar0->tx_traffic_int);
2650
6aa20a22 2651 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2652 * run out of skbs and will fail and eventually netpoll application such
2653 * as netdump will fail.
2654 */
2655 for (i = 0; i < config->tx_fifo_num; i++)
2656 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2657
b41477f3 2658 /* check for received packet and indicate up to network */
612eff0e
BH		 2659 for (i = 0; i < config->rx_ring_num; i++)
2660 rx_intr_handler(&mac_control->rings[i]);
2661
2662 for (i = 0; i < config->rx_ring_num; i++) {
2663 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2664 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2665 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
612eff0e
BH		 2666 break;
2667 }
2668 }
2669 atomic_dec(&nic->isr_cnt);
2670 enable_irq(dev->irq);
2671 return;
2672}
2673#endif
2674
20346722 2675/**
1da177e4
LT		 2676 * rx_intr_handler - Rx interrupt handler
2677 * @nic: device private variable.
20346722
K		 2678 * Description:
2679 * If the interrupt is because of a received frame or if the
1da177e4 2680 * receive ring contains fresh as yet un-processed frames,this function is
20346722
K		 2681 * called. It picks out the RxD at which place the last Rx processing had
2682 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2683 * the offset.
2684 * Return Value:
2685 * NONE.
2686 */
1ee6dd77 2687static void rx_intr_handler(struct ring_info *ring_data)
1da177e4 2688{
1ee6dd77 2689 struct s2io_nic *nic = ring_data->nic;
1da177e4 2690 struct net_device *dev = (struct net_device *) nic->dev;
da6971d8 2691 int get_block, put_block, put_offset;
1ee6dd77
RB		 2692 struct rx_curr_get_info get_info, put_info;
2693 struct RxD_t *rxdp;
1da177e4 2694 struct sk_buff *skb;
20346722 2695 int pkt_cnt = 0;
7d3d0439 2696 int i;
6d517a27
VP		 2697 struct RxD1* rxdp1;
2698 struct RxD3* rxdp3;
7d3d0439 2699
7ba013ac
K		 2700 spin_lock(&nic->rx_lock);
2701 if (atomic_read(&nic->card_state) == CARD_DOWN) {
776bd20f 2702 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
7ba013ac
K		 2703 __FUNCTION__, dev->name);
2704 spin_unlock(&nic->rx_lock);
776bd20f 2705 return;
7ba013ac
K		 2706 }
2707
20346722
K		 2708 get_info = ring_data->rx_curr_get_info;
2709 get_block = get_info.block_index;
1ee6dd77 2710 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2711 put_block = put_info.block_index;
da6971d8 2712 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65
SS		 2713 if (!napi) {
2714 spin_lock(&nic->put_lock);
2715 put_offset = ring_data->put_pos;
2716 spin_unlock(&nic->put_lock);
2717 } else
2718 put_offset = ring_data->put_pos;
2719
da6971d8 2720 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2721 /*
2722 * If your are next to put index then it's
2723 * FIFO full condition
2724 */
da6971d8
AR		 2725 if ((get_block == put_block) &&
2726 (get_info.offset + 1) == put_info.offset) {
75c30b13 2727 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
da6971d8
AR		 2728 break;
2729 }
20346722
K		 2730 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2731 if (skb == NULL) {
2732 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2733 dev->name);
2734 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
7ba013ac 2735 spin_unlock(&nic->rx_lock);
20346722 2736 return;
1da177e4 2737 }
da6971d8 2738 if (nic->rxd_mode == RXD_MODE_1) {
6d517a27 2739 rxdp1 = (struct RxD1*)rxdp;
da6971d8 2740 pci_unmap_single(nic->pdev, (dma_addr_t)
6d517a27
VP		 2741 rxdp1->Buffer0_ptr,
2742 dev->mtu +
2743 HEADER_ETHERNET_II_802_3_SIZE +
2744 HEADER_802_2_SIZE +
2745 HEADER_SNAP_SIZE,
2746 PCI_DMA_FROMDEVICE);
da6971d8 2747 } else if (nic->rxd_mode == RXD_MODE_3B) {
6d517a27 2748 rxdp3 = (struct RxD3*)rxdp;
75c30b13 2749 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
6d517a27
VP		 2750 rxdp3->Buffer0_ptr,
2751 BUF0_LEN, PCI_DMA_FROMDEVICE);
da6971d8 2752 pci_unmap_single(nic->pdev, (dma_addr_t)
6d517a27
VP		 2753 rxdp3->Buffer2_ptr,
2754 dev->mtu + 4,
2755 PCI_DMA_FROMDEVICE);
da6971d8 2756 }
863c11a9 2757 prefetch(skb->data);
20346722
K		 2758 rx_osm_handler(ring_data, rxdp);
2759 get_info.offset++;
da6971d8
AR		 2760 ring_data->rx_curr_get_info.offset = get_info.offset;
2761 rxdp = ring_data->rx_blocks[get_block].
2762 rxds[get_info.offset].virt_addr;
2763 if (get_info.offset == rxd_count[nic->rxd_mode]) {
20346722 2764 get_info.offset = 0;
da6971d8 2765 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 2766 get_block++;
da6971d8
AR		 2767 if (get_block == ring_data->block_count)
2768 get_block = 0;
2769 ring_data->rx_curr_get_info.block_index = get_block;
20346722
K		 2770 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2771 }
1da177e4 2772
20346722 2773 nic->pkts_to_process -= 1;
db874e65 2774 if ((napi) && (!nic->pkts_to_process))
20346722 2775 break;
20346722 2776 pkt_cnt++;
1da177e4
LT		 2777 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2778 break;
2779 }
7d3d0439
RA		 2780 if (nic->lro) {
2781 /* Clear all LRO sessions before exiting */
2782 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 2783 struct lro *lro = &nic->lro0_n[i];
7d3d0439
RA		 2784 if (lro->in_use) {
2785 update_L3L4_header(nic, lro);
2786 queue_rx_frame(lro->parent);
2787 clear_lro_session(lro);
2788 }
2789 }
2790 }
2791
7ba013ac 2792 spin_unlock(&nic->rx_lock);
1da177e4 2793}
20346722
K		 2794
2795/**
1da177e4
LT		 2796 * tx_intr_handler - Transmit interrupt handler
2797 * @nic : device private variable
20346722
K		 2798 * Description:
2799 * If an interrupt was raised to indicate DMA complete of the
2800 * Tx packet, this function is called. It identifies the last TxD
2801 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 2802 * DMA'ed into the NICs internal memory.
2803 * Return Value:
2804 * NONE
2805 */
2806
1ee6dd77 2807static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 2808{
1ee6dd77 2809 struct s2io_nic *nic = fifo_data->nic;
1da177e4 2810 struct net_device *dev = (struct net_device *) nic->dev;
1ee6dd77 2811 struct tx_curr_get_info get_info, put_info;
1da177e4 2812 struct sk_buff *skb;
1ee6dd77 2813 struct TxD *txdlp;
f9046eb3 2814 u8 err_mask;
1da177e4 2815
20346722 2816 get_info = fifo_data->tx_curr_get_info;
1ee6dd77
RB		 2817 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
2818 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
20346722
K		 2819 list_virt_addr;
2820 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2821 (get_info.offset != put_info.offset) &&
2822 (txdlp->Host_Control)) {
2823 /* Check for TxD errors */
2824 if (txdlp->Control_1 & TXD_T_CODE) {
2825 unsigned long long err;
2826 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0
AR		 2827 if (err & 0x1) {
2828 nic->mac_control.stats_info->sw_stat.
2829 parity_err_cnt++;
2830 }
491976b2
SH		 2831
2832 /* update t_code statistics */
f9046eb3
OH		 2833 err_mask = err >> 48;
2834 switch(err_mask) {
491976b2
SH		 2835 case 2:
2836 nic->mac_control.stats_info->sw_stat.
2837 tx_buf_abort_cnt++;
2838 break;
2839
2840 case 3:
2841 nic->mac_control.stats_info->sw_stat.
2842 tx_desc_abort_cnt++;
2843 break;
2844
2845 case 7:
2846 nic->mac_control.stats_info->sw_stat.
2847 tx_parity_err_cnt++;
2848 break;
2849
2850 case 10:
2851 nic->mac_control.stats_info->sw_stat.
2852 tx_link_loss_cnt++;
2853 break;
2854
2855 case 15:
2856 nic->mac_control.stats_info->sw_stat.
2857 tx_list_proc_err_cnt++;
2858 break;
2859 }
20346722 2860 }
1da177e4 2861
fed5eccd 2862 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722
K		 2863 if (skb == NULL) {
2864 DBG_PRINT(ERR_DBG, "%s: Null skb ",
2865 __FUNCTION__);
2866 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2867 return;
2868 }
2869
20346722 2870 /* Updating the statistics block */
20346722 2871 nic->stats.tx_bytes += skb->len;
491976b2 2872 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
20346722
K		 2873 dev_kfree_skb_irq(skb);
2874
2875 get_info.offset++;
863c11a9
AR		 2876 if (get_info.offset == get_info.fifo_len + 1)
2877 get_info.offset = 0;
1ee6dd77 2878 txdlp = (struct TxD *) fifo_data->list_info
20346722
K		 2879 [get_info.offset].list_virt_addr;
2880 fifo_data->tx_curr_get_info.offset =
2881 get_info.offset;
1da177e4
LT		 2882 }
2883
2884 spin_lock(&nic->tx_lock);
2885 if (netif_queue_stopped(dev))
2886 netif_wake_queue(dev);
2887 spin_unlock(&nic->tx_lock);
2888}
2889
bd1034f0
AR		 2890/**
2891 * s2io_mdio_write - Function to write in to MDIO registers
2892 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2893 * @addr : address value
2894 * @value : data value
2895 * @dev : pointer to net_device structure
2896 * Description:
2897 * This function is used to write values to the MDIO registers
2898 * NONE
2899 */
2900static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2901{
2902 u64 val64 = 0x0;
1ee6dd77
RB		 2903 struct s2io_nic *sp = dev->priv;
2904 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 2905
2906 //address transaction
2907 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2908 | MDIO_MMD_DEV_ADDR(mmd_type)
2909 | MDIO_MMS_PRT_ADDR(0x0);
2910 writeq(val64, &bar0->mdio_control);
2911 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2912 writeq(val64, &bar0->mdio_control);
2913 udelay(100);
2914
2915 //Data transaction
2916 val64 = 0x0;
2917 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2918 | MDIO_MMD_DEV_ADDR(mmd_type)
2919 | MDIO_MMS_PRT_ADDR(0x0)
2920 | MDIO_MDIO_DATA(value)
2921 | MDIO_OP(MDIO_OP_WRITE_TRANS);
2922 writeq(val64, &bar0->mdio_control);
2923 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2924 writeq(val64, &bar0->mdio_control);
2925 udelay(100);
2926
2927 val64 = 0x0;
2928 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2929 | MDIO_MMD_DEV_ADDR(mmd_type)
2930 | MDIO_MMS_PRT_ADDR(0x0)
2931 | MDIO_OP(MDIO_OP_READ_TRANS);
2932 writeq(val64, &bar0->mdio_control);
2933 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2934 writeq(val64, &bar0->mdio_control);
2935 udelay(100);
2936
2937}
2938
2939/**
2940 * s2io_mdio_read - Function to write in to MDIO registers
2941 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2942 * @addr : address value
2943 * @dev : pointer to net_device structure
2944 * Description:
2945 * This function is used to read values to the MDIO registers
2946 * NONE
2947 */
2948static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2949{
2950 u64 val64 = 0x0;
2951 u64 rval64 = 0x0;
1ee6dd77
RB		 2952 struct s2io_nic *sp = dev->priv;
2953 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 2954
2955 /* address transaction */
2956 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2957 | MDIO_MMD_DEV_ADDR(mmd_type)
2958 | MDIO_MMS_PRT_ADDR(0x0);
2959 writeq(val64, &bar0->mdio_control);
2960 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2961 writeq(val64, &bar0->mdio_control);
2962 udelay(100);
2963
2964 /* Data transaction */
2965 val64 = 0x0;
2966 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2967 | MDIO_MMD_DEV_ADDR(mmd_type)
2968 | MDIO_MMS_PRT_ADDR(0x0)
2969 | MDIO_OP(MDIO_OP_READ_TRANS);
2970 writeq(val64, &bar0->mdio_control);
2971 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2972 writeq(val64, &bar0->mdio_control);
2973 udelay(100);
2974
2975 /* Read the value from regs */
2976 rval64 = readq(&bar0->mdio_control);
2977 rval64 = rval64 & 0xFFFF0000;
2978 rval64 = rval64 >> 16;
2979 return rval64;
2980}
2981/**
2982 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
2983 * @counter : couter value to be updated
2984 * @flag : flag to indicate the status
2985 * @type : counter type
2986 * Description:
2987 * This function is to check the status of the xpak counters value
2988 * NONE
2989 */
2990
2991static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
2992{
2993 u64 mask = 0x3;
2994 u64 val64;
2995 int i;
2996 for(i = 0; i <index; i++)
2997 mask = mask << 0x2;
2998
2999 if(flag > 0)
3000 {
3001 *counter = *counter + 1;
3002 val64 = *regs_stat & mask;
3003 val64 = val64 >> (index * 0x2);
3004 val64 = val64 + 1;
3005 if(val64 == 3)
3006 {
3007 switch(type)
3008 {
3009 case 1:
3010 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3011 "service. Excessive temperatures may "
3012 "result in premature transceiver "
3013 "failure \n");
3014 break;
3015 case 2:
3016 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3017 "service Excessive bias currents may "
3018 "indicate imminent laser diode "
3019 "failure \n");
3020 break;
3021 case 3:
3022 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3023 "service Excessive laser output "
3024 "power may saturate far-end "
3025 "receiver\n");
3026 break;
3027 default:
3028 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3029 "type \n");
3030 }
3031 val64 = 0x0;
3032 }
3033 val64 = val64 << (index * 0x2);
3034 *regs_stat = (*regs_stat & (~mask)) | (val64);
3035
3036 } else {
3037 *regs_stat = *regs_stat & (~mask);
3038 }
3039}
3040
3041/**
3042 * s2io_updt_xpak_counter - Function to update the xpak counters
3043 * @dev : pointer to net_device struct
3044 * Description:
3045 * This function is to upate the status of the xpak counters value
3046 * NONE
3047 */
3048static void s2io_updt_xpak_counter(struct net_device *dev)
3049{
3050 u16 flag = 0x0;
3051 u16 type = 0x0;
3052 u16 val16 = 0x0;
3053 u64 val64 = 0x0;
3054 u64 addr = 0x0;
3055
1ee6dd77
RB		 3056 struct s2io_nic *sp = dev->priv;
3057 struct stat_block *stat_info = sp->mac_control.stats_info;
bd1034f0
AR		 3058
3059 /* Check the communication with the MDIO slave */
3060 addr = 0x0000;
3061 val64 = 0x0;
3062 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3063 if((val64 == 0xFFFF) || (val64 == 0x0000))
3064 {
3065 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3066 "Returned %llx\n", (unsigned long long)val64);
3067 return;
3068 }
3069
3070 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3071 if(val64 != 0x2040)
3072 {
3073 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3074 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3075 (unsigned long long)val64);
3076 return;
3077 }
3078
3079 /* Loading the DOM register to MDIO register */
3080 addr = 0xA100;
3081 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3082 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3083
3084 /* Reading the Alarm flags */
3085 addr = 0xA070;
3086 val64 = 0x0;
3087 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3088
3089 flag = CHECKBIT(val64, 0x7);
3090 type = 1;
3091 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3092 &stat_info->xpak_stat.xpak_regs_stat,
3093 0x0, flag, type);
3094
3095 if(CHECKBIT(val64, 0x6))
3096 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3097
3098 flag = CHECKBIT(val64, 0x3);
3099 type = 2;
3100 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3101 &stat_info->xpak_stat.xpak_regs_stat,
3102 0x2, flag, type);
3103
3104 if(CHECKBIT(val64, 0x2))
3105 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3106
3107 flag = CHECKBIT(val64, 0x1);
3108 type = 3;
3109 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3110 &stat_info->xpak_stat.xpak_regs_stat,
3111 0x4, flag, type);
3112
3113 if(CHECKBIT(val64, 0x0))
3114 stat_info->xpak_stat.alarm_laser_output_power_low++;
3115
3116 /* Reading the Warning flags */
3117 addr = 0xA074;
3118 val64 = 0x0;
3119 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3120
3121 if(CHECKBIT(val64, 0x7))
3122 stat_info->xpak_stat.warn_transceiver_temp_high++;
3123
3124 if(CHECKBIT(val64, 0x6))
3125 stat_info->xpak_stat.warn_transceiver_temp_low++;
3126
3127 if(CHECKBIT(val64, 0x3))
3128 stat_info->xpak_stat.warn_laser_bias_current_high++;
3129
3130 if(CHECKBIT(val64, 0x2))
3131 stat_info->xpak_stat.warn_laser_bias_current_low++;
3132
3133 if(CHECKBIT(val64, 0x1))
3134 stat_info->xpak_stat.warn_laser_output_power_high++;
3135
3136 if(CHECKBIT(val64, 0x0))
3137 stat_info->xpak_stat.warn_laser_output_power_low++;
3138}
3139
20346722 3140/**
1da177e4
LT		 3141 * alarm_intr_handler - Alarm Interrrupt handler
3142 * @nic: device private variable
20346722 3143 * Description: If the interrupt was neither because of Rx packet or Tx
1da177e4 3144 * complete, this function is called. If the interrupt was to indicate
20346722
K		 3145 * a loss of link, the OSM link status handler is invoked for any other
3146 * alarm interrupt the block that raised the interrupt is displayed
1da177e4
LT		 3147 * and a H/W reset is issued.
3148 * Return Value:
3149 * NONE
3150*/
3151
3152static void alarm_intr_handler(struct s2io_nic *nic)
3153{
3154 struct net_device *dev = (struct net_device *) nic->dev;
1ee6dd77 3155 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 3156 register u64 val64 = 0, err_reg = 0;
bd1034f0
AR		 3157 u64 cnt;
3158 int i;
372cc597
SS		 3159 if (atomic_read(&nic->card_state) == CARD_DOWN)
3160 return;
d796fdb7
LV		 3161 if (pci_channel_offline(nic->pdev))
3162 return;
bd1034f0
AR		 3163 nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3164 /* Handling the XPAK counters update */
3165 if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3166 /* waiting for an hour */
3167 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3168 } else {
3169 s2io_updt_xpak_counter(dev);
3170 /* reset the count to zero */
3171 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3172 }
1da177e4
LT		 3173
3174 /* Handling link status change error Intr */
a371a07d
K		 3175 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3176 err_reg = readq(&bar0->mac_rmac_err_reg);
3177 writeq(err_reg, &bar0->mac_rmac_err_reg);
3178 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3179 schedule_work(&nic->set_link_task);
3180 }
1da177e4
LT		 3181 }
3182
5e25b9dd
K		 3183 /* Handling Ecc errors */
3184 val64 = readq(&bar0->mc_err_reg);
3185 writeq(val64, &bar0->mc_err_reg);
3186 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3187 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
7ba013ac
K		 3188 nic->mac_control.stats_info->sw_stat.
3189 double_ecc_errs++;
776bd20f 3190 DBG_PRINT(INIT_DBG, "%s: Device indicates ",
5e25b9dd 3191 dev->name);
776bd20f 3192 DBG_PRINT(INIT_DBG, "double ECC error!!\n");
e960fc5c 3193 if (nic->device_type != XFRAME_II_DEVICE) {
776bd20f 3194 /* Reset XframeI only if critical error */
3195 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3196 MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3197 netif_stop_queue(dev);
3198 schedule_work(&nic->rst_timer_task);
bd1034f0
AR		 3199 nic->mac_control.stats_info->sw_stat.
3200 soft_reset_cnt++;
776bd20f 3201 }
e960fc5c 3202 }
5e25b9dd 3203 } else {
7ba013ac
K		 3204 nic->mac_control.stats_info->sw_stat.
3205 single_ecc_errs++;
5e25b9dd
K		 3206 }
3207 }
3208
1da177e4
LT		 3209 /* In case of a serious error, the device will be Reset. */
3210 val64 = readq(&bar0->serr_source);
3211 if (val64 & SERR_SOURCE_ANY) {
bd1034f0 3212 nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
1da177e4 3213 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
6aa20a22 3214 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
776bd20f 3215 (unsigned long long)val64);
1da177e4
LT		 3216 netif_stop_queue(dev);
3217 schedule_work(&nic->rst_timer_task);
bd1034f0 3218 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 3219 }
3220
3221 /*
3222 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3223 * Error occurs, the adapter will be recycled by disabling the
20346722 3224 * adapter enable bit and enabling it again after the device
1da177e4
LT		 3225 * becomes Quiescent.
3226 */
3227 val64 = readq(&bar0->pcc_err_reg);
3228 writeq(val64, &bar0->pcc_err_reg);
3229 if (val64 & PCC_FB_ECC_DB_ERR) {
3230 u64 ac = readq(&bar0->adapter_control);
3231 ac &= ~(ADAPTER_CNTL_EN);
3232 writeq(ac, &bar0->adapter_control);
3233 ac = readq(&bar0->adapter_control);
3234 schedule_work(&nic->set_link_task);
3235 }
bd1034f0
AR		 3236 /* Check for data parity error */
3237 val64 = readq(&bar0->pic_int_status);
3238 if (val64 & PIC_INT_GPIO) {
3239 val64 = readq(&bar0->gpio_int_reg);
3240 if (val64 & GPIO_INT_REG_DP_ERR_INT) {
3241 nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
3242 schedule_work(&nic->rst_timer_task);
3243 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3244 }
3245 }
3246
3247 /* Check for ring full counter */
3248 if (nic->device_type & XFRAME_II_DEVICE) {
3249 val64 = readq(&bar0->ring_bump_counter1);
3250 for (i=0; i<4; i++) {
3251 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3252 cnt >>= 64 - ((i+1)*16);
3253 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3254 += cnt;
3255 }
3256
3257 val64 = readq(&bar0->ring_bump_counter2);
3258 for (i=0; i<4; i++) {
3259 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3260 cnt >>= 64 - ((i+1)*16);
3261 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3262 += cnt;
3263 }
3264 }
1da177e4
LT		 3265
3266 /* Other type of interrupts are not being handled now, TODO */
3267}
3268
20346722 3269/**
1da177e4 3270 * wait_for_cmd_complete - waits for a command to complete.
20346722 3271 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3272 * s2io_nic structure.
20346722
K		 3273 * Description: Function that waits for a command to Write into RMAC
3274 * ADDR DATA registers to be completed and returns either success or
3275 * error depending on whether the command was complete or not.
1da177e4
LT		 3276 * Return value:
3277 * SUCCESS on success and FAILURE on failure.
3278 */
3279
9fc93a41
SS		 3280static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3281 int bit_state)
1da177e4 3282{
9fc93a41 3283 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3284 u64 val64;
3285
9fc93a41
SS		 3286 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3287 return FAILURE;
3288
3289 do {
c92ca04b 3290 val64 = readq(addr);
9fc93a41
SS		 3291 if (bit_state == S2IO_BIT_RESET) {
3292 if (!(val64 & busy_bit)) {
3293 ret = SUCCESS;
3294 break;
3295 }
3296 } else {
3297 if (!(val64 & busy_bit)) {
3298 ret = SUCCESS;
3299 break;
3300 }
1da177e4 3301 }
c92ca04b
AR		 3302
3303 if(in_interrupt())
9fc93a41 3304 mdelay(delay);
c92ca04b 3305 else
9fc93a41 3306 msleep(delay);
c92ca04b 3307
9fc93a41
SS		 3308 if (++cnt >= 10)
3309 delay = 50;
3310 } while (cnt < 20);
1da177e4
LT		 3311 return ret;
3312}
19a60522
SS		 3313/*
3314 * check_pci_device_id - Checks if the device id is supported
3315 * @id : device id
3316 * Description: Function to check if the pci device id is supported by driver.
3317 * Return value: Actual device id if supported else PCI_ANY_ID
3318 */
3319static u16 check_pci_device_id(u16 id)
3320{
3321 switch (id) {
3322 case PCI_DEVICE_ID_HERC_WIN:
3323 case PCI_DEVICE_ID_HERC_UNI:
3324 return XFRAME_II_DEVICE;
3325 case PCI_DEVICE_ID_S2IO_UNI:
3326 case PCI_DEVICE_ID_S2IO_WIN:
3327 return XFRAME_I_DEVICE;
3328 default:
3329 return PCI_ANY_ID;
3330 }
3331}
1da177e4 3332
20346722
K		 3333/**
3334 * s2io_reset - Resets the card.
1da177e4
LT		 3335 * @sp : private member of the device structure.
3336 * Description: Function to Reset the card. This function then also
20346722 3337 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3338 * the card reset also resets the configuration space.
3339 * Return value:
3340 * void.
3341 */
3342
1ee6dd77 3343static void s2io_reset(struct s2io_nic * sp)
1da177e4 3344{
1ee6dd77 3345 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3346 u64 val64;
5e25b9dd 3347 u16 subid, pci_cmd;
19a60522
SS		 3348 int i;
3349 u16 val16;
491976b2
SH		 3350 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3351 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3352
19a60522
SS		 3353 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3354 __FUNCTION__, sp->dev->name);
1da177e4 3355
0b1f7ebe 3356 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3357 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3358
19a60522
SS		 3359 if (sp->device_type == XFRAME_II_DEVICE) {
3360 int ret;
3361 ret = pci_set_power_state(sp->pdev, 3);
3362 if (!ret)
3363 ret = pci_set_power_state(sp->pdev, 0);
3364 else {
3365 DBG_PRINT(ERR_DBG,"%s PME based SW_Reset failed!\n",
3366 __FUNCTION__);
3367 goto old_way;
3368 }
3369 msleep(20);
3370 goto new_way;
3371 }
3372old_way:
1da177e4
LT		 3373 val64 = SW_RESET_ALL;
3374 writeq(val64, &bar0->sw_reset);
19a60522 3375new_way:
c92ca04b
AR		 3376 if (strstr(sp->product_name, "CX4")) {
3377 msleep(750);
3378 }
19a60522
SS		 3379 msleep(250);
3380 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3381
19a60522
SS		 3382 /* Restore the PCI state saved during initialization. */
3383 pci_restore_state(sp->pdev);
3384 pci_read_config_word(sp->pdev, 0x2, &val16);
3385 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3386 break;
3387 msleep(200);
3388 }
1da177e4 3389
19a60522
SS		 3390 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3391 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3392 }
3393
3394 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3395
3396 s2io_init_pci(sp);
1da177e4 3397
20346722
K		 3398 /* Set swapper to enable I/O register access */
3399 s2io_set_swapper(sp);
3400
cc6e7c44
RA		 3401 /* Restore the MSIX table entries from local variables */
3402 restore_xmsi_data(sp);
3403
5e25b9dd 3404 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3405 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3406 /* Clear "detected parity error" bit */
303bcb4b 3407 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3408
303bcb4b
K		 3409 /* Clearing PCIX Ecc status register */
3410 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3411
303bcb4b
K		 3412 /* Clearing PCI_STATUS error reflected here */
3413 writeq(BIT(62), &bar0->txpic_int_reg);
3414 }
5e25b9dd 3415
20346722
K		 3416 /* Reset device statistics maintained by OS */
3417 memset(&sp->stats, 0, sizeof (struct net_device_stats));
491976b2
SH		 3418
3419 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3420 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3421 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3422 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
363dc367 3423 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
491976b2
SH		 3424 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3425 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3426 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3427 /* save link up/down time/cnt, reset/memory/watchdog cnt */
363dc367 3428 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
491976b2
SH		 3429 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3430 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3431 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3432 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3433 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
363dc367 3434 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
491976b2
SH		 3435 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3436 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3437 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
20346722 3438
1da177e4
LT		 3439 /* SXE-002: Configure link and activity LED to turn it off */
3440 subid = sp->pdev->subsystem_device;
541ae68f
K		 3441 if (((subid & 0xFF) >= 0x07) &&
3442 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3443 val64 = readq(&bar0->gpio_control);
3444 val64 |= 0x0000800000000000ULL;
3445 writeq(val64, &bar0->gpio_control);
3446 val64 = 0x0411040400000000ULL;
509a2671 3447 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3448 }
3449
541ae68f
K		 3450 /*
3451 * Clear spurious ECC interrupts that would have occured on
3452 * XFRAME II cards after reset.
3453 */
3454 if (sp->device_type == XFRAME_II_DEVICE) {
3455 val64 = readq(&bar0->pcc_err_reg);
3456 writeq(val64, &bar0->pcc_err_reg);
3457 }
3458
d8d70caf
SS		 3459 /* restore the previously assigned mac address */
3460 s2io_set_mac_addr(sp->dev, (u8 *)&sp->def_mac_addr[0].mac_addr);
3461
1da177e4
LT		 3462 sp->device_enabled_once = FALSE;
3463}
3464
3465/**
20346722
K		 3466 * s2io_set_swapper - to set the swapper controle on the card
3467 * @sp : private member of the device structure,
1da177e4 3468 * pointer to the s2io_nic structure.
20346722 3469 * Description: Function to set the swapper control on the card
1da177e4
LT		 3470 * correctly depending on the 'endianness' of the system.
3471 * Return value:
3472 * SUCCESS on success and FAILURE on failure.
3473 */
3474
1ee6dd77 3475static int s2io_set_swapper(struct s2io_nic * sp)
1da177e4
LT		 3476{
3477 struct net_device *dev = sp->dev;
1ee6dd77 3478 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3479 u64 val64, valt, valr;
3480
20346722 3481 /*
1da177e4
LT		 3482 * Set proper endian settings and verify the same by reading
3483 * the PIF Feed-back register.
3484 */
3485
3486 val64 = readq(&bar0->pif_rd_swapper_fb);
3487 if (val64 != 0x0123456789ABCDEFULL) {
3488 int i = 0;
3489 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3490 0x8100008181000081ULL, /* FE=1, SE=0 */
3491 0x4200004242000042ULL, /* FE=0, SE=1 */
3492 0}; /* FE=0, SE=0 */
3493
3494 while(i<4) {
3495 writeq(value[i], &bar0->swapper_ctrl);
3496 val64 = readq(&bar0->pif_rd_swapper_fb);
3497 if (val64 == 0x0123456789ABCDEFULL)
3498 break;
3499 i++;
3500 }
3501 if (i == 4) {
3502 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3503 dev->name);
3504 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3505 (unsigned long long) val64);
3506 return FAILURE;
3507 }
3508 valr = value[i];
3509 } else {
3510 valr = readq(&bar0->swapper_ctrl);
3511 }
3512
3513 valt = 0x0123456789ABCDEFULL;
3514 writeq(valt, &bar0->xmsi_address);
3515 val64 = readq(&bar0->xmsi_address);
3516
3517 if(val64 != valt) {
3518 int i = 0;
3519 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3520 0x0081810000818100ULL, /* FE=1, SE=0 */
3521 0x0042420000424200ULL, /* FE=0, SE=1 */
3522 0}; /* FE=0, SE=0 */
3523
3524 while(i<4) {
3525 writeq((value[i] | valr), &bar0->swapper_ctrl);
3526 writeq(valt, &bar0->xmsi_address);
3527 val64 = readq(&bar0->xmsi_address);
3528 if(val64 == valt)
3529 break;
3530 i++;
3531 }
3532 if(i == 4) {
20346722 3533 unsigned long long x = val64;
1da177e4 3534 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3535 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3536 return FAILURE;
3537 }
3538 }
3539 val64 = readq(&bar0->swapper_ctrl);
3540 val64 &= 0xFFFF000000000000ULL;
3541
3542#ifdef __BIG_ENDIAN
20346722
K		 3543 /*
3544 * The device by default set to a big endian format, so a
1da177e4
LT		 3545 * big endian driver need not set anything.
3546 */
3547 val64 |= (SWAPPER_CTRL_TXP_FE |
3548 SWAPPER_CTRL_TXP_SE |
3549 SWAPPER_CTRL_TXD_R_FE |
3550 SWAPPER_CTRL_TXD_W_FE |
3551 SWAPPER_CTRL_TXF_R_FE |
3552 SWAPPER_CTRL_RXD_R_FE |
3553 SWAPPER_CTRL_RXD_W_FE |
3554 SWAPPER_CTRL_RXF_W_FE |
3555 SWAPPER_CTRL_XMSI_FE |
1da177e4 3556 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
92383340 3557 if (sp->intr_type == INTA)
cc6e7c44 3558 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3559 writeq(val64, &bar0->swapper_ctrl);
3560#else
20346722 3561 /*
1da177e4 3562 * Initially we enable all bits to make it accessible by the
20346722 3563 * driver, then we selectively enable only those bits that
1da177e4
LT		 3564 * we want to set.
3565 */
3566 val64 |= (SWAPPER_CTRL_TXP_FE |
3567 SWAPPER_CTRL_TXP_SE |
3568 SWAPPER_CTRL_TXD_R_FE |
3569 SWAPPER_CTRL_TXD_R_SE |
3570 SWAPPER_CTRL_TXD_W_FE |
3571 SWAPPER_CTRL_TXD_W_SE |
3572 SWAPPER_CTRL_TXF_R_FE |
3573 SWAPPER_CTRL_RXD_R_FE |
3574 SWAPPER_CTRL_RXD_R_SE |
3575 SWAPPER_CTRL_RXD_W_FE |
3576 SWAPPER_CTRL_RXD_W_SE |
3577 SWAPPER_CTRL_RXF_W_FE |
3578 SWAPPER_CTRL_XMSI_FE |
1da177e4 3579 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
cc6e7c44
RA		 3580 if (sp->intr_type == INTA)
3581 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3582 writeq(val64, &bar0->swapper_ctrl);
3583#endif
3584 val64 = readq(&bar0->swapper_ctrl);
3585
20346722
K		 3586 /*
3587 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3588 * feedback register.
3589 */
3590 val64 = readq(&bar0->pif_rd_swapper_fb);
3591 if (val64 != 0x0123456789ABCDEFULL) {
3592 /* Endian settings are incorrect, calls for another dekko. */
3593 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3594 dev->name);
3595 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3596 (unsigned long long) val64);
3597 return FAILURE;
3598 }
3599
3600 return SUCCESS;
3601}
3602
1ee6dd77 3603static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3604{
1ee6dd77 3605 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3606 u64 val64;
3607 int ret = 0, cnt = 0;
3608
3609 do {
3610 val64 = readq(&bar0->xmsi_access);
3611 if (!(val64 & BIT(15)))
3612 break;
3613 mdelay(1);
3614 cnt++;
3615 } while(cnt < 5);
3616 if (cnt == 5) {
3617 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3618 ret = 1;
3619 }
3620
3621 return ret;
3622}
3623
1ee6dd77 3624static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3625{
1ee6dd77 3626 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3627 u64 val64;
3628 int i;
3629
75c30b13 3630 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3631 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3632 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3633 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3634 writeq(val64, &bar0->xmsi_access);
3635 if (wait_for_msix_trans(nic, i)) {
3636 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3637 continue;
3638 }
3639 }
3640}
3641
1ee6dd77 3642static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3643{
1ee6dd77 3644 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3645 u64 val64, addr, data;
3646 int i;
3647
3648 /* Store and display */
75c30b13 3649 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3650 val64 = (BIT(15) | vBIT(i, 26, 6));
3651 writeq(val64, &bar0->xmsi_access);
3652 if (wait_for_msix_trans(nic, i)) {
3653 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3654 continue;
3655 }
3656 addr = readq(&bar0->xmsi_address);
3657 data = readq(&bar0->xmsi_data);
3658 if (addr && data) {
3659 nic->msix_info[i].addr = addr;
3660 nic->msix_info[i].data = data;
3661 }
3662 }
3663}
3664
1ee6dd77 3665int s2io_enable_msi(struct s2io_nic *nic)
cc6e7c44 3666{
1ee6dd77 3667 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3668 u16 msi_ctrl, msg_val;
3669 struct config_param *config = &nic->config;
3670 struct net_device *dev = nic->dev;
3671 u64 val64, tx_mat, rx_mat;
3672 int i, err;
3673
3674 val64 = readq(&bar0->pic_control);
3675 val64 &= ~BIT(1);
3676 writeq(val64, &bar0->pic_control);
3677
3678 err = pci_enable_msi(nic->pdev);
3679 if (err) {
3680 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3681 nic->dev->name);
3682 return err;
3683 }
3684
3685 /*
3686 * Enable MSI and use MSI-1 in stead of the standard MSI-0
3687 * for interrupt handling.
3688 */
3689 pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3690 msg_val ^= 0x1;
3691 pci_write_config_word(nic->pdev, 0x4c, msg_val);
3692 pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3693
3694 pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3695 msi_ctrl |= 0x10;
3696 pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3697
3698 /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3699 tx_mat = readq(&bar0->tx_mat0_n[0]);
3700 for (i=0; i<config->tx_fifo_num; i++) {
3701 tx_mat |= TX_MAT_SET(i, 1);
3702 }
3703 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3704
3705 rx_mat = readq(&bar0->rx_mat);
3706 for (i=0; i<config->rx_ring_num; i++) {
3707 rx_mat |= RX_MAT_SET(i, 1);
3708 }
3709 writeq(rx_mat, &bar0->rx_mat);
3710
3711 dev->irq = nic->pdev->irq;
3712 return 0;
3713}
3714
1ee6dd77 3715static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3716{
1ee6dd77 3717 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3718 u64 tx_mat, rx_mat;
3719 u16 msi_control; /* Temp variable */
3720 int ret, i, j, msix_indx = 1;
3721
3722 nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3723 GFP_KERNEL);
3724 if (nic->entries == NULL) {
491976b2
SH		 3725 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3726 __FUNCTION__);
c53d4945 3727 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44
RA		 3728 return -ENOMEM;
3729 }
491976b2
SH		 3730 nic->mac_control.stats_info->sw_stat.mem_allocated
3731 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3732 memset(nic->entries, 0,MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44
RA		 3733
3734 nic->s2io_entries =
3735 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3736 GFP_KERNEL);
3737 if (nic->s2io_entries == NULL) {
491976b2
SH		 3738 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3739 __FUNCTION__);
c53d4945 3740 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44 3741 kfree(nic->entries);
491976b2
SH		 3742 nic->mac_control.stats_info->sw_stat.mem_freed
3743 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44
RA		 3744 return -ENOMEM;
3745 }
491976b2
SH		 3746 nic->mac_control.stats_info->sw_stat.mem_allocated
3747 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3748 memset(nic->s2io_entries, 0,
3749 MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3750
3751 for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3752 nic->entries[i].entry = i;
3753 nic->s2io_entries[i].entry = i;
3754 nic->s2io_entries[i].arg = NULL;
3755 nic->s2io_entries[i].in_use = 0;
3756 }
3757
3758 tx_mat = readq(&bar0->tx_mat0_n[0]);
3759 for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3760 tx_mat |= TX_MAT_SET(i, msix_indx);
3761 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3762 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3763 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3764 }
3765 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3766
3767 if (!nic->config.bimodal) {
3768 rx_mat = readq(&bar0->rx_mat);
3769 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3770 rx_mat |= RX_MAT_SET(j, msix_indx);
491976b2
SH		 3771 nic->s2io_entries[msix_indx].arg
3772 = &nic->mac_control.rings[j];
cc6e7c44
RA		 3773 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3774 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3775 }
3776 writeq(rx_mat, &bar0->rx_mat);
3777 } else {
3778 tx_mat = readq(&bar0->tx_mat0_n[7]);
3779 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3780 tx_mat |= TX_MAT_SET(i, msix_indx);
491976b2
SH		 3781 nic->s2io_entries[msix_indx].arg
3782 = &nic->mac_control.rings[j];
cc6e7c44
RA		 3783 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3784 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3785 }
3786 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3787 }
3788
c92ca04b 3789 nic->avail_msix_vectors = 0;
cc6e7c44 3790 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
c92ca04b
AR		 3791 /* We fail init if error or we get less vectors than min required */
3792 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3793 nic->avail_msix_vectors = ret;
3794 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3795 }
cc6e7c44
RA		 3796 if (ret) {
3797 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3798 kfree(nic->entries);
491976b2
SH		 3799 nic->mac_control.stats_info->sw_stat.mem_freed
3800 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44 3801 kfree(nic->s2io_entries);
491976b2
SH		 3802 nic->mac_control.stats_info->sw_stat.mem_freed
3803 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3804 nic->entries = NULL;
3805 nic->s2io_entries = NULL;
c92ca04b 3806 nic->avail_msix_vectors = 0;
cc6e7c44
RA		 3807 return -ENOMEM;
3808 }
c92ca04b
AR		 3809 if (!nic->avail_msix_vectors)
3810 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
cc6e7c44
RA		 3811
3812 /*
3813 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3814 * in the herc NIC. (Temp change, needs to be removed later)
3815 */
3816 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3817 msi_control |= 0x1; /* Enable MSI */
3818 pci_write_config_word(nic->pdev, 0x42, msi_control);
3819
3820 return 0;
3821}
3822
1da177e4
LT		 3823/* ********************************************************* *
3824 * Functions defined below concern the OS part of the driver *
3825 * ********************************************************* */
3826
20346722 3827/**
1da177e4
LT		 3828 * s2io_open - open entry point of the driver
3829 * @dev : pointer to the device structure.
3830 * Description:
3831 * This function is the open entry point of the driver. It mainly calls a
3832 * function to allocate Rx buffers and inserts them into the buffer
20346722 3833 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3834 * Return value:
3835 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3836 * file on failure.
3837 */
3838
ac1f60db 3839static int s2io_open(struct net_device *dev)
1da177e4 3840{
1ee6dd77 3841 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 3842 int err = 0;
3843
20346722
K		 3844 /*
3845 * Make sure you have link off by default every time
1da177e4
LT		 3846 * Nic is initialized
3847 */
3848 netif_carrier_off(dev);
0b1f7ebe 3849 sp->last_link_state = 0;
1da177e4
LT		 3850
3851 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 3852 err = s2io_card_up(sp);
3853 if (err) {
1da177e4
LT		 3854 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3855 dev->name);
e6a8fee2 3856 goto hw_init_failed;
1da177e4
LT		 3857 }
3858
3859 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3860 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 3861 s2io_card_down(sp);
20346722 3862 err = -ENODEV;
e6a8fee2 3863 goto hw_init_failed;
1da177e4
LT		 3864 }
3865
3866 netif_start_queue(dev);
3867 return 0;
20346722 3868
20346722 3869hw_init_failed:
cc6e7c44 3870 if (sp->intr_type == MSI_X) {
491976b2 3871 if (sp->entries) {
cc6e7c44 3872 kfree(sp->entries);
491976b2
SH		 3873 sp->mac_control.stats_info->sw_stat.mem_freed
3874 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3875 }
3876 if (sp->s2io_entries) {
cc6e7c44 3877 kfree(sp->s2io_entries);
491976b2
SH		 3878 sp->mac_control.stats_info->sw_stat.mem_freed
3879 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3880 }
cc6e7c44 3881 }
20346722 3882 return err;
1da177e4
LT		 3883}
3884
3885/**
3886 * s2io_close -close entry point of the driver
3887 * @dev : device pointer.
3888 * Description:
3889 * This is the stop entry point of the driver. It needs to undo exactly
3890 * whatever was done by the open entry point,thus it's usually referred to
3891 * as the close function.Among other things this function mainly stops the
3892 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3893 * Return value:
3894 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3895 * file on failure.
3896 */
3897
ac1f60db 3898static int s2io_close(struct net_device *dev)
1da177e4 3899{
1ee6dd77 3900 struct s2io_nic *sp = dev->priv;
cc6e7c44 3901
1da177e4
LT		 3902 netif_stop_queue(dev);
3903 /* Reset card, kill tasklet and free Tx and Rx buffers. */
e6a8fee2 3904 s2io_card_down(sp);
cc6e7c44 3905
1da177e4
LT		 3906 return 0;
3907}
3908
3909/**
3910 * s2io_xmit - Tx entry point of te driver
3911 * @skb : the socket buffer containing the Tx data.
3912 * @dev : device pointer.
3913 * Description :
3914 * This function is the Tx entry point of the driver. S2IO NIC supports
3915 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3916 * NOTE: when device cant queue the pkt,just the trans_start variable will
3917 * not be upadted.
3918 * Return value:
3919 * 0 on success & 1 on failure.
3920 */
3921
ac1f60db 3922static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 3923{
1ee6dd77 3924 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 3925 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3926 register u64 val64;
1ee6dd77
RB		 3927 struct TxD *txdp;
3928 struct TxFIFO_element __iomem *tx_fifo;
1da177e4 3929 unsigned long flags;
be3a6b02
K		 3930 u16 vlan_tag = 0;
3931 int vlan_priority = 0;
1ee6dd77 3932 struct mac_info *mac_control;
1da177e4 3933 struct config_param *config;
75c30b13 3934 int offload_type;
1da177e4
LT		 3935
3936 mac_control = &sp->mac_control;
3937 config = &sp->config;
3938
20346722 3939 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 3940
3941 if (unlikely(skb->len <= 0)) {
3942 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3943 dev_kfree_skb_any(skb);
3944 return 0;
3945}
3946
1da177e4 3947 spin_lock_irqsave(&sp->tx_lock, flags);
1da177e4 3948 if (atomic_read(&sp->card_state) == CARD_DOWN) {
20346722 3949 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4
LT		 3950 dev->name);
3951 spin_unlock_irqrestore(&sp->tx_lock, flags);
20346722
K		 3952 dev_kfree_skb(skb);
3953 return 0;
1da177e4
LT		 3954 }
3955
3956 queue = 0;
be3a6b02
K		 3957 /* Get Fifo number to Transmit based on vlan priority */
3958 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3959 vlan_tag = vlan_tx_tag_get(skb);
3960 vlan_priority = vlan_tag >> 13;
3961 queue = config->fifo_mapping[vlan_priority];
3962 }
3963
20346722
K		 3964 put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3965 get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
1ee6dd77 3966 txdp = (struct TxD *) mac_control->fifos[queue].list_info[put_off].
20346722
K		 3967 list_virt_addr;
3968
3969 queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
1da177e4 3970 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9
AR		 3971 if (txdp->Host_Control ||
3972 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 3973 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
1da177e4
LT		 3974 netif_stop_queue(dev);
3975 dev_kfree_skb(skb);
3976 spin_unlock_irqrestore(&sp->tx_lock, flags);
3977 return 0;
3978 }
0b1f7ebe 3979
75c30b13 3980 offload_type = s2io_offload_type(skb);
75c30b13 3981 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 3982 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 3983 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 3984 }
84fa7933 3985 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 3986 txdp->Control_2 |=
3987 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3988 TXD_TX_CKO_UDP_EN);
3989 }
fed5eccd
AR		 3990 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
3991 txdp->Control_1 |= TXD_LIST_OWN_XENA;
1da177e4 3992 txdp->Control_2 |= config->tx_intr_type;
d8892c6e 3993
be3a6b02
K		 3994 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3995 txdp->Control_2 |= TXD_VLAN_ENABLE;
3996 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3997 }
3998
fed5eccd 3999 frg_len = skb->len - skb->data_len;
75c30b13 4000 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4001 int ufo_size;
4002
75c30b13 4003 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4004 ufo_size &= ~7;
4005 txdp->Control_1 |= TXD_UFO_EN;
4006 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4007 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4008#ifdef __BIG_ENDIAN
4009 sp->ufo_in_band_v[put_off] =
4010 (u64)skb_shinfo(skb)->ip6_frag_id;
4011#else
4012 sp->ufo_in_band_v[put_off] =
4013 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
4014#endif
4015 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
4016 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4017 sp->ufo_in_band_v,
4018 sizeof(u64), PCI_DMA_TODEVICE);
4019 txdp++;
fed5eccd 4020 }
1da177e4 4021
fed5eccd
AR		 4022 txdp->Buffer_Pointer = pci_map_single
4023 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
4024 txdp->Host_Control = (unsigned long) skb;
4025 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4026 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4027 txdp->Control_1 |= TXD_UFO_EN;
4028
4029 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4030 /* For fragmented SKB. */
4031 for (i = 0; i < frg_cnt; i++) {
4032 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe
K		 4033 /* A '0' length fragment will be ignored */
4034 if (!frag->size)
4035 continue;
1da177e4
LT		 4036 txdp++;
4037 txdp->Buffer_Pointer = (u64) pci_map_page
4038 (sp->pdev, frag->page, frag->page_offset,
4039 frag->size, PCI_DMA_TODEVICE);
efd51b5c 4040 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4041 if (offload_type == SKB_GSO_UDP)
fed5eccd 4042 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4043 }
4044 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4045
75c30b13 4046 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4047 frg_cnt++; /* as Txd0 was used for inband header */
4048
1da177e4 4049 tx_fifo = mac_control->tx_FIFO_start[queue];
20346722 4050 val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
1da177e4
LT		 4051 writeq(val64, &tx_fifo->TxDL_Pointer);
4052
4053 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4054 TX_FIFO_LAST_LIST);
75c30b13 4055 if (offload_type)
fed5eccd 4056 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4057
1da177e4
LT		 4058 writeq(val64, &tx_fifo->List_Control);
4059
303bcb4b
K		 4060 mmiowb();
4061
1da177e4 4062 put_off++;
863c11a9
AR		 4063 if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
4064 put_off = 0;
20346722 4065 mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
1da177e4
LT		 4066
4067 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4068 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
bd1034f0 4069 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
1da177e4
LT		 4070 DBG_PRINT(TX_DBG,
4071 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4072 put_off, get_off);
4073 netif_stop_queue(dev);
4074 }
491976b2 4075 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
1da177e4
LT		 4076 dev->trans_start = jiffies;
4077 spin_unlock_irqrestore(&sp->tx_lock, flags);
4078
4079 return 0;
4080}
4081
25fff88e
K		 4082static void
4083s2io_alarm_handle(unsigned long data)
4084{
1ee6dd77 4085 struct s2io_nic *sp = (struct s2io_nic *)data;
25fff88e
K		 4086
4087 alarm_intr_handler(sp);
4088 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4089}
4090
1ee6dd77 4091static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
75c30b13
AR		 4092{
4093 int rxb_size, level;
4094
4095 if (!sp->lro) {
4096 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4097 level = rx_buffer_level(sp, rxb_size, rng_n);
4098
4099 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4100 int ret;
4101 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4102 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4103 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
0c61ed5f 4104 DBG_PRINT(INFO_DBG, "Out of memory in %s",
75c30b13
AR		 4105 __FUNCTION__);
4106 clear_bit(0, (&sp->tasklet_status));
4107 return -1;
4108 }
4109 clear_bit(0, (&sp->tasklet_status));
4110 } else if (level == LOW)
4111 tasklet_schedule(&sp->task);
4112
4113 } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
0c61ed5f
RV		 4114 DBG_PRINT(INFO_DBG, "%s:Out of memory", sp->dev->name);
4115 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
75c30b13
AR		 4116 }
4117 return 0;
4118}
4119
7d12e780 4120static irqreturn_t s2io_msi_handle(int irq, void *dev_id)
cc6e7c44
RA		 4121{
4122 struct net_device *dev = (struct net_device *) dev_id;
1ee6dd77 4123 struct s2io_nic *sp = dev->priv;
cc6e7c44 4124 int i;
1ee6dd77 4125 struct mac_info *mac_control;
cc6e7c44
RA		 4126 struct config_param *config;
4127
4128 atomic_inc(&sp->isr_cnt);
4129 mac_control = &sp->mac_control;
4130 config = &sp->config;
4131 DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
4132
4133 /* If Intr is because of Rx Traffic */
4134 for (i = 0; i < config->rx_ring_num; i++)
4135 rx_intr_handler(&mac_control->rings[i]);
4136
4137 /* If Intr is because of Tx Traffic */
4138 for (i = 0; i < config->tx_fifo_num; i++)
4139 tx_intr_handler(&mac_control->fifos[i]);
4140
4141 /*
4142 * If the Rx buffer count is below the panic threshold then
4143 * reallocate the buffers from the interrupt handler itself,
4144 * else schedule a tasklet to reallocate the buffers.
4145 */
75c30b13
AR		 4146 for (i = 0; i < config->rx_ring_num; i++)
4147 s2io_chk_rx_buffers(sp, i);
cc6e7c44
RA		 4148
4149 atomic_dec(&sp->isr_cnt);
4150 return IRQ_HANDLED;
4151}
4152
7d12e780 4153static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4154{
1ee6dd77
RB		 4155 struct ring_info *ring = (struct ring_info *)dev_id;
4156 struct s2io_nic *sp = ring->nic;
cc6e7c44
RA		 4157
4158 atomic_inc(&sp->isr_cnt);
cc6e7c44 4159
75c30b13
AR		 4160 rx_intr_handler(ring);
4161 s2io_chk_rx_buffers(sp, ring->ring_no);
7d3d0439 4162
cc6e7c44 4163 atomic_dec(&sp->isr_cnt);
cc6e7c44
RA		 4164 return IRQ_HANDLED;
4165}
4166
7d12e780 4167static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4168{
1ee6dd77
RB		 4169 struct fifo_info *fifo = (struct fifo_info *)dev_id;
4170 struct s2io_nic *sp = fifo->nic;
cc6e7c44
RA		 4171
4172 atomic_inc(&sp->isr_cnt);
4173 tx_intr_handler(fifo);
4174 atomic_dec(&sp->isr_cnt);
4175 return IRQ_HANDLED;
4176}
1ee6dd77 4177static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4178{
1ee6dd77 4179 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d
K		 4180 u64 val64;
4181
4182 val64 = readq(&bar0->pic_int_status);
4183 if (val64 & PIC_INT_GPIO) {
4184 val64 = readq(&bar0->gpio_int_reg);
4185 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4186 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4187 /*
4188 * This is unstable state so clear both up/down
4189 * interrupt and adapter to re-evaluate the link state.
4190 */
a371a07d
K		 4191 val64 |= GPIO_INT_REG_LINK_DOWN;
4192 val64 |= GPIO_INT_REG_LINK_UP;
4193 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4194 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4195 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4196 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4197 writeq(val64, &bar0->gpio_int_mask);
a371a07d 4198 }
c92ca04b
AR		 4199 else if (val64 & GPIO_INT_REG_LINK_UP) {
4200 val64 = readq(&bar0->adapter_status);
c92ca04b 4201 /* Enable Adapter */
19a60522
SS		 4202 val64 = readq(&bar0->adapter_control);
4203 val64 |= ADAPTER_CNTL_EN;
4204 writeq(val64, &bar0->adapter_control);
4205 val64 |= ADAPTER_LED_ON;
4206 writeq(val64, &bar0->adapter_control);
4207 if (!sp->device_enabled_once)
4208 sp->device_enabled_once = 1;
c92ca04b 4209
19a60522
SS		 4210 s2io_link(sp, LINK_UP);
4211 /*
4212 * unmask link down interrupt and mask link-up
4213 * intr
4214 */
4215 val64 = readq(&bar0->gpio_int_mask);
4216 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4217 val64 |= GPIO_INT_MASK_LINK_UP;
4218 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4219
c92ca04b
AR		 4220 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4221 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4222 s2io_link(sp, LINK_DOWN);
4223 /* Link is down so unmaks link up interrupt */
4224 val64 = readq(&bar0->gpio_int_mask);
4225 val64 &= ~GPIO_INT_MASK_LINK_UP;
4226 val64 |= GPIO_INT_MASK_LINK_DOWN;
4227 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4228
4229 /* turn off LED */
4230 val64 = readq(&bar0->adapter_control);
4231 val64 = val64 &(~ADAPTER_LED_ON);
4232 writeq(val64, &bar0->adapter_control);
a371a07d
K		 4233 }
4234 }
c92ca04b 4235 val64 = readq(&bar0->gpio_int_mask);
a371a07d
K		 4236}
4237
1da177e4
LT		 4238/**
4239 * s2io_isr - ISR handler of the device .
4240 * @irq: the irq of the device.
4241 * @dev_id: a void pointer to the dev structure of the NIC.
20346722
K		 4242 * Description: This function is the ISR handler of the device. It
4243 * identifies the reason for the interrupt and calls the relevant
4244 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4245 * recv buffers, if their numbers are below the panic value which is
4246 * presently set to 25% of the original number of rcv buffers allocated.
4247 * Return value:
20346722 4248 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4249 * IRQ_NONE: will be returned if interrupt is not from our device
4250 */
7d12e780 4251static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4
LT		 4252{
4253 struct net_device *dev = (struct net_device *) dev_id;
1ee6dd77
RB		 4254 struct s2io_nic *sp = dev->priv;
4255 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4256 int i;
19a60522 4257 u64 reason = 0;
1ee6dd77 4258 struct mac_info *mac_control;
1da177e4
LT		 4259 struct config_param *config;
4260
d796fdb7
LV		 4261 /* Pretend we handled any irq's from a disconnected card */
4262 if (pci_channel_offline(sp->pdev))
4263 return IRQ_NONE;
4264
7ba013ac 4265 atomic_inc(&sp->isr_cnt);
1da177e4
LT		 4266 mac_control = &sp->mac_control;
4267 config = &sp->config;
4268
20346722 4269 /*
1da177e4
LT		 4270 * Identify the cause for interrupt and call the appropriate
4271 * interrupt handler. Causes for the interrupt could be;
4272 * 1. Rx of packet.
4273 * 2. Tx complete.
4274 * 3. Link down.
20346722 4275 * 4. Error in any functional blocks of the NIC.
1da177e4
LT		 4276 */
4277 reason = readq(&bar0->general_int_status);
4278
4279 if (!reason) {
19a60522
SS		 4280 /* The interrupt was not raised by us. */
4281 atomic_dec(&sp->isr_cnt);
4282 return IRQ_NONE;
4283 }
4284 else if (unlikely(reason == S2IO_MINUS_ONE) ) {
4285 /* Disable device and get out */
7ba013ac 4286 atomic_dec(&sp->isr_cnt);
1da177e4
LT		 4287 return IRQ_NONE;
4288 }
5d3213cc 4289
db874e65
SS		 4290 if (napi) {
4291 if (reason & GEN_INTR_RXTRAFFIC) {
19a60522 4292 if ( likely ( netif_rx_schedule_prep(dev)) ) {
db874e65 4293 __netif_rx_schedule(dev);
19a60522 4294 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
db874e65 4295 }
19a60522
SS		 4296 else
4297 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
db874e65
SS		 4298 }
4299 } else {
4300 /*
4301 * Rx handler is called by default, without checking for the
4302 * cause of interrupt.
4303 * rx_traffic_int reg is an R1 register, writing all 1's
4304 * will ensure that the actual interrupt causing bit get's
4305 * cleared and hence a read can be avoided.
4306 */
19a60522
SS		 4307 if (reason & GEN_INTR_RXTRAFFIC)
4308 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4309
db874e65
SS		 4310 for (i = 0; i < config->rx_ring_num; i++) {
4311 rx_intr_handler(&mac_control->rings[i]);
1da177e4
LT		 4312 }
4313 }
1da177e4 4314
863c11a9
AR		 4315 /*
4316 * tx_traffic_int reg is an R1 register, writing all 1's
4317 * will ensure that the actual interrupt causing bit get's
4318 * cleared and hence a read can be avoided.
4319 */
19a60522
SS		 4320 if (reason & GEN_INTR_TXTRAFFIC)
4321 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
fe113638 4322
863c11a9
AR		 4323 for (i = 0; i < config->tx_fifo_num; i++)
4324 tx_intr_handler(&mac_control->fifos[i]);
20346722 4325
a371a07d
K		 4326 if (reason & GEN_INTR_TXPIC)
4327 s2io_txpic_intr_handle(sp);
20346722
K		 4328 /*
4329 * If the Rx buffer count is below the panic threshold then
4330 * reallocate the buffers from the interrupt handler itself,
1da177e4
LT		 4331 * else schedule a tasklet to reallocate the buffers.
4332 */
db874e65
SS		 4333 if (!napi) {
4334 for (i = 0; i < config->rx_ring_num; i++)
4335 s2io_chk_rx_buffers(sp, i);
4336 }
4337
4338 writeq(0, &bar0->general_int_mask);
4339 readl(&bar0->general_int_status);
4340
7ba013ac 4341 atomic_dec(&sp->isr_cnt);
1da177e4
LT		 4342 return IRQ_HANDLED;
4343}
4344
7ba013ac
K		 4345/**
4346 * s2io_updt_stats -
4347 */
1ee6dd77 4348static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4349{
1ee6dd77 4350 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac
K		 4351 u64 val64;
4352 int cnt = 0;
4353
4354 if (atomic_read(&sp->card_state) == CARD_UP) {
4355 /* Apprx 30us on a 133 MHz bus */
4356 val64 = SET_UPDT_CLICKS(10) |
4357 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4358 writeq(val64, &bar0->stat_cfg);
4359 do {
4360 udelay(100);
4361 val64 = readq(&bar0->stat_cfg);
4362 if (!(val64 & BIT(0)))
4363 break;
4364 cnt++;
4365 if (cnt == 5)
4366 break; /* Updt failed */
4367 } while(1);
363dc367 4368 }
7ba013ac
K		 4369}
4370
1da177e4 4371/**
20346722 4372 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4373 * @dev : pointer to the device structure.
4374 * Description:
20346722 4375 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4376 * structure and returns a pointer to the same.
4377 * Return value:
4378 * pointer to the updated net_device_stats structure.
4379 */
4380
ac1f60db 4381static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4382{
1ee6dd77
RB		 4383 struct s2io_nic *sp = dev->priv;
4384 struct mac_info *mac_control;
1da177e4
LT		 4385 struct config_param *config;
4386
20346722 4387
1da177e4
LT		 4388 mac_control = &sp->mac_control;
4389 config = &sp->config;
4390
7ba013ac
K		 4391 /* Configure Stats for immediate updt */
4392 s2io_updt_stats(sp);
4393
4394 sp->stats.tx_packets =
4395 le32_to_cpu(mac_control->stats_info->tmac_frms);
20346722
K		 4396 sp->stats.tx_errors =
4397 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4398 sp->stats.rx_errors =
ee705dba 4399 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
20346722
K		 4400 sp->stats.multicast =
4401 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
1da177e4 4402 sp->stats.rx_length_errors =
ee705dba 4403 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
1da177e4
LT		 4404
4405 return (&sp->stats);
4406}
4407
4408/**
4409 * s2io_set_multicast - entry point for multicast address enable/disable.
4410 * @dev : pointer to the device structure
4411 * Description:
20346722
K		 4412 * This function is a driver entry point which gets called by the kernel
4413 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4414 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4415 * determine, if multicast address must be enabled or if promiscuous mode
4416 * is to be disabled etc.
4417 * Return value:
4418 * void.
4419 */
4420
4421static void s2io_set_multicast(struct net_device *dev)
4422{
4423 int i, j, prev_cnt;
4424 struct dev_mc_list *mclist;
1ee6dd77
RB		 4425 struct s2io_nic *sp = dev->priv;
4426 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4427 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4428 0xfeffffffffffULL;
4429 u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4430 void __iomem *add;
4431
4432 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4433 /* Enable all Multicast addresses */
4434 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4435 &bar0->rmac_addr_data0_mem);
4436 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4437 &bar0->rmac_addr_data1_mem);
4438 val64 = RMAC_ADDR_CMD_MEM_WE |
4439 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4440 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4441 writeq(val64, &bar0->rmac_addr_cmd_mem);
4442 /* Wait till command completes */
c92ca04b 4443 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4444 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4445 S2IO_BIT_RESET);
1da177e4
LT		 4446
4447 sp->m_cast_flg = 1;
4448 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4449 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4450 /* Disable all Multicast addresses */
4451 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4452 &bar0->rmac_addr_data0_mem);
5e25b9dd
K		 4453 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4454 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4455 val64 = RMAC_ADDR_CMD_MEM_WE |
4456 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4457 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4458 writeq(val64, &bar0->rmac_addr_cmd_mem);
4459 /* Wait till command completes */
c92ca04b 4460 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4461 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4462 S2IO_BIT_RESET);
1da177e4
LT		 4463
4464 sp->m_cast_flg = 0;
4465 sp->all_multi_pos = 0;
4466 }
4467
4468 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4469 /* Put the NIC into promiscuous mode */
4470 add = &bar0->mac_cfg;
4471 val64 = readq(&bar0->mac_cfg);
4472 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4473
4474 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4475 writel((u32) val64, add);
4476 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4477 writel((u32) (val64 >> 32), (add + 4));
4478
926930b2
SS		 4479 if (vlan_tag_strip != 1) {
4480 val64 = readq(&bar0->rx_pa_cfg);
4481 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4482 writeq(val64, &bar0->rx_pa_cfg);
4483 vlan_strip_flag = 0;
4484 }
4485
1da177e4
LT		 4486 val64 = readq(&bar0->mac_cfg);
4487 sp->promisc_flg = 1;
776bd20f 4488 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 4489 dev->name);
4490 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4491 /* Remove the NIC from promiscuous mode */
4492 add = &bar0->mac_cfg;
4493 val64 = readq(&bar0->mac_cfg);
4494 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4495
4496 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4497 writel((u32) val64, add);
4498 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4499 writel((u32) (val64 >> 32), (add + 4));
4500
926930b2
SS		 4501 if (vlan_tag_strip != 0) {
4502 val64 = readq(&bar0->rx_pa_cfg);
4503 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4504 writeq(val64, &bar0->rx_pa_cfg);
4505 vlan_strip_flag = 1;
4506 }
4507
1da177e4
LT		 4508 val64 = readq(&bar0->mac_cfg);
4509 sp->promisc_flg = 0;
776bd20f 4510 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 4511 dev->name);
4512 }
4513
4514 /* Update individual M_CAST address list */
4515 if ((!sp->m_cast_flg) && dev->mc_count) {
4516 if (dev->mc_count >
4517 (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4518 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4519 dev->name);
4520 DBG_PRINT(ERR_DBG, "can be added, please enable ");
4521 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4522 return;
4523 }
4524
4525 prev_cnt = sp->mc_addr_count;
4526 sp->mc_addr_count = dev->mc_count;
4527
4528 /* Clear out the previous list of Mc in the H/W. */
4529 for (i = 0; i < prev_cnt; i++) {
4530 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4531 &bar0->rmac_addr_data0_mem);
4532 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4533 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4534 val64 = RMAC_ADDR_CMD_MEM_WE |
4535 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4536 RMAC_ADDR_CMD_MEM_OFFSET
4537 (MAC_MC_ADDR_START_OFFSET + i);
4538 writeq(val64, &bar0->rmac_addr_cmd_mem);
4539
4540 /* Wait for command completes */
c92ca04b 4541 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4542 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4543 S2IO_BIT_RESET)) {
1da177e4
LT		 4544 DBG_PRINT(ERR_DBG, "%s: Adding ",
4545 dev->name);
4546 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4547 return;
4548 }
4549 }
4550
4551 /* Create the new Rx filter list and update the same in H/W. */
4552 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4553 i++, mclist = mclist->next) {
4554 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4555 ETH_ALEN);
a7a80d5a 4556 mac_addr = 0;
1da177e4
LT		 4557 for (j = 0; j < ETH_ALEN; j++) {
4558 mac_addr |= mclist->dmi_addr[j];
4559 mac_addr <<= 8;
4560 }
4561 mac_addr >>= 8;
4562 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4563 &bar0->rmac_addr_data0_mem);
4564 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4565 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4566 val64 = RMAC_ADDR_CMD_MEM_WE |
4567 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4568 RMAC_ADDR_CMD_MEM_OFFSET
4569 (i + MAC_MC_ADDR_START_OFFSET);
4570 writeq(val64, &bar0->rmac_addr_cmd_mem);
4571
4572 /* Wait for command completes */
c92ca04b 4573 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4574 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4575 S2IO_BIT_RESET)) {
1da177e4
LT		 4576 DBG_PRINT(ERR_DBG, "%s: Adding ",
4577 dev->name);
4578 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4579 return;
4580 }
4581 }
4582 }
4583}
4584
4585/**
20346722 4586 * s2io_set_mac_addr - Programs the Xframe mac address
1da177e4
LT		 4587 * @dev : pointer to the device structure.
4588 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 4589 * Description : This procedure will program the Xframe to receive
1da177e4 4590 * frames with new Mac Address
20346722 4591 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 4592 * as defined in errno.h file on failure.
4593 */
4594
26df54bf 4595static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
1da177e4 4596{
1ee6dd77
RB		 4597 struct s2io_nic *sp = dev->priv;
4598 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4599 register u64 val64, mac_addr = 0;
4600 int i;
d8d70caf 4601 u64 old_mac_addr = 0;
1da177e4 4602
20346722 4603 /*
1da177e4
LT		 4604 * Set the new MAC address as the new unicast filter and reflect this
4605 * change on the device address registered with the OS. It will be
20346722 4606 * at offset 0.
1da177e4
LT		 4607 */
4608 for (i = 0; i < ETH_ALEN; i++) {
4609 mac_addr <<= 8;
4610 mac_addr |= addr[i];
d8d70caf
SS		 4611 old_mac_addr <<= 8;
4612 old_mac_addr |= sp->def_mac_addr[0].mac_addr[i];
4613 }
4614
4615 if(0 == mac_addr)
4616 return SUCCESS;
4617
4618 /* Update the internal structure with this new mac address */
4619 if(mac_addr != old_mac_addr) {
4620 memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
4621 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_addr);
4622 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_addr >> 8);
4623 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_addr >> 16);
4624 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_addr >> 24);
4625 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_addr >> 32);
4626 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_addr >> 40);
1da177e4
LT		 4627 }
4628
4629 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4630 &bar0->rmac_addr_data0_mem);
4631
4632 val64 =
4633 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4634 RMAC_ADDR_CMD_MEM_OFFSET(0);
4635 writeq(val64, &bar0->rmac_addr_cmd_mem);
4636 /* Wait till command completes */
c92ca04b 4637 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41 4638 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET)) {
1da177e4
LT		 4639 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4640 return FAILURE;
4641 }
4642
4643 return SUCCESS;
4644}
4645
4646/**
20346722 4647 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 4648 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4649 * @info: pointer to the structure with parameters given by ethtool to set
4650 * link information.
4651 * Description:
20346722 4652 * The function sets different link parameters provided by the user onto
1da177e4
LT		 4653 * the NIC.
4654 * Return value:
4655 * 0 on success.
4656*/
4657
4658static int s2io_ethtool_sset(struct net_device *dev,
4659 struct ethtool_cmd *info)
4660{
1ee6dd77 4661 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4662 if ((info->autoneg == AUTONEG_ENABLE) ||
4663 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4664 return -EINVAL;
4665 else {
4666 s2io_close(sp->dev);
4667 s2io_open(sp->dev);
4668 }
4669
4670 return 0;
4671}
4672
4673/**
20346722 4674 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 4675 * @sp : private member of the device structure, pointer to the
4676 * s2io_nic structure.
4677 * @info : pointer to the structure with parameters given by ethtool
4678 * to return link information.
4679 * Description:
4680 * Returns link specific information like speed, duplex etc.. to ethtool.
4681 * Return value :
4682 * return 0 on success.
4683 */
4684
4685static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4686{
1ee6dd77 4687 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4688 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4689 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4690 info->port = PORT_FIBRE;
4691 /* info->transceiver?? TODO */
4692
4693 if (netif_carrier_ok(sp->dev)) {
4694 info->speed = 10000;
4695 info->duplex = DUPLEX_FULL;
4696 } else {
4697 info->speed = -1;
4698 info->duplex = -1;
4699 }
4700
4701 info->autoneg = AUTONEG_DISABLE;
4702 return 0;
4703}
4704
4705/**
20346722
K		 4706 * s2io_ethtool_gdrvinfo - Returns driver specific information.
4707 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4708 * s2io_nic structure.
4709 * @info : pointer to the structure with parameters given by ethtool to
4710 * return driver information.
4711 * Description:
4712 * Returns driver specefic information like name, version etc.. to ethtool.
4713 * Return value:
4714 * void
4715 */
4716
4717static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4718 struct ethtool_drvinfo *info)
4719{
1ee6dd77 4720 struct s2io_nic *sp = dev->priv;
1da177e4 4721
dbc2309d
JL		 4722 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4723 strncpy(info->version, s2io_driver_version, sizeof(info->version));
4724 strncpy(info->fw_version, "", sizeof(info->fw_version));
4725 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 4726 info->regdump_len = XENA_REG_SPACE;
4727 info->eedump_len = XENA_EEPROM_SPACE;
4728 info->testinfo_len = S2IO_TEST_LEN;
fa1f0cb3
SS		 4729
4730 if (sp->device_type == XFRAME_I_DEVICE)
4731 info->n_stats = XFRAME_I_STAT_LEN;
4732 else
4733 info->n_stats = XFRAME_II_STAT_LEN;
1da177e4
LT		 4734}
4735
4736/**
4737 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 4738 * @sp: private member of the device structure, which is a pointer to the
1da177e4 4739 * s2io_nic structure.
20346722 4740 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 4741 * dumping the registers.
4742 * @reg_space: The input argumnet into which all the registers are dumped.
4743 * Description:
4744 * Dumps the entire register space of xFrame NIC into the user given
4745 * buffer area.
4746 * Return value :
4747 * void .
4748*/
4749
4750static void s2io_ethtool_gregs(struct net_device *dev,
4751 struct ethtool_regs *regs, void *space)
4752{
4753 int i;
4754 u64 reg;
4755 u8 *reg_space = (u8 *) space;
1ee6dd77 4756 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4757
4758 regs->len = XENA_REG_SPACE;
4759 regs->version = sp->pdev->subsystem_device;
4760
4761 for (i = 0; i < regs->len; i += 8) {
4762 reg = readq(sp->bar0 + i);
4763 memcpy((reg_space + i), &reg, 8);
4764 }
4765}
4766
4767/**
4768 * s2io_phy_id - timer function that alternates adapter LED.
20346722 4769 * @data : address of the private member of the device structure, which
1da177e4 4770 * is a pointer to the s2io_nic structure, provided as an u32.
20346722
K		 4771 * Description: This is actually the timer function that alternates the
4772 * adapter LED bit of the adapter control bit to set/reset every time on
4773 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4
LT		 4774 * once every second.
4775*/
4776static void s2io_phy_id(unsigned long data)
4777{
1ee6dd77
RB		 4778 struct s2io_nic *sp = (struct s2io_nic *) data;
4779 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4780 u64 val64 = 0;
4781 u16 subid;
4782
4783 subid = sp->pdev->subsystem_device;
541ae68f
K		 4784 if ((sp->device_type == XFRAME_II_DEVICE) ||
4785 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 4786 val64 = readq(&bar0->gpio_control);
4787 val64 ^= GPIO_CTRL_GPIO_0;
4788 writeq(val64, &bar0->gpio_control);
4789 } else {
4790 val64 = readq(&bar0->adapter_control);
4791 val64 ^= ADAPTER_LED_ON;
4792 writeq(val64, &bar0->adapter_control);
4793 }
4794
4795 mod_timer(&sp->id_timer, jiffies + HZ / 2);
4796}
4797
4798/**
4799 * s2io_ethtool_idnic - To physically identify the nic on the system.
4800 * @sp : private member of the device structure, which is a pointer to the
4801 * s2io_nic structure.
20346722 4802 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 4803 * ethtool.
4804 * Description: Used to physically identify the NIC on the system.
20346722 4805 * The Link LED will blink for a time specified by the user for
1da177e4 4806 * identification.
20346722 4807 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 4808 * identification is possible only if it's link is up.
4809 * Return value:
4810 * int , returns 0 on success
4811 */
4812
4813static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4814{
4815 u64 val64 = 0, last_gpio_ctrl_val;
1ee6dd77
RB		 4816 struct s2io_nic *sp = dev->priv;
4817 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4818 u16 subid;
4819
4820 subid = sp->pdev->subsystem_device;
4821 last_gpio_ctrl_val = readq(&bar0->gpio_control);
541ae68f
K		 4822 if ((sp->device_type == XFRAME_I_DEVICE) &&
4823 ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 4824 val64 = readq(&bar0->adapter_control);
4825 if (!(val64 & ADAPTER_CNTL_EN)) {
4826 printk(KERN_ERR
4827 "Adapter Link down, cannot blink LED\n");
4828 return -EFAULT;
4829 }
4830 }
4831 if (sp->id_timer.function == NULL) {
4832 init_timer(&sp->id_timer);
4833 sp->id_timer.function = s2io_phy_id;
4834 sp->id_timer.data = (unsigned long) sp;
4835 }
4836 mod_timer(&sp->id_timer, jiffies);
4837 if (data)
20346722 4838 msleep_interruptible(data * HZ);
1da177e4 4839 else
20346722 4840 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 4841 del_timer_sync(&sp->id_timer);
4842
541ae68f 4843 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 4844 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4845 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4846 }
4847
4848 return 0;
4849}
4850
0cec35eb
SH		 4851static void s2io_ethtool_gringparam(struct net_device *dev,
4852 struct ethtool_ringparam *ering)
4853{
4854 struct s2io_nic *sp = dev->priv;
4855 int i,tx_desc_count=0,rx_desc_count=0;
4856
4857 if (sp->rxd_mode == RXD_MODE_1)
4858 ering->rx_max_pending = MAX_RX_DESC_1;
4859 else if (sp->rxd_mode == RXD_MODE_3B)
4860 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 4861
4862 ering->tx_max_pending = MAX_TX_DESC;
4863 for (i = 0 ; i < sp->config.tx_fifo_num ; i++) {
4864 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
4865 }
4866 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
4867 ering->tx_pending = tx_desc_count;
4868 rx_desc_count = 0;
4869 for (i = 0 ; i < sp->config.rx_ring_num ; i++) {
4870 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
4871 }
4872 ering->rx_pending = rx_desc_count;
4873
4874 ering->rx_mini_max_pending = 0;
4875 ering->rx_mini_pending = 0;
4876 if(sp->rxd_mode == RXD_MODE_1)
4877 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
4878 else if (sp->rxd_mode == RXD_MODE_3B)
4879 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
4880 ering->rx_jumbo_pending = rx_desc_count;
4881}
4882
1da177e4
LT		 4883/**
4884 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722
K		 4885 * @sp : private member of the device structure, which is a pointer to the
4886 * s2io_nic structure.
1da177e4
LT		 4887 * @ep : pointer to the structure with pause parameters given by ethtool.
4888 * Description:
4889 * Returns the Pause frame generation and reception capability of the NIC.
4890 * Return value:
4891 * void
4892 */
4893static void s2io_ethtool_getpause_data(struct net_device *dev,
4894 struct ethtool_pauseparam *ep)
4895{
4896 u64 val64;
1ee6dd77
RB		 4897 struct s2io_nic *sp = dev->priv;
4898 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4899
4900 val64 = readq(&bar0->rmac_pause_cfg);
4901 if (val64 & RMAC_PAUSE_GEN_ENABLE)
4902 ep->tx_pause = TRUE;
4903 if (val64 & RMAC_PAUSE_RX_ENABLE)
4904 ep->rx_pause = TRUE;
4905 ep->autoneg = FALSE;
4906}
4907
4908/**
4909 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 4910 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4911 * s2io_nic structure.
4912 * @ep : pointer to the structure with pause parameters given by ethtool.
4913 * Description:
4914 * It can be used to set or reset Pause frame generation or reception
4915 * support of the NIC.
4916 * Return value:
4917 * int, returns 0 on Success
4918 */
4919
4920static int s2io_ethtool_setpause_data(struct net_device *dev,
20346722 4921 struct ethtool_pauseparam *ep)
1da177e4
LT		 4922{
4923 u64 val64;
1ee6dd77
RB		 4924 struct s2io_nic *sp = dev->priv;
4925 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4926
4927 val64 = readq(&bar0->rmac_pause_cfg);
4928 if (ep->tx_pause)
4929 val64 |= RMAC_PAUSE_GEN_ENABLE;
4930 else
4931 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4932 if (ep->rx_pause)
4933 val64 |= RMAC_PAUSE_RX_ENABLE;
4934 else
4935 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4936 writeq(val64, &bar0->rmac_pause_cfg);
4937 return 0;
4938}
4939
4940/**
4941 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 4942 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4943 * s2io_nic structure.
4944 * @off : offset at which the data must be written
4945 * @data : Its an output parameter where the data read at the given
20346722 4946 * offset is stored.
1da177e4 4947 * Description:
20346722 4948 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 4949 * read data.
4950 * NOTE: Will allow to read only part of the EEPROM visible through the
4951 * I2C bus.
4952 * Return value:
4953 * -1 on failure and 0 on success.
4954 */
4955
4956#define S2IO_DEV_ID 5
1ee6dd77 4957static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
1da177e4
LT		 4958{
4959 int ret = -1;
4960 u32 exit_cnt = 0;
4961 u64 val64;
1ee6dd77 4962 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 4963
ad4ebed0 4964 if (sp->device_type == XFRAME_I_DEVICE) {
4965 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4966 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4967 I2C_CONTROL_CNTL_START;
4968 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 4969
ad4ebed0 4970 while (exit_cnt < 5) {
4971 val64 = readq(&bar0->i2c_control);
4972 if (I2C_CONTROL_CNTL_END(val64)) {
4973 *data = I2C_CONTROL_GET_DATA(val64);
4974 ret = 0;
4975 break;
4976 }
4977 msleep(50);
4978 exit_cnt++;
1da177e4 4979 }
1da177e4
LT		 4980 }
4981
ad4ebed0 4982 if (sp->device_type == XFRAME_II_DEVICE) {
4983 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 4984 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 4985 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4986 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4987 val64 |= SPI_CONTROL_REQ;
4988 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4989 while (exit_cnt < 5) {
4990 val64 = readq(&bar0->spi_control);
4991 if (val64 & SPI_CONTROL_NACK) {
4992 ret = 1;
4993 break;
4994 } else if (val64 & SPI_CONTROL_DONE) {
4995 *data = readq(&bar0->spi_data);
4996 *data &= 0xffffff;
4997 ret = 0;
4998 break;
4999 }
5000 msleep(50);
5001 exit_cnt++;
5002 }
5003 }
1da177e4
LT		 5004 return ret;
5005}
5006
5007/**
5008 * write_eeprom - actually writes the relevant part of the data value.
5009 * @sp : private member of the device structure, which is a pointer to the
5010 * s2io_nic structure.
5011 * @off : offset at which the data must be written
5012 * @data : The data that is to be written
20346722 5013 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5014 * the Eeprom. (max of 3)
5015 * Description:
5016 * Actually writes the relevant part of the data value into the Eeprom
5017 * through the I2C bus.
5018 * Return value:
5019 * 0 on success, -1 on failure.
5020 */
5021
1ee6dd77 5022static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
1da177e4
LT		 5023{
5024 int exit_cnt = 0, ret = -1;
5025 u64 val64;
1ee6dd77 5026 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5027
ad4ebed0 5028 if (sp->device_type == XFRAME_I_DEVICE) {
5029 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5030 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5031 I2C_CONTROL_CNTL_START;
5032 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5033
5034 while (exit_cnt < 5) {
5035 val64 = readq(&bar0->i2c_control);
5036 if (I2C_CONTROL_CNTL_END(val64)) {
5037 if (!(val64 & I2C_CONTROL_NACK))
5038 ret = 0;
5039 break;
5040 }
5041 msleep(50);
5042 exit_cnt++;
5043 }
5044 }
1da177e4 5045
ad4ebed0 5046 if (sp->device_type == XFRAME_II_DEVICE) {
5047 int write_cnt = (cnt == 8) ? 0 : cnt;
5048 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5049
5050 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5051 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5052 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5053 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5054 val64 |= SPI_CONTROL_REQ;
5055 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5056 while (exit_cnt < 5) {
5057 val64 = readq(&bar0->spi_control);
5058 if (val64 & SPI_CONTROL_NACK) {
5059 ret = 1;
5060 break;
5061 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5062 ret = 0;
ad4ebed0 5063 break;
5064 }
5065 msleep(50);
5066 exit_cnt++;
1da177e4 5067 }
1da177e4 5068 }
1da177e4
LT		 5069 return ret;
5070}
1ee6dd77 5071static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5072{
b41477f3
AR		 5073 u8 *vpd_data;
5074 u8 data;
9dc737a7
AR		 5075 int i=0, cnt, fail = 0;
5076 int vpd_addr = 0x80;
5077
5078 if (nic->device_type == XFRAME_II_DEVICE) {
5079 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5080 vpd_addr = 0x80;
5081 }
5082 else {
5083 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5084 vpd_addr = 0x50;
5085 }
19a60522 5086 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5087
b41477f3 5088 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945
SH		 5089 if (!vpd_data) {
5090 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
b41477f3 5091 return;
c53d4945 5092 }
491976b2 5093 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
b41477f3 5094
9dc737a7
AR		 5095 for (i = 0; i < 256; i +=4 ) {
5096 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5097 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5098 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5099 for (cnt = 0; cnt <5; cnt++) {
5100 msleep(2);
5101 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5102 if (data == 0x80)
5103 break;
5104 }
5105 if (cnt >= 5) {
5106 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5107 fail = 1;
5108 break;
5109 }
5110 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5111 (u32 *)&vpd_data[i]);
5112 }
19a60522
SS		 5113
5114 if(!fail) {
5115 /* read serial number of adapter */
5116 for (cnt = 0; cnt < 256; cnt++) {
5117 if ((vpd_data[cnt] == 'S') &&
5118 (vpd_data[cnt+1] == 'N') &&
5119 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5120 memset(nic->serial_num, 0, VPD_STRING_LEN);
5121 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5122 vpd_data[cnt+2]);
5123 break;
5124 }
5125 }
5126 }
5127
5128 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
9dc737a7
AR		 5129 memset(nic->product_name, 0, vpd_data[1]);
5130 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5131 }
b41477f3 5132 kfree(vpd_data);
491976b2 5133 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
9dc737a7
AR		 5134}
5135
1da177e4
LT		 5136/**
5137 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5138 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5139 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5140 * containing all relevant information.
5141 * @data_buf : user defined value to be written into Eeprom.
5142 * Description: Reads the values stored in the Eeprom at given offset
5143 * for a given length. Stores these values int the input argument data
5144 * buffer 'data_buf' and returns these to the caller (ethtool.)
5145 * Return value:
5146 * int 0 on success
5147 */
5148
5149static int s2io_ethtool_geeprom(struct net_device *dev,
20346722 5150 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5151{
ad4ebed0 5152 u32 i, valid;
5153 u64 data;
1ee6dd77 5154 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5155
5156 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5157
5158 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5159 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5160
5161 for (i = 0; i < eeprom->len; i += 4) {
5162 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5163 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5164 return -EFAULT;
5165 }
5166 valid = INV(data);
5167 memcpy((data_buf + i), &valid, 4);
5168 }
5169 return 0;
5170}
5171
5172/**
5173 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5174 * @sp : private member of the device structure, which is a pointer to the
5175 * s2io_nic structure.
20346722 5176 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5177 * containing all relevant information.
5178 * @data_buf ; user defined value to be written into Eeprom.
5179 * Description:
5180 * Tries to write the user provided value in the Eeprom, at the offset
5181 * given by the user.
5182 * Return value:
5183 * 0 on success, -EFAULT on failure.
5184 */
5185
5186static int s2io_ethtool_seeprom(struct net_device *dev,
5187 struct ethtool_eeprom *eeprom,
5188 u8 * data_buf)
5189{
5190 int len = eeprom->len, cnt = 0;
ad4ebed0 5191 u64 valid = 0, data;
1ee6dd77 5192 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5193
5194 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5195 DBG_PRINT(ERR_DBG,
5196 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5197 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5198 eeprom->magic);
5199 return -EFAULT;
5200 }
5201
5202 while (len) {
5203 data = (u32) data_buf[cnt] & 0x000000FF;
5204 if (data) {
5205 valid = (u32) (data << 24);
5206 } else
5207 valid = data;
5208
5209 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5210 DBG_PRINT(ERR_DBG,
5211 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5212 DBG_PRINT(ERR_DBG,
5213 "write into the specified offset\n");
5214 return -EFAULT;
5215 }
5216 cnt++;
5217 len--;
5218 }
5219
5220 return 0;
5221}
5222
5223/**
20346722
K		 5224 * s2io_register_test - reads and writes into all clock domains.
5225 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5226 * s2io_nic structure.
5227 * @data : variable that returns the result of each of the test conducted b
5228 * by the driver.
5229 * Description:
5230 * Read and write into all clock domains. The NIC has 3 clock domains,
5231 * see that registers in all the three regions are accessible.
5232 * Return value:
5233 * 0 on success.
5234 */
5235
1ee6dd77 5236static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5237{
1ee6dd77 5238 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5239 u64 val64 = 0, exp_val;
1da177e4
LT		 5240 int fail = 0;
5241
20346722
K		 5242 val64 = readq(&bar0->pif_rd_swapper_fb);
5243 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5244 fail = 1;
5245 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5246 }
5247
5248 val64 = readq(&bar0->rmac_pause_cfg);
5249 if (val64 != 0xc000ffff00000000ULL) {
5250 fail = 1;
5251 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5252 }
5253
5254 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5255 if (sp->device_type == XFRAME_II_DEVICE)
5256 exp_val = 0x0404040404040404ULL;
5257 else
5258 exp_val = 0x0808080808080808ULL;
5259 if (val64 != exp_val) {
1da177e4
LT		 5260 fail = 1;
5261 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5262 }
5263
5264 val64 = readq(&bar0->xgxs_efifo_cfg);
5265 if (val64 != 0x000000001923141EULL) {
5266 fail = 1;
5267 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5268 }
5269
5270 val64 = 0x5A5A5A5A5A5A5A5AULL;
5271 writeq(val64, &bar0->xmsi_data);
5272 val64 = readq(&bar0->xmsi_data);
5273 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5274 fail = 1;
5275 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5276 }
5277
5278 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5279 writeq(val64, &bar0->xmsi_data);
5280 val64 = readq(&bar0->xmsi_data);
5281 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5282 fail = 1;
5283 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5284 }
5285
5286 *data = fail;
ad4ebed0 5287 return fail;
1da177e4
LT		 5288}
5289
5290/**
20346722 5291 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5292 * @sp : private member of the device structure, which is a pointer to the
5293 * s2io_nic structure.
5294 * @data:variable that returns the result of each of the test conducted by
5295 * the driver.
5296 * Description:
20346722 5297 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5298 * register.
5299 * Return value:
5300 * 0 on success.
5301 */
5302
1ee6dd77 5303static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5304{
5305 int fail = 0;
ad4ebed0 5306 u64 ret_data, org_4F0, org_7F0;
5307 u8 saved_4F0 = 0, saved_7F0 = 0;
5308 struct net_device *dev = sp->dev;
1da177e4
LT		 5309
5310 /* Test Write Error at offset 0 */
ad4ebed0 5311 /* Note that SPI interface allows write access to all areas
5312 * of EEPROM. Hence doing all negative testing only for Xframe I.
5313 */
5314 if (sp->device_type == XFRAME_I_DEVICE)
5315 if (!write_eeprom(sp, 0, 0, 3))
5316 fail = 1;
5317
5318 /* Save current values at offsets 0x4F0 and 0x7F0 */
5319 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5320 saved_4F0 = 1;
5321 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5322 saved_7F0 = 1;
1da177e4
LT		 5323
5324 /* Test Write at offset 4f0 */
ad4ebed0 5325 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 5326 fail = 1;
5327 if (read_eeprom(sp, 0x4F0, &ret_data))
5328 fail = 1;
5329
ad4ebed0 5330 if (ret_data != 0x012345) {
26b7625c
AM		 5331 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5332 "Data written %llx Data read %llx\n",
5333 dev->name, (unsigned long long)0x12345,
5334 (unsigned long long)ret_data);
1da177e4 5335 fail = 1;
ad4ebed0 5336 }
1da177e4
LT		 5337
5338 /* Reset the EEPROM data go FFFF */
ad4ebed0 5339 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 5340
5341 /* Test Write Request Error at offset 0x7c */
ad4ebed0 5342 if (sp->device_type == XFRAME_I_DEVICE)
5343 if (!write_eeprom(sp, 0x07C, 0, 3))
5344 fail = 1;
1da177e4 5345
ad4ebed0 5346 /* Test Write Request at offset 0x7f0 */
5347 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 5348 fail = 1;
ad4ebed0 5349 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 5350 fail = 1;
5351
ad4ebed0 5352 if (ret_data != 0x012345) {
26b7625c
AM		 5353 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5354 "Data written %llx Data read %llx\n",
5355 dev->name, (unsigned long long)0x12345,
5356 (unsigned long long)ret_data);
1da177e4 5357 fail = 1;
ad4ebed0 5358 }
1da177e4
LT		 5359
5360 /* Reset the EEPROM data go FFFF */
ad4ebed0 5361 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 5362
ad4ebed0 5363 if (sp->device_type == XFRAME_I_DEVICE) {
5364 /* Test Write Error at offset 0x80 */
5365 if (!write_eeprom(sp, 0x080, 0, 3))
5366 fail = 1;
1da177e4 5367
ad4ebed0 5368 /* Test Write Error at offset 0xfc */
5369 if (!write_eeprom(sp, 0x0FC, 0, 3))
5370 fail = 1;
1da177e4 5371
ad4ebed0 5372 /* Test Write Error at offset 0x100 */
5373 if (!write_eeprom(sp, 0x100, 0, 3))
5374 fail = 1;
1da177e4 5375
ad4ebed0 5376 /* Test Write Error at offset 4ec */
5377 if (!write_eeprom(sp, 0x4EC, 0, 3))
5378 fail = 1;
5379 }
5380
5381 /* Restore values at offsets 0x4F0 and 0x7F0 */
5382 if (saved_4F0)
5383 write_eeprom(sp, 0x4F0, org_4F0, 3);
5384 if (saved_7F0)
5385 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 5386
5387 *data = fail;
ad4ebed0 5388 return fail;
1da177e4
LT		 5389}
5390
5391/**
5392 * s2io_bist_test - invokes the MemBist test of the card .
20346722 5393 * @sp : private member of the device structure, which is a pointer to the
1da177e4 5394 * s2io_nic structure.
20346722 5395 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 5396 * the driver.
5397 * Description:
5398 * This invokes the MemBist test of the card. We give around
5399 * 2 secs time for the Test to complete. If it's still not complete
20346722 5400 * within this peiod, we consider that the test failed.
1da177e4
LT		 5401 * Return value:
5402 * 0 on success and -1 on failure.
5403 */
5404
1ee6dd77 5405static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5406{
5407 u8 bist = 0;
5408 int cnt = 0, ret = -1;
5409
5410 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5411 bist |= PCI_BIST_START;
5412 pci_write_config_word(sp->pdev, PCI_BIST, bist);
5413
5414 while (cnt < 20) {
5415 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5416 if (!(bist & PCI_BIST_START)) {
5417 *data = (bist & PCI_BIST_CODE_MASK);
5418 ret = 0;
5419 break;
5420 }
5421 msleep(100);
5422 cnt++;
5423 }
5424
5425 return ret;
5426}
5427
5428/**
20346722
K		 5429 * s2io-link_test - verifies the link state of the nic
5430 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 5431 * s2io_nic structure.
5432 * @data: variable that returns the result of each of the test conducted by
5433 * the driver.
5434 * Description:
20346722 5435 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 5436 * argument 'data' appropriately.
5437 * Return value:
5438 * 0 on success.
5439 */
5440
1ee6dd77 5441static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5442{
1ee6dd77 5443 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5444 u64 val64;
5445
5446 val64 = readq(&bar0->adapter_status);
c92ca04b 5447 if(!(LINK_IS_UP(val64)))
1da177e4 5448 *data = 1;
c92ca04b
AR		 5449 else
5450 *data = 0;
1da177e4 5451
b41477f3 5452 return *data;
1da177e4
LT		 5453}
5454
5455/**
20346722
K		 5456 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5457 * @sp - private member of the device structure, which is a pointer to the
1da177e4 5458 * s2io_nic structure.
20346722 5459 * @data - variable that returns the result of each of the test
1da177e4
LT		 5460 * conducted by the driver.
5461 * Description:
20346722 5462 * This is one of the offline test that tests the read and write
1da177e4
LT		 5463 * access to the RldRam chip on the NIC.
5464 * Return value:
5465 * 0 on success.
5466 */
5467
1ee6dd77 5468static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5469{
1ee6dd77 5470 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5471 u64 val64;
ad4ebed0 5472 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 5473
5474 val64 = readq(&bar0->adapter_control);
5475 val64 &= ~ADAPTER_ECC_EN;
5476 writeq(val64, &bar0->adapter_control);
5477
5478 val64 = readq(&bar0->mc_rldram_test_ctrl);
5479 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 5480 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5481
5482 val64 = readq(&bar0->mc_rldram_mrs);
5483 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5484 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5485
5486 val64 |= MC_RLDRAM_MRS_ENABLE;
5487 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5488
5489 while (iteration < 2) {
5490 val64 = 0x55555555aaaa0000ULL;
5491 if (iteration == 1) {
5492 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5493 }
5494 writeq(val64, &bar0->mc_rldram_test_d0);
5495
5496 val64 = 0xaaaa5a5555550000ULL;
5497 if (iteration == 1) {
5498 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5499 }
5500 writeq(val64, &bar0->mc_rldram_test_d1);
5501
5502 val64 = 0x55aaaaaaaa5a0000ULL;
5503 if (iteration == 1) {
5504 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5505 }
5506 writeq(val64, &bar0->mc_rldram_test_d2);
5507
ad4ebed0 5508 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 5509 writeq(val64, &bar0->mc_rldram_test_add);
5510
ad4ebed0 5511 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5512 MC_RLDRAM_TEST_GO;
5513 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5514
5515 for (cnt = 0; cnt < 5; cnt++) {
5516 val64 = readq(&bar0->mc_rldram_test_ctrl);
5517 if (val64 & MC_RLDRAM_TEST_DONE)
5518 break;
5519 msleep(200);
5520 }
5521
5522 if (cnt == 5)
5523 break;
5524
ad4ebed0 5525 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5526 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5527
5528 for (cnt = 0; cnt < 5; cnt++) {
5529 val64 = readq(&bar0->mc_rldram_test_ctrl);
5530 if (val64 & MC_RLDRAM_TEST_DONE)
5531 break;
5532 msleep(500);
5533 }
5534
5535 if (cnt == 5)
5536 break;
5537
5538 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 5539 if (!(val64 & MC_RLDRAM_TEST_PASS))
5540 test_fail = 1;
1da177e4
LT		 5541
5542 iteration++;
5543 }
5544
ad4ebed0 5545 *data = test_fail;
1da177e4 5546
ad4ebed0 5547 /* Bring the adapter out of test mode */
5548 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5549
5550 return test_fail;
1da177e4
LT		 5551}
5552
5553/**
5554 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5555 * @sp : private member of the device structure, which is a pointer to the
5556 * s2io_nic structure.
5557 * @ethtest : pointer to a ethtool command specific structure that will be
5558 * returned to the user.
20346722 5559 * @data : variable that returns the result of each of the test
1da177e4
LT		 5560 * conducted by the driver.
5561 * Description:
5562 * This function conducts 6 tests ( 4 offline and 2 online) to determine
5563 * the health of the card.
5564 * Return value:
5565 * void
5566 */
5567
5568static void s2io_ethtool_test(struct net_device *dev,
5569 struct ethtool_test *ethtest,
5570 uint64_t * data)
5571{
1ee6dd77 5572 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5573 int orig_state = netif_running(sp->dev);
5574
5575 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5576 /* Offline Tests. */
20346722 5577 if (orig_state)
1da177e4 5578 s2io_close(sp->dev);
1da177e4
LT		 5579
5580 if (s2io_register_test(sp, &data[0]))
5581 ethtest->flags |= ETH_TEST_FL_FAILED;
5582
5583 s2io_reset(sp);
1da177e4
LT		 5584
5585 if (s2io_rldram_test(sp, &data[3]))
5586 ethtest->flags |= ETH_TEST_FL_FAILED;
5587
5588 s2io_reset(sp);
1da177e4
LT		 5589
5590 if (s2io_eeprom_test(sp, &data[1]))
5591 ethtest->flags |= ETH_TEST_FL_FAILED;
5592
5593 if (s2io_bist_test(sp, &data[4]))
5594 ethtest->flags |= ETH_TEST_FL_FAILED;
5595
5596 if (orig_state)
5597 s2io_open(sp->dev);
5598
5599 data[2] = 0;
5600 } else {
5601 /* Online Tests. */
5602 if (!orig_state) {
5603 DBG_PRINT(ERR_DBG,
5604 "%s: is not up, cannot run test\n",
5605 dev->name);
5606 data[0] = -1;
5607 data[1] = -1;
5608 data[2] = -1;
5609 data[3] = -1;
5610 data[4] = -1;
5611 }
5612
5613 if (s2io_link_test(sp, &data[2]))
5614 ethtest->flags |= ETH_TEST_FL_FAILED;
5615
5616 data[0] = 0;
5617 data[1] = 0;
5618 data[3] = 0;
5619 data[4] = 0;
5620 }
5621}
5622
5623static void s2io_get_ethtool_stats(struct net_device *dev,
5624 struct ethtool_stats *estats,
5625 u64 * tmp_stats)
5626{
5627 int i = 0;
1ee6dd77
RB		 5628 struct s2io_nic *sp = dev->priv;
5629 struct stat_block *stat_info = sp->mac_control.stats_info;
1da177e4 5630
7ba013ac 5631 s2io_updt_stats(sp);
541ae68f
K		 5632 tmp_stats[i++] =
5633 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
5634 le32_to_cpu(stat_info->tmac_frms);
5635 tmp_stats[i++] =
5636 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5637 le32_to_cpu(stat_info->tmac_data_octets);
1da177e4 5638 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
541ae68f
K		 5639 tmp_stats[i++] =
5640 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5641 le32_to_cpu(stat_info->tmac_mcst_frms);
5642 tmp_stats[i++] =
5643 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5644 le32_to_cpu(stat_info->tmac_bcst_frms);
1da177e4 5645 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
bd1034f0
AR		 5646 tmp_stats[i++] =
5647 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5648 le32_to_cpu(stat_info->tmac_ttl_octets);
5649 tmp_stats[i++] =
5650 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5651 le32_to_cpu(stat_info->tmac_ucst_frms);
5652 tmp_stats[i++] =
5653 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5654 le32_to_cpu(stat_info->tmac_nucst_frms);
541ae68f
K		 5655 tmp_stats[i++] =
5656 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5657 le32_to_cpu(stat_info->tmac_any_err_frms);
bd1034f0 5658 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
1da177e4 5659 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
541ae68f
K		 5660 tmp_stats[i++] =
5661 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5662 le32_to_cpu(stat_info->tmac_vld_ip);
5663 tmp_stats[i++] =
5664 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5665 le32_to_cpu(stat_info->tmac_drop_ip);
5666 tmp_stats[i++] =
5667 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5668 le32_to_cpu(stat_info->tmac_icmp);
5669 tmp_stats[i++] =
5670 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5671 le32_to_cpu(stat_info->tmac_rst_tcp);
1da177e4 5672 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
541ae68f
K		 5673 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5674 le32_to_cpu(stat_info->tmac_udp);
5675 tmp_stats[i++] =
5676 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5677 le32_to_cpu(stat_info->rmac_vld_frms);
5678 tmp_stats[i++] =
5679 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5680 le32_to_cpu(stat_info->rmac_data_octets);
1da177e4
LT		 5681 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5682 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
541ae68f
K		 5683 tmp_stats[i++] =
5684 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5685 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5686 tmp_stats[i++] =
5687 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5688 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
1da177e4 5689 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
bd1034f0 5690 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
1da177e4
LT		 5691 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5692 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
bd1034f0
AR		 5693 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
5694 tmp_stats[i++] =
5695 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
5696 le32_to_cpu(stat_info->rmac_ttl_octets);
5697 tmp_stats[i++] =
5698 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
5699 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
5700 tmp_stats[i++] =
5701 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
5702 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
541ae68f
K		 5703 tmp_stats[i++] =
5704 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5705 le32_to_cpu(stat_info->rmac_discarded_frms);
bd1034f0
AR		 5706 tmp_stats[i++] =
5707 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
5708 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
5709 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
5710 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
541ae68f
K		 5711 tmp_stats[i++] =
5712 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5713 le32_to_cpu(stat_info->rmac_usized_frms);
5714 tmp_stats[i++] =
5715 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5716 le32_to_cpu(stat_info->rmac_osized_frms);
5717 tmp_stats[i++] =
5718 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5719 le32_to_cpu(stat_info->rmac_frag_frms);
5720 tmp_stats[i++] =
5721 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5722 le32_to_cpu(stat_info->rmac_jabber_frms);
bd1034f0
AR		 5723 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
5724 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
5725 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
5726 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
5727 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
5728 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
5729 tmp_stats[i++] =
5730 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
541ae68f 5731 le32_to_cpu(stat_info->rmac_ip);
1da177e4
LT		 5732 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5733 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
bd1034f0
AR		 5734 tmp_stats[i++] =
5735 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
541ae68f 5736 le32_to_cpu(stat_info->rmac_drop_ip);
bd1034f0
AR		 5737 tmp_stats[i++] =
5738 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
541ae68f 5739 le32_to_cpu(stat_info->rmac_icmp);
1da177e4 5740 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
bd1034f0
AR		 5741 tmp_stats[i++] =
5742 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
541ae68f
K		 5743 le32_to_cpu(stat_info->rmac_udp);
5744 tmp_stats[i++] =
5745 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5746 le32_to_cpu(stat_info->rmac_err_drp_udp);
bd1034f0
AR		 5747 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
5748 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
5749 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
5750 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
5751 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
5752 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
5753 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
5754 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
5755 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
5756 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
5757 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
5758 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
5759 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
5760 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
5761 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
5762 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
5763 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
541ae68f
K		 5764 tmp_stats[i++] =
5765 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5766 le32_to_cpu(stat_info->rmac_pause_cnt);
bd1034f0
AR		 5767 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
5768 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
541ae68f
K		 5769 tmp_stats[i++] =
5770 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5771 le32_to_cpu(stat_info->rmac_accepted_ip);
1da177e4 5772 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
bd1034f0
AR		 5773 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
5774 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
5775 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
5776 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
5777 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
5778 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
5779 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
5780 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
5781 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
5782 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
5783 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
5784 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
5785 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
5786 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
5787 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
5788 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
5789 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
5790 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
fa1f0cb3
SS		 5791
5792 /* Enhanced statistics exist only for Hercules */
5793 if(sp->device_type == XFRAME_II_DEVICE) {
5794 tmp_stats[i++] =
5795 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
5796 tmp_stats[i++] =
5797 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
5798 tmp_stats[i++] =
5799 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
5800 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
5801 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
5802 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
5803 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
5804 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
5805 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
5806 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
5807 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
5808 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
5809 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
5810 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
5811 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
5812 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
5813 }
5814
7ba013ac
K		 5815 tmp_stats[i++] = 0;
5816 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5817 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
bd1034f0
AR		 5818 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
5819 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
5820 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
5821 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
5822 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt;
5823 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
5824 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
5825 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
5826 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
5827 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
5828 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
5829 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
5830 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
5831 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
5832 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
5833 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
5834 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
7d3d0439
RA		 5835 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
5836 tmp_stats[i++] = stat_info->sw_stat.sending_both;
5837 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
5838 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
fe931395 5839 if (stat_info->sw_stat.num_aggregations) {
bd1034f0
AR		 5840 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
5841 int count = 0;
6aa20a22 5842 /*
bd1034f0
AR		 5843 * Since 64-bit divide does not work on all platforms,
5844 * do repeated subtraction.
5845 */
5846 while (tmp >= stat_info->sw_stat.num_aggregations) {
5847 tmp -= stat_info->sw_stat.num_aggregations;
5848 count++;
5849 }
5850 tmp_stats[i++] = count;
fe931395 5851 }
bd1034f0
AR		 5852 else
5853 tmp_stats[i++] = 0;
c53d4945
SH		 5854 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
5855 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
491976b2
SH		 5856 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
5857 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
5858 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
5859 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
5860 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
5861 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
5862
5863 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
5864 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
5865 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
5866 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
5867 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
5868
5869 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
5870 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
5871 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
5872 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
5873 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
5874 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
5875 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
5876 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
5877 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
1da177e4
LT		 5878}
5879
ac1f60db 5880static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4
LT		 5881{
5882 return (XENA_REG_SPACE);
5883}
5884
5885
ac1f60db 5886static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
1da177e4 5887{
1ee6dd77 5888 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5889
5890 return (sp->rx_csum);
5891}
ac1f60db
AB		 5892
5893static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 5894{
1ee6dd77 5895 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5896
5897 if (data)
5898 sp->rx_csum = 1;
5899 else
5900 sp->rx_csum = 0;
5901
5902 return 0;
5903}
ac1f60db
AB		 5904
5905static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4
LT		 5906{
5907 return (XENA_EEPROM_SPACE);
5908}
5909
ac1f60db 5910static int s2io_ethtool_self_test_count(struct net_device *dev)
1da177e4
LT		 5911{
5912 return (S2IO_TEST_LEN);
5913}
ac1f60db
AB		 5914
5915static void s2io_ethtool_get_strings(struct net_device *dev,
5916 u32 stringset, u8 * data)
1da177e4 5917{
fa1f0cb3
SS		 5918 int stat_size = 0;
5919 struct s2io_nic *sp = dev->priv;
5920
1da177e4
LT		 5921 switch (stringset) {
5922 case ETH_SS_TEST:
5923 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5924 break;
5925 case ETH_SS_STATS:
fa1f0cb3
SS		 5926 stat_size = sizeof(ethtool_xena_stats_keys);
5927 memcpy(data, &ethtool_xena_stats_keys,stat_size);
5928 if(sp->device_type == XFRAME_II_DEVICE) {
5929 memcpy(data + stat_size,
5930 &ethtool_enhanced_stats_keys,
5931 sizeof(ethtool_enhanced_stats_keys));
5932 stat_size += sizeof(ethtool_enhanced_stats_keys);
5933 }
5934
5935 memcpy(data + stat_size, &ethtool_driver_stats_keys,
5936 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 5937 }
5938}
1da177e4
LT		 5939static int s2io_ethtool_get_stats_count(struct net_device *dev)
5940{
fa1f0cb3
SS		 5941 struct s2io_nic *sp = dev->priv;
5942 int stat_count = 0;
5943 switch(sp->device_type) {
5944 case XFRAME_I_DEVICE:
5945 stat_count = XFRAME_I_STAT_LEN;
5946 break;
5947
5948 case XFRAME_II_DEVICE:
5949 stat_count = XFRAME_II_STAT_LEN;
5950 break;
5951 }
5952
5953 return stat_count;
1da177e4
LT		 5954}
5955
ac1f60db 5956static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 5957{
5958 if (data)
5959 dev->features |= NETIF_F_IP_CSUM;
5960 else
5961 dev->features &= ~NETIF_F_IP_CSUM;
5962
5963 return 0;
5964}
5965
75c30b13
AR		 5966static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
5967{
5968 return (dev->features & NETIF_F_TSO) != 0;
5969}
5970static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
5971{
5972 if (data)
5973 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
5974 else
5975 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
5976
5977 return 0;
5978}
1da177e4 5979
7282d491 5980static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 5981 .get_settings = s2io_ethtool_gset,
5982 .set_settings = s2io_ethtool_sset,
5983 .get_drvinfo = s2io_ethtool_gdrvinfo,
5984 .get_regs_len = s2io_ethtool_get_regs_len,
5985 .get_regs = s2io_ethtool_gregs,
5986 .get_link = ethtool_op_get_link,
5987 .get_eeprom_len = s2io_get_eeprom_len,
5988 .get_eeprom = s2io_ethtool_geeprom,
5989 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 5990 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 5991 .get_pauseparam = s2io_ethtool_getpause_data,
5992 .set_pauseparam = s2io_ethtool_setpause_data,
5993 .get_rx_csum = s2io_ethtool_get_rx_csum,
5994 .set_rx_csum = s2io_ethtool_set_rx_csum,
5995 .get_tx_csum = ethtool_op_get_tx_csum,
5996 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5997 .get_sg = ethtool_op_get_sg,
5998 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 5999 .get_tso = s2io_ethtool_op_get_tso,
6000 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd
AR		 6001 .get_ufo = ethtool_op_get_ufo,
6002 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6003 .self_test_count = s2io_ethtool_self_test_count,
6004 .self_test = s2io_ethtool_test,
6005 .get_strings = s2io_ethtool_get_strings,
6006 .phys_id = s2io_ethtool_idnic,
6007 .get_stats_count = s2io_ethtool_get_stats_count,
6008 .get_ethtool_stats = s2io_get_ethtool_stats
6009};
6010
6011/**
20346722 6012 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6013 * @dev : Device pointer.
6014 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6015 * a proprietary structure used to pass information to the driver.
6016 * @cmd : This is used to distinguish between the different commands that
6017 * can be passed to the IOCTL functions.
6018 * Description:
20346722
K		 6019 * Currently there are no special functionality supported in IOCTL, hence
6020 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6021 */
6022
ac1f60db 6023static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6024{
6025 return -EOPNOTSUPP;
6026}
6027
6028/**
6029 * s2io_change_mtu - entry point to change MTU size for the device.
6030 * @dev : device pointer.
6031 * @new_mtu : the new MTU size for the device.
6032 * Description: A driver entry point to change MTU size for the device.
6033 * Before changing the MTU the device must be stopped.
6034 * Return value:
6035 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6036 * file on failure.
6037 */
6038
ac1f60db 6039static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6040{
1ee6dd77 6041 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6042
6043 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6044 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6045 dev->name);
6046 return -EPERM;
6047 }
6048
1da177e4 6049 dev->mtu = new_mtu;
d8892c6e 6050 if (netif_running(dev)) {
e6a8fee2 6051 s2io_card_down(sp);
d8892c6e
K		 6052 netif_stop_queue(dev);
6053 if (s2io_card_up(sp)) {
6054 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6055 __FUNCTION__);
6056 }
6057 if (netif_queue_stopped(dev))
6058 netif_wake_queue(dev);
6059 } else { /* Device is down */
1ee6dd77 6060 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e
K		 6061 u64 val64 = new_mtu;
6062
6063 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6064 }
1da177e4
LT		 6065
6066 return 0;
6067}
6068
6069/**
6070 * s2io_tasklet - Bottom half of the ISR.
6071 * @dev_adr : address of the device structure in dma_addr_t format.
6072 * Description:
6073 * This is the tasklet or the bottom half of the ISR. This is
20346722 6074 * an extension of the ISR which is scheduled by the scheduler to be run
1da177e4 6075 * when the load on the CPU is low. All low priority tasks of the ISR can
20346722 6076 * be pushed into the tasklet. For now the tasklet is used only to
1da177e4
LT		 6077 * replenish the Rx buffers in the Rx buffer descriptors.
6078 * Return value:
6079 * void.
6080 */
6081
6082static void s2io_tasklet(unsigned long dev_addr)
6083{
6084 struct net_device *dev = (struct net_device *) dev_addr;
1ee6dd77 6085 struct s2io_nic *sp = dev->priv;
1da177e4 6086 int i, ret;
1ee6dd77 6087 struct mac_info *mac_control;
1da177e4
LT		 6088 struct config_param *config;
6089
6090 mac_control = &sp->mac_control;
6091 config = &sp->config;
6092
6093 if (!TASKLET_IN_USE) {
6094 for (i = 0; i < config->rx_ring_num; i++) {
6095 ret = fill_rx_buffers(sp, i);
6096 if (ret == -ENOMEM) {
0c61ed5f 6097 DBG_PRINT(INFO_DBG, "%s: Out of ",
1da177e4 6098 dev->name);
491976b2 6099 DBG_PRINT(INFO_DBG, "memory in tasklet\n");
1da177e4
LT		 6100 break;
6101 } else if (ret == -EFILL) {
0c61ed5f 6102 DBG_PRINT(INFO_DBG,
1da177e4
LT		 6103 "%s: Rx Ring %d is full\n",
6104 dev->name, i);
6105 break;
6106 }
6107 }
6108 clear_bit(0, (&sp->tasklet_status));
6109 }
6110}
6111
6112/**
6113 * s2io_set_link - Set the LInk status
6114 * @data: long pointer to device private structue
6115 * Description: Sets the link status for the adapter
6116 */
6117
c4028958 6118static void s2io_set_link(struct work_struct *work)
1da177e4 6119{
1ee6dd77 6120 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
1da177e4 6121 struct net_device *dev = nic->dev;
1ee6dd77 6122 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6123 register u64 val64;
6124 u16 subid;
6125
22747d6b
FR		 6126 rtnl_lock();
6127
6128 if (!netif_running(dev))
6129 goto out_unlock;
6130
1da177e4
LT		 6131 if (test_and_set_bit(0, &(nic->link_state))) {
6132 /* The card is being reset, no point doing anything */
22747d6b 6133 goto out_unlock;
1da177e4
LT		 6134 }
6135
6136 subid = nic->pdev->subsystem_device;
a371a07d
K		 6137 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6138 /*
6139 * Allow a small delay for the NICs self initiated
6140 * cleanup to complete.
6141 */
6142 msleep(100);
6143 }
1da177e4
LT		 6144
6145 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6146 if (LINK_IS_UP(val64)) {
6147 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6148 if (verify_xena_quiescence(nic)) {
6149 val64 = readq(&bar0->adapter_control);
6150 val64 |= ADAPTER_CNTL_EN;
1da177e4 6151 writeq(val64, &bar0->adapter_control);
19a60522
SS		 6152 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6153 nic->device_type, subid)) {
6154 val64 = readq(&bar0->gpio_control);
6155 val64 |= GPIO_CTRL_GPIO_0;
6156 writeq(val64, &bar0->gpio_control);
6157 val64 = readq(&bar0->gpio_control);
6158 } else {
6159 val64 |= ADAPTER_LED_ON;
6160 writeq(val64, &bar0->adapter_control);
a371a07d 6161 }
1da177e4 6162 nic->device_enabled_once = TRUE;
19a60522
SS		 6163 } else {
6164 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6165 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6166 netif_stop_queue(dev);
1da177e4 6167 }
19a60522
SS		 6168 }
6169 val64 = readq(&bar0->adapter_status);
6170 if (!LINK_IS_UP(val64)) {
6171 DBG_PRINT(ERR_DBG, "%s:", dev->name);
6172 DBG_PRINT(ERR_DBG, " Link down after enabling ");
6173 DBG_PRINT(ERR_DBG, "device \n");
6174 } else
1da177e4 6175 s2io_link(nic, LINK_UP);
19a60522
SS		 6176 } else {
6177 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6178 subid)) {
6179 val64 = readq(&bar0->gpio_control);
6180 val64 &= ~GPIO_CTRL_GPIO_0;
6181 writeq(val64, &bar0->gpio_control);
6182 val64 = readq(&bar0->gpio_control);
1da177e4 6183 }
19a60522 6184 s2io_link(nic, LINK_DOWN);
1da177e4
LT		 6185 }
6186 clear_bit(0, &(nic->link_state));
22747d6b
FR		 6187
6188out_unlock:
d8d70caf 6189 rtnl_unlock();
1da177e4
LT		 6190}
6191
1ee6dd77
RB		 6192static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6193 struct buffAdd *ba,
6194 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6195 u64 *temp2, int size)
5d3213cc
AR		 6196{
6197 struct net_device *dev = sp->dev;
5d3213cc
AR		 6198
6199 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6200 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6201 /* allocate skb */
6202 if (*skb) {
6203 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6204 /*
6205 * As Rx frame are not going to be processed,
6206 * using same mapped address for the Rxd
6207 * buffer pointer
6208 */
6d517a27 6209 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6210 } else {
6211 *skb = dev_alloc_skb(size);
6212 if (!(*skb)) {
0c61ed5f 6213 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
c53d4945
SH		 6214 DBG_PRINT(INFO_DBG, "memory to allocate ");
6215 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6216 sp->mac_control.stats_info->sw_stat. \
6217 mem_alloc_fail_cnt++;
5d3213cc
AR		 6218 return -ENOMEM ;
6219 }
491976b2
SH		 6220 sp->mac_control.stats_info->sw_stat.mem_allocated
6221 += (*skb)->truesize;
5d3213cc
AR		 6222 /* storing the mapped addr in a temp variable
6223 * such it will be used for next rxd whose
6224 * Host Control is NULL
6225 */
6d517a27 6226 rxdp1->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6227 pci_map_single( sp->pdev, (*skb)->data,
6228 size - NET_IP_ALIGN,
6229 PCI_DMA_FROMDEVICE);
6230 rxdp->Host_Control = (unsigned long) (*skb);
6231 }
6232 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6233 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6234 /* Two buffer Mode */
6235 if (*skb) {
6d517a27
VP		 6236 rxdp3->Buffer2_ptr = *temp2;
6237 rxdp3->Buffer0_ptr = *temp0;
6238 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6239 } else {
6240 *skb = dev_alloc_skb(size);
2ceaac75 6241 if (!(*skb)) {
c53d4945
SH		 6242 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6243 DBG_PRINT(INFO_DBG, "memory to allocate ");
6244 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6245 sp->mac_control.stats_info->sw_stat. \
6246 mem_alloc_fail_cnt++;
2ceaac75
DR		 6247 return -ENOMEM;
6248 }
491976b2
SH		 6249 sp->mac_control.stats_info->sw_stat.mem_allocated
6250 += (*skb)->truesize;
6d517a27 6251 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6252 pci_map_single(sp->pdev, (*skb)->data,
6253 dev->mtu + 4,
6254 PCI_DMA_FROMDEVICE);
6d517a27 6255 rxdp3->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6256 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6257 PCI_DMA_FROMDEVICE);
6258 rxdp->Host_Control = (unsigned long) (*skb);
6259
6260 /* Buffer-1 will be dummy buffer not used */
6d517a27 6261 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6262 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
5d3213cc 6263 PCI_DMA_FROMDEVICE);
5d3213cc
AR		 6264 }
6265 }
6266 return 0;
6267}
1ee6dd77
RB		 6268static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6269 int size)
5d3213cc
AR		 6270{
6271 struct net_device *dev = sp->dev;
6272 if (sp->rxd_mode == RXD_MODE_1) {
6273 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6274 } else if (sp->rxd_mode == RXD_MODE_3B) {
6275 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6276 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6277 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
5d3213cc
AR		 6278 }
6279}
6280
1ee6dd77 6281static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6282{
6283 int i, j, k, blk_cnt = 0, size;
1ee6dd77 6284 struct mac_info * mac_control = &sp->mac_control;
5d3213cc
AR		 6285 struct config_param *config = &sp->config;
6286 struct net_device *dev = sp->dev;
1ee6dd77 6287 struct RxD_t *rxdp = NULL;
5d3213cc 6288 struct sk_buff *skb = NULL;
1ee6dd77 6289 struct buffAdd *ba = NULL;
5d3213cc
AR		 6290 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6291
6292 /* Calculate the size based on ring mode */
6293 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6294 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6295 if (sp->rxd_mode == RXD_MODE_1)
6296 size += NET_IP_ALIGN;
6297 else if (sp->rxd_mode == RXD_MODE_3B)
6298 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 6299
6300 for (i = 0; i < config->rx_ring_num; i++) {
6301 blk_cnt = config->rx_cfg[i].num_rxd /
6302 (rxd_count[sp->rxd_mode] +1);
6303
6304 for (j = 0; j < blk_cnt; j++) {
6305 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6306 rxdp = mac_control->rings[i].
6307 rx_blocks[j].rxds[k].virt_addr;
6d517a27 6308 if(sp->rxd_mode == RXD_MODE_3B)
5d3213cc 6309 ba = &mac_control->rings[i].ba[j][k];
ac1f90d6 6310 if (set_rxd_buffer_pointer(sp, rxdp, ba,
5d3213cc
AR		 6311 &skb,(u64 *)&temp0_64,
6312 (u64 *)&temp1_64,
ac1f90d6
SS		 6313 (u64 *)&temp2_64,
6314 size) == ENOMEM) {
6315 return 0;
6316 }
5d3213cc
AR		 6317
6318 set_rxd_buffer_size(sp, rxdp, size);
6319 wmb();
6320 /* flip the Ownership bit to Hardware */
6321 rxdp->Control_1 |= RXD_OWN_XENA;
6322 }
6323 }
6324 }
6325 return 0;
6326
6327}
6328
1ee6dd77 6329static int s2io_add_isr(struct s2io_nic * sp)
1da177e4 6330{
e6a8fee2 6331 int ret = 0;
c92ca04b 6332 struct net_device *dev = sp->dev;
e6a8fee2 6333 int err = 0;
1da177e4 6334
e6a8fee2
AR		 6335 if (sp->intr_type == MSI)
6336 ret = s2io_enable_msi(sp);
6337 else if (sp->intr_type == MSI_X)
6338 ret = s2io_enable_msi_x(sp);
6339 if (ret) {
6340 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6341 sp->intr_type = INTA;
20346722 6342 }
1da177e4 6343
1ee6dd77 6344 /* Store the values of the MSIX table in the struct s2io_nic structure */
e6a8fee2 6345 store_xmsi_data(sp);
c92ca04b 6346
e6a8fee2
AR		 6347 /* After proper initialization of H/W, register ISR */
6348 if (sp->intr_type == MSI) {
6349 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
6350 IRQF_SHARED, sp->name, dev);
6351 if (err) {
6352 pci_disable_msi(sp->pdev);
6353 DBG_PRINT(ERR_DBG, "%s: MSI registration failed\n",
6354 dev->name);
6355 return -1;
6356 }
6357 }
6358 if (sp->intr_type == MSI_X) {
fb6a825b 6359 int i, msix_tx_cnt=0,msix_rx_cnt=0;
c92ca04b 6360
e6a8fee2
AR		 6361 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6362 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6363 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6364 dev->name, i);
6365 err = request_irq(sp->entries[i].vector,
6366 s2io_msix_fifo_handle, 0, sp->desc[i],
6367 sp->s2io_entries[i].arg);
fb6a825b
SS		 6368 /* If either data or addr is zero print it */
6369 if(!(sp->msix_info[i].addr &&
6370 sp->msix_info[i].data)) {
6371 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6372 "Data:0x%lx\n",sp->desc[i],
6373 (unsigned long long)
6374 sp->msix_info[i].addr,
6375 (unsigned long)
6376 ntohl(sp->msix_info[i].data));
6377 } else {
6378 msix_tx_cnt++;
6379 }
e6a8fee2
AR		 6380 } else {
6381 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6382 dev->name, i);
6383 err = request_irq(sp->entries[i].vector,
6384 s2io_msix_ring_handle, 0, sp->desc[i],
6385 sp->s2io_entries[i].arg);
fb6a825b
SS		 6386 /* If either data or addr is zero print it */
6387 if(!(sp->msix_info[i].addr &&
6388 sp->msix_info[i].data)) {
6389 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6390 "Data:0x%lx\n",sp->desc[i],
6391 (unsigned long long)
6392 sp->msix_info[i].addr,
6393 (unsigned long)
6394 ntohl(sp->msix_info[i].data));
6395 } else {
6396 msix_rx_cnt++;
6397 }
c92ca04b 6398 }
e6a8fee2
AR		 6399 if (err) {
6400 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6401 "failed\n", dev->name, i);
6402 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6403 return -1;
6404 }
6405 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6406 }
fb6a825b
SS		 6407 printk("MSI-X-TX %d entries enabled\n",msix_tx_cnt);
6408 printk("MSI-X-RX %d entries enabled\n",msix_rx_cnt);
e6a8fee2
AR		 6409 }
6410 if (sp->intr_type == INTA) {
6411 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6412 sp->name, dev);
6413 if (err) {
6414 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6415 dev->name);
6416 return -1;
6417 }
6418 }
6419 return 0;
6420}
1ee6dd77 6421static void s2io_rem_isr(struct s2io_nic * sp)
e6a8fee2
AR		 6422{
6423 int cnt = 0;
6424 struct net_device *dev = sp->dev;
6425
6426 if (sp->intr_type == MSI_X) {
6427 int i;
6428 u16 msi_control;
6429
6430 for (i=1; (sp->s2io_entries[i].in_use ==
6431 MSIX_REGISTERED_SUCCESS); i++) {
6432 int vector = sp->entries[i].vector;
6433 void *arg = sp->s2io_entries[i].arg;
6434
6435 free_irq(vector, arg);
6436 }
6437 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6438 msi_control &= 0xFFFE; /* Disable MSI */
6439 pci_write_config_word(sp->pdev, 0x42, msi_control);
6440
6441 pci_disable_msix(sp->pdev);
6442 } else {
6443 free_irq(sp->pdev->irq, dev);
6444 if (sp->intr_type == MSI) {
6445 u16 val;
6446
6447 pci_disable_msi(sp->pdev);
6448 pci_read_config_word(sp->pdev, 0x4c, &val);
6449 val ^= 0x1;
6450 pci_write_config_word(sp->pdev, 0x4c, val);
c92ca04b
AR		 6451 }
6452 }
6453 /* Waiting till all Interrupt handlers are complete */
6454 cnt = 0;
6455 do {
6456 msleep(10);
6457 if (!atomic_read(&sp->isr_cnt))
6458 break;
6459 cnt++;
6460 } while(cnt < 5);
e6a8fee2
AR		 6461}
6462
d796fdb7 6463static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
e6a8fee2
AR		 6464{
6465 int cnt = 0;
1ee6dd77 6466 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2
AR		 6467 unsigned long flags;
6468 register u64 val64 = 0;
6469
6470 del_timer_sync(&sp->alarm_timer);
6471 /* If s2io_set_link task is executing, wait till it completes. */
6472 while (test_and_set_bit(0, &(sp->link_state))) {
6473 msleep(50);
6474 }
6475 atomic_set(&sp->card_state, CARD_DOWN);
6476
6477 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 6478 if (do_io)
6479 stop_nic(sp);
e6a8fee2
AR		 6480
6481 s2io_rem_isr(sp);
1da177e4
LT		 6482
6483 /* Kill tasklet. */
6484 tasklet_kill(&sp->task);
6485
6486 /* Check if the device is Quiescent and then Reset the NIC */
d796fdb7 6487 while(do_io) {
5d3213cc
AR		 6488 /* As per the HW requirement we need to replenish the
6489 * receive buffer to avoid the ring bump. Since there is
6490 * no intention of processing the Rx frame at this pointwe are
6491 * just settting the ownership bit of rxd in Each Rx
6492 * ring to HW and set the appropriate buffer size
6493 * based on the ring mode
6494 */
6495 rxd_owner_bit_reset(sp);
6496
1da177e4 6497 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6498 if (verify_xena_quiescence(sp)) {
6499 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
1da177e4
LT		 6500 break;
6501 }
6502
6503 msleep(50);
6504 cnt++;
6505 if (cnt == 10) {
6506 DBG_PRINT(ERR_DBG,
6507 "s2io_close:Device not Quiescent ");
6508 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6509 (unsigned long long) val64);
6510 break;
6511 }
d796fdb7
LV		 6512 }
6513 if (do_io)
6514 s2io_reset(sp);
1da177e4 6515
7ba013ac
K		 6516 spin_lock_irqsave(&sp->tx_lock, flags);
6517 /* Free all Tx buffers */
1da177e4 6518 free_tx_buffers(sp);
7ba013ac
K		 6519 spin_unlock_irqrestore(&sp->tx_lock, flags);
6520
6521 /* Free all Rx buffers */
6522 spin_lock_irqsave(&sp->rx_lock, flags);
1da177e4 6523 free_rx_buffers(sp);
7ba013ac 6524 spin_unlock_irqrestore(&sp->rx_lock, flags);
1da177e4 6525
1da177e4
LT		 6526 clear_bit(0, &(sp->link_state));
6527}
6528
d796fdb7
LV		 6529static void s2io_card_down(struct s2io_nic * sp)
6530{
6531 do_s2io_card_down(sp, 1);
6532}
6533
1ee6dd77 6534static int s2io_card_up(struct s2io_nic * sp)
1da177e4 6535{
cc6e7c44 6536 int i, ret = 0;
1ee6dd77 6537 struct mac_info *mac_control;
1da177e4
LT		 6538 struct config_param *config;
6539 struct net_device *dev = (struct net_device *) sp->dev;
e6a8fee2 6540 u16 interruptible;
1da177e4
LT		 6541
6542 /* Initialize the H/W I/O registers */
6543 if (init_nic(sp) != 0) {
6544 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6545 dev->name);
e6a8fee2 6546 s2io_reset(sp);
1da177e4
LT		 6547 return -ENODEV;
6548 }
6549
20346722
K		 6550 /*
6551 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 6552 * Rx ring and initializing buffers into 30 Rx blocks
6553 */
6554 mac_control = &sp->mac_control;
6555 config = &sp->config;
6556
6557 for (i = 0; i < config->rx_ring_num; i++) {
6558 if ((ret = fill_rx_buffers(sp, i))) {
6559 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6560 dev->name);
6561 s2io_reset(sp);
6562 free_rx_buffers(sp);
6563 return -ENOMEM;
6564 }
6565 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6566 atomic_read(&sp->rx_bufs_left[i]));
6567 }
19a60522
SS		 6568 /* Maintain the state prior to the open */
6569 if (sp->promisc_flg)
6570 sp->promisc_flg = 0;
6571 if (sp->m_cast_flg) {
6572 sp->m_cast_flg = 0;
6573 sp->all_multi_pos= 0;
6574 }
1da177e4
LT		 6575
6576 /* Setting its receive mode */
6577 s2io_set_multicast(dev);
6578
7d3d0439 6579 if (sp->lro) {
b41477f3 6580 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439
RA		 6581 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6582 /* Check if we can use(if specified) user provided value */
6583 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6584 sp->lro_max_aggr_per_sess = lro_max_pkts;
6585 }
6586
1da177e4
LT		 6587 /* Enable Rx Traffic and interrupts on the NIC */
6588 if (start_nic(sp)) {
6589 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 6590 s2io_reset(sp);
e6a8fee2
AR		 6591 free_rx_buffers(sp);
6592 return -ENODEV;
6593 }
6594
6595 /* Add interrupt service routine */
6596 if (s2io_add_isr(sp) != 0) {
6597 if (sp->intr_type == MSI_X)
6598 s2io_rem_isr(sp);
6599 s2io_reset(sp);
1da177e4
LT		 6600 free_rx_buffers(sp);
6601 return -ENODEV;
6602 }
6603
25fff88e
K		 6604 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6605
e6a8fee2
AR		 6606 /* Enable tasklet for the device */
6607 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6608
6609 /* Enable select interrupts */
6610 if (sp->intr_type != INTA)
6611 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6612 else {
6613 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6614 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
6615 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
6616 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6617 }
6618
6619
1da177e4
LT		 6620 atomic_set(&sp->card_state, CARD_UP);
6621 return 0;
6622}
6623
20346722 6624/**
1da177e4
LT		 6625 * s2io_restart_nic - Resets the NIC.
6626 * @data : long pointer to the device private structure
6627 * Description:
6628 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 6629 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 6630 * the run time of the watch dog routine which is run holding a
6631 * spin lock.
6632 */
6633
c4028958 6634static void s2io_restart_nic(struct work_struct *work)
1da177e4 6635{
1ee6dd77 6636 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 6637 struct net_device *dev = sp->dev;
1da177e4 6638
22747d6b
FR		 6639 rtnl_lock();
6640
6641 if (!netif_running(dev))
6642 goto out_unlock;
6643
e6a8fee2 6644 s2io_card_down(sp);
1da177e4
LT		 6645 if (s2io_card_up(sp)) {
6646 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6647 dev->name);
6648 }
6649 netif_wake_queue(dev);
6650 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
6651 dev->name);
22747d6b
FR		 6652out_unlock:
6653 rtnl_unlock();
1da177e4
LT		 6654}
6655
20346722
K		 6656/**
6657 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 6658 * @dev : Pointer to net device structure
6659 * Description:
6660 * This function is triggered if the Tx Queue is stopped
6661 * for a pre-defined amount of time when the Interface is still up.
6662 * If the Interface is jammed in such a situation, the hardware is
6663 * reset (by s2io_close) and restarted again (by s2io_open) to
6664 * overcome any problem that might have been caused in the hardware.
6665 * Return value:
6666 * void
6667 */
6668
6669static void s2io_tx_watchdog(struct net_device *dev)
6670{
1ee6dd77 6671 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6672
6673 if (netif_carrier_ok(dev)) {
c53d4945 6674 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
1da177e4 6675 schedule_work(&sp->rst_timer_task);
bd1034f0 6676 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 6677 }
6678}
6679
6680/**
6681 * rx_osm_handler - To perform some OS related operations on SKB.
6682 * @sp: private member of the device structure,pointer to s2io_nic structure.
6683 * @skb : the socket buffer pointer.
6684 * @len : length of the packet
6685 * @cksum : FCS checksum of the frame.
6686 * @ring_no : the ring from which this RxD was extracted.
20346722 6687 * Description:
b41477f3 6688 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 6689 * some OS related operations on the SKB before passing it to the upper
6690 * layers. It mainly checks if the checksum is OK, if so adds it to the
6691 * SKBs cksum variable, increments the Rx packet count and passes the SKB
6692 * to the upper layer. If the checksum is wrong, it increments the Rx
6693 * packet error count, frees the SKB and returns error.
6694 * Return value:
6695 * SUCCESS on success and -1 on failure.
6696 */
1ee6dd77 6697static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 6698{
1ee6dd77 6699 struct s2io_nic *sp = ring_data->nic;
1da177e4 6700 struct net_device *dev = (struct net_device *) sp->dev;
20346722
K		 6701 struct sk_buff *skb = (struct sk_buff *)
6702 ((unsigned long) rxdp->Host_Control);
6703 int ring_no = ring_data->ring_no;
1da177e4 6704 u16 l3_csum, l4_csum;
863c11a9 6705 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
1ee6dd77 6706 struct lro *lro;
f9046eb3 6707 u8 err_mask;
da6971d8 6708
20346722 6709 skb->dev = dev;
c92ca04b 6710
863c11a9 6711 if (err) {
bd1034f0
AR		 6712 /* Check for parity error */
6713 if (err & 0x1) {
6714 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
6715 }
f9046eb3
OH		 6716 err_mask = err >> 48;
6717 switch(err_mask) {
491976b2
SH		 6718 case 1:
6719 sp->mac_control.stats_info->sw_stat.
6720 rx_parity_err_cnt++;
6721 break;
6722
6723 case 2:
6724 sp->mac_control.stats_info->sw_stat.
6725 rx_abort_cnt++;
6726 break;
6727
6728 case 3:
6729 sp->mac_control.stats_info->sw_stat.
6730 rx_parity_abort_cnt++;
6731 break;
6732
6733 case 4:
6734 sp->mac_control.stats_info->sw_stat.
6735 rx_rda_fail_cnt++;
6736 break;
6737
6738 case 5:
6739 sp->mac_control.stats_info->sw_stat.
6740 rx_unkn_prot_cnt++;
6741 break;
6742
6743 case 6:
6744 sp->mac_control.stats_info->sw_stat.
6745 rx_fcs_err_cnt++;
6746 break;
bd1034f0 6747
491976b2
SH		 6748 case 7:
6749 sp->mac_control.stats_info->sw_stat.
6750 rx_buf_size_err_cnt++;
6751 break;
6752
6753 case 8:
6754 sp->mac_control.stats_info->sw_stat.
6755 rx_rxd_corrupt_cnt++;
6756 break;
6757
6758 case 15:
6759 sp->mac_control.stats_info->sw_stat.
6760 rx_unkn_err_cnt++;
6761 break;
6762 }
863c11a9
AR		 6763 /*
6764 * Drop the packet if bad transfer code. Exception being
6765 * 0x5, which could be due to unsupported IPv6 extension header.
6766 * In this case, we let stack handle the packet.
6767 * Note that in this case, since checksum will be incorrect,
6768 * stack will validate the same.
6769 */
f9046eb3
OH		 6770 if (err_mask != 0x5) {
6771 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
6772 dev->name, err_mask);
863c11a9 6773 sp->stats.rx_crc_errors++;
491976b2
SH		 6774 sp->mac_control.stats_info->sw_stat.mem_freed
6775 += skb->truesize;
863c11a9
AR		 6776 dev_kfree_skb(skb);
6777 atomic_dec(&sp->rx_bufs_left[ring_no]);
6778 rxdp->Host_Control = 0;
6779 return 0;
6780 }
20346722 6781 }
1da177e4 6782
20346722
K		 6783 /* Updating statistics */
6784 rxdp->Host_Control = 0;
da6971d8
AR		 6785 if (sp->rxd_mode == RXD_MODE_1) {
6786 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 6787
da6971d8
AR		 6788 sp->stats.rx_bytes += len;
6789 skb_put(skb, len);
6790
6d517a27 6791 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 6792 int get_block = ring_data->rx_curr_get_info.block_index;
6793 int get_off = ring_data->rx_curr_get_info.offset;
6794 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
6795 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
6796 unsigned char *buff = skb_push(skb, buf0_len);
6797
1ee6dd77 6798 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
da6971d8
AR		 6799 sp->stats.rx_bytes += buf0_len + buf2_len;
6800 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 6801 skb_put(skb, buf2_len);
da6971d8 6802 }
20346722 6803
7d3d0439
RA		 6804 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
6805 (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722
K		 6806 (sp->rx_csum)) {
6807 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 6808 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
6809 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 6810 /*
1da177e4
LT		 6811 * NIC verifies if the Checksum of the received
6812 * frame is Ok or not and accordingly returns
6813 * a flag in the RxD.
6814 */
6815 skb->ip_summed = CHECKSUM_UNNECESSARY;
7d3d0439
RA		 6816 if (sp->lro) {
6817 u32 tcp_len;
6818 u8 *tcp;
6819 int ret = 0;
6820
6821 ret = s2io_club_tcp_session(skb->data, &tcp,
6822 &tcp_len, &lro, rxdp, sp);
6823 switch (ret) {
6824 case 3: /* Begin anew */
6825 lro->parent = skb;
6826 goto aggregate;
6827 case 1: /* Aggregate */
6828 {
6829 lro_append_pkt(sp, lro,
6830 skb, tcp_len);
6831 goto aggregate;
6832 }
6833 case 4: /* Flush session */
6834 {
6835 lro_append_pkt(sp, lro,
6836 skb, tcp_len);
6837 queue_rx_frame(lro->parent);
6838 clear_lro_session(lro);
6839 sp->mac_control.stats_info->
6840 sw_stat.flush_max_pkts++;
6841 goto aggregate;
6842 }
6843 case 2: /* Flush both */
6844 lro->parent->data_len =
6845 lro->frags_len;
6846 sp->mac_control.stats_info->
6847 sw_stat.sending_both++;
6848 queue_rx_frame(lro->parent);
6849 clear_lro_session(lro);
6850 goto send_up;
6851 case 0: /* sessions exceeded */
c92ca04b
AR		 6852 case -1: /* non-TCP or not
6853 * L2 aggregatable
6854 */
7d3d0439
RA		 6855 case 5: /*
6856 * First pkt in session not
6857 * L3/L4 aggregatable
6858 */
6859 break;
6860 default:
6861 DBG_PRINT(ERR_DBG,
6862 "%s: Samadhana!!\n",
6863 __FUNCTION__);
6864 BUG();
6865 }
6866 }
1da177e4 6867 } else {
20346722
K		 6868 /*
6869 * Packet with erroneous checksum, let the
1da177e4
LT		 6870 * upper layers deal with it.
6871 */
6872 skb->ip_summed = CHECKSUM_NONE;
6873 }
6874 } else {
6875 skb->ip_summed = CHECKSUM_NONE;
6876 }
491976b2 6877 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7d3d0439
RA		 6878 if (!sp->lro) {
6879 skb->protocol = eth_type_trans(skb, dev);
926930b2
SS		 6880 if ((sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2) &&
6881 vlan_strip_flag)) {
7d3d0439 6882 /* Queueing the vlan frame to the upper layer */
db874e65
SS		 6883 if (napi)
6884 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
6885 RXD_GET_VLAN_TAG(rxdp->Control_2));
6886 else
6887 vlan_hwaccel_rx(skb, sp->vlgrp,
6888 RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 6889 } else {
db874e65
SS		 6890 if (napi)
6891 netif_receive_skb(skb);
6892 else
6893 netif_rx(skb);
7d3d0439 6894 }
7d3d0439
RA		 6895 } else {
6896send_up:
6897 queue_rx_frame(skb);
6aa20a22 6898 }
1da177e4 6899 dev->last_rx = jiffies;
7d3d0439 6900aggregate:
1da177e4 6901 atomic_dec(&sp->rx_bufs_left[ring_no]);
1da177e4
LT		 6902 return SUCCESS;
6903}
6904
6905/**
6906 * s2io_link - stops/starts the Tx queue.
6907 * @sp : private member of the device structure, which is a pointer to the
6908 * s2io_nic structure.
6909 * @link : inidicates whether link is UP/DOWN.
6910 * Description:
6911 * This function stops/starts the Tx queue depending on whether the link
20346722
K		 6912 * status of the NIC is is down or up. This is called by the Alarm
6913 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 6914 * Return value:
6915 * void.
6916 */
6917
1ee6dd77 6918static void s2io_link(struct s2io_nic * sp, int link)
1da177e4
LT		 6919{
6920 struct net_device *dev = (struct net_device *) sp->dev;
6921
6922 if (link != sp->last_link_state) {
6923 if (link == LINK_DOWN) {
6924 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
6925 netif_carrier_off(dev);
491976b2
SH		 6926 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
6927 sp->mac_control.stats_info->sw_stat.link_up_time =
6928 jiffies - sp->start_time;
6929 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
1da177e4
LT		 6930 } else {
6931 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
491976b2
SH		 6932 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
6933 sp->mac_control.stats_info->sw_stat.link_down_time =
6934 jiffies - sp->start_time;
6935 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
1da177e4
LT		 6936 netif_carrier_on(dev);
6937 }
6938 }
6939 sp->last_link_state = link;
491976b2 6940 sp->start_time = jiffies;
1da177e4
LT		 6941}
6942
20346722
K		 6943/**
6944 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
6945 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 6946 * s2io_nic structure.
6947 * Description:
6948 * This function initializes a few of the PCI and PCI-X configuration registers
6949 * with recommended values.
6950 * Return value:
6951 * void
6952 */
6953
1ee6dd77 6954static void s2io_init_pci(struct s2io_nic * sp)
1da177e4 6955{
20346722 6956 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 6957
6958 /* Enable Data Parity Error Recovery in PCI-X command register. */
6959 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6960 &(pcix_cmd));
1da177e4 6961 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6962 (pcix_cmd | 1));
1da177e4 6963 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6964 &(pcix_cmd));
1da177e4
LT		 6965
6966 /* Set the PErr Response bit in PCI command register. */
6967 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
6968 pci_write_config_word(sp->pdev, PCI_COMMAND,
6969 (pci_cmd | PCI_COMMAND_PARITY));
6970 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 6971}
6972
9dc737a7
AR		 6973static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
6974{
6975 if ( tx_fifo_num > 8) {
6976 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
6977 "supported\n");
6978 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
6979 tx_fifo_num = 8;
6980 }
6981 if ( rx_ring_num > 8) {
6982 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
6983 "supported\n");
6984 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
6985 rx_ring_num = 8;
6986 }
db874e65
SS		 6987 if (*dev_intr_type != INTA)
6988 napi = 0;
6989
9dc737a7
AR		 6990#ifndef CONFIG_PCI_MSI
6991 if (*dev_intr_type != INTA) {
6992 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
6993 "MSI/MSI-X. Defaulting to INTA\n");
6994 *dev_intr_type = INTA;
6995 }
6996#else
6997 if (*dev_intr_type > MSI_X) {
6998 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
6999 "Defaulting to INTA\n");
7000 *dev_intr_type = INTA;
7001 }
7002#endif
7003 if ((*dev_intr_type == MSI_X) &&
7004 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7005 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 7006 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
9dc737a7
AR		 7007 "Defaulting to INTA\n");
7008 *dev_intr_type = INTA;
7009 }
fb6a825b 7010
6d517a27 7011 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9dc737a7 7012 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6d517a27
VP		 7013 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7014 rx_ring_mode = 1;
9dc737a7
AR		 7015 }
7016 return SUCCESS;
7017}
7018
9fc93a41
SS		 7019/**
7020 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7021 * or Traffic class respectively.
7022 * @nic: device peivate variable
7023 * Description: The function configures the receive steering to
7024 * desired receive ring.
7025 * Return Value: SUCCESS on success and
7026 * '-1' on failure (endian settings incorrect).
7027 */
7028static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7029{
7030 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7031 register u64 val64 = 0;
7032
7033 if (ds_codepoint > 63)
7034 return FAILURE;
7035
7036 val64 = RTS_DS_MEM_DATA(ring);
7037 writeq(val64, &bar0->rts_ds_mem_data);
7038
7039 val64 = RTS_DS_MEM_CTRL_WE |
7040 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7041 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7042
7043 writeq(val64, &bar0->rts_ds_mem_ctrl);
7044
7045 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7046 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7047 S2IO_BIT_RESET);
7048}
7049
1da177e4 7050/**
20346722 7051 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7052 * @pdev : structure containing the PCI related information of the device.
7053 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7054 * Description:
7055 * The function initializes an adapter identified by the pci_dec structure.
20346722
K		 7056 * All OS related initialization including memory and device structure and
7057 * initlaization of the device private variable is done. Also the swapper
7058 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7059 * registers of the device.
7060 * Return value:
7061 * returns 0 on success and negative on failure.
7062 */
7063
7064static int __devinit
7065s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7066{
1ee6dd77 7067 struct s2io_nic *sp;
1da177e4 7068 struct net_device *dev;
1da177e4
LT		 7069 int i, j, ret;
7070 int dma_flag = FALSE;
7071 u32 mac_up, mac_down;
7072 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7073 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7074 u16 subid;
1ee6dd77 7075 struct mac_info *mac_control;
1da177e4 7076 struct config_param *config;
541ae68f 7077 int mode;
cc6e7c44 7078 u8 dev_intr_type = intr_type;
1da177e4 7079
9dc737a7
AR		 7080 if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
7081 return ret;
1da177e4
LT		 7082
7083 if ((ret = pci_enable_device(pdev))) {
7084 DBG_PRINT(ERR_DBG,
7085 "s2io_init_nic: pci_enable_device failed\n");
7086 return ret;
7087 }
7088
1e7f0bd8 7089 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7090 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7091 dma_flag = TRUE;
1da177e4 7092 if (pci_set_consistent_dma_mask
1e7f0bd8 7093 (pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7094 DBG_PRINT(ERR_DBG,
7095 "Unable to obtain 64bit DMA for \
7096 consistent allocations\n");
7097 pci_disable_device(pdev);
7098 return -ENOMEM;
7099 }
1e7f0bd8 7100 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 7101 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7102 } else {
7103 pci_disable_device(pdev);
7104 return -ENOMEM;
7105 }
cc6e7c44
RA		 7106 if (dev_intr_type != MSI_X) {
7107 if (pci_request_regions(pdev, s2io_driver_name)) {
b41477f3
AR		 7108 DBG_PRINT(ERR_DBG, "Request Regions failed\n");
7109 pci_disable_device(pdev);
cc6e7c44
RA		 7110 return -ENODEV;
7111 }
7112 }
7113 else {
7114 if (!(request_mem_region(pci_resource_start(pdev, 0),
7115 pci_resource_len(pdev, 0), s2io_driver_name))) {
7116 DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
7117 pci_disable_device(pdev);
7118 return -ENODEV;
7119 }
7120 if (!(request_mem_region(pci_resource_start(pdev, 2),
7121 pci_resource_len(pdev, 2), s2io_driver_name))) {
7122 DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
7123 release_mem_region(pci_resource_start(pdev, 0),
7124 pci_resource_len(pdev, 0));
7125 pci_disable_device(pdev);
7126 return -ENODEV;
7127 }
1da177e4
LT		 7128 }
7129
1ee6dd77 7130 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7131 if (dev == NULL) {
7132 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7133 pci_disable_device(pdev);
7134 pci_release_regions(pdev);
7135 return -ENODEV;
7136 }
7137
7138 pci_set_master(pdev);
7139 pci_set_drvdata(pdev, dev);
7140 SET_MODULE_OWNER(dev);
7141 SET_NETDEV_DEV(dev, &pdev->dev);
7142
7143 /* Private member variable initialized to s2io NIC structure */
7144 sp = dev->priv;
1ee6dd77 7145 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7146 sp->dev = dev;
7147 sp->pdev = pdev;
1da177e4 7148 sp->high_dma_flag = dma_flag;
1da177e4 7149 sp->device_enabled_once = FALSE;
da6971d8
AR		 7150 if (rx_ring_mode == 1)
7151 sp->rxd_mode = RXD_MODE_1;
7152 if (rx_ring_mode == 2)
7153 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7154
cc6e7c44 7155 sp->intr_type = dev_intr_type;
1da177e4 7156
541ae68f
K		 7157 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7158 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7159 sp->device_type = XFRAME_II_DEVICE;
7160 else
7161 sp->device_type = XFRAME_I_DEVICE;
7162
7d3d0439 7163 sp->lro = lro;
6aa20a22 7164
1da177e4
LT		 7165 /* Initialize some PCI/PCI-X fields of the NIC. */
7166 s2io_init_pci(sp);
7167
20346722 7168 /*
1da177e4 7169 * Setting the device configuration parameters.
20346722
K		 7170 * Most of these parameters can be specified by the user during
7171 * module insertion as they are module loadable parameters. If
7172 * these parameters are not not specified during load time, they
1da177e4
LT		 7173 * are initialized with default values.
7174 */
7175 mac_control = &sp->mac_control;
7176 config = &sp->config;
7177
7178 /* Tx side parameters. */
1da177e4
LT		 7179 config->tx_fifo_num = tx_fifo_num;
7180 for (i = 0; i < MAX_TX_FIFOS; i++) {
7181 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7182 config->tx_cfg[i].fifo_priority = i;
7183 }
7184
20346722
K		 7185 /* mapping the QoS priority to the configured fifos */
7186 for (i = 0; i < MAX_TX_FIFOS; i++)
7187 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
7188
1da177e4
LT		 7189 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7190 for (i = 0; i < config->tx_fifo_num; i++) {
7191 config->tx_cfg[i].f_no_snoop =
7192 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7193 if (config->tx_cfg[i].fifo_len < 65) {
7194 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7195 break;
7196 }
7197 }
fed5eccd
AR		 7198 /* + 2 because one Txd for skb->data and one Txd for UFO */
7199 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7200
7201 /* Rx side parameters. */
1da177e4
LT		 7202 config->rx_ring_num = rx_ring_num;
7203 for (i = 0; i < MAX_RX_RINGS; i++) {
7204 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
da6971d8 7205 (rxd_count[sp->rxd_mode] + 1);
1da177e4
LT		 7206 config->rx_cfg[i].ring_priority = i;
7207 }
7208
7209 for (i = 0; i < rx_ring_num; i++) {
7210 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7211 config->rx_cfg[i].f_no_snoop =
7212 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7213 }
7214
7215 /* Setting Mac Control parameters */
7216 mac_control->rmac_pause_time = rmac_pause_time;
7217 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7218 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7219
7220
7221 /* Initialize Ring buffer parameters. */
7222 for (i = 0; i < config->rx_ring_num; i++)
7223 atomic_set(&sp->rx_bufs_left[i], 0);
7224
7ba013ac
K		 7225 /* Initialize the number of ISRs currently running */
7226 atomic_set(&sp->isr_cnt, 0);
7227
1da177e4
LT		 7228 /* initialize the shared memory used by the NIC and the host */
7229 if (init_shared_mem(sp)) {
7230 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
b41477f3 7231 dev->name);
1da177e4
LT		 7232 ret = -ENOMEM;
7233 goto mem_alloc_failed;
7234 }
7235
7236 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7237 pci_resource_len(pdev, 0));
7238 if (!sp->bar0) {
19a60522 7239 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7240 dev->name);
7241 ret = -ENOMEM;
7242 goto bar0_remap_failed;
7243 }
7244
7245 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7246 pci_resource_len(pdev, 2));
7247 if (!sp->bar1) {
19a60522 7248 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7249 dev->name);
7250 ret = -ENOMEM;
7251 goto bar1_remap_failed;
7252 }
7253
7254 dev->irq = pdev->irq;
7255 dev->base_addr = (unsigned long) sp->bar0;
7256
7257 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7258 for (j = 0; j < MAX_TX_FIFOS; j++) {
1ee6dd77 7259 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
1da177e4
LT		 7260 (sp->bar1 + (j * 0x00020000));
7261 }
7262
7263 /* Driver entry points */
7264 dev->open = &s2io_open;
7265 dev->stop = &s2io_close;
7266 dev->hard_start_xmit = &s2io_xmit;
7267 dev->get_stats = &s2io_get_stats;
7268 dev->set_multicast_list = &s2io_set_multicast;
7269 dev->do_ioctl = &s2io_ioctl;
7270 dev->change_mtu = &s2io_change_mtu;
7271 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02
K		 7272 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7273 dev->vlan_rx_register = s2io_vlan_rx_register;
20346722 7274
1da177e4
LT		 7275 /*
7276 * will use eth_mac_addr() for dev->set_mac_address
7277 * mac address will be set every time dev->open() is called
7278 */
1da177e4 7279 dev->poll = s2io_poll;
20346722 7280 dev->weight = 32;
1da177e4 7281
612eff0e
BH		 7282#ifdef CONFIG_NET_POLL_CONTROLLER
7283 dev->poll_controller = s2io_netpoll;
7284#endif
7285
1da177e4
LT		 7286 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7287 if (sp->high_dma_flag == TRUE)
7288 dev->features |= NETIF_F_HIGHDMA;
1da177e4 7289 dev->features |= NETIF_F_TSO;
f83ef8c0 7290 dev->features |= NETIF_F_TSO6;
db874e65 7291 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 7292 dev->features |= NETIF_F_UFO;
7293 dev->features |= NETIF_F_HW_CSUM;
7294 }
1da177e4
LT		 7295
7296 dev->tx_timeout = &s2io_tx_watchdog;
7297 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 7298 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7299 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 7300
e960fc5c 7301 pci_save_state(sp->pdev);
1da177e4
LT		 7302
7303 /* Setting swapper control on the NIC, for proper reset operation */
7304 if (s2io_set_swapper(sp)) {
7305 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7306 dev->name);
7307 ret = -EAGAIN;
7308 goto set_swap_failed;
7309 }
7310
541ae68f
K		 7311 /* Verify if the Herc works on the slot its placed into */
7312 if (sp->device_type & XFRAME_II_DEVICE) {
7313 mode = s2io_verify_pci_mode(sp);
7314 if (mode < 0) {
7315 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7316 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7317 ret = -EBADSLT;
7318 goto set_swap_failed;
7319 }
7320 }
7321
7322 /* Not needed for Herc */
7323 if (sp->device_type & XFRAME_I_DEVICE) {
7324 /*
7325 * Fix for all "FFs" MAC address problems observed on
7326 * Alpha platforms
7327 */
7328 fix_mac_address(sp);
7329 s2io_reset(sp);
7330 }
1da177e4
LT		 7331
7332 /*
1da177e4
LT		 7333 * MAC address initialization.
7334 * For now only one mac address will be read and used.
7335 */
7336 bar0 = sp->bar0;
7337 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7338 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7339 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 7340 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41 7341 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
1da177e4
LT		 7342 tmp64 = readq(&bar0->rmac_addr_data0_mem);
7343 mac_down = (u32) tmp64;
7344 mac_up = (u32) (tmp64 >> 32);
7345
1da177e4
LT		 7346 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7347 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7348 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7349 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7350 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7351 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7352
1da177e4
LT		 7353 /* Set the factory defined MAC address initially */
7354 dev->addr_len = ETH_ALEN;
7355 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7356
b41477f3
AR		 7357 /* reset Nic and bring it to known state */
7358 s2io_reset(sp);
7359
1da177e4 7360 /*
20346722 7361 * Initialize the tasklet status and link state flags
541ae68f 7362 * and the card state parameter
1da177e4
LT		 7363 */
7364 atomic_set(&(sp->card_state), 0);
7365 sp->tasklet_status = 0;
7366 sp->link_state = 0;
7367
1da177e4
LT		 7368 /* Initialize spinlocks */
7369 spin_lock_init(&sp->tx_lock);
db874e65
SS		 7370
7371 if (!napi)
7372 spin_lock_init(&sp->put_lock);
7ba013ac 7373 spin_lock_init(&sp->rx_lock);
1da177e4 7374
20346722
K		 7375 /*
7376 * SXE-002: Configure link and activity LED to init state
7377 * on driver load.
1da177e4
LT		 7378 */
7379 subid = sp->pdev->subsystem_device;
7380 if ((subid & 0xFF) >= 0x07) {
7381 val64 = readq(&bar0->gpio_control);
7382 val64 |= 0x0000800000000000ULL;
7383 writeq(val64, &bar0->gpio_control);
7384 val64 = 0x0411040400000000ULL;
7385 writeq(val64, (void __iomem *) bar0 + 0x2700);
7386 val64 = readq(&bar0->gpio_control);
7387 }
7388
7389 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
7390
7391 if (register_netdev(dev)) {
7392 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7393 ret = -ENODEV;
7394 goto register_failed;
7395 }
9dc737a7 7396 s2io_vpd_read(sp);
0c61ed5f 7397 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
b41477f3 7398 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
44c10138 7399 sp->product_name, pdev->revision);
b41477f3
AR		 7400 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7401 s2io_driver_version);
9dc737a7 7402 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
19a60522 7403 "%02x:%02x:%02x:%02x:%02x:%02x", dev->name,
541ae68f
K		 7404 sp->def_mac_addr[0].mac_addr[0],
7405 sp->def_mac_addr[0].mac_addr[1],
7406 sp->def_mac_addr[0].mac_addr[2],
7407 sp->def_mac_addr[0].mac_addr[3],
7408 sp->def_mac_addr[0].mac_addr[4],
7409 sp->def_mac_addr[0].mac_addr[5]);
19a60522 7410 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
9dc737a7 7411 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 7412 mode = s2io_print_pci_mode(sp);
541ae68f 7413 if (mode < 0) {
9dc737a7 7414 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 7415 ret = -EBADSLT;
9dc737a7 7416 unregister_netdev(dev);
541ae68f
K		 7417 goto set_swap_failed;
7418 }
541ae68f 7419 }
9dc737a7
AR		 7420 switch(sp->rxd_mode) {
7421 case RXD_MODE_1:
7422 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7423 dev->name);
7424 break;
7425 case RXD_MODE_3B:
7426 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7427 dev->name);
7428 break;
9dc737a7 7429 }
db874e65
SS		 7430
7431 if (napi)
7432 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
9dc737a7
AR		 7433 switch(sp->intr_type) {
7434 case INTA:
7435 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7436 break;
7437 case MSI:
7438 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI\n", dev->name);
7439 break;
7440 case MSI_X:
7441 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7442 break;
7443 }
7d3d0439
RA		 7444 if (sp->lro)
7445 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 7446 dev->name);
db874e65
SS		 7447 if (ufo)
7448 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
7449 " enabled\n", dev->name);
7ba013ac 7450 /* Initialize device name */
9dc737a7 7451 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 7452
b6e3f982
K		 7453 /* Initialize bimodal Interrupts */
7454 sp->config.bimodal = bimodal;
7455 if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
7456 sp->config.bimodal = 0;
7457 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
7458 dev->name);
7459 }
7460
20346722
K		 7461 /*
7462 * Make Link state as off at this point, when the Link change
7463 * interrupt comes the state will be automatically changed to
1da177e4
LT		 7464 * the right state.
7465 */
7466 netif_carrier_off(dev);
1da177e4
LT		 7467
7468 return 0;
7469
7470 register_failed:
7471 set_swap_failed:
7472 iounmap(sp->bar1);
7473 bar1_remap_failed:
7474 iounmap(sp->bar0);
7475 bar0_remap_failed:
7476 mem_alloc_failed:
7477 free_shared_mem(sp);
7478 pci_disable_device(pdev);
cc6e7c44
RA		 7479 if (dev_intr_type != MSI_X)
7480 pci_release_regions(pdev);
7481 else {
7482 release_mem_region(pci_resource_start(pdev, 0),
7483 pci_resource_len(pdev, 0));
7484 release_mem_region(pci_resource_start(pdev, 2),
7485 pci_resource_len(pdev, 2));
7486 }
1da177e4
LT		 7487 pci_set_drvdata(pdev, NULL);
7488 free_netdev(dev);
7489
7490 return ret;
7491}
7492
7493/**
20346722 7494 * s2io_rem_nic - Free the PCI device
1da177e4 7495 * @pdev: structure containing the PCI related information of the device.
20346722 7496 * Description: This function is called by the Pci subsystem to release a
1da177e4 7497 * PCI device and free up all resource held up by the device. This could
20346722 7498 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 7499 * from memory.
7500 */
7501
7502static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7503{
7504 struct net_device *dev =
7505 (struct net_device *) pci_get_drvdata(pdev);
1ee6dd77 7506 struct s2io_nic *sp;
1da177e4
LT		 7507
7508 if (dev == NULL) {
7509 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7510 return;
7511 }
7512
22747d6b
FR		 7513 flush_scheduled_work();
7514
1da177e4
LT		 7515 sp = dev->priv;
7516 unregister_netdev(dev);
7517
7518 free_shared_mem(sp);
7519 iounmap(sp->bar0);
7520 iounmap(sp->bar1);
cc6e7c44
RA		 7521 if (sp->intr_type != MSI_X)
7522 pci_release_regions(pdev);
7523 else {
7524 release_mem_region(pci_resource_start(pdev, 0),
7525 pci_resource_len(pdev, 0));
7526 release_mem_region(pci_resource_start(pdev, 2),
7527 pci_resource_len(pdev, 2));
7528 }
1da177e4 7529 pci_set_drvdata(pdev, NULL);
1da177e4 7530 free_netdev(dev);
19a60522 7531 pci_disable_device(pdev);
1da177e4
LT		 7532}
7533
7534/**
7535 * s2io_starter - Entry point for the driver
7536 * Description: This function is the entry point for the driver. It verifies
7537 * the module loadable parameters and initializes PCI configuration space.
7538 */
7539
7540int __init s2io_starter(void)
7541{
29917620 7542 return pci_register_driver(&s2io_driver);
1da177e4
LT		 7543}
7544
7545/**
20346722 7546 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 7547 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7548 */
7549
372cc597 7550static __exit void s2io_closer(void)
1da177e4
LT		 7551{
7552 pci_unregister_driver(&s2io_driver);
7553 DBG_PRINT(INIT_DBG, "cleanup done\n");
7554}
7555
7556module_init(s2io_starter);
7557module_exit(s2io_closer);
7d3d0439 7558
6aa20a22 7559static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
1ee6dd77 7560 struct tcphdr **tcp, struct RxD_t *rxdp)
7d3d0439
RA		 7561{
7562 int ip_off;
7563 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7564
7565 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7566 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7567 __FUNCTION__);
7568 return -1;
7569 }
7570
7571 /* TODO:
7572 * By default the VLAN field in the MAC is stripped by the card, if this
7573 * feature is turned off in rx_pa_cfg register, then the ip_off field
7574 * has to be shifted by a further 2 bytes
7575 */
7576 switch (l2_type) {
7577 case 0: /* DIX type */
7578 case 4: /* DIX type with VLAN */
7579 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7580 break;
7581 /* LLC, SNAP etc are considered non-mergeable */
7582 default:
7583 return -1;
7584 }
7585
7586 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7587 ip_len = (u8)((*ip)->ihl);
7588 ip_len <<= 2;
7589 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7590
7591 return 0;
7592}
7593
1ee6dd77 7594static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 7595 struct tcphdr *tcp)
7596{
7597 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7598 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7599 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7600 return -1;
7601 return 0;
7602}
7603
7604static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7605{
7606 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7607}
7608
1ee6dd77 7609static void initiate_new_session(struct lro *lro, u8 *l2h,
7d3d0439
RA		 7610 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7611{
7612 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7613 lro->l2h = l2h;
7614 lro->iph = ip;
7615 lro->tcph = tcp;
7616 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7617 lro->tcp_ack = ntohl(tcp->ack_seq);
7618 lro->sg_num = 1;
7619 lro->total_len = ntohs(ip->tot_len);
7620 lro->frags_len = 0;
6aa20a22 7621 /*
7d3d0439
RA		 7622 * check if we saw TCP timestamp. Other consistency checks have
7623 * already been done.
7624 */
7625 if (tcp->doff == 8) {
7626 u32 *ptr;
7627 ptr = (u32 *)(tcp+1);
7628 lro->saw_ts = 1;
7629 lro->cur_tsval = *(ptr+1);
7630 lro->cur_tsecr = *(ptr+2);
7631 }
7632 lro->in_use = 1;
7633}
7634
1ee6dd77 7635static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 7636{
7637 struct iphdr *ip = lro->iph;
7638 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 7639 __sum16 nchk;
1ee6dd77 7640 struct stat_block *statinfo = sp->mac_control.stats_info;
7d3d0439
RA		 7641 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7642
7643 /* Update L3 header */
7644 ip->tot_len = htons(lro->total_len);
7645 ip->check = 0;
7646 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7647 ip->check = nchk;
7648
7649 /* Update L4 header */
7650 tcp->ack_seq = lro->tcp_ack;
7651 tcp->window = lro->window;
7652
7653 /* Update tsecr field if this session has timestamps enabled */
7654 if (lro->saw_ts) {
7655 u32 *ptr = (u32 *)(tcp + 1);
7656 *(ptr+2) = lro->cur_tsecr;
7657 }
7658
7659 /* Update counters required for calculation of
7660 * average no. of packets aggregated.
7661 */
7662 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
7663 statinfo->sw_stat.num_aggregations++;
7664}
7665
1ee6dd77 7666static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 7667 struct tcphdr *tcp, u32 l4_pyld)
7668{
7669 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7670 lro->total_len += l4_pyld;
7671 lro->frags_len += l4_pyld;
7672 lro->tcp_next_seq += l4_pyld;
7673 lro->sg_num++;
7674
7675 /* Update ack seq no. and window ad(from this pkt) in LRO object */
7676 lro->tcp_ack = tcp->ack_seq;
7677 lro->window = tcp->window;
6aa20a22 7678
7d3d0439
RA		 7679 if (lro->saw_ts) {
7680 u32 *ptr;
7681 /* Update tsecr and tsval from this packet */
7682 ptr = (u32 *) (tcp + 1);
6aa20a22 7683 lro->cur_tsval = *(ptr + 1);
7d3d0439
RA		 7684 lro->cur_tsecr = *(ptr + 2);
7685 }
7686}
7687
1ee6dd77 7688static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 7689 struct tcphdr *tcp, u32 tcp_pyld_len)
7690{
7d3d0439
RA		 7691 u8 *ptr;
7692
79dc1901
AM		 7693 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7694
7d3d0439
RA		 7695 if (!tcp_pyld_len) {
7696 /* Runt frame or a pure ack */
7697 return -1;
7698 }
7699
7700 if (ip->ihl != 5) /* IP has options */
7701 return -1;
7702
75c30b13
AR		 7703 /* If we see CE codepoint in IP header, packet is not mergeable */
7704 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
7705 return -1;
7706
7707 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7d3d0439 7708 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
75c30b13 7709 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 7710 /*
7711 * Currently recognize only the ack control word and
7712 * any other control field being set would result in
7713 * flushing the LRO session
7714 */
7715 return -1;
7716 }
7717
6aa20a22 7718 /*
7d3d0439
RA		 7719 * Allow only one TCP timestamp option. Don't aggregate if
7720 * any other options are detected.
7721 */
7722 if (tcp->doff != 5 && tcp->doff != 8)
7723 return -1;
7724
7725 if (tcp->doff == 8) {
6aa20a22 7726 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 7727 while (*ptr == TCPOPT_NOP)
7728 ptr++;
7729 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
7730 return -1;
7731
7732 /* Ensure timestamp value increases monotonically */
7733 if (l_lro)
7734 if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
7735 return -1;
7736
7737 /* timestamp echo reply should be non-zero */
6aa20a22 7738 if (*((u32 *)(ptr+6)) == 0)
7d3d0439
RA		 7739 return -1;
7740 }
7741
7742 return 0;
7743}
7744
7745static int
1ee6dd77
RB		 7746s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
7747 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 7748{
7749 struct iphdr *ip;
7750 struct tcphdr *tcph;
7751 int ret = 0, i;
7752
7753 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
7754 rxdp))) {
7755 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
7756 ip->saddr, ip->daddr);
7757 } else {
7758 return ret;
7759 }
7760
7761 tcph = (struct tcphdr *)*tcp;
7762 *tcp_len = get_l4_pyld_length(ip, tcph);
7763 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 7764 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 7765 if (l_lro->in_use) {
7766 if (check_for_socket_match(l_lro, ip, tcph))
7767 continue;
7768 /* Sock pair matched */
7769 *lro = l_lro;
7770
7771 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
7772 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
7773 "0x%x, actual 0x%x\n", __FUNCTION__,
7774 (*lro)->tcp_next_seq,
7775 ntohl(tcph->seq));
7776
7777 sp->mac_control.stats_info->
7778 sw_stat.outof_sequence_pkts++;
7779 ret = 2;
7780 break;
7781 }
7782
7783 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
7784 ret = 1; /* Aggregate */
7785 else
7786 ret = 2; /* Flush both */
7787 break;
7788 }
7789 }
7790
7791 if (ret == 0) {
7792 /* Before searching for available LRO objects,
7793 * check if the pkt is L3/L4 aggregatable. If not
7794 * don't create new LRO session. Just send this
7795 * packet up.
7796 */
7797 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
7798 return 5;
7799 }
7800
7801 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 7802 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 7803 if (!(l_lro->in_use)) {
7804 *lro = l_lro;
7805 ret = 3; /* Begin anew */
7806 break;
7807 }
7808 }
7809 }
7810
7811 if (ret == 0) { /* sessions exceeded */
7812 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
7813 __FUNCTION__);
7814 *lro = NULL;
7815 return ret;
7816 }
7817
7818 switch (ret) {
7819 case 3:
7820 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
7821 break;
7822 case 2:
7823 update_L3L4_header(sp, *lro);
7824 break;
7825 case 1:
7826 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
7827 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7828 update_L3L4_header(sp, *lro);
7829 ret = 4; /* Flush the LRO */
7830 }
7831 break;
7832 default:
7833 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
7834 __FUNCTION__);
7835 break;
7836 }
7837
7838 return ret;
7839}
7840
1ee6dd77 7841static void clear_lro_session(struct lro *lro)
7d3d0439 7842{
1ee6dd77 7843 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 7844
7845 memset(lro, 0, lro_struct_size);
7846}
7847
7848static void queue_rx_frame(struct sk_buff *skb)
7849{
7850 struct net_device *dev = skb->dev;
7851
7852 skb->protocol = eth_type_trans(skb, dev);
db874e65
SS		 7853 if (napi)
7854 netif_receive_skb(skb);
7855 else
7856 netif_rx(skb);
7d3d0439
RA		 7857}
7858
1ee6dd77
RB		 7859static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
7860 struct sk_buff *skb,
7d3d0439
RA		 7861 u32 tcp_len)
7862{
75c30b13 7863 struct sk_buff *first = lro->parent;
7d3d0439
RA		 7864
7865 first->len += tcp_len;
7866 first->data_len = lro->frags_len;
7867 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 7868 if (skb_shinfo(first)->frag_list)
7869 lro->last_frag->next = skb;
7d3d0439
RA		 7870 else
7871 skb_shinfo(first)->frag_list = skb;
372cc597 7872 first->truesize += skb->truesize;
75c30b13 7873 lro->last_frag = skb;
7d3d0439
RA		 7874 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
7875 return;
7876}
d796fdb7
LV		 7877
7878/**
7879 * s2io_io_error_detected - called when PCI error is detected
7880 * @pdev: Pointer to PCI device
8453d43f 7881 * @state: The current pci connection state
d796fdb7
LV		 7882 *
7883 * This function is called after a PCI bus error affecting
7884 * this device has been detected.
7885 */
7886static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
7887 pci_channel_state_t state)
7888{
7889 struct net_device *netdev = pci_get_drvdata(pdev);
7890 struct s2io_nic *sp = netdev->priv;
7891
7892 netif_device_detach(netdev);
7893
7894 if (netif_running(netdev)) {
7895 /* Bring down the card, while avoiding PCI I/O */
7896 do_s2io_card_down(sp, 0);
d796fdb7
LV		 7897 }
7898 pci_disable_device(pdev);
7899
7900 return PCI_ERS_RESULT_NEED_RESET;
7901}
7902
7903/**
7904 * s2io_io_slot_reset - called after the pci bus has been reset.
7905 * @pdev: Pointer to PCI device
7906 *
7907 * Restart the card from scratch, as if from a cold-boot.
7908 * At this point, the card has exprienced a hard reset,
7909 * followed by fixups by BIOS, and has its config space
7910 * set up identically to what it was at cold boot.
7911 */
7912static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
7913{
7914 struct net_device *netdev = pci_get_drvdata(pdev);
7915 struct s2io_nic *sp = netdev->priv;
7916
7917 if (pci_enable_device(pdev)) {
7918 printk(KERN_ERR "s2io: "
7919 "Cannot re-enable PCI device after reset.\n");
7920 return PCI_ERS_RESULT_DISCONNECT;
7921 }
7922
7923 pci_set_master(pdev);
7924 s2io_reset(sp);
7925
7926 return PCI_ERS_RESULT_RECOVERED;
7927}
7928
7929/**
7930 * s2io_io_resume - called when traffic can start flowing again.
7931 * @pdev: Pointer to PCI device
7932 *
7933 * This callback is called when the error recovery driver tells
7934 * us that its OK to resume normal operation.
7935 */
7936static void s2io_io_resume(struct pci_dev *pdev)
7937{
7938 struct net_device *netdev = pci_get_drvdata(pdev);
7939 struct s2io_nic *sp = netdev->priv;
7940
7941 if (netif_running(netdev)) {
7942 if (s2io_card_up(sp)) {
7943 printk(KERN_ERR "s2io: "
7944 "Can't bring device back up after reset.\n");
7945 return;
7946 }
7947
7948 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
7949 s2io_card_down(sp);
7950 printk(KERN_ERR "s2io: "
7951 "Can't resetore mac addr after reset.\n");
7952 return;
7953 }
7954 }
7955
7956 netif_device_attach(netdev);
7957 netif_wake_queue(netdev);
7958}
Clone of davem's net-next-2.6 tree