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netxen: drop redudant spinlock
[net-next-2.6.git] / drivers / net / s2io.c
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1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
1da177e4
LT		 4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722
K		 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4
LT		 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
9dc737a7 29 *
20346722
K		 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8
AR		 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2 and 3.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7
AR		 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 1(MSI), 2(MSI_X). Default value is '0(INTA)'
41 * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
1da177e4
LT		 53 ************************************************************************/
54
1da177e4
LT		 55#include <linux/module.h>
56#include <linux/types.h>
57#include <linux/errno.h>
58#include <linux/ioport.h>
59#include <linux/pci.h>
1e7f0bd8 60#include <linux/dma-mapping.h>
1da177e4
LT		 61#include <linux/kernel.h>
62#include <linux/netdevice.h>
63#include <linux/etherdevice.h>
64#include <linux/skbuff.h>
65#include <linux/init.h>
66#include <linux/delay.h>
67#include <linux/stddef.h>
68#include <linux/ioctl.h>
69#include <linux/timex.h>
1da177e4 70#include <linux/ethtool.h>
1da177e4 71#include <linux/workqueue.h>
be3a6b02 72#include <linux/if_vlan.h>
7d3d0439
RA		 73#include <linux/ip.h>
74#include <linux/tcp.h>
75#include <net/tcp.h>
1da177e4 76
1da177e4
LT		 77#include <asm/system.h>
78#include <asm/uaccess.h>
20346722 79#include <asm/io.h>
fe931395 80#include <asm/div64.h>
330ce0de 81#include <asm/irq.h>
1da177e4
LT		 82
83/* local include */
84#include "s2io.h"
85#include "s2io-regs.h"
86
491976b2 87#define DRV_VERSION "2.0.23.1"
6c1792f4 88
1da177e4 89/* S2io Driver name & version. */
20346722 90static char s2io_driver_name[] = "Neterion";
6c1792f4 91static char s2io_driver_version[] = DRV_VERSION;
1da177e4 92
26df54bf
AB		 93static int rxd_size[4] = {32,48,48,64};
94static int rxd_count[4] = {127,85,85,63};
da6971d8 95
1ee6dd77 96static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd
K		 97{
98 int ret;
99
100 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
101 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
102
103 return ret;
104}
105
20346722 106/*
1da177e4
LT		 107 * Cards with following subsystem_id have a link state indication
108 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
109 * macro below identifies these cards given the subsystem_id.
110 */
541ae68f
K		 111#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
112 (dev_type == XFRAME_I_DEVICE) ? \
113 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
114 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 115
116#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
117 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
118#define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
119#define PANIC 1
120#define LOW 2
1ee6dd77 121static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
1da177e4 122{
1ee6dd77 123 struct mac_info *mac_control;
20346722
K		 124
125 mac_control = &sp->mac_control;
863c11a9
AR		 126 if (rxb_size <= rxd_count[sp->rxd_mode])
127 return PANIC;
128 else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
129 return LOW;
130 return 0;
1da177e4
LT		 131}
132
133/* Ethtool related variables and Macros. */
134static char s2io_gstrings[][ETH_GSTRING_LEN] = {
135 "Register test\t(offline)",
136 "Eeprom test\t(offline)",
137 "Link test\t(online)",
138 "RLDRAM test\t(offline)",
139 "BIST Test\t(offline)"
140};
141
fa1f0cb3 142static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 143 {"tmac_frms"},
144 {"tmac_data_octets"},
145 {"tmac_drop_frms"},
146 {"tmac_mcst_frms"},
147 {"tmac_bcst_frms"},
148 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 149 {"tmac_ttl_octets"},
150 {"tmac_ucst_frms"},
151 {"tmac_nucst_frms"},
1da177e4 152 {"tmac_any_err_frms"},
bd1034f0 153 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 154 {"tmac_vld_ip_octets"},
155 {"tmac_vld_ip"},
156 {"tmac_drop_ip"},
157 {"tmac_icmp"},
158 {"tmac_rst_tcp"},
159 {"tmac_tcp"},
160 {"tmac_udp"},
161 {"rmac_vld_frms"},
162 {"rmac_data_octets"},
163 {"rmac_fcs_err_frms"},
164 {"rmac_drop_frms"},
165 {"rmac_vld_mcst_frms"},
166 {"rmac_vld_bcst_frms"},
167 {"rmac_in_rng_len_err_frms"},
bd1034f0 168 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 169 {"rmac_long_frms"},
170 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 171 {"rmac_unsup_ctrl_frms"},
172 {"rmac_ttl_octets"},
173 {"rmac_accepted_ucst_frms"},
174 {"rmac_accepted_nucst_frms"},
1da177e4 175 {"rmac_discarded_frms"},
bd1034f0
AR		 176 {"rmac_drop_events"},
177 {"rmac_ttl_less_fb_octets"},
178 {"rmac_ttl_frms"},
1da177e4
LT		 179 {"rmac_usized_frms"},
180 {"rmac_osized_frms"},
181 {"rmac_frag_frms"},
182 {"rmac_jabber_frms"},
bd1034f0
AR		 183 {"rmac_ttl_64_frms"},
184 {"rmac_ttl_65_127_frms"},
185 {"rmac_ttl_128_255_frms"},
186 {"rmac_ttl_256_511_frms"},
187 {"rmac_ttl_512_1023_frms"},
188 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 189 {"rmac_ip"},
190 {"rmac_ip_octets"},
191 {"rmac_hdr_err_ip"},
192 {"rmac_drop_ip"},
193 {"rmac_icmp"},
194 {"rmac_tcp"},
195 {"rmac_udp"},
196 {"rmac_err_drp_udp"},
bd1034f0
AR		 197 {"rmac_xgmii_err_sym"},
198 {"rmac_frms_q0"},
199 {"rmac_frms_q1"},
200 {"rmac_frms_q2"},
201 {"rmac_frms_q3"},
202 {"rmac_frms_q4"},
203 {"rmac_frms_q5"},
204 {"rmac_frms_q6"},
205 {"rmac_frms_q7"},
206 {"rmac_full_q0"},
207 {"rmac_full_q1"},
208 {"rmac_full_q2"},
209 {"rmac_full_q3"},
210 {"rmac_full_q4"},
211 {"rmac_full_q5"},
212 {"rmac_full_q6"},
213 {"rmac_full_q7"},
1da177e4 214 {"rmac_pause_cnt"},
bd1034f0
AR		 215 {"rmac_xgmii_data_err_cnt"},
216 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 217 {"rmac_accepted_ip"},
218 {"rmac_err_tcp"},
bd1034f0
AR		 219 {"rd_req_cnt"},
220 {"new_rd_req_cnt"},
221 {"new_rd_req_rtry_cnt"},
222 {"rd_rtry_cnt"},
223 {"wr_rtry_rd_ack_cnt"},
224 {"wr_req_cnt"},
225 {"new_wr_req_cnt"},
226 {"new_wr_req_rtry_cnt"},
227 {"wr_rtry_cnt"},
228 {"wr_disc_cnt"},
229 {"rd_rtry_wr_ack_cnt"},
230 {"txp_wr_cnt"},
231 {"txd_rd_cnt"},
232 {"txd_wr_cnt"},
233 {"rxd_rd_cnt"},
234 {"rxd_wr_cnt"},
235 {"txf_rd_cnt"},
fa1f0cb3
SS		 236 {"rxf_wr_cnt"}
237};
238
239static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 240 {"rmac_ttl_1519_4095_frms"},
241 {"rmac_ttl_4096_8191_frms"},
242 {"rmac_ttl_8192_max_frms"},
243 {"rmac_ttl_gt_max_frms"},
244 {"rmac_osized_alt_frms"},
245 {"rmac_jabber_alt_frms"},
246 {"rmac_gt_max_alt_frms"},
247 {"rmac_vlan_frms"},
248 {"rmac_len_discard"},
249 {"rmac_fcs_discard"},
250 {"rmac_pf_discard"},
251 {"rmac_da_discard"},
252 {"rmac_red_discard"},
253 {"rmac_rts_discard"},
254 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 255 {"link_fault_cnt"}
256};
257
258static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac
K		 259 {"\n DRIVER STATISTICS"},
260 {"single_bit_ecc_errs"},
261 {"double_bit_ecc_errs"},
bd1034f0
AR		 262 {"parity_err_cnt"},
263 {"serious_err_cnt"},
264 {"soft_reset_cnt"},
265 {"fifo_full_cnt"},
266 {"ring_full_cnt"},
267 ("alarm_transceiver_temp_high"),
268 ("alarm_transceiver_temp_low"),
269 ("alarm_laser_bias_current_high"),
270 ("alarm_laser_bias_current_low"),
271 ("alarm_laser_output_power_high"),
272 ("alarm_laser_output_power_low"),
273 ("warn_transceiver_temp_high"),
274 ("warn_transceiver_temp_low"),
275 ("warn_laser_bias_current_high"),
276 ("warn_laser_bias_current_low"),
277 ("warn_laser_output_power_high"),
278 ("warn_laser_output_power_low"),
7d3d0439
RA		 279 ("lro_aggregated_pkts"),
280 ("lro_flush_both_count"),
281 ("lro_out_of_sequence_pkts"),
282 ("lro_flush_due_to_max_pkts"),
283 ("lro_avg_aggr_pkts"),
c53d4945 284 ("mem_alloc_fail_cnt"),
491976b2
SH		 285 ("watchdog_timer_cnt"),
286 ("mem_allocated"),
287 ("mem_freed"),
288 ("link_up_cnt"),
289 ("link_down_cnt"),
290 ("link_up_time"),
291 ("link_down_time"),
292 ("tx_tcode_buf_abort_cnt"),
293 ("tx_tcode_desc_abort_cnt"),
294 ("tx_tcode_parity_err_cnt"),
295 ("tx_tcode_link_loss_cnt"),
296 ("tx_tcode_list_proc_err_cnt"),
297 ("rx_tcode_parity_err_cnt"),
298 ("rx_tcode_abort_cnt"),
299 ("rx_tcode_parity_abort_cnt"),
300 ("rx_tcode_rda_fail_cnt"),
301 ("rx_tcode_unkn_prot_cnt"),
302 ("rx_tcode_fcs_err_cnt"),
303 ("rx_tcode_buf_size_err_cnt"),
304 ("rx_tcode_rxd_corrupt_cnt"),
305 ("rx_tcode_unkn_err_cnt")
1da177e4
LT		 306};
307
fa1f0cb3
SS		 308#define S2IO_XENA_STAT_LEN sizeof(ethtool_xena_stats_keys)/ ETH_GSTRING_LEN
309#define S2IO_ENHANCED_STAT_LEN sizeof(ethtool_enhanced_stats_keys)/ \
310 ETH_GSTRING_LEN
311#define S2IO_DRIVER_STAT_LEN sizeof(ethtool_driver_stats_keys)/ ETH_GSTRING_LEN
312
313#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
314#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
315
316#define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
317#define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
1da177e4
LT		 318
319#define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
320#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
321
25fff88e
K		 322#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
323 init_timer(&timer); \
324 timer.function = handle; \
325 timer.data = (unsigned long) arg; \
326 mod_timer(&timer, (jiffies + exp)) \
327
be3a6b02
K		 328/* Add the vlan */
329static void s2io_vlan_rx_register(struct net_device *dev,
330 struct vlan_group *grp)
331{
1ee6dd77 332 struct s2io_nic *nic = dev->priv;
be3a6b02
K		 333 unsigned long flags;
334
335 spin_lock_irqsave(&nic->tx_lock, flags);
336 nic->vlgrp = grp;
337 spin_unlock_irqrestore(&nic->tx_lock, flags);
338}
339
926930b2 340/* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
7b490343 341static int vlan_strip_flag;
926930b2 342
20346722 343/*
1da177e4
LT		 344 * Constants to be programmed into the Xena's registers, to configure
345 * the XAUI.
346 */
347
1da177e4 348#define END_SIGN 0x0
f71e1309 349static const u64 herc_act_dtx_cfg[] = {
541ae68f 350 /* Set address */
e960fc5c 351 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 352 /* Write data */
e960fc5c 353 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f
K		 354 /* Set address */
355 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
356 /* Write data */
357 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
358 /* Set address */
e960fc5c 359 0x801205150D440000ULL, 0x801205150D4400E0ULL,
360 /* Write data */
361 0x801205150D440004ULL, 0x801205150D4400E4ULL,
362 /* Set address */
541ae68f
K		 363 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
364 /* Write data */
365 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
366 /* Done */
367 END_SIGN
368};
369
f71e1309 370static const u64 xena_dtx_cfg[] = {
c92ca04b 371 /* Set address */
1da177e4 372 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 373 /* Write data */
374 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
375 /* Set address */
376 0x8001051500000000ULL, 0x80010515000000E0ULL,
377 /* Write data */
378 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
379 /* Set address */
1da177e4 380 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 381 /* Write data */
382 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 383 END_SIGN
384};
385
20346722 386/*
1da177e4
LT		 387 * Constants for Fixing the MacAddress problem seen mostly on
388 * Alpha machines.
389 */
f71e1309 390static const u64 fix_mac[] = {
1da177e4
LT		 391 0x0060000000000000ULL, 0x0060600000000000ULL,
392 0x0040600000000000ULL, 0x0000600000000000ULL,
393 0x0020600000000000ULL, 0x0060600000000000ULL,
394 0x0020600000000000ULL, 0x0060600000000000ULL,
395 0x0020600000000000ULL, 0x0060600000000000ULL,
396 0x0020600000000000ULL, 0x0060600000000000ULL,
397 0x0020600000000000ULL, 0x0060600000000000ULL,
398 0x0020600000000000ULL, 0x0060600000000000ULL,
399 0x0020600000000000ULL, 0x0060600000000000ULL,
400 0x0020600000000000ULL, 0x0060600000000000ULL,
401 0x0020600000000000ULL, 0x0060600000000000ULL,
402 0x0020600000000000ULL, 0x0060600000000000ULL,
403 0x0020600000000000ULL, 0x0000600000000000ULL,
404 0x0040600000000000ULL, 0x0060600000000000ULL,
405 END_SIGN
406};
407
b41477f3
AR		 408MODULE_LICENSE("GPL");
409MODULE_VERSION(DRV_VERSION);
410
411
1da177e4 412/* Module Loadable parameters. */
b41477f3
AR		 413S2IO_PARM_INT(tx_fifo_num, 1);
414S2IO_PARM_INT(rx_ring_num, 1);
415
416
417S2IO_PARM_INT(rx_ring_mode, 1);
418S2IO_PARM_INT(use_continuous_tx_intrs, 1);
419S2IO_PARM_INT(rmac_pause_time, 0x100);
420S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
421S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
422S2IO_PARM_INT(shared_splits, 0);
423S2IO_PARM_INT(tmac_util_period, 5);
424S2IO_PARM_INT(rmac_util_period, 5);
425S2IO_PARM_INT(bimodal, 0);
426S2IO_PARM_INT(l3l4hdr_size, 128);
303bcb4b 427/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 428S2IO_PARM_INT(rxsync_frequency, 3);
cc6e7c44 429/* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
b41477f3 430S2IO_PARM_INT(intr_type, 0);
7d3d0439 431/* Large receive offload feature */
b41477f3 432S2IO_PARM_INT(lro, 0);
7d3d0439
RA		 433/* Max pkts to be aggregated by LRO at one time. If not specified,
434 * aggregation happens until we hit max IP pkt size(64K)
435 */
b41477f3 436S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 437S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 438
439S2IO_PARM_INT(napi, 1);
440S2IO_PARM_INT(ufo, 0);
926930b2 441S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 442
443static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
444 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
445static unsigned int rx_ring_sz[MAX_RX_RINGS] =
446 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
447static unsigned int rts_frm_len[MAX_RX_RINGS] =
448 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
449
450module_param_array(tx_fifo_len, uint, NULL, 0);
451module_param_array(rx_ring_sz, uint, NULL, 0);
452module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 453
20346722 454/*
1da177e4 455 * S2IO device table.
20346722 456 * This table lists all the devices that this driver supports.
1da177e4
LT		 457 */
458static struct pci_device_id s2io_tbl[] __devinitdata = {
459 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
460 PCI_ANY_ID, PCI_ANY_ID},
461 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
462 PCI_ANY_ID, PCI_ANY_ID},
463 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
20346722
K		 464 PCI_ANY_ID, PCI_ANY_ID},
465 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
466 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 467 {0,}
468};
469
470MODULE_DEVICE_TABLE(pci, s2io_tbl);
471
d796fdb7
LV		 472static struct pci_error_handlers s2io_err_handler = {
473 .error_detected = s2io_io_error_detected,
474 .slot_reset = s2io_io_slot_reset,
475 .resume = s2io_io_resume,
476};
477
1da177e4
LT		 478static struct pci_driver s2io_driver = {
479 .name = "S2IO",
480 .id_table = s2io_tbl,
481 .probe = s2io_init_nic,
482 .remove = __devexit_p(s2io_rem_nic),
d796fdb7 483 .err_handler = &s2io_err_handler,
1da177e4
LT		 484};
485
486/* A simplifier macro used both by init and free shared_mem Fns(). */
487#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
488
489/**
490 * init_shared_mem - Allocation and Initialization of Memory
491 * @nic: Device private variable.
20346722
K		 492 * Description: The function allocates all the memory areas shared
493 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 494 * Rx descriptors and the statistics block.
495 */
496
497static int init_shared_mem(struct s2io_nic *nic)
498{
499 u32 size;
500 void *tmp_v_addr, *tmp_v_addr_next;
501 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 502 struct RxD_block *pre_rxd_blk = NULL;
372cc597 503 int i, j, blk_cnt;
1da177e4
LT		 504 int lst_size, lst_per_page;
505 struct net_device *dev = nic->dev;
8ae418cf 506 unsigned long tmp;
1ee6dd77 507 struct buffAdd *ba;
1da177e4 508
1ee6dd77 509 struct mac_info *mac_control;
1da177e4 510 struct config_param *config;
491976b2 511 unsigned long long mem_allocated = 0;
1da177e4
LT		 512
513 mac_control = &nic->mac_control;
514 config = &nic->config;
515
516
517 /* Allocation and initialization of TXDLs in FIOFs */
518 size = 0;
519 for (i = 0; i < config->tx_fifo_num; i++) {
520 size += config->tx_cfg[i].fifo_len;
521 }
522 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 523 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
0b1f7ebe 524 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
b41477f3 525 return -EINVAL;
1da177e4
LT		 526 }
527
1ee6dd77 528 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 529 lst_per_page = PAGE_SIZE / lst_size;
530
531 for (i = 0; i < config->tx_fifo_num; i++) {
532 int fifo_len = config->tx_cfg[i].fifo_len;
1ee6dd77 533 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
20346722
K		 534 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
535 GFP_KERNEL);
536 if (!mac_control->fifos[i].list_info) {
0c61ed5f 537 DBG_PRINT(INFO_DBG,
1da177e4
LT		 538 "Malloc failed for list_info\n");
539 return -ENOMEM;
540 }
491976b2 541 mem_allocated += list_holder_size;
20346722 542 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
1da177e4
LT		 543 }
544 for (i = 0; i < config->tx_fifo_num; i++) {
545 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
546 lst_per_page);
20346722
K		 547 mac_control->fifos[i].tx_curr_put_info.offset = 0;
548 mac_control->fifos[i].tx_curr_put_info.fifo_len =
1da177e4 549 config->tx_cfg[i].fifo_len - 1;
20346722
K		 550 mac_control->fifos[i].tx_curr_get_info.offset = 0;
551 mac_control->fifos[i].tx_curr_get_info.fifo_len =
1da177e4 552 config->tx_cfg[i].fifo_len - 1;
20346722
K		 553 mac_control->fifos[i].fifo_no = i;
554 mac_control->fifos[i].nic = nic;
fed5eccd 555 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
20346722 556
1da177e4
LT		 557 for (j = 0; j < page_num; j++) {
558 int k = 0;
559 dma_addr_t tmp_p;
560 void *tmp_v;
561 tmp_v = pci_alloc_consistent(nic->pdev,
562 PAGE_SIZE, &tmp_p);
563 if (!tmp_v) {
0c61ed5f 564 DBG_PRINT(INFO_DBG,
1da177e4 565 "pci_alloc_consistent ");
0c61ed5f 566 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
1da177e4
LT		 567 return -ENOMEM;
568 }
776bd20f 569 /* If we got a zero DMA address(can happen on
570 * certain platforms like PPC), reallocate.
571 * Store virtual address of page we don't want,
572 * to be freed later.
573 */
574 if (!tmp_p) {
575 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 576 DBG_PRINT(INIT_DBG,
776bd20f 577 "%s: Zero DMA address for TxDL. ", dev->name);
6aa20a22 578 DBG_PRINT(INIT_DBG,
6b4d617d 579 "Virtual address %p\n", tmp_v);
776bd20f 580 tmp_v = pci_alloc_consistent(nic->pdev,
581 PAGE_SIZE, &tmp_p);
582 if (!tmp_v) {
0c61ed5f 583 DBG_PRINT(INFO_DBG,
776bd20f 584 "pci_alloc_consistent ");
0c61ed5f 585 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
776bd20f 586 return -ENOMEM;
587 }
491976b2 588 mem_allocated += PAGE_SIZE;
776bd20f 589 }
1da177e4
LT		 590 while (k < lst_per_page) {
591 int l = (j * lst_per_page) + k;
592 if (l == config->tx_cfg[i].fifo_len)
20346722
K		 593 break;
594 mac_control->fifos[i].list_info[l].list_virt_addr =
1da177e4 595 tmp_v + (k * lst_size);
20346722 596 mac_control->fifos[i].list_info[l].list_phy_addr =
1da177e4
LT		 597 tmp_p + (k * lst_size);
598 k++;
599 }
600 }
601 }
1da177e4 602
4384247b 603 nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
fed5eccd
AR		 604 if (!nic->ufo_in_band_v)
605 return -ENOMEM;
491976b2 606 mem_allocated += (size * sizeof(u64));
fed5eccd 607
1da177e4
LT		 608 /* Allocation and initialization of RXDs in Rings */
609 size = 0;
610 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 611 if (config->rx_cfg[i].num_rxd %
612 (rxd_count[nic->rxd_mode] + 1)) {
1da177e4
LT		 613 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
614 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
615 i);
616 DBG_PRINT(ERR_DBG, "RxDs per Block");
617 return FAILURE;
618 }
619 size += config->rx_cfg[i].num_rxd;
20346722 620 mac_control->rings[i].block_count =
da6971d8
AR		 621 config->rx_cfg[i].num_rxd /
622 (rxd_count[nic->rxd_mode] + 1 );
623 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
624 mac_control->rings[i].block_count;
1da177e4 625 }
da6971d8 626 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 627 size = (size * (sizeof(struct RxD1)));
da6971d8 628 else
1ee6dd77 629 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 630
631 for (i = 0; i < config->rx_ring_num; i++) {
20346722
K		 632 mac_control->rings[i].rx_curr_get_info.block_index = 0;
633 mac_control->rings[i].rx_curr_get_info.offset = 0;
634 mac_control->rings[i].rx_curr_get_info.ring_len =
1da177e4 635 config->rx_cfg[i].num_rxd - 1;
20346722
K		 636 mac_control->rings[i].rx_curr_put_info.block_index = 0;
637 mac_control->rings[i].rx_curr_put_info.offset = 0;
638 mac_control->rings[i].rx_curr_put_info.ring_len =
1da177e4 639 config->rx_cfg[i].num_rxd - 1;
20346722
K		 640 mac_control->rings[i].nic = nic;
641 mac_control->rings[i].ring_no = i;
642
da6971d8
AR		 643 blk_cnt = config->rx_cfg[i].num_rxd /
644 (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 645 /* Allocating all the Rx blocks */
646 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 647 struct rx_block_info *rx_blocks;
da6971d8
AR		 648 int l;
649
650 rx_blocks = &mac_control->rings[i].rx_blocks[j];
651 size = SIZE_OF_BLOCK; //size is always page size
1da177e4
LT		 652 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
653 &tmp_p_addr);
654 if (tmp_v_addr == NULL) {
655 /*
20346722
K		 656 * In case of failure, free_shared_mem()
657 * is called, which should free any
658 * memory that was alloced till the
1da177e4
LT		 659 * failure happened.
660 */
da6971d8 661 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 662 return -ENOMEM;
663 }
491976b2 664 mem_allocated += size;
1da177e4 665 memset(tmp_v_addr, 0, size);
da6971d8
AR		 666 rx_blocks->block_virt_addr = tmp_v_addr;
667 rx_blocks->block_dma_addr = tmp_p_addr;
1ee6dd77 668 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
da6971d8
AR		 669 rxd_count[nic->rxd_mode],
670 GFP_KERNEL);
372cc597
SS		 671 if (!rx_blocks->rxds)
672 return -ENOMEM;
491976b2
SH		 673 mem_allocated +=
674 (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
da6971d8
AR		 675 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
676 rx_blocks->rxds[l].virt_addr =
677 rx_blocks->block_virt_addr +
678 (rxd_size[nic->rxd_mode] * l);
679 rx_blocks->rxds[l].dma_addr =
680 rx_blocks->block_dma_addr +
681 (rxd_size[nic->rxd_mode] * l);
682 }
1da177e4
LT		 683 }
684 /* Interlinking all Rx Blocks */
685 for (j = 0; j < blk_cnt; j++) {
20346722
K		 686 tmp_v_addr =
687 mac_control->rings[i].rx_blocks[j].block_virt_addr;
1da177e4 688 tmp_v_addr_next =
20346722 689 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4 690 blk_cnt].block_virt_addr;
20346722
K		 691 tmp_p_addr =
692 mac_control->rings[i].rx_blocks[j].block_dma_addr;
1da177e4 693 tmp_p_addr_next =
20346722 694 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4
LT		 695 blk_cnt].block_dma_addr;
696
1ee6dd77 697 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
1da177e4
LT		 698 pre_rxd_blk->reserved_2_pNext_RxD_block =
699 (unsigned long) tmp_v_addr_next;
1da177e4
LT		 700 pre_rxd_blk->pNext_RxD_Blk_physical =
701 (u64) tmp_p_addr_next;
702 }
703 }
da6971d8
AR		 704 if (nic->rxd_mode >= RXD_MODE_3A) {
705 /*
706 * Allocation of Storages for buffer addresses in 2BUFF mode
707 * and the buffers as well.
708 */
709 for (i = 0; i < config->rx_ring_num; i++) {
710 blk_cnt = config->rx_cfg[i].num_rxd /
711 (rxd_count[nic->rxd_mode]+ 1);
712 mac_control->rings[i].ba =
1ee6dd77 713 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
1da177e4 714 GFP_KERNEL);
da6971d8 715 if (!mac_control->rings[i].ba)
1da177e4 716 return -ENOMEM;
491976b2 717 mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
da6971d8
AR		 718 for (j = 0; j < blk_cnt; j++) {
719 int k = 0;
720 mac_control->rings[i].ba[j] =
1ee6dd77 721 kmalloc((sizeof(struct buffAdd) *
da6971d8
AR		 722 (rxd_count[nic->rxd_mode] + 1)),
723 GFP_KERNEL);
724 if (!mac_control->rings[i].ba[j])
1da177e4 725 return -ENOMEM;
491976b2
SH		 726 mem_allocated += (sizeof(struct buffAdd) * \
727 (rxd_count[nic->rxd_mode] + 1));
da6971d8
AR		 728 while (k != rxd_count[nic->rxd_mode]) {
729 ba = &mac_control->rings[i].ba[j][k];
730
731 ba->ba_0_org = (void *) kmalloc
732 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
733 if (!ba->ba_0_org)
734 return -ENOMEM;
491976b2
SH		 735 mem_allocated +=
736 (BUF0_LEN + ALIGN_SIZE);
da6971d8
AR		 737 tmp = (unsigned long)ba->ba_0_org;
738 tmp += ALIGN_SIZE;
739 tmp &= ~((unsigned long) ALIGN_SIZE);
740 ba->ba_0 = (void *) tmp;
741
742 ba->ba_1_org = (void *) kmalloc
743 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
744 if (!ba->ba_1_org)
745 return -ENOMEM;
491976b2
SH		 746 mem_allocated
747 += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 748 tmp = (unsigned long) ba->ba_1_org;
749 tmp += ALIGN_SIZE;
750 tmp &= ~((unsigned long) ALIGN_SIZE);
751 ba->ba_1 = (void *) tmp;
752 k++;
753 }
1da177e4
LT		 754 }
755 }
756 }
1da177e4
LT		 757
758 /* Allocation and initialization of Statistics block */
1ee6dd77 759 size = sizeof(struct stat_block);
1da177e4
LT		 760 mac_control->stats_mem = pci_alloc_consistent
761 (nic->pdev, size, &mac_control->stats_mem_phy);
762
763 if (!mac_control->stats_mem) {
20346722
K		 764 /*
765 * In case of failure, free_shared_mem() is called, which
766 * should free any memory that was alloced till the
1da177e4
LT		 767 * failure happened.
768 */
769 return -ENOMEM;
770 }
491976b2 771 mem_allocated += size;
1da177e4
LT		 772 mac_control->stats_mem_sz = size;
773
774 tmp_v_addr = mac_control->stats_mem;
1ee6dd77 775 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
1da177e4 776 memset(tmp_v_addr, 0, size);
1da177e4
LT		 777 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
778 (unsigned long long) tmp_p_addr);
491976b2 779 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 780 return SUCCESS;
781}
782
20346722
K		 783/**
784 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 785 * @nic: Device private variable.
786 * Description: This function is to free all memory locations allocated by
787 * the init_shared_mem() function and return it to the kernel.
788 */
789
790static void free_shared_mem(struct s2io_nic *nic)
791{
792 int i, j, blk_cnt, size;
491976b2 793 u32 ufo_size = 0;
1da177e4
LT		 794 void *tmp_v_addr;
795 dma_addr_t tmp_p_addr;
1ee6dd77 796 struct mac_info *mac_control;
1da177e4
LT		 797 struct config_param *config;
798 int lst_size, lst_per_page;
8910b49f 799 struct net_device *dev;
491976b2 800 int page_num = 0;
1da177e4
LT		 801
802 if (!nic)
803 return;
804
8910b49f
MG		 805 dev = nic->dev;
806
1da177e4
LT		 807 mac_control = &nic->mac_control;
808 config = &nic->config;
809
1ee6dd77 810 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 811 lst_per_page = PAGE_SIZE / lst_size;
812
813 for (i = 0; i < config->tx_fifo_num; i++) {
491976b2
SH		 814 ufo_size += config->tx_cfg[i].fifo_len;
815 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
816 lst_per_page);
1da177e4
LT		 817 for (j = 0; j < page_num; j++) {
818 int mem_blks = (j * lst_per_page);
776bd20f 819 if (!mac_control->fifos[i].list_info)
6aa20a22 820 return;
776bd20f 821 if (!mac_control->fifos[i].list_info[mem_blks].
822 list_virt_addr)
1da177e4
LT		 823 break;
824 pci_free_consistent(nic->pdev, PAGE_SIZE,
20346722
K		 825 mac_control->fifos[i].
826 list_info[mem_blks].
1da177e4 827 list_virt_addr,
20346722
K		 828 mac_control->fifos[i].
829 list_info[mem_blks].
1da177e4 830 list_phy_addr);
491976b2
SH		 831 nic->mac_control.stats_info->sw_stat.mem_freed
832 += PAGE_SIZE;
1da177e4 833 }
776bd20f 834 /* If we got a zero DMA address during allocation,
835 * free the page now
836 */
837 if (mac_control->zerodma_virt_addr) {
838 pci_free_consistent(nic->pdev, PAGE_SIZE,
839 mac_control->zerodma_virt_addr,
840 (dma_addr_t)0);
6aa20a22 841 DBG_PRINT(INIT_DBG,
6b4d617d
AM		 842 "%s: Freeing TxDL with zero DMA addr. ",
843 dev->name);
844 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
845 mac_control->zerodma_virt_addr);
491976b2
SH		 846 nic->mac_control.stats_info->sw_stat.mem_freed
847 += PAGE_SIZE;
776bd20f 848 }
20346722 849 kfree(mac_control->fifos[i].list_info);
491976b2
SH		 850 nic->mac_control.stats_info->sw_stat.mem_freed +=
851 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
1da177e4
LT		 852 }
853
1da177e4 854 size = SIZE_OF_BLOCK;
1da177e4 855 for (i = 0; i < config->rx_ring_num; i++) {
20346722 856 blk_cnt = mac_control->rings[i].block_count;
1da177e4 857 for (j = 0; j < blk_cnt; j++) {
20346722
K		 858 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
859 block_virt_addr;
860 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
861 block_dma_addr;
1da177e4
LT		 862 if (tmp_v_addr == NULL)
863 break;
864 pci_free_consistent(nic->pdev, size,
865 tmp_v_addr, tmp_p_addr);
491976b2 866 nic->mac_control.stats_info->sw_stat.mem_freed += size;
da6971d8 867 kfree(mac_control->rings[i].rx_blocks[j].rxds);
491976b2
SH		 868 nic->mac_control.stats_info->sw_stat.mem_freed +=
869 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1da177e4
LT		 870 }
871 }
872
da6971d8
AR		 873 if (nic->rxd_mode >= RXD_MODE_3A) {
874 /* Freeing buffer storage addresses in 2BUFF mode. */
875 for (i = 0; i < config->rx_ring_num; i++) {
876 blk_cnt = config->rx_cfg[i].num_rxd /
877 (rxd_count[nic->rxd_mode] + 1);
878 for (j = 0; j < blk_cnt; j++) {
879 int k = 0;
880 if (!mac_control->rings[i].ba[j])
881 continue;
882 while (k != rxd_count[nic->rxd_mode]) {
1ee6dd77 883 struct buffAdd *ba =
da6971d8
AR		 884 &mac_control->rings[i].ba[j][k];
885 kfree(ba->ba_0_org);
491976b2
SH		 886 nic->mac_control.stats_info->sw_stat.\
887 mem_freed += (BUF0_LEN + ALIGN_SIZE);
da6971d8 888 kfree(ba->ba_1_org);
491976b2
SH		 889 nic->mac_control.stats_info->sw_stat.\
890 mem_freed += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 891 k++;
892 }
893 kfree(mac_control->rings[i].ba[j]);
491976b2
SH		 894 nic->mac_control.stats_info->sw_stat.mem_freed += (sizeof(struct buffAdd) *
895 (rxd_count[nic->rxd_mode] + 1));
1da177e4 896 }
da6971d8 897 kfree(mac_control->rings[i].ba);
491976b2
SH		 898 nic->mac_control.stats_info->sw_stat.mem_freed +=
899 (sizeof(struct buffAdd *) * blk_cnt);
1da177e4 900 }
1da177e4 901 }
1da177e4
LT		 902
903 if (mac_control->stats_mem) {
904 pci_free_consistent(nic->pdev,
905 mac_control->stats_mem_sz,
906 mac_control->stats_mem,
907 mac_control->stats_mem_phy);
491976b2
SH		 908 nic->mac_control.stats_info->sw_stat.mem_freed +=
909 mac_control->stats_mem_sz;
1da177e4 910 }
491976b2 911 if (nic->ufo_in_band_v) {
fed5eccd 912 kfree(nic->ufo_in_band_v);
491976b2
SH		 913 nic->mac_control.stats_info->sw_stat.mem_freed
914 += (ufo_size * sizeof(u64));
915 }
1da177e4
LT		 916}
917
541ae68f
K		 918/**
919 * s2io_verify_pci_mode -
920 */
921
1ee6dd77 922static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 923{
1ee6dd77 924 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 925 register u64 val64 = 0;
926 int mode;
927
928 val64 = readq(&bar0->pci_mode);
929 mode = (u8)GET_PCI_MODE(val64);
930
931 if ( val64 & PCI_MODE_UNKNOWN_MODE)
932 return -1; /* Unknown PCI mode */
933 return mode;
934}
935
c92ca04b
AR		 936#define NEC_VENID 0x1033
937#define NEC_DEVID 0x0125
938static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
939{
940 struct pci_dev *tdev = NULL;
26d36b64
AC		 941 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
942 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
c92ca04b 943 if (tdev->bus == s2io_pdev->bus->parent)
26d36b64 944 pci_dev_put(tdev);
c92ca04b
AR		 945 return 1;
946 }
947 }
948 return 0;
949}
541ae68f 950
7b32a312 951static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f
K		 952/**
953 * s2io_print_pci_mode -
954 */
1ee6dd77 955static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 956{
1ee6dd77 957 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 958 register u64 val64 = 0;
959 int mode;
960 struct config_param *config = &nic->config;
961
962 val64 = readq(&bar0->pci_mode);
963 mode = (u8)GET_PCI_MODE(val64);
964
965 if ( val64 & PCI_MODE_UNKNOWN_MODE)
966 return -1; /* Unknown PCI mode */
967
c92ca04b
AR		 968 config->bus_speed = bus_speed[mode];
969
970 if (s2io_on_nec_bridge(nic->pdev)) {
971 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
972 nic->dev->name);
973 return mode;
974 }
975
541ae68f
K		 976 if (val64 & PCI_MODE_32_BITS) {
977 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
978 } else {
979 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
980 }
981
982 switch(mode) {
983 case PCI_MODE_PCI_33:
984 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
541ae68f
K		 985 break;
986 case PCI_MODE_PCI_66:
987 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
541ae68f
K		 988 break;
989 case PCI_MODE_PCIX_M1_66:
990 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
541ae68f
K		 991 break;
992 case PCI_MODE_PCIX_M1_100:
993 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
541ae68f
K		 994 break;
995 case PCI_MODE_PCIX_M1_133:
996 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
541ae68f
K		 997 break;
998 case PCI_MODE_PCIX_M2_66:
999 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
541ae68f
K		 1000 break;
1001 case PCI_MODE_PCIX_M2_100:
1002 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
541ae68f
K		 1003 break;
1004 case PCI_MODE_PCIX_M2_133:
1005 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
541ae68f
K		 1006 break;
1007 default:
1008 return -1; /* Unsupported bus speed */
1009 }
1010
1011 return mode;
1012}
1013
20346722
K		 1014/**
1015 * init_nic - Initialization of hardware
1da177e4 1016 * @nic: device peivate variable
20346722
K		 1017 * Description: The function sequentially configures every block
1018 * of the H/W from their reset values.
1019 * Return Value: SUCCESS on success and
1da177e4
LT		 1020 * '-1' on failure (endian settings incorrect).
1021 */
1022
1023static int init_nic(struct s2io_nic *nic)
1024{
1ee6dd77 1025 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1026 struct net_device *dev = nic->dev;
1027 register u64 val64 = 0;
1028 void __iomem *add;
1029 u32 time;
1030 int i, j;
1ee6dd77 1031 struct mac_info *mac_control;
1da177e4 1032 struct config_param *config;
c92ca04b 1033 int dtx_cnt = 0;
1da177e4 1034 unsigned long long mem_share;
20346722 1035 int mem_size;
1da177e4
LT		 1036
1037 mac_control = &nic->mac_control;
1038 config = &nic->config;
1039
5e25b9dd 1040 /* to set the swapper controle on the card */
20346722 1041 if(s2io_set_swapper(nic)) {
1da177e4
LT		 1042 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1043 return -1;
1044 }
1045
541ae68f
K		 1046 /*
1047 * Herc requires EOI to be removed from reset before XGXS, so..
1048 */
1049 if (nic->device_type & XFRAME_II_DEVICE) {
1050 val64 = 0xA500000000ULL;
1051 writeq(val64, &bar0->sw_reset);
1052 msleep(500);
1053 val64 = readq(&bar0->sw_reset);
1054 }
1055
1da177e4
LT		 1056 /* Remove XGXS from reset state */
1057 val64 = 0;
1058 writeq(val64, &bar0->sw_reset);
1da177e4 1059 msleep(500);
20346722 1060 val64 = readq(&bar0->sw_reset);
1da177e4
LT		 1061
1062 /* Enable Receiving broadcasts */
1063 add = &bar0->mac_cfg;
1064 val64 = readq(&bar0->mac_cfg);
1065 val64 |= MAC_RMAC_BCAST_ENABLE;
1066 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1067 writel((u32) val64, add);
1068 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1069 writel((u32) (val64 >> 32), (add + 4));
1070
1071 /* Read registers in all blocks */
1072 val64 = readq(&bar0->mac_int_mask);
1073 val64 = readq(&bar0->mc_int_mask);
1074 val64 = readq(&bar0->xgxs_int_mask);
1075
1076 /* Set MTU */
1077 val64 = dev->mtu;
1078 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1079
541ae68f
K		 1080 if (nic->device_type & XFRAME_II_DEVICE) {
1081 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1082 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1083 &bar0->dtx_control, UF);
541ae68f
K		 1084 if (dtx_cnt & 0x1)
1085 msleep(1); /* Necessary!! */
1da177e4
LT		 1086 dtx_cnt++;
1087 }
541ae68f 1088 } else {
c92ca04b
AR		 1089 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1090 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1091 &bar0->dtx_control, UF);
1092 val64 = readq(&bar0->dtx_control);
1093 dtx_cnt++;
1da177e4
LT		 1094 }
1095 }
1096
1097 /* Tx DMA Initialization */
1098 val64 = 0;
1099 writeq(val64, &bar0->tx_fifo_partition_0);
1100 writeq(val64, &bar0->tx_fifo_partition_1);
1101 writeq(val64, &bar0->tx_fifo_partition_2);
1102 writeq(val64, &bar0->tx_fifo_partition_3);
1103
1104
1105 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1106 val64 |=
1107 vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1108 13) | vBIT(config->tx_cfg[i].fifo_priority,
1109 ((i * 32) + 5), 3);
1110
1111 if (i == (config->tx_fifo_num - 1)) {
1112 if (i % 2 == 0)
1113 i++;
1114 }
1115
1116 switch (i) {
1117 case 1:
1118 writeq(val64, &bar0->tx_fifo_partition_0);
1119 val64 = 0;
1120 break;
1121 case 3:
1122 writeq(val64, &bar0->tx_fifo_partition_1);
1123 val64 = 0;
1124 break;
1125 case 5:
1126 writeq(val64, &bar0->tx_fifo_partition_2);
1127 val64 = 0;
1128 break;
1129 case 7:
1130 writeq(val64, &bar0->tx_fifo_partition_3);
1131 break;
1132 }
1133 }
1134
5e25b9dd
K		 1135 /*
1136 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1137 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1138 */
541ae68f 1139 if ((nic->device_type == XFRAME_I_DEVICE) &&
44c10138 1140 (nic->pdev->revision < 4))
5e25b9dd
K		 1141 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1142
1da177e4
LT		 1143 val64 = readq(&bar0->tx_fifo_partition_0);
1144 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1145 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1146
20346722
K		 1147 /*
1148 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1149 * integrity checking.
1150 */
1151 val64 = readq(&bar0->tx_pa_cfg);
1152 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1153 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1154 writeq(val64, &bar0->tx_pa_cfg);
1155
1156 /* Rx DMA intialization. */
1157 val64 = 0;
1158 for (i = 0; i < config->rx_ring_num; i++) {
1159 val64 |=
1160 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1161 3);
1162 }
1163 writeq(val64, &bar0->rx_queue_priority);
1164
20346722
K		 1165 /*
1166 * Allocating equal share of memory to all the
1da177e4
LT		 1167 * configured Rings.
1168 */
1169 val64 = 0;
541ae68f
K		 1170 if (nic->device_type & XFRAME_II_DEVICE)
1171 mem_size = 32;
1172 else
1173 mem_size = 64;
1174
1da177e4
LT		 1175 for (i = 0; i < config->rx_ring_num; i++) {
1176 switch (i) {
1177 case 0:
20346722
K		 1178 mem_share = (mem_size / config->rx_ring_num +
1179 mem_size % config->rx_ring_num);
1da177e4
LT		 1180 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1181 continue;
1182 case 1:
20346722 1183 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1184 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1185 continue;
1186 case 2:
20346722 1187 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1188 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1189 continue;
1190 case 3:
20346722 1191 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1192 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1193 continue;
1194 case 4:
20346722 1195 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1196 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1197 continue;
1198 case 5:
20346722 1199 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1200 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1201 continue;
1202 case 6:
20346722 1203 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1204 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1205 continue;
1206 case 7:
20346722 1207 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1208 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1209 continue;
1210 }
1211 }
1212 writeq(val64, &bar0->rx_queue_cfg);
1213
20346722 1214 /*
5e25b9dd
K		 1215 * Filling Tx round robin registers
1216 * as per the number of FIFOs
1da177e4 1217 */
5e25b9dd
K		 1218 switch (config->tx_fifo_num) {
1219 case 1:
1220 val64 = 0x0000000000000000ULL;
1221 writeq(val64, &bar0->tx_w_round_robin_0);
1222 writeq(val64, &bar0->tx_w_round_robin_1);
1223 writeq(val64, &bar0->tx_w_round_robin_2);
1224 writeq(val64, &bar0->tx_w_round_robin_3);
1225 writeq(val64, &bar0->tx_w_round_robin_4);
1226 break;
1227 case 2:
1228 val64 = 0x0000010000010000ULL;
1229 writeq(val64, &bar0->tx_w_round_robin_0);
1230 val64 = 0x0100000100000100ULL;
1231 writeq(val64, &bar0->tx_w_round_robin_1);
1232 val64 = 0x0001000001000001ULL;
1233 writeq(val64, &bar0->tx_w_round_robin_2);
1234 val64 = 0x0000010000010000ULL;
1235 writeq(val64, &bar0->tx_w_round_robin_3);
1236 val64 = 0x0100000000000000ULL;
1237 writeq(val64, &bar0->tx_w_round_robin_4);
1238 break;
1239 case 3:
1240 val64 = 0x0001000102000001ULL;
1241 writeq(val64, &bar0->tx_w_round_robin_0);
1242 val64 = 0x0001020000010001ULL;
1243 writeq(val64, &bar0->tx_w_round_robin_1);
1244 val64 = 0x0200000100010200ULL;
1245 writeq(val64, &bar0->tx_w_round_robin_2);
1246 val64 = 0x0001000102000001ULL;
1247 writeq(val64, &bar0->tx_w_round_robin_3);
1248 val64 = 0x0001020000000000ULL;
1249 writeq(val64, &bar0->tx_w_round_robin_4);
1250 break;
1251 case 4:
1252 val64 = 0x0001020300010200ULL;
1253 writeq(val64, &bar0->tx_w_round_robin_0);
1254 val64 = 0x0100000102030001ULL;
1255 writeq(val64, &bar0->tx_w_round_robin_1);
1256 val64 = 0x0200010000010203ULL;
1257 writeq(val64, &bar0->tx_w_round_robin_2);
1258 val64 = 0x0001020001000001ULL;
1259 writeq(val64, &bar0->tx_w_round_robin_3);
1260 val64 = 0x0203000100000000ULL;
1261 writeq(val64, &bar0->tx_w_round_robin_4);
1262 break;
1263 case 5:
1264 val64 = 0x0001000203000102ULL;
1265 writeq(val64, &bar0->tx_w_round_robin_0);
1266 val64 = 0x0001020001030004ULL;
1267 writeq(val64, &bar0->tx_w_round_robin_1);
1268 val64 = 0x0001000203000102ULL;
1269 writeq(val64, &bar0->tx_w_round_robin_2);
1270 val64 = 0x0001020001030004ULL;
1271 writeq(val64, &bar0->tx_w_round_robin_3);
1272 val64 = 0x0001000000000000ULL;
1273 writeq(val64, &bar0->tx_w_round_robin_4);
1274 break;
1275 case 6:
1276 val64 = 0x0001020304000102ULL;
1277 writeq(val64, &bar0->tx_w_round_robin_0);
1278 val64 = 0x0304050001020001ULL;
1279 writeq(val64, &bar0->tx_w_round_robin_1);
1280 val64 = 0x0203000100000102ULL;
1281 writeq(val64, &bar0->tx_w_round_robin_2);
1282 val64 = 0x0304000102030405ULL;
1283 writeq(val64, &bar0->tx_w_round_robin_3);
1284 val64 = 0x0001000200000000ULL;
1285 writeq(val64, &bar0->tx_w_round_robin_4);
1286 break;
1287 case 7:
1288 val64 = 0x0001020001020300ULL;
1289 writeq(val64, &bar0->tx_w_round_robin_0);
1290 val64 = 0x0102030400010203ULL;
1291 writeq(val64, &bar0->tx_w_round_robin_1);
1292 val64 = 0x0405060001020001ULL;
1293 writeq(val64, &bar0->tx_w_round_robin_2);
1294 val64 = 0x0304050000010200ULL;
1295 writeq(val64, &bar0->tx_w_round_robin_3);
1296 val64 = 0x0102030000000000ULL;
1297 writeq(val64, &bar0->tx_w_round_robin_4);
1298 break;
1299 case 8:
1300 val64 = 0x0001020300040105ULL;
1301 writeq(val64, &bar0->tx_w_round_robin_0);
1302 val64 = 0x0200030106000204ULL;
1303 writeq(val64, &bar0->tx_w_round_robin_1);
1304 val64 = 0x0103000502010007ULL;
1305 writeq(val64, &bar0->tx_w_round_robin_2);
1306 val64 = 0x0304010002060500ULL;
1307 writeq(val64, &bar0->tx_w_round_robin_3);
1308 val64 = 0x0103020400000000ULL;
1309 writeq(val64, &bar0->tx_w_round_robin_4);
1310 break;
1311 }
1312
b41477f3 1313 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1314 val64 = readq(&bar0->tx_fifo_partition_0);
1315 val64 |= (TX_FIFO_PARTITION_EN);
1316 writeq(val64, &bar0->tx_fifo_partition_0);
1317
5e25b9dd
K		 1318 /* Filling the Rx round robin registers as per the
1319 * number of Rings and steering based on QoS.
1320 */
1321 switch (config->rx_ring_num) {
1322 case 1:
1323 val64 = 0x8080808080808080ULL;
1324 writeq(val64, &bar0->rts_qos_steering);
1325 break;
1326 case 2:
1327 val64 = 0x0000010000010000ULL;
1328 writeq(val64, &bar0->rx_w_round_robin_0);
1329 val64 = 0x0100000100000100ULL;
1330 writeq(val64, &bar0->rx_w_round_robin_1);
1331 val64 = 0x0001000001000001ULL;
1332 writeq(val64, &bar0->rx_w_round_robin_2);
1333 val64 = 0x0000010000010000ULL;
1334 writeq(val64, &bar0->rx_w_round_robin_3);
1335 val64 = 0x0100000000000000ULL;
1336 writeq(val64, &bar0->rx_w_round_robin_4);
1337
1338 val64 = 0x8080808040404040ULL;
1339 writeq(val64, &bar0->rts_qos_steering);
1340 break;
1341 case 3:
1342 val64 = 0x0001000102000001ULL;
1343 writeq(val64, &bar0->rx_w_round_robin_0);
1344 val64 = 0x0001020000010001ULL;
1345 writeq(val64, &bar0->rx_w_round_robin_1);
1346 val64 = 0x0200000100010200ULL;
1347 writeq(val64, &bar0->rx_w_round_robin_2);
1348 val64 = 0x0001000102000001ULL;
1349 writeq(val64, &bar0->rx_w_round_robin_3);
1350 val64 = 0x0001020000000000ULL;
1351 writeq(val64, &bar0->rx_w_round_robin_4);
1352
1353 val64 = 0x8080804040402020ULL;
1354 writeq(val64, &bar0->rts_qos_steering);
1355 break;
1356 case 4:
1357 val64 = 0x0001020300010200ULL;
1358 writeq(val64, &bar0->rx_w_round_robin_0);
1359 val64 = 0x0100000102030001ULL;
1360 writeq(val64, &bar0->rx_w_round_robin_1);
1361 val64 = 0x0200010000010203ULL;
1362 writeq(val64, &bar0->rx_w_round_robin_2);
6aa20a22 1363 val64 = 0x0001020001000001ULL;
5e25b9dd
K		 1364 writeq(val64, &bar0->rx_w_round_robin_3);
1365 val64 = 0x0203000100000000ULL;
1366 writeq(val64, &bar0->rx_w_round_robin_4);
1367
1368 val64 = 0x8080404020201010ULL;
1369 writeq(val64, &bar0->rts_qos_steering);
1370 break;
1371 case 5:
1372 val64 = 0x0001000203000102ULL;
1373 writeq(val64, &bar0->rx_w_round_robin_0);
1374 val64 = 0x0001020001030004ULL;
1375 writeq(val64, &bar0->rx_w_round_robin_1);
1376 val64 = 0x0001000203000102ULL;
1377 writeq(val64, &bar0->rx_w_round_robin_2);
1378 val64 = 0x0001020001030004ULL;
1379 writeq(val64, &bar0->rx_w_round_robin_3);
1380 val64 = 0x0001000000000000ULL;
1381 writeq(val64, &bar0->rx_w_round_robin_4);
1382
1383 val64 = 0x8080404020201008ULL;
1384 writeq(val64, &bar0->rts_qos_steering);
1385 break;
1386 case 6:
1387 val64 = 0x0001020304000102ULL;
1388 writeq(val64, &bar0->rx_w_round_robin_0);
1389 val64 = 0x0304050001020001ULL;
1390 writeq(val64, &bar0->rx_w_round_robin_1);
1391 val64 = 0x0203000100000102ULL;
1392 writeq(val64, &bar0->rx_w_round_robin_2);
1393 val64 = 0x0304000102030405ULL;
1394 writeq(val64, &bar0->rx_w_round_robin_3);
1395 val64 = 0x0001000200000000ULL;
1396 writeq(val64, &bar0->rx_w_round_robin_4);
1397
1398 val64 = 0x8080404020100804ULL;
1399 writeq(val64, &bar0->rts_qos_steering);
1400 break;
1401 case 7:
1402 val64 = 0x0001020001020300ULL;
1403 writeq(val64, &bar0->rx_w_round_robin_0);
1404 val64 = 0x0102030400010203ULL;
1405 writeq(val64, &bar0->rx_w_round_robin_1);
1406 val64 = 0x0405060001020001ULL;
1407 writeq(val64, &bar0->rx_w_round_robin_2);
1408 val64 = 0x0304050000010200ULL;
1409 writeq(val64, &bar0->rx_w_round_robin_3);
1410 val64 = 0x0102030000000000ULL;
1411 writeq(val64, &bar0->rx_w_round_robin_4);
1412
1413 val64 = 0x8080402010080402ULL;
1414 writeq(val64, &bar0->rts_qos_steering);
1415 break;
1416 case 8:
1417 val64 = 0x0001020300040105ULL;
1418 writeq(val64, &bar0->rx_w_round_robin_0);
1419 val64 = 0x0200030106000204ULL;
1420 writeq(val64, &bar0->rx_w_round_robin_1);
1421 val64 = 0x0103000502010007ULL;
1422 writeq(val64, &bar0->rx_w_round_robin_2);
1423 val64 = 0x0304010002060500ULL;
1424 writeq(val64, &bar0->rx_w_round_robin_3);
1425 val64 = 0x0103020400000000ULL;
1426 writeq(val64, &bar0->rx_w_round_robin_4);
1427
1428 val64 = 0x8040201008040201ULL;
1429 writeq(val64, &bar0->rts_qos_steering);
1430 break;
1431 }
1da177e4
LT		 1432
1433 /* UDP Fix */
1434 val64 = 0;
20346722 1435 for (i = 0; i < 8; i++)
1da177e4
LT		 1436 writeq(val64, &bar0->rts_frm_len_n[i]);
1437
5e25b9dd
K		 1438 /* Set the default rts frame length for the rings configured */
1439 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1440 for (i = 0 ; i < config->rx_ring_num ; i++)
1441 writeq(val64, &bar0->rts_frm_len_n[i]);
1442
1443 /* Set the frame length for the configured rings
1444 * desired by the user
1445 */
1446 for (i = 0; i < config->rx_ring_num; i++) {
1447 /* If rts_frm_len[i] == 0 then it is assumed that user not
1448 * specified frame length steering.
1449 * If the user provides the frame length then program
1450 * the rts_frm_len register for those values or else
1451 * leave it as it is.
1452 */
1453 if (rts_frm_len[i] != 0) {
1454 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1455 &bar0->rts_frm_len_n[i]);
1456 }
1457 }
926930b2 1458
9fc93a41
SS		 1459 /* Disable differentiated services steering logic */
1460 for (i = 0; i < 64; i++) {
1461 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1462 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1463 dev->name);
1464 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1465 return FAILURE;
1466 }
1467 }
1468
20346722 1469 /* Program statistics memory */
1da177e4 1470 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1471
541ae68f
K		 1472 if (nic->device_type == XFRAME_II_DEVICE) {
1473 val64 = STAT_BC(0x320);
1474 writeq(val64, &bar0->stat_byte_cnt);
1475 }
1476
20346722 1477 /*
1da177e4
LT		 1478 * Initializing the sampling rate for the device to calculate the
1479 * bandwidth utilization.
1480 */
1481 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1482 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1483 writeq(val64, &bar0->mac_link_util);
1484
1485
20346722
K		 1486 /*
1487 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1488 * Scheme.
1489 */
20346722
K		 1490 /*
1491 * TTI Initialization. Default Tx timer gets us about
1da177e4
LT		 1492 * 250 interrupts per sec. Continuous interrupts are enabled
1493 * by default.
1494 */
541ae68f
K		 1495 if (nic->device_type == XFRAME_II_DEVICE) {
1496 int count = (nic->config.bus_speed * 125)/2;
1497 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1498 } else {
1499
1500 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1501 }
1502 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1da177e4 1503 TTI_DATA1_MEM_TX_URNG_B(0x10) |
5e25b9dd 1504 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
541ae68f
K		 1505 if (use_continuous_tx_intrs)
1506 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1da177e4
LT		 1507 writeq(val64, &bar0->tti_data1_mem);
1508
1509 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1510 TTI_DATA2_MEM_TX_UFC_B(0x20) |
19a60522 1511 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1da177e4
LT		 1512 writeq(val64, &bar0->tti_data2_mem);
1513
1514 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1515 writeq(val64, &bar0->tti_command_mem);
1516
20346722 1517 /*
1da177e4
LT		 1518 * Once the operation completes, the Strobe bit of the command
1519 * register will be reset. We poll for this particular condition
1520 * We wait for a maximum of 500ms for the operation to complete,
1521 * if it's not complete by then we return error.
1522 */
1523 time = 0;
1524 while (TRUE) {
1525 val64 = readq(&bar0->tti_command_mem);
1526 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1527 break;
1528 }
1529 if (time > 10) {
1530 DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1531 dev->name);
1532 return -1;
1533 }
1534 msleep(50);
1535 time++;
1536 }
1537
b6e3f982
K		 1538 if (nic->config.bimodal) {
1539 int k = 0;
1540 for (k = 0; k < config->rx_ring_num; k++) {
1541 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1542 val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1543 writeq(val64, &bar0->tti_command_mem);
541ae68f 1544
541ae68f 1545 /*
b6e3f982
K		 1546 * Once the operation completes, the Strobe bit of the command
1547 * register will be reset. We poll for this particular condition
1548 * We wait for a maximum of 500ms for the operation to complete,
1549 * if it's not complete by then we return error.
1550 */
1551 time = 0;
1552 while (TRUE) {
1553 val64 = readq(&bar0->tti_command_mem);
1554 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1555 break;
1556 }
1557 if (time > 10) {
1558 DBG_PRINT(ERR_DBG,
1559 "%s: TTI init Failed\n",
1560 dev->name);
1561 return -1;
1562 }
1563 time++;
1564 msleep(50);
1565 }
1566 }
541ae68f 1567 } else {
1da177e4 1568
b6e3f982
K		 1569 /* RTI Initialization */
1570 if (nic->device_type == XFRAME_II_DEVICE) {
1571 /*
1572 * Programmed to generate Apprx 500 Intrs per
1573 * second
1574 */
1575 int count = (nic->config.bus_speed * 125)/4;
1576 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1577 } else {
1578 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1579 }
1580 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1581 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1582 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1da177e4 1583
b6e3f982 1584 writeq(val64, &bar0->rti_data1_mem);
1da177e4 1585
b6e3f982 1586 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
cc6e7c44
RA		 1587 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1588 if (nic->intr_type == MSI_X)
1589 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1590 RTI_DATA2_MEM_RX_UFC_D(0x40));
1591 else
1592 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1593 RTI_DATA2_MEM_RX_UFC_D(0x80));
b6e3f982 1594 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1595
b6e3f982
K		 1596 for (i = 0; i < config->rx_ring_num; i++) {
1597 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1598 | RTI_CMD_MEM_OFFSET(i);
1599 writeq(val64, &bar0->rti_command_mem);
1600
1601 /*
1602 * Once the operation completes, the Strobe bit of the
1603 * command register will be reset. We poll for this
1604 * particular condition. We wait for a maximum of 500ms
1605 * for the operation to complete, if it's not complete
1606 * by then we return error.
1607 */
1608 time = 0;
1609 while (TRUE) {
1610 val64 = readq(&bar0->rti_command_mem);
1611 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1612 break;
1613 }
1614 if (time > 10) {
1615 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1616 dev->name);
1617 return -1;
1618 }
1619 time++;
1620 msleep(50);
1621 }
1da177e4 1622 }
1da177e4
LT		 1623 }
1624
20346722
K		 1625 /*
1626 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1627 * the 8 Queues on Rx side.
1628 */
1629 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1630 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1631
1632 /* Disable RMAC PAD STRIPPING */
509a2671 1633 add = &bar0->mac_cfg;
1da177e4
LT		 1634 val64 = readq(&bar0->mac_cfg);
1635 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1636 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1637 writel((u32) (val64), add);
1638 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1639 writel((u32) (val64 >> 32), (add + 4));
1640 val64 = readq(&bar0->mac_cfg);
1641
7d3d0439
RA		 1642 /* Enable FCS stripping by adapter */
1643 add = &bar0->mac_cfg;
1644 val64 = readq(&bar0->mac_cfg);
1645 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1646 if (nic->device_type == XFRAME_II_DEVICE)
1647 writeq(val64, &bar0->mac_cfg);
1648 else {
1649 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1650 writel((u32) (val64), add);
1651 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1652 writel((u32) (val64 >> 32), (add + 4));
1653 }
1654
20346722
K		 1655 /*
1656 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1657 * generated by xena.
1658 */
1659 val64 = readq(&bar0->rmac_pause_cfg);
1660 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1661 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1662 writeq(val64, &bar0->rmac_pause_cfg);
1663
20346722 1664 /*
1da177e4
LT		 1665 * Set the Threshold Limit for Generating the pause frame
1666 * If the amount of data in any Queue exceeds ratio of
1667 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1668 * pause frame is generated
1669 */
1670 val64 = 0;
1671 for (i = 0; i < 4; i++) {
1672 val64 |=
1673 (((u64) 0xFF00 | nic->mac_control.
1674 mc_pause_threshold_q0q3)
1675 << (i * 2 * 8));
1676 }
1677 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1678
1679 val64 = 0;
1680 for (i = 0; i < 4; i++) {
1681 val64 |=
1682 (((u64) 0xFF00 | nic->mac_control.
1683 mc_pause_threshold_q4q7)
1684 << (i * 2 * 8));
1685 }
1686 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1687
20346722
K		 1688 /*
1689 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1690 * exceeded the limit pointed by shared_splits
1691 */
1692 val64 = readq(&bar0->pic_control);
1693 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1694 writeq(val64, &bar0->pic_control);
1695
863c11a9
AR		 1696 if (nic->config.bus_speed == 266) {
1697 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1698 writeq(0x0, &bar0->read_retry_delay);
1699 writeq(0x0, &bar0->write_retry_delay);
1700 }
1701
541ae68f
K		 1702 /*
1703 * Programming the Herc to split every write transaction
1704 * that does not start on an ADB to reduce disconnects.
1705 */
1706 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1707 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1708 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1709 writeq(val64, &bar0->misc_control);
1710 val64 = readq(&bar0->pic_control2);
1711 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1712 writeq(val64, &bar0->pic_control2);
541ae68f 1713 }
c92ca04b
AR		 1714 if (strstr(nic->product_name, "CX4")) {
1715 val64 = TMAC_AVG_IPG(0x17);
1716 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d
K		 1717 }
1718
1da177e4
LT		 1719 return SUCCESS;
1720}
a371a07d
K		 1721#define LINK_UP_DOWN_INTERRUPT 1
1722#define MAC_RMAC_ERR_TIMER 2
1723
1ee6dd77 1724static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d 1725{
cc6e7c44
RA		 1726 if (nic->intr_type != INTA)
1727 return MAC_RMAC_ERR_TIMER;
a371a07d
K		 1728 if (nic->device_type == XFRAME_II_DEVICE)
1729 return LINK_UP_DOWN_INTERRUPT;
1730 else
1731 return MAC_RMAC_ERR_TIMER;
1732}
1da177e4 1733
20346722
K		 1734/**
1735 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 1736 * @nic: device private variable,
1737 * @mask: A mask indicating which Intr block must be modified and,
1738 * @flag: A flag indicating whether to enable or disable the Intrs.
1739 * Description: This function will either disable or enable the interrupts
20346722
K		 1740 * depending on the flag argument. The mask argument can be used to
1741 * enable/disable any Intr block.
1da177e4
LT		 1742 * Return Value: NONE.
1743 */
1744
1745static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1746{
1ee6dd77 1747 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1748 register u64 val64 = 0, temp64 = 0;
1749
1750 /* Top level interrupt classification */
1751 /* PIC Interrupts */
1752 if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1753 /* Enable PIC Intrs in the general intr mask register */
a113ae06 1754 val64 = TXPIC_INT_M;
1da177e4
LT		 1755 if (flag == ENABLE_INTRS) {
1756 temp64 = readq(&bar0->general_int_mask);
1757 temp64 &= ~((u64) val64);
1758 writeq(temp64, &bar0->general_int_mask);
20346722 1759 /*
a371a07d 1760 * If Hercules adapter enable GPIO otherwise
b41477f3 1761 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722
K		 1762 * interrupts for now.
1763 * TODO
1da177e4 1764 */
a371a07d
K		 1765 if (s2io_link_fault_indication(nic) ==
1766 LINK_UP_DOWN_INTERRUPT ) {
1767 temp64 = readq(&bar0->pic_int_mask);
1768 temp64 &= ~((u64) PIC_INT_GPIO);
1769 writeq(temp64, &bar0->pic_int_mask);
1770 temp64 = readq(&bar0->gpio_int_mask);
1771 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1772 writeq(temp64, &bar0->gpio_int_mask);
1773 } else {
1774 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1775 }
20346722 1776 /*
1da177e4
LT		 1777 * No MSI Support is available presently, so TTI and
1778 * RTI interrupts are also disabled.
1779 */
1780 } else if (flag == DISABLE_INTRS) {
20346722
K		 1781 /*
1782 * Disable PIC Intrs in the general
1783 * intr mask register
1da177e4
LT		 1784 */
1785 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1786 temp64 = readq(&bar0->general_int_mask);
1787 val64 |= temp64;
1788 writeq(val64, &bar0->general_int_mask);
1789 }
1790 }
1791
1da177e4
LT		 1792 /* MAC Interrupts */
1793 /* Enabling/Disabling MAC interrupts */
1794 if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1795 val64 = TXMAC_INT_M | RXMAC_INT_M;
1796 if (flag == ENABLE_INTRS) {
1797 temp64 = readq(&bar0->general_int_mask);
1798 temp64 &= ~((u64) val64);
1799 writeq(temp64, &bar0->general_int_mask);
20346722
K		 1800 /*
1801 * All MAC block error interrupts are disabled for now
1da177e4
LT		 1802 * TODO
1803 */
1da177e4 1804 } else if (flag == DISABLE_INTRS) {
20346722
K		 1805 /*
1806 * Disable MAC Intrs in the general intr mask register
1da177e4
LT		 1807 */
1808 writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1809 writeq(DISABLE_ALL_INTRS,
1810 &bar0->mac_rmac_err_mask);
1811
1812 temp64 = readq(&bar0->general_int_mask);
1813 val64 |= temp64;
1814 writeq(val64, &bar0->general_int_mask);
1815 }
1816 }
1817
1da177e4
LT		 1818 /* Tx traffic interrupts */
1819 if (mask & TX_TRAFFIC_INTR) {
1820 val64 = TXTRAFFIC_INT_M;
1821 if (flag == ENABLE_INTRS) {
1822 temp64 = readq(&bar0->general_int_mask);
1823 temp64 &= ~((u64) val64);
1824 writeq(temp64, &bar0->general_int_mask);
20346722 1825 /*
1da177e4 1826 * Enable all the Tx side interrupts
20346722 1827 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 1828 */
1829 writeq(0x0, &bar0->tx_traffic_mask);
1830 } else if (flag == DISABLE_INTRS) {
20346722
K		 1831 /*
1832 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 1833 * register.
1834 */
1835 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1836 temp64 = readq(&bar0->general_int_mask);
1837 val64 |= temp64;
1838 writeq(val64, &bar0->general_int_mask);
1839 }
1840 }
1841
1842 /* Rx traffic interrupts */
1843 if (mask & RX_TRAFFIC_INTR) {
1844 val64 = RXTRAFFIC_INT_M;
1845 if (flag == ENABLE_INTRS) {
1846 temp64 = readq(&bar0->general_int_mask);
1847 temp64 &= ~((u64) val64);
1848 writeq(temp64, &bar0->general_int_mask);
1849 /* writing 0 Enables all 8 RX interrupt levels */
1850 writeq(0x0, &bar0->rx_traffic_mask);
1851 } else if (flag == DISABLE_INTRS) {
20346722
K		 1852 /*
1853 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 1854 * register.
1855 */
1856 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1857 temp64 = readq(&bar0->general_int_mask);
1858 val64 |= temp64;
1859 writeq(val64, &bar0->general_int_mask);
1860 }
1861 }
1862}
1863
19a60522
SS		 1864/**
1865 * verify_pcc_quiescent- Checks for PCC quiescent state
1866 * Return: 1 If PCC is quiescence
1867 * 0 If PCC is not quiescence
1868 */
1ee6dd77 1869static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 1870{
19a60522 1871 int ret = 0, herc;
1ee6dd77 1872 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 1873 u64 val64 = readq(&bar0->adapter_status);
1874
1875 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722
K		 1876
1877 if (flag == FALSE) {
44c10138 1878 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 1879 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 1880 ret = 1;
19a60522
SS		 1881 } else {
1882 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 1883 ret = 1;
20346722
K		 1884 }
1885 } else {
44c10138 1886 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 1887 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 1888 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 1889 ret = 1;
5e25b9dd
K		 1890 } else {
1891 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 1892 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 1893 ret = 1;
20346722
K		 1894 }
1895 }
1896
1897 return ret;
1898}
1899/**
1900 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 1901 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 1902 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 1903 * differs and the calling function passes the input argument flag to
1904 * indicate this.
20346722 1905 * Return: 1 If xena is quiescence
1da177e4
LT		 1906 * 0 If Xena is not quiescence
1907 */
1908
1ee6dd77 1909static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 1910{
19a60522 1911 int mode;
1ee6dd77 1912 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 1913 u64 val64 = readq(&bar0->adapter_status);
1914 mode = s2io_verify_pci_mode(sp);
1da177e4 1915
19a60522
SS		 1916 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
1917 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
1918 return 0;
1919 }
1920 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
1921 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
1922 return 0;
1923 }
1924 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
1925 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
1926 return 0;
1927 }
1928 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
1929 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
1930 return 0;
1931 }
1932 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
1933 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
1934 return 0;
1935 }
1936 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
1937 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
1938 return 0;
1939 }
1940 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
1941 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
1942 return 0;
1943 }
1944 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
1945 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
1946 return 0;
1da177e4
LT		 1947 }
1948
19a60522
SS		 1949 /*
1950 * In PCI 33 mode, the P_PLL is not used, and therefore,
1951 * the the P_PLL_LOCK bit in the adapter_status register will
1952 * not be asserted.
1953 */
1954 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
1955 sp->device_type == XFRAME_II_DEVICE && mode !=
1956 PCI_MODE_PCI_33) {
1957 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
1958 return 0;
1959 }
1960 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1961 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1962 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
1963 return 0;
1964 }
1965 return 1;
1da177e4
LT		 1966}
1967
1968/**
1969 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
1970 * @sp: Pointer to device specifc structure
20346722 1971 * Description :
1da177e4
LT		 1972 * New procedure to clear mac address reading problems on Alpha platforms
1973 *
1974 */
1975
1ee6dd77 1976static void fix_mac_address(struct s2io_nic * sp)
1da177e4 1977{
1ee6dd77 1978 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 1979 u64 val64;
1980 int i = 0;
1981
1982 while (fix_mac[i] != END_SIGN) {
1983 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 1984 udelay(10);
1da177e4
LT		 1985 val64 = readq(&bar0->gpio_control);
1986 }
1987}
1988
1989/**
20346722 1990 * start_nic - Turns the device on
1da177e4 1991 * @nic : device private variable.
20346722
K		 1992 * Description:
1993 * This function actually turns the device on. Before this function is
1994 * called,all Registers are configured from their reset states
1995 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 1996 * calling this function, the device interrupts are cleared and the NIC is
1997 * literally switched on by writing into the adapter control register.
20346722 1998 * Return Value:
1da177e4
LT		 1999 * SUCCESS on success and -1 on failure.
2000 */
2001
2002static int start_nic(struct s2io_nic *nic)
2003{
1ee6dd77 2004 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2005 struct net_device *dev = nic->dev;
2006 register u64 val64 = 0;
20346722 2007 u16 subid, i;
1ee6dd77 2008 struct mac_info *mac_control;
1da177e4
LT		 2009 struct config_param *config;
2010
2011 mac_control = &nic->mac_control;
2012 config = &nic->config;
2013
2014 /* PRC Initialization and configuration */
2015 for (i = 0; i < config->rx_ring_num; i++) {
20346722 2016 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1da177e4
LT		 2017 &bar0->prc_rxd0_n[i]);
2018
2019 val64 = readq(&bar0->prc_ctrl_n[i]);
b6e3f982
K		 2020 if (nic->config.bimodal)
2021 val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
da6971d8
AR		 2022 if (nic->rxd_mode == RXD_MODE_1)
2023 val64 |= PRC_CTRL_RC_ENABLED;
2024 else
2025 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2026 if (nic->device_type == XFRAME_II_DEVICE)
2027 val64 |= PRC_CTRL_GROUP_READS;
2028 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2029 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2030 writeq(val64, &bar0->prc_ctrl_n[i]);
2031 }
2032
da6971d8
AR		 2033 if (nic->rxd_mode == RXD_MODE_3B) {
2034 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2035 val64 = readq(&bar0->rx_pa_cfg);
2036 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2037 writeq(val64, &bar0->rx_pa_cfg);
2038 }
1da177e4 2039
926930b2
SS		 2040 if (vlan_tag_strip == 0) {
2041 val64 = readq(&bar0->rx_pa_cfg);
2042 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2043 writeq(val64, &bar0->rx_pa_cfg);
2044 vlan_strip_flag = 0;
2045 }
2046
20346722 2047 /*
1da177e4
LT		 2048 * Enabling MC-RLDRAM. After enabling the device, we timeout
2049 * for around 100ms, which is approximately the time required
2050 * for the device to be ready for operation.
2051 */
2052 val64 = readq(&bar0->mc_rldram_mrs);
2053 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2054 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2055 val64 = readq(&bar0->mc_rldram_mrs);
2056
20346722 2057 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2058
2059 /* Enabling ECC Protection. */
2060 val64 = readq(&bar0->adapter_control);
2061 val64 &= ~ADAPTER_ECC_EN;
2062 writeq(val64, &bar0->adapter_control);
2063
20346722
K		 2064 /*
2065 * Clearing any possible Link state change interrupts that
1da177e4
LT		 2066 * could have popped up just before Enabling the card.
2067 */
2068 val64 = readq(&bar0->mac_rmac_err_reg);
2069 if (val64)
2070 writeq(val64, &bar0->mac_rmac_err_reg);
2071
20346722
K		 2072 /*
2073 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2074 * it.
2075 */
2076 val64 = readq(&bar0->adapter_status);
19a60522 2077 if (!verify_xena_quiescence(nic)) {
1da177e4
LT		 2078 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2079 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2080 (unsigned long long) val64);
2081 return FAILURE;
2082 }
2083
20346722 2084 /*
1da177e4 2085 * With some switches, link might be already up at this point.
20346722
K		 2086 * Because of this weird behavior, when we enable laser,
2087 * we may not get link. We need to handle this. We cannot
2088 * figure out which switch is misbehaving. So we are forced to
2089 * make a global change.
1da177e4
LT		 2090 */
2091
2092 /* Enabling Laser. */
2093 val64 = readq(&bar0->adapter_control);
2094 val64 |= ADAPTER_EOI_TX_ON;
2095 writeq(val64, &bar0->adapter_control);
2096
c92ca04b
AR		 2097 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2098 /*
2099 * Dont see link state interrupts initally on some switches,
2100 * so directly scheduling the link state task here.
2101 */
2102 schedule_work(&nic->set_link_task);
2103 }
1da177e4
LT		 2104 /* SXE-002: Initialize link and activity LED */
2105 subid = nic->pdev->subsystem_device;
541ae68f
K		 2106 if (((subid & 0xFF) >= 0x07) &&
2107 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2108 val64 = readq(&bar0->gpio_control);
2109 val64 |= 0x0000800000000000ULL;
2110 writeq(val64, &bar0->gpio_control);
2111 val64 = 0x0411040400000000ULL;
509a2671 2112 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2113 }
2114
1da177e4
LT		 2115 return SUCCESS;
2116}
fed5eccd
AR		 2117/**
2118 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2119 */
1ee6dd77
RB		 2120static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2121 TxD *txdlp, int get_off)
fed5eccd 2122{
1ee6dd77 2123 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2124 struct sk_buff *skb;
1ee6dd77 2125 struct TxD *txds;
fed5eccd
AR		 2126 u16 j, frg_cnt;
2127
2128 txds = txdlp;
26b7625c 2129 if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
fed5eccd
AR		 2130 pci_unmap_single(nic->pdev, (dma_addr_t)
2131 txds->Buffer_Pointer, sizeof(u64),
2132 PCI_DMA_TODEVICE);
2133 txds++;
2134 }
2135
2136 skb = (struct sk_buff *) ((unsigned long)
2137 txds->Host_Control);
2138 if (!skb) {
1ee6dd77 2139 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2140 return NULL;
2141 }
2142 pci_unmap_single(nic->pdev, (dma_addr_t)
2143 txds->Buffer_Pointer,
2144 skb->len - skb->data_len,
2145 PCI_DMA_TODEVICE);
2146 frg_cnt = skb_shinfo(skb)->nr_frags;
2147 if (frg_cnt) {
2148 txds++;
2149 for (j = 0; j < frg_cnt; j++, txds++) {
2150 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2151 if (!txds->Buffer_Pointer)
2152 break;
6aa20a22 2153 pci_unmap_page(nic->pdev, (dma_addr_t)
fed5eccd
AR		 2154 txds->Buffer_Pointer,
2155 frag->size, PCI_DMA_TODEVICE);
2156 }
2157 }
1ee6dd77 2158 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2159 return(skb);
2160}
1da177e4 2161
20346722
K		 2162/**
2163 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2164 * @nic : device private variable.
20346722 2165 * Description:
1da177e4 2166 * Free all queued Tx buffers.
20346722 2167 * Return Value: void
1da177e4
LT		 2168*/
2169
2170static void free_tx_buffers(struct s2io_nic *nic)
2171{
2172 struct net_device *dev = nic->dev;
2173 struct sk_buff *skb;
1ee6dd77 2174 struct TxD *txdp;
1da177e4 2175 int i, j;
1ee6dd77 2176 struct mac_info *mac_control;
1da177e4 2177 struct config_param *config;
fed5eccd 2178 int cnt = 0;
1da177e4
LT		 2179
2180 mac_control = &nic->mac_control;
2181 config = &nic->config;
2182
2183 for (i = 0; i < config->tx_fifo_num; i++) {
2184 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
491976b2
SH		 2185 txdp = (struct TxD *) \
2186 mac_control->fifos[i].list_info[j].list_virt_addr;
fed5eccd
AR		 2187 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2188 if (skb) {
491976b2
SH		 2189 nic->mac_control.stats_info->sw_stat.mem_freed
2190 += skb->truesize;
fed5eccd
AR		 2191 dev_kfree_skb(skb);
2192 cnt++;
1da177e4 2193 }
1da177e4
LT		 2194 }
2195 DBG_PRINT(INTR_DBG,
2196 "%s:forcibly freeing %d skbs on FIFO%d\n",
2197 dev->name, cnt, i);
20346722
K		 2198 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2199 mac_control->fifos[i].tx_curr_put_info.offset = 0;
1da177e4
LT		 2200 }
2201}
2202
20346722
K		 2203/**
2204 * stop_nic - To stop the nic
1da177e4 2205 * @nic ; device private variable.
20346722
K		 2206 * Description:
2207 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2208 * function does. This function is called to stop the device.
2209 * Return Value:
2210 * void.
2211 */
2212
2213static void stop_nic(struct s2io_nic *nic)
2214{
1ee6dd77 2215 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2216 register u64 val64 = 0;
5d3213cc 2217 u16 interruptible;
1ee6dd77 2218 struct mac_info *mac_control;
1da177e4
LT		 2219 struct config_param *config;
2220
2221 mac_control = &nic->mac_control;
2222 config = &nic->config;
2223
2224 /* Disable all interrupts */
e960fc5c 2225 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
a371a07d
K		 2226 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2227 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
1da177e4
LT		 2228 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2229
5d3213cc
AR		 2230 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2231 val64 = readq(&bar0->adapter_control);
2232 val64 &= ~(ADAPTER_CNTL_EN);
2233 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2234}
2235
1ee6dd77
RB		 2236static int fill_rxd_3buf(struct s2io_nic *nic, struct RxD_t *rxdp, struct \
2237 sk_buff *skb)
da6971d8
AR		 2238{
2239 struct net_device *dev = nic->dev;
2240 struct sk_buff *frag_list;
50eb8006 2241 void *tmp;
da6971d8
AR		 2242
2243 /* Buffer-1 receives L3/L4 headers */
1ee6dd77 2244 ((struct RxD3*)rxdp)->Buffer1_ptr = pci_map_single
da6971d8
AR		 2245 (nic->pdev, skb->data, l3l4hdr_size + 4,
2246 PCI_DMA_FROMDEVICE);
2247
2248 /* skb_shinfo(skb)->frag_list will have L4 data payload */
2249 skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2250 if (skb_shinfo(skb)->frag_list == NULL) {
c53d4945 2251 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
0c61ed5f 2252 DBG_PRINT(INFO_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
da6971d8
AR		 2253 return -ENOMEM ;
2254 }
2255 frag_list = skb_shinfo(skb)->frag_list;
372cc597 2256 skb->truesize += frag_list->truesize;
491976b2
SH		 2257 nic->mac_control.stats_info->sw_stat.mem_allocated
2258 += frag_list->truesize;
da6971d8 2259 frag_list->next = NULL;
50eb8006
JG		 2260 tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2261 frag_list->data = tmp;
27a884dc 2262 skb_reset_tail_pointer(frag_list);
da6971d8
AR		 2263
2264 /* Buffer-2 receives L4 data payload */
1ee6dd77 2265 ((struct RxD3*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
da6971d8
AR		 2266 frag_list->data, dev->mtu,
2267 PCI_DMA_FROMDEVICE);
2268 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2269 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2270
2271 return SUCCESS;
2272}
2273
20346722
K		 2274/**
2275 * fill_rx_buffers - Allocates the Rx side skbs
1da177e4 2276 * @nic: device private variable
20346722
K		 2277 * @ring_no: ring number
2278 * Description:
1da177e4
LT		 2279 * The function allocates Rx side skbs and puts the physical
2280 * address of these buffers into the RxD buffer pointers, so that the NIC
2281 * can DMA the received frame into these locations.
2282 * The NIC supports 3 receive modes, viz
2283 * 1. single buffer,
2284 * 2. three buffer and
2285 * 3. Five buffer modes.
20346722
K		 2286 * Each mode defines how many fragments the received frame will be split
2287 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2288 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2289 * is split into 3 fragments. As of now only single buffer mode is
2290 * supported.
2291 * Return Value:
2292 * SUCCESS on success or an appropriate -ve value on failure.
2293 */
2294
ac1f60db 2295static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1da177e4
LT		 2296{
2297 struct net_device *dev = nic->dev;
2298 struct sk_buff *skb;
1ee6dd77 2299 struct RxD_t *rxdp;
1da177e4 2300 int off, off1, size, block_no, block_no1;
1da177e4 2301 u32 alloc_tab = 0;
20346722 2302 u32 alloc_cnt;
1ee6dd77 2303 struct mac_info *mac_control;
1da177e4 2304 struct config_param *config;
20346722 2305 u64 tmp;
1ee6dd77 2306 struct buffAdd *ba;
1da177e4 2307 unsigned long flags;
1ee6dd77 2308 struct RxD_t *first_rxdp = NULL;
363dc367 2309 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
1da177e4
LT		 2310
2311 mac_control = &nic->mac_control;
2312 config = &nic->config;
20346722
K		 2313 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2314 atomic_read(&nic->rx_bufs_left[ring_no]);
1da177e4 2315
5d3213cc 2316 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
863c11a9 2317 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
1da177e4 2318 while (alloc_tab < alloc_cnt) {
20346722 2319 block_no = mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2320 block_index;
20346722 2321 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
1da177e4 2322
da6971d8
AR		 2323 rxdp = mac_control->rings[ring_no].
2324 rx_blocks[block_no].rxds[off].virt_addr;
2325
2326 if ((block_no == block_no1) && (off == off1) &&
2327 (rxdp->Host_Control)) {
2328 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2329 dev->name);
1da177e4
LT		 2330 DBG_PRINT(INTR_DBG, " info equated\n");
2331 goto end;
2332 }
da6971d8 2333 if (off && (off == rxd_count[nic->rxd_mode])) {
20346722 2334 mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2335 block_index++;
da6971d8
AR		 2336 if (mac_control->rings[ring_no].rx_curr_put_info.
2337 block_index == mac_control->rings[ring_no].
2338 block_count)
2339 mac_control->rings[ring_no].rx_curr_put_info.
2340 block_index = 0;
2341 block_no = mac_control->rings[ring_no].
2342 rx_curr_put_info.block_index;
2343 if (off == rxd_count[nic->rxd_mode])
2344 off = 0;
20346722 2345 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8
AR		 2346 offset = off;
2347 rxdp = mac_control->rings[ring_no].
2348 rx_blocks[block_no].block_virt_addr;
1da177e4
LT		 2349 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2350 dev->name, rxdp);
2351 }
db874e65
SS		 2352 if(!napi) {
2353 spin_lock_irqsave(&nic->put_lock, flags);
2354 mac_control->rings[ring_no].put_pos =
2355 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2356 spin_unlock_irqrestore(&nic->put_lock, flags);
2357 } else {
2358 mac_control->rings[ring_no].put_pos =
2359 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2360 }
da6971d8
AR		 2361 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2362 ((nic->rxd_mode >= RXD_MODE_3A) &&
2363 (rxdp->Control_2 & BIT(0)))) {
20346722 2364 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8 2365 offset = off;
1da177e4
LT		 2366 goto end;
2367 }
da6971d8
AR		 2368 /* calculate size of skb based on ring mode */
2369 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2370 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2371 if (nic->rxd_mode == RXD_MODE_1)
2372 size += NET_IP_ALIGN;
2373 else if (nic->rxd_mode == RXD_MODE_3B)
2374 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2375 else
2376 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2377
da6971d8
AR		 2378 /* allocate skb */
2379 skb = dev_alloc_skb(size);
2380 if(!skb) {
0c61ed5f
RV		 2381 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
2382 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
303bcb4b
K		 2383 if (first_rxdp) {
2384 wmb();
2385 first_rxdp->Control_1 |= RXD_OWN_XENA;
2386 }
c53d4945
SH		 2387 nic->mac_control.stats_info->sw_stat. \
2388 mem_alloc_fail_cnt++;
da6971d8
AR		 2389 return -ENOMEM ;
2390 }
491976b2
SH		 2391 nic->mac_control.stats_info->sw_stat.mem_allocated
2392 += skb->truesize;
da6971d8
AR		 2393 if (nic->rxd_mode == RXD_MODE_1) {
2394 /* 1 buffer mode - normal operation mode */
1ee6dd77 2395 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2396 skb_reserve(skb, NET_IP_ALIGN);
1ee6dd77 2397 ((struct RxD1*)rxdp)->Buffer0_ptr = pci_map_single
863c11a9
AR		 2398 (nic->pdev, skb->data, size - NET_IP_ALIGN,
2399 PCI_DMA_FROMDEVICE);
491976b2
SH		 2400 rxdp->Control_2 =
2401 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
da6971d8
AR		 2402
2403 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2404 /*
2405 * 2 or 3 buffer mode -
2406 * Both 2 buffer mode and 3 buffer mode provides 128
2407 * byte aligned receive buffers.
2408 *
2409 * 3 buffer mode provides header separation where in
2410 * skb->data will have L3/L4 headers where as
2411 * skb_shinfo(skb)->frag_list will have the L4 data
2412 * payload
2413 */
2414
491976b2 2415 /* save buffer pointers to avoid frequent dma mapping */
363dc367
RV		 2416 Buffer0_ptr = ((struct RxD3*)rxdp)->Buffer0_ptr;
2417 Buffer1_ptr = ((struct RxD3*)rxdp)->Buffer1_ptr;
1ee6dd77 2418 memset(rxdp, 0, sizeof(struct RxD3));
363dc367
RV		 2419 /* restore the buffer pointers for dma sync*/
2420 ((struct RxD3*)rxdp)->Buffer0_ptr = Buffer0_ptr;
2421 ((struct RxD3*)rxdp)->Buffer1_ptr = Buffer1_ptr;
2422
da6971d8
AR		 2423 ba = &mac_control->rings[ring_no].ba[block_no][off];
2424 skb_reserve(skb, BUF0_LEN);
2425 tmp = (u64)(unsigned long) skb->data;
2426 tmp += ALIGN_SIZE;
2427 tmp &= ~ALIGN_SIZE;
2428 skb->data = (void *) (unsigned long)tmp;
27a884dc 2429 skb_reset_tail_pointer(skb);
da6971d8 2430
1ee6dd77
RB		 2431 if (!(((struct RxD3*)rxdp)->Buffer0_ptr))
2432 ((struct RxD3*)rxdp)->Buffer0_ptr =
75c30b13 2433 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
da6971d8 2434 PCI_DMA_FROMDEVICE);
75c30b13
AR		 2435 else
2436 pci_dma_sync_single_for_device(nic->pdev,
491976b2 2437 (dma_addr_t) ((struct RxD3*)rxdp)->Buffer0_ptr,
75c30b13 2438 BUF0_LEN, PCI_DMA_FROMDEVICE);
da6971d8
AR		 2439 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2440 if (nic->rxd_mode == RXD_MODE_3B) {
2441 /* Two buffer mode */
2442
2443 /*
6aa20a22 2444 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2445 * L4 payload
2446 */
1ee6dd77 2447 ((struct RxD3*)rxdp)->Buffer2_ptr = pci_map_single
da6971d8
AR		 2448 (nic->pdev, skb->data, dev->mtu + 4,
2449 PCI_DMA_FROMDEVICE);
2450
75c30b13 2451 /* Buffer-1 will be dummy buffer. Not used */
1ee6dd77
RB		 2452 if (!(((struct RxD3*)rxdp)->Buffer1_ptr)) {
2453 ((struct RxD3*)rxdp)->Buffer1_ptr =
6aa20a22 2454 pci_map_single(nic->pdev,
75c30b13
AR		 2455 ba->ba_1, BUF1_LEN,
2456 PCI_DMA_FROMDEVICE);
2457 }
da6971d8
AR		 2458 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2459 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2460 (dev->mtu + 4);
2461 } else {
2462 /* 3 buffer mode */
2463 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
491976b2
SH		 2464 nic->mac_control.stats_info->sw_stat.\
2465 mem_freed += skb->truesize;
da6971d8
AR		 2466 dev_kfree_skb_irq(skb);
2467 if (first_rxdp) {
2468 wmb();
2469 first_rxdp->Control_1 |=
2470 RXD_OWN_XENA;
2471 }
2472 return -ENOMEM ;
2473 }
2474 }
2475 rxdp->Control_2 |= BIT(0);
1da177e4 2476 }
1da177e4 2477 rxdp->Host_Control = (unsigned long) (skb);
303bcb4b
K		 2478 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2479 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2480 off++;
da6971d8
AR		 2481 if (off == (rxd_count[nic->rxd_mode] + 1))
2482 off = 0;
20346722 2483 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
20346722 2484
da6971d8 2485 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b
K		 2486 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2487 if (first_rxdp) {
2488 wmb();
2489 first_rxdp->Control_1 |= RXD_OWN_XENA;
2490 }
2491 first_rxdp = rxdp;
2492 }
1da177e4
LT		 2493 atomic_inc(&nic->rx_bufs_left[ring_no]);
2494 alloc_tab++;
2495 }
2496
2497 end:
303bcb4b
K		 2498 /* Transfer ownership of first descriptor to adapter just before
2499 * exiting. Before that, use memory barrier so that ownership
2500 * and other fields are seen by adapter correctly.
2501 */
2502 if (first_rxdp) {
2503 wmb();
2504 first_rxdp->Control_1 |= RXD_OWN_XENA;
2505 }
2506
1da177e4
LT		 2507 return SUCCESS;
2508}
2509
da6971d8
AR		 2510static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2511{
2512 struct net_device *dev = sp->dev;
2513 int j;
2514 struct sk_buff *skb;
1ee6dd77
RB		 2515 struct RxD_t *rxdp;
2516 struct mac_info *mac_control;
2517 struct buffAdd *ba;
da6971d8
AR		 2518
2519 mac_control = &sp->mac_control;
2520 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2521 rxdp = mac_control->rings[ring_no].
2522 rx_blocks[blk].rxds[j].virt_addr;
2523 skb = (struct sk_buff *)
2524 ((unsigned long) rxdp->Host_Control);
2525 if (!skb) {
2526 continue;
2527 }
2528 if (sp->rxd_mode == RXD_MODE_1) {
2529 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2530 ((struct RxD1*)rxdp)->Buffer0_ptr,
da6971d8
AR		 2531 dev->mtu +
2532 HEADER_ETHERNET_II_802_3_SIZE
2533 + HEADER_802_2_SIZE +
2534 HEADER_SNAP_SIZE,
2535 PCI_DMA_FROMDEVICE);
1ee6dd77 2536 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8
AR		 2537 } else if(sp->rxd_mode == RXD_MODE_3B) {
2538 ba = &mac_control->rings[ring_no].
2539 ba[blk][j];
2540 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2541 ((struct RxD3*)rxdp)->Buffer0_ptr,
da6971d8
AR		 2542 BUF0_LEN,
2543 PCI_DMA_FROMDEVICE);
2544 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2545 ((struct RxD3*)rxdp)->Buffer1_ptr,
da6971d8
AR		 2546 BUF1_LEN,
2547 PCI_DMA_FROMDEVICE);
2548 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2549 ((struct RxD3*)rxdp)->Buffer2_ptr,
da6971d8
AR		 2550 dev->mtu + 4,
2551 PCI_DMA_FROMDEVICE);
1ee6dd77 2552 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8
AR		 2553 } else {
2554 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2555 ((struct RxD3*)rxdp)->Buffer0_ptr, BUF0_LEN,
da6971d8
AR		 2556 PCI_DMA_FROMDEVICE);
2557 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2558 ((struct RxD3*)rxdp)->Buffer1_ptr,
da6971d8
AR		 2559 l3l4hdr_size + 4,
2560 PCI_DMA_FROMDEVICE);
2561 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2562 ((struct RxD3*)rxdp)->Buffer2_ptr, dev->mtu,
da6971d8 2563 PCI_DMA_FROMDEVICE);
1ee6dd77 2564 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2565 }
491976b2 2566 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
da6971d8
AR		 2567 dev_kfree_skb(skb);
2568 atomic_dec(&sp->rx_bufs_left[ring_no]);
2569 }
2570}
2571
1da177e4 2572/**
20346722 2573 * free_rx_buffers - Frees all Rx buffers
1da177e4 2574 * @sp: device private variable.
20346722 2575 * Description:
1da177e4
LT		 2576 * This function will free all Rx buffers allocated by host.
2577 * Return Value:
2578 * NONE.
2579 */
2580
2581static void free_rx_buffers(struct s2io_nic *sp)
2582{
2583 struct net_device *dev = sp->dev;
da6971d8 2584 int i, blk = 0, buf_cnt = 0;
1ee6dd77 2585 struct mac_info *mac_control;
1da177e4 2586 struct config_param *config;
1da177e4
LT		 2587
2588 mac_control = &sp->mac_control;
2589 config = &sp->config;
2590
2591 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 2592 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2593 free_rxd_blk(sp,i,blk);
1da177e4 2594
20346722
K		 2595 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2596 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2597 mac_control->rings[i].rx_curr_put_info.offset = 0;
2598 mac_control->rings[i].rx_curr_get_info.offset = 0;
1da177e4
LT		 2599 atomic_set(&sp->rx_bufs_left[i], 0);
2600 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2601 dev->name, buf_cnt, i);
2602 }
2603}
2604
2605/**
2606 * s2io_poll - Rx interrupt handler for NAPI support
2607 * @dev : pointer to the device structure.
20346722 2608 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2609 * during one pass through the 'Poll" function.
2610 * Description:
2611 * Comes into picture only if NAPI support has been incorporated. It does
2612 * the same thing that rx_intr_handler does, but not in a interrupt context
2613 * also It will process only a given number of packets.
2614 * Return value:
2615 * 0 on success and 1 if there are No Rx packets to be processed.
2616 */
2617
1da177e4
LT		 2618static int s2io_poll(struct net_device *dev, int *budget)
2619{
1ee6dd77 2620 struct s2io_nic *nic = dev->priv;
20346722 2621 int pkt_cnt = 0, org_pkts_to_process;
1ee6dd77 2622 struct mac_info *mac_control;
1da177e4 2623 struct config_param *config;
1ee6dd77 2624 struct XENA_dev_config __iomem *bar0 = nic->bar0;
20346722 2625 int i;
1da177e4 2626
7ba013ac 2627 atomic_inc(&nic->isr_cnt);
1da177e4
LT		 2628 mac_control = &nic->mac_control;
2629 config = &nic->config;
2630
20346722
K		 2631 nic->pkts_to_process = *budget;
2632 if (nic->pkts_to_process > dev->quota)
2633 nic->pkts_to_process = dev->quota;
2634 org_pkts_to_process = nic->pkts_to_process;
1da177e4 2635
19a60522
SS		 2636 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2637 readl(&bar0->rx_traffic_int);
1da177e4
LT		 2638
2639 for (i = 0; i < config->rx_ring_num; i++) {
20346722
K		 2640 rx_intr_handler(&mac_control->rings[i]);
2641 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2642 if (!nic->pkts_to_process) {
2643 /* Quota for the current iteration has been met */
2644 goto no_rx;
1da177e4 2645 }
1da177e4
LT		 2646 }
2647 if (!pkt_cnt)
2648 pkt_cnt = 1;
2649
2650 dev->quota -= pkt_cnt;
2651 *budget -= pkt_cnt;
2652 netif_rx_complete(dev);
2653
2654 for (i = 0; i < config->rx_ring_num; i++) {
2655 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2656 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2657 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
1da177e4
LT		 2658 break;
2659 }
2660 }
2661 /* Re enable the Rx interrupts. */
c92ca04b 2662 writeq(0x0, &bar0->rx_traffic_mask);
19a60522 2663 readl(&bar0->rx_traffic_mask);
7ba013ac 2664 atomic_dec(&nic->isr_cnt);
1da177e4
LT		 2665 return 0;
2666
20346722 2667no_rx:
1da177e4
LT		 2668 dev->quota -= pkt_cnt;
2669 *budget -= pkt_cnt;
2670
2671 for (i = 0; i < config->rx_ring_num; i++) {
2672 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2673 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2674 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
1da177e4
LT		 2675 break;
2676 }
2677 }
7ba013ac 2678 atomic_dec(&nic->isr_cnt);
1da177e4
LT		 2679 return 1;
2680}
20346722 2681
b41477f3 2682#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2683/**
b41477f3 2684 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2685 * @dev : pointer to the device structure.
2686 * Description:
b41477f3
AR		 2687 * This function will be called by upper layer to check for events on the
2688 * interface in situations where interrupts are disabled. It is used for
2689 * specific in-kernel networking tasks, such as remote consoles and kernel
2690 * debugging over the network (example netdump in RedHat).
612eff0e 2691 */
612eff0e
BH		 2692static void s2io_netpoll(struct net_device *dev)
2693{
1ee6dd77
RB		 2694 struct s2io_nic *nic = dev->priv;
2695 struct mac_info *mac_control;
612eff0e 2696 struct config_param *config;
1ee6dd77 2697 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2698 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e
BH		 2699 int i;
2700
d796fdb7
LV		 2701 if (pci_channel_offline(nic->pdev))
2702 return;
2703
612eff0e
BH		 2704 disable_irq(dev->irq);
2705
2706 atomic_inc(&nic->isr_cnt);
2707 mac_control = &nic->mac_control;
2708 config = &nic->config;
2709
612eff0e 2710 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2711 writeq(val64, &bar0->tx_traffic_int);
2712
6aa20a22 2713 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2714 * run out of skbs and will fail and eventually netpoll application such
2715 * as netdump will fail.
2716 */
2717 for (i = 0; i < config->tx_fifo_num; i++)
2718 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2719
b41477f3 2720 /* check for received packet and indicate up to network */
612eff0e
BH		 2721 for (i = 0; i < config->rx_ring_num; i++)
2722 rx_intr_handler(&mac_control->rings[i]);
2723
2724 for (i = 0; i < config->rx_ring_num; i++) {
2725 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2726 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2727 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
612eff0e
BH		 2728 break;
2729 }
2730 }
2731 atomic_dec(&nic->isr_cnt);
2732 enable_irq(dev->irq);
2733 return;
2734}
2735#endif
2736
20346722 2737/**
1da177e4
LT		 2738 * rx_intr_handler - Rx interrupt handler
2739 * @nic: device private variable.
20346722
K		 2740 * Description:
2741 * If the interrupt is because of a received frame or if the
1da177e4 2742 * receive ring contains fresh as yet un-processed frames,this function is
20346722
K		 2743 * called. It picks out the RxD at which place the last Rx processing had
2744 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2745 * the offset.
2746 * Return Value:
2747 * NONE.
2748 */
1ee6dd77 2749static void rx_intr_handler(struct ring_info *ring_data)
1da177e4 2750{
1ee6dd77 2751 struct s2io_nic *nic = ring_data->nic;
1da177e4 2752 struct net_device *dev = (struct net_device *) nic->dev;
da6971d8 2753 int get_block, put_block, put_offset;
1ee6dd77
RB		 2754 struct rx_curr_get_info get_info, put_info;
2755 struct RxD_t *rxdp;
1da177e4 2756 struct sk_buff *skb;
20346722 2757 int pkt_cnt = 0;
7d3d0439
RA		 2758 int i;
2759
7ba013ac
K		 2760 spin_lock(&nic->rx_lock);
2761 if (atomic_read(&nic->card_state) == CARD_DOWN) {
776bd20f 2762 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
7ba013ac
K		 2763 __FUNCTION__, dev->name);
2764 spin_unlock(&nic->rx_lock);
776bd20f 2765 return;
7ba013ac
K		 2766 }
2767
20346722
K		 2768 get_info = ring_data->rx_curr_get_info;
2769 get_block = get_info.block_index;
1ee6dd77 2770 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2771 put_block = put_info.block_index;
da6971d8 2772 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65
SS		 2773 if (!napi) {
2774 spin_lock(&nic->put_lock);
2775 put_offset = ring_data->put_pos;
2776 spin_unlock(&nic->put_lock);
2777 } else
2778 put_offset = ring_data->put_pos;
2779
da6971d8 2780 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2781 /*
2782 * If your are next to put index then it's
2783 * FIFO full condition
2784 */
da6971d8
AR		 2785 if ((get_block == put_block) &&
2786 (get_info.offset + 1) == put_info.offset) {
75c30b13 2787 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
da6971d8
AR		 2788 break;
2789 }
20346722
K		 2790 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2791 if (skb == NULL) {
2792 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2793 dev->name);
2794 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
7ba013ac 2795 spin_unlock(&nic->rx_lock);
20346722 2796 return;
1da177e4 2797 }
da6971d8
AR		 2798 if (nic->rxd_mode == RXD_MODE_1) {
2799 pci_unmap_single(nic->pdev, (dma_addr_t)
1ee6dd77 2800 ((struct RxD1*)rxdp)->Buffer0_ptr,
20346722
K		 2801 dev->mtu +
2802 HEADER_ETHERNET_II_802_3_SIZE +
2803 HEADER_802_2_SIZE +
2804 HEADER_SNAP_SIZE,
2805 PCI_DMA_FROMDEVICE);
da6971d8 2806 } else if (nic->rxd_mode == RXD_MODE_3B) {
75c30b13 2807 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
1ee6dd77 2808 ((struct RxD3*)rxdp)->Buffer0_ptr,
20346722 2809 BUF0_LEN, PCI_DMA_FROMDEVICE);
da6971d8 2810 pci_unmap_single(nic->pdev, (dma_addr_t)
1ee6dd77 2811 ((struct RxD3*)rxdp)->Buffer2_ptr,
da6971d8 2812 dev->mtu + 4,
20346722 2813 PCI_DMA_FROMDEVICE);
da6971d8 2814 } else {
75c30b13 2815 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
1ee6dd77 2816 ((struct RxD3*)rxdp)->Buffer0_ptr, BUF0_LEN,
da6971d8
AR		 2817 PCI_DMA_FROMDEVICE);
2818 pci_unmap_single(nic->pdev, (dma_addr_t)
1ee6dd77 2819 ((struct RxD3*)rxdp)->Buffer1_ptr,
da6971d8
AR		 2820 l3l4hdr_size + 4,
2821 PCI_DMA_FROMDEVICE);
2822 pci_unmap_single(nic->pdev, (dma_addr_t)
1ee6dd77 2823 ((struct RxD3*)rxdp)->Buffer2_ptr,
da6971d8
AR		 2824 dev->mtu, PCI_DMA_FROMDEVICE);
2825 }
863c11a9 2826 prefetch(skb->data);
20346722
K		 2827 rx_osm_handler(ring_data, rxdp);
2828 get_info.offset++;
da6971d8
AR		 2829 ring_data->rx_curr_get_info.offset = get_info.offset;
2830 rxdp = ring_data->rx_blocks[get_block].
2831 rxds[get_info.offset].virt_addr;
2832 if (get_info.offset == rxd_count[nic->rxd_mode]) {
20346722 2833 get_info.offset = 0;
da6971d8 2834 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 2835 get_block++;
da6971d8
AR		 2836 if (get_block == ring_data->block_count)
2837 get_block = 0;
2838 ring_data->rx_curr_get_info.block_index = get_block;
20346722
K		 2839 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2840 }
1da177e4 2841
20346722 2842 nic->pkts_to_process -= 1;
db874e65 2843 if ((napi) && (!nic->pkts_to_process))
20346722 2844 break;
20346722 2845 pkt_cnt++;
1da177e4
LT		 2846 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2847 break;
2848 }
7d3d0439
RA		 2849 if (nic->lro) {
2850 /* Clear all LRO sessions before exiting */
2851 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 2852 struct lro *lro = &nic->lro0_n[i];
7d3d0439
RA		 2853 if (lro->in_use) {
2854 update_L3L4_header(nic, lro);
2855 queue_rx_frame(lro->parent);
2856 clear_lro_session(lro);
2857 }
2858 }
2859 }
2860
7ba013ac 2861 spin_unlock(&nic->rx_lock);
1da177e4 2862}
20346722
K		 2863
2864/**
1da177e4
LT		 2865 * tx_intr_handler - Transmit interrupt handler
2866 * @nic : device private variable
20346722
K		 2867 * Description:
2868 * If an interrupt was raised to indicate DMA complete of the
2869 * Tx packet, this function is called. It identifies the last TxD
2870 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 2871 * DMA'ed into the NICs internal memory.
2872 * Return Value:
2873 * NONE
2874 */
2875
1ee6dd77 2876static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 2877{
1ee6dd77 2878 struct s2io_nic *nic = fifo_data->nic;
1da177e4 2879 struct net_device *dev = (struct net_device *) nic->dev;
1ee6dd77 2880 struct tx_curr_get_info get_info, put_info;
1da177e4 2881 struct sk_buff *skb;
1ee6dd77 2882 struct TxD *txdlp;
f9046eb3 2883 u8 err_mask;
1da177e4 2884
20346722 2885 get_info = fifo_data->tx_curr_get_info;
1ee6dd77
RB		 2886 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
2887 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
20346722
K		 2888 list_virt_addr;
2889 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2890 (get_info.offset != put_info.offset) &&
2891 (txdlp->Host_Control)) {
2892 /* Check for TxD errors */
2893 if (txdlp->Control_1 & TXD_T_CODE) {
2894 unsigned long long err;
2895 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0
AR		 2896 if (err & 0x1) {
2897 nic->mac_control.stats_info->sw_stat.
2898 parity_err_cnt++;
2899 }
491976b2
SH		 2900
2901 /* update t_code statistics */
f9046eb3
OH		 2902 err_mask = err >> 48;
2903 switch(err_mask) {
491976b2
SH		 2904 case 2:
2905 nic->mac_control.stats_info->sw_stat.
2906 tx_buf_abort_cnt++;
2907 break;
2908
2909 case 3:
2910 nic->mac_control.stats_info->sw_stat.
2911 tx_desc_abort_cnt++;
2912 break;
2913
2914 case 7:
2915 nic->mac_control.stats_info->sw_stat.
2916 tx_parity_err_cnt++;
2917 break;
2918
2919 case 10:
2920 nic->mac_control.stats_info->sw_stat.
2921 tx_link_loss_cnt++;
2922 break;
2923
2924 case 15:
2925 nic->mac_control.stats_info->sw_stat.
2926 tx_list_proc_err_cnt++;
2927 break;
2928 }
20346722 2929 }
1da177e4 2930
fed5eccd 2931 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722
K		 2932 if (skb == NULL) {
2933 DBG_PRINT(ERR_DBG, "%s: Null skb ",
2934 __FUNCTION__);
2935 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2936 return;
2937 }
2938
20346722 2939 /* Updating the statistics block */
20346722 2940 nic->stats.tx_bytes += skb->len;
491976b2 2941 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
20346722
K		 2942 dev_kfree_skb_irq(skb);
2943
2944 get_info.offset++;
863c11a9
AR		 2945 if (get_info.offset == get_info.fifo_len + 1)
2946 get_info.offset = 0;
1ee6dd77 2947 txdlp = (struct TxD *) fifo_data->list_info
20346722
K		 2948 [get_info.offset].list_virt_addr;
2949 fifo_data->tx_curr_get_info.offset =
2950 get_info.offset;
1da177e4
LT		 2951 }
2952
2953 spin_lock(&nic->tx_lock);
2954 if (netif_queue_stopped(dev))
2955 netif_wake_queue(dev);
2956 spin_unlock(&nic->tx_lock);
2957}
2958
bd1034f0
AR		 2959/**
2960 * s2io_mdio_write - Function to write in to MDIO registers
2961 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2962 * @addr : address value
2963 * @value : data value
2964 * @dev : pointer to net_device structure
2965 * Description:
2966 * This function is used to write values to the MDIO registers
2967 * NONE
2968 */
2969static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2970{
2971 u64 val64 = 0x0;
1ee6dd77
RB		 2972 struct s2io_nic *sp = dev->priv;
2973 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 2974
2975 //address transaction
2976 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2977 | MDIO_MMD_DEV_ADDR(mmd_type)
2978 | MDIO_MMS_PRT_ADDR(0x0);
2979 writeq(val64, &bar0->mdio_control);
2980 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2981 writeq(val64, &bar0->mdio_control);
2982 udelay(100);
2983
2984 //Data transaction
2985 val64 = 0x0;
2986 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2987 | MDIO_MMD_DEV_ADDR(mmd_type)
2988 | MDIO_MMS_PRT_ADDR(0x0)
2989 | MDIO_MDIO_DATA(value)
2990 | MDIO_OP(MDIO_OP_WRITE_TRANS);
2991 writeq(val64, &bar0->mdio_control);
2992 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2993 writeq(val64, &bar0->mdio_control);
2994 udelay(100);
2995
2996 val64 = 0x0;
2997 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2998 | MDIO_MMD_DEV_ADDR(mmd_type)
2999 | MDIO_MMS_PRT_ADDR(0x0)
3000 | MDIO_OP(MDIO_OP_READ_TRANS);
3001 writeq(val64, &bar0->mdio_control);
3002 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3003 writeq(val64, &bar0->mdio_control);
3004 udelay(100);
3005
3006}
3007
3008/**
3009 * s2io_mdio_read - Function to write in to MDIO registers
3010 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3011 * @addr : address value
3012 * @dev : pointer to net_device structure
3013 * Description:
3014 * This function is used to read values to the MDIO registers
3015 * NONE
3016 */
3017static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3018{
3019 u64 val64 = 0x0;
3020 u64 rval64 = 0x0;
1ee6dd77
RB		 3021 struct s2io_nic *sp = dev->priv;
3022 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3023
3024 /* address transaction */
3025 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3026 | MDIO_MMD_DEV_ADDR(mmd_type)
3027 | MDIO_MMS_PRT_ADDR(0x0);
3028 writeq(val64, &bar0->mdio_control);
3029 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3030 writeq(val64, &bar0->mdio_control);
3031 udelay(100);
3032
3033 /* Data transaction */
3034 val64 = 0x0;
3035 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3036 | MDIO_MMD_DEV_ADDR(mmd_type)
3037 | MDIO_MMS_PRT_ADDR(0x0)
3038 | MDIO_OP(MDIO_OP_READ_TRANS);
3039 writeq(val64, &bar0->mdio_control);
3040 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3041 writeq(val64, &bar0->mdio_control);
3042 udelay(100);
3043
3044 /* Read the value from regs */
3045 rval64 = readq(&bar0->mdio_control);
3046 rval64 = rval64 & 0xFFFF0000;
3047 rval64 = rval64 >> 16;
3048 return rval64;
3049}
3050/**
3051 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3052 * @counter : couter value to be updated
3053 * @flag : flag to indicate the status
3054 * @type : counter type
3055 * Description:
3056 * This function is to check the status of the xpak counters value
3057 * NONE
3058 */
3059
3060static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3061{
3062 u64 mask = 0x3;
3063 u64 val64;
3064 int i;
3065 for(i = 0; i <index; i++)
3066 mask = mask << 0x2;
3067
3068 if(flag > 0)
3069 {
3070 *counter = *counter + 1;
3071 val64 = *regs_stat & mask;
3072 val64 = val64 >> (index * 0x2);
3073 val64 = val64 + 1;
3074 if(val64 == 3)
3075 {
3076 switch(type)
3077 {
3078 case 1:
3079 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3080 "service. Excessive temperatures may "
3081 "result in premature transceiver "
3082 "failure \n");
3083 break;
3084 case 2:
3085 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3086 "service Excessive bias currents may "
3087 "indicate imminent laser diode "
3088 "failure \n");
3089 break;
3090 case 3:
3091 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3092 "service Excessive laser output "
3093 "power may saturate far-end "
3094 "receiver\n");
3095 break;
3096 default:
3097 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3098 "type \n");
3099 }
3100 val64 = 0x0;
3101 }
3102 val64 = val64 << (index * 0x2);
3103 *regs_stat = (*regs_stat & (~mask)) | (val64);
3104
3105 } else {
3106 *regs_stat = *regs_stat & (~mask);
3107 }
3108}
3109
3110/**
3111 * s2io_updt_xpak_counter - Function to update the xpak counters
3112 * @dev : pointer to net_device struct
3113 * Description:
3114 * This function is to upate the status of the xpak counters value
3115 * NONE
3116 */
3117static void s2io_updt_xpak_counter(struct net_device *dev)
3118{
3119 u16 flag = 0x0;
3120 u16 type = 0x0;
3121 u16 val16 = 0x0;
3122 u64 val64 = 0x0;
3123 u64 addr = 0x0;
3124
1ee6dd77
RB		 3125 struct s2io_nic *sp = dev->priv;
3126 struct stat_block *stat_info = sp->mac_control.stats_info;
bd1034f0
AR		 3127
3128 /* Check the communication with the MDIO slave */
3129 addr = 0x0000;
3130 val64 = 0x0;
3131 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3132 if((val64 == 0xFFFF) || (val64 == 0x0000))
3133 {
3134 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3135 "Returned %llx\n", (unsigned long long)val64);
3136 return;
3137 }
3138
3139 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3140 if(val64 != 0x2040)
3141 {
3142 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3143 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3144 (unsigned long long)val64);
3145 return;
3146 }
3147
3148 /* Loading the DOM register to MDIO register */
3149 addr = 0xA100;
3150 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3151 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3152
3153 /* Reading the Alarm flags */
3154 addr = 0xA070;
3155 val64 = 0x0;
3156 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3157
3158 flag = CHECKBIT(val64, 0x7);
3159 type = 1;
3160 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3161 &stat_info->xpak_stat.xpak_regs_stat,
3162 0x0, flag, type);
3163
3164 if(CHECKBIT(val64, 0x6))
3165 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3166
3167 flag = CHECKBIT(val64, 0x3);
3168 type = 2;
3169 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3170 &stat_info->xpak_stat.xpak_regs_stat,
3171 0x2, flag, type);
3172
3173 if(CHECKBIT(val64, 0x2))
3174 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3175
3176 flag = CHECKBIT(val64, 0x1);
3177 type = 3;
3178 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3179 &stat_info->xpak_stat.xpak_regs_stat,
3180 0x4, flag, type);
3181
3182 if(CHECKBIT(val64, 0x0))
3183 stat_info->xpak_stat.alarm_laser_output_power_low++;
3184
3185 /* Reading the Warning flags */
3186 addr = 0xA074;
3187 val64 = 0x0;
3188 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3189
3190 if(CHECKBIT(val64, 0x7))
3191 stat_info->xpak_stat.warn_transceiver_temp_high++;
3192
3193 if(CHECKBIT(val64, 0x6))
3194 stat_info->xpak_stat.warn_transceiver_temp_low++;
3195
3196 if(CHECKBIT(val64, 0x3))
3197 stat_info->xpak_stat.warn_laser_bias_current_high++;
3198
3199 if(CHECKBIT(val64, 0x2))
3200 stat_info->xpak_stat.warn_laser_bias_current_low++;
3201
3202 if(CHECKBIT(val64, 0x1))
3203 stat_info->xpak_stat.warn_laser_output_power_high++;
3204
3205 if(CHECKBIT(val64, 0x0))
3206 stat_info->xpak_stat.warn_laser_output_power_low++;
3207}
3208
20346722 3209/**
1da177e4
LT		 3210 * alarm_intr_handler - Alarm Interrrupt handler
3211 * @nic: device private variable
20346722 3212 * Description: If the interrupt was neither because of Rx packet or Tx
1da177e4 3213 * complete, this function is called. If the interrupt was to indicate
20346722
K		 3214 * a loss of link, the OSM link status handler is invoked for any other
3215 * alarm interrupt the block that raised the interrupt is displayed
1da177e4
LT		 3216 * and a H/W reset is issued.
3217 * Return Value:
3218 * NONE
3219*/
3220
3221static void alarm_intr_handler(struct s2io_nic *nic)
3222{
3223 struct net_device *dev = (struct net_device *) nic->dev;
1ee6dd77 3224 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 3225 register u64 val64 = 0, err_reg = 0;
bd1034f0
AR		 3226 u64 cnt;
3227 int i;
372cc597
SS		 3228 if (atomic_read(&nic->card_state) == CARD_DOWN)
3229 return;
d796fdb7
LV		 3230 if (pci_channel_offline(nic->pdev))
3231 return;
bd1034f0
AR		 3232 nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3233 /* Handling the XPAK counters update */
3234 if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3235 /* waiting for an hour */
3236 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3237 } else {
3238 s2io_updt_xpak_counter(dev);
3239 /* reset the count to zero */
3240 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3241 }
1da177e4
LT		 3242
3243 /* Handling link status change error Intr */
a371a07d
K		 3244 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3245 err_reg = readq(&bar0->mac_rmac_err_reg);
3246 writeq(err_reg, &bar0->mac_rmac_err_reg);
3247 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3248 schedule_work(&nic->set_link_task);
3249 }
1da177e4
LT		 3250 }
3251
5e25b9dd
K		 3252 /* Handling Ecc errors */
3253 val64 = readq(&bar0->mc_err_reg);
3254 writeq(val64, &bar0->mc_err_reg);
3255 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3256 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
7ba013ac
K		 3257 nic->mac_control.stats_info->sw_stat.
3258 double_ecc_errs++;
776bd20f 3259 DBG_PRINT(INIT_DBG, "%s: Device indicates ",
5e25b9dd 3260 dev->name);
776bd20f 3261 DBG_PRINT(INIT_DBG, "double ECC error!!\n");
e960fc5c 3262 if (nic->device_type != XFRAME_II_DEVICE) {
776bd20f 3263 /* Reset XframeI only if critical error */
3264 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3265 MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3266 netif_stop_queue(dev);
3267 schedule_work(&nic->rst_timer_task);
bd1034f0
AR		 3268 nic->mac_control.stats_info->sw_stat.
3269 soft_reset_cnt++;
776bd20f 3270 }
e960fc5c 3271 }
5e25b9dd 3272 } else {
7ba013ac
K		 3273 nic->mac_control.stats_info->sw_stat.
3274 single_ecc_errs++;
5e25b9dd
K		 3275 }
3276 }
3277
1da177e4
LT		 3278 /* In case of a serious error, the device will be Reset. */
3279 val64 = readq(&bar0->serr_source);
3280 if (val64 & SERR_SOURCE_ANY) {
bd1034f0 3281 nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
1da177e4 3282 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
6aa20a22 3283 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
776bd20f 3284 (unsigned long long)val64);
1da177e4
LT		 3285 netif_stop_queue(dev);
3286 schedule_work(&nic->rst_timer_task);
bd1034f0 3287 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 3288 }
3289
3290 /*
3291 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3292 * Error occurs, the adapter will be recycled by disabling the
20346722 3293 * adapter enable bit and enabling it again after the device
1da177e4
LT		 3294 * becomes Quiescent.
3295 */
3296 val64 = readq(&bar0->pcc_err_reg);
3297 writeq(val64, &bar0->pcc_err_reg);
3298 if (val64 & PCC_FB_ECC_DB_ERR) {
3299 u64 ac = readq(&bar0->adapter_control);
3300 ac &= ~(ADAPTER_CNTL_EN);
3301 writeq(ac, &bar0->adapter_control);
3302 ac = readq(&bar0->adapter_control);
3303 schedule_work(&nic->set_link_task);
3304 }
bd1034f0
AR		 3305 /* Check for data parity error */
3306 val64 = readq(&bar0->pic_int_status);
3307 if (val64 & PIC_INT_GPIO) {
3308 val64 = readq(&bar0->gpio_int_reg);
3309 if (val64 & GPIO_INT_REG_DP_ERR_INT) {
3310 nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
3311 schedule_work(&nic->rst_timer_task);
3312 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3313 }
3314 }
3315
3316 /* Check for ring full counter */
3317 if (nic->device_type & XFRAME_II_DEVICE) {
3318 val64 = readq(&bar0->ring_bump_counter1);
3319 for (i=0; i<4; i++) {
3320 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3321 cnt >>= 64 - ((i+1)*16);
3322 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3323 += cnt;
3324 }
3325
3326 val64 = readq(&bar0->ring_bump_counter2);
3327 for (i=0; i<4; i++) {
3328 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3329 cnt >>= 64 - ((i+1)*16);
3330 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3331 += cnt;
3332 }
3333 }
1da177e4
LT		 3334
3335 /* Other type of interrupts are not being handled now, TODO */
3336}
3337
20346722 3338/**
1da177e4 3339 * wait_for_cmd_complete - waits for a command to complete.
20346722 3340 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3341 * s2io_nic structure.
20346722
K		 3342 * Description: Function that waits for a command to Write into RMAC
3343 * ADDR DATA registers to be completed and returns either success or
3344 * error depending on whether the command was complete or not.
1da177e4
LT		 3345 * Return value:
3346 * SUCCESS on success and FAILURE on failure.
3347 */
3348
9fc93a41
SS		 3349static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3350 int bit_state)
1da177e4 3351{
9fc93a41 3352 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3353 u64 val64;
3354
9fc93a41
SS		 3355 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3356 return FAILURE;
3357
3358 do {
c92ca04b 3359 val64 = readq(addr);
9fc93a41
SS		 3360 if (bit_state == S2IO_BIT_RESET) {
3361 if (!(val64 & busy_bit)) {
3362 ret = SUCCESS;
3363 break;
3364 }
3365 } else {
3366 if (!(val64 & busy_bit)) {
3367 ret = SUCCESS;
3368 break;
3369 }
1da177e4 3370 }
c92ca04b
AR		 3371
3372 if(in_interrupt())
9fc93a41 3373 mdelay(delay);
c92ca04b 3374 else
9fc93a41 3375 msleep(delay);
c92ca04b 3376
9fc93a41
SS		 3377 if (++cnt >= 10)
3378 delay = 50;
3379 } while (cnt < 20);
1da177e4
LT		 3380 return ret;
3381}
19a60522
SS		 3382/*
3383 * check_pci_device_id - Checks if the device id is supported
3384 * @id : device id
3385 * Description: Function to check if the pci device id is supported by driver.
3386 * Return value: Actual device id if supported else PCI_ANY_ID
3387 */
3388static u16 check_pci_device_id(u16 id)
3389{
3390 switch (id) {
3391 case PCI_DEVICE_ID_HERC_WIN:
3392 case PCI_DEVICE_ID_HERC_UNI:
3393 return XFRAME_II_DEVICE;
3394 case PCI_DEVICE_ID_S2IO_UNI:
3395 case PCI_DEVICE_ID_S2IO_WIN:
3396 return XFRAME_I_DEVICE;
3397 default:
3398 return PCI_ANY_ID;
3399 }
3400}
1da177e4 3401
20346722
K		 3402/**
3403 * s2io_reset - Resets the card.
1da177e4
LT		 3404 * @sp : private member of the device structure.
3405 * Description: Function to Reset the card. This function then also
20346722 3406 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3407 * the card reset also resets the configuration space.
3408 * Return value:
3409 * void.
3410 */
3411
1ee6dd77 3412static void s2io_reset(struct s2io_nic * sp)
1da177e4 3413{
1ee6dd77 3414 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3415 u64 val64;
5e25b9dd 3416 u16 subid, pci_cmd;
19a60522
SS		 3417 int i;
3418 u16 val16;
491976b2
SH		 3419 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3420 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3421
19a60522
SS		 3422 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3423 __FUNCTION__, sp->dev->name);
1da177e4 3424
0b1f7ebe 3425 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3426 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3427
19a60522
SS		 3428 if (sp->device_type == XFRAME_II_DEVICE) {
3429 int ret;
3430 ret = pci_set_power_state(sp->pdev, 3);
3431 if (!ret)
3432 ret = pci_set_power_state(sp->pdev, 0);
3433 else {
3434 DBG_PRINT(ERR_DBG,"%s PME based SW_Reset failed!\n",
3435 __FUNCTION__);
3436 goto old_way;
3437 }
3438 msleep(20);
3439 goto new_way;
3440 }
3441old_way:
1da177e4
LT		 3442 val64 = SW_RESET_ALL;
3443 writeq(val64, &bar0->sw_reset);
19a60522 3444new_way:
c92ca04b
AR		 3445 if (strstr(sp->product_name, "CX4")) {
3446 msleep(750);
3447 }
19a60522
SS		 3448 msleep(250);
3449 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3450
19a60522
SS		 3451 /* Restore the PCI state saved during initialization. */
3452 pci_restore_state(sp->pdev);
3453 pci_read_config_word(sp->pdev, 0x2, &val16);
3454 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3455 break;
3456 msleep(200);
3457 }
1da177e4 3458
19a60522
SS		 3459 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3460 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3461 }
3462
3463 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3464
3465 s2io_init_pci(sp);
1da177e4 3466
20346722
K		 3467 /* Set swapper to enable I/O register access */
3468 s2io_set_swapper(sp);
3469
cc6e7c44
RA		 3470 /* Restore the MSIX table entries from local variables */
3471 restore_xmsi_data(sp);
3472
5e25b9dd 3473 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3474 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3475 /* Clear "detected parity error" bit */
303bcb4b 3476 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3477
303bcb4b
K		 3478 /* Clearing PCIX Ecc status register */
3479 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3480
303bcb4b
K		 3481 /* Clearing PCI_STATUS error reflected here */
3482 writeq(BIT(62), &bar0->txpic_int_reg);
3483 }
5e25b9dd 3484
20346722
K		 3485 /* Reset device statistics maintained by OS */
3486 memset(&sp->stats, 0, sizeof (struct net_device_stats));
491976b2
SH		 3487
3488 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3489 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3490 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3491 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
363dc367 3492 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
491976b2
SH		 3493 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3494 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3495 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3496 /* save link up/down time/cnt, reset/memory/watchdog cnt */
363dc367 3497 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
491976b2
SH		 3498 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3499 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3500 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3501 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3502 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
363dc367 3503 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
491976b2
SH		 3504 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3505 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3506 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
20346722 3507
1da177e4
LT		 3508 /* SXE-002: Configure link and activity LED to turn it off */
3509 subid = sp->pdev->subsystem_device;
541ae68f
K		 3510 if (((subid & 0xFF) >= 0x07) &&
3511 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3512 val64 = readq(&bar0->gpio_control);
3513 val64 |= 0x0000800000000000ULL;
3514 writeq(val64, &bar0->gpio_control);
3515 val64 = 0x0411040400000000ULL;
509a2671 3516 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3517 }
3518
541ae68f
K		 3519 /*
3520 * Clear spurious ECC interrupts that would have occured on
3521 * XFRAME II cards after reset.
3522 */
3523 if (sp->device_type == XFRAME_II_DEVICE) {
3524 val64 = readq(&bar0->pcc_err_reg);
3525 writeq(val64, &bar0->pcc_err_reg);
3526 }
3527
d8d70caf
SS		 3528 /* restore the previously assigned mac address */
3529 s2io_set_mac_addr(sp->dev, (u8 *)&sp->def_mac_addr[0].mac_addr);
3530
1da177e4
LT		 3531 sp->device_enabled_once = FALSE;
3532}
3533
3534/**
20346722
K		 3535 * s2io_set_swapper - to set the swapper controle on the card
3536 * @sp : private member of the device structure,
1da177e4 3537 * pointer to the s2io_nic structure.
20346722 3538 * Description: Function to set the swapper control on the card
1da177e4
LT		 3539 * correctly depending on the 'endianness' of the system.
3540 * Return value:
3541 * SUCCESS on success and FAILURE on failure.
3542 */
3543
1ee6dd77 3544static int s2io_set_swapper(struct s2io_nic * sp)
1da177e4
LT		 3545{
3546 struct net_device *dev = sp->dev;
1ee6dd77 3547 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3548 u64 val64, valt, valr;
3549
20346722 3550 /*
1da177e4
LT		 3551 * Set proper endian settings and verify the same by reading
3552 * the PIF Feed-back register.
3553 */
3554
3555 val64 = readq(&bar0->pif_rd_swapper_fb);
3556 if (val64 != 0x0123456789ABCDEFULL) {
3557 int i = 0;
3558 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3559 0x8100008181000081ULL, /* FE=1, SE=0 */
3560 0x4200004242000042ULL, /* FE=0, SE=1 */
3561 0}; /* FE=0, SE=0 */
3562
3563 while(i<4) {
3564 writeq(value[i], &bar0->swapper_ctrl);
3565 val64 = readq(&bar0->pif_rd_swapper_fb);
3566 if (val64 == 0x0123456789ABCDEFULL)
3567 break;
3568 i++;
3569 }
3570 if (i == 4) {
3571 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3572 dev->name);
3573 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3574 (unsigned long long) val64);
3575 return FAILURE;
3576 }
3577 valr = value[i];
3578 } else {
3579 valr = readq(&bar0->swapper_ctrl);
3580 }
3581
3582 valt = 0x0123456789ABCDEFULL;
3583 writeq(valt, &bar0->xmsi_address);
3584 val64 = readq(&bar0->xmsi_address);
3585
3586 if(val64 != valt) {
3587 int i = 0;
3588 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3589 0x0081810000818100ULL, /* FE=1, SE=0 */
3590 0x0042420000424200ULL, /* FE=0, SE=1 */
3591 0}; /* FE=0, SE=0 */
3592
3593 while(i<4) {
3594 writeq((value[i] | valr), &bar0->swapper_ctrl);
3595 writeq(valt, &bar0->xmsi_address);
3596 val64 = readq(&bar0->xmsi_address);
3597 if(val64 == valt)
3598 break;
3599 i++;
3600 }
3601 if(i == 4) {
20346722 3602 unsigned long long x = val64;
1da177e4 3603 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3604 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3605 return FAILURE;
3606 }
3607 }
3608 val64 = readq(&bar0->swapper_ctrl);
3609 val64 &= 0xFFFF000000000000ULL;
3610
3611#ifdef __BIG_ENDIAN
20346722
K		 3612 /*
3613 * The device by default set to a big endian format, so a
1da177e4
LT		 3614 * big endian driver need not set anything.
3615 */
3616 val64 |= (SWAPPER_CTRL_TXP_FE |
3617 SWAPPER_CTRL_TXP_SE |
3618 SWAPPER_CTRL_TXD_R_FE |
3619 SWAPPER_CTRL_TXD_W_FE |
3620 SWAPPER_CTRL_TXF_R_FE |
3621 SWAPPER_CTRL_RXD_R_FE |
3622 SWAPPER_CTRL_RXD_W_FE |
3623 SWAPPER_CTRL_RXF_W_FE |
3624 SWAPPER_CTRL_XMSI_FE |
1da177e4 3625 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
92383340 3626 if (sp->intr_type == INTA)
cc6e7c44 3627 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3628 writeq(val64, &bar0->swapper_ctrl);
3629#else
20346722 3630 /*
1da177e4 3631 * Initially we enable all bits to make it accessible by the
20346722 3632 * driver, then we selectively enable only those bits that
1da177e4
LT		 3633 * we want to set.
3634 */
3635 val64 |= (SWAPPER_CTRL_TXP_FE |
3636 SWAPPER_CTRL_TXP_SE |
3637 SWAPPER_CTRL_TXD_R_FE |
3638 SWAPPER_CTRL_TXD_R_SE |
3639 SWAPPER_CTRL_TXD_W_FE |
3640 SWAPPER_CTRL_TXD_W_SE |
3641 SWAPPER_CTRL_TXF_R_FE |
3642 SWAPPER_CTRL_RXD_R_FE |
3643 SWAPPER_CTRL_RXD_R_SE |
3644 SWAPPER_CTRL_RXD_W_FE |
3645 SWAPPER_CTRL_RXD_W_SE |
3646 SWAPPER_CTRL_RXF_W_FE |
3647 SWAPPER_CTRL_XMSI_FE |
1da177e4 3648 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
cc6e7c44
RA		 3649 if (sp->intr_type == INTA)
3650 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3651 writeq(val64, &bar0->swapper_ctrl);
3652#endif
3653 val64 = readq(&bar0->swapper_ctrl);
3654
20346722
K		 3655 /*
3656 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3657 * feedback register.
3658 */
3659 val64 = readq(&bar0->pif_rd_swapper_fb);
3660 if (val64 != 0x0123456789ABCDEFULL) {
3661 /* Endian settings are incorrect, calls for another dekko. */
3662 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3663 dev->name);
3664 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3665 (unsigned long long) val64);
3666 return FAILURE;
3667 }
3668
3669 return SUCCESS;
3670}
3671
1ee6dd77 3672static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3673{
1ee6dd77 3674 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3675 u64 val64;
3676 int ret = 0, cnt = 0;
3677
3678 do {
3679 val64 = readq(&bar0->xmsi_access);
3680 if (!(val64 & BIT(15)))
3681 break;
3682 mdelay(1);
3683 cnt++;
3684 } while(cnt < 5);
3685 if (cnt == 5) {
3686 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3687 ret = 1;
3688 }
3689
3690 return ret;
3691}
3692
1ee6dd77 3693static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3694{
1ee6dd77 3695 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3696 u64 val64;
3697 int i;
3698
75c30b13 3699 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3700 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3701 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3702 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3703 writeq(val64, &bar0->xmsi_access);
3704 if (wait_for_msix_trans(nic, i)) {
3705 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3706 continue;
3707 }
3708 }
3709}
3710
1ee6dd77 3711static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3712{
1ee6dd77 3713 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3714 u64 val64, addr, data;
3715 int i;
3716
3717 /* Store and display */
75c30b13 3718 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3719 val64 = (BIT(15) | vBIT(i, 26, 6));
3720 writeq(val64, &bar0->xmsi_access);
3721 if (wait_for_msix_trans(nic, i)) {
3722 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3723 continue;
3724 }
3725 addr = readq(&bar0->xmsi_address);
3726 data = readq(&bar0->xmsi_data);
3727 if (addr && data) {
3728 nic->msix_info[i].addr = addr;
3729 nic->msix_info[i].data = data;
3730 }
3731 }
3732}
3733
1ee6dd77 3734int s2io_enable_msi(struct s2io_nic *nic)
cc6e7c44 3735{
1ee6dd77 3736 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3737 u16 msi_ctrl, msg_val;
3738 struct config_param *config = &nic->config;
3739 struct net_device *dev = nic->dev;
3740 u64 val64, tx_mat, rx_mat;
3741 int i, err;
3742
3743 val64 = readq(&bar0->pic_control);
3744 val64 &= ~BIT(1);
3745 writeq(val64, &bar0->pic_control);
3746
3747 err = pci_enable_msi(nic->pdev);
3748 if (err) {
3749 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3750 nic->dev->name);
3751 return err;
3752 }
3753
3754 /*
3755 * Enable MSI and use MSI-1 in stead of the standard MSI-0
3756 * for interrupt handling.
3757 */
3758 pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3759 msg_val ^= 0x1;
3760 pci_write_config_word(nic->pdev, 0x4c, msg_val);
3761 pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3762
3763 pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3764 msi_ctrl |= 0x10;
3765 pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3766
3767 /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3768 tx_mat = readq(&bar0->tx_mat0_n[0]);
3769 for (i=0; i<config->tx_fifo_num; i++) {
3770 tx_mat |= TX_MAT_SET(i, 1);
3771 }
3772 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3773
3774 rx_mat = readq(&bar0->rx_mat);
3775 for (i=0; i<config->rx_ring_num; i++) {
3776 rx_mat |= RX_MAT_SET(i, 1);
3777 }
3778 writeq(rx_mat, &bar0->rx_mat);
3779
3780 dev->irq = nic->pdev->irq;
3781 return 0;
3782}
3783
1ee6dd77 3784static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3785{
1ee6dd77 3786 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3787 u64 tx_mat, rx_mat;
3788 u16 msi_control; /* Temp variable */
3789 int ret, i, j, msix_indx = 1;
3790
3791 nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3792 GFP_KERNEL);
3793 if (nic->entries == NULL) {
491976b2
SH		 3794 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3795 __FUNCTION__);
c53d4945 3796 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44
RA		 3797 return -ENOMEM;
3798 }
491976b2
SH		 3799 nic->mac_control.stats_info->sw_stat.mem_allocated
3800 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3801 memset(nic->entries, 0,MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44
RA		 3802
3803 nic->s2io_entries =
3804 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3805 GFP_KERNEL);
3806 if (nic->s2io_entries == NULL) {
491976b2
SH		 3807 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3808 __FUNCTION__);
c53d4945 3809 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44 3810 kfree(nic->entries);
491976b2
SH		 3811 nic->mac_control.stats_info->sw_stat.mem_freed
3812 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44
RA		 3813 return -ENOMEM;
3814 }
491976b2
SH		 3815 nic->mac_control.stats_info->sw_stat.mem_allocated
3816 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3817 memset(nic->s2io_entries, 0,
3818 MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3819
3820 for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3821 nic->entries[i].entry = i;
3822 nic->s2io_entries[i].entry = i;
3823 nic->s2io_entries[i].arg = NULL;
3824 nic->s2io_entries[i].in_use = 0;
3825 }
3826
3827 tx_mat = readq(&bar0->tx_mat0_n[0]);
3828 for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3829 tx_mat |= TX_MAT_SET(i, msix_indx);
3830 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3831 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3832 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3833 }
3834 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3835
3836 if (!nic->config.bimodal) {
3837 rx_mat = readq(&bar0->rx_mat);
3838 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3839 rx_mat |= RX_MAT_SET(j, msix_indx);
491976b2
SH		 3840 nic->s2io_entries[msix_indx].arg
3841 = &nic->mac_control.rings[j];
cc6e7c44
RA		 3842 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3843 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3844 }
3845 writeq(rx_mat, &bar0->rx_mat);
3846 } else {
3847 tx_mat = readq(&bar0->tx_mat0_n[7]);
3848 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3849 tx_mat |= TX_MAT_SET(i, msix_indx);
491976b2
SH		 3850 nic->s2io_entries[msix_indx].arg
3851 = &nic->mac_control.rings[j];
cc6e7c44
RA		 3852 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3853 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3854 }
3855 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3856 }
3857
c92ca04b 3858 nic->avail_msix_vectors = 0;
cc6e7c44 3859 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
c92ca04b
AR		 3860 /* We fail init if error or we get less vectors than min required */
3861 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3862 nic->avail_msix_vectors = ret;
3863 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3864 }
cc6e7c44
RA		 3865 if (ret) {
3866 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3867 kfree(nic->entries);
491976b2
SH		 3868 nic->mac_control.stats_info->sw_stat.mem_freed
3869 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44 3870 kfree(nic->s2io_entries);
491976b2
SH		 3871 nic->mac_control.stats_info->sw_stat.mem_freed
3872 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3873 nic->entries = NULL;
3874 nic->s2io_entries = NULL;
c92ca04b 3875 nic->avail_msix_vectors = 0;
cc6e7c44
RA		 3876 return -ENOMEM;
3877 }
c92ca04b
AR		 3878 if (!nic->avail_msix_vectors)
3879 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
cc6e7c44
RA		 3880
3881 /*
3882 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3883 * in the herc NIC. (Temp change, needs to be removed later)
3884 */
3885 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3886 msi_control |= 0x1; /* Enable MSI */
3887 pci_write_config_word(nic->pdev, 0x42, msi_control);
3888
3889 return 0;
3890}
3891
1da177e4
LT		 3892/* ********************************************************* *
3893 * Functions defined below concern the OS part of the driver *
3894 * ********************************************************* */
3895
20346722 3896/**
1da177e4
LT		 3897 * s2io_open - open entry point of the driver
3898 * @dev : pointer to the device structure.
3899 * Description:
3900 * This function is the open entry point of the driver. It mainly calls a
3901 * function to allocate Rx buffers and inserts them into the buffer
20346722 3902 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3903 * Return value:
3904 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3905 * file on failure.
3906 */
3907
ac1f60db 3908static int s2io_open(struct net_device *dev)
1da177e4 3909{
1ee6dd77 3910 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 3911 int err = 0;
3912
20346722
K		 3913 /*
3914 * Make sure you have link off by default every time
1da177e4
LT		 3915 * Nic is initialized
3916 */
3917 netif_carrier_off(dev);
0b1f7ebe 3918 sp->last_link_state = 0;
1da177e4
LT		 3919
3920 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 3921 err = s2io_card_up(sp);
3922 if (err) {
1da177e4
LT		 3923 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3924 dev->name);
e6a8fee2 3925 goto hw_init_failed;
1da177e4
LT		 3926 }
3927
3928 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3929 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 3930 s2io_card_down(sp);
20346722 3931 err = -ENODEV;
e6a8fee2 3932 goto hw_init_failed;
1da177e4
LT		 3933 }
3934
3935 netif_start_queue(dev);
3936 return 0;
20346722 3937
20346722 3938hw_init_failed:
cc6e7c44 3939 if (sp->intr_type == MSI_X) {
491976b2 3940 if (sp->entries) {
cc6e7c44 3941 kfree(sp->entries);
491976b2
SH		 3942 sp->mac_control.stats_info->sw_stat.mem_freed
3943 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3944 }
3945 if (sp->s2io_entries) {
cc6e7c44 3946 kfree(sp->s2io_entries);
491976b2
SH		 3947 sp->mac_control.stats_info->sw_stat.mem_freed
3948 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3949 }
cc6e7c44 3950 }
20346722 3951 return err;
1da177e4
LT		 3952}
3953
3954/**
3955 * s2io_close -close entry point of the driver
3956 * @dev : device pointer.
3957 * Description:
3958 * This is the stop entry point of the driver. It needs to undo exactly
3959 * whatever was done by the open entry point,thus it's usually referred to
3960 * as the close function.Among other things this function mainly stops the
3961 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3962 * Return value:
3963 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3964 * file on failure.
3965 */
3966
ac1f60db 3967static int s2io_close(struct net_device *dev)
1da177e4 3968{
1ee6dd77 3969 struct s2io_nic *sp = dev->priv;
cc6e7c44 3970
1da177e4
LT		 3971 netif_stop_queue(dev);
3972 /* Reset card, kill tasklet and free Tx and Rx buffers. */
e6a8fee2 3973 s2io_card_down(sp);
cc6e7c44 3974
1da177e4
LT		 3975 return 0;
3976}
3977
3978/**
3979 * s2io_xmit - Tx entry point of te driver
3980 * @skb : the socket buffer containing the Tx data.
3981 * @dev : device pointer.
3982 * Description :
3983 * This function is the Tx entry point of the driver. S2IO NIC supports
3984 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3985 * NOTE: when device cant queue the pkt,just the trans_start variable will
3986 * not be upadted.
3987 * Return value:
3988 * 0 on success & 1 on failure.
3989 */
3990
ac1f60db 3991static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 3992{
1ee6dd77 3993 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 3994 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3995 register u64 val64;
1ee6dd77
RB		 3996 struct TxD *txdp;
3997 struct TxFIFO_element __iomem *tx_fifo;
1da177e4 3998 unsigned long flags;
be3a6b02
K		 3999 u16 vlan_tag = 0;
4000 int vlan_priority = 0;
1ee6dd77 4001 struct mac_info *mac_control;
1da177e4 4002 struct config_param *config;
75c30b13 4003 int offload_type;
1da177e4
LT		 4004
4005 mac_control = &sp->mac_control;
4006 config = &sp->config;
4007
20346722 4008 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4009
4010 if (unlikely(skb->len <= 0)) {
4011 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4012 dev_kfree_skb_any(skb);
4013 return 0;
4014}
4015
1da177e4 4016 spin_lock_irqsave(&sp->tx_lock, flags);
1da177e4 4017 if (atomic_read(&sp->card_state) == CARD_DOWN) {
20346722 4018 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4
LT		 4019 dev->name);
4020 spin_unlock_irqrestore(&sp->tx_lock, flags);
20346722
K		 4021 dev_kfree_skb(skb);
4022 return 0;
1da177e4
LT		 4023 }
4024
4025 queue = 0;
be3a6b02
K		 4026 /* Get Fifo number to Transmit based on vlan priority */
4027 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
4028 vlan_tag = vlan_tx_tag_get(skb);
4029 vlan_priority = vlan_tag >> 13;
4030 queue = config->fifo_mapping[vlan_priority];
4031 }
4032
20346722
K		 4033 put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
4034 get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
1ee6dd77 4035 txdp = (struct TxD *) mac_control->fifos[queue].list_info[put_off].
20346722
K		 4036 list_virt_addr;
4037
4038 queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
1da177e4 4039 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9
AR		 4040 if (txdp->Host_Control ||
4041 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4042 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
1da177e4
LT		 4043 netif_stop_queue(dev);
4044 dev_kfree_skb(skb);
4045 spin_unlock_irqrestore(&sp->tx_lock, flags);
4046 return 0;
4047 }
0b1f7ebe 4048
75c30b13 4049 offload_type = s2io_offload_type(skb);
75c30b13 4050 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4051 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4052 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4053 }
84fa7933 4054 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 4055 txdp->Control_2 |=
4056 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4057 TXD_TX_CKO_UDP_EN);
4058 }
fed5eccd
AR		 4059 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4060 txdp->Control_1 |= TXD_LIST_OWN_XENA;
1da177e4 4061 txdp->Control_2 |= config->tx_intr_type;
d8892c6e 4062
be3a6b02
K		 4063 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
4064 txdp->Control_2 |= TXD_VLAN_ENABLE;
4065 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4066 }
4067
fed5eccd 4068 frg_len = skb->len - skb->data_len;
75c30b13 4069 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4070 int ufo_size;
4071
75c30b13 4072 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4073 ufo_size &= ~7;
4074 txdp->Control_1 |= TXD_UFO_EN;
4075 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4076 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4077#ifdef __BIG_ENDIAN
4078 sp->ufo_in_band_v[put_off] =
4079 (u64)skb_shinfo(skb)->ip6_frag_id;
4080#else
4081 sp->ufo_in_band_v[put_off] =
4082 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
4083#endif
4084 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
4085 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4086 sp->ufo_in_band_v,
4087 sizeof(u64), PCI_DMA_TODEVICE);
4088 txdp++;
fed5eccd 4089 }
1da177e4 4090
fed5eccd
AR		 4091 txdp->Buffer_Pointer = pci_map_single
4092 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
4093 txdp->Host_Control = (unsigned long) skb;
4094 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4095 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4096 txdp->Control_1 |= TXD_UFO_EN;
4097
4098 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4099 /* For fragmented SKB. */
4100 for (i = 0; i < frg_cnt; i++) {
4101 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe
K		 4102 /* A '0' length fragment will be ignored */
4103 if (!frag->size)
4104 continue;
1da177e4
LT		 4105 txdp++;
4106 txdp->Buffer_Pointer = (u64) pci_map_page
4107 (sp->pdev, frag->page, frag->page_offset,
4108 frag->size, PCI_DMA_TODEVICE);
efd51b5c 4109 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4110 if (offload_type == SKB_GSO_UDP)
fed5eccd 4111 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4112 }
4113 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4114
75c30b13 4115 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4116 frg_cnt++; /* as Txd0 was used for inband header */
4117
1da177e4 4118 tx_fifo = mac_control->tx_FIFO_start[queue];
20346722 4119 val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
1da177e4
LT		 4120 writeq(val64, &tx_fifo->TxDL_Pointer);
4121
4122 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4123 TX_FIFO_LAST_LIST);
75c30b13 4124 if (offload_type)
fed5eccd 4125 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4126
1da177e4
LT		 4127 writeq(val64, &tx_fifo->List_Control);
4128
303bcb4b
K		 4129 mmiowb();
4130
1da177e4 4131 put_off++;
863c11a9
AR		 4132 if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
4133 put_off = 0;
20346722 4134 mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
1da177e4
LT		 4135
4136 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4137 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
bd1034f0 4138 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
1da177e4
LT		 4139 DBG_PRINT(TX_DBG,
4140 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4141 put_off, get_off);
4142 netif_stop_queue(dev);
4143 }
491976b2 4144 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
1da177e4
LT		 4145 dev->trans_start = jiffies;
4146 spin_unlock_irqrestore(&sp->tx_lock, flags);
4147
4148 return 0;
4149}
4150
25fff88e
K		 4151static void
4152s2io_alarm_handle(unsigned long data)
4153{
1ee6dd77 4154 struct s2io_nic *sp = (struct s2io_nic *)data;
25fff88e
K		 4155
4156 alarm_intr_handler(sp);
4157 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4158}
4159
1ee6dd77 4160static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
75c30b13
AR		 4161{
4162 int rxb_size, level;
4163
4164 if (!sp->lro) {
4165 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4166 level = rx_buffer_level(sp, rxb_size, rng_n);
4167
4168 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4169 int ret;
4170 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4171 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4172 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
0c61ed5f 4173 DBG_PRINT(INFO_DBG, "Out of memory in %s",
75c30b13
AR		 4174 __FUNCTION__);
4175 clear_bit(0, (&sp->tasklet_status));
4176 return -1;
4177 }
4178 clear_bit(0, (&sp->tasklet_status));
4179 } else if (level == LOW)
4180 tasklet_schedule(&sp->task);
4181
4182 } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
0c61ed5f
RV		 4183 DBG_PRINT(INFO_DBG, "%s:Out of memory", sp->dev->name);
4184 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
75c30b13
AR		 4185 }
4186 return 0;
4187}
4188
7d12e780 4189static irqreturn_t s2io_msi_handle(int irq, void *dev_id)
cc6e7c44
RA		 4190{
4191 struct net_device *dev = (struct net_device *) dev_id;
1ee6dd77 4192 struct s2io_nic *sp = dev->priv;
cc6e7c44 4193 int i;
1ee6dd77 4194 struct mac_info *mac_control;
cc6e7c44
RA		 4195 struct config_param *config;
4196
4197 atomic_inc(&sp->isr_cnt);
4198 mac_control = &sp->mac_control;
4199 config = &sp->config;
4200 DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
4201
4202 /* If Intr is because of Rx Traffic */
4203 for (i = 0; i < config->rx_ring_num; i++)
4204 rx_intr_handler(&mac_control->rings[i]);
4205
4206 /* If Intr is because of Tx Traffic */
4207 for (i = 0; i < config->tx_fifo_num; i++)
4208 tx_intr_handler(&mac_control->fifos[i]);
4209
4210 /*
4211 * If the Rx buffer count is below the panic threshold then
4212 * reallocate the buffers from the interrupt handler itself,
4213 * else schedule a tasklet to reallocate the buffers.
4214 */
75c30b13
AR		 4215 for (i = 0; i < config->rx_ring_num; i++)
4216 s2io_chk_rx_buffers(sp, i);
cc6e7c44
RA		 4217
4218 atomic_dec(&sp->isr_cnt);
4219 return IRQ_HANDLED;
4220}
4221
7d12e780 4222static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4223{
1ee6dd77
RB		 4224 struct ring_info *ring = (struct ring_info *)dev_id;
4225 struct s2io_nic *sp = ring->nic;
cc6e7c44
RA		 4226
4227 atomic_inc(&sp->isr_cnt);
cc6e7c44 4228
75c30b13
AR		 4229 rx_intr_handler(ring);
4230 s2io_chk_rx_buffers(sp, ring->ring_no);
7d3d0439 4231
cc6e7c44 4232 atomic_dec(&sp->isr_cnt);
cc6e7c44
RA		 4233 return IRQ_HANDLED;
4234}
4235
7d12e780 4236static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4237{
1ee6dd77
RB		 4238 struct fifo_info *fifo = (struct fifo_info *)dev_id;
4239 struct s2io_nic *sp = fifo->nic;
cc6e7c44
RA		 4240
4241 atomic_inc(&sp->isr_cnt);
4242 tx_intr_handler(fifo);
4243 atomic_dec(&sp->isr_cnt);
4244 return IRQ_HANDLED;
4245}
1ee6dd77 4246static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4247{
1ee6dd77 4248 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d
K		 4249 u64 val64;
4250
4251 val64 = readq(&bar0->pic_int_status);
4252 if (val64 & PIC_INT_GPIO) {
4253 val64 = readq(&bar0->gpio_int_reg);
4254 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4255 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4256 /*
4257 * This is unstable state so clear both up/down
4258 * interrupt and adapter to re-evaluate the link state.
4259 */
a371a07d
K		 4260 val64 |= GPIO_INT_REG_LINK_DOWN;
4261 val64 |= GPIO_INT_REG_LINK_UP;
4262 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4263 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4264 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4265 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4266 writeq(val64, &bar0->gpio_int_mask);
a371a07d 4267 }
c92ca04b
AR		 4268 else if (val64 & GPIO_INT_REG_LINK_UP) {
4269 val64 = readq(&bar0->adapter_status);
c92ca04b 4270 /* Enable Adapter */
19a60522
SS		 4271 val64 = readq(&bar0->adapter_control);
4272 val64 |= ADAPTER_CNTL_EN;
4273 writeq(val64, &bar0->adapter_control);
4274 val64 |= ADAPTER_LED_ON;
4275 writeq(val64, &bar0->adapter_control);
4276 if (!sp->device_enabled_once)
4277 sp->device_enabled_once = 1;
c92ca04b 4278
19a60522
SS		 4279 s2io_link(sp, LINK_UP);
4280 /*
4281 * unmask link down interrupt and mask link-up
4282 * intr
4283 */
4284 val64 = readq(&bar0->gpio_int_mask);
4285 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4286 val64 |= GPIO_INT_MASK_LINK_UP;
4287 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4288
c92ca04b
AR		 4289 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4290 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4291 s2io_link(sp, LINK_DOWN);
4292 /* Link is down so unmaks link up interrupt */
4293 val64 = readq(&bar0->gpio_int_mask);
4294 val64 &= ~GPIO_INT_MASK_LINK_UP;
4295 val64 |= GPIO_INT_MASK_LINK_DOWN;
4296 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4297
4298 /* turn off LED */
4299 val64 = readq(&bar0->adapter_control);
4300 val64 = val64 &(~ADAPTER_LED_ON);
4301 writeq(val64, &bar0->adapter_control);
a371a07d
K		 4302 }
4303 }
c92ca04b 4304 val64 = readq(&bar0->gpio_int_mask);
a371a07d
K		 4305}
4306
1da177e4
LT		 4307/**
4308 * s2io_isr - ISR handler of the device .
4309 * @irq: the irq of the device.
4310 * @dev_id: a void pointer to the dev structure of the NIC.
20346722
K		 4311 * Description: This function is the ISR handler of the device. It
4312 * identifies the reason for the interrupt and calls the relevant
4313 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4314 * recv buffers, if their numbers are below the panic value which is
4315 * presently set to 25% of the original number of rcv buffers allocated.
4316 * Return value:
20346722 4317 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4318 * IRQ_NONE: will be returned if interrupt is not from our device
4319 */
7d12e780 4320static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4
LT		 4321{
4322 struct net_device *dev = (struct net_device *) dev_id;
1ee6dd77
RB		 4323 struct s2io_nic *sp = dev->priv;
4324 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4325 int i;
19a60522 4326 u64 reason = 0;
1ee6dd77 4327 struct mac_info *mac_control;
1da177e4
LT		 4328 struct config_param *config;
4329
d796fdb7
LV		 4330 /* Pretend we handled any irq's from a disconnected card */
4331 if (pci_channel_offline(sp->pdev))
4332 return IRQ_NONE;
4333
7ba013ac 4334 atomic_inc(&sp->isr_cnt);
1da177e4
LT		 4335 mac_control = &sp->mac_control;
4336 config = &sp->config;
4337
20346722 4338 /*
1da177e4
LT		 4339 * Identify the cause for interrupt and call the appropriate
4340 * interrupt handler. Causes for the interrupt could be;
4341 * 1. Rx of packet.
4342 * 2. Tx complete.
4343 * 3. Link down.
20346722 4344 * 4. Error in any functional blocks of the NIC.
1da177e4
LT		 4345 */
4346 reason = readq(&bar0->general_int_status);
4347
4348 if (!reason) {
19a60522
SS		 4349 /* The interrupt was not raised by us. */
4350 atomic_dec(&sp->isr_cnt);
4351 return IRQ_NONE;
4352 }
4353 else if (unlikely(reason == S2IO_MINUS_ONE) ) {
4354 /* Disable device and get out */
7ba013ac 4355 atomic_dec(&sp->isr_cnt);
1da177e4
LT		 4356 return IRQ_NONE;
4357 }
5d3213cc 4358
db874e65
SS		 4359 if (napi) {
4360 if (reason & GEN_INTR_RXTRAFFIC) {
19a60522 4361 if ( likely ( netif_rx_schedule_prep(dev)) ) {
db874e65 4362 __netif_rx_schedule(dev);
19a60522 4363 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
db874e65 4364 }
19a60522
SS		 4365 else
4366 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
db874e65
SS		 4367 }
4368 } else {
4369 /*
4370 * Rx handler is called by default, without checking for the
4371 * cause of interrupt.
4372 * rx_traffic_int reg is an R1 register, writing all 1's
4373 * will ensure that the actual interrupt causing bit get's
4374 * cleared and hence a read can be avoided.
4375 */
19a60522
SS		 4376 if (reason & GEN_INTR_RXTRAFFIC)
4377 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4378
db874e65
SS		 4379 for (i = 0; i < config->rx_ring_num; i++) {
4380 rx_intr_handler(&mac_control->rings[i]);
1da177e4
LT		 4381 }
4382 }
1da177e4 4383
863c11a9
AR		 4384 /*
4385 * tx_traffic_int reg is an R1 register, writing all 1's
4386 * will ensure that the actual interrupt causing bit get's
4387 * cleared and hence a read can be avoided.
4388 */
19a60522
SS		 4389 if (reason & GEN_INTR_TXTRAFFIC)
4390 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
fe113638 4391
863c11a9
AR		 4392 for (i = 0; i < config->tx_fifo_num; i++)
4393 tx_intr_handler(&mac_control->fifos[i]);
20346722 4394
a371a07d
K		 4395 if (reason & GEN_INTR_TXPIC)
4396 s2io_txpic_intr_handle(sp);
20346722
K		 4397 /*
4398 * If the Rx buffer count is below the panic threshold then
4399 * reallocate the buffers from the interrupt handler itself,
1da177e4
LT		 4400 * else schedule a tasklet to reallocate the buffers.
4401 */
db874e65
SS		 4402 if (!napi) {
4403 for (i = 0; i < config->rx_ring_num; i++)
4404 s2io_chk_rx_buffers(sp, i);
4405 }
4406
4407 writeq(0, &bar0->general_int_mask);
4408 readl(&bar0->general_int_status);
4409
7ba013ac 4410 atomic_dec(&sp->isr_cnt);
1da177e4
LT		 4411 return IRQ_HANDLED;
4412}
4413
7ba013ac
K		 4414/**
4415 * s2io_updt_stats -
4416 */
1ee6dd77 4417static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4418{
1ee6dd77 4419 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac
K		 4420 u64 val64;
4421 int cnt = 0;
4422
4423 if (atomic_read(&sp->card_state) == CARD_UP) {
4424 /* Apprx 30us on a 133 MHz bus */
4425 val64 = SET_UPDT_CLICKS(10) |
4426 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4427 writeq(val64, &bar0->stat_cfg);
4428 do {
4429 udelay(100);
4430 val64 = readq(&bar0->stat_cfg);
4431 if (!(val64 & BIT(0)))
4432 break;
4433 cnt++;
4434 if (cnt == 5)
4435 break; /* Updt failed */
4436 } while(1);
363dc367 4437 }
7ba013ac
K		 4438}
4439
1da177e4 4440/**
20346722 4441 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4442 * @dev : pointer to the device structure.
4443 * Description:
20346722 4444 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4445 * structure and returns a pointer to the same.
4446 * Return value:
4447 * pointer to the updated net_device_stats structure.
4448 */
4449
ac1f60db 4450static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4451{
1ee6dd77
RB		 4452 struct s2io_nic *sp = dev->priv;
4453 struct mac_info *mac_control;
1da177e4
LT		 4454 struct config_param *config;
4455
20346722 4456
1da177e4
LT		 4457 mac_control = &sp->mac_control;
4458 config = &sp->config;
4459
7ba013ac
K		 4460 /* Configure Stats for immediate updt */
4461 s2io_updt_stats(sp);
4462
4463 sp->stats.tx_packets =
4464 le32_to_cpu(mac_control->stats_info->tmac_frms);
20346722
K		 4465 sp->stats.tx_errors =
4466 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4467 sp->stats.rx_errors =
ee705dba 4468 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
20346722
K		 4469 sp->stats.multicast =
4470 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
1da177e4 4471 sp->stats.rx_length_errors =
ee705dba 4472 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
1da177e4
LT		 4473
4474 return (&sp->stats);
4475}
4476
4477/**
4478 * s2io_set_multicast - entry point for multicast address enable/disable.
4479 * @dev : pointer to the device structure
4480 * Description:
20346722
K		 4481 * This function is a driver entry point which gets called by the kernel
4482 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4483 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4484 * determine, if multicast address must be enabled or if promiscuous mode
4485 * is to be disabled etc.
4486 * Return value:
4487 * void.
4488 */
4489
4490static void s2io_set_multicast(struct net_device *dev)
4491{
4492 int i, j, prev_cnt;
4493 struct dev_mc_list *mclist;
1ee6dd77
RB		 4494 struct s2io_nic *sp = dev->priv;
4495 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4496 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4497 0xfeffffffffffULL;
4498 u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4499 void __iomem *add;
4500
4501 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4502 /* Enable all Multicast addresses */
4503 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4504 &bar0->rmac_addr_data0_mem);
4505 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4506 &bar0->rmac_addr_data1_mem);
4507 val64 = RMAC_ADDR_CMD_MEM_WE |
4508 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4509 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4510 writeq(val64, &bar0->rmac_addr_cmd_mem);
4511 /* Wait till command completes */
c92ca04b 4512 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4513 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4514 S2IO_BIT_RESET);
1da177e4
LT		 4515
4516 sp->m_cast_flg = 1;
4517 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4518 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4519 /* Disable all Multicast addresses */
4520 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4521 &bar0->rmac_addr_data0_mem);
5e25b9dd
K		 4522 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4523 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4524 val64 = RMAC_ADDR_CMD_MEM_WE |
4525 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4526 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4527 writeq(val64, &bar0->rmac_addr_cmd_mem);
4528 /* Wait till command completes */
c92ca04b 4529 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4530 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4531 S2IO_BIT_RESET);
1da177e4
LT		 4532
4533 sp->m_cast_flg = 0;
4534 sp->all_multi_pos = 0;
4535 }
4536
4537 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4538 /* Put the NIC into promiscuous mode */
4539 add = &bar0->mac_cfg;
4540 val64 = readq(&bar0->mac_cfg);
4541 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4542
4543 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4544 writel((u32) val64, add);
4545 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4546 writel((u32) (val64 >> 32), (add + 4));
4547
926930b2
SS		 4548 if (vlan_tag_strip != 1) {
4549 val64 = readq(&bar0->rx_pa_cfg);
4550 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4551 writeq(val64, &bar0->rx_pa_cfg);
4552 vlan_strip_flag = 0;
4553 }
4554
1da177e4
LT		 4555 val64 = readq(&bar0->mac_cfg);
4556 sp->promisc_flg = 1;
776bd20f 4557 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 4558 dev->name);
4559 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4560 /* Remove the NIC from promiscuous mode */
4561 add = &bar0->mac_cfg;
4562 val64 = readq(&bar0->mac_cfg);
4563 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4564
4565 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4566 writel((u32) val64, add);
4567 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4568 writel((u32) (val64 >> 32), (add + 4));
4569
926930b2
SS		 4570 if (vlan_tag_strip != 0) {
4571 val64 = readq(&bar0->rx_pa_cfg);
4572 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4573 writeq(val64, &bar0->rx_pa_cfg);
4574 vlan_strip_flag = 1;
4575 }
4576
1da177e4
LT		 4577 val64 = readq(&bar0->mac_cfg);
4578 sp->promisc_flg = 0;
776bd20f 4579 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 4580 dev->name);
4581 }
4582
4583 /* Update individual M_CAST address list */
4584 if ((!sp->m_cast_flg) && dev->mc_count) {
4585 if (dev->mc_count >
4586 (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4587 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4588 dev->name);
4589 DBG_PRINT(ERR_DBG, "can be added, please enable ");
4590 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4591 return;
4592 }
4593
4594 prev_cnt = sp->mc_addr_count;
4595 sp->mc_addr_count = dev->mc_count;
4596
4597 /* Clear out the previous list of Mc in the H/W. */
4598 for (i = 0; i < prev_cnt; i++) {
4599 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4600 &bar0->rmac_addr_data0_mem);
4601 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4602 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4603 val64 = RMAC_ADDR_CMD_MEM_WE |
4604 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4605 RMAC_ADDR_CMD_MEM_OFFSET
4606 (MAC_MC_ADDR_START_OFFSET + i);
4607 writeq(val64, &bar0->rmac_addr_cmd_mem);
4608
4609 /* Wait for command completes */
c92ca04b 4610 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4611 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4612 S2IO_BIT_RESET)) {
1da177e4
LT		 4613 DBG_PRINT(ERR_DBG, "%s: Adding ",
4614 dev->name);
4615 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4616 return;
4617 }
4618 }
4619
4620 /* Create the new Rx filter list and update the same in H/W. */
4621 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4622 i++, mclist = mclist->next) {
4623 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4624 ETH_ALEN);
a7a80d5a 4625 mac_addr = 0;
1da177e4
LT		 4626 for (j = 0; j < ETH_ALEN; j++) {
4627 mac_addr |= mclist->dmi_addr[j];
4628 mac_addr <<= 8;
4629 }
4630 mac_addr >>= 8;
4631 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4632 &bar0->rmac_addr_data0_mem);
4633 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4634 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4635 val64 = RMAC_ADDR_CMD_MEM_WE |
4636 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4637 RMAC_ADDR_CMD_MEM_OFFSET
4638 (i + MAC_MC_ADDR_START_OFFSET);
4639 writeq(val64, &bar0->rmac_addr_cmd_mem);
4640
4641 /* Wait for command completes */
c92ca04b 4642 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4643 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4644 S2IO_BIT_RESET)) {
1da177e4
LT		 4645 DBG_PRINT(ERR_DBG, "%s: Adding ",
4646 dev->name);
4647 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4648 return;
4649 }
4650 }
4651 }
4652}
4653
4654/**
20346722 4655 * s2io_set_mac_addr - Programs the Xframe mac address
1da177e4
LT		 4656 * @dev : pointer to the device structure.
4657 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 4658 * Description : This procedure will program the Xframe to receive
1da177e4 4659 * frames with new Mac Address
20346722 4660 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 4661 * as defined in errno.h file on failure.
4662 */
4663
26df54bf 4664static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
1da177e4 4665{
1ee6dd77
RB		 4666 struct s2io_nic *sp = dev->priv;
4667 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4668 register u64 val64, mac_addr = 0;
4669 int i;
d8d70caf 4670 u64 old_mac_addr = 0;
1da177e4 4671
20346722 4672 /*
1da177e4
LT		 4673 * Set the new MAC address as the new unicast filter and reflect this
4674 * change on the device address registered with the OS. It will be
20346722 4675 * at offset 0.
1da177e4
LT		 4676 */
4677 for (i = 0; i < ETH_ALEN; i++) {
4678 mac_addr <<= 8;
4679 mac_addr |= addr[i];
d8d70caf
SS		 4680 old_mac_addr <<= 8;
4681 old_mac_addr |= sp->def_mac_addr[0].mac_addr[i];
4682 }
4683
4684 if(0 == mac_addr)
4685 return SUCCESS;
4686
4687 /* Update the internal structure with this new mac address */
4688 if(mac_addr != old_mac_addr) {
4689 memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
4690 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_addr);
4691 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_addr >> 8);
4692 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_addr >> 16);
4693 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_addr >> 24);
4694 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_addr >> 32);
4695 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_addr >> 40);
1da177e4
LT		 4696 }
4697
4698 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4699 &bar0->rmac_addr_data0_mem);
4700
4701 val64 =
4702 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4703 RMAC_ADDR_CMD_MEM_OFFSET(0);
4704 writeq(val64, &bar0->rmac_addr_cmd_mem);
4705 /* Wait till command completes */
c92ca04b 4706 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41 4707 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET)) {
1da177e4
LT		 4708 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4709 return FAILURE;
4710 }
4711
4712 return SUCCESS;
4713}
4714
4715/**
20346722 4716 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 4717 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4718 * @info: pointer to the structure with parameters given by ethtool to set
4719 * link information.
4720 * Description:
20346722 4721 * The function sets different link parameters provided by the user onto
1da177e4
LT		 4722 * the NIC.
4723 * Return value:
4724 * 0 on success.
4725*/
4726
4727static int s2io_ethtool_sset(struct net_device *dev,
4728 struct ethtool_cmd *info)
4729{
1ee6dd77 4730 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4731 if ((info->autoneg == AUTONEG_ENABLE) ||
4732 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4733 return -EINVAL;
4734 else {
4735 s2io_close(sp->dev);
4736 s2io_open(sp->dev);
4737 }
4738
4739 return 0;
4740}
4741
4742/**
20346722 4743 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 4744 * @sp : private member of the device structure, pointer to the
4745 * s2io_nic structure.
4746 * @info : pointer to the structure with parameters given by ethtool
4747 * to return link information.
4748 * Description:
4749 * Returns link specific information like speed, duplex etc.. to ethtool.
4750 * Return value :
4751 * return 0 on success.
4752 */
4753
4754static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4755{
1ee6dd77 4756 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4757 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4758 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4759 info->port = PORT_FIBRE;
4760 /* info->transceiver?? TODO */
4761
4762 if (netif_carrier_ok(sp->dev)) {
4763 info->speed = 10000;
4764 info->duplex = DUPLEX_FULL;
4765 } else {
4766 info->speed = -1;
4767 info->duplex = -1;
4768 }
4769
4770 info->autoneg = AUTONEG_DISABLE;
4771 return 0;
4772}
4773
4774/**
20346722
K		 4775 * s2io_ethtool_gdrvinfo - Returns driver specific information.
4776 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4777 * s2io_nic structure.
4778 * @info : pointer to the structure with parameters given by ethtool to
4779 * return driver information.
4780 * Description:
4781 * Returns driver specefic information like name, version etc.. to ethtool.
4782 * Return value:
4783 * void
4784 */
4785
4786static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4787 struct ethtool_drvinfo *info)
4788{
1ee6dd77 4789 struct s2io_nic *sp = dev->priv;
1da177e4 4790
dbc2309d
JL		 4791 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4792 strncpy(info->version, s2io_driver_version, sizeof(info->version));
4793 strncpy(info->fw_version, "", sizeof(info->fw_version));
4794 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 4795 info->regdump_len = XENA_REG_SPACE;
4796 info->eedump_len = XENA_EEPROM_SPACE;
4797 info->testinfo_len = S2IO_TEST_LEN;
fa1f0cb3
SS		 4798
4799 if (sp->device_type == XFRAME_I_DEVICE)
4800 info->n_stats = XFRAME_I_STAT_LEN;
4801 else
4802 info->n_stats = XFRAME_II_STAT_LEN;
1da177e4
LT		 4803}
4804
4805/**
4806 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 4807 * @sp: private member of the device structure, which is a pointer to the
1da177e4 4808 * s2io_nic structure.
20346722 4809 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 4810 * dumping the registers.
4811 * @reg_space: The input argumnet into which all the registers are dumped.
4812 * Description:
4813 * Dumps the entire register space of xFrame NIC into the user given
4814 * buffer area.
4815 * Return value :
4816 * void .
4817*/
4818
4819static void s2io_ethtool_gregs(struct net_device *dev,
4820 struct ethtool_regs *regs, void *space)
4821{
4822 int i;
4823 u64 reg;
4824 u8 *reg_space = (u8 *) space;
1ee6dd77 4825 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4826
4827 regs->len = XENA_REG_SPACE;
4828 regs->version = sp->pdev->subsystem_device;
4829
4830 for (i = 0; i < regs->len; i += 8) {
4831 reg = readq(sp->bar0 + i);
4832 memcpy((reg_space + i), &reg, 8);
4833 }
4834}
4835
4836/**
4837 * s2io_phy_id - timer function that alternates adapter LED.
20346722 4838 * @data : address of the private member of the device structure, which
1da177e4 4839 * is a pointer to the s2io_nic structure, provided as an u32.
20346722
K		 4840 * Description: This is actually the timer function that alternates the
4841 * adapter LED bit of the adapter control bit to set/reset every time on
4842 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4
LT		 4843 * once every second.
4844*/
4845static void s2io_phy_id(unsigned long data)
4846{
1ee6dd77
RB		 4847 struct s2io_nic *sp = (struct s2io_nic *) data;
4848 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4849 u64 val64 = 0;
4850 u16 subid;
4851
4852 subid = sp->pdev->subsystem_device;
541ae68f
K		 4853 if ((sp->device_type == XFRAME_II_DEVICE) ||
4854 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 4855 val64 = readq(&bar0->gpio_control);
4856 val64 ^= GPIO_CTRL_GPIO_0;
4857 writeq(val64, &bar0->gpio_control);
4858 } else {
4859 val64 = readq(&bar0->adapter_control);
4860 val64 ^= ADAPTER_LED_ON;
4861 writeq(val64, &bar0->adapter_control);
4862 }
4863
4864 mod_timer(&sp->id_timer, jiffies + HZ / 2);
4865}
4866
4867/**
4868 * s2io_ethtool_idnic - To physically identify the nic on the system.
4869 * @sp : private member of the device structure, which is a pointer to the
4870 * s2io_nic structure.
20346722 4871 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 4872 * ethtool.
4873 * Description: Used to physically identify the NIC on the system.
20346722 4874 * The Link LED will blink for a time specified by the user for
1da177e4 4875 * identification.
20346722 4876 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 4877 * identification is possible only if it's link is up.
4878 * Return value:
4879 * int , returns 0 on success
4880 */
4881
4882static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4883{
4884 u64 val64 = 0, last_gpio_ctrl_val;
1ee6dd77
RB		 4885 struct s2io_nic *sp = dev->priv;
4886 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4887 u16 subid;
4888
4889 subid = sp->pdev->subsystem_device;
4890 last_gpio_ctrl_val = readq(&bar0->gpio_control);
541ae68f
K		 4891 if ((sp->device_type == XFRAME_I_DEVICE) &&
4892 ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 4893 val64 = readq(&bar0->adapter_control);
4894 if (!(val64 & ADAPTER_CNTL_EN)) {
4895 printk(KERN_ERR
4896 "Adapter Link down, cannot blink LED\n");
4897 return -EFAULT;
4898 }
4899 }
4900 if (sp->id_timer.function == NULL) {
4901 init_timer(&sp->id_timer);
4902 sp->id_timer.function = s2io_phy_id;
4903 sp->id_timer.data = (unsigned long) sp;
4904 }
4905 mod_timer(&sp->id_timer, jiffies);
4906 if (data)
20346722 4907 msleep_interruptible(data * HZ);
1da177e4 4908 else
20346722 4909 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 4910 del_timer_sync(&sp->id_timer);
4911
541ae68f 4912 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 4913 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4914 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4915 }
4916
4917 return 0;
4918}
4919
0cec35eb
SH		 4920static void s2io_ethtool_gringparam(struct net_device *dev,
4921 struct ethtool_ringparam *ering)
4922{
4923 struct s2io_nic *sp = dev->priv;
4924 int i,tx_desc_count=0,rx_desc_count=0;
4925
4926 if (sp->rxd_mode == RXD_MODE_1)
4927 ering->rx_max_pending = MAX_RX_DESC_1;
4928 else if (sp->rxd_mode == RXD_MODE_3B)
4929 ering->rx_max_pending = MAX_RX_DESC_2;
4930 else if (sp->rxd_mode == RXD_MODE_3A)
4931 ering->rx_max_pending = MAX_RX_DESC_3;
4932
4933 ering->tx_max_pending = MAX_TX_DESC;
4934 for (i = 0 ; i < sp->config.tx_fifo_num ; i++) {
4935 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
4936 }
4937 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
4938 ering->tx_pending = tx_desc_count;
4939 rx_desc_count = 0;
4940 for (i = 0 ; i < sp->config.rx_ring_num ; i++) {
4941 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
4942 }
4943 ering->rx_pending = rx_desc_count;
4944
4945 ering->rx_mini_max_pending = 0;
4946 ering->rx_mini_pending = 0;
4947 if(sp->rxd_mode == RXD_MODE_1)
4948 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
4949 else if (sp->rxd_mode == RXD_MODE_3B)
4950 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
4951 ering->rx_jumbo_pending = rx_desc_count;
4952}
4953
1da177e4
LT		 4954/**
4955 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722
K		 4956 * @sp : private member of the device structure, which is a pointer to the
4957 * s2io_nic structure.
1da177e4
LT		 4958 * @ep : pointer to the structure with pause parameters given by ethtool.
4959 * Description:
4960 * Returns the Pause frame generation and reception capability of the NIC.
4961 * Return value:
4962 * void
4963 */
4964static void s2io_ethtool_getpause_data(struct net_device *dev,
4965 struct ethtool_pauseparam *ep)
4966{
4967 u64 val64;
1ee6dd77
RB		 4968 struct s2io_nic *sp = dev->priv;
4969 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4970
4971 val64 = readq(&bar0->rmac_pause_cfg);
4972 if (val64 & RMAC_PAUSE_GEN_ENABLE)
4973 ep->tx_pause = TRUE;
4974 if (val64 & RMAC_PAUSE_RX_ENABLE)
4975 ep->rx_pause = TRUE;
4976 ep->autoneg = FALSE;
4977}
4978
4979/**
4980 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 4981 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4982 * s2io_nic structure.
4983 * @ep : pointer to the structure with pause parameters given by ethtool.
4984 * Description:
4985 * It can be used to set or reset Pause frame generation or reception
4986 * support of the NIC.
4987 * Return value:
4988 * int, returns 0 on Success
4989 */
4990
4991static int s2io_ethtool_setpause_data(struct net_device *dev,
20346722 4992 struct ethtool_pauseparam *ep)
1da177e4
LT		 4993{
4994 u64 val64;
1ee6dd77
RB		 4995 struct s2io_nic *sp = dev->priv;
4996 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4997
4998 val64 = readq(&bar0->rmac_pause_cfg);
4999 if (ep->tx_pause)
5000 val64 |= RMAC_PAUSE_GEN_ENABLE;
5001 else
5002 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5003 if (ep->rx_pause)
5004 val64 |= RMAC_PAUSE_RX_ENABLE;
5005 else
5006 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5007 writeq(val64, &bar0->rmac_pause_cfg);
5008 return 0;
5009}
5010
5011/**
5012 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5013 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5014 * s2io_nic structure.
5015 * @off : offset at which the data must be written
5016 * @data : Its an output parameter where the data read at the given
20346722 5017 * offset is stored.
1da177e4 5018 * Description:
20346722 5019 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5020 * read data.
5021 * NOTE: Will allow to read only part of the EEPROM visible through the
5022 * I2C bus.
5023 * Return value:
5024 * -1 on failure and 0 on success.
5025 */
5026
5027#define S2IO_DEV_ID 5
1ee6dd77 5028static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
1da177e4
LT		 5029{
5030 int ret = -1;
5031 u32 exit_cnt = 0;
5032 u64 val64;
1ee6dd77 5033 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5034
ad4ebed0 5035 if (sp->device_type == XFRAME_I_DEVICE) {
5036 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5037 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5038 I2C_CONTROL_CNTL_START;
5039 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5040
ad4ebed0 5041 while (exit_cnt < 5) {
5042 val64 = readq(&bar0->i2c_control);
5043 if (I2C_CONTROL_CNTL_END(val64)) {
5044 *data = I2C_CONTROL_GET_DATA(val64);
5045 ret = 0;
5046 break;
5047 }
5048 msleep(50);
5049 exit_cnt++;
1da177e4 5050 }
1da177e4
LT		 5051 }
5052
ad4ebed0 5053 if (sp->device_type == XFRAME_II_DEVICE) {
5054 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5055 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5056 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5057 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5058 val64 |= SPI_CONTROL_REQ;
5059 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5060 while (exit_cnt < 5) {
5061 val64 = readq(&bar0->spi_control);
5062 if (val64 & SPI_CONTROL_NACK) {
5063 ret = 1;
5064 break;
5065 } else if (val64 & SPI_CONTROL_DONE) {
5066 *data = readq(&bar0->spi_data);
5067 *data &= 0xffffff;
5068 ret = 0;
5069 break;
5070 }
5071 msleep(50);
5072 exit_cnt++;
5073 }
5074 }
1da177e4
LT		 5075 return ret;
5076}
5077
5078/**
5079 * write_eeprom - actually writes the relevant part of the data value.
5080 * @sp : private member of the device structure, which is a pointer to the
5081 * s2io_nic structure.
5082 * @off : offset at which the data must be written
5083 * @data : The data that is to be written
20346722 5084 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5085 * the Eeprom. (max of 3)
5086 * Description:
5087 * Actually writes the relevant part of the data value into the Eeprom
5088 * through the I2C bus.
5089 * Return value:
5090 * 0 on success, -1 on failure.
5091 */
5092
1ee6dd77 5093static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
1da177e4
LT		 5094{
5095 int exit_cnt = 0, ret = -1;
5096 u64 val64;
1ee6dd77 5097 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5098
ad4ebed0 5099 if (sp->device_type == XFRAME_I_DEVICE) {
5100 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5101 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5102 I2C_CONTROL_CNTL_START;
5103 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5104
5105 while (exit_cnt < 5) {
5106 val64 = readq(&bar0->i2c_control);
5107 if (I2C_CONTROL_CNTL_END(val64)) {
5108 if (!(val64 & I2C_CONTROL_NACK))
5109 ret = 0;
5110 break;
5111 }
5112 msleep(50);
5113 exit_cnt++;
5114 }
5115 }
1da177e4 5116
ad4ebed0 5117 if (sp->device_type == XFRAME_II_DEVICE) {
5118 int write_cnt = (cnt == 8) ? 0 : cnt;
5119 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5120
5121 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5122 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5123 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5124 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5125 val64 |= SPI_CONTROL_REQ;
5126 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5127 while (exit_cnt < 5) {
5128 val64 = readq(&bar0->spi_control);
5129 if (val64 & SPI_CONTROL_NACK) {
5130 ret = 1;
5131 break;
5132 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5133 ret = 0;
ad4ebed0 5134 break;
5135 }
5136 msleep(50);
5137 exit_cnt++;
1da177e4 5138 }
1da177e4 5139 }
1da177e4
LT		 5140 return ret;
5141}
1ee6dd77 5142static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5143{
b41477f3
AR		 5144 u8 *vpd_data;
5145 u8 data;
9dc737a7
AR		 5146 int i=0, cnt, fail = 0;
5147 int vpd_addr = 0x80;
5148
5149 if (nic->device_type == XFRAME_II_DEVICE) {
5150 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5151 vpd_addr = 0x80;
5152 }
5153 else {
5154 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5155 vpd_addr = 0x50;
5156 }
19a60522 5157 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5158
b41477f3 5159 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945
SH		 5160 if (!vpd_data) {
5161 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
b41477f3 5162 return;
c53d4945 5163 }
491976b2 5164 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
b41477f3 5165
9dc737a7
AR		 5166 for (i = 0; i < 256; i +=4 ) {
5167 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5168 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5169 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5170 for (cnt = 0; cnt <5; cnt++) {
5171 msleep(2);
5172 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5173 if (data == 0x80)
5174 break;
5175 }
5176 if (cnt >= 5) {
5177 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5178 fail = 1;
5179 break;
5180 }
5181 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5182 (u32 *)&vpd_data[i]);
5183 }
19a60522
SS		 5184
5185 if(!fail) {
5186 /* read serial number of adapter */
5187 for (cnt = 0; cnt < 256; cnt++) {
5188 if ((vpd_data[cnt] == 'S') &&
5189 (vpd_data[cnt+1] == 'N') &&
5190 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5191 memset(nic->serial_num, 0, VPD_STRING_LEN);
5192 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5193 vpd_data[cnt+2]);
5194 break;
5195 }
5196 }
5197 }
5198
5199 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
9dc737a7
AR		 5200 memset(nic->product_name, 0, vpd_data[1]);
5201 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5202 }
b41477f3 5203 kfree(vpd_data);
491976b2 5204 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
9dc737a7
AR		 5205}
5206
1da177e4
LT		 5207/**
5208 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5209 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5210 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5211 * containing all relevant information.
5212 * @data_buf : user defined value to be written into Eeprom.
5213 * Description: Reads the values stored in the Eeprom at given offset
5214 * for a given length. Stores these values int the input argument data
5215 * buffer 'data_buf' and returns these to the caller (ethtool.)
5216 * Return value:
5217 * int 0 on success
5218 */
5219
5220static int s2io_ethtool_geeprom(struct net_device *dev,
20346722 5221 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5222{
ad4ebed0 5223 u32 i, valid;
5224 u64 data;
1ee6dd77 5225 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5226
5227 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5228
5229 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5230 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5231
5232 for (i = 0; i < eeprom->len; i += 4) {
5233 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5234 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5235 return -EFAULT;
5236 }
5237 valid = INV(data);
5238 memcpy((data_buf + i), &valid, 4);
5239 }
5240 return 0;
5241}
5242
5243/**
5244 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5245 * @sp : private member of the device structure, which is a pointer to the
5246 * s2io_nic structure.
20346722 5247 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5248 * containing all relevant information.
5249 * @data_buf ; user defined value to be written into Eeprom.
5250 * Description:
5251 * Tries to write the user provided value in the Eeprom, at the offset
5252 * given by the user.
5253 * Return value:
5254 * 0 on success, -EFAULT on failure.
5255 */
5256
5257static int s2io_ethtool_seeprom(struct net_device *dev,
5258 struct ethtool_eeprom *eeprom,
5259 u8 * data_buf)
5260{
5261 int len = eeprom->len, cnt = 0;
ad4ebed0 5262 u64 valid = 0, data;
1ee6dd77 5263 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5264
5265 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5266 DBG_PRINT(ERR_DBG,
5267 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5268 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5269 eeprom->magic);
5270 return -EFAULT;
5271 }
5272
5273 while (len) {
5274 data = (u32) data_buf[cnt] & 0x000000FF;
5275 if (data) {
5276 valid = (u32) (data << 24);
5277 } else
5278 valid = data;
5279
5280 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5281 DBG_PRINT(ERR_DBG,
5282 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5283 DBG_PRINT(ERR_DBG,
5284 "write into the specified offset\n");
5285 return -EFAULT;
5286 }
5287 cnt++;
5288 len--;
5289 }
5290
5291 return 0;
5292}
5293
5294/**
20346722
K		 5295 * s2io_register_test - reads and writes into all clock domains.
5296 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5297 * s2io_nic structure.
5298 * @data : variable that returns the result of each of the test conducted b
5299 * by the driver.
5300 * Description:
5301 * Read and write into all clock domains. The NIC has 3 clock domains,
5302 * see that registers in all the three regions are accessible.
5303 * Return value:
5304 * 0 on success.
5305 */
5306
1ee6dd77 5307static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5308{
1ee6dd77 5309 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5310 u64 val64 = 0, exp_val;
1da177e4
LT		 5311 int fail = 0;
5312
20346722
K		 5313 val64 = readq(&bar0->pif_rd_swapper_fb);
5314 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5315 fail = 1;
5316 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5317 }
5318
5319 val64 = readq(&bar0->rmac_pause_cfg);
5320 if (val64 != 0xc000ffff00000000ULL) {
5321 fail = 1;
5322 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5323 }
5324
5325 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5326 if (sp->device_type == XFRAME_II_DEVICE)
5327 exp_val = 0x0404040404040404ULL;
5328 else
5329 exp_val = 0x0808080808080808ULL;
5330 if (val64 != exp_val) {
1da177e4
LT		 5331 fail = 1;
5332 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5333 }
5334
5335 val64 = readq(&bar0->xgxs_efifo_cfg);
5336 if (val64 != 0x000000001923141EULL) {
5337 fail = 1;
5338 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5339 }
5340
5341 val64 = 0x5A5A5A5A5A5A5A5AULL;
5342 writeq(val64, &bar0->xmsi_data);
5343 val64 = readq(&bar0->xmsi_data);
5344 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5345 fail = 1;
5346 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5347 }
5348
5349 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5350 writeq(val64, &bar0->xmsi_data);
5351 val64 = readq(&bar0->xmsi_data);
5352 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5353 fail = 1;
5354 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5355 }
5356
5357 *data = fail;
ad4ebed0 5358 return fail;
1da177e4
LT		 5359}
5360
5361/**
20346722 5362 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5363 * @sp : private member of the device structure, which is a pointer to the
5364 * s2io_nic structure.
5365 * @data:variable that returns the result of each of the test conducted by
5366 * the driver.
5367 * Description:
20346722 5368 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5369 * register.
5370 * Return value:
5371 * 0 on success.
5372 */
5373
1ee6dd77 5374static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5375{
5376 int fail = 0;
ad4ebed0 5377 u64 ret_data, org_4F0, org_7F0;
5378 u8 saved_4F0 = 0, saved_7F0 = 0;
5379 struct net_device *dev = sp->dev;
1da177e4
LT		 5380
5381 /* Test Write Error at offset 0 */
ad4ebed0 5382 /* Note that SPI interface allows write access to all areas
5383 * of EEPROM. Hence doing all negative testing only for Xframe I.
5384 */
5385 if (sp->device_type == XFRAME_I_DEVICE)
5386 if (!write_eeprom(sp, 0, 0, 3))
5387 fail = 1;
5388
5389 /* Save current values at offsets 0x4F0 and 0x7F0 */
5390 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5391 saved_4F0 = 1;
5392 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5393 saved_7F0 = 1;
1da177e4
LT		 5394
5395 /* Test Write at offset 4f0 */
ad4ebed0 5396 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 5397 fail = 1;
5398 if (read_eeprom(sp, 0x4F0, &ret_data))
5399 fail = 1;
5400
ad4ebed0 5401 if (ret_data != 0x012345) {
26b7625c
AM		 5402 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5403 "Data written %llx Data read %llx\n",
5404 dev->name, (unsigned long long)0x12345,
5405 (unsigned long long)ret_data);
1da177e4 5406 fail = 1;
ad4ebed0 5407 }
1da177e4
LT		 5408
5409 /* Reset the EEPROM data go FFFF */
ad4ebed0 5410 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 5411
5412 /* Test Write Request Error at offset 0x7c */
ad4ebed0 5413 if (sp->device_type == XFRAME_I_DEVICE)
5414 if (!write_eeprom(sp, 0x07C, 0, 3))
5415 fail = 1;
1da177e4 5416
ad4ebed0 5417 /* Test Write Request at offset 0x7f0 */
5418 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 5419 fail = 1;
ad4ebed0 5420 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 5421 fail = 1;
5422
ad4ebed0 5423 if (ret_data != 0x012345) {
26b7625c
AM		 5424 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5425 "Data written %llx Data read %llx\n",
5426 dev->name, (unsigned long long)0x12345,
5427 (unsigned long long)ret_data);
1da177e4 5428 fail = 1;
ad4ebed0 5429 }
1da177e4
LT		 5430
5431 /* Reset the EEPROM data go FFFF */
ad4ebed0 5432 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 5433
ad4ebed0 5434 if (sp->device_type == XFRAME_I_DEVICE) {
5435 /* Test Write Error at offset 0x80 */
5436 if (!write_eeprom(sp, 0x080, 0, 3))
5437 fail = 1;
1da177e4 5438
ad4ebed0 5439 /* Test Write Error at offset 0xfc */
5440 if (!write_eeprom(sp, 0x0FC, 0, 3))
5441 fail = 1;
1da177e4 5442
ad4ebed0 5443 /* Test Write Error at offset 0x100 */
5444 if (!write_eeprom(sp, 0x100, 0, 3))
5445 fail = 1;
1da177e4 5446
ad4ebed0 5447 /* Test Write Error at offset 4ec */
5448 if (!write_eeprom(sp, 0x4EC, 0, 3))
5449 fail = 1;
5450 }
5451
5452 /* Restore values at offsets 0x4F0 and 0x7F0 */
5453 if (saved_4F0)
5454 write_eeprom(sp, 0x4F0, org_4F0, 3);
5455 if (saved_7F0)
5456 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 5457
5458 *data = fail;
ad4ebed0 5459 return fail;
1da177e4
LT		 5460}
5461
5462/**
5463 * s2io_bist_test - invokes the MemBist test of the card .
20346722 5464 * @sp : private member of the device structure, which is a pointer to the
1da177e4 5465 * s2io_nic structure.
20346722 5466 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 5467 * the driver.
5468 * Description:
5469 * This invokes the MemBist test of the card. We give around
5470 * 2 secs time for the Test to complete. If it's still not complete
20346722 5471 * within this peiod, we consider that the test failed.
1da177e4
LT		 5472 * Return value:
5473 * 0 on success and -1 on failure.
5474 */
5475
1ee6dd77 5476static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5477{
5478 u8 bist = 0;
5479 int cnt = 0, ret = -1;
5480
5481 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5482 bist |= PCI_BIST_START;
5483 pci_write_config_word(sp->pdev, PCI_BIST, bist);
5484
5485 while (cnt < 20) {
5486 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5487 if (!(bist & PCI_BIST_START)) {
5488 *data = (bist & PCI_BIST_CODE_MASK);
5489 ret = 0;
5490 break;
5491 }
5492 msleep(100);
5493 cnt++;
5494 }
5495
5496 return ret;
5497}
5498
5499/**
20346722
K		 5500 * s2io-link_test - verifies the link state of the nic
5501 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 5502 * s2io_nic structure.
5503 * @data: variable that returns the result of each of the test conducted by
5504 * the driver.
5505 * Description:
20346722 5506 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 5507 * argument 'data' appropriately.
5508 * Return value:
5509 * 0 on success.
5510 */
5511
1ee6dd77 5512static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5513{
1ee6dd77 5514 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5515 u64 val64;
5516
5517 val64 = readq(&bar0->adapter_status);
c92ca04b 5518 if(!(LINK_IS_UP(val64)))
1da177e4 5519 *data = 1;
c92ca04b
AR		 5520 else
5521 *data = 0;
1da177e4 5522
b41477f3 5523 return *data;
1da177e4
LT		 5524}
5525
5526/**
20346722
K		 5527 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5528 * @sp - private member of the device structure, which is a pointer to the
1da177e4 5529 * s2io_nic structure.
20346722 5530 * @data - variable that returns the result of each of the test
1da177e4
LT		 5531 * conducted by the driver.
5532 * Description:
20346722 5533 * This is one of the offline test that tests the read and write
1da177e4
LT		 5534 * access to the RldRam chip on the NIC.
5535 * Return value:
5536 * 0 on success.
5537 */
5538
1ee6dd77 5539static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5540{
1ee6dd77 5541 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5542 u64 val64;
ad4ebed0 5543 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 5544
5545 val64 = readq(&bar0->adapter_control);
5546 val64 &= ~ADAPTER_ECC_EN;
5547 writeq(val64, &bar0->adapter_control);
5548
5549 val64 = readq(&bar0->mc_rldram_test_ctrl);
5550 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 5551 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5552
5553 val64 = readq(&bar0->mc_rldram_mrs);
5554 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5555 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5556
5557 val64 |= MC_RLDRAM_MRS_ENABLE;
5558 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5559
5560 while (iteration < 2) {
5561 val64 = 0x55555555aaaa0000ULL;
5562 if (iteration == 1) {
5563 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5564 }
5565 writeq(val64, &bar0->mc_rldram_test_d0);
5566
5567 val64 = 0xaaaa5a5555550000ULL;
5568 if (iteration == 1) {
5569 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5570 }
5571 writeq(val64, &bar0->mc_rldram_test_d1);
5572
5573 val64 = 0x55aaaaaaaa5a0000ULL;
5574 if (iteration == 1) {
5575 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5576 }
5577 writeq(val64, &bar0->mc_rldram_test_d2);
5578
ad4ebed0 5579 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 5580 writeq(val64, &bar0->mc_rldram_test_add);
5581
ad4ebed0 5582 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5583 MC_RLDRAM_TEST_GO;
5584 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5585
5586 for (cnt = 0; cnt < 5; cnt++) {
5587 val64 = readq(&bar0->mc_rldram_test_ctrl);
5588 if (val64 & MC_RLDRAM_TEST_DONE)
5589 break;
5590 msleep(200);
5591 }
5592
5593 if (cnt == 5)
5594 break;
5595
ad4ebed0 5596 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5597 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5598
5599 for (cnt = 0; cnt < 5; cnt++) {
5600 val64 = readq(&bar0->mc_rldram_test_ctrl);
5601 if (val64 & MC_RLDRAM_TEST_DONE)
5602 break;
5603 msleep(500);
5604 }
5605
5606 if (cnt == 5)
5607 break;
5608
5609 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 5610 if (!(val64 & MC_RLDRAM_TEST_PASS))
5611 test_fail = 1;
1da177e4
LT		 5612
5613 iteration++;
5614 }
5615
ad4ebed0 5616 *data = test_fail;
1da177e4 5617
ad4ebed0 5618 /* Bring the adapter out of test mode */
5619 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5620
5621 return test_fail;
1da177e4
LT		 5622}
5623
5624/**
5625 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5626 * @sp : private member of the device structure, which is a pointer to the
5627 * s2io_nic structure.
5628 * @ethtest : pointer to a ethtool command specific structure that will be
5629 * returned to the user.
20346722 5630 * @data : variable that returns the result of each of the test
1da177e4
LT		 5631 * conducted by the driver.
5632 * Description:
5633 * This function conducts 6 tests ( 4 offline and 2 online) to determine
5634 * the health of the card.
5635 * Return value:
5636 * void
5637 */
5638
5639static void s2io_ethtool_test(struct net_device *dev,
5640 struct ethtool_test *ethtest,
5641 uint64_t * data)
5642{
1ee6dd77 5643 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5644 int orig_state = netif_running(sp->dev);
5645
5646 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5647 /* Offline Tests. */
20346722 5648 if (orig_state)
1da177e4 5649 s2io_close(sp->dev);
1da177e4
LT		 5650
5651 if (s2io_register_test(sp, &data[0]))
5652 ethtest->flags |= ETH_TEST_FL_FAILED;
5653
5654 s2io_reset(sp);
1da177e4
LT		 5655
5656 if (s2io_rldram_test(sp, &data[3]))
5657 ethtest->flags |= ETH_TEST_FL_FAILED;
5658
5659 s2io_reset(sp);
1da177e4
LT		 5660
5661 if (s2io_eeprom_test(sp, &data[1]))
5662 ethtest->flags |= ETH_TEST_FL_FAILED;
5663
5664 if (s2io_bist_test(sp, &data[4]))
5665 ethtest->flags |= ETH_TEST_FL_FAILED;
5666
5667 if (orig_state)
5668 s2io_open(sp->dev);
5669
5670 data[2] = 0;
5671 } else {
5672 /* Online Tests. */
5673 if (!orig_state) {
5674 DBG_PRINT(ERR_DBG,
5675 "%s: is not up, cannot run test\n",
5676 dev->name);
5677 data[0] = -1;
5678 data[1] = -1;
5679 data[2] = -1;
5680 data[3] = -1;
5681 data[4] = -1;
5682 }
5683
5684 if (s2io_link_test(sp, &data[2]))
5685 ethtest->flags |= ETH_TEST_FL_FAILED;
5686
5687 data[0] = 0;
5688 data[1] = 0;
5689 data[3] = 0;
5690 data[4] = 0;
5691 }
5692}
5693
5694static void s2io_get_ethtool_stats(struct net_device *dev,
5695 struct ethtool_stats *estats,
5696 u64 * tmp_stats)
5697{
5698 int i = 0;
1ee6dd77
RB		 5699 struct s2io_nic *sp = dev->priv;
5700 struct stat_block *stat_info = sp->mac_control.stats_info;
1da177e4 5701
7ba013ac 5702 s2io_updt_stats(sp);
541ae68f
K		 5703 tmp_stats[i++] =
5704 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
5705 le32_to_cpu(stat_info->tmac_frms);
5706 tmp_stats[i++] =
5707 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5708 le32_to_cpu(stat_info->tmac_data_octets);
1da177e4 5709 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
541ae68f
K		 5710 tmp_stats[i++] =
5711 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5712 le32_to_cpu(stat_info->tmac_mcst_frms);
5713 tmp_stats[i++] =
5714 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5715 le32_to_cpu(stat_info->tmac_bcst_frms);
1da177e4 5716 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
bd1034f0
AR		 5717 tmp_stats[i++] =
5718 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5719 le32_to_cpu(stat_info->tmac_ttl_octets);
5720 tmp_stats[i++] =
5721 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5722 le32_to_cpu(stat_info->tmac_ucst_frms);
5723 tmp_stats[i++] =
5724 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5725 le32_to_cpu(stat_info->tmac_nucst_frms);
541ae68f
K		 5726 tmp_stats[i++] =
5727 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5728 le32_to_cpu(stat_info->tmac_any_err_frms);
bd1034f0 5729 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
1da177e4 5730 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
541ae68f
K		 5731 tmp_stats[i++] =
5732 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5733 le32_to_cpu(stat_info->tmac_vld_ip);
5734 tmp_stats[i++] =
5735 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5736 le32_to_cpu(stat_info->tmac_drop_ip);
5737 tmp_stats[i++] =
5738 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5739 le32_to_cpu(stat_info->tmac_icmp);
5740 tmp_stats[i++] =
5741 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5742 le32_to_cpu(stat_info->tmac_rst_tcp);
1da177e4 5743 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
541ae68f
K		 5744 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5745 le32_to_cpu(stat_info->tmac_udp);
5746 tmp_stats[i++] =
5747 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5748 le32_to_cpu(stat_info->rmac_vld_frms);
5749 tmp_stats[i++] =
5750 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5751 le32_to_cpu(stat_info->rmac_data_octets);
1da177e4
LT		 5752 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5753 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
541ae68f
K		 5754 tmp_stats[i++] =
5755 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5756 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5757 tmp_stats[i++] =
5758 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5759 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
1da177e4 5760 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
bd1034f0 5761 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
1da177e4
LT		 5762 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5763 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
bd1034f0
AR		 5764 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
5765 tmp_stats[i++] =
5766 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
5767 le32_to_cpu(stat_info->rmac_ttl_octets);
5768 tmp_stats[i++] =
5769 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
5770 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
5771 tmp_stats[i++] =
5772 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
5773 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
541ae68f
K		 5774 tmp_stats[i++] =
5775 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5776 le32_to_cpu(stat_info->rmac_discarded_frms);
bd1034f0
AR		 5777 tmp_stats[i++] =
5778 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
5779 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
5780 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
5781 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
541ae68f
K		 5782 tmp_stats[i++] =
5783 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5784 le32_to_cpu(stat_info->rmac_usized_frms);
5785 tmp_stats[i++] =
5786 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5787 le32_to_cpu(stat_info->rmac_osized_frms);
5788 tmp_stats[i++] =
5789 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5790 le32_to_cpu(stat_info->rmac_frag_frms);
5791 tmp_stats[i++] =
5792 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5793 le32_to_cpu(stat_info->rmac_jabber_frms);
bd1034f0
AR		 5794 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
5795 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
5796 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
5797 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
5798 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
5799 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
5800 tmp_stats[i++] =
5801 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
541ae68f 5802 le32_to_cpu(stat_info->rmac_ip);
1da177e4
LT		 5803 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5804 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
bd1034f0
AR		 5805 tmp_stats[i++] =
5806 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
541ae68f 5807 le32_to_cpu(stat_info->rmac_drop_ip);
bd1034f0
AR		 5808 tmp_stats[i++] =
5809 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
541ae68f 5810 le32_to_cpu(stat_info->rmac_icmp);
1da177e4 5811 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
bd1034f0
AR		 5812 tmp_stats[i++] =
5813 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
541ae68f
K		 5814 le32_to_cpu(stat_info->rmac_udp);
5815 tmp_stats[i++] =
5816 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5817 le32_to_cpu(stat_info->rmac_err_drp_udp);
bd1034f0
AR		 5818 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
5819 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
5820 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
5821 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
5822 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
5823 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
5824 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
5825 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
5826 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
5827 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
5828 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
5829 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
5830 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
5831 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
5832 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
5833 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
5834 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
541ae68f
K		 5835 tmp_stats[i++] =
5836 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5837 le32_to_cpu(stat_info->rmac_pause_cnt);
bd1034f0
AR		 5838 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
5839 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
541ae68f
K		 5840 tmp_stats[i++] =
5841 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5842 le32_to_cpu(stat_info->rmac_accepted_ip);
1da177e4 5843 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
bd1034f0
AR		 5844 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
5845 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
5846 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
5847 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
5848 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
5849 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
5850 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
5851 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
5852 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
5853 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
5854 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
5855 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
5856 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
5857 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
5858 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
5859 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
5860 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
5861 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
fa1f0cb3
SS		 5862
5863 /* Enhanced statistics exist only for Hercules */
5864 if(sp->device_type == XFRAME_II_DEVICE) {
5865 tmp_stats[i++] =
5866 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
5867 tmp_stats[i++] =
5868 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
5869 tmp_stats[i++] =
5870 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
5871 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
5872 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
5873 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
5874 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
5875 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
5876 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
5877 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
5878 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
5879 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
5880 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
5881 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
5882 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
5883 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
5884 }
5885
7ba013ac
K		 5886 tmp_stats[i++] = 0;
5887 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5888 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
bd1034f0
AR		 5889 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
5890 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
5891 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
5892 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
5893 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt;
5894 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
5895 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
5896 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
5897 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
5898 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
5899 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
5900 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
5901 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
5902 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
5903 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
5904 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
5905 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
7d3d0439
RA		 5906 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
5907 tmp_stats[i++] = stat_info->sw_stat.sending_both;
5908 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
5909 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
fe931395 5910 if (stat_info->sw_stat.num_aggregations) {
bd1034f0
AR		 5911 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
5912 int count = 0;
6aa20a22 5913 /*
bd1034f0
AR		 5914 * Since 64-bit divide does not work on all platforms,
5915 * do repeated subtraction.
5916 */
5917 while (tmp >= stat_info->sw_stat.num_aggregations) {
5918 tmp -= stat_info->sw_stat.num_aggregations;
5919 count++;
5920 }
5921 tmp_stats[i++] = count;
fe931395 5922 }
bd1034f0
AR		 5923 else
5924 tmp_stats[i++] = 0;
c53d4945
SH		 5925 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
5926 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
491976b2
SH		 5927 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
5928 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
5929 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
5930 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
5931 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
5932 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
5933
5934 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
5935 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
5936 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
5937 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
5938 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
5939
5940 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
5941 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
5942 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
5943 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
5944 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
5945 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
5946 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
5947 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
5948 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
1da177e4
LT		 5949}
5950
ac1f60db 5951static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4
LT		 5952{
5953 return (XENA_REG_SPACE);
5954}
5955
5956
ac1f60db 5957static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
1da177e4 5958{
1ee6dd77 5959 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5960
5961 return (sp->rx_csum);
5962}
ac1f60db
AB		 5963
5964static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 5965{
1ee6dd77 5966 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5967
5968 if (data)
5969 sp->rx_csum = 1;
5970 else
5971 sp->rx_csum = 0;
5972
5973 return 0;
5974}
ac1f60db
AB		 5975
5976static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4
LT		 5977{
5978 return (XENA_EEPROM_SPACE);
5979}
5980
ac1f60db 5981static int s2io_ethtool_self_test_count(struct net_device *dev)
1da177e4
LT		 5982{
5983 return (S2IO_TEST_LEN);
5984}
ac1f60db
AB		 5985
5986static void s2io_ethtool_get_strings(struct net_device *dev,
5987 u32 stringset, u8 * data)
1da177e4 5988{
fa1f0cb3
SS		 5989 int stat_size = 0;
5990 struct s2io_nic *sp = dev->priv;
5991
1da177e4
LT		 5992 switch (stringset) {
5993 case ETH_SS_TEST:
5994 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5995 break;
5996 case ETH_SS_STATS:
fa1f0cb3
SS		 5997 stat_size = sizeof(ethtool_xena_stats_keys);
5998 memcpy(data, &ethtool_xena_stats_keys,stat_size);
5999 if(sp->device_type == XFRAME_II_DEVICE) {
6000 memcpy(data + stat_size,
6001 &ethtool_enhanced_stats_keys,
6002 sizeof(ethtool_enhanced_stats_keys));
6003 stat_size += sizeof(ethtool_enhanced_stats_keys);
6004 }
6005
6006 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6007 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6008 }
6009}
1da177e4
LT		 6010static int s2io_ethtool_get_stats_count(struct net_device *dev)
6011{
fa1f0cb3
SS		 6012 struct s2io_nic *sp = dev->priv;
6013 int stat_count = 0;
6014 switch(sp->device_type) {
6015 case XFRAME_I_DEVICE:
6016 stat_count = XFRAME_I_STAT_LEN;
6017 break;
6018
6019 case XFRAME_II_DEVICE:
6020 stat_count = XFRAME_II_STAT_LEN;
6021 break;
6022 }
6023
6024 return stat_count;
1da177e4
LT		 6025}
6026
ac1f60db 6027static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 6028{
6029 if (data)
6030 dev->features |= NETIF_F_IP_CSUM;
6031 else
6032 dev->features &= ~NETIF_F_IP_CSUM;
6033
6034 return 0;
6035}
6036
75c30b13
AR		 6037static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6038{
6039 return (dev->features & NETIF_F_TSO) != 0;
6040}
6041static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6042{
6043 if (data)
6044 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6045 else
6046 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6047
6048 return 0;
6049}
1da177e4 6050
7282d491 6051static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6052 .get_settings = s2io_ethtool_gset,
6053 .set_settings = s2io_ethtool_sset,
6054 .get_drvinfo = s2io_ethtool_gdrvinfo,
6055 .get_regs_len = s2io_ethtool_get_regs_len,
6056 .get_regs = s2io_ethtool_gregs,
6057 .get_link = ethtool_op_get_link,
6058 .get_eeprom_len = s2io_get_eeprom_len,
6059 .get_eeprom = s2io_ethtool_geeprom,
6060 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6061 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6062 .get_pauseparam = s2io_ethtool_getpause_data,
6063 .set_pauseparam = s2io_ethtool_setpause_data,
6064 .get_rx_csum = s2io_ethtool_get_rx_csum,
6065 .set_rx_csum = s2io_ethtool_set_rx_csum,
6066 .get_tx_csum = ethtool_op_get_tx_csum,
6067 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6068 .get_sg = ethtool_op_get_sg,
6069 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 6070 .get_tso = s2io_ethtool_op_get_tso,
6071 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd
AR		 6072 .get_ufo = ethtool_op_get_ufo,
6073 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6074 .self_test_count = s2io_ethtool_self_test_count,
6075 .self_test = s2io_ethtool_test,
6076 .get_strings = s2io_ethtool_get_strings,
6077 .phys_id = s2io_ethtool_idnic,
6078 .get_stats_count = s2io_ethtool_get_stats_count,
6079 .get_ethtool_stats = s2io_get_ethtool_stats
6080};
6081
6082/**
20346722 6083 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6084 * @dev : Device pointer.
6085 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6086 * a proprietary structure used to pass information to the driver.
6087 * @cmd : This is used to distinguish between the different commands that
6088 * can be passed to the IOCTL functions.
6089 * Description:
20346722
K		 6090 * Currently there are no special functionality supported in IOCTL, hence
6091 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6092 */
6093
ac1f60db 6094static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6095{
6096 return -EOPNOTSUPP;
6097}
6098
6099/**
6100 * s2io_change_mtu - entry point to change MTU size for the device.
6101 * @dev : device pointer.
6102 * @new_mtu : the new MTU size for the device.
6103 * Description: A driver entry point to change MTU size for the device.
6104 * Before changing the MTU the device must be stopped.
6105 * Return value:
6106 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6107 * file on failure.
6108 */
6109
ac1f60db 6110static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6111{
1ee6dd77 6112 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6113
6114 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6115 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6116 dev->name);
6117 return -EPERM;
6118 }
6119
1da177e4 6120 dev->mtu = new_mtu;
d8892c6e 6121 if (netif_running(dev)) {
e6a8fee2 6122 s2io_card_down(sp);
d8892c6e
K		 6123 netif_stop_queue(dev);
6124 if (s2io_card_up(sp)) {
6125 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6126 __FUNCTION__);
6127 }
6128 if (netif_queue_stopped(dev))
6129 netif_wake_queue(dev);
6130 } else { /* Device is down */
1ee6dd77 6131 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e
K		 6132 u64 val64 = new_mtu;
6133
6134 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6135 }
1da177e4
LT		 6136
6137 return 0;
6138}
6139
6140/**
6141 * s2io_tasklet - Bottom half of the ISR.
6142 * @dev_adr : address of the device structure in dma_addr_t format.
6143 * Description:
6144 * This is the tasklet or the bottom half of the ISR. This is
20346722 6145 * an extension of the ISR which is scheduled by the scheduler to be run
1da177e4 6146 * when the load on the CPU is low. All low priority tasks of the ISR can
20346722 6147 * be pushed into the tasklet. For now the tasklet is used only to
1da177e4
LT		 6148 * replenish the Rx buffers in the Rx buffer descriptors.
6149 * Return value:
6150 * void.
6151 */
6152
6153static void s2io_tasklet(unsigned long dev_addr)
6154{
6155 struct net_device *dev = (struct net_device *) dev_addr;
1ee6dd77 6156 struct s2io_nic *sp = dev->priv;
1da177e4 6157 int i, ret;
1ee6dd77 6158 struct mac_info *mac_control;
1da177e4
LT		 6159 struct config_param *config;
6160
6161 mac_control = &sp->mac_control;
6162 config = &sp->config;
6163
6164 if (!TASKLET_IN_USE) {
6165 for (i = 0; i < config->rx_ring_num; i++) {
6166 ret = fill_rx_buffers(sp, i);
6167 if (ret == -ENOMEM) {
0c61ed5f 6168 DBG_PRINT(INFO_DBG, "%s: Out of ",
1da177e4 6169 dev->name);
491976b2 6170 DBG_PRINT(INFO_DBG, "memory in tasklet\n");
1da177e4
LT		 6171 break;
6172 } else if (ret == -EFILL) {
0c61ed5f 6173 DBG_PRINT(INFO_DBG,
1da177e4
LT		 6174 "%s: Rx Ring %d is full\n",
6175 dev->name, i);
6176 break;
6177 }
6178 }
6179 clear_bit(0, (&sp->tasklet_status));
6180 }
6181}
6182
6183/**
6184 * s2io_set_link - Set the LInk status
6185 * @data: long pointer to device private structue
6186 * Description: Sets the link status for the adapter
6187 */
6188
c4028958 6189static void s2io_set_link(struct work_struct *work)
1da177e4 6190{
1ee6dd77 6191 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
1da177e4 6192 struct net_device *dev = nic->dev;
1ee6dd77 6193 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6194 register u64 val64;
6195 u16 subid;
6196
22747d6b
FR		 6197 rtnl_lock();
6198
6199 if (!netif_running(dev))
6200 goto out_unlock;
6201
1da177e4
LT		 6202 if (test_and_set_bit(0, &(nic->link_state))) {
6203 /* The card is being reset, no point doing anything */
22747d6b 6204 goto out_unlock;
1da177e4
LT		 6205 }
6206
6207 subid = nic->pdev->subsystem_device;
a371a07d
K		 6208 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6209 /*
6210 * Allow a small delay for the NICs self initiated
6211 * cleanup to complete.
6212 */
6213 msleep(100);
6214 }
1da177e4
LT		 6215
6216 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6217 if (LINK_IS_UP(val64)) {
6218 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6219 if (verify_xena_quiescence(nic)) {
6220 val64 = readq(&bar0->adapter_control);
6221 val64 |= ADAPTER_CNTL_EN;
1da177e4 6222 writeq(val64, &bar0->adapter_control);
19a60522
SS		 6223 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6224 nic->device_type, subid)) {
6225 val64 = readq(&bar0->gpio_control);
6226 val64 |= GPIO_CTRL_GPIO_0;
6227 writeq(val64, &bar0->gpio_control);
6228 val64 = readq(&bar0->gpio_control);
6229 } else {
6230 val64 |= ADAPTER_LED_ON;
6231 writeq(val64, &bar0->adapter_control);
a371a07d 6232 }
1da177e4 6233 nic->device_enabled_once = TRUE;
19a60522
SS		 6234 } else {
6235 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6236 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6237 netif_stop_queue(dev);
1da177e4 6238 }
19a60522
SS		 6239 }
6240 val64 = readq(&bar0->adapter_status);
6241 if (!LINK_IS_UP(val64)) {
6242 DBG_PRINT(ERR_DBG, "%s:", dev->name);
6243 DBG_PRINT(ERR_DBG, " Link down after enabling ");
6244 DBG_PRINT(ERR_DBG, "device \n");
6245 } else
1da177e4 6246 s2io_link(nic, LINK_UP);
19a60522
SS		 6247 } else {
6248 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6249 subid)) {
6250 val64 = readq(&bar0->gpio_control);
6251 val64 &= ~GPIO_CTRL_GPIO_0;
6252 writeq(val64, &bar0->gpio_control);
6253 val64 = readq(&bar0->gpio_control);
1da177e4 6254 }
19a60522 6255 s2io_link(nic, LINK_DOWN);
1da177e4
LT		 6256 }
6257 clear_bit(0, &(nic->link_state));
22747d6b
FR		 6258
6259out_unlock:
d8d70caf 6260 rtnl_unlock();
1da177e4
LT		 6261}
6262
1ee6dd77
RB		 6263static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6264 struct buffAdd *ba,
6265 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6266 u64 *temp2, int size)
5d3213cc
AR		 6267{
6268 struct net_device *dev = sp->dev;
6269 struct sk_buff *frag_list;
6270
6271 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6272 /* allocate skb */
6273 if (*skb) {
6274 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6275 /*
6276 * As Rx frame are not going to be processed,
6277 * using same mapped address for the Rxd
6278 * buffer pointer
6279 */
1ee6dd77 6280 ((struct RxD1*)rxdp)->Buffer0_ptr = *temp0;
5d3213cc
AR		 6281 } else {
6282 *skb = dev_alloc_skb(size);
6283 if (!(*skb)) {
0c61ed5f 6284 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
c53d4945
SH		 6285 DBG_PRINT(INFO_DBG, "memory to allocate ");
6286 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6287 sp->mac_control.stats_info->sw_stat. \
6288 mem_alloc_fail_cnt++;
5d3213cc
AR		 6289 return -ENOMEM ;
6290 }
491976b2
SH		 6291 sp->mac_control.stats_info->sw_stat.mem_allocated
6292 += (*skb)->truesize;
5d3213cc
AR		 6293 /* storing the mapped addr in a temp variable
6294 * such it will be used for next rxd whose
6295 * Host Control is NULL
6296 */
1ee6dd77 6297 ((struct RxD1*)rxdp)->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6298 pci_map_single( sp->pdev, (*skb)->data,
6299 size - NET_IP_ALIGN,
6300 PCI_DMA_FROMDEVICE);
6301 rxdp->Host_Control = (unsigned long) (*skb);
6302 }
6303 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6304 /* Two buffer Mode */
6305 if (*skb) {
1ee6dd77
RB		 6306 ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2;
6307 ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0;
6308 ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1;
5d3213cc
AR		 6309 } else {
6310 *skb = dev_alloc_skb(size);
2ceaac75 6311 if (!(*skb)) {
c53d4945
SH		 6312 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6313 DBG_PRINT(INFO_DBG, "memory to allocate ");
6314 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6315 sp->mac_control.stats_info->sw_stat. \
6316 mem_alloc_fail_cnt++;
2ceaac75
DR		 6317 return -ENOMEM;
6318 }
491976b2
SH		 6319 sp->mac_control.stats_info->sw_stat.mem_allocated
6320 += (*skb)->truesize;
1ee6dd77 6321 ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6322 pci_map_single(sp->pdev, (*skb)->data,
6323 dev->mtu + 4,
6324 PCI_DMA_FROMDEVICE);
1ee6dd77 6325 ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6326 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6327 PCI_DMA_FROMDEVICE);
6328 rxdp->Host_Control = (unsigned long) (*skb);
6329
6330 /* Buffer-1 will be dummy buffer not used */
1ee6dd77 6331 ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1 =
5d3213cc
AR		 6332 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6333 PCI_DMA_FROMDEVICE);
6334 }
6335 } else if ((rxdp->Host_Control == 0)) {
6336 /* Three buffer mode */
6337 if (*skb) {
1ee6dd77
RB		 6338 ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0;
6339 ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1;
6340 ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2;
5d3213cc
AR		 6341 } else {
6342 *skb = dev_alloc_skb(size);
2ceaac75 6343 if (!(*skb)) {
c53d4945
SH		 6344 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6345 DBG_PRINT(INFO_DBG, "memory to allocate ");
6346 DBG_PRINT(INFO_DBG, "3 buf mode SKBs\n");
6347 sp->mac_control.stats_info->sw_stat. \
6348 mem_alloc_fail_cnt++;
2ceaac75
DR		 6349 return -ENOMEM;
6350 }
491976b2
SH		 6351 sp->mac_control.stats_info->sw_stat.mem_allocated
6352 += (*skb)->truesize;
1ee6dd77 6353 ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6354 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6355 PCI_DMA_FROMDEVICE);
6356 /* Buffer-1 receives L3/L4 headers */
1ee6dd77 6357 ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1 =
5d3213cc
AR		 6358 pci_map_single( sp->pdev, (*skb)->data,
6359 l3l4hdr_size + 4,
6360 PCI_DMA_FROMDEVICE);
6361 /*
6362 * skb_shinfo(skb)->frag_list will have L4
6363 * data payload
6364 */
6365 skb_shinfo(*skb)->frag_list = dev_alloc_skb(dev->mtu +
6366 ALIGN_SIZE);
6367 if (skb_shinfo(*skb)->frag_list == NULL) {
6368 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb \
6369 failed\n ", dev->name);
c53d4945
SH		 6370 sp->mac_control.stats_info->sw_stat. \
6371 mem_alloc_fail_cnt++;
5d3213cc
AR		 6372 return -ENOMEM ;
6373 }
6374 frag_list = skb_shinfo(*skb)->frag_list;
6375 frag_list->next = NULL;
491976b2
SH		 6376 sp->mac_control.stats_info->sw_stat.mem_allocated
6377 += frag_list->truesize;
5d3213cc
AR		 6378 /*
6379 * Buffer-2 receives L4 data payload
6380 */
1ee6dd77 6381 ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6382 pci_map_single( sp->pdev, frag_list->data,
6383 dev->mtu, PCI_DMA_FROMDEVICE);
6384 }
6385 }
6386 return 0;
6387}
1ee6dd77
RB		 6388static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6389 int size)
5d3213cc
AR		 6390{
6391 struct net_device *dev = sp->dev;
6392 if (sp->rxd_mode == RXD_MODE_1) {
6393 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6394 } else if (sp->rxd_mode == RXD_MODE_3B) {
6395 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6396 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6397 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6398 } else {
6399 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6400 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
6401 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
6402 }
6403}
6404
1ee6dd77 6405static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6406{
6407 int i, j, k, blk_cnt = 0, size;
1ee6dd77 6408 struct mac_info * mac_control = &sp->mac_control;
5d3213cc
AR		 6409 struct config_param *config = &sp->config;
6410 struct net_device *dev = sp->dev;
1ee6dd77 6411 struct RxD_t *rxdp = NULL;
5d3213cc 6412 struct sk_buff *skb = NULL;
1ee6dd77 6413 struct buffAdd *ba = NULL;
5d3213cc
AR		 6414 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6415
6416 /* Calculate the size based on ring mode */
6417 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6418 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6419 if (sp->rxd_mode == RXD_MODE_1)
6420 size += NET_IP_ALIGN;
6421 else if (sp->rxd_mode == RXD_MODE_3B)
6422 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6423 else
6424 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
6425
6426 for (i = 0; i < config->rx_ring_num; i++) {
6427 blk_cnt = config->rx_cfg[i].num_rxd /
6428 (rxd_count[sp->rxd_mode] +1);
6429
6430 for (j = 0; j < blk_cnt; j++) {
6431 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6432 rxdp = mac_control->rings[i].
6433 rx_blocks[j].rxds[k].virt_addr;
6434 if(sp->rxd_mode >= RXD_MODE_3A)
6435 ba = &mac_control->rings[i].ba[j][k];
ac1f90d6 6436 if (set_rxd_buffer_pointer(sp, rxdp, ba,
5d3213cc
AR		 6437 &skb,(u64 *)&temp0_64,
6438 (u64 *)&temp1_64,
ac1f90d6
SS		 6439 (u64 *)&temp2_64,
6440 size) == ENOMEM) {
6441 return 0;
6442 }
5d3213cc
AR		 6443
6444 set_rxd_buffer_size(sp, rxdp, size);
6445 wmb();
6446 /* flip the Ownership bit to Hardware */
6447 rxdp->Control_1 |= RXD_OWN_XENA;
6448 }
6449 }
6450 }
6451 return 0;
6452
6453}
6454
1ee6dd77 6455static int s2io_add_isr(struct s2io_nic * sp)
1da177e4 6456{
e6a8fee2 6457 int ret = 0;
c92ca04b 6458 struct net_device *dev = sp->dev;
e6a8fee2 6459 int err = 0;
1da177e4 6460
e6a8fee2
AR		 6461 if (sp->intr_type == MSI)
6462 ret = s2io_enable_msi(sp);
6463 else if (sp->intr_type == MSI_X)
6464 ret = s2io_enable_msi_x(sp);
6465 if (ret) {
6466 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6467 sp->intr_type = INTA;
20346722 6468 }
1da177e4 6469
1ee6dd77 6470 /* Store the values of the MSIX table in the struct s2io_nic structure */
e6a8fee2 6471 store_xmsi_data(sp);
c92ca04b 6472
e6a8fee2
AR		 6473 /* After proper initialization of H/W, register ISR */
6474 if (sp->intr_type == MSI) {
6475 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
6476 IRQF_SHARED, sp->name, dev);
6477 if (err) {
6478 pci_disable_msi(sp->pdev);
6479 DBG_PRINT(ERR_DBG, "%s: MSI registration failed\n",
6480 dev->name);
6481 return -1;
6482 }
6483 }
6484 if (sp->intr_type == MSI_X) {
fb6a825b 6485 int i, msix_tx_cnt=0,msix_rx_cnt=0;
c92ca04b 6486
e6a8fee2
AR		 6487 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6488 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6489 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6490 dev->name, i);
6491 err = request_irq(sp->entries[i].vector,
6492 s2io_msix_fifo_handle, 0, sp->desc[i],
6493 sp->s2io_entries[i].arg);
fb6a825b
SS		 6494 /* If either data or addr is zero print it */
6495 if(!(sp->msix_info[i].addr &&
6496 sp->msix_info[i].data)) {
6497 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6498 "Data:0x%lx\n",sp->desc[i],
6499 (unsigned long long)
6500 sp->msix_info[i].addr,
6501 (unsigned long)
6502 ntohl(sp->msix_info[i].data));
6503 } else {
6504 msix_tx_cnt++;
6505 }
e6a8fee2
AR		 6506 } else {
6507 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6508 dev->name, i);
6509 err = request_irq(sp->entries[i].vector,
6510 s2io_msix_ring_handle, 0, sp->desc[i],
6511 sp->s2io_entries[i].arg);
fb6a825b
SS		 6512 /* If either data or addr is zero print it */
6513 if(!(sp->msix_info[i].addr &&
6514 sp->msix_info[i].data)) {
6515 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6516 "Data:0x%lx\n",sp->desc[i],
6517 (unsigned long long)
6518 sp->msix_info[i].addr,
6519 (unsigned long)
6520 ntohl(sp->msix_info[i].data));
6521 } else {
6522 msix_rx_cnt++;
6523 }
c92ca04b 6524 }
e6a8fee2
AR		 6525 if (err) {
6526 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6527 "failed\n", dev->name, i);
6528 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6529 return -1;
6530 }
6531 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6532 }
fb6a825b
SS		 6533 printk("MSI-X-TX %d entries enabled\n",msix_tx_cnt);
6534 printk("MSI-X-RX %d entries enabled\n",msix_rx_cnt);
e6a8fee2
AR		 6535 }
6536 if (sp->intr_type == INTA) {
6537 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6538 sp->name, dev);
6539 if (err) {
6540 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6541 dev->name);
6542 return -1;
6543 }
6544 }
6545 return 0;
6546}
1ee6dd77 6547static void s2io_rem_isr(struct s2io_nic * sp)
e6a8fee2
AR		 6548{
6549 int cnt = 0;
6550 struct net_device *dev = sp->dev;
6551
6552 if (sp->intr_type == MSI_X) {
6553 int i;
6554 u16 msi_control;
6555
6556 for (i=1; (sp->s2io_entries[i].in_use ==
6557 MSIX_REGISTERED_SUCCESS); i++) {
6558 int vector = sp->entries[i].vector;
6559 void *arg = sp->s2io_entries[i].arg;
6560
6561 free_irq(vector, arg);
6562 }
6563 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6564 msi_control &= 0xFFFE; /* Disable MSI */
6565 pci_write_config_word(sp->pdev, 0x42, msi_control);
6566
6567 pci_disable_msix(sp->pdev);
6568 } else {
6569 free_irq(sp->pdev->irq, dev);
6570 if (sp->intr_type == MSI) {
6571 u16 val;
6572
6573 pci_disable_msi(sp->pdev);
6574 pci_read_config_word(sp->pdev, 0x4c, &val);
6575 val ^= 0x1;
6576 pci_write_config_word(sp->pdev, 0x4c, val);
c92ca04b
AR		 6577 }
6578 }
6579 /* Waiting till all Interrupt handlers are complete */
6580 cnt = 0;
6581 do {
6582 msleep(10);
6583 if (!atomic_read(&sp->isr_cnt))
6584 break;
6585 cnt++;
6586 } while(cnt < 5);
e6a8fee2
AR		 6587}
6588
d796fdb7 6589static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
e6a8fee2
AR		 6590{
6591 int cnt = 0;
1ee6dd77 6592 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2
AR		 6593 unsigned long flags;
6594 register u64 val64 = 0;
6595
6596 del_timer_sync(&sp->alarm_timer);
6597 /* If s2io_set_link task is executing, wait till it completes. */
6598 while (test_and_set_bit(0, &(sp->link_state))) {
6599 msleep(50);
6600 }
6601 atomic_set(&sp->card_state, CARD_DOWN);
6602
6603 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 6604 if (do_io)
6605 stop_nic(sp);
e6a8fee2
AR		 6606
6607 s2io_rem_isr(sp);
1da177e4
LT		 6608
6609 /* Kill tasklet. */
6610 tasklet_kill(&sp->task);
6611
6612 /* Check if the device is Quiescent and then Reset the NIC */
d796fdb7 6613 while(do_io) {
5d3213cc
AR		 6614 /* As per the HW requirement we need to replenish the
6615 * receive buffer to avoid the ring bump. Since there is
6616 * no intention of processing the Rx frame at this pointwe are
6617 * just settting the ownership bit of rxd in Each Rx
6618 * ring to HW and set the appropriate buffer size
6619 * based on the ring mode
6620 */
6621 rxd_owner_bit_reset(sp);
6622
1da177e4 6623 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6624 if (verify_xena_quiescence(sp)) {
6625 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
1da177e4
LT		 6626 break;
6627 }
6628
6629 msleep(50);
6630 cnt++;
6631 if (cnt == 10) {
6632 DBG_PRINT(ERR_DBG,
6633 "s2io_close:Device not Quiescent ");
6634 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6635 (unsigned long long) val64);
6636 break;
6637 }
d796fdb7
LV		 6638 }
6639 if (do_io)
6640 s2io_reset(sp);
1da177e4 6641
7ba013ac
K		 6642 spin_lock_irqsave(&sp->tx_lock, flags);
6643 /* Free all Tx buffers */
1da177e4 6644 free_tx_buffers(sp);
7ba013ac
K		 6645 spin_unlock_irqrestore(&sp->tx_lock, flags);
6646
6647 /* Free all Rx buffers */
6648 spin_lock_irqsave(&sp->rx_lock, flags);
1da177e4 6649 free_rx_buffers(sp);
7ba013ac 6650 spin_unlock_irqrestore(&sp->rx_lock, flags);
1da177e4 6651
1da177e4
LT		 6652 clear_bit(0, &(sp->link_state));
6653}
6654
d796fdb7
LV		 6655static void s2io_card_down(struct s2io_nic * sp)
6656{
6657 do_s2io_card_down(sp, 1);
6658}
6659
1ee6dd77 6660static int s2io_card_up(struct s2io_nic * sp)
1da177e4 6661{
cc6e7c44 6662 int i, ret = 0;
1ee6dd77 6663 struct mac_info *mac_control;
1da177e4
LT		 6664 struct config_param *config;
6665 struct net_device *dev = (struct net_device *) sp->dev;
e6a8fee2 6666 u16 interruptible;
1da177e4
LT		 6667
6668 /* Initialize the H/W I/O registers */
6669 if (init_nic(sp) != 0) {
6670 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6671 dev->name);
e6a8fee2 6672 s2io_reset(sp);
1da177e4
LT		 6673 return -ENODEV;
6674 }
6675
20346722
K		 6676 /*
6677 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 6678 * Rx ring and initializing buffers into 30 Rx blocks
6679 */
6680 mac_control = &sp->mac_control;
6681 config = &sp->config;
6682
6683 for (i = 0; i < config->rx_ring_num; i++) {
6684 if ((ret = fill_rx_buffers(sp, i))) {
6685 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6686 dev->name);
6687 s2io_reset(sp);
6688 free_rx_buffers(sp);
6689 return -ENOMEM;
6690 }
6691 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6692 atomic_read(&sp->rx_bufs_left[i]));
6693 }
19a60522
SS		 6694 /* Maintain the state prior to the open */
6695 if (sp->promisc_flg)
6696 sp->promisc_flg = 0;
6697 if (sp->m_cast_flg) {
6698 sp->m_cast_flg = 0;
6699 sp->all_multi_pos= 0;
6700 }
1da177e4
LT		 6701
6702 /* Setting its receive mode */
6703 s2io_set_multicast(dev);
6704
7d3d0439 6705 if (sp->lro) {
b41477f3 6706 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439
RA		 6707 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6708 /* Check if we can use(if specified) user provided value */
6709 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6710 sp->lro_max_aggr_per_sess = lro_max_pkts;
6711 }
6712
1da177e4
LT		 6713 /* Enable Rx Traffic and interrupts on the NIC */
6714 if (start_nic(sp)) {
6715 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 6716 s2io_reset(sp);
e6a8fee2
AR		 6717 free_rx_buffers(sp);
6718 return -ENODEV;
6719 }
6720
6721 /* Add interrupt service routine */
6722 if (s2io_add_isr(sp) != 0) {
6723 if (sp->intr_type == MSI_X)
6724 s2io_rem_isr(sp);
6725 s2io_reset(sp);
1da177e4
LT		 6726 free_rx_buffers(sp);
6727 return -ENODEV;
6728 }
6729
25fff88e
K		 6730 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6731
e6a8fee2
AR		 6732 /* Enable tasklet for the device */
6733 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6734
6735 /* Enable select interrupts */
6736 if (sp->intr_type != INTA)
6737 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6738 else {
6739 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6740 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
6741 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
6742 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6743 }
6744
6745
1da177e4
LT		 6746 atomic_set(&sp->card_state, CARD_UP);
6747 return 0;
6748}
6749
20346722 6750/**
1da177e4
LT		 6751 * s2io_restart_nic - Resets the NIC.
6752 * @data : long pointer to the device private structure
6753 * Description:
6754 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 6755 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 6756 * the run time of the watch dog routine which is run holding a
6757 * spin lock.
6758 */
6759
c4028958 6760static void s2io_restart_nic(struct work_struct *work)
1da177e4 6761{
1ee6dd77 6762 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 6763 struct net_device *dev = sp->dev;
1da177e4 6764
22747d6b
FR		 6765 rtnl_lock();
6766
6767 if (!netif_running(dev))
6768 goto out_unlock;
6769
e6a8fee2 6770 s2io_card_down(sp);
1da177e4
LT		 6771 if (s2io_card_up(sp)) {
6772 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6773 dev->name);
6774 }
6775 netif_wake_queue(dev);
6776 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
6777 dev->name);
22747d6b
FR		 6778out_unlock:
6779 rtnl_unlock();
1da177e4
LT		 6780}
6781
20346722
K		 6782/**
6783 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 6784 * @dev : Pointer to net device structure
6785 * Description:
6786 * This function is triggered if the Tx Queue is stopped
6787 * for a pre-defined amount of time when the Interface is still up.
6788 * If the Interface is jammed in such a situation, the hardware is
6789 * reset (by s2io_close) and restarted again (by s2io_open) to
6790 * overcome any problem that might have been caused in the hardware.
6791 * Return value:
6792 * void
6793 */
6794
6795static void s2io_tx_watchdog(struct net_device *dev)
6796{
1ee6dd77 6797 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6798
6799 if (netif_carrier_ok(dev)) {
c53d4945 6800 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
1da177e4 6801 schedule_work(&sp->rst_timer_task);
bd1034f0 6802 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 6803 }
6804}
6805
6806/**
6807 * rx_osm_handler - To perform some OS related operations on SKB.
6808 * @sp: private member of the device structure,pointer to s2io_nic structure.
6809 * @skb : the socket buffer pointer.
6810 * @len : length of the packet
6811 * @cksum : FCS checksum of the frame.
6812 * @ring_no : the ring from which this RxD was extracted.
20346722 6813 * Description:
b41477f3 6814 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 6815 * some OS related operations on the SKB before passing it to the upper
6816 * layers. It mainly checks if the checksum is OK, if so adds it to the
6817 * SKBs cksum variable, increments the Rx packet count and passes the SKB
6818 * to the upper layer. If the checksum is wrong, it increments the Rx
6819 * packet error count, frees the SKB and returns error.
6820 * Return value:
6821 * SUCCESS on success and -1 on failure.
6822 */
1ee6dd77 6823static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 6824{
1ee6dd77 6825 struct s2io_nic *sp = ring_data->nic;
1da177e4 6826 struct net_device *dev = (struct net_device *) sp->dev;
20346722
K		 6827 struct sk_buff *skb = (struct sk_buff *)
6828 ((unsigned long) rxdp->Host_Control);
6829 int ring_no = ring_data->ring_no;
1da177e4 6830 u16 l3_csum, l4_csum;
863c11a9 6831 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
1ee6dd77 6832 struct lro *lro;
f9046eb3 6833 u8 err_mask;
da6971d8 6834
20346722 6835 skb->dev = dev;
c92ca04b 6836
863c11a9 6837 if (err) {
bd1034f0
AR		 6838 /* Check for parity error */
6839 if (err & 0x1) {
6840 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
6841 }
f9046eb3
OH		 6842 err_mask = err >> 48;
6843 switch(err_mask) {
491976b2
SH		 6844 case 1:
6845 sp->mac_control.stats_info->sw_stat.
6846 rx_parity_err_cnt++;
6847 break;
6848
6849 case 2:
6850 sp->mac_control.stats_info->sw_stat.
6851 rx_abort_cnt++;
6852 break;
6853
6854 case 3:
6855 sp->mac_control.stats_info->sw_stat.
6856 rx_parity_abort_cnt++;
6857 break;
6858
6859 case 4:
6860 sp->mac_control.stats_info->sw_stat.
6861 rx_rda_fail_cnt++;
6862 break;
6863
6864 case 5:
6865 sp->mac_control.stats_info->sw_stat.
6866 rx_unkn_prot_cnt++;
6867 break;
6868
6869 case 6:
6870 sp->mac_control.stats_info->sw_stat.
6871 rx_fcs_err_cnt++;
6872 break;
bd1034f0 6873
491976b2
SH		 6874 case 7:
6875 sp->mac_control.stats_info->sw_stat.
6876 rx_buf_size_err_cnt++;
6877 break;
6878
6879 case 8:
6880 sp->mac_control.stats_info->sw_stat.
6881 rx_rxd_corrupt_cnt++;
6882 break;
6883
6884 case 15:
6885 sp->mac_control.stats_info->sw_stat.
6886 rx_unkn_err_cnt++;
6887 break;
6888 }
863c11a9
AR		 6889 /*
6890 * Drop the packet if bad transfer code. Exception being
6891 * 0x5, which could be due to unsupported IPv6 extension header.
6892 * In this case, we let stack handle the packet.
6893 * Note that in this case, since checksum will be incorrect,
6894 * stack will validate the same.
6895 */
f9046eb3
OH		 6896 if (err_mask != 0x5) {
6897 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
6898 dev->name, err_mask);
863c11a9 6899 sp->stats.rx_crc_errors++;
491976b2
SH		 6900 sp->mac_control.stats_info->sw_stat.mem_freed
6901 += skb->truesize;
863c11a9
AR		 6902 dev_kfree_skb(skb);
6903 atomic_dec(&sp->rx_bufs_left[ring_no]);
6904 rxdp->Host_Control = 0;
6905 return 0;
6906 }
20346722 6907 }
1da177e4 6908
20346722
K		 6909 /* Updating statistics */
6910 rxdp->Host_Control = 0;
da6971d8
AR		 6911 if (sp->rxd_mode == RXD_MODE_1) {
6912 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 6913
da6971d8
AR		 6914 sp->stats.rx_bytes += len;
6915 skb_put(skb, len);
6916
6917 } else if (sp->rxd_mode >= RXD_MODE_3A) {
6918 int get_block = ring_data->rx_curr_get_info.block_index;
6919 int get_off = ring_data->rx_curr_get_info.offset;
6920 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
6921 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
6922 unsigned char *buff = skb_push(skb, buf0_len);
6923
1ee6dd77 6924 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
da6971d8
AR		 6925 sp->stats.rx_bytes += buf0_len + buf2_len;
6926 memcpy(buff, ba->ba_0, buf0_len);
6927
6928 if (sp->rxd_mode == RXD_MODE_3A) {
6929 int buf1_len = RXD_GET_BUFFER1_SIZE_3(rxdp->Control_2);
6930
6931 skb_put(skb, buf1_len);
6932 skb->len += buf2_len;
6933 skb->data_len += buf2_len;
da6971d8
AR		 6934 skb_put(skb_shinfo(skb)->frag_list, buf2_len);
6935 sp->stats.rx_bytes += buf1_len;
6936
6937 } else
6938 skb_put(skb, buf2_len);
6939 }
20346722 6940
7d3d0439
RA		 6941 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
6942 (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722
K		 6943 (sp->rx_csum)) {
6944 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 6945 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
6946 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 6947 /*
1da177e4
LT		 6948 * NIC verifies if the Checksum of the received
6949 * frame is Ok or not and accordingly returns
6950 * a flag in the RxD.
6951 */
6952 skb->ip_summed = CHECKSUM_UNNECESSARY;
7d3d0439
RA		 6953 if (sp->lro) {
6954 u32 tcp_len;
6955 u8 *tcp;
6956 int ret = 0;
6957
6958 ret = s2io_club_tcp_session(skb->data, &tcp,
6959 &tcp_len, &lro, rxdp, sp);
6960 switch (ret) {
6961 case 3: /* Begin anew */
6962 lro->parent = skb;
6963 goto aggregate;
6964 case 1: /* Aggregate */
6965 {
6966 lro_append_pkt(sp, lro,
6967 skb, tcp_len);
6968 goto aggregate;
6969 }
6970 case 4: /* Flush session */
6971 {
6972 lro_append_pkt(sp, lro,
6973 skb, tcp_len);
6974 queue_rx_frame(lro->parent);
6975 clear_lro_session(lro);
6976 sp->mac_control.stats_info->
6977 sw_stat.flush_max_pkts++;
6978 goto aggregate;
6979 }
6980 case 2: /* Flush both */
6981 lro->parent->data_len =
6982 lro->frags_len;
6983 sp->mac_control.stats_info->
6984 sw_stat.sending_both++;
6985 queue_rx_frame(lro->parent);
6986 clear_lro_session(lro);
6987 goto send_up;
6988 case 0: /* sessions exceeded */
c92ca04b
AR		 6989 case -1: /* non-TCP or not
6990 * L2 aggregatable
6991 */
7d3d0439
RA		 6992 case 5: /*
6993 * First pkt in session not
6994 * L3/L4 aggregatable
6995 */
6996 break;
6997 default:
6998 DBG_PRINT(ERR_DBG,
6999 "%s: Samadhana!!\n",
7000 __FUNCTION__);
7001 BUG();
7002 }
7003 }
1da177e4 7004 } else {
20346722
K		 7005 /*
7006 * Packet with erroneous checksum, let the
1da177e4
LT		 7007 * upper layers deal with it.
7008 */
7009 skb->ip_summed = CHECKSUM_NONE;
7010 }
7011 } else {
7012 skb->ip_summed = CHECKSUM_NONE;
7013 }
491976b2 7014 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7d3d0439
RA		 7015 if (!sp->lro) {
7016 skb->protocol = eth_type_trans(skb, dev);
926930b2
SS		 7017 if ((sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2) &&
7018 vlan_strip_flag)) {
7d3d0439 7019 /* Queueing the vlan frame to the upper layer */
db874e65
SS		 7020 if (napi)
7021 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
7022 RXD_GET_VLAN_TAG(rxdp->Control_2));
7023 else
7024 vlan_hwaccel_rx(skb, sp->vlgrp,
7025 RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 7026 } else {
db874e65
SS		 7027 if (napi)
7028 netif_receive_skb(skb);
7029 else
7030 netif_rx(skb);
7d3d0439 7031 }
7d3d0439
RA		 7032 } else {
7033send_up:
7034 queue_rx_frame(skb);
6aa20a22 7035 }
1da177e4 7036 dev->last_rx = jiffies;
7d3d0439 7037aggregate:
1da177e4 7038 atomic_dec(&sp->rx_bufs_left[ring_no]);
1da177e4
LT		 7039 return SUCCESS;
7040}
7041
7042/**
7043 * s2io_link - stops/starts the Tx queue.
7044 * @sp : private member of the device structure, which is a pointer to the
7045 * s2io_nic structure.
7046 * @link : inidicates whether link is UP/DOWN.
7047 * Description:
7048 * This function stops/starts the Tx queue depending on whether the link
20346722
K		 7049 * status of the NIC is is down or up. This is called by the Alarm
7050 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7051 * Return value:
7052 * void.
7053 */
7054
1ee6dd77 7055static void s2io_link(struct s2io_nic * sp, int link)
1da177e4
LT		 7056{
7057 struct net_device *dev = (struct net_device *) sp->dev;
7058
7059 if (link != sp->last_link_state) {
7060 if (link == LINK_DOWN) {
7061 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7062 netif_carrier_off(dev);
491976b2
SH		 7063 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
7064 sp->mac_control.stats_info->sw_stat.link_up_time =
7065 jiffies - sp->start_time;
7066 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
1da177e4
LT		 7067 } else {
7068 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
491976b2
SH		 7069 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
7070 sp->mac_control.stats_info->sw_stat.link_down_time =
7071 jiffies - sp->start_time;
7072 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
1da177e4
LT		 7073 netif_carrier_on(dev);
7074 }
7075 }
7076 sp->last_link_state = link;
491976b2 7077 sp->start_time = jiffies;
1da177e4
LT		 7078}
7079
20346722
K		 7080/**
7081 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7082 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7083 * s2io_nic structure.
7084 * Description:
7085 * This function initializes a few of the PCI and PCI-X configuration registers
7086 * with recommended values.
7087 * Return value:
7088 * void
7089 */
7090
1ee6dd77 7091static void s2io_init_pci(struct s2io_nic * sp)
1da177e4 7092{
20346722 7093 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7094
7095 /* Enable Data Parity Error Recovery in PCI-X command register. */
7096 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7097 &(pcix_cmd));
1da177e4 7098 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7099 (pcix_cmd | 1));
1da177e4 7100 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7101 &(pcix_cmd));
1da177e4
LT		 7102
7103 /* Set the PErr Response bit in PCI command register. */
7104 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7105 pci_write_config_word(sp->pdev, PCI_COMMAND,
7106 (pci_cmd | PCI_COMMAND_PARITY));
7107 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7108}
7109
9dc737a7
AR		 7110static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
7111{
7112 if ( tx_fifo_num > 8) {
7113 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
7114 "supported\n");
7115 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
7116 tx_fifo_num = 8;
7117 }
7118 if ( rx_ring_num > 8) {
7119 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
7120 "supported\n");
7121 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
7122 rx_ring_num = 8;
7123 }
db874e65
SS		 7124 if (*dev_intr_type != INTA)
7125 napi = 0;
7126
9dc737a7
AR		 7127#ifndef CONFIG_PCI_MSI
7128 if (*dev_intr_type != INTA) {
7129 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
7130 "MSI/MSI-X. Defaulting to INTA\n");
7131 *dev_intr_type = INTA;
7132 }
7133#else
7134 if (*dev_intr_type > MSI_X) {
7135 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7136 "Defaulting to INTA\n");
7137 *dev_intr_type = INTA;
7138 }
7139#endif
7140 if ((*dev_intr_type == MSI_X) &&
7141 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7142 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 7143 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
9dc737a7
AR		 7144 "Defaulting to INTA\n");
7145 *dev_intr_type = INTA;
7146 }
fb6a825b 7147
9dc737a7
AR		 7148 if (rx_ring_mode > 3) {
7149 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
7150 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 3-buffer mode\n");
7151 rx_ring_mode = 3;
7152 }
7153 return SUCCESS;
7154}
7155
9fc93a41
SS		 7156/**
7157 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7158 * or Traffic class respectively.
7159 * @nic: device peivate variable
7160 * Description: The function configures the receive steering to
7161 * desired receive ring.
7162 * Return Value: SUCCESS on success and
7163 * '-1' on failure (endian settings incorrect).
7164 */
7165static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7166{
7167 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7168 register u64 val64 = 0;
7169
7170 if (ds_codepoint > 63)
7171 return FAILURE;
7172
7173 val64 = RTS_DS_MEM_DATA(ring);
7174 writeq(val64, &bar0->rts_ds_mem_data);
7175
7176 val64 = RTS_DS_MEM_CTRL_WE |
7177 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7178 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7179
7180 writeq(val64, &bar0->rts_ds_mem_ctrl);
7181
7182 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7183 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7184 S2IO_BIT_RESET);
7185}
7186
1da177e4 7187/**
20346722 7188 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7189 * @pdev : structure containing the PCI related information of the device.
7190 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7191 * Description:
7192 * The function initializes an adapter identified by the pci_dec structure.
20346722
K		 7193 * All OS related initialization including memory and device structure and
7194 * initlaization of the device private variable is done. Also the swapper
7195 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7196 * registers of the device.
7197 * Return value:
7198 * returns 0 on success and negative on failure.
7199 */
7200
7201static int __devinit
7202s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7203{
1ee6dd77 7204 struct s2io_nic *sp;
1da177e4 7205 struct net_device *dev;
1da177e4
LT		 7206 int i, j, ret;
7207 int dma_flag = FALSE;
7208 u32 mac_up, mac_down;
7209 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7210 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7211 u16 subid;
1ee6dd77 7212 struct mac_info *mac_control;
1da177e4 7213 struct config_param *config;
541ae68f 7214 int mode;
cc6e7c44 7215 u8 dev_intr_type = intr_type;
1da177e4 7216
9dc737a7
AR		 7217 if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
7218 return ret;
1da177e4
LT		 7219
7220 if ((ret = pci_enable_device(pdev))) {
7221 DBG_PRINT(ERR_DBG,
7222 "s2io_init_nic: pci_enable_device failed\n");
7223 return ret;
7224 }
7225
1e7f0bd8 7226 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7227 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7228 dma_flag = TRUE;
1da177e4 7229 if (pci_set_consistent_dma_mask
1e7f0bd8 7230 (pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7231 DBG_PRINT(ERR_DBG,
7232 "Unable to obtain 64bit DMA for \
7233 consistent allocations\n");
7234 pci_disable_device(pdev);
7235 return -ENOMEM;
7236 }
1e7f0bd8 7237 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 7238 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7239 } else {
7240 pci_disable_device(pdev);
7241 return -ENOMEM;
7242 }
cc6e7c44
RA		 7243 if (dev_intr_type != MSI_X) {
7244 if (pci_request_regions(pdev, s2io_driver_name)) {
b41477f3
AR		 7245 DBG_PRINT(ERR_DBG, "Request Regions failed\n");
7246 pci_disable_device(pdev);
cc6e7c44
RA		 7247 return -ENODEV;
7248 }
7249 }
7250 else {
7251 if (!(request_mem_region(pci_resource_start(pdev, 0),
7252 pci_resource_len(pdev, 0), s2io_driver_name))) {
7253 DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
7254 pci_disable_device(pdev);
7255 return -ENODEV;
7256 }
7257 if (!(request_mem_region(pci_resource_start(pdev, 2),
7258 pci_resource_len(pdev, 2), s2io_driver_name))) {
7259 DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
7260 release_mem_region(pci_resource_start(pdev, 0),
7261 pci_resource_len(pdev, 0));
7262 pci_disable_device(pdev);
7263 return -ENODEV;
7264 }
1da177e4
LT		 7265 }
7266
1ee6dd77 7267 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7268 if (dev == NULL) {
7269 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7270 pci_disable_device(pdev);
7271 pci_release_regions(pdev);
7272 return -ENODEV;
7273 }
7274
7275 pci_set_master(pdev);
7276 pci_set_drvdata(pdev, dev);
7277 SET_MODULE_OWNER(dev);
7278 SET_NETDEV_DEV(dev, &pdev->dev);
7279
7280 /* Private member variable initialized to s2io NIC structure */
7281 sp = dev->priv;
1ee6dd77 7282 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7283 sp->dev = dev;
7284 sp->pdev = pdev;
1da177e4 7285 sp->high_dma_flag = dma_flag;
1da177e4 7286 sp->device_enabled_once = FALSE;
da6971d8
AR		 7287 if (rx_ring_mode == 1)
7288 sp->rxd_mode = RXD_MODE_1;
7289 if (rx_ring_mode == 2)
7290 sp->rxd_mode = RXD_MODE_3B;
7291 if (rx_ring_mode == 3)
7292 sp->rxd_mode = RXD_MODE_3A;
7293
cc6e7c44 7294 sp->intr_type = dev_intr_type;
1da177e4 7295
541ae68f
K		 7296 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7297 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7298 sp->device_type = XFRAME_II_DEVICE;
7299 else
7300 sp->device_type = XFRAME_I_DEVICE;
7301
7d3d0439 7302 sp->lro = lro;
6aa20a22 7303
1da177e4
LT		 7304 /* Initialize some PCI/PCI-X fields of the NIC. */
7305 s2io_init_pci(sp);
7306
20346722 7307 /*
1da177e4 7308 * Setting the device configuration parameters.
20346722
K		 7309 * Most of these parameters can be specified by the user during
7310 * module insertion as they are module loadable parameters. If
7311 * these parameters are not not specified during load time, they
1da177e4
LT		 7312 * are initialized with default values.
7313 */
7314 mac_control = &sp->mac_control;
7315 config = &sp->config;
7316
7317 /* Tx side parameters. */
1da177e4
LT		 7318 config->tx_fifo_num = tx_fifo_num;
7319 for (i = 0; i < MAX_TX_FIFOS; i++) {
7320 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7321 config->tx_cfg[i].fifo_priority = i;
7322 }
7323
20346722
K		 7324 /* mapping the QoS priority to the configured fifos */
7325 for (i = 0; i < MAX_TX_FIFOS; i++)
7326 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
7327
1da177e4
LT		 7328 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7329 for (i = 0; i < config->tx_fifo_num; i++) {
7330 config->tx_cfg[i].f_no_snoop =
7331 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7332 if (config->tx_cfg[i].fifo_len < 65) {
7333 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7334 break;
7335 }
7336 }
fed5eccd
AR		 7337 /* + 2 because one Txd for skb->data and one Txd for UFO */
7338 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7339
7340 /* Rx side parameters. */
1da177e4
LT		 7341 config->rx_ring_num = rx_ring_num;
7342 for (i = 0; i < MAX_RX_RINGS; i++) {
7343 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
da6971d8 7344 (rxd_count[sp->rxd_mode] + 1);
1da177e4
LT		 7345 config->rx_cfg[i].ring_priority = i;
7346 }
7347
7348 for (i = 0; i < rx_ring_num; i++) {
7349 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7350 config->rx_cfg[i].f_no_snoop =
7351 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7352 }
7353
7354 /* Setting Mac Control parameters */
7355 mac_control->rmac_pause_time = rmac_pause_time;
7356 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7357 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7358
7359
7360 /* Initialize Ring buffer parameters. */
7361 for (i = 0; i < config->rx_ring_num; i++)
7362 atomic_set(&sp->rx_bufs_left[i], 0);
7363
7ba013ac
K		 7364 /* Initialize the number of ISRs currently running */
7365 atomic_set(&sp->isr_cnt, 0);
7366
1da177e4
LT		 7367 /* initialize the shared memory used by the NIC and the host */
7368 if (init_shared_mem(sp)) {
7369 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
b41477f3 7370 dev->name);
1da177e4
LT		 7371 ret = -ENOMEM;
7372 goto mem_alloc_failed;
7373 }
7374
7375 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7376 pci_resource_len(pdev, 0));
7377 if (!sp->bar0) {
19a60522 7378 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7379 dev->name);
7380 ret = -ENOMEM;
7381 goto bar0_remap_failed;
7382 }
7383
7384 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7385 pci_resource_len(pdev, 2));
7386 if (!sp->bar1) {
19a60522 7387 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7388 dev->name);
7389 ret = -ENOMEM;
7390 goto bar1_remap_failed;
7391 }
7392
7393 dev->irq = pdev->irq;
7394 dev->base_addr = (unsigned long) sp->bar0;
7395
7396 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7397 for (j = 0; j < MAX_TX_FIFOS; j++) {
1ee6dd77 7398 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
1da177e4
LT		 7399 (sp->bar1 + (j * 0x00020000));
7400 }
7401
7402 /* Driver entry points */
7403 dev->open = &s2io_open;
7404 dev->stop = &s2io_close;
7405 dev->hard_start_xmit = &s2io_xmit;
7406 dev->get_stats = &s2io_get_stats;
7407 dev->set_multicast_list = &s2io_set_multicast;
7408 dev->do_ioctl = &s2io_ioctl;
7409 dev->change_mtu = &s2io_change_mtu;
7410 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02
K		 7411 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7412 dev->vlan_rx_register = s2io_vlan_rx_register;
20346722 7413
1da177e4
LT		 7414 /*
7415 * will use eth_mac_addr() for dev->set_mac_address
7416 * mac address will be set every time dev->open() is called
7417 */
1da177e4 7418 dev->poll = s2io_poll;
20346722 7419 dev->weight = 32;
1da177e4 7420
612eff0e
BH		 7421#ifdef CONFIG_NET_POLL_CONTROLLER
7422 dev->poll_controller = s2io_netpoll;
7423#endif
7424
1da177e4
LT		 7425 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7426 if (sp->high_dma_flag == TRUE)
7427 dev->features |= NETIF_F_HIGHDMA;
1da177e4 7428 dev->features |= NETIF_F_TSO;
f83ef8c0 7429 dev->features |= NETIF_F_TSO6;
db874e65 7430 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 7431 dev->features |= NETIF_F_UFO;
7432 dev->features |= NETIF_F_HW_CSUM;
7433 }
1da177e4
LT		 7434
7435 dev->tx_timeout = &s2io_tx_watchdog;
7436 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 7437 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7438 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 7439
e960fc5c 7440 pci_save_state(sp->pdev);
1da177e4
LT		 7441
7442 /* Setting swapper control on the NIC, for proper reset operation */
7443 if (s2io_set_swapper(sp)) {
7444 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7445 dev->name);
7446 ret = -EAGAIN;
7447 goto set_swap_failed;
7448 }
7449
541ae68f
K		 7450 /* Verify if the Herc works on the slot its placed into */
7451 if (sp->device_type & XFRAME_II_DEVICE) {
7452 mode = s2io_verify_pci_mode(sp);
7453 if (mode < 0) {
7454 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7455 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7456 ret = -EBADSLT;
7457 goto set_swap_failed;
7458 }
7459 }
7460
7461 /* Not needed for Herc */
7462 if (sp->device_type & XFRAME_I_DEVICE) {
7463 /*
7464 * Fix for all "FFs" MAC address problems observed on
7465 * Alpha platforms
7466 */
7467 fix_mac_address(sp);
7468 s2io_reset(sp);
7469 }
1da177e4
LT		 7470
7471 /*
1da177e4
LT		 7472 * MAC address initialization.
7473 * For now only one mac address will be read and used.
7474 */
7475 bar0 = sp->bar0;
7476 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7477 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7478 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 7479 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41 7480 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
1da177e4
LT		 7481 tmp64 = readq(&bar0->rmac_addr_data0_mem);
7482 mac_down = (u32) tmp64;
7483 mac_up = (u32) (tmp64 >> 32);
7484
1da177e4
LT		 7485 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7486 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7487 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7488 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7489 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7490 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7491
1da177e4
LT		 7492 /* Set the factory defined MAC address initially */
7493 dev->addr_len = ETH_ALEN;
7494 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7495
b41477f3
AR		 7496 /* reset Nic and bring it to known state */
7497 s2io_reset(sp);
7498
1da177e4 7499 /*
20346722 7500 * Initialize the tasklet status and link state flags
541ae68f 7501 * and the card state parameter
1da177e4
LT		 7502 */
7503 atomic_set(&(sp->card_state), 0);
7504 sp->tasklet_status = 0;
7505 sp->link_state = 0;
7506
1da177e4
LT		 7507 /* Initialize spinlocks */
7508 spin_lock_init(&sp->tx_lock);
db874e65
SS		 7509
7510 if (!napi)
7511 spin_lock_init(&sp->put_lock);
7ba013ac 7512 spin_lock_init(&sp->rx_lock);
1da177e4 7513
20346722
K		 7514 /*
7515 * SXE-002: Configure link and activity LED to init state
7516 * on driver load.
1da177e4
LT		 7517 */
7518 subid = sp->pdev->subsystem_device;
7519 if ((subid & 0xFF) >= 0x07) {
7520 val64 = readq(&bar0->gpio_control);
7521 val64 |= 0x0000800000000000ULL;
7522 writeq(val64, &bar0->gpio_control);
7523 val64 = 0x0411040400000000ULL;
7524 writeq(val64, (void __iomem *) bar0 + 0x2700);
7525 val64 = readq(&bar0->gpio_control);
7526 }
7527
7528 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
7529
7530 if (register_netdev(dev)) {
7531 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7532 ret = -ENODEV;
7533 goto register_failed;
7534 }
9dc737a7 7535 s2io_vpd_read(sp);
0c61ed5f 7536 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
b41477f3 7537 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
44c10138 7538 sp->product_name, pdev->revision);
b41477f3
AR		 7539 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7540 s2io_driver_version);
9dc737a7 7541 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
19a60522 7542 "%02x:%02x:%02x:%02x:%02x:%02x", dev->name,
541ae68f
K		 7543 sp->def_mac_addr[0].mac_addr[0],
7544 sp->def_mac_addr[0].mac_addr[1],
7545 sp->def_mac_addr[0].mac_addr[2],
7546 sp->def_mac_addr[0].mac_addr[3],
7547 sp->def_mac_addr[0].mac_addr[4],
7548 sp->def_mac_addr[0].mac_addr[5]);
19a60522 7549 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
9dc737a7 7550 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 7551 mode = s2io_print_pci_mode(sp);
541ae68f 7552 if (mode < 0) {
9dc737a7 7553 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 7554 ret = -EBADSLT;
9dc737a7 7555 unregister_netdev(dev);
541ae68f
K		 7556 goto set_swap_failed;
7557 }
541ae68f 7558 }
9dc737a7
AR		 7559 switch(sp->rxd_mode) {
7560 case RXD_MODE_1:
7561 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7562 dev->name);
7563 break;
7564 case RXD_MODE_3B:
7565 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7566 dev->name);
7567 break;
7568 case RXD_MODE_3A:
7569 DBG_PRINT(ERR_DBG, "%s: 3-Buffer receive mode enabled\n",
7570 dev->name);
7571 break;
7572 }
db874e65
SS		 7573
7574 if (napi)
7575 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
9dc737a7
AR		 7576 switch(sp->intr_type) {
7577 case INTA:
7578 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7579 break;
7580 case MSI:
7581 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI\n", dev->name);
7582 break;
7583 case MSI_X:
7584 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7585 break;
7586 }
7d3d0439
RA		 7587 if (sp->lro)
7588 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 7589 dev->name);
db874e65
SS		 7590 if (ufo)
7591 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
7592 " enabled\n", dev->name);
7ba013ac 7593 /* Initialize device name */
9dc737a7 7594 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 7595
b6e3f982
K		 7596 /* Initialize bimodal Interrupts */
7597 sp->config.bimodal = bimodal;
7598 if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
7599 sp->config.bimodal = 0;
7600 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
7601 dev->name);
7602 }
7603
20346722
K		 7604 /*
7605 * Make Link state as off at this point, when the Link change
7606 * interrupt comes the state will be automatically changed to
1da177e4
LT		 7607 * the right state.
7608 */
7609 netif_carrier_off(dev);
1da177e4
LT		 7610
7611 return 0;
7612
7613 register_failed:
7614 set_swap_failed:
7615 iounmap(sp->bar1);
7616 bar1_remap_failed:
7617 iounmap(sp->bar0);
7618 bar0_remap_failed:
7619 mem_alloc_failed:
7620 free_shared_mem(sp);
7621 pci_disable_device(pdev);
cc6e7c44
RA		 7622 if (dev_intr_type != MSI_X)
7623 pci_release_regions(pdev);
7624 else {
7625 release_mem_region(pci_resource_start(pdev, 0),
7626 pci_resource_len(pdev, 0));
7627 release_mem_region(pci_resource_start(pdev, 2),
7628 pci_resource_len(pdev, 2));
7629 }
1da177e4
LT		 7630 pci_set_drvdata(pdev, NULL);
7631 free_netdev(dev);
7632
7633 return ret;
7634}
7635
7636/**
20346722 7637 * s2io_rem_nic - Free the PCI device
1da177e4 7638 * @pdev: structure containing the PCI related information of the device.
20346722 7639 * Description: This function is called by the Pci subsystem to release a
1da177e4 7640 * PCI device and free up all resource held up by the device. This could
20346722 7641 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 7642 * from memory.
7643 */
7644
7645static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7646{
7647 struct net_device *dev =
7648 (struct net_device *) pci_get_drvdata(pdev);
1ee6dd77 7649 struct s2io_nic *sp;
1da177e4
LT		 7650
7651 if (dev == NULL) {
7652 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7653 return;
7654 }
7655
22747d6b
FR		 7656 flush_scheduled_work();
7657
1da177e4
LT		 7658 sp = dev->priv;
7659 unregister_netdev(dev);
7660
7661 free_shared_mem(sp);
7662 iounmap(sp->bar0);
7663 iounmap(sp->bar1);
cc6e7c44
RA		 7664 if (sp->intr_type != MSI_X)
7665 pci_release_regions(pdev);
7666 else {
7667 release_mem_region(pci_resource_start(pdev, 0),
7668 pci_resource_len(pdev, 0));
7669 release_mem_region(pci_resource_start(pdev, 2),
7670 pci_resource_len(pdev, 2));
7671 }
1da177e4 7672 pci_set_drvdata(pdev, NULL);
1da177e4 7673 free_netdev(dev);
19a60522 7674 pci_disable_device(pdev);
1da177e4
LT		 7675}
7676
7677/**
7678 * s2io_starter - Entry point for the driver
7679 * Description: This function is the entry point for the driver. It verifies
7680 * the module loadable parameters and initializes PCI configuration space.
7681 */
7682
7683int __init s2io_starter(void)
7684{
29917620 7685 return pci_register_driver(&s2io_driver);
1da177e4
LT		 7686}
7687
7688/**
20346722 7689 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 7690 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7691 */
7692
372cc597 7693static __exit void s2io_closer(void)
1da177e4
LT		 7694{
7695 pci_unregister_driver(&s2io_driver);
7696 DBG_PRINT(INIT_DBG, "cleanup done\n");
7697}
7698
7699module_init(s2io_starter);
7700module_exit(s2io_closer);
7d3d0439 7701
6aa20a22 7702static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
1ee6dd77 7703 struct tcphdr **tcp, struct RxD_t *rxdp)
7d3d0439
RA		 7704{
7705 int ip_off;
7706 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7707
7708 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7709 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7710 __FUNCTION__);
7711 return -1;
7712 }
7713
7714 /* TODO:
7715 * By default the VLAN field in the MAC is stripped by the card, if this
7716 * feature is turned off in rx_pa_cfg register, then the ip_off field
7717 * has to be shifted by a further 2 bytes
7718 */
7719 switch (l2_type) {
7720 case 0: /* DIX type */
7721 case 4: /* DIX type with VLAN */
7722 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7723 break;
7724 /* LLC, SNAP etc are considered non-mergeable */
7725 default:
7726 return -1;
7727 }
7728
7729 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7730 ip_len = (u8)((*ip)->ihl);
7731 ip_len <<= 2;
7732 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7733
7734 return 0;
7735}
7736
1ee6dd77 7737static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 7738 struct tcphdr *tcp)
7739{
7740 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7741 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7742 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7743 return -1;
7744 return 0;
7745}
7746
7747static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7748{
7749 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7750}
7751
1ee6dd77 7752static void initiate_new_session(struct lro *lro, u8 *l2h,
7d3d0439
RA		 7753 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7754{
7755 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7756 lro->l2h = l2h;
7757 lro->iph = ip;
7758 lro->tcph = tcp;
7759 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7760 lro->tcp_ack = ntohl(tcp->ack_seq);
7761 lro->sg_num = 1;
7762 lro->total_len = ntohs(ip->tot_len);
7763 lro->frags_len = 0;
6aa20a22 7764 /*
7d3d0439
RA		 7765 * check if we saw TCP timestamp. Other consistency checks have
7766 * already been done.
7767 */
7768 if (tcp->doff == 8) {
7769 u32 *ptr;
7770 ptr = (u32 *)(tcp+1);
7771 lro->saw_ts = 1;
7772 lro->cur_tsval = *(ptr+1);
7773 lro->cur_tsecr = *(ptr+2);
7774 }
7775 lro->in_use = 1;
7776}
7777
1ee6dd77 7778static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 7779{
7780 struct iphdr *ip = lro->iph;
7781 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 7782 __sum16 nchk;
1ee6dd77 7783 struct stat_block *statinfo = sp->mac_control.stats_info;
7d3d0439
RA		 7784 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7785
7786 /* Update L3 header */
7787 ip->tot_len = htons(lro->total_len);
7788 ip->check = 0;
7789 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7790 ip->check = nchk;
7791
7792 /* Update L4 header */
7793 tcp->ack_seq = lro->tcp_ack;
7794 tcp->window = lro->window;
7795
7796 /* Update tsecr field if this session has timestamps enabled */
7797 if (lro->saw_ts) {
7798 u32 *ptr = (u32 *)(tcp + 1);
7799 *(ptr+2) = lro->cur_tsecr;
7800 }
7801
7802 /* Update counters required for calculation of
7803 * average no. of packets aggregated.
7804 */
7805 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
7806 statinfo->sw_stat.num_aggregations++;
7807}
7808
1ee6dd77 7809static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 7810 struct tcphdr *tcp, u32 l4_pyld)
7811{
7812 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7813 lro->total_len += l4_pyld;
7814 lro->frags_len += l4_pyld;
7815 lro->tcp_next_seq += l4_pyld;
7816 lro->sg_num++;
7817
7818 /* Update ack seq no. and window ad(from this pkt) in LRO object */
7819 lro->tcp_ack = tcp->ack_seq;
7820 lro->window = tcp->window;
6aa20a22 7821
7d3d0439
RA		 7822 if (lro->saw_ts) {
7823 u32 *ptr;
7824 /* Update tsecr and tsval from this packet */
7825 ptr = (u32 *) (tcp + 1);
6aa20a22 7826 lro->cur_tsval = *(ptr + 1);
7d3d0439
RA		 7827 lro->cur_tsecr = *(ptr + 2);
7828 }
7829}
7830
1ee6dd77 7831static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 7832 struct tcphdr *tcp, u32 tcp_pyld_len)
7833{
7d3d0439
RA		 7834 u8 *ptr;
7835
79dc1901
AM		 7836 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7837
7d3d0439
RA		 7838 if (!tcp_pyld_len) {
7839 /* Runt frame or a pure ack */
7840 return -1;
7841 }
7842
7843 if (ip->ihl != 5) /* IP has options */
7844 return -1;
7845
75c30b13
AR		 7846 /* If we see CE codepoint in IP header, packet is not mergeable */
7847 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
7848 return -1;
7849
7850 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7d3d0439 7851 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
75c30b13 7852 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 7853 /*
7854 * Currently recognize only the ack control word and
7855 * any other control field being set would result in
7856 * flushing the LRO session
7857 */
7858 return -1;
7859 }
7860
6aa20a22 7861 /*
7d3d0439
RA		 7862 * Allow only one TCP timestamp option. Don't aggregate if
7863 * any other options are detected.
7864 */
7865 if (tcp->doff != 5 && tcp->doff != 8)
7866 return -1;
7867
7868 if (tcp->doff == 8) {
6aa20a22 7869 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 7870 while (*ptr == TCPOPT_NOP)
7871 ptr++;
7872 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
7873 return -1;
7874
7875 /* Ensure timestamp value increases monotonically */
7876 if (l_lro)
7877 if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
7878 return -1;
7879
7880 /* timestamp echo reply should be non-zero */
6aa20a22 7881 if (*((u32 *)(ptr+6)) == 0)
7d3d0439
RA		 7882 return -1;
7883 }
7884
7885 return 0;
7886}
7887
7888static int
1ee6dd77
RB		 7889s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
7890 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 7891{
7892 struct iphdr *ip;
7893 struct tcphdr *tcph;
7894 int ret = 0, i;
7895
7896 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
7897 rxdp))) {
7898 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
7899 ip->saddr, ip->daddr);
7900 } else {
7901 return ret;
7902 }
7903
7904 tcph = (struct tcphdr *)*tcp;
7905 *tcp_len = get_l4_pyld_length(ip, tcph);
7906 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 7907 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 7908 if (l_lro->in_use) {
7909 if (check_for_socket_match(l_lro, ip, tcph))
7910 continue;
7911 /* Sock pair matched */
7912 *lro = l_lro;
7913
7914 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
7915 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
7916 "0x%x, actual 0x%x\n", __FUNCTION__,
7917 (*lro)->tcp_next_seq,
7918 ntohl(tcph->seq));
7919
7920 sp->mac_control.stats_info->
7921 sw_stat.outof_sequence_pkts++;
7922 ret = 2;
7923 break;
7924 }
7925
7926 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
7927 ret = 1; /* Aggregate */
7928 else
7929 ret = 2; /* Flush both */
7930 break;
7931 }
7932 }
7933
7934 if (ret == 0) {
7935 /* Before searching for available LRO objects,
7936 * check if the pkt is L3/L4 aggregatable. If not
7937 * don't create new LRO session. Just send this
7938 * packet up.
7939 */
7940 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
7941 return 5;
7942 }
7943
7944 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 7945 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 7946 if (!(l_lro->in_use)) {
7947 *lro = l_lro;
7948 ret = 3; /* Begin anew */
7949 break;
7950 }
7951 }
7952 }
7953
7954 if (ret == 0) { /* sessions exceeded */
7955 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
7956 __FUNCTION__);
7957 *lro = NULL;
7958 return ret;
7959 }
7960
7961 switch (ret) {
7962 case 3:
7963 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
7964 break;
7965 case 2:
7966 update_L3L4_header(sp, *lro);
7967 break;
7968 case 1:
7969 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
7970 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7971 update_L3L4_header(sp, *lro);
7972 ret = 4; /* Flush the LRO */
7973 }
7974 break;
7975 default:
7976 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
7977 __FUNCTION__);
7978 break;
7979 }
7980
7981 return ret;
7982}
7983
1ee6dd77 7984static void clear_lro_session(struct lro *lro)
7d3d0439 7985{
1ee6dd77 7986 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 7987
7988 memset(lro, 0, lro_struct_size);
7989}
7990
7991static void queue_rx_frame(struct sk_buff *skb)
7992{
7993 struct net_device *dev = skb->dev;
7994
7995 skb->protocol = eth_type_trans(skb, dev);
db874e65
SS		 7996 if (napi)
7997 netif_receive_skb(skb);
7998 else
7999 netif_rx(skb);
7d3d0439
RA		 8000}
8001
1ee6dd77
RB		 8002static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8003 struct sk_buff *skb,
7d3d0439
RA		 8004 u32 tcp_len)
8005{
75c30b13 8006 struct sk_buff *first = lro->parent;
7d3d0439
RA		 8007
8008 first->len += tcp_len;
8009 first->data_len = lro->frags_len;
8010 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8011 if (skb_shinfo(first)->frag_list)
8012 lro->last_frag->next = skb;
7d3d0439
RA		 8013 else
8014 skb_shinfo(first)->frag_list = skb;
372cc597 8015 first->truesize += skb->truesize;
75c30b13 8016 lro->last_frag = skb;
7d3d0439
RA		 8017 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8018 return;
8019}
d796fdb7
LV		 8020
8021/**
8022 * s2io_io_error_detected - called when PCI error is detected
8023 * @pdev: Pointer to PCI device
8453d43f 8024 * @state: The current pci connection state
d796fdb7
LV		 8025 *
8026 * This function is called after a PCI bus error affecting
8027 * this device has been detected.
8028 */
8029static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8030 pci_channel_state_t state)
8031{
8032 struct net_device *netdev = pci_get_drvdata(pdev);
8033 struct s2io_nic *sp = netdev->priv;
8034
8035 netif_device_detach(netdev);
8036
8037 if (netif_running(netdev)) {
8038 /* Bring down the card, while avoiding PCI I/O */
8039 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8040 }
8041 pci_disable_device(pdev);
8042
8043 return PCI_ERS_RESULT_NEED_RESET;
8044}
8045
8046/**
8047 * s2io_io_slot_reset - called after the pci bus has been reset.
8048 * @pdev: Pointer to PCI device
8049 *
8050 * Restart the card from scratch, as if from a cold-boot.
8051 * At this point, the card has exprienced a hard reset,
8052 * followed by fixups by BIOS, and has its config space
8053 * set up identically to what it was at cold boot.
8054 */
8055static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8056{
8057 struct net_device *netdev = pci_get_drvdata(pdev);
8058 struct s2io_nic *sp = netdev->priv;
8059
8060 if (pci_enable_device(pdev)) {
8061 printk(KERN_ERR "s2io: "
8062 "Cannot re-enable PCI device after reset.\n");
8063 return PCI_ERS_RESULT_DISCONNECT;
8064 }
8065
8066 pci_set_master(pdev);
8067 s2io_reset(sp);
8068
8069 return PCI_ERS_RESULT_RECOVERED;
8070}
8071
8072/**
8073 * s2io_io_resume - called when traffic can start flowing again.
8074 * @pdev: Pointer to PCI device
8075 *
8076 * This callback is called when the error recovery driver tells
8077 * us that its OK to resume normal operation.
8078 */
8079static void s2io_io_resume(struct pci_dev *pdev)
8080{
8081 struct net_device *netdev = pci_get_drvdata(pdev);
8082 struct s2io_nic *sp = netdev->priv;
8083
8084 if (netif_running(netdev)) {
8085 if (s2io_card_up(sp)) {
8086 printk(KERN_ERR "s2io: "
8087 "Can't bring device back up after reset.\n");
8088 return;
8089 }
8090
8091 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8092 s2io_card_down(sp);
8093 printk(KERN_ERR "s2io: "
8094 "Can't resetore mac addr after reset.\n");
8095 return;
8096 }
8097 }
8098
8099 netif_device_attach(netdev);
8100 netif_wake_queue(netdev);
8101}
Clone of davem's net-next-2.6 tree