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[PATCH] r8169: ethtool message level control support
[net-next-2.6.git] / drivers / net / r8169.c
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1da177e4
LT		 1/*
2=========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
9 2004 - Massive updates. See kernel SCM system for details.
10=========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
14
15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
21
22 2. Support TBI mode.
23=========================================================================
24VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
28 exchanging Link Code Word (FLP).
29
30VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */
52
53#include <linux/module.h>
54#include <linux/moduleparam.h>
55#include <linux/pci.h>
56#include <linux/netdevice.h>
57#include <linux/etherdevice.h>
58#include <linux/delay.h>
59#include <linux/ethtool.h>
60#include <linux/mii.h>
61#include <linux/if_vlan.h>
62#include <linux/crc32.h>
63#include <linux/in.h>
64#include <linux/ip.h>
65#include <linux/tcp.h>
66#include <linux/init.h>
67#include <linux/dma-mapping.h>
68
69#include <asm/io.h>
70#include <asm/irq.h>
71
f7ccf420
SH		 72#ifdef CONFIG_R8169_NAPI
73#define NAPI_SUFFIX "-NAPI"
74#else
75#define NAPI_SUFFIX ""
76#endif
77
78#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 79#define MODULENAME "r8169"
80#define PFX MODULENAME ": "
81
82#ifdef RTL8169_DEBUG
83#define assert(expr) \
84 if(!(expr)) { \
85 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
86 #expr,__FILE__,__FUNCTION__,__LINE__); \
87 }
88#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
89#else
90#define assert(expr) do {} while (0)
91#define dprintk(fmt, args...) do {} while (0)
92#endif /* RTL8169_DEBUG */
93
b57b7e5a
SH		 94#define R8169_MSG_DEFAULT \
95 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | NETIF_MSG_IFUP | \
96 NETIF_MSG_IFDOWN)
97
1da177e4
LT		 98#define TX_BUFFS_AVAIL(tp) \
99 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
100
101#ifdef CONFIG_R8169_NAPI
102#define rtl8169_rx_skb netif_receive_skb
103#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
104#define rtl8169_rx_quota(count, quota) min(count, quota)
105#else
106#define rtl8169_rx_skb netif_rx
107#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
108#define rtl8169_rx_quota(count, quota) count
109#endif
110
111/* media options */
112#define MAX_UNITS 8
113static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
114static int num_media = 0;
115
116/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
117static int max_interrupt_work = 20;
118
119/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
120 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
121static int multicast_filter_limit = 32;
122
123/* MAC address length */
124#define MAC_ADDR_LEN 6
125
126#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
127#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
128#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
129#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
130#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
131#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
132#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
133
134#define R8169_REGS_SIZE 256
135#define R8169_NAPI_WEIGHT 64
136#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
137#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
138#define RX_BUF_SIZE 1536 /* Rx Buffer size */
139#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
140#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
141
142#define RTL8169_TX_TIMEOUT (6*HZ)
143#define RTL8169_PHY_TIMEOUT (10*HZ)
144
145/* write/read MMIO register */
146#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
147#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
148#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
149#define RTL_R8(reg) readb (ioaddr + (reg))
150#define RTL_R16(reg) readw (ioaddr + (reg))
151#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
152
153enum mac_version {
154 RTL_GIGA_MAC_VER_B = 0x00,
155 /* RTL_GIGA_MAC_VER_C = 0x03, */
156 RTL_GIGA_MAC_VER_D = 0x01,
157 RTL_GIGA_MAC_VER_E = 0x02,
158 RTL_GIGA_MAC_VER_X = 0x04 /* Greater than RTL_GIGA_MAC_VER_E */
159};
160
161enum phy_version {
162 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
163 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
164 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
165 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
166 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
167 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
168};
169
170
171#define _R(NAME,MAC,MASK) \
172 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
173
174const static struct {
175 const char *name;
176 u8 mac_version;
177 u32 RxConfigMask; /* Clears the bits supported by this chip */
178} rtl_chip_info[] = {
179 _R("RTL8169", RTL_GIGA_MAC_VER_B, 0xff7e1880),
180 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_D, 0xff7e1880),
181 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_E, 0xff7e1880),
182 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_X, 0xff7e1880),
183};
184#undef _R
185
186static struct pci_device_id rtl8169_pci_tbl[] = {
53456f60
FR		 187 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), },
188 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), },
189 { PCI_DEVICE(0x16ec, 0x0116), },
1da177e4
LT		 190 {0,},
191};
192
193MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
194
195static int rx_copybreak = 200;
196static int use_dac;
b57b7e5a
SH		 197static struct {
198 u32 msg_enable;
199} debug = { -1 };
1da177e4
LT		 200
201enum RTL8169_registers {
202 MAC0 = 0, /* Ethernet hardware address. */
203 MAR0 = 8, /* Multicast filter. */
204 TxDescStartAddrLow = 0x20,
205 TxDescStartAddrHigh = 0x24,
206 TxHDescStartAddrLow = 0x28,
207 TxHDescStartAddrHigh = 0x2c,
208 FLASH = 0x30,
209 ERSR = 0x36,
210 ChipCmd = 0x37,
211 TxPoll = 0x38,
212 IntrMask = 0x3C,
213 IntrStatus = 0x3E,
214 TxConfig = 0x40,
215 RxConfig = 0x44,
216 RxMissed = 0x4C,
217 Cfg9346 = 0x50,
218 Config0 = 0x51,
219 Config1 = 0x52,
220 Config2 = 0x53,
221 Config3 = 0x54,
222 Config4 = 0x55,
223 Config5 = 0x56,
224 MultiIntr = 0x5C,
225 PHYAR = 0x60,
226 TBICSR = 0x64,
227 TBI_ANAR = 0x68,
228 TBI_LPAR = 0x6A,
229 PHYstatus = 0x6C,
230 RxMaxSize = 0xDA,
231 CPlusCmd = 0xE0,
232 IntrMitigate = 0xE2,
233 RxDescAddrLow = 0xE4,
234 RxDescAddrHigh = 0xE8,
235 EarlyTxThres = 0xEC,
236 FuncEvent = 0xF0,
237 FuncEventMask = 0xF4,
238 FuncPresetState = 0xF8,
239 FuncForceEvent = 0xFC,
240};
241
242enum RTL8169_register_content {
243 /* InterruptStatusBits */
244 SYSErr = 0x8000,
245 PCSTimeout = 0x4000,
246 SWInt = 0x0100,
247 TxDescUnavail = 0x80,
248 RxFIFOOver = 0x40,
249 LinkChg = 0x20,
250 RxOverflow = 0x10,
251 TxErr = 0x08,
252 TxOK = 0x04,
253 RxErr = 0x02,
254 RxOK = 0x01,
255
256 /* RxStatusDesc */
257 RxRES = 0x00200000,
258 RxCRC = 0x00080000,
259 RxRUNT = 0x00100000,
260 RxRWT = 0x00400000,
261
262 /* ChipCmdBits */
263 CmdReset = 0x10,
264 CmdRxEnb = 0x08,
265 CmdTxEnb = 0x04,
266 RxBufEmpty = 0x01,
267
268 /* Cfg9346Bits */
269 Cfg9346_Lock = 0x00,
270 Cfg9346_Unlock = 0xC0,
271
272 /* rx_mode_bits */
273 AcceptErr = 0x20,
274 AcceptRunt = 0x10,
275 AcceptBroadcast = 0x08,
276 AcceptMulticast = 0x04,
277 AcceptMyPhys = 0x02,
278 AcceptAllPhys = 0x01,
279
280 /* RxConfigBits */
281 RxCfgFIFOShift = 13,
282 RxCfgDMAShift = 8,
283
284 /* TxConfigBits */
285 TxInterFrameGapShift = 24,
286 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
287
288 /* TBICSR p.28 */
289 TBIReset = 0x80000000,
290 TBILoopback = 0x40000000,
291 TBINwEnable = 0x20000000,
292 TBINwRestart = 0x10000000,
293 TBILinkOk = 0x02000000,
294 TBINwComplete = 0x01000000,
295
296 /* CPlusCmd p.31 */
297 RxVlan = (1 << 6),
298 RxChkSum = (1 << 5),
299 PCIDAC = (1 << 4),
300 PCIMulRW = (1 << 3),
301
302 /* rtl8169_PHYstatus */
303 TBI_Enable = 0x80,
304 TxFlowCtrl = 0x40,
305 RxFlowCtrl = 0x20,
306 _1000bpsF = 0x10,
307 _100bps = 0x08,
308 _10bps = 0x04,
309 LinkStatus = 0x02,
310 FullDup = 0x01,
311
312 /* GIGABIT_PHY_registers */
313 PHY_CTRL_REG = 0,
314 PHY_STAT_REG = 1,
315 PHY_AUTO_NEGO_REG = 4,
316 PHY_1000_CTRL_REG = 9,
317
318 /* GIGABIT_PHY_REG_BIT */
319 PHY_Restart_Auto_Nego = 0x0200,
320 PHY_Enable_Auto_Nego = 0x1000,
321
322 /* PHY_STAT_REG = 1 */
323 PHY_Auto_Neco_Comp = 0x0020,
324
325 /* PHY_AUTO_NEGO_REG = 4 */
326 PHY_Cap_10_Half = 0x0020,
327 PHY_Cap_10_Full = 0x0040,
328 PHY_Cap_100_Half = 0x0080,
329 PHY_Cap_100_Full = 0x0100,
330
331 /* PHY_1000_CTRL_REG = 9 */
332 PHY_Cap_1000_Full = 0x0200,
333
334 PHY_Cap_Null = 0x0,
335
336 /* _MediaType */
337 _10_Half = 0x01,
338 _10_Full = 0x02,
339 _100_Half = 0x04,
340 _100_Full = 0x08,
341 _1000_Full = 0x10,
342
343 /* _TBICSRBit */
344 TBILinkOK = 0x02000000,
345};
346
347enum _DescStatusBit {
348 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
349 RingEnd = (1 << 30), /* End of descriptor ring */
350 FirstFrag = (1 << 29), /* First segment of a packet */
351 LastFrag = (1 << 28), /* Final segment of a packet */
352
353 /* Tx private */
354 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
355 MSSShift = 16, /* MSS value position */
356 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
357 IPCS = (1 << 18), /* Calculate IP checksum */
358 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
359 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
360 TxVlanTag = (1 << 17), /* Add VLAN tag */
361
362 /* Rx private */
363 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
364 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
365
366#define RxProtoUDP (PID1)
367#define RxProtoTCP (PID0)
368#define RxProtoIP (PID1 | PID0)
369#define RxProtoMask RxProtoIP
370
371 IPFail = (1 << 16), /* IP checksum failed */
372 UDPFail = (1 << 15), /* UDP/IP checksum failed */
373 TCPFail = (1 << 14), /* TCP/IP checksum failed */
374 RxVlanTag = (1 << 16), /* VLAN tag available */
375};
376
377#define RsvdMask 0x3fffc000
378
379struct TxDesc {
380 u32 opts1;
381 u32 opts2;
382 u64 addr;
383};
384
385struct RxDesc {
386 u32 opts1;
387 u32 opts2;
388 u64 addr;
389};
390
391struct ring_info {
392 struct sk_buff *skb;
393 u32 len;
394 u8 __pad[sizeof(void *) - sizeof(u32)];
395};
396
397struct rtl8169_private {
398 void __iomem *mmio_addr; /* memory map physical address */
399 struct pci_dev *pci_dev; /* Index of PCI device */
400 struct net_device_stats stats; /* statistics of net device */
401 spinlock_t lock; /* spin lock flag */
b57b7e5a 402 u32 msg_enable;
1da177e4
LT		 403 int chipset;
404 int mac_version;
405 int phy_version;
406 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
407 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
408 u32 dirty_rx;
409 u32 dirty_tx;
410 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
411 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
412 dma_addr_t TxPhyAddr;
413 dma_addr_t RxPhyAddr;
414 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
415 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
416 unsigned rx_buf_sz;
417 struct timer_list timer;
418 u16 cp_cmd;
419 u16 intr_mask;
420 int phy_auto_nego_reg;
421 int phy_1000_ctrl_reg;
422#ifdef CONFIG_R8169_VLAN
423 struct vlan_group *vlgrp;
424#endif
425 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
426 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
427 void (*phy_reset_enable)(void __iomem *);
428 unsigned int (*phy_reset_pending)(void __iomem *);
429 unsigned int (*link_ok)(void __iomem *);
430 struct work_struct task;
431};
432
433MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@oss.sgi.com>");
434MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
435module_param_array(media, int, &num_media, 0);
df0a1bf6 436MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
1da177e4 437module_param(rx_copybreak, int, 0);
1b7efd58 438MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 439module_param(use_dac, int, 0);
440MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 441module_param_named(debug, debug.msg_enable, int, 0);
442MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 443MODULE_LICENSE("GPL");
444MODULE_VERSION(RTL8169_VERSION);
445
446static int rtl8169_open(struct net_device *dev);
447static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
448static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
449 struct pt_regs *regs);
450static int rtl8169_init_ring(struct net_device *dev);
451static void rtl8169_hw_start(struct net_device *dev);
452static int rtl8169_close(struct net_device *dev);
453static void rtl8169_set_rx_mode(struct net_device *dev);
454static void rtl8169_tx_timeout(struct net_device *dev);
455static struct net_device_stats *rtl8169_get_stats(struct net_device *netdev);
456static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
457 void __iomem *);
458static int rtl8169_change_mtu(struct net_device *netdev, int new_mtu);
459static void rtl8169_down(struct net_device *dev);
460
461#ifdef CONFIG_R8169_NAPI
462static int rtl8169_poll(struct net_device *dev, int *budget);
463#endif
464
465static const u16 rtl8169_intr_mask =
466 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
467static const u16 rtl8169_napi_event =
468 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
469static const unsigned int rtl8169_rx_config =
470 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
471
472#define PHY_Cap_10_Half_Or_Less PHY_Cap_10_Half
473#define PHY_Cap_10_Full_Or_Less PHY_Cap_10_Full | PHY_Cap_10_Half_Or_Less
474#define PHY_Cap_100_Half_Or_Less PHY_Cap_100_Half | PHY_Cap_10_Full_Or_Less
475#define PHY_Cap_100_Full_Or_Less PHY_Cap_100_Full | PHY_Cap_100_Half_Or_Less
476
477static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
478{
479 int i;
480
481 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
482 udelay(1000);
483
484 for (i = 2000; i > 0; i--) {
485 /* Check if the RTL8169 has completed writing to the specified MII register */
486 if (!(RTL_R32(PHYAR) & 0x80000000))
487 break;
488 udelay(100);
489 }
490}
491
492static int mdio_read(void __iomem *ioaddr, int RegAddr)
493{
494 int i, value = -1;
495
496 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
497 udelay(1000);
498
499 for (i = 2000; i > 0; i--) {
500 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
501 if (RTL_R32(PHYAR) & 0x80000000) {
502 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
503 break;
504 }
505 udelay(100);
506 }
507 return value;
508}
509
510static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
511{
512 RTL_W16(IntrMask, 0x0000);
513
514 RTL_W16(IntrStatus, 0xffff);
515}
516
517static void rtl8169_asic_down(void __iomem *ioaddr)
518{
519 RTL_W8(ChipCmd, 0x00);
520 rtl8169_irq_mask_and_ack(ioaddr);
521 RTL_R16(CPlusCmd);
522}
523
524static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
525{
526 return RTL_R32(TBICSR) & TBIReset;
527}
528
529static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
530{
531 return mdio_read(ioaddr, 0) & 0x8000;
532}
533
534static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
535{
536 return RTL_R32(TBICSR) & TBILinkOk;
537}
538
539static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
540{
541 return RTL_R8(PHYstatus) & LinkStatus;
542}
543
544static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
545{
546 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
547}
548
549static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
550{
551 unsigned int val;
552
553 val = (mdio_read(ioaddr, PHY_CTRL_REG) | 0x8000) & 0xffff;
554 mdio_write(ioaddr, PHY_CTRL_REG, val);
555}
556
557static void rtl8169_check_link_status(struct net_device *dev,
558 struct rtl8169_private *tp, void __iomem *ioaddr)
559{
560 unsigned long flags;
561
562 spin_lock_irqsave(&tp->lock, flags);
563 if (tp->link_ok(ioaddr)) {
564 netif_carrier_on(dev);
b57b7e5a
SH		 565 if (netif_msg_ifup(tp))
566 printk(KERN_INFO PFX "%s: link up\n", dev->name);
567 } else {
568 if (netif_msg_ifdown(tp))
569 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 570 netif_carrier_off(dev);
b57b7e5a 571 }
1da177e4
LT		 572 spin_unlock_irqrestore(&tp->lock, flags);
573}
574
575static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
576{
577 struct {
578 u16 speed;
579 u8 duplex;
580 u8 autoneg;
581 u8 media;
582 } link_settings[] = {
583 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
584 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
585 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
586 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
587 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
588 /* Make TBI happy */
589 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
590 }, *p;
591 unsigned char option;
592
593 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
594
b57b7e5a 595 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
1da177e4
LT		 596 printk(KERN_WARNING PFX "media option is deprecated.\n");
597
598 for (p = link_settings; p->media != 0xff; p++) {
599 if (p->media == option)
600 break;
601 }
602 *autoneg = p->autoneg;
603 *speed = p->speed;
604 *duplex = p->duplex;
605}
606
607static void rtl8169_get_drvinfo(struct net_device *dev,
608 struct ethtool_drvinfo *info)
609{
610 struct rtl8169_private *tp = netdev_priv(dev);
611
612 strcpy(info->driver, MODULENAME);
613 strcpy(info->version, RTL8169_VERSION);
614 strcpy(info->bus_info, pci_name(tp->pci_dev));
615}
616
617static int rtl8169_get_regs_len(struct net_device *dev)
618{
619 return R8169_REGS_SIZE;
620}
621
622static int rtl8169_set_speed_tbi(struct net_device *dev,
623 u8 autoneg, u16 speed, u8 duplex)
624{
625 struct rtl8169_private *tp = netdev_priv(dev);
626 void __iomem *ioaddr = tp->mmio_addr;
627 int ret = 0;
628 u32 reg;
629
630 reg = RTL_R32(TBICSR);
631 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
632 (duplex == DUPLEX_FULL)) {
633 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
634 } else if (autoneg == AUTONEG_ENABLE)
635 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
636 else {
b57b7e5a
SH		 637 if (netif_msg_link(tp)) {
638 printk(KERN_WARNING "%s: "
639 "incorrect speed setting refused in TBI mode\n",
640 dev->name);
641 }
1da177e4
LT		 642 ret = -EOPNOTSUPP;
643 }
644
645 return ret;
646}
647
648static int rtl8169_set_speed_xmii(struct net_device *dev,
649 u8 autoneg, u16 speed, u8 duplex)
650{
651 struct rtl8169_private *tp = netdev_priv(dev);
652 void __iomem *ioaddr = tp->mmio_addr;
653 int auto_nego, giga_ctrl;
654
655 auto_nego = mdio_read(ioaddr, PHY_AUTO_NEGO_REG);
656 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_10_Full |
657 PHY_Cap_100_Half | PHY_Cap_100_Full);
658 giga_ctrl = mdio_read(ioaddr, PHY_1000_CTRL_REG);
659 giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_Null);
660
661 if (autoneg == AUTONEG_ENABLE) {
662 auto_nego |= (PHY_Cap_10_Half | PHY_Cap_10_Full |
663 PHY_Cap_100_Half | PHY_Cap_100_Full);
664 giga_ctrl |= PHY_Cap_1000_Full;
665 } else {
666 if (speed == SPEED_10)
667 auto_nego |= PHY_Cap_10_Half | PHY_Cap_10_Full;
668 else if (speed == SPEED_100)
669 auto_nego |= PHY_Cap_100_Half | PHY_Cap_100_Full;
670 else if (speed == SPEED_1000)
671 giga_ctrl |= PHY_Cap_1000_Full;
672
673 if (duplex == DUPLEX_HALF)
674 auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full);
675 }
676
677 tp->phy_auto_nego_reg = auto_nego;
678 tp->phy_1000_ctrl_reg = giga_ctrl;
679
680 mdio_write(ioaddr, PHY_AUTO_NEGO_REG, auto_nego);
681 mdio_write(ioaddr, PHY_1000_CTRL_REG, giga_ctrl);
682 mdio_write(ioaddr, PHY_CTRL_REG, PHY_Enable_Auto_Nego |
683 PHY_Restart_Auto_Nego);
684 return 0;
685}
686
687static int rtl8169_set_speed(struct net_device *dev,
688 u8 autoneg, u16 speed, u8 duplex)
689{
690 struct rtl8169_private *tp = netdev_priv(dev);
691 int ret;
692
693 ret = tp->set_speed(dev, autoneg, speed, duplex);
694
695 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
696 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
697
698 return ret;
699}
700
701static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
702{
703 struct rtl8169_private *tp = netdev_priv(dev);
704 unsigned long flags;
705 int ret;
706
707 spin_lock_irqsave(&tp->lock, flags);
708 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
709 spin_unlock_irqrestore(&tp->lock, flags);
710
711 return ret;
712}
713
714static u32 rtl8169_get_rx_csum(struct net_device *dev)
715{
716 struct rtl8169_private *tp = netdev_priv(dev);
717
718 return tp->cp_cmd & RxChkSum;
719}
720
721static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
722{
723 struct rtl8169_private *tp = netdev_priv(dev);
724 void __iomem *ioaddr = tp->mmio_addr;
725 unsigned long flags;
726
727 spin_lock_irqsave(&tp->lock, flags);
728
729 if (data)
730 tp->cp_cmd |= RxChkSum;
731 else
732 tp->cp_cmd &= ~RxChkSum;
733
734 RTL_W16(CPlusCmd, tp->cp_cmd);
735 RTL_R16(CPlusCmd);
736
737 spin_unlock_irqrestore(&tp->lock, flags);
738
739 return 0;
740}
741
742#ifdef CONFIG_R8169_VLAN
743
744static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
745 struct sk_buff *skb)
746{
747 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
748 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
749}
750
751static void rtl8169_vlan_rx_register(struct net_device *dev,
752 struct vlan_group *grp)
753{
754 struct rtl8169_private *tp = netdev_priv(dev);
755 void __iomem *ioaddr = tp->mmio_addr;
756 unsigned long flags;
757
758 spin_lock_irqsave(&tp->lock, flags);
759 tp->vlgrp = grp;
760 if (tp->vlgrp)
761 tp->cp_cmd |= RxVlan;
762 else
763 tp->cp_cmd &= ~RxVlan;
764 RTL_W16(CPlusCmd, tp->cp_cmd);
765 RTL_R16(CPlusCmd);
766 spin_unlock_irqrestore(&tp->lock, flags);
767}
768
769static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
770{
771 struct rtl8169_private *tp = netdev_priv(dev);
772 unsigned long flags;
773
774 spin_lock_irqsave(&tp->lock, flags);
775 if (tp->vlgrp)
776 tp->vlgrp->vlan_devices[vid] = NULL;
777 spin_unlock_irqrestore(&tp->lock, flags);
778}
779
780static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
781 struct sk_buff *skb)
782{
783 u32 opts2 = le32_to_cpu(desc->opts2);
784 int ret;
785
786 if (tp->vlgrp && (opts2 & RxVlanTag)) {
787 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
788 swab16(opts2 & 0xffff));
789 ret = 0;
790 } else
791 ret = -1;
792 desc->opts2 = 0;
793 return ret;
794}
795
796#else /* !CONFIG_R8169_VLAN */
797
798static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
799 struct sk_buff *skb)
800{
801 return 0;
802}
803
804static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
805 struct sk_buff *skb)
806{
807 return -1;
808}
809
810#endif
811
812static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
813{
814 struct rtl8169_private *tp = netdev_priv(dev);
815 void __iomem *ioaddr = tp->mmio_addr;
816 u32 status;
817
818 cmd->supported =
819 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
820 cmd->port = PORT_FIBRE;
821 cmd->transceiver = XCVR_INTERNAL;
822
823 status = RTL_R32(TBICSR);
824 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
825 cmd->autoneg = !!(status & TBINwEnable);
826
827 cmd->speed = SPEED_1000;
828 cmd->duplex = DUPLEX_FULL; /* Always set */
829}
830
831static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
832{
833 struct rtl8169_private *tp = netdev_priv(dev);
834 void __iomem *ioaddr = tp->mmio_addr;
835 u8 status;
836
837 cmd->supported = SUPPORTED_10baseT_Half |
838 SUPPORTED_10baseT_Full |
839 SUPPORTED_100baseT_Half |
840 SUPPORTED_100baseT_Full |
841 SUPPORTED_1000baseT_Full |
842 SUPPORTED_Autoneg |
843 SUPPORTED_TP;
844
845 cmd->autoneg = 1;
846 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
847
848 if (tp->phy_auto_nego_reg & PHY_Cap_10_Half)
849 cmd->advertising |= ADVERTISED_10baseT_Half;
850 if (tp->phy_auto_nego_reg & PHY_Cap_10_Full)
851 cmd->advertising |= ADVERTISED_10baseT_Full;
852 if (tp->phy_auto_nego_reg & PHY_Cap_100_Half)
853 cmd->advertising |= ADVERTISED_100baseT_Half;
854 if (tp->phy_auto_nego_reg & PHY_Cap_100_Full)
855 cmd->advertising |= ADVERTISED_100baseT_Full;
856 if (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full)
857 cmd->advertising |= ADVERTISED_1000baseT_Full;
858
859 status = RTL_R8(PHYstatus);
860
861 if (status & _1000bpsF)
862 cmd->speed = SPEED_1000;
863 else if (status & _100bps)
864 cmd->speed = SPEED_100;
865 else if (status & _10bps)
866 cmd->speed = SPEED_10;
867
868 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
869 DUPLEX_FULL : DUPLEX_HALF;
870}
871
872static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
873{
874 struct rtl8169_private *tp = netdev_priv(dev);
875 unsigned long flags;
876
877 spin_lock_irqsave(&tp->lock, flags);
878
879 tp->get_settings(dev, cmd);
880
881 spin_unlock_irqrestore(&tp->lock, flags);
882 return 0;
883}
884
885static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
886 void *p)
887{
888 struct rtl8169_private *tp = netdev_priv(dev);
889 unsigned long flags;
890
891 if (regs->len > R8169_REGS_SIZE)
892 regs->len = R8169_REGS_SIZE;
893
894 spin_lock_irqsave(&tp->lock, flags);
895 memcpy_fromio(p, tp->mmio_addr, regs->len);
896 spin_unlock_irqrestore(&tp->lock, flags);
897}
898
b57b7e5a
SH		 899static u32 rtl8169_get_msglevel(struct net_device *dev)
900{
901 struct rtl8169_private *tp = netdev_priv(dev);
902
903 return tp->msg_enable;
904}
905
906static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
907{
908 struct rtl8169_private *tp = netdev_priv(dev);
909
910 tp->msg_enable = value;
911}
912
1da177e4
LT		 913static struct ethtool_ops rtl8169_ethtool_ops = {
914 .get_drvinfo = rtl8169_get_drvinfo,
915 .get_regs_len = rtl8169_get_regs_len,
916 .get_link = ethtool_op_get_link,
917 .get_settings = rtl8169_get_settings,
918 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 919 .get_msglevel = rtl8169_get_msglevel,
920 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 921 .get_rx_csum = rtl8169_get_rx_csum,
922 .set_rx_csum = rtl8169_set_rx_csum,
923 .get_tx_csum = ethtool_op_get_tx_csum,
924 .set_tx_csum = ethtool_op_set_tx_csum,
925 .get_sg = ethtool_op_get_sg,
926 .set_sg = ethtool_op_set_sg,
927 .get_tso = ethtool_op_get_tso,
928 .set_tso = ethtool_op_set_tso,
929 .get_regs = rtl8169_get_regs,
930};
931
932static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
933 int bitval)
934{
935 int val;
936
937 val = mdio_read(ioaddr, reg);
938 val = (bitval == 1) ?
939 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
940 mdio_write(ioaddr, reg, val & 0xffff);
941}
942
943static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
944{
945 const struct {
946 u32 mask;
947 int mac_version;
948 } mac_info[] = {
949 { 0x1 << 28, RTL_GIGA_MAC_VER_X },
950 { 0x1 << 26, RTL_GIGA_MAC_VER_E },
951 { 0x1 << 23, RTL_GIGA_MAC_VER_D },
952 { 0x00000000, RTL_GIGA_MAC_VER_B } /* Catch-all */
953 }, *p = mac_info;
954 u32 reg;
955
956 reg = RTL_R32(TxConfig) & 0x7c800000;
957 while ((reg & p->mask) != p->mask)
958 p++;
959 tp->mac_version = p->mac_version;
960}
961
962static void rtl8169_print_mac_version(struct rtl8169_private *tp)
963{
964 struct {
965 int version;
966 char *msg;
967 } mac_print[] = {
968 { RTL_GIGA_MAC_VER_E, "RTL_GIGA_MAC_VER_E" },
969 { RTL_GIGA_MAC_VER_D, "RTL_GIGA_MAC_VER_D" },
970 { RTL_GIGA_MAC_VER_B, "RTL_GIGA_MAC_VER_B" },
971 { 0, NULL }
972 }, *p;
973
974 for (p = mac_print; p->msg; p++) {
975 if (tp->mac_version == p->version) {
976 dprintk("mac_version == %s (%04d)\n", p->msg,
977 p->version);
978 return;
979 }
980 }
981 dprintk("mac_version == Unknown\n");
982}
983
984static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
985{
986 const struct {
987 u16 mask;
988 u16 set;
989 int phy_version;
990 } phy_info[] = {
991 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
992 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
993 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
994 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
995 }, *p = phy_info;
996 u16 reg;
997
998 reg = mdio_read(ioaddr, 3) & 0xffff;
999 while ((reg & p->mask) != p->set)
1000 p++;
1001 tp->phy_version = p->phy_version;
1002}
1003
1004static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1005{
1006 struct {
1007 int version;
1008 char *msg;
1009 u32 reg;
1010 } phy_print[] = {
1011 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1012 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1013 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1014 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1015 { 0, NULL, 0x0000 }
1016 }, *p;
1017
1018 for (p = phy_print; p->msg; p++) {
1019 if (tp->phy_version == p->version) {
1020 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1021 return;
1022 }
1023 }
1024 dprintk("phy_version == Unknown\n");
1025}
1026
1027static void rtl8169_hw_phy_config(struct net_device *dev)
1028{
1029 struct rtl8169_private *tp = netdev_priv(dev);
1030 void __iomem *ioaddr = tp->mmio_addr;
1031 struct {
1032 u16 regs[5]; /* Beware of bit-sign propagation */
1033 } phy_magic[5] = { {
1034 { 0x0000, //w 4 15 12 0
1035 0x00a1, //w 3 15 0 00a1
1036 0x0008, //w 2 15 0 0008
1037 0x1020, //w 1 15 0 1020
1038 0x1000 } },{ //w 0 15 0 1000
1039 { 0x7000, //w 4 15 12 7
1040 0xff41, //w 3 15 0 ff41
1041 0xde60, //w 2 15 0 de60
1042 0x0140, //w 1 15 0 0140
1043 0x0077 } },{ //w 0 15 0 0077
1044 { 0xa000, //w 4 15 12 a
1045 0xdf01, //w 3 15 0 df01
1046 0xdf20, //w 2 15 0 df20
1047 0xff95, //w 1 15 0 ff95
1048 0xfa00 } },{ //w 0 15 0 fa00
1049 { 0xb000, //w 4 15 12 b
1050 0xff41, //w 3 15 0 ff41
1051 0xde20, //w 2 15 0 de20
1052 0x0140, //w 1 15 0 0140
1053 0x00bb } },{ //w 0 15 0 00bb
1054 { 0xf000, //w 4 15 12 f
1055 0xdf01, //w 3 15 0 df01
1056 0xdf20, //w 2 15 0 df20
1057 0xff95, //w 1 15 0 ff95
1058 0xbf00 } //w 0 15 0 bf00
1059 }
1060 }, *p = phy_magic;
1061 int i;
1062
1063 rtl8169_print_mac_version(tp);
1064 rtl8169_print_phy_version(tp);
1065
1066 if (tp->mac_version <= RTL_GIGA_MAC_VER_B)
1067 return;
1068 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1069 return;
1070
1071 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1072 dprintk("Do final_reg2.cfg\n");
1073
1074 /* Shazam ! */
1075
1076 if (tp->mac_version == RTL_GIGA_MAC_VER_X) {
1077 mdio_write(ioaddr, 31, 0x0001);
1078 mdio_write(ioaddr, 9, 0x273a);
1079 mdio_write(ioaddr, 14, 0x7bfb);
1080 mdio_write(ioaddr, 27, 0x841e);
1081
1082 mdio_write(ioaddr, 31, 0x0002);
1083 mdio_write(ioaddr, 1, 0x90d0);
1084 mdio_write(ioaddr, 31, 0x0000);
1085 return;
1086 }
1087
1088 /* phy config for RTL8169s mac_version C chip */
1089 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1090 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1091 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1092 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1093
1094 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1095 int val, pos = 4;
1096
1097 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1098 mdio_write(ioaddr, pos, val);
1099 while (--pos >= 0)
1100 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1101 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1102 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1103 }
1104 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1105}
1106
1107static void rtl8169_phy_timer(unsigned long __opaque)
1108{
1109 struct net_device *dev = (struct net_device *)__opaque;
1110 struct rtl8169_private *tp = netdev_priv(dev);
1111 struct timer_list *timer = &tp->timer;
1112 void __iomem *ioaddr = tp->mmio_addr;
1113 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1114
1115 assert(tp->mac_version > RTL_GIGA_MAC_VER_B);
1116 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1117
1118 if (!(tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
1119 return;
1120
1121 spin_lock_irq(&tp->lock);
1122
1123 if (tp->phy_reset_pending(ioaddr)) {
1124 /*
1125 * A busy loop could burn quite a few cycles on nowadays CPU.
1126 * Let's delay the execution of the timer for a few ticks.
1127 */
1128 timeout = HZ/10;
1129 goto out_mod_timer;
1130 }
1131
1132 if (tp->link_ok(ioaddr))
1133 goto out_unlock;
1134
b57b7e5a
SH		 1135 if (netif_msg_link(tp))
1136 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1137
1138 tp->phy_reset_enable(ioaddr);
1139
1140out_mod_timer:
1141 mod_timer(timer, jiffies + timeout);
1142out_unlock:
1143 spin_unlock_irq(&tp->lock);
1144}
1145
1146static inline void rtl8169_delete_timer(struct net_device *dev)
1147{
1148 struct rtl8169_private *tp = netdev_priv(dev);
1149 struct timer_list *timer = &tp->timer;
1150
1151 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1152 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1153 return;
1154
1155 del_timer_sync(timer);
1156}
1157
1158static inline void rtl8169_request_timer(struct net_device *dev)
1159{
1160 struct rtl8169_private *tp = netdev_priv(dev);
1161 struct timer_list *timer = &tp->timer;
1162
1163 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1164 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1165 return;
1166
1167 init_timer(timer);
1168 timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
1169 timer->data = (unsigned long)(dev);
1170 timer->function = rtl8169_phy_timer;
1171 add_timer(timer);
1172}
1173
1174#ifdef CONFIG_NET_POLL_CONTROLLER
1175/*
1176 * Polling 'interrupt' - used by things like netconsole to send skbs
1177 * without having to re-enable interrupts. It's not called while
1178 * the interrupt routine is executing.
1179 */
1180static void rtl8169_netpoll(struct net_device *dev)
1181{
1182 struct rtl8169_private *tp = netdev_priv(dev);
1183 struct pci_dev *pdev = tp->pci_dev;
1184
1185 disable_irq(pdev->irq);
1186 rtl8169_interrupt(pdev->irq, dev, NULL);
1187 enable_irq(pdev->irq);
1188}
1189#endif
1190
1191static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1192 void __iomem *ioaddr)
1193{
1194 iounmap(ioaddr);
1195 pci_release_regions(pdev);
1196 pci_disable_device(pdev);
1197 free_netdev(dev);
1198}
1199
1200static int __devinit
1201rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1202 void __iomem **ioaddr_out)
1203{
1204 void __iomem *ioaddr;
1205 struct net_device *dev;
1206 struct rtl8169_private *tp;
1207 int rc = -ENOMEM, i, acpi_idle_state = 0, pm_cap;
1208
1209 assert(ioaddr_out != NULL);
1210
1211 /* dev zeroed in alloc_etherdev */
1212 dev = alloc_etherdev(sizeof (*tp));
1213 if (dev == NULL) {
b57b7e5a
SH		 1214 if (netif_msg_drv(&debug))
1215 printk(KERN_ERR PFX "unable to alloc new ethernet\n");
1da177e4
LT		 1216 goto err_out;
1217 }
1218
1219 SET_MODULE_OWNER(dev);
1220 SET_NETDEV_DEV(dev, &pdev->dev);
1221 tp = netdev_priv(dev);
b57b7e5a 1222 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1223
1224 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1225 rc = pci_enable_device(pdev);
b57b7e5a
SH		 1226 if (rc < 0) {
1227 if (netif_msg_probe(tp)) {
1228 printk(KERN_ERR PFX "%s: enable failure\n",
1229 pci_name(pdev));
1230 }
1da177e4
LT		 1231 goto err_out_free_dev;
1232 }
1233
1234 rc = pci_set_mwi(pdev);
1235 if (rc < 0)
1236 goto err_out_disable;
1237
1238 /* save power state before pci_enable_device overwrites it */
1239 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1240 if (pm_cap) {
1241 u16 pwr_command;
1242
1243 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1244 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1245 } else {
b57b7e5a
SH		 1246 if (netif_msg_probe(tp)) {
1247 printk(KERN_ERR PFX
1248 "Cannot find PowerManagement capability. "
1249 "Aborting.\n");
1250 }
1da177e4
LT		 1251 goto err_out_mwi;
1252 }
1253
1254 /* make sure PCI base addr 1 is MMIO */
1255 if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
b57b7e5a
SH		 1256 if (netif_msg_probe(tp)) {
1257 printk(KERN_ERR PFX
1258 "region #1 not an MMIO resource, aborting\n");
1259 }
1da177e4
LT		 1260 rc = -ENODEV;
1261 goto err_out_mwi;
1262 }
1263 /* check for weird/broken PCI region reporting */
1264 if (pci_resource_len(pdev, 1) < R8169_REGS_SIZE) {
b57b7e5a
SH		 1265 if (netif_msg_probe(tp)) {
1266 printk(KERN_ERR PFX
1267 "Invalid PCI region size(s), aborting\n");
1268 }
1da177e4
LT		 1269 rc = -ENODEV;
1270 goto err_out_mwi;
1271 }
1272
1273 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a
SH		 1274 if (rc < 0) {
1275 if (netif_msg_probe(tp)) {
1276 printk(KERN_ERR PFX "%s: could not request regions.\n",
1277 pci_name(pdev));
1278 }
1da177e4
LT		 1279 goto err_out_mwi;
1280 }
1281
1282 tp->cp_cmd = PCIMulRW | RxChkSum;
1283
1284 if ((sizeof(dma_addr_t) > 4) &&
1285 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1286 tp->cp_cmd |= PCIDAC;
1287 dev->features |= NETIF_F_HIGHDMA;
1288 } else {
1289 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1290 if (rc < 0) {
b57b7e5a
SH		 1291 if (netif_msg_probe(tp)) {
1292 printk(KERN_ERR PFX
1293 "DMA configuration failed.\n");
1294 }
1da177e4
LT		 1295 goto err_out_free_res;
1296 }
1297 }
1298
1299 pci_set_master(pdev);
1300
1301 /* ioremap MMIO region */
1302 ioaddr = ioremap(pci_resource_start(pdev, 1), R8169_REGS_SIZE);
1303 if (ioaddr == NULL) {
b57b7e5a
SH		 1304 if (netif_msg_probe(tp))
1305 printk(KERN_ERR PFX "cannot remap MMIO, aborting\n");
1da177e4
LT		 1306 rc = -EIO;
1307 goto err_out_free_res;
1308 }
1309
1310 /* Unneeded ? Don't mess with Mrs. Murphy. */
1311 rtl8169_irq_mask_and_ack(ioaddr);
1312
1313 /* Soft reset the chip. */
1314 RTL_W8(ChipCmd, CmdReset);
1315
1316 /* Check that the chip has finished the reset. */
1317 for (i = 1000; i > 0; i--) {
1318 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1319 break;
1320 udelay(10);
1321 }
1322
1323 /* Identify chip attached to board */
1324 rtl8169_get_mac_version(tp, ioaddr);
1325 rtl8169_get_phy_version(tp, ioaddr);
1326
1327 rtl8169_print_mac_version(tp);
1328 rtl8169_print_phy_version(tp);
1329
1330 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1331 if (tp->mac_version == rtl_chip_info[i].mac_version)
1332 break;
1333 }
1334 if (i < 0) {
1335 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a
SH		 1336 if (netif_msg_probe(tp)) {
1337 printk(KERN_DEBUG PFX "PCI device %s: "
1338 "unknown chip version, assuming %s\n",
1339 pci_name(pdev), rtl_chip_info[0].name);
1340 }
1da177e4
LT		 1341 i++;
1342 }
1343 tp->chipset = i;
1344
1345 *ioaddr_out = ioaddr;
1346 *dev_out = dev;
1347out:
1348 return rc;
1349
1350err_out_free_res:
1351 pci_release_regions(pdev);
1352
1353err_out_mwi:
1354 pci_clear_mwi(pdev);
1355
1356err_out_disable:
1357 pci_disable_device(pdev);
1358
1359err_out_free_dev:
1360 free_netdev(dev);
1361err_out:
1362 *ioaddr_out = NULL;
1363 *dev_out = NULL;
1364 goto out;
1365}
1366
1367static int __devinit
1368rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1369{
1370 struct net_device *dev = NULL;
1371 struct rtl8169_private *tp;
1372 void __iomem *ioaddr = NULL;
1373 static int board_idx = -1;
1da177e4
LT		 1374 u8 autoneg, duplex;
1375 u16 speed;
1376 int i, rc;
1377
1378 assert(pdev != NULL);
1379 assert(ent != NULL);
1380
1381 board_idx++;
1382
b57b7e5a 1383 if (netif_msg_drv(&debug)) {
1da177e4
LT		 1384 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1385 MODULENAME, RTL8169_VERSION);
1da177e4
LT		 1386 }
1387
1388 rc = rtl8169_init_board(pdev, &dev, &ioaddr);
1389 if (rc)
1390 return rc;
1391
1392 tp = netdev_priv(dev);
1393 assert(ioaddr != NULL);
1394
1395 if (RTL_R8(PHYstatus) & TBI_Enable) {
1396 tp->set_speed = rtl8169_set_speed_tbi;
1397 tp->get_settings = rtl8169_gset_tbi;
1398 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1399 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1400 tp->link_ok = rtl8169_tbi_link_ok;
1401
1402 tp->phy_1000_ctrl_reg = PHY_Cap_1000_Full; /* Implied by TBI */
1403 } else {
1404 tp->set_speed = rtl8169_set_speed_xmii;
1405 tp->get_settings = rtl8169_gset_xmii;
1406 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1407 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1408 tp->link_ok = rtl8169_xmii_link_ok;
1409 }
1410
1411 /* Get MAC address. FIXME: read EEPROM */
1412 for (i = 0; i < MAC_ADDR_LEN; i++)
1413 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1414
1415 dev->open = rtl8169_open;
1416 dev->hard_start_xmit = rtl8169_start_xmit;
1417 dev->get_stats = rtl8169_get_stats;
1418 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1419 dev->stop = rtl8169_close;
1420 dev->tx_timeout = rtl8169_tx_timeout;
1421 dev->set_multicast_list = rtl8169_set_rx_mode;
1422 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1423 dev->irq = pdev->irq;
1424 dev->base_addr = (unsigned long) ioaddr;
1425 dev->change_mtu = rtl8169_change_mtu;
1426
1427#ifdef CONFIG_R8169_NAPI
1428 dev->poll = rtl8169_poll;
1429 dev->weight = R8169_NAPI_WEIGHT;
1da177e4
LT		 1430#endif
1431
1432#ifdef CONFIG_R8169_VLAN
1433 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1434 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1435 dev->vlan_rx_kill_vid = rtl8169_vlan_rx_kill_vid;
1436#endif
1437
1438#ifdef CONFIG_NET_POLL_CONTROLLER
1439 dev->poll_controller = rtl8169_netpoll;
1440#endif
1441
1442 tp->intr_mask = 0xffff;
1443 tp->pci_dev = pdev;
1444 tp->mmio_addr = ioaddr;
1445
1446 spin_lock_init(&tp->lock);
1447
1448 rc = register_netdev(dev);
1449 if (rc) {
1450 rtl8169_release_board(pdev, dev, ioaddr);
1451 return rc;
1452 }
1453
b57b7e5a
SH		 1454 if (netif_msg_probe(tp)) {
1455 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n",
1456 dev->name, rtl_chip_info[tp->chipset].name);
1457 }
1da177e4
LT		 1458
1459 pci_set_drvdata(pdev, dev);
1460
b57b7e5a
SH		 1461 if (netif_msg_probe(tp)) {
1462 printk(KERN_INFO "%s: %s at 0x%lx, "
1463 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1464 "IRQ %d\n",
1465 dev->name,
1466 rtl_chip_info[ent->driver_data].name,
1467 dev->base_addr,
1468 dev->dev_addr[0], dev->dev_addr[1],
1469 dev->dev_addr[2], dev->dev_addr[3],
1470 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1471 }
1da177e4
LT		 1472
1473 rtl8169_hw_phy_config(dev);
1474
1475 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1476 RTL_W8(0x82, 0x01);
1477
1478 if (tp->mac_version < RTL_GIGA_MAC_VER_E) {
1479 dprintk("Set PCI Latency=0x40\n");
1480 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
1481 }
1482
1483 if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
1484 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1485 RTL_W8(0x82, 0x01);
1486 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1487 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1488 }
1489
1490 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1491
1492 rtl8169_set_speed(dev, autoneg, speed, duplex);
1493
b57b7e5a 1494 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1da177e4
LT		 1495 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1496
1497 return 0;
1498}
1499
1500static void __devexit
1501rtl8169_remove_one(struct pci_dev *pdev)
1502{
1503 struct net_device *dev = pci_get_drvdata(pdev);
1504 struct rtl8169_private *tp = netdev_priv(dev);
1505
1506 assert(dev != NULL);
1507 assert(tp != NULL);
1508
1509 unregister_netdev(dev);
1510 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1511 pci_set_drvdata(pdev, NULL);
1512}
1513
1514#ifdef CONFIG_PM
1515
05adc3b7 1516static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 1517{
1518 struct net_device *dev = pci_get_drvdata(pdev);
1519 struct rtl8169_private *tp = netdev_priv(dev);
1520 void __iomem *ioaddr = tp->mmio_addr;
1521 unsigned long flags;
1522
1523 if (!netif_running(dev))
1524 return 0;
1525
1526 netif_device_detach(dev);
1527 netif_stop_queue(dev);
1528 spin_lock_irqsave(&tp->lock, flags);
1529
1530 /* Disable interrupts, stop Rx and Tx */
1531 RTL_W16(IntrMask, 0);
1532 RTL_W8(ChipCmd, 0);
1533
1534 /* Update the error counts. */
1535 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
1536 RTL_W32(RxMissed, 0);
1537 spin_unlock_irqrestore(&tp->lock, flags);
1538
1539 return 0;
1540}
1541
1542static int rtl8169_resume(struct pci_dev *pdev)
1543{
1544 struct net_device *dev = pci_get_drvdata(pdev);
1545
1546 if (!netif_running(dev))
1547 return 0;
1548
1549 netif_device_attach(dev);
1550 rtl8169_hw_start(dev);
1551
1552 return 0;
1553}
1554
1555#endif /* CONFIG_PM */
1556
1557static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1558 struct net_device *dev)
1559{
1560 unsigned int mtu = dev->mtu;
1561
1562 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1563}
1564
1565static int rtl8169_open(struct net_device *dev)
1566{
1567 struct rtl8169_private *tp = netdev_priv(dev);
1568 struct pci_dev *pdev = tp->pci_dev;
1569 int retval;
1570
1571 rtl8169_set_rxbufsize(tp, dev);
1572
1573 retval =
1574 request_irq(dev->irq, rtl8169_interrupt, SA_SHIRQ, dev->name, dev);
1575 if (retval < 0)
1576 goto out;
1577
1578 retval = -ENOMEM;
1579
1580 /*
1581 * Rx and Tx desscriptors needs 256 bytes alignment.
1582 * pci_alloc_consistent provides more.
1583 */
1584 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1585 &tp->TxPhyAddr);
1586 if (!tp->TxDescArray)
1587 goto err_free_irq;
1588
1589 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1590 &tp->RxPhyAddr);
1591 if (!tp->RxDescArray)
1592 goto err_free_tx;
1593
1594 retval = rtl8169_init_ring(dev);
1595 if (retval < 0)
1596 goto err_free_rx;
1597
1598 INIT_WORK(&tp->task, NULL, dev);
1599
1600 rtl8169_hw_start(dev);
1601
1602 rtl8169_request_timer(dev);
1603
1604 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1605out:
1606 return retval;
1607
1608err_free_rx:
1609 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1610 tp->RxPhyAddr);
1611err_free_tx:
1612 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1613 tp->TxPhyAddr);
1614err_free_irq:
1615 free_irq(dev->irq, dev);
1616 goto out;
1617}
1618
1619static void rtl8169_hw_reset(void __iomem *ioaddr)
1620{
1621 /* Disable interrupts */
1622 rtl8169_irq_mask_and_ack(ioaddr);
1623
1624 /* Reset the chipset */
1625 RTL_W8(ChipCmd, CmdReset);
1626
1627 /* PCI commit */
1628 RTL_R8(ChipCmd);
1629}
1630
1631static void
1632rtl8169_hw_start(struct net_device *dev)
1633{
1634 struct rtl8169_private *tp = netdev_priv(dev);
1635 void __iomem *ioaddr = tp->mmio_addr;
1636 u32 i;
1637
1638 /* Soft reset the chip. */
1639 RTL_W8(ChipCmd, CmdReset);
1640
1641 /* Check that the chip has finished the reset. */
1642 for (i = 1000; i > 0; i--) {
1643 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1644 break;
1645 udelay(10);
1646 }
1647
1648 RTL_W8(Cfg9346, Cfg9346_Unlock);
1649 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1650 RTL_W8(EarlyTxThres, EarlyTxThld);
1651
126fa4b9
FR		 1652 /* Low hurts. Let's disable the filtering. */
1653 RTL_W16(RxMaxSize, 16383);
1da177e4
LT		 1654
1655 /* Set Rx Config register */
1656 i = rtl8169_rx_config |
1657 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1658 RTL_W32(RxConfig, i);
1659
1660 /* Set DMA burst size and Interframe Gap Time */
1661 RTL_W32(TxConfig,
1662 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
1663 TxInterFrameGapShift));
1664 tp->cp_cmd |= RTL_R16(CPlusCmd);
1665 RTL_W16(CPlusCmd, tp->cp_cmd);
1666
1667 if ((tp->mac_version == RTL_GIGA_MAC_VER_D) ||
1668 (tp->mac_version == RTL_GIGA_MAC_VER_E)) {
1669 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1670 "Bit-3 and bit-14 MUST be 1\n");
1671 tp->cp_cmd |= (1 << 14) | PCIMulRW;
1672 RTL_W16(CPlusCmd, tp->cp_cmd);
1673 }
1674
1675 /*
1676 * Undocumented corner. Supposedly:
1677 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1678 */
1679 RTL_W16(IntrMitigate, 0x0000);
1680
1681 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1682 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
1683 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1684 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1685 RTL_W8(Cfg9346, Cfg9346_Lock);
1686 udelay(10);
1687
1688 RTL_W32(RxMissed, 0);
1689
1690 rtl8169_set_rx_mode(dev);
1691
1692 /* no early-rx interrupts */
1693 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1694
1695 /* Enable all known interrupts by setting the interrupt mask. */
1696 RTL_W16(IntrMask, rtl8169_intr_mask);
1697
1698 netif_start_queue(dev);
1699}
1700
1701static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
1702{
1703 struct rtl8169_private *tp = netdev_priv(dev);
1704 int ret = 0;
1705
1706 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
1707 return -EINVAL;
1708
1709 dev->mtu = new_mtu;
1710
1711 if (!netif_running(dev))
1712 goto out;
1713
1714 rtl8169_down(dev);
1715
1716 rtl8169_set_rxbufsize(tp, dev);
1717
1718 ret = rtl8169_init_ring(dev);
1719 if (ret < 0)
1720 goto out;
1721
1722 netif_poll_enable(dev);
1723
1724 rtl8169_hw_start(dev);
1725
1726 rtl8169_request_timer(dev);
1727
1728out:
1729 return ret;
1730}
1731
1732static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
1733{
1734 desc->addr = 0x0badbadbadbadbadull;
1735 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
1736}
1737
1738static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
1739 struct sk_buff **sk_buff, struct RxDesc *desc)
1740{
1741 struct pci_dev *pdev = tp->pci_dev;
1742
1743 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
1744 PCI_DMA_FROMDEVICE);
1745 dev_kfree_skb(*sk_buff);
1746 *sk_buff = NULL;
1747 rtl8169_make_unusable_by_asic(desc);
1748}
1749
1750static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
1751{
1752 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
1753
1754 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
1755}
1756
1757static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
1758 u32 rx_buf_sz)
1759{
1760 desc->addr = cpu_to_le64(mapping);
1761 wmb();
1762 rtl8169_mark_to_asic(desc, rx_buf_sz);
1763}
1764
1765static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
1766 struct RxDesc *desc, int rx_buf_sz)
1767{
1768 struct sk_buff *skb;
1769 dma_addr_t mapping;
1770 int ret = 0;
1771
1772 skb = dev_alloc_skb(rx_buf_sz + NET_IP_ALIGN);
1773 if (!skb)
1774 goto err_out;
1775
1776 skb_reserve(skb, NET_IP_ALIGN);
1777 *sk_buff = skb;
1778
1779 mapping = pci_map_single(pdev, skb->tail, rx_buf_sz,
1780 PCI_DMA_FROMDEVICE);
1781
1782 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1783
1784out:
1785 return ret;
1786
1787err_out:
1788 ret = -ENOMEM;
1789 rtl8169_make_unusable_by_asic(desc);
1790 goto out;
1791}
1792
1793static void rtl8169_rx_clear(struct rtl8169_private *tp)
1794{
1795 int i;
1796
1797 for (i = 0; i < NUM_RX_DESC; i++) {
1798 if (tp->Rx_skbuff[i]) {
1799 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
1800 tp->RxDescArray + i);
1801 }
1802 }
1803}
1804
1805static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
1806 u32 start, u32 end)
1807{
1808 u32 cur;
1809
1810 for (cur = start; end - cur > 0; cur++) {
1811 int ret, i = cur % NUM_RX_DESC;
1812
1813 if (tp->Rx_skbuff[i])
1814 continue;
1815
1816 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
1817 tp->RxDescArray + i, tp->rx_buf_sz);
1818 if (ret < 0)
1819 break;
1820 }
1821 return cur - start;
1822}
1823
1824static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1825{
1826 desc->opts1 |= cpu_to_le32(RingEnd);
1827}
1828
1829static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
1830{
1831 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
1832}
1833
1834static int rtl8169_init_ring(struct net_device *dev)
1835{
1836 struct rtl8169_private *tp = netdev_priv(dev);
1837
1838 rtl8169_init_ring_indexes(tp);
1839
1840 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
1841 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
1842
1843 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
1844 goto err_out;
1845
1846 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
1847
1848 return 0;
1849
1850err_out:
1851 rtl8169_rx_clear(tp);
1852 return -ENOMEM;
1853}
1854
1855static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
1856 struct TxDesc *desc)
1857{
1858 unsigned int len = tx_skb->len;
1859
1860 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
1861 desc->opts1 = 0x00;
1862 desc->opts2 = 0x00;
1863 desc->addr = 0x00;
1864 tx_skb->len = 0;
1865}
1866
1867static void rtl8169_tx_clear(struct rtl8169_private *tp)
1868{
1869 unsigned int i;
1870
1871 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
1872 unsigned int entry = i % NUM_TX_DESC;
1873 struct ring_info *tx_skb = tp->tx_skb + entry;
1874 unsigned int len = tx_skb->len;
1875
1876 if (len) {
1877 struct sk_buff *skb = tx_skb->skb;
1878
1879 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
1880 tp->TxDescArray + entry);
1881 if (skb) {
1882 dev_kfree_skb(skb);
1883 tx_skb->skb = NULL;
1884 }
1885 tp->stats.tx_dropped++;
1886 }
1887 }
1888 tp->cur_tx = tp->dirty_tx = 0;
1889}
1890
1891static void rtl8169_schedule_work(struct net_device *dev, void (*task)(void *))
1892{
1893 struct rtl8169_private *tp = netdev_priv(dev);
1894
1895 PREPARE_WORK(&tp->task, task, dev);
1896 schedule_delayed_work(&tp->task, 4);
1897}
1898
1899static void rtl8169_wait_for_quiescence(struct net_device *dev)
1900{
1901 struct rtl8169_private *tp = netdev_priv(dev);
1902 void __iomem *ioaddr = tp->mmio_addr;
1903
1904 synchronize_irq(dev->irq);
1905
1906 /* Wait for any pending NAPI task to complete */
1907 netif_poll_disable(dev);
1908
1909 rtl8169_irq_mask_and_ack(ioaddr);
1910
1911 netif_poll_enable(dev);
1912}
1913
1914static void rtl8169_reinit_task(void *_data)
1915{
1916 struct net_device *dev = _data;
1917 int ret;
1918
1919 if (netif_running(dev)) {
1920 rtl8169_wait_for_quiescence(dev);
1921 rtl8169_close(dev);
1922 }
1923
1924 ret = rtl8169_open(dev);
1925 if (unlikely(ret < 0)) {
1926 if (net_ratelimit()) {
b57b7e5a
SH		 1927 struct rtl8169_private *tp = netdev_priv(dev);
1928
1929 if (netif_msg_drv(tp)) {
1930 printk(PFX KERN_ERR
1931 "%s: reinit failure (status = %d)."
1932 " Rescheduling.\n", dev->name, ret);
1933 }
1da177e4
LT		 1934 }
1935 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1936 }
1937}
1938
1939static void rtl8169_reset_task(void *_data)
1940{
1941 struct net_device *dev = _data;
1942 struct rtl8169_private *tp = netdev_priv(dev);
1943
1944 if (!netif_running(dev))
1945 return;
1946
1947 rtl8169_wait_for_quiescence(dev);
1948
1949 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
1950 rtl8169_tx_clear(tp);
1951
1952 if (tp->dirty_rx == tp->cur_rx) {
1953 rtl8169_init_ring_indexes(tp);
1954 rtl8169_hw_start(dev);
1955 netif_wake_queue(dev);
1956 } else {
1957 if (net_ratelimit()) {
b57b7e5a
SH		 1958 struct rtl8169_private *tp = netdev_priv(dev);
1959
1960 if (netif_msg_intr(tp)) {
1961 printk(PFX KERN_EMERG
1962 "%s: Rx buffers shortage\n", dev->name);
1963 }
1da177e4
LT		 1964 }
1965 rtl8169_schedule_work(dev, rtl8169_reset_task);
1966 }
1967}
1968
1969static void rtl8169_tx_timeout(struct net_device *dev)
1970{
1971 struct rtl8169_private *tp = netdev_priv(dev);
1972
1973 rtl8169_hw_reset(tp->mmio_addr);
1974
1975 /* Let's wait a bit while any (async) irq lands on */
1976 rtl8169_schedule_work(dev, rtl8169_reset_task);
1977}
1978
1979static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
1980 u32 opts1)
1981{
1982 struct skb_shared_info *info = skb_shinfo(skb);
1983 unsigned int cur_frag, entry;
1984 struct TxDesc *txd;
1985
1986 entry = tp->cur_tx;
1987 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
1988 skb_frag_t *frag = info->frags + cur_frag;
1989 dma_addr_t mapping;
1990 u32 status, len;
1991 void *addr;
1992
1993 entry = (entry + 1) % NUM_TX_DESC;
1994
1995 txd = tp->TxDescArray + entry;
1996 len = frag->size;
1997 addr = ((void *) page_address(frag->page)) + frag->page_offset;
1998 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
1999
2000 /* anti gcc 2.95.3 bugware (sic) */
2001 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2002
2003 txd->opts1 = cpu_to_le32(status);
2004 txd->addr = cpu_to_le64(mapping);
2005
2006 tp->tx_skb[entry].len = len;
2007 }
2008
2009 if (cur_frag) {
2010 tp->tx_skb[entry].skb = skb;
2011 txd->opts1 |= cpu_to_le32(LastFrag);
2012 }
2013
2014 return cur_frag;
2015}
2016
2017static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2018{
2019 if (dev->features & NETIF_F_TSO) {
2020 u32 mss = skb_shinfo(skb)->tso_size;
2021
2022 if (mss)
2023 return LargeSend | ((mss & MSSMask) << MSSShift);
2024 }
2025 if (skb->ip_summed == CHECKSUM_HW) {
2026 const struct iphdr *ip = skb->nh.iph;
2027
2028 if (ip->protocol == IPPROTO_TCP)
2029 return IPCS | TCPCS;
2030 else if (ip->protocol == IPPROTO_UDP)
2031 return IPCS | UDPCS;
2032 WARN_ON(1); /* we need a WARN() */
2033 }
2034 return 0;
2035}
2036
2037static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2038{
2039 struct rtl8169_private *tp = netdev_priv(dev);
2040 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2041 struct TxDesc *txd = tp->TxDescArray + entry;
2042 void __iomem *ioaddr = tp->mmio_addr;
2043 dma_addr_t mapping;
2044 u32 status, len;
2045 u32 opts1;
2046 int ret = 0;
2047
2048 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2049 if (netif_msg_drv(tp)) {
2050 printk(KERN_ERR
2051 "%s: BUG! Tx Ring full when queue awake!\n",
2052 dev->name);
2053 }
1da177e4
LT		 2054 goto err_stop;
2055 }
2056
2057 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2058 goto err_stop;
2059
2060 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2061
2062 frags = rtl8169_xmit_frags(tp, skb, opts1);
2063 if (frags) {
2064 len = skb_headlen(skb);
2065 opts1 |= FirstFrag;
2066 } else {
2067 len = skb->len;
2068
2069 if (unlikely(len < ETH_ZLEN)) {
2070 skb = skb_padto(skb, ETH_ZLEN);
2071 if (!skb)
2072 goto err_update_stats;
2073 len = ETH_ZLEN;
2074 }
2075
2076 opts1 |= FirstFrag | LastFrag;
2077 tp->tx_skb[entry].skb = skb;
2078 }
2079
2080 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2081
2082 tp->tx_skb[entry].len = len;
2083 txd->addr = cpu_to_le64(mapping);
2084 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2085
2086 wmb();
2087
2088 /* anti gcc 2.95.3 bugware (sic) */
2089 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2090 txd->opts1 = cpu_to_le32(status);
2091
2092 dev->trans_start = jiffies;
2093
2094 tp->cur_tx += frags + 1;
2095
2096 smp_wmb();
2097
2098 RTL_W8(TxPoll, 0x40); /* set polling bit */
2099
2100 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2101 netif_stop_queue(dev);
2102 smp_rmb();
2103 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2104 netif_wake_queue(dev);
2105 }
2106
2107out:
2108 return ret;
2109
2110err_stop:
2111 netif_stop_queue(dev);
2112 ret = 1;
2113err_update_stats:
2114 tp->stats.tx_dropped++;
2115 goto out;
2116}
2117
2118static void rtl8169_pcierr_interrupt(struct net_device *dev)
2119{
2120 struct rtl8169_private *tp = netdev_priv(dev);
2121 struct pci_dev *pdev = tp->pci_dev;
2122 void __iomem *ioaddr = tp->mmio_addr;
2123 u16 pci_status, pci_cmd;
2124
2125 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2126 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2127
b57b7e5a
SH		 2128 if (netif_msg_intr(tp)) {
2129 printk(KERN_ERR
2130 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2131 dev->name, pci_cmd, pci_status);
2132 }
1da177e4
LT		 2133
2134 /*
2135 * The recovery sequence below admits a very elaborated explanation:
2136 * - it seems to work;
2137 * - I did not see what else could be done.
2138 *
2139 * Feel free to adjust to your needs.
2140 */
2141 pci_write_config_word(pdev, PCI_COMMAND,
2142 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2143
2144 pci_write_config_word(pdev, PCI_STATUS,
2145 pci_status & (PCI_STATUS_DETECTED_PARITY |
2146 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2147 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2148
2149 /* The infamous DAC f*ckup only happens at boot time */
2150 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2151 if (netif_msg_intr(tp))
2152 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2153 tp->cp_cmd &= ~PCIDAC;
2154 RTL_W16(CPlusCmd, tp->cp_cmd);
2155 dev->features &= ~NETIF_F_HIGHDMA;
2156 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2157 }
2158
2159 rtl8169_hw_reset(ioaddr);
2160}
2161
2162static void
2163rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2164 void __iomem *ioaddr)
2165{
2166 unsigned int dirty_tx, tx_left;
2167
2168 assert(dev != NULL);
2169 assert(tp != NULL);
2170 assert(ioaddr != NULL);
2171
2172 dirty_tx = tp->dirty_tx;
2173 smp_rmb();
2174 tx_left = tp->cur_tx - dirty_tx;
2175
2176 while (tx_left > 0) {
2177 unsigned int entry = dirty_tx % NUM_TX_DESC;
2178 struct ring_info *tx_skb = tp->tx_skb + entry;
2179 u32 len = tx_skb->len;
2180 u32 status;
2181
2182 rmb();
2183 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2184 if (status & DescOwn)
2185 break;
2186
2187 tp->stats.tx_bytes += len;
2188 tp->stats.tx_packets++;
2189
2190 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2191
2192 if (status & LastFrag) {
2193 dev_kfree_skb_irq(tx_skb->skb);
2194 tx_skb->skb = NULL;
2195 }
2196 dirty_tx++;
2197 tx_left--;
2198 }
2199
2200 if (tp->dirty_tx != dirty_tx) {
2201 tp->dirty_tx = dirty_tx;
2202 smp_wmb();
2203 if (netif_queue_stopped(dev) &&
2204 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2205 netif_wake_queue(dev);
2206 }
2207 }
2208}
2209
126fa4b9
FR		 2210static inline int rtl8169_fragmented_frame(u32 status)
2211{
2212 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2213}
2214
1da177e4
LT		 2215static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2216{
2217 u32 opts1 = le32_to_cpu(desc->opts1);
2218 u32 status = opts1 & RxProtoMask;
2219
2220 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2221 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2222 ((status == RxProtoIP) && !(opts1 & IPFail)))
2223 skb->ip_summed = CHECKSUM_UNNECESSARY;
2224 else
2225 skb->ip_summed = CHECKSUM_NONE;
2226}
2227
2228static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
2229 struct RxDesc *desc, int rx_buf_sz)
2230{
2231 int ret = -1;
2232
2233 if (pkt_size < rx_copybreak) {
2234 struct sk_buff *skb;
2235
2236 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
2237 if (skb) {
2238 skb_reserve(skb, NET_IP_ALIGN);
2239 eth_copy_and_sum(skb, sk_buff[0]->tail, pkt_size, 0);
2240 *sk_buff = skb;
2241 rtl8169_mark_to_asic(desc, rx_buf_sz);
2242 ret = 0;
2243 }
2244 }
2245 return ret;
2246}
2247
2248static int
2249rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2250 void __iomem *ioaddr)
2251{
2252 unsigned int cur_rx, rx_left;
2253 unsigned int delta, count;
2254
2255 assert(dev != NULL);
2256 assert(tp != NULL);
2257 assert(ioaddr != NULL);
2258
2259 cur_rx = tp->cur_rx;
2260 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2261 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2262
2263 while (rx_left > 0) {
2264 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2265 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2266 u32 status;
2267
2268 rmb();
126fa4b9 2269 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2270
2271 if (status & DescOwn)
2272 break;
2273 if (status & RxRES) {
b57b7e5a
SH		 2274 if (netif_msg_rx_err(tp)) {
2275 printk(KERN_INFO
2276 "%s: Rx ERROR. status = %08x\n",
2277 dev->name, status);
2278 }
1da177e4
LT		 2279 tp->stats.rx_errors++;
2280 if (status & (RxRWT | RxRUNT))
2281 tp->stats.rx_length_errors++;
2282 if (status & RxCRC)
2283 tp->stats.rx_crc_errors++;
126fa4b9 2284 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2285 } else {
1da177e4
LT		 2286 struct sk_buff *skb = tp->Rx_skbuff[entry];
2287 int pkt_size = (status & 0x00001FFF) - 4;
2288 void (*pci_action)(struct pci_dev *, dma_addr_t,
2289 size_t, int) = pci_dma_sync_single_for_device;
2290
126fa4b9
FR		 2291 /*
2292 * The driver does not support incoming fragmented
2293 * frames. They are seen as a symptom of over-mtu
2294 * sized frames.
2295 */
2296 if (unlikely(rtl8169_fragmented_frame(status))) {
2297 tp->stats.rx_dropped++;
2298 tp->stats.rx_length_errors++;
2299 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2300 goto move_on;
2301 }
2302
1da177e4
LT		 2303 rtl8169_rx_csum(skb, desc);
2304
2305 pci_dma_sync_single_for_cpu(tp->pci_dev,
2306 le64_to_cpu(desc->addr), tp->rx_buf_sz,
2307 PCI_DMA_FROMDEVICE);
2308
2309 if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
2310 tp->rx_buf_sz)) {
2311 pci_action = pci_unmap_single;
2312 tp->Rx_skbuff[entry] = NULL;
2313 }
2314
2315 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
2316 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
2317
2318 skb->dev = dev;
2319 skb_put(skb, pkt_size);
2320 skb->protocol = eth_type_trans(skb, dev);
2321
2322 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2323 rtl8169_rx_skb(skb);
2324
2325 dev->last_rx = jiffies;
2326 tp->stats.rx_bytes += pkt_size;
2327 tp->stats.rx_packets++;
2328 }
126fa4b9 2329move_on:
1da177e4
LT		 2330 cur_rx++;
2331 rx_left--;
2332 }
2333
2334 count = cur_rx - tp->cur_rx;
2335 tp->cur_rx = cur_rx;
2336
2337 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2338 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2339 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2340 tp->dirty_rx += delta;
2341
2342 /*
2343 * FIXME: until there is periodic timer to try and refill the ring,
2344 * a temporary shortage may definitely kill the Rx process.
2345 * - disable the asic to try and avoid an overflow and kick it again
2346 * after refill ?
2347 * - how do others driver handle this condition (Uh oh...).
2348 */
b57b7e5a 2349 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2350 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2351
2352 return count;
2353}
2354
2355/* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2356static irqreturn_t
2357rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
2358{
2359 struct net_device *dev = (struct net_device *) dev_instance;
2360 struct rtl8169_private *tp = netdev_priv(dev);
2361 int boguscnt = max_interrupt_work;
2362 void __iomem *ioaddr = tp->mmio_addr;
2363 int status;
2364 int handled = 0;
2365
2366 do {
2367 status = RTL_R16(IntrStatus);
2368
2369 /* hotplug/major error/no more work/shared irq */
2370 if ((status == 0xFFFF) || !status)
2371 break;
2372
2373 handled = 1;
2374
2375 if (unlikely(!netif_running(dev))) {
2376 rtl8169_asic_down(ioaddr);
2377 goto out;
2378 }
2379
2380 status &= tp->intr_mask;
2381 RTL_W16(IntrStatus,
2382 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2383
2384 if (!(status & rtl8169_intr_mask))
2385 break;
2386
2387 if (unlikely(status & SYSErr)) {
2388 rtl8169_pcierr_interrupt(dev);
2389 break;
2390 }
2391
2392 if (status & LinkChg)
2393 rtl8169_check_link_status(dev, tp, ioaddr);
2394
2395#ifdef CONFIG_R8169_NAPI
2396 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
2397 tp->intr_mask = ~rtl8169_napi_event;
2398
2399 if (likely(netif_rx_schedule_prep(dev)))
2400 __netif_rx_schedule(dev);
b57b7e5a 2401 else if (netif_msg_intr(tp)) {
1da177e4
LT		 2402 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2403 dev->name, status);
2404 }
2405 break;
2406#else
2407 /* Rx interrupt */
2408 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2409 rtl8169_rx_interrupt(dev, tp, ioaddr);
2410 }
2411 /* Tx interrupt */
2412 if (status & (TxOK | TxErr))
2413 rtl8169_tx_interrupt(dev, tp, ioaddr);
2414#endif
2415
2416 boguscnt--;
2417 } while (boguscnt > 0);
2418
2419 if (boguscnt <= 0) {
b57b7e5a
SH		 2420 if (net_ratelimit() && netif_msg_intr(tp)) {
2421 printk(KERN_WARNING
2422 "%s: Too much work at interrupt!\n", dev->name);
2423 }
1da177e4
LT		 2424 /* Clear all interrupt sources. */
2425 RTL_W16(IntrStatus, 0xffff);
2426 }
2427out:
2428 return IRQ_RETVAL(handled);
2429}
2430
2431#ifdef CONFIG_R8169_NAPI
2432static int rtl8169_poll(struct net_device *dev, int *budget)
2433{
2434 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2435 struct rtl8169_private *tp = netdev_priv(dev);
2436 void __iomem *ioaddr = tp->mmio_addr;
2437
2438 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2439 rtl8169_tx_interrupt(dev, tp, ioaddr);
2440
2441 *budget -= work_done;
2442 dev->quota -= work_done;
2443
2444 if (work_done < work_to_do) {
2445 netif_rx_complete(dev);
2446 tp->intr_mask = 0xffff;
2447 /*
2448 * 20040426: the barrier is not strictly required but the
2449 * behavior of the irq handler could be less predictable
2450 * without it. Btw, the lack of flush for the posted pci
2451 * write is safe - FR
2452 */
2453 smp_wmb();
2454 RTL_W16(IntrMask, rtl8169_intr_mask);
2455 }
2456
2457 return (work_done >= work_to_do);
2458}
2459#endif
2460
2461static void rtl8169_down(struct net_device *dev)
2462{
2463 struct rtl8169_private *tp = netdev_priv(dev);
2464 void __iomem *ioaddr = tp->mmio_addr;
2465 unsigned int poll_locked = 0;
2466
2467 rtl8169_delete_timer(dev);
2468
2469 netif_stop_queue(dev);
2470
2471 flush_scheduled_work();
2472
2473core_down:
2474 spin_lock_irq(&tp->lock);
2475
2476 rtl8169_asic_down(ioaddr);
2477
2478 /* Update the error counts. */
2479 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2480 RTL_W32(RxMissed, 0);
2481
2482 spin_unlock_irq(&tp->lock);
2483
2484 synchronize_irq(dev->irq);
2485
2486 if (!poll_locked) {
2487 netif_poll_disable(dev);
2488 poll_locked++;
2489 }
2490
2491 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2492 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2493
2494 /*
2495 * And now for the 50k$ question: are IRQ disabled or not ?
2496 *
2497 * Two paths lead here:
2498 * 1) dev->close
2499 * -> netif_running() is available to sync the current code and the
2500 * IRQ handler. See rtl8169_interrupt for details.
2501 * 2) dev->change_mtu
2502 * -> rtl8169_poll can not be issued again and re-enable the
2503 * interruptions. Let's simply issue the IRQ down sequence again.
2504 */
2505 if (RTL_R16(IntrMask))
2506 goto core_down;
2507
2508 rtl8169_tx_clear(tp);
2509
2510 rtl8169_rx_clear(tp);
2511}
2512
2513static int rtl8169_close(struct net_device *dev)
2514{
2515 struct rtl8169_private *tp = netdev_priv(dev);
2516 struct pci_dev *pdev = tp->pci_dev;
2517
2518 rtl8169_down(dev);
2519
2520 free_irq(dev->irq, dev);
2521
2522 netif_poll_enable(dev);
2523
2524 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2525 tp->RxPhyAddr);
2526 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2527 tp->TxPhyAddr);
2528 tp->TxDescArray = NULL;
2529 tp->RxDescArray = NULL;
2530
2531 return 0;
2532}
2533
2534static void
2535rtl8169_set_rx_mode(struct net_device *dev)
2536{
2537 struct rtl8169_private *tp = netdev_priv(dev);
2538 void __iomem *ioaddr = tp->mmio_addr;
2539 unsigned long flags;
2540 u32 mc_filter[2]; /* Multicast hash filter */
2541 int i, rx_mode;
2542 u32 tmp = 0;
2543
2544 if (dev->flags & IFF_PROMISC) {
2545 /* Unconditionally log net taps. */
b57b7e5a
SH		 2546 if (netif_msg_link(tp)) {
2547 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2548 dev->name);
2549 }
1da177e4
LT		 2550 rx_mode =
2551 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2552 AcceptAllPhys;
2553 mc_filter[1] = mc_filter[0] = 0xffffffff;
2554 } else if ((dev->mc_count > multicast_filter_limit)
2555 || (dev->flags & IFF_ALLMULTI)) {
2556 /* Too many to filter perfectly -- accept all multicasts. */
2557 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2558 mc_filter[1] = mc_filter[0] = 0xffffffff;
2559 } else {
2560 struct dev_mc_list *mclist;
2561 rx_mode = AcceptBroadcast | AcceptMyPhys;
2562 mc_filter[1] = mc_filter[0] = 0;
2563 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2564 i++, mclist = mclist->next) {
2565 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2566 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2567 rx_mode |= AcceptMulticast;
2568 }
2569 }
2570
2571 spin_lock_irqsave(&tp->lock, flags);
2572
2573 tmp = rtl8169_rx_config | rx_mode |
2574 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2575
2576 RTL_W32(RxConfig, tmp);
2577 RTL_W32(MAR0 + 0, mc_filter[0]);
2578 RTL_W32(MAR0 + 4, mc_filter[1]);
2579
2580 spin_unlock_irqrestore(&tp->lock, flags);
2581}
2582
2583/**
2584 * rtl8169_get_stats - Get rtl8169 read/write statistics
2585 * @dev: The Ethernet Device to get statistics for
2586 *
2587 * Get TX/RX statistics for rtl8169
2588 */
2589static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2590{
2591 struct rtl8169_private *tp = netdev_priv(dev);
2592 void __iomem *ioaddr = tp->mmio_addr;
2593 unsigned long flags;
2594
2595 if (netif_running(dev)) {
2596 spin_lock_irqsave(&tp->lock, flags);
2597 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2598 RTL_W32(RxMissed, 0);
2599 spin_unlock_irqrestore(&tp->lock, flags);
2600 }
2601
2602 return &tp->stats;
2603}
2604
2605static struct pci_driver rtl8169_pci_driver = {
2606 .name = MODULENAME,
2607 .id_table = rtl8169_pci_tbl,
2608 .probe = rtl8169_init_one,
2609 .remove = __devexit_p(rtl8169_remove_one),
2610#ifdef CONFIG_PM
2611 .suspend = rtl8169_suspend,
2612 .resume = rtl8169_resume,
2613#endif
2614};
2615
2616static int __init
2617rtl8169_init_module(void)
2618{
2619 return pci_module_init(&rtl8169_pci_driver);
2620}
2621
2622static void __exit
2623rtl8169_cleanup_module(void)
2624{
2625 pci_unregister_driver(&rtl8169_pci_driver);
2626}
2627
2628module_init(rtl8169_init_module);
2629module_exit(rtl8169_cleanup_module);
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