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[net-next-2.6.git] / drivers / net / qlge / qlge_dbg.c
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c4e84bde
RM		 1#include "qlge.h"
2
24bb55b4
RM		 3/* Read a NIC register from the alternate function. */
4static u32 ql_read_other_func_reg(struct ql_adapter *qdev,
5 u32 reg)
6{
7 u32 register_to_read;
8 u32 reg_val;
9 unsigned int status = 0;
10
11 register_to_read = MPI_NIC_REG_BLOCK
12 | MPI_NIC_READ
13 | (qdev->alt_func << MPI_NIC_FUNCTION_SHIFT)
14 | reg;
15 status = ql_read_mpi_reg(qdev, register_to_read, &reg_val);
16 if (status != 0)
17 return 0xffffffff;
18
19 return reg_val;
20}
a61f8026 21
a48c86fd
RM		 22/* Write a NIC register from the alternate function. */
23static int ql_write_other_func_reg(struct ql_adapter *qdev,
24 u32 reg, u32 reg_val)
25{
26 u32 register_to_read;
27 int status = 0;
28
29 register_to_read = MPI_NIC_REG_BLOCK
30 | MPI_NIC_READ
31 | (qdev->alt_func << MPI_NIC_FUNCTION_SHIFT)
32 | reg;
33 status = ql_write_mpi_reg(qdev, register_to_read, reg_val);
34
35 return status;
36}
37
38static int ql_wait_other_func_reg_rdy(struct ql_adapter *qdev, u32 reg,
39 u32 bit, u32 err_bit)
40{
41 u32 temp;
42 int count = 10;
43
44 while (count) {
45 temp = ql_read_other_func_reg(qdev, reg);
46
47 /* check for errors */
48 if (temp & err_bit)
49 return -1;
50 else if (temp & bit)
51 return 0;
52 mdelay(10);
53 count--;
54 }
55 return -1;
56}
57
58static int ql_read_other_func_serdes_reg(struct ql_adapter *qdev, u32 reg,
59 u32 *data)
60{
61 int status;
62
63 /* wait for reg to come ready */
64 status = ql_wait_other_func_reg_rdy(qdev, XG_SERDES_ADDR / 4,
65 XG_SERDES_ADDR_RDY, 0);
66 if (status)
67 goto exit;
68
69 /* set up for reg read */
70 ql_write_other_func_reg(qdev, XG_SERDES_ADDR/4, reg | PROC_ADDR_R);
71
72 /* wait for reg to come ready */
73 status = ql_wait_other_func_reg_rdy(qdev, XG_SERDES_ADDR / 4,
74 XG_SERDES_ADDR_RDY, 0);
75 if (status)
76 goto exit;
77
78 /* get the data */
79 *data = ql_read_other_func_reg(qdev, (XG_SERDES_DATA / 4));
80exit:
81 return status;
82}
83
84/* Read out the SERDES registers */
85static int ql_read_serdes_reg(struct ql_adapter *qdev, u32 reg, u32 * data)
86{
87 int status;
88
89 /* wait for reg to come ready */
90 status = ql_wait_reg_rdy(qdev, XG_SERDES_ADDR, XG_SERDES_ADDR_RDY, 0);
91 if (status)
92 goto exit;
93
94 /* set up for reg read */
95 ql_write32(qdev, XG_SERDES_ADDR, reg | PROC_ADDR_R);
96
97 /* wait for reg to come ready */
98 status = ql_wait_reg_rdy(qdev, XG_SERDES_ADDR, XG_SERDES_ADDR_RDY, 0);
99 if (status)
100 goto exit;
101
102 /* get the data */
103 *data = ql_read32(qdev, XG_SERDES_DATA);
104exit:
105 return status;
106}
107
108static void ql_get_both_serdes(struct ql_adapter *qdev, u32 addr,
109 u32 *direct_ptr, u32 *indirect_ptr,
110 unsigned int direct_valid, unsigned int indirect_valid)
111{
112 unsigned int status;
113
114 status = 1;
115 if (direct_valid)
116 status = ql_read_serdes_reg(qdev, addr, direct_ptr);
117 /* Dead fill any failures or invalids. */
118 if (status)
119 *direct_ptr = 0xDEADBEEF;
120
121 status = 1;
122 if (indirect_valid)
123 status = ql_read_other_func_serdes_reg(
124 qdev, addr, indirect_ptr);
125 /* Dead fill any failures or invalids. */
126 if (status)
127 *indirect_ptr = 0xDEADBEEF;
128}
129
130static int ql_get_serdes_regs(struct ql_adapter *qdev,
131 struct ql_mpi_coredump *mpi_coredump)
132{
133 int status;
134 unsigned int xfi_direct_valid, xfi_indirect_valid, xaui_direct_valid;
135 unsigned int xaui_indirect_valid, i;
136 u32 *direct_ptr, temp;
137 u32 *indirect_ptr;
138
139 xfi_direct_valid = xfi_indirect_valid = 0;
140 xaui_direct_valid = xaui_indirect_valid = 1;
141
142 /* The XAUI needs to be read out per port */
143 if (qdev->func & 1) {
144 /* We are NIC 2 */
145 status = ql_read_other_func_serdes_reg(qdev,
146 XG_SERDES_XAUI_HSS_PCS_START, &temp);
147 if (status)
148 temp = XG_SERDES_ADDR_XAUI_PWR_DOWN;
149 if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) ==
150 XG_SERDES_ADDR_XAUI_PWR_DOWN)
151 xaui_indirect_valid = 0;
152
153 status = ql_read_serdes_reg(qdev,
154 XG_SERDES_XAUI_HSS_PCS_START, &temp);
155 if (status)
156 temp = XG_SERDES_ADDR_XAUI_PWR_DOWN;
157
158 if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) ==
159 XG_SERDES_ADDR_XAUI_PWR_DOWN)
160 xaui_direct_valid = 0;
161 } else {
162 /* We are NIC 1 */
163 status = ql_read_other_func_serdes_reg(qdev,
164 XG_SERDES_XAUI_HSS_PCS_START, &temp);
165 if (status)
166 temp = XG_SERDES_ADDR_XAUI_PWR_DOWN;
167 if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) ==
168 XG_SERDES_ADDR_XAUI_PWR_DOWN)
169 xaui_indirect_valid = 0;
170
171 status = ql_read_serdes_reg(qdev,
172 XG_SERDES_XAUI_HSS_PCS_START, &temp);
173 if (status)
174 temp = XG_SERDES_ADDR_XAUI_PWR_DOWN;
175 if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) ==
176 XG_SERDES_ADDR_XAUI_PWR_DOWN)
177 xaui_direct_valid = 0;
178 }
179
180 /*
181 * XFI register is shared so only need to read one
182 * functions and then check the bits.
183 */
184 status = ql_read_serdes_reg(qdev, XG_SERDES_ADDR_STS, &temp);
185 if (status)
186 temp = 0;
187
188 if ((temp & XG_SERDES_ADDR_XFI1_PWR_UP) ==
189 XG_SERDES_ADDR_XFI1_PWR_UP) {
190 /* now see if i'm NIC 1 or NIC 2 */
191 if (qdev->func & 1)
192 /* I'm NIC 2, so the indirect (NIC1) xfi is up. */
193 xfi_indirect_valid = 1;
194 else
195 xfi_direct_valid = 1;
196 }
197 if ((temp & XG_SERDES_ADDR_XFI2_PWR_UP) ==
198 XG_SERDES_ADDR_XFI2_PWR_UP) {
199 /* now see if i'm NIC 1 or NIC 2 */
200 if (qdev->func & 1)
201 /* I'm NIC 2, so the indirect (NIC1) xfi is up. */
202 xfi_direct_valid = 1;
203 else
204 xfi_indirect_valid = 1;
205 }
206
207 /* Get XAUI_AN register block. */
208 if (qdev->func & 1) {
209 /* Function 2 is direct */
210 direct_ptr = mpi_coredump->serdes2_xaui_an;
211 indirect_ptr = mpi_coredump->serdes_xaui_an;
212 } else {
213 /* Function 1 is direct */
214 direct_ptr = mpi_coredump->serdes_xaui_an;
215 indirect_ptr = mpi_coredump->serdes2_xaui_an;
216 }
217
218 for (i = 0; i <= 0x000000034; i += 4, direct_ptr++, indirect_ptr++)
219 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
220 xaui_direct_valid, xaui_indirect_valid);
221
222 /* Get XAUI_HSS_PCS register block. */
223 if (qdev->func & 1) {
224 direct_ptr =
225 mpi_coredump->serdes2_xaui_hss_pcs;
226 indirect_ptr =
227 mpi_coredump->serdes_xaui_hss_pcs;
228 } else {
229 direct_ptr =
230 mpi_coredump->serdes_xaui_hss_pcs;
231 indirect_ptr =
232 mpi_coredump->serdes2_xaui_hss_pcs;
233 }
234
235 for (i = 0x800; i <= 0x880; i += 4, direct_ptr++, indirect_ptr++)
236 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
237 xaui_direct_valid, xaui_indirect_valid);
238
239 /* Get XAUI_XFI_AN register block. */
240 if (qdev->func & 1) {
241 direct_ptr = mpi_coredump->serdes2_xfi_an;
242 indirect_ptr = mpi_coredump->serdes_xfi_an;
243 } else {
244 direct_ptr = mpi_coredump->serdes_xfi_an;
245 indirect_ptr = mpi_coredump->serdes2_xfi_an;
246 }
247
248 for (i = 0x1000; i <= 0x1034; i += 4, direct_ptr++, indirect_ptr++)
249 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
250 xfi_direct_valid, xfi_indirect_valid);
251
252 /* Get XAUI_XFI_TRAIN register block. */
253 if (qdev->func & 1) {
254 direct_ptr = mpi_coredump->serdes2_xfi_train;
255 indirect_ptr =
256 mpi_coredump->serdes_xfi_train;
257 } else {
258 direct_ptr = mpi_coredump->serdes_xfi_train;
259 indirect_ptr =
260 mpi_coredump->serdes2_xfi_train;
261 }
262
263 for (i = 0x1050; i <= 0x107c; i += 4, direct_ptr++, indirect_ptr++)
264 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
265 xfi_direct_valid, xfi_indirect_valid);
266
267 /* Get XAUI_XFI_HSS_PCS register block. */
268 if (qdev->func & 1) {
269 direct_ptr =
270 mpi_coredump->serdes2_xfi_hss_pcs;
271 indirect_ptr =
272 mpi_coredump->serdes_xfi_hss_pcs;
273 } else {
274 direct_ptr =
275 mpi_coredump->serdes_xfi_hss_pcs;
276 indirect_ptr =
277 mpi_coredump->serdes2_xfi_hss_pcs;
278 }
279
280 for (i = 0x1800; i <= 0x1838; i += 4, direct_ptr++, indirect_ptr++)
281 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
282 xfi_direct_valid, xfi_indirect_valid);
283
284 /* Get XAUI_XFI_HSS_TX register block. */
285 if (qdev->func & 1) {
286 direct_ptr =
287 mpi_coredump->serdes2_xfi_hss_tx;
288 indirect_ptr =
289 mpi_coredump->serdes_xfi_hss_tx;
290 } else {
291 direct_ptr = mpi_coredump->serdes_xfi_hss_tx;
292 indirect_ptr =
293 mpi_coredump->serdes2_xfi_hss_tx;
294 }
295 for (i = 0x1c00; i <= 0x1c1f; i++, direct_ptr++, indirect_ptr++)
296 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
297 xfi_direct_valid, xfi_indirect_valid);
298
299 /* Get XAUI_XFI_HSS_RX register block. */
300 if (qdev->func & 1) {
301 direct_ptr =
302 mpi_coredump->serdes2_xfi_hss_rx;
303 indirect_ptr =
304 mpi_coredump->serdes_xfi_hss_rx;
305 } else {
306 direct_ptr = mpi_coredump->serdes_xfi_hss_rx;
307 indirect_ptr =
308 mpi_coredump->serdes2_xfi_hss_rx;
309 }
310
311 for (i = 0x1c40; i <= 0x1c5f; i++, direct_ptr++, indirect_ptr++)
312 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
313 xfi_direct_valid, xfi_indirect_valid);
314
315
316 /* Get XAUI_XFI_HSS_PLL register block. */
317 if (qdev->func & 1) {
318 direct_ptr =
319 mpi_coredump->serdes2_xfi_hss_pll;
320 indirect_ptr =
321 mpi_coredump->serdes_xfi_hss_pll;
322 } else {
323 direct_ptr =
324 mpi_coredump->serdes_xfi_hss_pll;
325 indirect_ptr =
326 mpi_coredump->serdes2_xfi_hss_pll;
327 }
328 for (i = 0x1e00; i <= 0x1e1f; i++, direct_ptr++, indirect_ptr++)
329 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
330 xfi_direct_valid, xfi_indirect_valid);
331 return 0;
332}
333
a2f98232
RM		 334static int ql_read_other_func_xgmac_reg(struct ql_adapter *qdev, u32 reg,
335 u32 *data)
336{
337 int status = 0;
338
339 /* wait for reg to come ready */
340 status = ql_wait_other_func_reg_rdy(qdev, XGMAC_ADDR / 4,
341 XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
342 if (status)
343 goto exit;
344
345 /* set up for reg read */
346 ql_write_other_func_reg(qdev, XGMAC_ADDR / 4, reg | XGMAC_ADDR_R);
347
348 /* wait for reg to come ready */
349 status = ql_wait_other_func_reg_rdy(qdev, XGMAC_ADDR / 4,
350 XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
351 if (status)
352 goto exit;
353
354 /* get the data */
355 *data = ql_read_other_func_reg(qdev, XGMAC_DATA / 4);
356exit:
357 return status;
358}
359
360/* Read the 400 xgmac control/statistics registers
361 * skipping unused locations.
362 */
363static int ql_get_xgmac_regs(struct ql_adapter *qdev, u32 * buf,
364 unsigned int other_function)
365{
366 int status = 0;
367 int i;
368
369 for (i = PAUSE_SRC_LO; i < XGMAC_REGISTER_END; i += 4, buf++) {
370 /* We're reading 400 xgmac registers, but we filter out
371 * serveral locations that are non-responsive to reads.
372 */
373 if ((i == 0x00000114) ||
374 (i == 0x00000118) ||
375 (i == 0x0000013c) ||
376 (i == 0x00000140) ||
377 (i > 0x00000150 && i < 0x000001fc) ||
378 (i > 0x00000278 && i < 0x000002a0) ||
379 (i > 0x000002c0 && i < 0x000002cf) ||
380 (i > 0x000002dc && i < 0x000002f0) ||
381 (i > 0x000003c8 && i < 0x00000400) ||
382 (i > 0x00000400 && i < 0x00000410) ||
383 (i > 0x00000410 && i < 0x00000420) ||
384 (i > 0x00000420 && i < 0x00000430) ||
385 (i > 0x00000430 && i < 0x00000440) ||
386 (i > 0x00000440 && i < 0x00000450) ||
387 (i > 0x00000450 && i < 0x00000500) ||
388 (i > 0x0000054c && i < 0x00000568) ||
389 (i > 0x000005c8 && i < 0x00000600)) {
390 if (other_function)
391 status =
392 ql_read_other_func_xgmac_reg(qdev, i, buf);
393 else
394 status = ql_read_xgmac_reg(qdev, i, buf);
395
396 if (status)
397 *buf = 0xdeadbeef;
398 break;
399 }
400 }
401 return status;
402}
403
a61f8026
RM		 404static int ql_get_ets_regs(struct ql_adapter *qdev, u32 * buf)
405{
406 int status = 0;
407 int i;
408
409 for (i = 0; i < 8; i++, buf++) {
410 ql_write32(qdev, NIC_ETS, i << 29 | 0x08000000);
411 *buf = ql_read32(qdev, NIC_ETS);
412 }
413
414 for (i = 0; i < 2; i++, buf++) {
415 ql_write32(qdev, CNA_ETS, i << 29 | 0x08000000);
416 *buf = ql_read32(qdev, CNA_ETS);
417 }
418
419 return status;
420}
421
422static void ql_get_intr_states(struct ql_adapter *qdev, u32 * buf)
423{
424 int i;
425
426 for (i = 0; i < qdev->rx_ring_count; i++, buf++) {
427 ql_write32(qdev, INTR_EN,
428 qdev->intr_context[i].intr_read_mask);
429 *buf = ql_read32(qdev, INTR_EN);
430 }
431}
432
433static int ql_get_cam_entries(struct ql_adapter *qdev, u32 * buf)
434{
435 int i, status;
436 u32 value[3];
437
438 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
439 if (status)
440 return status;
441
442 for (i = 0; i < 16; i++) {
443 status = ql_get_mac_addr_reg(qdev,
444 MAC_ADDR_TYPE_CAM_MAC, i, value);
445 if (status) {
ae9540f7
JP		 446 netif_err(qdev, drv, qdev->ndev,
447 "Failed read of mac index register.\n");
a61f8026
RM		 448 goto err;
449 }
450 *buf++ = value[0]; /* lower MAC address */
451 *buf++ = value[1]; /* upper MAC address */
452 *buf++ = value[2]; /* output */
453 }
454 for (i = 0; i < 32; i++) {
455 status = ql_get_mac_addr_reg(qdev,
456 MAC_ADDR_TYPE_MULTI_MAC, i, value);
457 if (status) {
ae9540f7
JP		 458 netif_err(qdev, drv, qdev->ndev,
459 "Failed read of mac index register.\n");
a61f8026
RM		 460 goto err;
461 }
462 *buf++ = value[0]; /* lower Mcast address */
463 *buf++ = value[1]; /* upper Mcast address */
464 }
465err:
466 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
467 return status;
468}
469
470static int ql_get_routing_entries(struct ql_adapter *qdev, u32 * buf)
471{
472 int status;
473 u32 value, i;
474
475 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
476 if (status)
477 return status;
478
479 for (i = 0; i < 16; i++) {
480 status = ql_get_routing_reg(qdev, i, &value);
481 if (status) {
ae9540f7
JP		 482 netif_err(qdev, drv, qdev->ndev,
483 "Failed read of routing index register.\n");
a61f8026
RM		 484 goto err;
485 } else {
486 *buf++ = value;
487 }
488 }
489err:
490 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
491 return status;
492}
493
8aae2600
RM		 494/* Read the MPI Processor shadow registers */
495static int ql_get_mpi_shadow_regs(struct ql_adapter *qdev, u32 * buf)
496{
497 u32 i;
498 int status;
499
500 for (i = 0; i < MPI_CORE_SH_REGS_CNT; i++, buf++) {
501 status = ql_write_mpi_reg(qdev, RISC_124,
502 (SHADOW_OFFSET | i << SHADOW_REG_SHIFT));
503 if (status)
504 goto end;
505 status = ql_read_mpi_reg(qdev, RISC_127, buf);
506 if (status)
507 goto end;
508 }
509end:
510 return status;
511}
512
513/* Read the MPI Processor core registers */
514static int ql_get_mpi_regs(struct ql_adapter *qdev, u32 * buf,
515 u32 offset, u32 count)
516{
517 int i, status = 0;
518 for (i = 0; i < count; i++, buf++) {
519 status = ql_read_mpi_reg(qdev, offset + i, buf);
520 if (status)
521 return status;
522 }
523 return status;
524}
525
c89ec8b9
RM		 526/* Read the ASIC probe dump */
527static unsigned int *ql_get_probe(struct ql_adapter *qdev, u32 clock,
528 u32 valid, u32 *buf)
529{
530 u32 module, mux_sel, probe, lo_val, hi_val;
531
532 for (module = 0; module < PRB_MX_ADDR_MAX_MODS; module++) {
533 if (!((valid >> module) & 1))
534 continue;
535 for (mux_sel = 0; mux_sel < PRB_MX_ADDR_MAX_MUX; mux_sel++) {
536 probe = clock
537 | PRB_MX_ADDR_ARE
538 | mux_sel
539 | (module << PRB_MX_ADDR_MOD_SEL_SHIFT);
540 ql_write32(qdev, PRB_MX_ADDR, probe);
541 lo_val = ql_read32(qdev, PRB_MX_DATA);
542 if (mux_sel == 0) {
543 *buf = probe;
544 buf++;
545 }
546 probe |= PRB_MX_ADDR_UP;
547 ql_write32(qdev, PRB_MX_ADDR, probe);
548 hi_val = ql_read32(qdev, PRB_MX_DATA);
549 *buf = lo_val;
550 buf++;
551 *buf = hi_val;
552 buf++;
553 }
554 }
555 return buf;
556}
557
558static int ql_get_probe_dump(struct ql_adapter *qdev, unsigned int *buf)
559{
560 /* First we have to enable the probe mux */
561 ql_write_mpi_reg(qdev, MPI_TEST_FUNC_PRB_CTL, MPI_TEST_FUNC_PRB_EN);
562 buf = ql_get_probe(qdev, PRB_MX_ADDR_SYS_CLOCK,
563 PRB_MX_ADDR_VALID_SYS_MOD, buf);
564 buf = ql_get_probe(qdev, PRB_MX_ADDR_PCI_CLOCK,
565 PRB_MX_ADDR_VALID_PCI_MOD, buf);
566 buf = ql_get_probe(qdev, PRB_MX_ADDR_XGM_CLOCK,
567 PRB_MX_ADDR_VALID_XGM_MOD, buf);
568 buf = ql_get_probe(qdev, PRB_MX_ADDR_FC_CLOCK,
569 PRB_MX_ADDR_VALID_FC_MOD, buf);
570 return 0;
571
572}
8aae2600
RM		 573
574/* Read out the routing index registers */
575static int ql_get_routing_index_registers(struct ql_adapter *qdev, u32 *buf)
576{
577 int status;
578 u32 type, index, index_max;
579 u32 result_index;
580 u32 result_data;
581 u32 val;
582
583 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
584 if (status)
585 return status;
586
587 for (type = 0; type < 4; type++) {
588 if (type < 2)
589 index_max = 8;
590 else
591 index_max = 16;
592 for (index = 0; index < index_max; index++) {
593 val = RT_IDX_RS
594 | (type << RT_IDX_TYPE_SHIFT)
595 | (index << RT_IDX_IDX_SHIFT);
596 ql_write32(qdev, RT_IDX, val);
597 result_index = 0;
598 while ((result_index & RT_IDX_MR) == 0)
599 result_index = ql_read32(qdev, RT_IDX);
600 result_data = ql_read32(qdev, RT_DATA);
601 *buf = type;
602 buf++;
603 *buf = index;
604 buf++;
605 *buf = result_index;
606 buf++;
607 *buf = result_data;
608 buf++;
609 }
610 }
611 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
612 return status;
613}
614
615/* Read out the MAC protocol registers */
616static void ql_get_mac_protocol_registers(struct ql_adapter *qdev, u32 *buf)
617{
618 u32 result_index, result_data;
619 u32 type;
620 u32 index;
621 u32 offset;
622 u32 val;
623 u32 initial_val = MAC_ADDR_RS;
624 u32 max_index;
625 u32 max_offset;
626
627 for (type = 0; type < MAC_ADDR_TYPE_COUNT; type++) {
628 switch (type) {
629
630 case 0: /* CAM */
631 initial_val |= MAC_ADDR_ADR;
632 max_index = MAC_ADDR_MAX_CAM_ENTRIES;
633 max_offset = MAC_ADDR_MAX_CAM_WCOUNT;
634 break;
635 case 1: /* Multicast MAC Address */
636 max_index = MAC_ADDR_MAX_CAM_WCOUNT;
637 max_offset = MAC_ADDR_MAX_CAM_WCOUNT;
638 break;
639 case 2: /* VLAN filter mask */
640 case 3: /* MC filter mask */
641 max_index = MAC_ADDR_MAX_CAM_WCOUNT;
642 max_offset = MAC_ADDR_MAX_CAM_WCOUNT;
643 break;
644 case 4: /* FC MAC addresses */
645 max_index = MAC_ADDR_MAX_FC_MAC_ENTRIES;
646 max_offset = MAC_ADDR_MAX_FC_MAC_WCOUNT;
647 break;
648 case 5: /* Mgmt MAC addresses */
649 max_index = MAC_ADDR_MAX_MGMT_MAC_ENTRIES;
650 max_offset = MAC_ADDR_MAX_MGMT_MAC_WCOUNT;
651 break;
652 case 6: /* Mgmt VLAN addresses */
653 max_index = MAC_ADDR_MAX_MGMT_VLAN_ENTRIES;
654 max_offset = MAC_ADDR_MAX_MGMT_VLAN_WCOUNT;
655 break;
656 case 7: /* Mgmt IPv4 address */
657 max_index = MAC_ADDR_MAX_MGMT_V4_ENTRIES;
658 max_offset = MAC_ADDR_MAX_MGMT_V4_WCOUNT;
659 break;
660 case 8: /* Mgmt IPv6 address */
661 max_index = MAC_ADDR_MAX_MGMT_V6_ENTRIES;
662 max_offset = MAC_ADDR_MAX_MGMT_V6_WCOUNT;
663 break;
664 case 9: /* Mgmt TCP/UDP Dest port */
665 max_index = MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES;
666 max_offset = MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT;
667 break;
668 default:
669 printk(KERN_ERR"Bad type!!! 0x%08x\n", type);
670 max_index = 0;
671 max_offset = 0;
672 break;
673 }
674 for (index = 0; index < max_index; index++) {
675 for (offset = 0; offset < max_offset; offset++) {
676 val = initial_val
677 | (type << MAC_ADDR_TYPE_SHIFT)
678 | (index << MAC_ADDR_IDX_SHIFT)
679 | (offset);
680 ql_write32(qdev, MAC_ADDR_IDX, val);
681 result_index = 0;
682 while ((result_index & MAC_ADDR_MR) == 0) {
683 result_index = ql_read32(qdev,
684 MAC_ADDR_IDX);
685 }
686 result_data = ql_read32(qdev, MAC_ADDR_DATA);
687 *buf = result_index;
688 buf++;
689 *buf = result_data;
690 buf++;
691 }
692 }
693 }
694}
695
696static void ql_get_sem_registers(struct ql_adapter *qdev, u32 *buf)
697{
698 u32 func_num, reg, reg_val;
699 int status;
700
701 for (func_num = 0; func_num < MAX_SEMAPHORE_FUNCTIONS ; func_num++) {
702 reg = MPI_NIC_REG_BLOCK
703 | (func_num << MPI_NIC_FUNCTION_SHIFT)
704 | (SEM / 4);
705 status = ql_read_mpi_reg(qdev, reg, &reg_val);
706 *buf = reg_val;
707 /* if the read failed then dead fill the element. */
708 if (!status)
709 *buf = 0xdeadbeef;
710 buf++;
711 }
712}
713
a61f8026
RM		 714/* Create a coredump segment header */
715static void ql_build_coredump_seg_header(
716 struct mpi_coredump_segment_header *seg_hdr,
717 u32 seg_number, u32 seg_size, u8 *desc)
718{
719 memset(seg_hdr, 0, sizeof(struct mpi_coredump_segment_header));
720 seg_hdr->cookie = MPI_COREDUMP_COOKIE;
721 seg_hdr->segNum = seg_number;
722 seg_hdr->segSize = seg_size;
723 memcpy(seg_hdr->description, desc, (sizeof(seg_hdr->description)) - 1);
724}
725
8aae2600
RM		 726/*
727 * This function should be called when a coredump / probedump
728 * is to be extracted from the HBA. It is assumed there is a
729 * qdev structure that contains the base address of the register
730 * space for this function as well as a coredump structure that
731 * will contain the dump.
732 */
733int ql_core_dump(struct ql_adapter *qdev, struct ql_mpi_coredump *mpi_coredump)
734{
735 int status;
736 int i;
737
738 if (!mpi_coredump) {
ae9540f7 739 netif_err(qdev, drv, qdev->ndev, "No memory available.\n");
8aae2600
RM		 740 return -ENOMEM;
741 }
742
743 /* Try to get the spinlock, but dont worry if
744 * it isn't available. If the firmware died it
745 * might be holding the sem.
746 */
747 ql_sem_spinlock(qdev, SEM_PROC_REG_MASK);
748
749 status = ql_pause_mpi_risc(qdev);
750 if (status) {
ae9540f7
JP		 751 netif_err(qdev, drv, qdev->ndev,
752 "Failed RISC pause. Status = 0x%.08x\n", status);
8aae2600
RM		 753 goto err;
754 }
755
756 /* Insert the global header */
757 memset(&(mpi_coredump->mpi_global_header), 0,
758 sizeof(struct mpi_coredump_global_header));
759 mpi_coredump->mpi_global_header.cookie = MPI_COREDUMP_COOKIE;
760 mpi_coredump->mpi_global_header.headerSize =
761 sizeof(struct mpi_coredump_global_header);
762 mpi_coredump->mpi_global_header.imageSize =
763 sizeof(struct ql_mpi_coredump);
764 memcpy(mpi_coredump->mpi_global_header.idString, "MPI Coredump",
765 sizeof(mpi_coredump->mpi_global_header.idString));
766
767 /* Get generic NIC reg dump */
768 ql_build_coredump_seg_header(&mpi_coredump->nic_regs_seg_hdr,
769 NIC1_CONTROL_SEG_NUM,
770 sizeof(struct mpi_coredump_segment_header) +
771 sizeof(mpi_coredump->nic_regs), "NIC1 Registers");
772
24bb55b4
RM		 773 ql_build_coredump_seg_header(&mpi_coredump->nic2_regs_seg_hdr,
774 NIC2_CONTROL_SEG_NUM,
775 sizeof(struct mpi_coredump_segment_header) +
776 sizeof(mpi_coredump->nic2_regs), "NIC2 Registers");
777
a2f98232
RM		 778 /* Get XGMac registers. (Segment 18, Rev C. step 21) */
779 ql_build_coredump_seg_header(&mpi_coredump->xgmac1_seg_hdr,
780 NIC1_XGMAC_SEG_NUM,
781 sizeof(struct mpi_coredump_segment_header) +
782 sizeof(mpi_coredump->xgmac1), "NIC1 XGMac Registers");
783
784 ql_build_coredump_seg_header(&mpi_coredump->xgmac2_seg_hdr,
785 NIC2_XGMAC_SEG_NUM,
786 sizeof(struct mpi_coredump_segment_header) +
787 sizeof(mpi_coredump->xgmac2), "NIC2 XGMac Registers");
788
8aae2600
RM		 789 if (qdev->func & 1) {
790 /* Odd means our function is NIC 2 */
791 for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++)
792 mpi_coredump->nic2_regs[i] =
793 ql_read32(qdev, i * sizeof(u32));
24bb55b4
RM		 794
795 for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++)
796 mpi_coredump->nic_regs[i] =
797 ql_read_other_func_reg(qdev, (i * sizeof(u32)) / 4);
a2f98232
RM		 798
799 ql_get_xgmac_regs(qdev, &mpi_coredump->xgmac2[0], 0);
800 ql_get_xgmac_regs(qdev, &mpi_coredump->xgmac1[0], 1);
8aae2600
RM		 801 } else {
802 /* Even means our function is NIC 1 */
803 for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++)
804 mpi_coredump->nic_regs[i] =
805 ql_read32(qdev, i * sizeof(u32));
24bb55b4
RM		 806 for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++)
807 mpi_coredump->nic2_regs[i] =
808 ql_read_other_func_reg(qdev, (i * sizeof(u32)) / 4);
a2f98232
RM		 809
810 ql_get_xgmac_regs(qdev, &mpi_coredump->xgmac1[0], 0);
811 ql_get_xgmac_regs(qdev, &mpi_coredump->xgmac2[0], 1);
8aae2600
RM		 812 }
813
a48c86fd
RM		 814 /* Rev C. Step 20a */
815 ql_build_coredump_seg_header(&mpi_coredump->xaui_an_hdr,
816 XAUI_AN_SEG_NUM,
817 sizeof(struct mpi_coredump_segment_header) +
818 sizeof(mpi_coredump->serdes_xaui_an),
819 "XAUI AN Registers");
820
821 /* Rev C. Step 20b */
822 ql_build_coredump_seg_header(&mpi_coredump->xaui_hss_pcs_hdr,
823 XAUI_HSS_PCS_SEG_NUM,
824 sizeof(struct mpi_coredump_segment_header) +
825 sizeof(mpi_coredump->serdes_xaui_hss_pcs),
826 "XAUI HSS PCS Registers");
827
828 ql_build_coredump_seg_header(&mpi_coredump->xfi_an_hdr, XFI_AN_SEG_NUM,
829 sizeof(struct mpi_coredump_segment_header) +
830 sizeof(mpi_coredump->serdes_xfi_an),
831 "XFI AN Registers");
832
833 ql_build_coredump_seg_header(&mpi_coredump->xfi_train_hdr,
834 XFI_TRAIN_SEG_NUM,
835 sizeof(struct mpi_coredump_segment_header) +
836 sizeof(mpi_coredump->serdes_xfi_train),
837 "XFI TRAIN Registers");
838
839 ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_pcs_hdr,
840 XFI_HSS_PCS_SEG_NUM,
841 sizeof(struct mpi_coredump_segment_header) +
842 sizeof(mpi_coredump->serdes_xfi_hss_pcs),
843 "XFI HSS PCS Registers");
844
845 ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_tx_hdr,
846 XFI_HSS_TX_SEG_NUM,
847 sizeof(struct mpi_coredump_segment_header) +
848 sizeof(mpi_coredump->serdes_xfi_hss_tx),
849 "XFI HSS TX Registers");
850
851 ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_rx_hdr,
852 XFI_HSS_RX_SEG_NUM,
853 sizeof(struct mpi_coredump_segment_header) +
854 sizeof(mpi_coredump->serdes_xfi_hss_rx),
855 "XFI HSS RX Registers");
856
857 ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_pll_hdr,
858 XFI_HSS_PLL_SEG_NUM,
859 sizeof(struct mpi_coredump_segment_header) +
860 sizeof(mpi_coredump->serdes_xfi_hss_pll),
861 "XFI HSS PLL Registers");
862
863 ql_build_coredump_seg_header(&mpi_coredump->xaui2_an_hdr,
864 XAUI2_AN_SEG_NUM,
865 sizeof(struct mpi_coredump_segment_header) +
866 sizeof(mpi_coredump->serdes2_xaui_an),
867 "XAUI2 AN Registers");
868
869 ql_build_coredump_seg_header(&mpi_coredump->xaui2_hss_pcs_hdr,
870 XAUI2_HSS_PCS_SEG_NUM,
871 sizeof(struct mpi_coredump_segment_header) +
872 sizeof(mpi_coredump->serdes2_xaui_hss_pcs),
873 "XAUI2 HSS PCS Registers");
874
875 ql_build_coredump_seg_header(&mpi_coredump->xfi2_an_hdr,
876 XFI2_AN_SEG_NUM,
877 sizeof(struct mpi_coredump_segment_header) +
878 sizeof(mpi_coredump->serdes2_xfi_an),
879 "XFI2 AN Registers");
880
881 ql_build_coredump_seg_header(&mpi_coredump->xfi2_train_hdr,
882 XFI2_TRAIN_SEG_NUM,
883 sizeof(struct mpi_coredump_segment_header) +
884 sizeof(mpi_coredump->serdes2_xfi_train),
885 "XFI2 TRAIN Registers");
886
887 ql_build_coredump_seg_header(&mpi_coredump->xfi2_hss_pcs_hdr,
888 XFI2_HSS_PCS_SEG_NUM,
889 sizeof(struct mpi_coredump_segment_header) +
890 sizeof(mpi_coredump->serdes2_xfi_hss_pcs),
891 "XFI2 HSS PCS Registers");
892
893 ql_build_coredump_seg_header(&mpi_coredump->xfi2_hss_tx_hdr,
894 XFI2_HSS_TX_SEG_NUM,
895 sizeof(struct mpi_coredump_segment_header) +
896 sizeof(mpi_coredump->serdes2_xfi_hss_tx),
897 "XFI2 HSS TX Registers");
898
899 ql_build_coredump_seg_header(&mpi_coredump->xfi2_hss_rx_hdr,
900 XFI2_HSS_RX_SEG_NUM,
901 sizeof(struct mpi_coredump_segment_header) +
902 sizeof(mpi_coredump->serdes2_xfi_hss_rx),
903 "XFI2 HSS RX Registers");
904
905 ql_build_coredump_seg_header(&mpi_coredump->xfi2_hss_pll_hdr,
906 XFI2_HSS_PLL_SEG_NUM,
907 sizeof(struct mpi_coredump_segment_header) +
908 sizeof(mpi_coredump->serdes2_xfi_hss_pll),
909 "XFI2 HSS PLL Registers");
910
911 status = ql_get_serdes_regs(qdev, mpi_coredump);
912 if (status) {
ae9540f7
JP		 913 netif_err(qdev, drv, qdev->ndev,
914 "Failed Dump of Serdes Registers. Status = 0x%.08x\n",
915 status);
a48c86fd
RM		 916 goto err;
917 }
918
8aae2600
RM		 919 ql_build_coredump_seg_header(&mpi_coredump->core_regs_seg_hdr,
920 CORE_SEG_NUM,
921 sizeof(mpi_coredump->core_regs_seg_hdr) +
922 sizeof(mpi_coredump->mpi_core_regs) +
923 sizeof(mpi_coredump->mpi_core_sh_regs),
924 "Core Registers");
925
926 /* Get the MPI Core Registers */
927 status = ql_get_mpi_regs(qdev, &mpi_coredump->mpi_core_regs[0],
928 MPI_CORE_REGS_ADDR, MPI_CORE_REGS_CNT);
929 if (status)
930 goto err;
931 /* Get the 16 MPI shadow registers */
932 status = ql_get_mpi_shadow_regs(qdev,
933 &mpi_coredump->mpi_core_sh_regs[0]);
934 if (status)
935 goto err;
936
937 /* Get the Test Logic Registers */
938 ql_build_coredump_seg_header(&mpi_coredump->test_logic_regs_seg_hdr,
939 TEST_LOGIC_SEG_NUM,
940 sizeof(struct mpi_coredump_segment_header)
941 + sizeof(mpi_coredump->test_logic_regs),
942 "Test Logic Regs");
943 status = ql_get_mpi_regs(qdev, &mpi_coredump->test_logic_regs[0],
944 TEST_REGS_ADDR, TEST_REGS_CNT);
945 if (status)
946 goto err;
947
948 /* Get the RMII Registers */
949 ql_build_coredump_seg_header(&mpi_coredump->rmii_regs_seg_hdr,
950 RMII_SEG_NUM,
951 sizeof(struct mpi_coredump_segment_header)
952 + sizeof(mpi_coredump->rmii_regs),
953 "RMII Registers");
954 status = ql_get_mpi_regs(qdev, &mpi_coredump->rmii_regs[0],
955 RMII_REGS_ADDR, RMII_REGS_CNT);
956 if (status)
957 goto err;
958
959 /* Get the FCMAC1 Registers */
960 ql_build_coredump_seg_header(&mpi_coredump->fcmac1_regs_seg_hdr,
961 FCMAC1_SEG_NUM,
962 sizeof(struct mpi_coredump_segment_header)
963 + sizeof(mpi_coredump->fcmac1_regs),
964 "FCMAC1 Registers");
965 status = ql_get_mpi_regs(qdev, &mpi_coredump->fcmac1_regs[0],
966 FCMAC1_REGS_ADDR, FCMAC_REGS_CNT);
967 if (status)
968 goto err;
969
970 /* Get the FCMAC2 Registers */
971
972 ql_build_coredump_seg_header(&mpi_coredump->fcmac2_regs_seg_hdr,
973 FCMAC2_SEG_NUM,
974 sizeof(struct mpi_coredump_segment_header)
975 + sizeof(mpi_coredump->fcmac2_regs),
976 "FCMAC2 Registers");
977
978 status = ql_get_mpi_regs(qdev, &mpi_coredump->fcmac2_regs[0],
979 FCMAC2_REGS_ADDR, FCMAC_REGS_CNT);
980 if (status)
981 goto err;
982
983 /* Get the FC1 MBX Registers */
984 ql_build_coredump_seg_header(&mpi_coredump->fc1_mbx_regs_seg_hdr,
985 FC1_MBOX_SEG_NUM,
986 sizeof(struct mpi_coredump_segment_header)
987 + sizeof(mpi_coredump->fc1_mbx_regs),
988 "FC1 MBox Regs");
989 status = ql_get_mpi_regs(qdev, &mpi_coredump->fc1_mbx_regs[0],
990 FC1_MBX_REGS_ADDR, FC_MBX_REGS_CNT);
991 if (status)
992 goto err;
993
994 /* Get the IDE Registers */
995 ql_build_coredump_seg_header(&mpi_coredump->ide_regs_seg_hdr,
996 IDE_SEG_NUM,
997 sizeof(struct mpi_coredump_segment_header)
998 + sizeof(mpi_coredump->ide_regs),
999 "IDE Registers");
1000 status = ql_get_mpi_regs(qdev, &mpi_coredump->ide_regs[0],
1001 IDE_REGS_ADDR, IDE_REGS_CNT);
1002 if (status)
1003 goto err;
1004
1005 /* Get the NIC1 MBX Registers */
1006 ql_build_coredump_seg_header(&mpi_coredump->nic1_mbx_regs_seg_hdr,
1007 NIC1_MBOX_SEG_NUM,
1008 sizeof(struct mpi_coredump_segment_header)
1009 + sizeof(mpi_coredump->nic1_mbx_regs),
1010 "NIC1 MBox Regs");
1011 status = ql_get_mpi_regs(qdev, &mpi_coredump->nic1_mbx_regs[0],
1012 NIC1_MBX_REGS_ADDR, NIC_MBX_REGS_CNT);
1013 if (status)
1014 goto err;
1015
1016 /* Get the SMBus Registers */
1017 ql_build_coredump_seg_header(&mpi_coredump->smbus_regs_seg_hdr,
1018 SMBUS_SEG_NUM,
1019 sizeof(struct mpi_coredump_segment_header)
1020 + sizeof(mpi_coredump->smbus_regs),
1021 "SMBus Registers");
1022 status = ql_get_mpi_regs(qdev, &mpi_coredump->smbus_regs[0],
1023 SMBUS_REGS_ADDR, SMBUS_REGS_CNT);
1024 if (status)
1025 goto err;
1026
1027 /* Get the FC2 MBX Registers */
1028 ql_build_coredump_seg_header(&mpi_coredump->fc2_mbx_regs_seg_hdr,
1029 FC2_MBOX_SEG_NUM,
1030 sizeof(struct mpi_coredump_segment_header)
1031 + sizeof(mpi_coredump->fc2_mbx_regs),
1032 "FC2 MBox Regs");
1033 status = ql_get_mpi_regs(qdev, &mpi_coredump->fc2_mbx_regs[0],
1034 FC2_MBX_REGS_ADDR, FC_MBX_REGS_CNT);
1035 if (status)
1036 goto err;
1037
1038 /* Get the NIC2 MBX Registers */
1039 ql_build_coredump_seg_header(&mpi_coredump->nic2_mbx_regs_seg_hdr,
1040 NIC2_MBOX_SEG_NUM,
1041 sizeof(struct mpi_coredump_segment_header)
1042 + sizeof(mpi_coredump->nic2_mbx_regs),
1043 "NIC2 MBox Regs");
1044 status = ql_get_mpi_regs(qdev, &mpi_coredump->nic2_mbx_regs[0],
1045 NIC2_MBX_REGS_ADDR, NIC_MBX_REGS_CNT);
1046 if (status)
1047 goto err;
1048
1049 /* Get the I2C Registers */
1050 ql_build_coredump_seg_header(&mpi_coredump->i2c_regs_seg_hdr,
1051 I2C_SEG_NUM,
1052 sizeof(struct mpi_coredump_segment_header)
1053 + sizeof(mpi_coredump->i2c_regs),
1054 "I2C Registers");
1055 status = ql_get_mpi_regs(qdev, &mpi_coredump->i2c_regs[0],
1056 I2C_REGS_ADDR, I2C_REGS_CNT);
1057 if (status)
1058 goto err;
1059
1060 /* Get the MEMC Registers */
1061 ql_build_coredump_seg_header(&mpi_coredump->memc_regs_seg_hdr,
1062 MEMC_SEG_NUM,
1063 sizeof(struct mpi_coredump_segment_header)
1064 + sizeof(mpi_coredump->memc_regs),
1065 "MEMC Registers");
1066 status = ql_get_mpi_regs(qdev, &mpi_coredump->memc_regs[0],
1067 MEMC_REGS_ADDR, MEMC_REGS_CNT);
1068 if (status)
1069 goto err;
1070
1071 /* Get the PBus Registers */
1072 ql_build_coredump_seg_header(&mpi_coredump->pbus_regs_seg_hdr,
1073 PBUS_SEG_NUM,
1074 sizeof(struct mpi_coredump_segment_header)
1075 + sizeof(mpi_coredump->pbus_regs),
1076 "PBUS Registers");
1077 status = ql_get_mpi_regs(qdev, &mpi_coredump->pbus_regs[0],
1078 PBUS_REGS_ADDR, PBUS_REGS_CNT);
1079 if (status)
1080 goto err;
1081
1082 /* Get the MDE Registers */
1083 ql_build_coredump_seg_header(&mpi_coredump->mde_regs_seg_hdr,
1084 MDE_SEG_NUM,
1085 sizeof(struct mpi_coredump_segment_header)
1086 + sizeof(mpi_coredump->mde_regs),
1087 "MDE Registers");
1088 status = ql_get_mpi_regs(qdev, &mpi_coredump->mde_regs[0],
1089 MDE_REGS_ADDR, MDE_REGS_CNT);
1090 if (status)
1091 goto err;
1092
1093 ql_build_coredump_seg_header(&mpi_coredump->misc_nic_seg_hdr,
1094 MISC_NIC_INFO_SEG_NUM,
1095 sizeof(struct mpi_coredump_segment_header)
1096 + sizeof(mpi_coredump->misc_nic_info),
1097 "MISC NIC INFO");
1098 mpi_coredump->misc_nic_info.rx_ring_count = qdev->rx_ring_count;
1099 mpi_coredump->misc_nic_info.tx_ring_count = qdev->tx_ring_count;
1100 mpi_coredump->misc_nic_info.intr_count = qdev->intr_count;
1101 mpi_coredump->misc_nic_info.function = qdev->func;
1102
1103 /* Segment 31 */
1104 /* Get indexed register values. */
1105 ql_build_coredump_seg_header(&mpi_coredump->intr_states_seg_hdr,
1106 INTR_STATES_SEG_NUM,
1107 sizeof(struct mpi_coredump_segment_header)
1108 + sizeof(mpi_coredump->intr_states),
1109 "INTR States");
1110 ql_get_intr_states(qdev, &mpi_coredump->intr_states[0]);
1111
1112 ql_build_coredump_seg_header(&mpi_coredump->cam_entries_seg_hdr,
1113 CAM_ENTRIES_SEG_NUM,
1114 sizeof(struct mpi_coredump_segment_header)
1115 + sizeof(mpi_coredump->cam_entries),
1116 "CAM Entries");
1117 status = ql_get_cam_entries(qdev, &mpi_coredump->cam_entries[0]);
1118 if (status)
1119 goto err;
1120
1121 ql_build_coredump_seg_header(&mpi_coredump->nic_routing_words_seg_hdr,
1122 ROUTING_WORDS_SEG_NUM,
1123 sizeof(struct mpi_coredump_segment_header)
1124 + sizeof(mpi_coredump->nic_routing_words),
1125 "Routing Words");
1126 status = ql_get_routing_entries(qdev,
1127 &mpi_coredump->nic_routing_words[0]);
1128 if (status)
1129 goto err;
1130
1131 /* Segment 34 (Rev C. step 23) */
1132 ql_build_coredump_seg_header(&mpi_coredump->ets_seg_hdr,
1133 ETS_SEG_NUM,
1134 sizeof(struct mpi_coredump_segment_header)
1135 + sizeof(mpi_coredump->ets),
1136 "ETS Registers");
1137 status = ql_get_ets_regs(qdev, &mpi_coredump->ets[0]);
1138 if (status)
1139 goto err;
1140
c89ec8b9
RM		 1141 ql_build_coredump_seg_header(&mpi_coredump->probe_dump_seg_hdr,
1142 PROBE_DUMP_SEG_NUM,
1143 sizeof(struct mpi_coredump_segment_header)
1144 + sizeof(mpi_coredump->probe_dump),
1145 "Probe Dump");
1146 ql_get_probe_dump(qdev, &mpi_coredump->probe_dump[0]);
1147
8aae2600
RM		 1148 ql_build_coredump_seg_header(&mpi_coredump->routing_reg_seg_hdr,
1149 ROUTING_INDEX_SEG_NUM,
1150 sizeof(struct mpi_coredump_segment_header)
1151 + sizeof(mpi_coredump->routing_regs),
1152 "Routing Regs");
1153 status = ql_get_routing_index_registers(qdev,
1154 &mpi_coredump->routing_regs[0]);
1155 if (status)
1156 goto err;
1157
1158 ql_build_coredump_seg_header(&mpi_coredump->mac_prot_reg_seg_hdr,
1159 MAC_PROTOCOL_SEG_NUM,
1160 sizeof(struct mpi_coredump_segment_header)
1161 + sizeof(mpi_coredump->mac_prot_regs),
1162 "MAC Prot Regs");
1163 ql_get_mac_protocol_registers(qdev, &mpi_coredump->mac_prot_regs[0]);
1164
1165 /* Get the semaphore registers for all 5 functions */
1166 ql_build_coredump_seg_header(&mpi_coredump->sem_regs_seg_hdr,
1167 SEM_REGS_SEG_NUM,
1168 sizeof(struct mpi_coredump_segment_header) +
1169 sizeof(mpi_coredump->sem_regs), "Sem Registers");
1170
1171 ql_get_sem_registers(qdev, &mpi_coredump->sem_regs[0]);
1172
1173 /* Prevent the mpi restarting while we dump the memory.*/
1174 ql_write_mpi_reg(qdev, MPI_TEST_FUNC_RST_STS, MPI_TEST_FUNC_RST_FRC);
1175
1176 /* clear the pause */
1177 status = ql_unpause_mpi_risc(qdev);
1178 if (status) {
ae9540f7
JP		 1179 netif_err(qdev, drv, qdev->ndev,
1180 "Failed RISC unpause. Status = 0x%.08x\n", status);
8aae2600
RM		 1181 goto err;
1182 }
2c1f73c3
RM		 1183
1184 /* Reset the RISC so we can dump RAM */
1185 status = ql_hard_reset_mpi_risc(qdev);
1186 if (status) {
ae9540f7
JP		 1187 netif_err(qdev, drv, qdev->ndev,
1188 "Failed RISC reset. Status = 0x%.08x\n", status);
2c1f73c3
RM		 1189 goto err;
1190 }
1191
1192 ql_build_coredump_seg_header(&mpi_coredump->code_ram_seg_hdr,
1193 WCS_RAM_SEG_NUM,
1194 sizeof(struct mpi_coredump_segment_header)
1195 + sizeof(mpi_coredump->code_ram),
1196 "WCS RAM");
1197 status = ql_dump_risc_ram_area(qdev, &mpi_coredump->code_ram[0],
1198 CODE_RAM_ADDR, CODE_RAM_CNT);
1199 if (status) {
ae9540f7
JP		 1200 netif_err(qdev, drv, qdev->ndev,
1201 "Failed Dump of CODE RAM. Status = 0x%.08x\n",
1202 status);
2c1f73c3
RM		 1203 goto err;
1204 }
1205
1206 /* Insert the segment header */
1207 ql_build_coredump_seg_header(&mpi_coredump->memc_ram_seg_hdr,
1208 MEMC_RAM_SEG_NUM,
1209 sizeof(struct mpi_coredump_segment_header)
1210 + sizeof(mpi_coredump->memc_ram),
1211 "MEMC RAM");
1212 status = ql_dump_risc_ram_area(qdev, &mpi_coredump->memc_ram[0],
1213 MEMC_RAM_ADDR, MEMC_RAM_CNT);
1214 if (status) {
ae9540f7
JP		 1215 netif_err(qdev, drv, qdev->ndev,
1216 "Failed Dump of MEMC RAM. Status = 0x%.08x\n",
1217 status);
2c1f73c3
RM		 1218 goto err;
1219 }
8aae2600
RM		 1220err:
1221 ql_sem_unlock(qdev, SEM_PROC_REG_MASK); /* does flush too */
1222 return status;
1223
1224}
1225
d5c1da56
RM		 1226static void ql_get_core_dump(struct ql_adapter *qdev)
1227{
1228 if (!ql_own_firmware(qdev)) {
ae9540f7 1229 netif_err(qdev, drv, qdev->ndev, "Don't own firmware!\n");
d5c1da56
RM		 1230 return;
1231 }
1232
1233 if (!netif_running(qdev->ndev)) {
ae9540f7
JP		 1234 netif_err(qdev, ifup, qdev->ndev,
1235 "Force Coredump can only be done from interface that is up.\n");
d5c1da56
RM		 1236 return;
1237 }
1238
1239 if (ql_mb_sys_err(qdev)) {
ae9540f7
JP		 1240 netif_err(qdev, ifup, qdev->ndev,
1241 "Fail force coredump with ql_mb_sys_err().\n");
d5c1da56
RM		 1242 return;
1243 }
1244}
1245
a61f8026
RM		 1246void ql_gen_reg_dump(struct ql_adapter *qdev,
1247 struct ql_reg_dump *mpi_coredump)
1248{
1249 int i, status;
1250
1251
1252 memset(&(mpi_coredump->mpi_global_header), 0,
1253 sizeof(struct mpi_coredump_global_header));
1254 mpi_coredump->mpi_global_header.cookie = MPI_COREDUMP_COOKIE;
1255 mpi_coredump->mpi_global_header.headerSize =
1256 sizeof(struct mpi_coredump_global_header);
1257 mpi_coredump->mpi_global_header.imageSize =
1258 sizeof(struct ql_reg_dump);
1259 memcpy(mpi_coredump->mpi_global_header.idString, "MPI Coredump",
1260 sizeof(mpi_coredump->mpi_global_header.idString));
1261
1262
1263 /* segment 16 */
1264 ql_build_coredump_seg_header(&mpi_coredump->misc_nic_seg_hdr,
1265 MISC_NIC_INFO_SEG_NUM,
1266 sizeof(struct mpi_coredump_segment_header)
1267 + sizeof(mpi_coredump->misc_nic_info),
1268 "MISC NIC INFO");
1269 mpi_coredump->misc_nic_info.rx_ring_count = qdev->rx_ring_count;
1270 mpi_coredump->misc_nic_info.tx_ring_count = qdev->tx_ring_count;
1271 mpi_coredump->misc_nic_info.intr_count = qdev->intr_count;
1272 mpi_coredump->misc_nic_info.function = qdev->func;
1273
1274 /* Segment 16, Rev C. Step 18 */
1275 ql_build_coredump_seg_header(&mpi_coredump->nic_regs_seg_hdr,
1276 NIC1_CONTROL_SEG_NUM,
1277 sizeof(struct mpi_coredump_segment_header)
1278 + sizeof(mpi_coredump->nic_regs),
1279 "NIC Registers");
1280 /* Get generic reg dump */
1281 for (i = 0; i < 64; i++)
1282 mpi_coredump->nic_regs[i] = ql_read32(qdev, i * sizeof(u32));
1283
1284 /* Segment 31 */
1285 /* Get indexed register values. */
1286 ql_build_coredump_seg_header(&mpi_coredump->intr_states_seg_hdr,
1287 INTR_STATES_SEG_NUM,
1288 sizeof(struct mpi_coredump_segment_header)
1289 + sizeof(mpi_coredump->intr_states),
1290 "INTR States");
1291 ql_get_intr_states(qdev, &mpi_coredump->intr_states[0]);
1292
1293 ql_build_coredump_seg_header(&mpi_coredump->cam_entries_seg_hdr,
1294 CAM_ENTRIES_SEG_NUM,
1295 sizeof(struct mpi_coredump_segment_header)
1296 + sizeof(mpi_coredump->cam_entries),
1297 "CAM Entries");
1298 status = ql_get_cam_entries(qdev, &mpi_coredump->cam_entries[0]);
1299 if (status)
1300 return;
1301
1302 ql_build_coredump_seg_header(&mpi_coredump->nic_routing_words_seg_hdr,
1303 ROUTING_WORDS_SEG_NUM,
1304 sizeof(struct mpi_coredump_segment_header)
1305 + sizeof(mpi_coredump->nic_routing_words),
1306 "Routing Words");
1307 status = ql_get_routing_entries(qdev,
1308 &mpi_coredump->nic_routing_words[0]);
1309 if (status)
1310 return;
1311
1312 /* Segment 34 (Rev C. step 23) */
1313 ql_build_coredump_seg_header(&mpi_coredump->ets_seg_hdr,
1314 ETS_SEG_NUM,
1315 sizeof(struct mpi_coredump_segment_header)
1316 + sizeof(mpi_coredump->ets),
1317 "ETS Registers");
1318 status = ql_get_ets_regs(qdev, &mpi_coredump->ets[0]);
1319 if (status)
1320 return;
d5c1da56
RM		 1321
1322 if (test_bit(QL_FRC_COREDUMP, &qdev->flags))
1323 ql_get_core_dump(qdev);
a61f8026
RM		 1324}
1325
8aae2600
RM		 1326/* Coredump to messages log file using separate worker thread */
1327void ql_mpi_core_to_log(struct work_struct *work)
1328{
1329 struct ql_adapter *qdev =
1330 container_of(work, struct ql_adapter, mpi_core_to_log.work);
1331 u32 *tmp, count;
1332 int i;
1333
1334 count = sizeof(struct ql_mpi_coredump) / sizeof(u32);
1335 tmp = (u32 *)qdev->mpi_coredump;
ae9540f7
JP		 1336 netif_printk(qdev, drv, KERN_DEBUG, qdev->ndev,
1337 "Core is dumping to log file!\n");
8aae2600
RM		 1338
1339 for (i = 0; i < count; i += 8) {
1340 printk(KERN_ERR "%.08x: %.08x %.08x %.08x %.08x %.08x "
2381a55c 1341 "%.08x %.08x %.08x\n", i,
8aae2600
RM		 1342 tmp[i + 0],
1343 tmp[i + 1],
1344 tmp[i + 2],
1345 tmp[i + 3],
1346 tmp[i + 4],
1347 tmp[i + 5],
1348 tmp[i + 6],
1349 tmp[i + 7]);
1350 msleep(5);
1351 }
1352}
1353
c4e84bde
RM		 1354#ifdef QL_REG_DUMP
1355static void ql_dump_intr_states(struct ql_adapter *qdev)
1356{
1357 int i;
1358 u32 value;
1359 for (i = 0; i < qdev->intr_count; i++) {
1360 ql_write32(qdev, INTR_EN, qdev->intr_context[i].intr_read_mask);
1361 value = ql_read32(qdev, INTR_EN);
1362 printk(KERN_ERR PFX
1363 "%s: Interrupt %d is %s.\n",
1364 qdev->ndev->name, i,
1365 (value & INTR_EN_EN ? "enabled" : "disabled"));
1366 }
1367}
1368
1369void ql_dump_xgmac_control_regs(struct ql_adapter *qdev)
1370{
1371 u32 data;
1372 if (ql_sem_spinlock(qdev, qdev->xg_sem_mask)) {
1373 printk(KERN_ERR "%s: Couldn't get xgmac sem.\n", __func__);
1374 return;
1375 }
1376 ql_read_xgmac_reg(qdev, PAUSE_SRC_LO, &data);
1377 printk(KERN_ERR PFX "%s: PAUSE_SRC_LO = 0x%.08x.\n", qdev->ndev->name,
1378 data);
1379 ql_read_xgmac_reg(qdev, PAUSE_SRC_HI, &data);
1380 printk(KERN_ERR PFX "%s: PAUSE_SRC_HI = 0x%.08x.\n", qdev->ndev->name,
1381 data);
1382 ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
1383 printk(KERN_ERR PFX "%s: GLOBAL_CFG = 0x%.08x.\n", qdev->ndev->name,
1384 data);
1385 ql_read_xgmac_reg(qdev, TX_CFG, &data);
1386 printk(KERN_ERR PFX "%s: TX_CFG = 0x%.08x.\n", qdev->ndev->name, data);
1387 ql_read_xgmac_reg(qdev, RX_CFG, &data);
1388 printk(KERN_ERR PFX "%s: RX_CFG = 0x%.08x.\n", qdev->ndev->name, data);
1389 ql_read_xgmac_reg(qdev, FLOW_CTL, &data);
1390 printk(KERN_ERR PFX "%s: FLOW_CTL = 0x%.08x.\n", qdev->ndev->name,
1391 data);
1392 ql_read_xgmac_reg(qdev, PAUSE_OPCODE, &data);
1393 printk(KERN_ERR PFX "%s: PAUSE_OPCODE = 0x%.08x.\n", qdev->ndev->name,
1394 data);
1395 ql_read_xgmac_reg(qdev, PAUSE_TIMER, &data);
1396 printk(KERN_ERR PFX "%s: PAUSE_TIMER = 0x%.08x.\n", qdev->ndev->name,
1397 data);
1398 ql_read_xgmac_reg(qdev, PAUSE_FRM_DEST_LO, &data);
1399 printk(KERN_ERR PFX "%s: PAUSE_FRM_DEST_LO = 0x%.08x.\n",
1400 qdev->ndev->name, data);
1401 ql_read_xgmac_reg(qdev, PAUSE_FRM_DEST_HI, &data);
1402 printk(KERN_ERR PFX "%s: PAUSE_FRM_DEST_HI = 0x%.08x.\n",
1403 qdev->ndev->name, data);
1404 ql_read_xgmac_reg(qdev, MAC_TX_PARAMS, &data);
1405 printk(KERN_ERR PFX "%s: MAC_TX_PARAMS = 0x%.08x.\n", qdev->ndev->name,
1406 data);
1407 ql_read_xgmac_reg(qdev, MAC_RX_PARAMS, &data);
1408 printk(KERN_ERR PFX "%s: MAC_RX_PARAMS = 0x%.08x.\n", qdev->ndev->name,
1409 data);
1410 ql_read_xgmac_reg(qdev, MAC_SYS_INT, &data);
1411 printk(KERN_ERR PFX "%s: MAC_SYS_INT = 0x%.08x.\n", qdev->ndev->name,
1412 data);
1413 ql_read_xgmac_reg(qdev, MAC_SYS_INT_MASK, &data);
1414 printk(KERN_ERR PFX "%s: MAC_SYS_INT_MASK = 0x%.08x.\n",
1415 qdev->ndev->name, data);
1416 ql_read_xgmac_reg(qdev, MAC_MGMT_INT, &data);
1417 printk(KERN_ERR PFX "%s: MAC_MGMT_INT = 0x%.08x.\n", qdev->ndev->name,
1418 data);
1419 ql_read_xgmac_reg(qdev, MAC_MGMT_IN_MASK, &data);
1420 printk(KERN_ERR PFX "%s: MAC_MGMT_IN_MASK = 0x%.08x.\n",
1421 qdev->ndev->name, data);
1422 ql_read_xgmac_reg(qdev, EXT_ARB_MODE, &data);
1423 printk(KERN_ERR PFX "%s: EXT_ARB_MODE = 0x%.08x.\n", qdev->ndev->name,
1424 data);
1425 ql_sem_unlock(qdev, qdev->xg_sem_mask);
1426
1427}
1428
1429static void ql_dump_ets_regs(struct ql_adapter *qdev)
1430{
1431}
1432
1433static void ql_dump_cam_entries(struct ql_adapter *qdev)
1434{
1435 int i;
1436 u32 value[3];
cc288f54
RM		 1437
1438 i = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1439 if (i)
1440 return;
c4e84bde
RM		 1441 for (i = 0; i < 4; i++) {
1442 if (ql_get_mac_addr_reg(qdev, MAC_ADDR_TYPE_CAM_MAC, i, value)) {
1443 printk(KERN_ERR PFX
1444 "%s: Failed read of mac index register.\n",
1445 __func__);
1446 return;
1447 } else {
1448 if (value[0])
1449 printk(KERN_ERR PFX
1450 "%s: CAM index %d CAM Lookup Lower = 0x%.08x:%.08x, Output = 0x%.08x.\n",
1451 qdev->ndev->name, i, value[1], value[0],
1452 value[2]);
1453 }
1454 }
1455 for (i = 0; i < 32; i++) {
1456 if (ql_get_mac_addr_reg
1457 (qdev, MAC_ADDR_TYPE_MULTI_MAC, i, value)) {
1458 printk(KERN_ERR PFX
1459 "%s: Failed read of mac index register.\n",
1460 __func__);
1461 return;
1462 } else {
1463 if (value[0])
1464 printk(KERN_ERR PFX
1465 "%s: MCAST index %d CAM Lookup Lower = 0x%.08x:%.08x.\n",
1466 qdev->ndev->name, i, value[1], value[0]);
1467 }
1468 }
cc288f54 1469 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
c4e84bde
RM		 1470}
1471
1472void ql_dump_routing_entries(struct ql_adapter *qdev)
1473{
1474 int i;
1475 u32 value;
cc288f54
RM		 1476 i = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
1477 if (i)
1478 return;
c4e84bde
RM		 1479 for (i = 0; i < 16; i++) {
1480 value = 0;
1481 if (ql_get_routing_reg(qdev, i, &value)) {
1482 printk(KERN_ERR PFX
1483 "%s: Failed read of routing index register.\n",
1484 __func__);
1485 return;
1486 } else {
1487 if (value)
1488 printk(KERN_ERR PFX
1489 "%s: Routing Mask %d = 0x%.08x.\n",
1490 qdev->ndev->name, i, value);
1491 }
1492 }
cc288f54 1493 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
c4e84bde
RM		 1494}
1495
1496void ql_dump_regs(struct ql_adapter *qdev)
1497{
1498 printk(KERN_ERR PFX "reg dump for function #%d.\n", qdev->func);
1499 printk(KERN_ERR PFX "SYS = 0x%x.\n",
1500 ql_read32(qdev, SYS));
1501 printk(KERN_ERR PFX "RST_FO = 0x%x.\n",
1502 ql_read32(qdev, RST_FO));
1503 printk(KERN_ERR PFX "FSC = 0x%x.\n",
1504 ql_read32(qdev, FSC));
1505 printk(KERN_ERR PFX "CSR = 0x%x.\n",
1506 ql_read32(qdev, CSR));
1507 printk(KERN_ERR PFX "ICB_RID = 0x%x.\n",
1508 ql_read32(qdev, ICB_RID));
1509 printk(KERN_ERR PFX "ICB_L = 0x%x.\n",
1510 ql_read32(qdev, ICB_L));
1511 printk(KERN_ERR PFX "ICB_H = 0x%x.\n",
1512 ql_read32(qdev, ICB_H));
1513 printk(KERN_ERR PFX "CFG = 0x%x.\n",
1514 ql_read32(qdev, CFG));
1515 printk(KERN_ERR PFX "BIOS_ADDR = 0x%x.\n",
1516 ql_read32(qdev, BIOS_ADDR));
1517 printk(KERN_ERR PFX "STS = 0x%x.\n",
1518 ql_read32(qdev, STS));
1519 printk(KERN_ERR PFX "INTR_EN = 0x%x.\n",
1520 ql_read32(qdev, INTR_EN));
1521 printk(KERN_ERR PFX "INTR_MASK = 0x%x.\n",
1522 ql_read32(qdev, INTR_MASK));
1523 printk(KERN_ERR PFX "ISR1 = 0x%x.\n",
1524 ql_read32(qdev, ISR1));
1525 printk(KERN_ERR PFX "ISR2 = 0x%x.\n",
1526 ql_read32(qdev, ISR2));
1527 printk(KERN_ERR PFX "ISR3 = 0x%x.\n",
1528 ql_read32(qdev, ISR3));
1529 printk(KERN_ERR PFX "ISR4 = 0x%x.\n",
1530 ql_read32(qdev, ISR4));
1531 printk(KERN_ERR PFX "REV_ID = 0x%x.\n",
1532 ql_read32(qdev, REV_ID));
1533 printk(KERN_ERR PFX "FRC_ECC_ERR = 0x%x.\n",
1534 ql_read32(qdev, FRC_ECC_ERR));
1535 printk(KERN_ERR PFX "ERR_STS = 0x%x.\n",
1536 ql_read32(qdev, ERR_STS));
1537 printk(KERN_ERR PFX "RAM_DBG_ADDR = 0x%x.\n",
1538 ql_read32(qdev, RAM_DBG_ADDR));
1539 printk(KERN_ERR PFX "RAM_DBG_DATA = 0x%x.\n",
1540 ql_read32(qdev, RAM_DBG_DATA));
1541 printk(KERN_ERR PFX "ECC_ERR_CNT = 0x%x.\n",
1542 ql_read32(qdev, ECC_ERR_CNT));
1543 printk(KERN_ERR PFX "SEM = 0x%x.\n",
1544 ql_read32(qdev, SEM));
1545 printk(KERN_ERR PFX "GPIO_1 = 0x%x.\n",
1546 ql_read32(qdev, GPIO_1));
1547 printk(KERN_ERR PFX "GPIO_2 = 0x%x.\n",
1548 ql_read32(qdev, GPIO_2));
1549 printk(KERN_ERR PFX "GPIO_3 = 0x%x.\n",
1550 ql_read32(qdev, GPIO_3));
1551 printk(KERN_ERR PFX "XGMAC_ADDR = 0x%x.\n",
1552 ql_read32(qdev, XGMAC_ADDR));
1553 printk(KERN_ERR PFX "XGMAC_DATA = 0x%x.\n",
1554 ql_read32(qdev, XGMAC_DATA));
1555 printk(KERN_ERR PFX "NIC_ETS = 0x%x.\n",
1556 ql_read32(qdev, NIC_ETS));
1557 printk(KERN_ERR PFX "CNA_ETS = 0x%x.\n",
1558 ql_read32(qdev, CNA_ETS));
1559 printk(KERN_ERR PFX "FLASH_ADDR = 0x%x.\n",
1560 ql_read32(qdev, FLASH_ADDR));
1561 printk(KERN_ERR PFX "FLASH_DATA = 0x%x.\n",
1562 ql_read32(qdev, FLASH_DATA));
1563 printk(KERN_ERR PFX "CQ_STOP = 0x%x.\n",
1564 ql_read32(qdev, CQ_STOP));
1565 printk(KERN_ERR PFX "PAGE_TBL_RID = 0x%x.\n",
1566 ql_read32(qdev, PAGE_TBL_RID));
1567 printk(KERN_ERR PFX "WQ_PAGE_TBL_LO = 0x%x.\n",
1568 ql_read32(qdev, WQ_PAGE_TBL_LO));
1569 printk(KERN_ERR PFX "WQ_PAGE_TBL_HI = 0x%x.\n",
1570 ql_read32(qdev, WQ_PAGE_TBL_HI));
1571 printk(KERN_ERR PFX "CQ_PAGE_TBL_LO = 0x%x.\n",
1572 ql_read32(qdev, CQ_PAGE_TBL_LO));
1573 printk(KERN_ERR PFX "CQ_PAGE_TBL_HI = 0x%x.\n",
1574 ql_read32(qdev, CQ_PAGE_TBL_HI));
1575 printk(KERN_ERR PFX "COS_DFLT_CQ1 = 0x%x.\n",
1576 ql_read32(qdev, COS_DFLT_CQ1));
1577 printk(KERN_ERR PFX "COS_DFLT_CQ2 = 0x%x.\n",
1578 ql_read32(qdev, COS_DFLT_CQ2));
1579 printk(KERN_ERR PFX "SPLT_HDR = 0x%x.\n",
1580 ql_read32(qdev, SPLT_HDR));
1581 printk(KERN_ERR PFX "FC_PAUSE_THRES = 0x%x.\n",
1582 ql_read32(qdev, FC_PAUSE_THRES));
1583 printk(KERN_ERR PFX "NIC_PAUSE_THRES = 0x%x.\n",
1584 ql_read32(qdev, NIC_PAUSE_THRES));
1585 printk(KERN_ERR PFX "FC_ETHERTYPE = 0x%x.\n",
1586 ql_read32(qdev, FC_ETHERTYPE));
1587 printk(KERN_ERR PFX "FC_RCV_CFG = 0x%x.\n",
1588 ql_read32(qdev, FC_RCV_CFG));
1589 printk(KERN_ERR PFX "NIC_RCV_CFG = 0x%x.\n",
1590 ql_read32(qdev, NIC_RCV_CFG));
1591 printk(KERN_ERR PFX "FC_COS_TAGS = 0x%x.\n",
1592 ql_read32(qdev, FC_COS_TAGS));
1593 printk(KERN_ERR PFX "NIC_COS_TAGS = 0x%x.\n",
1594 ql_read32(qdev, NIC_COS_TAGS));
1595 printk(KERN_ERR PFX "MGMT_RCV_CFG = 0x%x.\n",
1596 ql_read32(qdev, MGMT_RCV_CFG));
1597 printk(KERN_ERR PFX "XG_SERDES_ADDR = 0x%x.\n",
1598 ql_read32(qdev, XG_SERDES_ADDR));
1599 printk(KERN_ERR PFX "XG_SERDES_DATA = 0x%x.\n",
1600 ql_read32(qdev, XG_SERDES_DATA));
1601 printk(KERN_ERR PFX "PRB_MX_ADDR = 0x%x.\n",
1602 ql_read32(qdev, PRB_MX_ADDR));
1603 printk(KERN_ERR PFX "PRB_MX_DATA = 0x%x.\n",
1604 ql_read32(qdev, PRB_MX_DATA));
1605 ql_dump_intr_states(qdev);
1606 ql_dump_xgmac_control_regs(qdev);
1607 ql_dump_ets_regs(qdev);
1608 ql_dump_cam_entries(qdev);
1609 ql_dump_routing_entries(qdev);
1610}
1611#endif
1612
1613#ifdef QL_STAT_DUMP
1614void ql_dump_stat(struct ql_adapter *qdev)
1615{
1616 printk(KERN_ERR "%s: Enter.\n", __func__);
1617 printk(KERN_ERR "tx_pkts = %ld\n",
1618 (unsigned long)qdev->nic_stats.tx_pkts);
1619 printk(KERN_ERR "tx_bytes = %ld\n",
1620 (unsigned long)qdev->nic_stats.tx_bytes);
1621 printk(KERN_ERR "tx_mcast_pkts = %ld.\n",
1622 (unsigned long)qdev->nic_stats.tx_mcast_pkts);
1623 printk(KERN_ERR "tx_bcast_pkts = %ld.\n",
1624 (unsigned long)qdev->nic_stats.tx_bcast_pkts);
1625 printk(KERN_ERR "tx_ucast_pkts = %ld.\n",
1626 (unsigned long)qdev->nic_stats.tx_ucast_pkts);
1627 printk(KERN_ERR "tx_ctl_pkts = %ld.\n",
1628 (unsigned long)qdev->nic_stats.tx_ctl_pkts);
1629 printk(KERN_ERR "tx_pause_pkts = %ld.\n",
1630 (unsigned long)qdev->nic_stats.tx_pause_pkts);
1631 printk(KERN_ERR "tx_64_pkt = %ld.\n",
1632 (unsigned long)qdev->nic_stats.tx_64_pkt);
1633 printk(KERN_ERR "tx_65_to_127_pkt = %ld.\n",
1634 (unsigned long)qdev->nic_stats.tx_65_to_127_pkt);
1635 printk(KERN_ERR "tx_128_to_255_pkt = %ld.\n",
1636 (unsigned long)qdev->nic_stats.tx_128_to_255_pkt);
1637 printk(KERN_ERR "tx_256_511_pkt = %ld.\n",
1638 (unsigned long)qdev->nic_stats.tx_256_511_pkt);
1639 printk(KERN_ERR "tx_512_to_1023_pkt = %ld.\n",
1640 (unsigned long)qdev->nic_stats.tx_512_to_1023_pkt);
1641 printk(KERN_ERR "tx_1024_to_1518_pkt = %ld.\n",
1642 (unsigned long)qdev->nic_stats.tx_1024_to_1518_pkt);
1643 printk(KERN_ERR "tx_1519_to_max_pkt = %ld.\n",
1644 (unsigned long)qdev->nic_stats.tx_1519_to_max_pkt);
1645 printk(KERN_ERR "tx_undersize_pkt = %ld.\n",
1646 (unsigned long)qdev->nic_stats.tx_undersize_pkt);
1647 printk(KERN_ERR "tx_oversize_pkt = %ld.\n",
1648 (unsigned long)qdev->nic_stats.tx_oversize_pkt);
1649 printk(KERN_ERR "rx_bytes = %ld.\n",
1650 (unsigned long)qdev->nic_stats.rx_bytes);
1651 printk(KERN_ERR "rx_bytes_ok = %ld.\n",
1652 (unsigned long)qdev->nic_stats.rx_bytes_ok);
1653 printk(KERN_ERR "rx_pkts = %ld.\n",
1654 (unsigned long)qdev->nic_stats.rx_pkts);
1655 printk(KERN_ERR "rx_pkts_ok = %ld.\n",
1656 (unsigned long)qdev->nic_stats.rx_pkts_ok);
1657 printk(KERN_ERR "rx_bcast_pkts = %ld.\n",
1658 (unsigned long)qdev->nic_stats.rx_bcast_pkts);
1659 printk(KERN_ERR "rx_mcast_pkts = %ld.\n",
1660 (unsigned long)qdev->nic_stats.rx_mcast_pkts);
1661 printk(KERN_ERR "rx_ucast_pkts = %ld.\n",
1662 (unsigned long)qdev->nic_stats.rx_ucast_pkts);
1663 printk(KERN_ERR "rx_undersize_pkts = %ld.\n",
1664 (unsigned long)qdev->nic_stats.rx_undersize_pkts);
1665 printk(KERN_ERR "rx_oversize_pkts = %ld.\n",
1666 (unsigned long)qdev->nic_stats.rx_oversize_pkts);
1667 printk(KERN_ERR "rx_jabber_pkts = %ld.\n",
1668 (unsigned long)qdev->nic_stats.rx_jabber_pkts);
1669 printk(KERN_ERR "rx_undersize_fcerr_pkts = %ld.\n",
1670 (unsigned long)qdev->nic_stats.rx_undersize_fcerr_pkts);
1671 printk(KERN_ERR "rx_drop_events = %ld.\n",
1672 (unsigned long)qdev->nic_stats.rx_drop_events);
1673 printk(KERN_ERR "rx_fcerr_pkts = %ld.\n",
1674 (unsigned long)qdev->nic_stats.rx_fcerr_pkts);
1675 printk(KERN_ERR "rx_align_err = %ld.\n",
1676 (unsigned long)qdev->nic_stats.rx_align_err);
1677 printk(KERN_ERR "rx_symbol_err = %ld.\n",
1678 (unsigned long)qdev->nic_stats.rx_symbol_err);
1679 printk(KERN_ERR "rx_mac_err = %ld.\n",
1680 (unsigned long)qdev->nic_stats.rx_mac_err);
1681 printk(KERN_ERR "rx_ctl_pkts = %ld.\n",
1682 (unsigned long)qdev->nic_stats.rx_ctl_pkts);
1683 printk(KERN_ERR "rx_pause_pkts = %ld.\n",
1684 (unsigned long)qdev->nic_stats.rx_pause_pkts);
1685 printk(KERN_ERR "rx_64_pkts = %ld.\n",
1686 (unsigned long)qdev->nic_stats.rx_64_pkts);
1687 printk(KERN_ERR "rx_65_to_127_pkts = %ld.\n",
1688 (unsigned long)qdev->nic_stats.rx_65_to_127_pkts);
1689 printk(KERN_ERR "rx_128_255_pkts = %ld.\n",
1690 (unsigned long)qdev->nic_stats.rx_128_255_pkts);
1691 printk(KERN_ERR "rx_256_511_pkts = %ld.\n",
1692 (unsigned long)qdev->nic_stats.rx_256_511_pkts);
1693 printk(KERN_ERR "rx_512_to_1023_pkts = %ld.\n",
1694 (unsigned long)qdev->nic_stats.rx_512_to_1023_pkts);
1695 printk(KERN_ERR "rx_1024_to_1518_pkts = %ld.\n",
1696 (unsigned long)qdev->nic_stats.rx_1024_to_1518_pkts);
1697 printk(KERN_ERR "rx_1519_to_max_pkts = %ld.\n",
1698 (unsigned long)qdev->nic_stats.rx_1519_to_max_pkts);
1699 printk(KERN_ERR "rx_len_err_pkts = %ld.\n",
1700 (unsigned long)qdev->nic_stats.rx_len_err_pkts);
1701};
1702#endif
1703
1704#ifdef QL_DEV_DUMP
1705void ql_dump_qdev(struct ql_adapter *qdev)
1706{
1707 int i;
1708 printk(KERN_ERR PFX "qdev->flags = %lx.\n",
1709 qdev->flags);
1710 printk(KERN_ERR PFX "qdev->vlgrp = %p.\n",
1711 qdev->vlgrp);
1712 printk(KERN_ERR PFX "qdev->pdev = %p.\n",
1713 qdev->pdev);
1714 printk(KERN_ERR PFX "qdev->ndev = %p.\n",
1715 qdev->ndev);
1716 printk(KERN_ERR PFX "qdev->chip_rev_id = %d.\n",
1717 qdev->chip_rev_id);
1718 printk(KERN_ERR PFX "qdev->reg_base = %p.\n",
1719 qdev->reg_base);
1720 printk(KERN_ERR PFX "qdev->doorbell_area = %p.\n",
1721 qdev->doorbell_area);
1722 printk(KERN_ERR PFX "qdev->doorbell_area_size = %d.\n",
1723 qdev->doorbell_area_size);
1724 printk(KERN_ERR PFX "msg_enable = %x.\n",
1725 qdev->msg_enable);
1726 printk(KERN_ERR PFX "qdev->rx_ring_shadow_reg_area = %p.\n",
1727 qdev->rx_ring_shadow_reg_area);
53159d06
DM		 1728 printk(KERN_ERR PFX "qdev->rx_ring_shadow_reg_dma = %llx.\n",
1729 (unsigned long long) qdev->rx_ring_shadow_reg_dma);
c4e84bde
RM		 1730 printk(KERN_ERR PFX "qdev->tx_ring_shadow_reg_area = %p.\n",
1731 qdev->tx_ring_shadow_reg_area);
53159d06
DM		 1732 printk(KERN_ERR PFX "qdev->tx_ring_shadow_reg_dma = %llx.\n",
1733 (unsigned long long) qdev->tx_ring_shadow_reg_dma);
c4e84bde
RM		 1734 printk(KERN_ERR PFX "qdev->intr_count = %d.\n",
1735 qdev->intr_count);
1736 if (qdev->msi_x_entry)
1737 for (i = 0; i < qdev->intr_count; i++) {
1738 printk(KERN_ERR PFX
1739 "msi_x_entry.[%d]vector = %d.\n", i,
1740 qdev->msi_x_entry[i].vector);
1741 printk(KERN_ERR PFX
1742 "msi_x_entry.[%d]entry = %d.\n", i,
1743 qdev->msi_x_entry[i].entry);
1744 }
1745 for (i = 0; i < qdev->intr_count; i++) {
1746 printk(KERN_ERR PFX
1747 "intr_context[%d].qdev = %p.\n", i,
1748 qdev->intr_context[i].qdev);
1749 printk(KERN_ERR PFX
1750 "intr_context[%d].intr = %d.\n", i,
1751 qdev->intr_context[i].intr);
1752 printk(KERN_ERR PFX
1753 "intr_context[%d].hooked = %d.\n", i,
1754 qdev->intr_context[i].hooked);
1755 printk(KERN_ERR PFX
1756 "intr_context[%d].intr_en_mask = 0x%08x.\n", i,
1757 qdev->intr_context[i].intr_en_mask);
1758 printk(KERN_ERR PFX
1759 "intr_context[%d].intr_dis_mask = 0x%08x.\n", i,
1760 qdev->intr_context[i].intr_dis_mask);
1761 printk(KERN_ERR PFX
1762 "intr_context[%d].intr_read_mask = 0x%08x.\n", i,
1763 qdev->intr_context[i].intr_read_mask);
1764 }
1765 printk(KERN_ERR PFX "qdev->tx_ring_count = %d.\n", qdev->tx_ring_count);
1766 printk(KERN_ERR PFX "qdev->rx_ring_count = %d.\n", qdev->rx_ring_count);
1767 printk(KERN_ERR PFX "qdev->ring_mem_size = %d.\n", qdev->ring_mem_size);
1768 printk(KERN_ERR PFX "qdev->ring_mem = %p.\n", qdev->ring_mem);
1769 printk(KERN_ERR PFX "qdev->intr_count = %d.\n", qdev->intr_count);
1770 printk(KERN_ERR PFX "qdev->tx_ring = %p.\n",
1771 qdev->tx_ring);
c4e84bde
RM		 1772 printk(KERN_ERR PFX "qdev->rss_ring_count = %d.\n",
1773 qdev->rss_ring_count);
1774 printk(KERN_ERR PFX "qdev->rx_ring = %p.\n", qdev->rx_ring);
1775 printk(KERN_ERR PFX "qdev->default_rx_queue = %d.\n",
1776 qdev->default_rx_queue);
1777 printk(KERN_ERR PFX "qdev->xg_sem_mask = 0x%08x.\n",
1778 qdev->xg_sem_mask);
1779 printk(KERN_ERR PFX "qdev->port_link_up = 0x%08x.\n",
1780 qdev->port_link_up);
1781 printk(KERN_ERR PFX "qdev->port_init = 0x%08x.\n",
1782 qdev->port_init);
1783
1784}
1785#endif
1786
1787#ifdef QL_CB_DUMP
1788void ql_dump_wqicb(struct wqicb *wqicb)
1789{
1790 printk(KERN_ERR PFX "Dumping wqicb stuff...\n");
1791 printk(KERN_ERR PFX "wqicb->len = 0x%x.\n", le16_to_cpu(wqicb->len));
1792 printk(KERN_ERR PFX "wqicb->flags = %x.\n", le16_to_cpu(wqicb->flags));
1793 printk(KERN_ERR PFX "wqicb->cq_id_rss = %d.\n",
1794 le16_to_cpu(wqicb->cq_id_rss));
1795 printk(KERN_ERR PFX "wqicb->rid = 0x%x.\n", le16_to_cpu(wqicb->rid));
97345524
RM		 1796 printk(KERN_ERR PFX "wqicb->wq_addr = 0x%llx.\n",
1797 (unsigned long long) le64_to_cpu(wqicb->addr));
1798 printk(KERN_ERR PFX "wqicb->wq_cnsmr_idx_addr = 0x%llx.\n",
1799 (unsigned long long) le64_to_cpu(wqicb->cnsmr_idx_addr));
c4e84bde
RM		 1800}
1801
1802void ql_dump_tx_ring(struct tx_ring *tx_ring)
1803{
1804 if (tx_ring == NULL)
1805 return;
1806 printk(KERN_ERR PFX
1807 "===================== Dumping tx_ring %d ===============.\n",
1808 tx_ring->wq_id);
1809 printk(KERN_ERR PFX "tx_ring->base = %p.\n", tx_ring->wq_base);
1810 printk(KERN_ERR PFX "tx_ring->base_dma = 0x%llx.\n",
53159d06 1811 (unsigned long long) tx_ring->wq_base_dma);
ba7cd3ba
RM		 1812 printk(KERN_ERR PFX
1813 "tx_ring->cnsmr_idx_sh_reg, addr = 0x%p, value = %d.\n",
1814 tx_ring->cnsmr_idx_sh_reg,
1815 tx_ring->cnsmr_idx_sh_reg
1816 ? ql_read_sh_reg(tx_ring->cnsmr_idx_sh_reg) : 0);
c4e84bde
RM		 1817 printk(KERN_ERR PFX "tx_ring->size = %d.\n", tx_ring->wq_size);
1818 printk(KERN_ERR PFX "tx_ring->len = %d.\n", tx_ring->wq_len);
1819 printk(KERN_ERR PFX "tx_ring->prod_idx_db_reg = %p.\n",
1820 tx_ring->prod_idx_db_reg);
1821 printk(KERN_ERR PFX "tx_ring->valid_db_reg = %p.\n",
1822 tx_ring->valid_db_reg);
1823 printk(KERN_ERR PFX "tx_ring->prod_idx = %d.\n", tx_ring->prod_idx);
1824 printk(KERN_ERR PFX "tx_ring->cq_id = %d.\n", tx_ring->cq_id);
1825 printk(KERN_ERR PFX "tx_ring->wq_id = %d.\n", tx_ring->wq_id);
1826 printk(KERN_ERR PFX "tx_ring->q = %p.\n", tx_ring->q);
1827 printk(KERN_ERR PFX "tx_ring->tx_count = %d.\n",
1828 atomic_read(&tx_ring->tx_count));
1829}
1830
1831void ql_dump_ricb(struct ricb *ricb)
1832{
1833 int i;
1834 printk(KERN_ERR PFX
1835 "===================== Dumping ricb ===============.\n");
1836 printk(KERN_ERR PFX "Dumping ricb stuff...\n");
1837
1838 printk(KERN_ERR PFX "ricb->base_cq = %d.\n", ricb->base_cq & 0x1f);
1839 printk(KERN_ERR PFX "ricb->flags = %s%s%s%s%s%s%s%s%s.\n",
1840 ricb->base_cq & RSS_L4K ? "RSS_L4K " : "",
1841 ricb->flags & RSS_L6K ? "RSS_L6K " : "",
1842 ricb->flags & RSS_LI ? "RSS_LI " : "",
1843 ricb->flags & RSS_LB ? "RSS_LB " : "",
1844 ricb->flags & RSS_LM ? "RSS_LM " : "",
1845 ricb->flags & RSS_RI4 ? "RSS_RI4 " : "",
1846 ricb->flags & RSS_RT4 ? "RSS_RT4 " : "",
1847 ricb->flags & RSS_RI6 ? "RSS_RI6 " : "",
1848 ricb->flags & RSS_RT6 ? "RSS_RT6 " : "");
1849 printk(KERN_ERR PFX "ricb->mask = 0x%.04x.\n", le16_to_cpu(ricb->mask));
1850 for (i = 0; i < 16; i++)
1851 printk(KERN_ERR PFX "ricb->hash_cq_id[%d] = 0x%.08x.\n", i,
1852 le32_to_cpu(ricb->hash_cq_id[i]));
1853 for (i = 0; i < 10; i++)
1854 printk(KERN_ERR PFX "ricb->ipv6_hash_key[%d] = 0x%.08x.\n", i,
1855 le32_to_cpu(ricb->ipv6_hash_key[i]));
1856 for (i = 0; i < 4; i++)
1857 printk(KERN_ERR PFX "ricb->ipv4_hash_key[%d] = 0x%.08x.\n", i,
1858 le32_to_cpu(ricb->ipv4_hash_key[i]));
1859}
1860
1861void ql_dump_cqicb(struct cqicb *cqicb)
1862{
1863 printk(KERN_ERR PFX "Dumping cqicb stuff...\n");
1864
1865 printk(KERN_ERR PFX "cqicb->msix_vect = %d.\n", cqicb->msix_vect);
1866 printk(KERN_ERR PFX "cqicb->flags = %x.\n", cqicb->flags);
1867 printk(KERN_ERR PFX "cqicb->len = %d.\n", le16_to_cpu(cqicb->len));
97345524
RM		 1868 printk(KERN_ERR PFX "cqicb->addr = 0x%llx.\n",
1869 (unsigned long long) le64_to_cpu(cqicb->addr));
1870 printk(KERN_ERR PFX "cqicb->prod_idx_addr = 0x%llx.\n",
1871 (unsigned long long) le64_to_cpu(cqicb->prod_idx_addr));
c4e84bde
RM		 1872 printk(KERN_ERR PFX "cqicb->pkt_delay = 0x%.04x.\n",
1873 le16_to_cpu(cqicb->pkt_delay));
1874 printk(KERN_ERR PFX "cqicb->irq_delay = 0x%.04x.\n",
1875 le16_to_cpu(cqicb->irq_delay));
97345524
RM		 1876 printk(KERN_ERR PFX "cqicb->lbq_addr = 0x%llx.\n",
1877 (unsigned long long) le64_to_cpu(cqicb->lbq_addr));
c4e84bde
RM		 1878 printk(KERN_ERR PFX "cqicb->lbq_buf_size = 0x%.04x.\n",
1879 le16_to_cpu(cqicb->lbq_buf_size));
1880 printk(KERN_ERR PFX "cqicb->lbq_len = 0x%.04x.\n",
1881 le16_to_cpu(cqicb->lbq_len));
97345524
RM		 1882 printk(KERN_ERR PFX "cqicb->sbq_addr = 0x%llx.\n",
1883 (unsigned long long) le64_to_cpu(cqicb->sbq_addr));
c4e84bde
RM		 1884 printk(KERN_ERR PFX "cqicb->sbq_buf_size = 0x%.04x.\n",
1885 le16_to_cpu(cqicb->sbq_buf_size));
1886 printk(KERN_ERR PFX "cqicb->sbq_len = 0x%.04x.\n",
1887 le16_to_cpu(cqicb->sbq_len));
1888}
1889
1890void ql_dump_rx_ring(struct rx_ring *rx_ring)
1891{
1892 if (rx_ring == NULL)
1893 return;
1894 printk(KERN_ERR PFX
1895 "===================== Dumping rx_ring %d ===============.\n",
1896 rx_ring->cq_id);
1897 printk(KERN_ERR PFX "Dumping rx_ring %d, type = %s%s%s.\n",
1898 rx_ring->cq_id, rx_ring->type == DEFAULT_Q ? "DEFAULT" : "",
1899 rx_ring->type == TX_Q ? "OUTBOUND COMPLETIONS" : "",
1900 rx_ring->type == RX_Q ? "INBOUND_COMPLETIONS" : "");
1901 printk(KERN_ERR PFX "rx_ring->cqicb = %p.\n", &rx_ring->cqicb);
1902 printk(KERN_ERR PFX "rx_ring->cq_base = %p.\n", rx_ring->cq_base);
1903 printk(KERN_ERR PFX "rx_ring->cq_base_dma = %llx.\n",
53159d06 1904 (unsigned long long) rx_ring->cq_base_dma);
c4e84bde
RM		 1905 printk(KERN_ERR PFX "rx_ring->cq_size = %d.\n", rx_ring->cq_size);
1906 printk(KERN_ERR PFX "rx_ring->cq_len = %d.\n", rx_ring->cq_len);
1907 printk(KERN_ERR PFX
ba7cd3ba 1908 "rx_ring->prod_idx_sh_reg, addr = 0x%p, value = %d.\n",
c4e84bde 1909 rx_ring->prod_idx_sh_reg,
ba7cd3ba
RM		 1910 rx_ring->prod_idx_sh_reg
1911 ? ql_read_sh_reg(rx_ring->prod_idx_sh_reg) : 0);
c4e84bde 1912 printk(KERN_ERR PFX "rx_ring->prod_idx_sh_reg_dma = %llx.\n",
53159d06 1913 (unsigned long long) rx_ring->prod_idx_sh_reg_dma);
c4e84bde
RM		 1914 printk(KERN_ERR PFX "rx_ring->cnsmr_idx_db_reg = %p.\n",
1915 rx_ring->cnsmr_idx_db_reg);
1916 printk(KERN_ERR PFX "rx_ring->cnsmr_idx = %d.\n", rx_ring->cnsmr_idx);
1917 printk(KERN_ERR PFX "rx_ring->curr_entry = %p.\n", rx_ring->curr_entry);
1918 printk(KERN_ERR PFX "rx_ring->valid_db_reg = %p.\n",
1919 rx_ring->valid_db_reg);
1920
1921 printk(KERN_ERR PFX "rx_ring->lbq_base = %p.\n", rx_ring->lbq_base);
1922 printk(KERN_ERR PFX "rx_ring->lbq_base_dma = %llx.\n",
53159d06 1923 (unsigned long long) rx_ring->lbq_base_dma);
c4e84bde
RM		 1924 printk(KERN_ERR PFX "rx_ring->lbq_base_indirect = %p.\n",
1925 rx_ring->lbq_base_indirect);
1926 printk(KERN_ERR PFX "rx_ring->lbq_base_indirect_dma = %llx.\n",
53159d06 1927 (unsigned long long) rx_ring->lbq_base_indirect_dma);
c4e84bde
RM		 1928 printk(KERN_ERR PFX "rx_ring->lbq = %p.\n", rx_ring->lbq);
1929 printk(KERN_ERR PFX "rx_ring->lbq_len = %d.\n", rx_ring->lbq_len);
1930 printk(KERN_ERR PFX "rx_ring->lbq_size = %d.\n", rx_ring->lbq_size);
1931 printk(KERN_ERR PFX "rx_ring->lbq_prod_idx_db_reg = %p.\n",
1932 rx_ring->lbq_prod_idx_db_reg);
1933 printk(KERN_ERR PFX "rx_ring->lbq_prod_idx = %d.\n",
1934 rx_ring->lbq_prod_idx);
1935 printk(KERN_ERR PFX "rx_ring->lbq_curr_idx = %d.\n",
1936 rx_ring->lbq_curr_idx);
1937 printk(KERN_ERR PFX "rx_ring->lbq_clean_idx = %d.\n",
1938 rx_ring->lbq_clean_idx);
1939 printk(KERN_ERR PFX "rx_ring->lbq_free_cnt = %d.\n",
1940 rx_ring->lbq_free_cnt);
1941 printk(KERN_ERR PFX "rx_ring->lbq_buf_size = %d.\n",
1942 rx_ring->lbq_buf_size);
1943
1944 printk(KERN_ERR PFX "rx_ring->sbq_base = %p.\n", rx_ring->sbq_base);
1945 printk(KERN_ERR PFX "rx_ring->sbq_base_dma = %llx.\n",
53159d06 1946 (unsigned long long) rx_ring->sbq_base_dma);
c4e84bde
RM		 1947 printk(KERN_ERR PFX "rx_ring->sbq_base_indirect = %p.\n",
1948 rx_ring->sbq_base_indirect);
1949 printk(KERN_ERR PFX "rx_ring->sbq_base_indirect_dma = %llx.\n",
53159d06 1950 (unsigned long long) rx_ring->sbq_base_indirect_dma);
c4e84bde
RM		 1951 printk(KERN_ERR PFX "rx_ring->sbq = %p.\n", rx_ring->sbq);
1952 printk(KERN_ERR PFX "rx_ring->sbq_len = %d.\n", rx_ring->sbq_len);
1953 printk(KERN_ERR PFX "rx_ring->sbq_size = %d.\n", rx_ring->sbq_size);
1954 printk(KERN_ERR PFX "rx_ring->sbq_prod_idx_db_reg addr = %p.\n",
1955 rx_ring->sbq_prod_idx_db_reg);
1956 printk(KERN_ERR PFX "rx_ring->sbq_prod_idx = %d.\n",
1957 rx_ring->sbq_prod_idx);
1958 printk(KERN_ERR PFX "rx_ring->sbq_curr_idx = %d.\n",
1959 rx_ring->sbq_curr_idx);
1960 printk(KERN_ERR PFX "rx_ring->sbq_clean_idx = %d.\n",
1961 rx_ring->sbq_clean_idx);
1962 printk(KERN_ERR PFX "rx_ring->sbq_free_cnt = %d.\n",
1963 rx_ring->sbq_free_cnt);
1964 printk(KERN_ERR PFX "rx_ring->sbq_buf_size = %d.\n",
1965 rx_ring->sbq_buf_size);
1966 printk(KERN_ERR PFX "rx_ring->cq_id = %d.\n", rx_ring->cq_id);
1967 printk(KERN_ERR PFX "rx_ring->irq = %d.\n", rx_ring->irq);
1968 printk(KERN_ERR PFX "rx_ring->cpu = %d.\n", rx_ring->cpu);
1969 printk(KERN_ERR PFX "rx_ring->qdev = %p.\n", rx_ring->qdev);
1970}
1971
1972void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id)
1973{
1974 void *ptr;
1975
1976 printk(KERN_ERR PFX "%s: Enter.\n", __func__);
1977
1978 ptr = kmalloc(size, GFP_ATOMIC);
1979 if (ptr == NULL) {
1980 printk(KERN_ERR PFX "%s: Couldn't allocate a buffer.\n",
1981 __func__);
1982 return;
1983 }
1984
1985 if (ql_write_cfg(qdev, ptr, size, bit, q_id)) {
1986 printk(KERN_ERR "%s: Failed to upload control block!\n",
1987 __func__);
1988 goto fail_it;
1989 }
1990 switch (bit) {
1991 case CFG_DRQ:
1992 ql_dump_wqicb((struct wqicb *)ptr);
1993 break;
1994 case CFG_DCQ:
1995 ql_dump_cqicb((struct cqicb *)ptr);
1996 break;
1997 case CFG_DR:
1998 ql_dump_ricb((struct ricb *)ptr);
1999 break;
2000 default:
2001 printk(KERN_ERR PFX "%s: Invalid bit value = %x.\n",
2002 __func__, bit);
2003 break;
2004 }
2005fail_it:
2006 kfree(ptr);
2007}
2008#endif
2009
2010#ifdef QL_OB_DUMP
2011void ql_dump_tx_desc(struct tx_buf_desc *tbd)
2012{
2013 printk(KERN_ERR PFX "tbd->addr = 0x%llx\n",
2014 le64_to_cpu((u64) tbd->addr));
2015 printk(KERN_ERR PFX "tbd->len = %d\n",
2016 le32_to_cpu(tbd->len & TX_DESC_LEN_MASK));
2017 printk(KERN_ERR PFX "tbd->flags = %s %s\n",
2018 tbd->len & TX_DESC_C ? "C" : ".",
2019 tbd->len & TX_DESC_E ? "E" : ".");
2020 tbd++;
2021 printk(KERN_ERR PFX "tbd->addr = 0x%llx\n",
2022 le64_to_cpu((u64) tbd->addr));
2023 printk(KERN_ERR PFX "tbd->len = %d\n",
2024 le32_to_cpu(tbd->len & TX_DESC_LEN_MASK));
2025 printk(KERN_ERR PFX "tbd->flags = %s %s\n",
2026 tbd->len & TX_DESC_C ? "C" : ".",
2027 tbd->len & TX_DESC_E ? "E" : ".");
2028 tbd++;
2029 printk(KERN_ERR PFX "tbd->addr = 0x%llx\n",
2030 le64_to_cpu((u64) tbd->addr));
2031 printk(KERN_ERR PFX "tbd->len = %d\n",
2032 le32_to_cpu(tbd->len & TX_DESC_LEN_MASK));
2033 printk(KERN_ERR PFX "tbd->flags = %s %s\n",
2034 tbd->len & TX_DESC_C ? "C" : ".",
2035 tbd->len & TX_DESC_E ? "E" : ".");
2036
2037}
2038
2039void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb)
2040{
2041 struct ob_mac_tso_iocb_req *ob_mac_tso_iocb =
2042 (struct ob_mac_tso_iocb_req *)ob_mac_iocb;
2043 struct tx_buf_desc *tbd;
2044 u16 frame_len;
2045
2046 printk(KERN_ERR PFX "%s\n", __func__);
2047 printk(KERN_ERR PFX "opcode = %s\n",
2048 (ob_mac_iocb->opcode == OPCODE_OB_MAC_IOCB) ? "MAC" : "TSO");
2049 printk(KERN_ERR PFX "flags1 = %s %s %s %s %s\n",
2050 ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_OI ? "OI" : "",
2051 ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_I ? "I" : "",
2052 ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_D ? "D" : "",
2053 ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_IP4 ? "IP4" : "",
2054 ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_IP6 ? "IP6" : "");
2055 printk(KERN_ERR PFX "flags2 = %s %s %s\n",
2056 ob_mac_tso_iocb->flags2 & OB_MAC_TSO_IOCB_LSO ? "LSO" : "",
2057 ob_mac_tso_iocb->flags2 & OB_MAC_TSO_IOCB_UC ? "UC" : "",
2058 ob_mac_tso_iocb->flags2 & OB_MAC_TSO_IOCB_TC ? "TC" : "");
2381a55c 2059 printk(KERN_ERR PFX "flags3 = %s %s %s\n",
c4e84bde
RM		 2060 ob_mac_tso_iocb->flags3 & OB_MAC_TSO_IOCB_IC ? "IC" : "",
2061 ob_mac_tso_iocb->flags3 & OB_MAC_TSO_IOCB_DFP ? "DFP" : "",
2062 ob_mac_tso_iocb->flags3 & OB_MAC_TSO_IOCB_V ? "V" : "");
2063 printk(KERN_ERR PFX "tid = %x\n", ob_mac_iocb->tid);
2064 printk(KERN_ERR PFX "txq_idx = %d\n", ob_mac_iocb->txq_idx);
2065 printk(KERN_ERR PFX "vlan_tci = %x\n", ob_mac_tso_iocb->vlan_tci);
2066 if (ob_mac_iocb->opcode == OPCODE_OB_MAC_TSO_IOCB) {
2067 printk(KERN_ERR PFX "frame_len = %d\n",
2068 le32_to_cpu(ob_mac_tso_iocb->frame_len));
2069 printk(KERN_ERR PFX "mss = %d\n",
2070 le16_to_cpu(ob_mac_tso_iocb->mss));
2071 printk(KERN_ERR PFX "prot_hdr_len = %d\n",
2072 le16_to_cpu(ob_mac_tso_iocb->total_hdrs_len));
2073 printk(KERN_ERR PFX "hdr_offset = 0x%.04x\n",
2074 le16_to_cpu(ob_mac_tso_iocb->net_trans_offset));
2075 frame_len = le32_to_cpu(ob_mac_tso_iocb->frame_len);
2076 } else {
2077 printk(KERN_ERR PFX "frame_len = %d\n",
2078 le16_to_cpu(ob_mac_iocb->frame_len));
2079 frame_len = le16_to_cpu(ob_mac_iocb->frame_len);
2080 }
2081 tbd = &ob_mac_iocb->tbd[0];
2082 ql_dump_tx_desc(tbd);
2083}
2084
2085void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp)
2086{
2087 printk(KERN_ERR PFX "%s\n", __func__);
2088 printk(KERN_ERR PFX "opcode = %d\n", ob_mac_rsp->opcode);
2089 printk(KERN_ERR PFX "flags = %s %s %s %s %s %s %s\n",
2090 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_OI ? "OI" : ".",
2091 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_I ? "I" : ".",
2092 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_E ? "E" : ".",
2093 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_S ? "S" : ".",
2094 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_L ? "L" : ".",
2095 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_P ? "P" : ".",
2096 ob_mac_rsp->flags2 & OB_MAC_IOCB_RSP_B ? "B" : ".");
2097 printk(KERN_ERR PFX "tid = %x\n", ob_mac_rsp->tid);
2098}
2099#endif
2100
2101#ifdef QL_IB_DUMP
2102void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp)
2103{
2104 printk(KERN_ERR PFX "%s\n", __func__);
2105 printk(KERN_ERR PFX "opcode = 0x%x\n", ib_mac_rsp->opcode);
2106 printk(KERN_ERR PFX "flags1 = %s%s%s%s%s%s\n",
2107 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_OI ? "OI " : "",
2108 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_I ? "I " : "",
2109 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_TE ? "TE " : "",
2110 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU ? "NU " : "",
2111 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_IE ? "IE " : "",
2112 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_B ? "B " : "");
2113
2114 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK)
2115 printk(KERN_ERR PFX "%s%s%s Multicast.\n",
2116 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
2117 IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
2118 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
2119 IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
2120 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
2121 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
2122
2123 printk(KERN_ERR PFX "flags2 = %s%s%s%s%s\n",
2124 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) ? "P " : "",
2125 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ? "V " : "",
2126 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) ? "U " : "",
2127 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ? "T " : "",
2128 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_FO) ? "FO " : "");
2129
2130 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK)
2131 printk(KERN_ERR PFX "%s%s%s%s%s error.\n",
2132 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) ==
2133 IB_MAC_IOCB_RSP_ERR_OVERSIZE ? "oversize" : "",
2134 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) ==
2135 IB_MAC_IOCB_RSP_ERR_UNDERSIZE ? "undersize" : "",
2136 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) ==
2137 IB_MAC_IOCB_RSP_ERR_PREAMBLE ? "preamble" : "",
2138 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) ==
2139 IB_MAC_IOCB_RSP_ERR_FRAME_LEN ? "frame length" : "",
2140 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) ==
2141 IB_MAC_IOCB_RSP_ERR_CRC ? "CRC" : "");
2142
2143 printk(KERN_ERR PFX "flags3 = %s%s.\n",
2144 ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS ? "DS " : "",
2145 ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL ? "DL " : "");
2146
2147 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK)
2148 printk(KERN_ERR PFX "RSS flags = %s%s%s%s.\n",
2149 ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) ==
2150 IB_MAC_IOCB_RSP_M_IPV4) ? "IPv4 RSS" : "",
2151 ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) ==
2152 IB_MAC_IOCB_RSP_M_IPV6) ? "IPv6 RSS " : "",
2153 ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) ==
2154 IB_MAC_IOCB_RSP_M_TCP_V4) ? "TCP/IPv4 RSS" : "",
2155 ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) ==
2156 IB_MAC_IOCB_RSP_M_TCP_V6) ? "TCP/IPv6 RSS" : "");
2157
2158 printk(KERN_ERR PFX "data_len = %d\n",
2159 le32_to_cpu(ib_mac_rsp->data_len));
97345524
RM		 2160 printk(KERN_ERR PFX "data_addr = 0x%llx\n",
2161 (unsigned long long) le64_to_cpu(ib_mac_rsp->data_addr));
c4e84bde
RM		 2162 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK)
2163 printk(KERN_ERR PFX "rss = %x\n",
2164 le32_to_cpu(ib_mac_rsp->rss));
2165 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)
2166 printk(KERN_ERR PFX "vlan_id = %x\n",
2167 le16_to_cpu(ib_mac_rsp->vlan_id));
2168
2169 printk(KERN_ERR PFX "flags4 = %s%s%s.\n",
a303ce09
RM		 2170 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV ? "HV " : "",
2171 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS ? "HS " : "",
2172 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HL ? "HL " : "");
2173
2174 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV) {
c4e84bde
RM		 2175 printk(KERN_ERR PFX "hdr length = %d.\n",
2176 le32_to_cpu(ib_mac_rsp->hdr_len));
97345524
RM		 2177 printk(KERN_ERR PFX "hdr addr = 0x%llx.\n",
2178 (unsigned long long) le64_to_cpu(ib_mac_rsp->hdr_addr));
c4e84bde
RM		 2179 }
2180}
2181#endif
2182
2183#ifdef QL_ALL_DUMP
2184void ql_dump_all(struct ql_adapter *qdev)
2185{
2186 int i;
2187
2188 QL_DUMP_REGS(qdev);
2189 QL_DUMP_QDEV(qdev);
2190 for (i = 0; i < qdev->tx_ring_count; i++) {
2191 QL_DUMP_TX_RING(&qdev->tx_ring[i]);
2192 QL_DUMP_WQICB((struct wqicb *)&qdev->tx_ring[i]);
2193 }
2194 for (i = 0; i < qdev->rx_ring_count; i++) {
2195 QL_DUMP_RX_RING(&qdev->rx_ring[i]);
2196 QL_DUMP_CQICB((struct cqicb *)&qdev->rx_ring[i]);
2197 }
2198}
2199#endif
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