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net: Use sk_tx_queue_mapping for connected sockets
[net-next-2.6.git] / drivers / net / qlge / qlge.h
CommitLineData
c4e84bde
RM		 1/*
2 * QLogic QLA41xx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qlge for copyright and licensing details.
6 */
7#ifndef _QLGE_H_
8#define _QLGE_H_
9
10#include <linux/pci.h>
11#include <linux/netdevice.h>
86aaf9ad 12#include <linux/rtnetlink.h>
c4e84bde
RM		 13
14/*
15 * General definitions...
16 */
17#define DRV_NAME "qlge"
18#define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver "
19#define DRV_VERSION "v1.00.00-b3"
20
21#define PFX "qlge: "
22#define QPRINTK(qdev, nlevel, klevel, fmt, args...) \
23 do { \
24 if (!((qdev)->msg_enable & NETIF_MSG_##nlevel)) \
25 ; \
26 else \
27 dev_printk(KERN_##klevel, &((qdev)->pdev->dev), \
28 "%s: " fmt, __func__, ##args); \
29 } while (0)
30
88c55e3c
RM		 31#define WQ_ADDR_ALIGN 0x3 /* 4 byte alignment */
32
c4e84bde 33#define QLGE_VENDOR_ID 0x1077
b0c2aadf 34#define QLGE_DEVICE_ID_8012 0x8012
cdca8d02 35#define QLGE_DEVICE_ID_8000 0x8000
683d46a9
RM		 36#define MAX_CPUS 8
37#define MAX_TX_RINGS MAX_CPUS
38#define MAX_RX_RINGS ((MAX_CPUS * 2) + 1)
c4e84bde
RM		 39
40#define NUM_TX_RING_ENTRIES 256
41#define NUM_RX_RING_ENTRIES 256
42
43#define NUM_SMALL_BUFFERS 512
44#define NUM_LARGE_BUFFERS 512
b8facca0
RM		 45#define DB_PAGE_SIZE 4096
46
47/* Calculate the number of (4k) pages required to
48 * contain a buffer queue of the given length.
49 */
50#define MAX_DB_PAGES_PER_BQ(x) \
51 (((x * sizeof(u64)) / DB_PAGE_SIZE) + \
52 (((x * sizeof(u64)) % DB_PAGE_SIZE) ? 1 : 0))
c4e84bde 53
b8facca0
RM		 54#define RX_RING_SHADOW_SPACE (sizeof(u64) + \
55 MAX_DB_PAGES_PER_BQ(NUM_SMALL_BUFFERS) * sizeof(u64) + \
56 MAX_DB_PAGES_PER_BQ(NUM_LARGE_BUFFERS) * sizeof(u64))
52e55f3c
RM		 57#define SMALL_BUFFER_SIZE 512
58#define SMALL_BUF_MAP_SIZE (SMALL_BUFFER_SIZE / 2)
7c734359
RM		 59#define LARGE_BUFFER_MAX_SIZE 8192
60#define LARGE_BUFFER_MIN_SIZE 2048
c4e84bde
RM		 61#define MAX_SPLIT_SIZE 1023
62#define QLGE_SB_PAD 32
63
683d46a9 64#define MAX_CQ 128
c4e84bde
RM		 65#define DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */
66#define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */
67#define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2)
68#define UDELAY_COUNT 3
d2ba4986 69#define UDELAY_DELAY 100
c4e84bde
RM		 70
71
72#define TX_DESC_PER_IOCB 8
73/* The maximum number of frags we handle is based
74 * on PAGE_SIZE...
75 */
76#if (PAGE_SHIFT == 12) || (PAGE_SHIFT == 13) /* 4k & 8k pages */
77#define TX_DESC_PER_OAL ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2)
48501371 78#else /* all other page sizes */
c4e84bde
RM		 79#define TX_DESC_PER_OAL 0
80#endif
81
e4552f51
RM		 82/* MPI test register definitions. This register
83 * is used for determining alternate NIC function's
84 * PCI->func number.
85 */
86enum {
87 MPI_TEST_FUNC_PORT_CFG = 0x1002,
88 MPI_TEST_NIC1_FUNC_SHIFT = 1,
89 MPI_TEST_NIC2_FUNC_SHIFT = 5,
90 MPI_TEST_NIC_FUNC_MASK = 0x00000007,
91};
92
c4e84bde
RM		 93/*
94 * Processor Address Register (PROC_ADDR) bit definitions.
95 */
96enum {
97
98 /* Misc. stuff */
99 MAILBOX_COUNT = 16,
100
101 PROC_ADDR_RDY = (1 << 31),
102 PROC_ADDR_R = (1 << 30),
103 PROC_ADDR_ERR = (1 << 29),
104 PROC_ADDR_DA = (1 << 28),
105 PROC_ADDR_FUNC0_MBI = 0x00001180,
106 PROC_ADDR_FUNC0_MBO = (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT),
107 PROC_ADDR_FUNC0_CTL = 0x000011a1,
108 PROC_ADDR_FUNC2_MBI = 0x00001280,
109 PROC_ADDR_FUNC2_MBO = (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT),
110 PROC_ADDR_FUNC2_CTL = 0x000012a1,
111 PROC_ADDR_MPI_RISC = 0x00000000,
112 PROC_ADDR_MDE = 0x00010000,
113 PROC_ADDR_REGBLOCK = 0x00020000,
114 PROC_ADDR_RISC_REG = 0x00030000,
115};
116
117/*
118 * System Register (SYS) bit definitions.
119 */
120enum {
121 SYS_EFE = (1 << 0),
122 SYS_FAE = (1 << 1),
123 SYS_MDC = (1 << 2),
124 SYS_DST = (1 << 3),
125 SYS_DWC = (1 << 4),
126 SYS_EVW = (1 << 5),
127 SYS_OMP_DLY_MASK = 0x3f000000,
128 /*
129 * There are no values defined as of edit #15.
130 */
131 SYS_ODI = (1 << 14),
132};
133
134/*
135 * Reset/Failover Register (RST_FO) bit definitions.
136 */
137enum {
138 RST_FO_TFO = (1 << 0),
139 RST_FO_RR_MASK = 0x00060000,
140 RST_FO_RR_CQ_CAM = 0x00000000,
d799bbfb
RM		 141 RST_FO_RR_DROP = 0x00000002,
142 RST_FO_RR_DQ = 0x00000004,
143 RST_FO_RR_RCV_FUNC_CQ = 0x00000006,
c4e84bde
RM		 144 RST_FO_FRB = (1 << 12),
145 RST_FO_MOP = (1 << 13),
146 RST_FO_REG = (1 << 14),
147 RST_FO_FR = (1 << 15),
148};
149
150/*
151 * Function Specific Control Register (FSC) bit definitions.
152 */
153enum {
154 FSC_DBRST_MASK = 0x00070000,
155 FSC_DBRST_256 = 0x00000000,
156 FSC_DBRST_512 = 0x00000001,
157 FSC_DBRST_768 = 0x00000002,
158 FSC_DBRST_1024 = 0x00000003,
159 FSC_DBL_MASK = 0x00180000,
160 FSC_DBL_DBRST = 0x00000000,
161 FSC_DBL_MAX_PLD = 0x00000008,
162 FSC_DBL_MAX_BRST = 0x00000010,
163 FSC_DBL_128_BYTES = 0x00000018,
164 FSC_EC = (1 << 5),
165 FSC_EPC_MASK = 0x00c00000,
166 FSC_EPC_INBOUND = (1 << 6),
167 FSC_EPC_OUTBOUND = (1 << 7),
168 FSC_VM_PAGESIZE_MASK = 0x07000000,
169 FSC_VM_PAGE_2K = 0x00000100,
170 FSC_VM_PAGE_4K = 0x00000200,
171 FSC_VM_PAGE_8K = 0x00000300,
172 FSC_VM_PAGE_64K = 0x00000600,
173 FSC_SH = (1 << 11),
174 FSC_DSB = (1 << 12),
175 FSC_STE = (1 << 13),
176 FSC_FE = (1 << 15),
177};
178
179/*
180 * Host Command Status Register (CSR) bit definitions.
181 */
182enum {
183 CSR_ERR_STS_MASK = 0x0000003f,
184 /*
185 * There are no valued defined as of edit #15.
186 */
187 CSR_RR = (1 << 8),
188 CSR_HRI = (1 << 9),
189 CSR_RP = (1 << 10),
190 CSR_CMD_PARM_SHIFT = 22,
191 CSR_CMD_NOP = 0x00000000,
b82808b7 192 CSR_CMD_SET_RST = 0x10000000,
c4e84bde
RM		 193 CSR_CMD_CLR_RST = 0x20000000,
194 CSR_CMD_SET_PAUSE = 0x30000000,
195 CSR_CMD_CLR_PAUSE = 0x40000000,
196 CSR_CMD_SET_H2R_INT = 0x50000000,
197 CSR_CMD_CLR_H2R_INT = 0x60000000,
198 CSR_CMD_PAR_EN = 0x70000000,
199 CSR_CMD_SET_BAD_PAR = 0x80000000,
200 CSR_CMD_CLR_BAD_PAR = 0x90000000,
201 CSR_CMD_CLR_R2PCI_INT = 0xa0000000,
202};
203
204/*
205 * Configuration Register (CFG) bit definitions.
206 */
207enum {
208 CFG_LRQ = (1 << 0),
209 CFG_DRQ = (1 << 1),
210 CFG_LR = (1 << 2),
211 CFG_DR = (1 << 3),
212 CFG_LE = (1 << 5),
213 CFG_LCQ = (1 << 6),
214 CFG_DCQ = (1 << 7),
215 CFG_Q_SHIFT = 8,
216 CFG_Q_MASK = 0x7f000000,
217};
218
219/*
220 * Status Register (STS) bit definitions.
221 */
222enum {
223 STS_FE = (1 << 0),
224 STS_PI = (1 << 1),
225 STS_PL0 = (1 << 2),
226 STS_PL1 = (1 << 3),
227 STS_PI0 = (1 << 4),
228 STS_PI1 = (1 << 5),
229 STS_FUNC_ID_MASK = 0x000000c0,
230 STS_FUNC_ID_SHIFT = 6,
231 STS_F0E = (1 << 8),
232 STS_F1E = (1 << 9),
233 STS_F2E = (1 << 10),
234 STS_F3E = (1 << 11),
235 STS_NFE = (1 << 12),
236};
237
238/*
239 * Interrupt Enable Register (INTR_EN) bit definitions.
240 */
241enum {
242 INTR_EN_INTR_MASK = 0x007f0000,
243 INTR_EN_TYPE_MASK = 0x03000000,
244 INTR_EN_TYPE_ENABLE = 0x00000100,
245 INTR_EN_TYPE_DISABLE = 0x00000200,
246 INTR_EN_TYPE_READ = 0x00000300,
247 INTR_EN_IHD = (1 << 13),
248 INTR_EN_IHD_MASK = (INTR_EN_IHD << 16),
249 INTR_EN_EI = (1 << 14),
250 INTR_EN_EN = (1 << 15),
251};
252
253/*
254 * Interrupt Mask Register (INTR_MASK) bit definitions.
255 */
256enum {
257 INTR_MASK_PI = (1 << 0),
258 INTR_MASK_HL0 = (1 << 1),
259 INTR_MASK_LH0 = (1 << 2),
260 INTR_MASK_HL1 = (1 << 3),
261 INTR_MASK_LH1 = (1 << 4),
262 INTR_MASK_SE = (1 << 5),
263 INTR_MASK_LSC = (1 << 6),
264 INTR_MASK_MC = (1 << 7),
265 INTR_MASK_LINK_IRQS = INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC,
266};
267
268/*
269 * Register (REV_ID) bit definitions.
270 */
271enum {
272 REV_ID_MASK = 0x0000000f,
273 REV_ID_NICROLL_SHIFT = 0,
274 REV_ID_NICREV_SHIFT = 4,
275 REV_ID_XGROLL_SHIFT = 8,
276 REV_ID_XGREV_SHIFT = 12,
277 REV_ID_CHIPREV_SHIFT = 28,
278};
279
280/*
281 * Force ECC Error Register (FRC_ECC_ERR) bit definitions.
282 */
283enum {
284 FRC_ECC_ERR_VW = (1 << 12),
285 FRC_ECC_ERR_VB = (1 << 13),
286 FRC_ECC_ERR_NI = (1 << 14),
287 FRC_ECC_ERR_NO = (1 << 15),
288 FRC_ECC_PFE_SHIFT = 16,
289 FRC_ECC_ERR_DO = (1 << 18),
290 FRC_ECC_P14 = (1 << 19),
291};
292
293/*
294 * Error Status Register (ERR_STS) bit definitions.
295 */
296enum {
297 ERR_STS_NOF = (1 << 0),
298 ERR_STS_NIF = (1 << 1),
299 ERR_STS_DRP = (1 << 2),
300 ERR_STS_XGP = (1 << 3),
301 ERR_STS_FOU = (1 << 4),
302 ERR_STS_FOC = (1 << 5),
303 ERR_STS_FOF = (1 << 6),
304 ERR_STS_FIU = (1 << 7),
305 ERR_STS_FIC = (1 << 8),
306 ERR_STS_FIF = (1 << 9),
307 ERR_STS_MOF = (1 << 10),
308 ERR_STS_TA = (1 << 11),
309 ERR_STS_MA = (1 << 12),
310 ERR_STS_MPE = (1 << 13),
311 ERR_STS_SCE = (1 << 14),
312 ERR_STS_STE = (1 << 15),
313 ERR_STS_FOW = (1 << 16),
314 ERR_STS_UE = (1 << 17),
315 ERR_STS_MCH = (1 << 26),
316 ERR_STS_LOC_SHIFT = 27,
317};
318
319/*
320 * RAM Debug Address Register (RAM_DBG_ADDR) bit definitions.
321 */
322enum {
323 RAM_DBG_ADDR_FW = (1 << 30),
324 RAM_DBG_ADDR_FR = (1 << 31),
325};
326
327/*
328 * Semaphore Register (SEM) bit definitions.
329 */
330enum {
331 /*
332 * Example:
333 * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT)
334 */
335 SEM_CLEAR = 0,
336 SEM_SET = 1,
337 SEM_FORCE = 3,
338 SEM_XGMAC0_SHIFT = 0,
339 SEM_XGMAC1_SHIFT = 2,
340 SEM_ICB_SHIFT = 4,
341 SEM_MAC_ADDR_SHIFT = 6,
342 SEM_FLASH_SHIFT = 8,
343 SEM_PROBE_SHIFT = 10,
344 SEM_RT_IDX_SHIFT = 12,
345 SEM_PROC_REG_SHIFT = 14,
346 SEM_XGMAC0_MASK = 0x00030000,
347 SEM_XGMAC1_MASK = 0x000c0000,
348 SEM_ICB_MASK = 0x00300000,
349 SEM_MAC_ADDR_MASK = 0x00c00000,
350 SEM_FLASH_MASK = 0x03000000,
351 SEM_PROBE_MASK = 0x0c000000,
352 SEM_RT_IDX_MASK = 0x30000000,
353 SEM_PROC_REG_MASK = 0xc0000000,
354};
355
356/*
357 * 10G MAC Address Register (XGMAC_ADDR) bit definitions.
358 */
359enum {
360 XGMAC_ADDR_RDY = (1 << 31),
361 XGMAC_ADDR_R = (1 << 30),
362 XGMAC_ADDR_XME = (1 << 29),
363
364 /* XGMAC control registers */
365 PAUSE_SRC_LO = 0x00000100,
366 PAUSE_SRC_HI = 0x00000104,
367 GLOBAL_CFG = 0x00000108,
368 GLOBAL_CFG_RESET = (1 << 0),
369 GLOBAL_CFG_JUMBO = (1 << 6),
370 GLOBAL_CFG_TX_STAT_EN = (1 << 10),
371 GLOBAL_CFG_RX_STAT_EN = (1 << 11),
372 TX_CFG = 0x0000010c,
373 TX_CFG_RESET = (1 << 0),
374 TX_CFG_EN = (1 << 1),
375 TX_CFG_PREAM = (1 << 2),
376 RX_CFG = 0x00000110,
377 RX_CFG_RESET = (1 << 0),
378 RX_CFG_EN = (1 << 1),
379 RX_CFG_PREAM = (1 << 2),
380 FLOW_CTL = 0x0000011c,
381 PAUSE_OPCODE = 0x00000120,
382 PAUSE_TIMER = 0x00000124,
383 PAUSE_FRM_DEST_LO = 0x00000128,
384 PAUSE_FRM_DEST_HI = 0x0000012c,
385 MAC_TX_PARAMS = 0x00000134,
386 MAC_TX_PARAMS_JUMBO = (1 << 31),
387 MAC_TX_PARAMS_SIZE_SHIFT = 16,
388 MAC_RX_PARAMS = 0x00000138,
389 MAC_SYS_INT = 0x00000144,
390 MAC_SYS_INT_MASK = 0x00000148,
391 MAC_MGMT_INT = 0x0000014c,
392 MAC_MGMT_IN_MASK = 0x00000150,
393 EXT_ARB_MODE = 0x000001fc,
394
395 /* XGMAC TX statistics registers */
396 TX_PKTS = 0x00000200,
397 TX_BYTES = 0x00000208,
398 TX_MCAST_PKTS = 0x00000210,
399 TX_BCAST_PKTS = 0x00000218,
400 TX_UCAST_PKTS = 0x00000220,
401 TX_CTL_PKTS = 0x00000228,
402 TX_PAUSE_PKTS = 0x00000230,
403 TX_64_PKT = 0x00000238,
404 TX_65_TO_127_PKT = 0x00000240,
405 TX_128_TO_255_PKT = 0x00000248,
406 TX_256_511_PKT = 0x00000250,
407 TX_512_TO_1023_PKT = 0x00000258,
408 TX_1024_TO_1518_PKT = 0x00000260,
409 TX_1519_TO_MAX_PKT = 0x00000268,
410 TX_UNDERSIZE_PKT = 0x00000270,
411 TX_OVERSIZE_PKT = 0x00000278,
412
413 /* XGMAC statistics control registers */
414 RX_HALF_FULL_DET = 0x000002a0,
415 TX_HALF_FULL_DET = 0x000002a4,
416 RX_OVERFLOW_DET = 0x000002a8,
417 TX_OVERFLOW_DET = 0x000002ac,
418 RX_HALF_FULL_MASK = 0x000002b0,
419 TX_HALF_FULL_MASK = 0x000002b4,
420 RX_OVERFLOW_MASK = 0x000002b8,
421 TX_OVERFLOW_MASK = 0x000002bc,
422 STAT_CNT_CTL = 0x000002c0,
423 STAT_CNT_CTL_CLEAR_TX = (1 << 0),
424 STAT_CNT_CTL_CLEAR_RX = (1 << 1),
425 AUX_RX_HALF_FULL_DET = 0x000002d0,
426 AUX_TX_HALF_FULL_DET = 0x000002d4,
427 AUX_RX_OVERFLOW_DET = 0x000002d8,
428 AUX_TX_OVERFLOW_DET = 0x000002dc,
429 AUX_RX_HALF_FULL_MASK = 0x000002f0,
430 AUX_TX_HALF_FULL_MASK = 0x000002f4,
431 AUX_RX_OVERFLOW_MASK = 0x000002f8,
432 AUX_TX_OVERFLOW_MASK = 0x000002fc,
433
434 /* XGMAC RX statistics registers */
435 RX_BYTES = 0x00000300,
436 RX_BYTES_OK = 0x00000308,
437 RX_PKTS = 0x00000310,
438 RX_PKTS_OK = 0x00000318,
439 RX_BCAST_PKTS = 0x00000320,
440 RX_MCAST_PKTS = 0x00000328,
441 RX_UCAST_PKTS = 0x00000330,
442 RX_UNDERSIZE_PKTS = 0x00000338,
443 RX_OVERSIZE_PKTS = 0x00000340,
444 RX_JABBER_PKTS = 0x00000348,
445 RX_UNDERSIZE_FCERR_PKTS = 0x00000350,
446 RX_DROP_EVENTS = 0x00000358,
447 RX_FCERR_PKTS = 0x00000360,
448 RX_ALIGN_ERR = 0x00000368,
449 RX_SYMBOL_ERR = 0x00000370,
450 RX_MAC_ERR = 0x00000378,
451 RX_CTL_PKTS = 0x00000380,
b82808b7 452 RX_PAUSE_PKTS = 0x00000388,
c4e84bde
RM		 453 RX_64_PKTS = 0x00000390,
454 RX_65_TO_127_PKTS = 0x00000398,
455 RX_128_255_PKTS = 0x000003a0,
456 RX_256_511_PKTS = 0x000003a8,
457 RX_512_TO_1023_PKTS = 0x000003b0,
458 RX_1024_TO_1518_PKTS = 0x000003b8,
459 RX_1519_TO_MAX_PKTS = 0x000003c0,
460 RX_LEN_ERR_PKTS = 0x000003c8,
461
462 /* XGMAC MDIO control registers */
463 MDIO_TX_DATA = 0x00000400,
464 MDIO_RX_DATA = 0x00000410,
465 MDIO_CMD = 0x00000420,
466 MDIO_PHY_ADDR = 0x00000430,
467 MDIO_PORT = 0x00000440,
468 MDIO_STATUS = 0x00000450,
469
470 /* XGMAC AUX statistics registers */
471};
472
473/*
474 * Enhanced Transmission Schedule Registers (NIC_ETS,CNA_ETS) bit definitions.
475 */
476enum {
477 ETS_QUEUE_SHIFT = 29,
478 ETS_REF = (1 << 26),
479 ETS_RS = (1 << 27),
480 ETS_P = (1 << 28),
481 ETS_FC_COS_SHIFT = 23,
482};
483
484/*
485 * Flash Address Register (FLASH_ADDR) bit definitions.
486 */
487enum {
488 FLASH_ADDR_RDY = (1 << 31),
489 FLASH_ADDR_R = (1 << 30),
490 FLASH_ADDR_ERR = (1 << 29),
491};
492
493/*
494 * Stop CQ Processing Register (CQ_STOP) bit definitions.
495 */
496enum {
497 CQ_STOP_QUEUE_MASK = (0x007f0000),
498 CQ_STOP_TYPE_MASK = (0x03000000),
499 CQ_STOP_TYPE_START = 0x00000100,
500 CQ_STOP_TYPE_STOP = 0x00000200,
501 CQ_STOP_TYPE_READ = 0x00000300,
502 CQ_STOP_EN = (1 << 15),
503};
504
505/*
506 * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions.
507 */
508enum {
509 MAC_ADDR_IDX_SHIFT = 4,
510 MAC_ADDR_TYPE_SHIFT = 16,
511 MAC_ADDR_TYPE_MASK = 0x000f0000,
512 MAC_ADDR_TYPE_CAM_MAC = 0x00000000,
513 MAC_ADDR_TYPE_MULTI_MAC = 0x00010000,
514 MAC_ADDR_TYPE_VLAN = 0x00020000,
515 MAC_ADDR_TYPE_MULTI_FLTR = 0x00030000,
516 MAC_ADDR_TYPE_FC_MAC = 0x00040000,
517 MAC_ADDR_TYPE_MGMT_MAC = 0x00050000,
518 MAC_ADDR_TYPE_MGMT_VLAN = 0x00060000,
519 MAC_ADDR_TYPE_MGMT_V4 = 0x00070000,
520 MAC_ADDR_TYPE_MGMT_V6 = 0x00080000,
521 MAC_ADDR_TYPE_MGMT_TU_DP = 0x00090000,
522 MAC_ADDR_ADR = (1 << 25),
523 MAC_ADDR_RS = (1 << 26),
524 MAC_ADDR_E = (1 << 27),
525 MAC_ADDR_MR = (1 << 30),
526 MAC_ADDR_MW = (1 << 31),
527 MAX_MULTICAST_ENTRIES = 32,
528};
529
530/*
531 * MAC Protocol Address Index Register (SPLT_HDR) bit definitions.
532 */
533enum {
534 SPLT_HDR_EP = (1 << 31),
535};
536
537/*
538 * FCoE Receive Configuration Register (FC_RCV_CFG) bit definitions.
539 */
540enum {
541 FC_RCV_CFG_ECT = (1 << 15),
542 FC_RCV_CFG_DFH = (1 << 20),
543 FC_RCV_CFG_DVF = (1 << 21),
544 FC_RCV_CFG_RCE = (1 << 27),
545 FC_RCV_CFG_RFE = (1 << 28),
546 FC_RCV_CFG_TEE = (1 << 29),
547 FC_RCV_CFG_TCE = (1 << 30),
548 FC_RCV_CFG_TFE = (1 << 31),
549};
550
551/*
552 * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions.
553 */
554enum {
555 NIC_RCV_CFG_PPE = (1 << 0),
556 NIC_RCV_CFG_VLAN_MASK = 0x00060000,
557 NIC_RCV_CFG_VLAN_ALL = 0x00000000,
558 NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002,
559 NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004,
560 NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006,
561 NIC_RCV_CFG_RV = (1 << 3),
562 NIC_RCV_CFG_DFQ_MASK = (0x7f000000),
563 NIC_RCV_CFG_DFQ_SHIFT = 8,
564 NIC_RCV_CFG_DFQ = 0, /* HARDCODE default queue to 0. */
565};
566
567/*
568 * Mgmt Receive Configuration Register (MGMT_RCV_CFG) bit definitions.
569 */
570enum {
571 MGMT_RCV_CFG_ARP = (1 << 0),
572 MGMT_RCV_CFG_DHC = (1 << 1),
573 MGMT_RCV_CFG_DHS = (1 << 2),
574 MGMT_RCV_CFG_NP = (1 << 3),
575 MGMT_RCV_CFG_I6N = (1 << 4),
576 MGMT_RCV_CFG_I6R = (1 << 5),
577 MGMT_RCV_CFG_DH6 = (1 << 6),
578 MGMT_RCV_CFG_UD1 = (1 << 7),
579 MGMT_RCV_CFG_UD0 = (1 << 8),
580 MGMT_RCV_CFG_BCT = (1 << 9),
581 MGMT_RCV_CFG_MCT = (1 << 10),
582 MGMT_RCV_CFG_DM = (1 << 11),
583 MGMT_RCV_CFG_RM = (1 << 12),
584 MGMT_RCV_CFG_STL = (1 << 13),
585 MGMT_RCV_CFG_VLAN_MASK = 0xc0000000,
586 MGMT_RCV_CFG_VLAN_ALL = 0x00000000,
587 MGMT_RCV_CFG_VLAN_MATCH_ONLY = 0x00004000,
588 MGMT_RCV_CFG_VLAN_MATCH_AND_NON = 0x00008000,
589 MGMT_RCV_CFG_VLAN_NONE_AND_NON = 0x0000c000,
590};
591
592/*
593 * Routing Index Register (RT_IDX) bit definitions.
594 */
595enum {
596 RT_IDX_IDX_SHIFT = 8,
597 RT_IDX_TYPE_MASK = 0x000f0000,
598 RT_IDX_TYPE_RT = 0x00000000,
599 RT_IDX_TYPE_RT_INV = 0x00010000,
600 RT_IDX_TYPE_NICQ = 0x00020000,
601 RT_IDX_TYPE_NICQ_INV = 0x00030000,
602 RT_IDX_DST_MASK = 0x00700000,
603 RT_IDX_DST_RSS = 0x00000000,
604 RT_IDX_DST_CAM_Q = 0x00100000,
605 RT_IDX_DST_COS_Q = 0x00200000,
606 RT_IDX_DST_DFLT_Q = 0x00300000,
607 RT_IDX_DST_DEST_Q = 0x00400000,
608 RT_IDX_RS = (1 << 26),
609 RT_IDX_E = (1 << 27),
610 RT_IDX_MR = (1 << 30),
611 RT_IDX_MW = (1 << 31),
612
613 /* Nic Queue format - type 2 bits */
614 RT_IDX_BCAST = (1 << 0),
615 RT_IDX_MCAST = (1 << 1),
616 RT_IDX_MCAST_MATCH = (1 << 2),
617 RT_IDX_MCAST_REG_MATCH = (1 << 3),
618 RT_IDX_MCAST_HASH_MATCH = (1 << 4),
619 RT_IDX_FC_MACH = (1 << 5),
620 RT_IDX_ETH_FCOE = (1 << 6),
621 RT_IDX_CAM_HIT = (1 << 7),
622 RT_IDX_CAM_BIT0 = (1 << 8),
623 RT_IDX_CAM_BIT1 = (1 << 9),
624 RT_IDX_VLAN_TAG = (1 << 10),
625 RT_IDX_VLAN_MATCH = (1 << 11),
626 RT_IDX_VLAN_FILTER = (1 << 12),
627 RT_IDX_ETH_SKIP1 = (1 << 13),
628 RT_IDX_ETH_SKIP2 = (1 << 14),
629 RT_IDX_BCAST_MCAST_MATCH = (1 << 15),
630 RT_IDX_802_3 = (1 << 16),
631 RT_IDX_LLDP = (1 << 17),
632 RT_IDX_UNUSED018 = (1 << 18),
633 RT_IDX_UNUSED019 = (1 << 19),
634 RT_IDX_UNUSED20 = (1 << 20),
635 RT_IDX_UNUSED21 = (1 << 21),
636 RT_IDX_ERR = (1 << 22),
637 RT_IDX_VALID = (1 << 23),
638 RT_IDX_TU_CSUM_ERR = (1 << 24),
639 RT_IDX_IP_CSUM_ERR = (1 << 25),
640 RT_IDX_MAC_ERR = (1 << 26),
641 RT_IDX_RSS_TCP6 = (1 << 27),
642 RT_IDX_RSS_TCP4 = (1 << 28),
643 RT_IDX_RSS_IPV6 = (1 << 29),
644 RT_IDX_RSS_IPV4 = (1 << 30),
645 RT_IDX_RSS_MATCH = (1 << 31),
646
647 /* Hierarchy for the NIC Queue Mask */
648 RT_IDX_ALL_ERR_SLOT = 0,
649 RT_IDX_MAC_ERR_SLOT = 0,
650 RT_IDX_IP_CSUM_ERR_SLOT = 1,
651 RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2,
652 RT_IDX_BCAST_SLOT = 3,
653 RT_IDX_MCAST_MATCH_SLOT = 4,
654 RT_IDX_ALLMULTI_SLOT = 5,
655 RT_IDX_UNUSED6_SLOT = 6,
656 RT_IDX_UNUSED7_SLOT = 7,
657 RT_IDX_RSS_MATCH_SLOT = 8,
658 RT_IDX_RSS_IPV4_SLOT = 8,
659 RT_IDX_RSS_IPV6_SLOT = 9,
660 RT_IDX_RSS_TCP4_SLOT = 10,
661 RT_IDX_RSS_TCP6_SLOT = 11,
662 RT_IDX_CAM_HIT_SLOT = 12,
663 RT_IDX_UNUSED013 = 13,
664 RT_IDX_UNUSED014 = 14,
665 RT_IDX_PROMISCUOUS_SLOT = 15,
666 RT_IDX_MAX_SLOTS = 16,
667};
668
669/*
670 * Control Register Set Map
671 */
672enum {
673 PROC_ADDR = 0, /* Use semaphore */
674 PROC_DATA = 0x04, /* Use semaphore */
675 SYS = 0x08,
676 RST_FO = 0x0c,
677 FSC = 0x10,
678 CSR = 0x14,
679 LED = 0x18,
680 ICB_RID = 0x1c, /* Use semaphore */
681 ICB_L = 0x20, /* Use semaphore */
682 ICB_H = 0x24, /* Use semaphore */
683 CFG = 0x28,
684 BIOS_ADDR = 0x2c,
685 STS = 0x30,
686 INTR_EN = 0x34,
687 INTR_MASK = 0x38,
688 ISR1 = 0x3c,
689 ISR2 = 0x40,
690 ISR3 = 0x44,
691 ISR4 = 0x48,
692 REV_ID = 0x4c,
693 FRC_ECC_ERR = 0x50,
694 ERR_STS = 0x54,
695 RAM_DBG_ADDR = 0x58,
696 RAM_DBG_DATA = 0x5c,
697 ECC_ERR_CNT = 0x60,
698 SEM = 0x64,
699 GPIO_1 = 0x68, /* Use semaphore */
700 GPIO_2 = 0x6c, /* Use semaphore */
701 GPIO_3 = 0x70, /* Use semaphore */
702 RSVD2 = 0x74,
703 XGMAC_ADDR = 0x78, /* Use semaphore */
704 XGMAC_DATA = 0x7c, /* Use semaphore */
705 NIC_ETS = 0x80,
706 CNA_ETS = 0x84,
707 FLASH_ADDR = 0x88, /* Use semaphore */
708 FLASH_DATA = 0x8c, /* Use semaphore */
709 CQ_STOP = 0x90,
710 PAGE_TBL_RID = 0x94,
711 WQ_PAGE_TBL_LO = 0x98,
712 WQ_PAGE_TBL_HI = 0x9c,
713 CQ_PAGE_TBL_LO = 0xa0,
714 CQ_PAGE_TBL_HI = 0xa4,
715 MAC_ADDR_IDX = 0xa8, /* Use semaphore */
716 MAC_ADDR_DATA = 0xac, /* Use semaphore */
717 COS_DFLT_CQ1 = 0xb0,
718 COS_DFLT_CQ2 = 0xb4,
719 ETYPE_SKIP1 = 0xb8,
720 ETYPE_SKIP2 = 0xbc,
721 SPLT_HDR = 0xc0,
722 FC_PAUSE_THRES = 0xc4,
723 NIC_PAUSE_THRES = 0xc8,
724 FC_ETHERTYPE = 0xcc,
725 FC_RCV_CFG = 0xd0,
726 NIC_RCV_CFG = 0xd4,
727 FC_COS_TAGS = 0xd8,
728 NIC_COS_TAGS = 0xdc,
729 MGMT_RCV_CFG = 0xe0,
730 RT_IDX = 0xe4,
731 RT_DATA = 0xe8,
732 RSVD7 = 0xec,
733 XG_SERDES_ADDR = 0xf0,
734 XG_SERDES_DATA = 0xf4,
735 PRB_MX_ADDR = 0xf8, /* Use semaphore */
736 PRB_MX_DATA = 0xfc, /* Use semaphore */
737};
738
739/*
740 * CAM output format.
741 */
742enum {
743 CAM_OUT_ROUTE_FC = 0,
744 CAM_OUT_ROUTE_NIC = 1,
745 CAM_OUT_FUNC_SHIFT = 2,
746 CAM_OUT_RV = (1 << 4),
747 CAM_OUT_SH = (1 << 15),
748 CAM_OUT_CQ_ID_SHIFT = 5,
749};
750
751/*
752 * Mailbox definitions
753 */
754enum {
755 /* Asynchronous Event Notifications */
756 AEN_SYS_ERR = 0x00008002,
757 AEN_LINK_UP = 0x00008011,
758 AEN_LINK_DOWN = 0x00008012,
759 AEN_IDC_CMPLT = 0x00008100,
760 AEN_IDC_REQ = 0x00008101,
b82808b7
RM		 761 AEN_IDC_EXT = 0x00008102,
762 AEN_DCBX_CHG = 0x00008110,
763 AEN_AEN_LOST = 0x00008120,
764 AEN_AEN_SFP_IN = 0x00008130,
765 AEN_AEN_SFP_OUT = 0x00008131,
c4e84bde
RM		 766 AEN_FW_INIT_DONE = 0x00008400,
767 AEN_FW_INIT_FAIL = 0x00008401,
768
769 /* Mailbox Command Opcodes. */
770 MB_CMD_NOP = 0x00000000,
771 MB_CMD_EX_FW = 0x00000002,
772 MB_CMD_MB_TEST = 0x00000006,
773 MB_CMD_CSUM_TEST = 0x00000007, /* Verify Checksum */
774 MB_CMD_ABOUT_FW = 0x00000008,
b82808b7 775 MB_CMD_COPY_RISC_RAM = 0x0000000a,
c4e84bde
RM		 776 MB_CMD_LOAD_RISC_RAM = 0x0000000b,
777 MB_CMD_DUMP_RISC_RAM = 0x0000000c,
778 MB_CMD_WRITE_RAM = 0x0000000d,
b82808b7 779 MB_CMD_INIT_RISC_RAM = 0x0000000e,
c4e84bde
RM		 780 MB_CMD_READ_RAM = 0x0000000f,
781 MB_CMD_STOP_FW = 0x00000014,
782 MB_CMD_MAKE_SYS_ERR = 0x0000002a,
b82808b7
RM		 783 MB_CMD_WRITE_SFP = 0x00000030,
784 MB_CMD_READ_SFP = 0x00000031,
c4e84bde 785 MB_CMD_INIT_FW = 0x00000060,
b82808b7 786 MB_CMD_GET_IFCB = 0x00000061,
c4e84bde
RM		 787 MB_CMD_GET_FW_STATE = 0x00000069,
788 MB_CMD_IDC_REQ = 0x00000100, /* Inter-Driver Communication */
789 MB_CMD_IDC_ACK = 0x00000101, /* Inter-Driver Communication */
790 MB_CMD_SET_WOL_MODE = 0x00000110, /* Wake On Lan */
b82808b7
RM		 791 MB_WOL_DISABLE = 0,
792 MB_WOL_MAGIC_PKT = (1 << 1),
793 MB_WOL_FLTR = (1 << 2),
794 MB_WOL_UCAST = (1 << 3),
795 MB_WOL_MCAST = (1 << 4),
796 MB_WOL_BCAST = (1 << 5),
797 MB_WOL_LINK_UP = (1 << 6),
798 MB_WOL_LINK_DOWN = (1 << 7),
c4e84bde 799 MB_CMD_SET_WOL_FLTR = 0x00000111, /* Wake On Lan Filter */
b82808b7 800 MB_CMD_CLEAR_WOL_FLTR = 0x00000112, /* Wake On Lan Filter */
c4e84bde 801 MB_CMD_SET_WOL_MAGIC = 0x00000113, /* Wake On Lan Magic Packet */
b82808b7
RM		 802 MB_CMD_CLEAR_WOL_MAGIC = 0x00000114,/* Wake On Lan Magic Packet */
803 MB_CMD_SET_WOL_IMMED = 0x00000115,
c4e84bde
RM		 804 MB_CMD_PORT_RESET = 0x00000120,
805 MB_CMD_SET_PORT_CFG = 0x00000122,
806 MB_CMD_GET_PORT_CFG = 0x00000123,
b82808b7 807 MB_CMD_GET_LINK_STS = 0x00000124,
84087f4d
RM		 808 MB_CMD_SET_MGMNT_TFK_CTL = 0x00000160, /* Set Mgmnt Traffic Control */
809 MB_SET_MPI_TFK_STOP = (1 << 0),
810 MB_SET_MPI_TFK_RESUME = (1 << 1),
811 MB_CMD_GET_MGMNT_TFK_CTL = 0x00000161, /* Get Mgmnt Traffic Control */
812 MB_GET_MPI_TFK_STOPPED = (1 << 0),
813 MB_GET_MPI_TFK_FIFO_EMPTY = (1 << 1),
c4e84bde
RM		 814
815 /* Mailbox Command Status. */
816 MB_CMD_STS_GOOD = 0x00004000, /* Success. */
817 MB_CMD_STS_INTRMDT = 0x00001000, /* Intermediate Complete. */
b82808b7
RM		 818 MB_CMD_STS_INVLD_CMD = 0x00004001, /* Invalid. */
819 MB_CMD_STS_XFC_ERR = 0x00004002, /* Interface Error. */
820 MB_CMD_STS_CSUM_ERR = 0x00004003, /* Csum Error. */
821 MB_CMD_STS_ERR = 0x00004005, /* System Error. */
822 MB_CMD_STS_PARAM_ERR = 0x00004006, /* Parameter Error. */
c4e84bde
RM		 823};
824
825struct mbox_params {
826 u32 mbox_in[MAILBOX_COUNT];
827 u32 mbox_out[MAILBOX_COUNT];
828 int in_count;
829 int out_count;
830};
831
b0c2aadf 832struct flash_params_8012 {
c4e84bde 833 u8 dev_id_str[4];
26351479
RM		 834 __le16 size;
835 __le16 csum;
836 __le16 ver;
837 __le16 sub_dev_id;
c4e84bde 838 u8 mac_addr[6];
26351479 839 __le16 res;
c4e84bde
RM		 840};
841
cdca8d02
RM		 842/* 8000 device's flash is a different structure
843 * at a different offset in flash.
844 */
845#define FUNC0_FLASH_OFFSET 0x140200
846#define FUNC1_FLASH_OFFSET 0x140600
847
848/* Flash related data structures. */
849struct flash_params_8000 {
850 u8 dev_id_str[4]; /* "8000" */
851 __le16 ver;
852 __le16 size;
853 __le16 csum;
854 __le16 reserved0;
855 __le16 total_size;
856 __le16 entry_count;
857 u8 data_type0;
858 u8 data_size0;
859 u8 mac_addr[6];
860 u8 data_type1;
861 u8 data_size1;
862 u8 mac_addr1[6];
863 u8 data_type2;
864 u8 data_size2;
865 __le16 vlan_id;
866 u8 data_type3;
867 u8 data_size3;
868 __le16 last;
869 u8 reserved1[464];
870 __le16 subsys_ven_id;
871 __le16 subsys_dev_id;
872 u8 reserved2[4];
873};
874
b0c2aadf
RM		 875union flash_params {
876 struct flash_params_8012 flash_params_8012;
cdca8d02 877 struct flash_params_8000 flash_params_8000;
b0c2aadf 878};
c4e84bde
RM		 879
880/*
881 * doorbell space for the rx ring context
882 */
883struct rx_doorbell_context {
884 u32 cnsmr_idx; /* 0x00 */
885 u32 valid; /* 0x04 */
886 u32 reserved[4]; /* 0x08-0x14 */
887 u32 lbq_prod_idx; /* 0x18 */
888 u32 sbq_prod_idx; /* 0x1c */
889};
890
891/*
892 * doorbell space for the tx ring context
893 */
894struct tx_doorbell_context {
895 u32 prod_idx; /* 0x00 */
896 u32 valid; /* 0x04 */
897 u32 reserved[4]; /* 0x08-0x14 */
898 u32 lbq_prod_idx; /* 0x18 */
899 u32 sbq_prod_idx; /* 0x1c */
900};
901
902/* DATA STRUCTURES SHARED WITH HARDWARE. */
c4e84bde
RM		 903struct tx_buf_desc {
904 __le64 addr;
905 __le32 len;
906#define TX_DESC_LEN_MASK 0x000fffff
907#define TX_DESC_C 0x40000000
908#define TX_DESC_E 0x80000000
909} __attribute((packed));
910
911/*
912 * IOCB Definitions...
913 */
914
915#define OPCODE_OB_MAC_IOCB 0x01
916#define OPCODE_OB_MAC_TSO_IOCB 0x02
917#define OPCODE_IB_MAC_IOCB 0x20
918#define OPCODE_IB_MPI_IOCB 0x21
919#define OPCODE_IB_AE_IOCB 0x3f
920
921struct ob_mac_iocb_req {
922 u8 opcode;
923 u8 flags1;
924#define OB_MAC_IOCB_REQ_OI 0x01
925#define OB_MAC_IOCB_REQ_I 0x02
926#define OB_MAC_IOCB_REQ_D 0x08
927#define OB_MAC_IOCB_REQ_F 0x10
928 u8 flags2;
929 u8 flags3;
930#define OB_MAC_IOCB_DFP 0x02
931#define OB_MAC_IOCB_V 0x04
932 __le32 reserved1[2];
933 __le16 frame_len;
934#define OB_MAC_IOCB_LEN_MASK 0x3ffff
935 __le16 reserved2;
3537d54c
RM		 936 u32 tid;
937 u32 txq_idx;
c4e84bde
RM		 938 __le32 reserved3;
939 __le16 vlan_tci;
940 __le16 reserved4;
941 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
942} __attribute((packed));
943
944struct ob_mac_iocb_rsp {
945 u8 opcode; /* */
946 u8 flags1; /* */
947#define OB_MAC_IOCB_RSP_OI 0x01 /* */
948#define OB_MAC_IOCB_RSP_I 0x02 /* */
949#define OB_MAC_IOCB_RSP_E 0x08 /* */
950#define OB_MAC_IOCB_RSP_S 0x10 /* too Short */
951#define OB_MAC_IOCB_RSP_L 0x20 /* too Large */
952#define OB_MAC_IOCB_RSP_P 0x40 /* Padded */
953 u8 flags2; /* */
954 u8 flags3; /* */
955#define OB_MAC_IOCB_RSP_B 0x80 /* */
3537d54c
RM		 956 u32 tid;
957 u32 txq_idx;
c4e84bde
RM		 958 __le32 reserved[13];
959} __attribute((packed));
960
961struct ob_mac_tso_iocb_req {
962 u8 opcode;
963 u8 flags1;
964#define OB_MAC_TSO_IOCB_OI 0x01
965#define OB_MAC_TSO_IOCB_I 0x02
966#define OB_MAC_TSO_IOCB_D 0x08
967#define OB_MAC_TSO_IOCB_IP4 0x40
968#define OB_MAC_TSO_IOCB_IP6 0x80
969 u8 flags2;
970#define OB_MAC_TSO_IOCB_LSO 0x20
971#define OB_MAC_TSO_IOCB_UC 0x40
972#define OB_MAC_TSO_IOCB_TC 0x80
973 u8 flags3;
974#define OB_MAC_TSO_IOCB_IC 0x01
975#define OB_MAC_TSO_IOCB_DFP 0x02
976#define OB_MAC_TSO_IOCB_V 0x04
977 __le32 reserved1[2];
978 __le32 frame_len;
3537d54c
RM		 979 u32 tid;
980 u32 txq_idx;
c4e84bde
RM		 981 __le16 total_hdrs_len;
982 __le16 net_trans_offset;
983#define OB_MAC_TRANSPORT_HDR_SHIFT 6
984 __le16 vlan_tci;
985 __le16 mss;
986 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
987} __attribute((packed));
988
989struct ob_mac_tso_iocb_rsp {
990 u8 opcode;
991 u8 flags1;
992#define OB_MAC_TSO_IOCB_RSP_OI 0x01
993#define OB_MAC_TSO_IOCB_RSP_I 0x02
994#define OB_MAC_TSO_IOCB_RSP_E 0x08
995#define OB_MAC_TSO_IOCB_RSP_S 0x10
996#define OB_MAC_TSO_IOCB_RSP_L 0x20
997#define OB_MAC_TSO_IOCB_RSP_P 0x40
998 u8 flags2; /* */
999 u8 flags3; /* */
1000#define OB_MAC_TSO_IOCB_RSP_B 0x8000
3537d54c
RM		 1001 u32 tid;
1002 u32 txq_idx;
c4e84bde
RM		 1003 __le32 reserved2[13];
1004} __attribute((packed));
1005
1006struct ib_mac_iocb_rsp {
1007 u8 opcode; /* 0x20 */
1008 u8 flags1;
1009#define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */
1010#define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */
d555f592 1011#define IB_MAC_CSUM_ERR_MASK 0x1c /* A mask to use for csum errs */
c4e84bde
RM		 1012#define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */
1013#define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */
1014#define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */
1015#define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */
1016#define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */
1017#define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */
1018#define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */
1019#define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */
1020#define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */
1021 u8 flags2;
1022#define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */
1023#define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */
1024#define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */
1025#define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04
1026#define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08
1027#define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10
1028#define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14
1029#define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18
1030#define IB_MAC_IOCB_RSP_ERR_CRC 0x1c
1031#define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */
1032#define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */
1033#define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */
1034 u8 flags3;
1035#define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */
1036#define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */
1037#define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */
1038#define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */
1039#define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */
1040#define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */
1041#define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */
1042#define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */
1043#define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */
1044#define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */
1045#define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */
1046 __le32 data_len; /* */
97345524 1047 __le64 data_addr; /* */
c4e84bde
RM		 1048 __le32 rss; /* */
1049 __le16 vlan_id; /* 12 bits */
1050#define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */
1051#define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */
b82808b7 1052#define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff
c4e84bde
RM		 1053
1054 __le16 reserved1;
1055 __le32 reserved2[6];
a303ce09
RM		 1056 u8 reserved3[3];
1057 u8 flags4;
1058#define IB_MAC_IOCB_RSP_HV 0x20
1059#define IB_MAC_IOCB_RSP_HS 0x40
1060#define IB_MAC_IOCB_RSP_HL 0x80
c4e84bde 1061 __le32 hdr_len; /* */
97345524 1062 __le64 hdr_addr; /* */
c4e84bde
RM		 1063} __attribute((packed));
1064
1065struct ib_ae_iocb_rsp {
1066 u8 opcode;
1067 u8 flags1;
1068#define IB_AE_IOCB_RSP_OI 0x01
1069#define IB_AE_IOCB_RSP_I 0x02
1070 u8 event;
1071#define LINK_UP_EVENT 0x00
1072#define LINK_DOWN_EVENT 0x01
1073#define CAM_LOOKUP_ERR_EVENT 0x06
1074#define SOFT_ECC_ERROR_EVENT 0x07
1075#define MGMT_ERR_EVENT 0x08
1076#define TEN_GIG_MAC_EVENT 0x09
1077#define GPI0_H2L_EVENT 0x10
1078#define GPI0_L2H_EVENT 0x20
1079#define GPI1_H2L_EVENT 0x11
1080#define GPI1_L2H_EVENT 0x21
1081#define PCI_ERR_ANON_BUF_RD 0x40
1082 u8 q_id;
1083 __le32 reserved[15];
1084} __attribute((packed));
1085
1086/*
1087 * These three structures are for generic
1088 * handling of ib and ob iocbs.
1089 */
1090struct ql_net_rsp_iocb {
1091 u8 opcode;
1092 u8 flags0;
1093 __le16 length;
1094 __le32 tid;
1095 __le32 reserved[14];
1096} __attribute((packed));
1097
1098struct net_req_iocb {
1099 u8 opcode;
1100 u8 flags0;
1101 __le16 flags1;
1102 __le32 tid;
1103 __le32 reserved1[30];
1104} __attribute((packed));
1105
1106/*
1107 * tx ring initialization control block for chip.
1108 * It is defined as:
1109 * "Work Queue Initialization Control Block"
1110 */
1111struct wqicb {
1112 __le16 len;
1113#define Q_LEN_V (1 << 4)
1114#define Q_LEN_CPP_CONT 0x0000
1115#define Q_LEN_CPP_16 0x0001
1116#define Q_LEN_CPP_32 0x0002
1117#define Q_LEN_CPP_64 0x0003
b82808b7 1118#define Q_LEN_CPP_512 0x0006
c4e84bde
RM		 1119 __le16 flags;
1120#define Q_PRI_SHIFT 1
1121#define Q_FLAGS_LC 0x1000
1122#define Q_FLAGS_LB 0x2000
1123#define Q_FLAGS_LI 0x4000
1124#define Q_FLAGS_LO 0x8000
1125 __le16 cq_id_rss;
1126#define Q_CQ_ID_RSS_RV 0x8000
1127 __le16 rid;
97345524
RM		 1128 __le64 addr;
1129 __le64 cnsmr_idx_addr;
c4e84bde
RM		 1130} __attribute((packed));
1131
1132/*
1133 * rx ring initialization control block for chip.
1134 * It is defined as:
1135 * "Completion Queue Initialization Control Block"
1136 */
1137struct cqicb {
1138 u8 msix_vect;
1139 u8 reserved1;
1140 u8 reserved2;
1141 u8 flags;
1142#define FLAGS_LV 0x08
1143#define FLAGS_LS 0x10
1144#define FLAGS_LL 0x20
1145#define FLAGS_LI 0x40
1146#define FLAGS_LC 0x80
1147 __le16 len;
1148#define LEN_V (1 << 4)
1149#define LEN_CPP_CONT 0x0000
1150#define LEN_CPP_32 0x0001
1151#define LEN_CPP_64 0x0002
1152#define LEN_CPP_128 0x0003
1153 __le16 rid;
97345524
RM		 1154 __le64 addr;
1155 __le64 prod_idx_addr;
c4e84bde
RM		 1156 __le16 pkt_delay;
1157 __le16 irq_delay;
97345524 1158 __le64 lbq_addr;
c4e84bde
RM		 1159 __le16 lbq_buf_size;
1160 __le16 lbq_len; /* entry count */
97345524 1161 __le64 sbq_addr;
c4e84bde
RM		 1162 __le16 sbq_buf_size;
1163 __le16 sbq_len; /* entry count */
1164} __attribute((packed));
1165
1166struct ricb {
1167 u8 base_cq;
1168#define RSS_L4K 0x80
1169 u8 flags;
1170#define RSS_L6K 0x01
1171#define RSS_LI 0x02
1172#define RSS_LB 0x04
1173#define RSS_LM 0x08
1174#define RSS_RI4 0x10
1175#define RSS_RT4 0x20
1176#define RSS_RI6 0x40
1177#define RSS_RT6 0x80
1178 __le16 mask;
541ae28c 1179 u8 hash_cq_id[1024];
c4e84bde
RM		 1180 __le32 ipv6_hash_key[10];
1181 __le32 ipv4_hash_key[4];
1182} __attribute((packed));
1183
1184/* SOFTWARE/DRIVER DATA STRUCTURES. */
1185
1186struct oal {
1187 struct tx_buf_desc oal[TX_DESC_PER_OAL];
1188};
1189
1190struct map_list {
1191 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1192 DECLARE_PCI_UNMAP_LEN(maplen);
1193};
1194
1195struct tx_ring_desc {
1196 struct sk_buff *skb;
1197 struct ob_mac_iocb_req *queue_entry;
3537d54c 1198 u32 index;
c4e84bde
RM		 1199 struct oal oal;
1200 struct map_list map[MAX_SKB_FRAGS + 1];
1201 int map_cnt;
1202 struct tx_ring_desc *next;
1203};
1204
7c734359
RM		 1205struct page_chunk {
1206 struct page *page; /* master page */
1207 char *va; /* virt addr for this chunk */
1208 u64 map; /* mapping for master */
1209 unsigned int offset; /* offset for this chunk */
1210 unsigned int last_flag; /* flag set for last chunk in page */
1211};
1212
c4e84bde
RM		 1213struct bq_desc {
1214 union {
7c734359 1215 struct page_chunk pg_chunk;
c4e84bde
RM		 1216 struct sk_buff *skb;
1217 } p;
2c9a0d41 1218 __le64 *addr;
3537d54c 1219 u32 index;
c4e84bde
RM		 1220 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1221 DECLARE_PCI_UNMAP_LEN(maplen);
1222};
1223
1224#define QL_TXQ_IDX(qdev, skb) (smp_processor_id()%(qdev->tx_ring_count))
1225
1226struct tx_ring {
1227 /*
1228 * queue info.
1229 */
1230 struct wqicb wqicb; /* structure used to inform chip of new queue */
1231 void *wq_base; /* pci_alloc:virtual addr for tx */
1232 dma_addr_t wq_base_dma; /* pci_alloc:dma addr for tx */
ba7cd3ba 1233 __le32 *cnsmr_idx_sh_reg; /* shadow copy of consumer idx */
c4e84bde
RM		 1234 dma_addr_t cnsmr_idx_sh_reg_dma; /* dma-shadow copy of consumer */
1235 u32 wq_size; /* size in bytes of queue area */
1236 u32 wq_len; /* number of entries in queue */
1237 void __iomem *prod_idx_db_reg; /* doorbell area index reg at offset 0x00 */
1238 void __iomem *valid_db_reg; /* doorbell area valid reg at offset 0x04 */
1239 u16 prod_idx; /* current value for prod idx */
1240 u16 cq_id; /* completion (rx) queue for tx completions */
1241 u8 wq_id; /* queue id for this entry */
1242 u8 reserved1[3];
1243 struct tx_ring_desc *q; /* descriptor list for the queue */
1244 spinlock_t lock;
1245 atomic_t tx_count; /* counts down for every outstanding IO */
1246 atomic_t queue_stopped; /* Turns queue off when full. */
1247 struct delayed_work tx_work;
1248 struct ql_adapter *qdev;
1249};
1250
1251/*
1252 * Type of inbound queue.
1253 */
1254enum {
1255 DEFAULT_Q = 2, /* Handles slow queue and chip/MPI events. */
1256 TX_Q = 3, /* Handles outbound completions. */
1257 RX_Q = 4, /* Handles inbound completions. */
1258};
1259
1260struct rx_ring {
1261 struct cqicb cqicb; /* The chip's completion queue init control block. */
1262
1263 /* Completion queue elements. */
1264 void *cq_base;
1265 dma_addr_t cq_base_dma;
1266 u32 cq_size;
1267 u32 cq_len;
1268 u16 cq_id;
ba7cd3ba 1269 __le32 *prod_idx_sh_reg; /* Shadowed producer register. */
c4e84bde
RM		 1270 dma_addr_t prod_idx_sh_reg_dma;
1271 void __iomem *cnsmr_idx_db_reg; /* PCI doorbell mem area + 0 */
1272 u32 cnsmr_idx; /* current sw idx */
1273 struct ql_net_rsp_iocb *curr_entry; /* next entry on queue */
1274 void __iomem *valid_db_reg; /* PCI doorbell mem area + 0x04 */
1275
1276 /* Large buffer queue elements. */
1277 u32 lbq_len; /* entry count */
1278 u32 lbq_size; /* size in bytes of queue */
1279 u32 lbq_buf_size;
1280 void *lbq_base;
1281 dma_addr_t lbq_base_dma;
1282 void *lbq_base_indirect;
1283 dma_addr_t lbq_base_indirect_dma;
7c734359 1284 struct page_chunk pg_chunk; /* current page for chunks */
c4e84bde
RM		 1285 struct bq_desc *lbq; /* array of control blocks */
1286 void __iomem *lbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x18 */
1287 u32 lbq_prod_idx; /* current sw prod idx */
1288 u32 lbq_curr_idx; /* next entry we expect */
1289 u32 lbq_clean_idx; /* beginning of new descs */
1290 u32 lbq_free_cnt; /* free buffer desc cnt */
1291
1292 /* Small buffer queue elements. */
1293 u32 sbq_len; /* entry count */
1294 u32 sbq_size; /* size in bytes of queue */
1295 u32 sbq_buf_size;
1296 void *sbq_base;
1297 dma_addr_t sbq_base_dma;
1298 void *sbq_base_indirect;
1299 dma_addr_t sbq_base_indirect_dma;
1300 struct bq_desc *sbq; /* array of control blocks */
1301 void __iomem *sbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x1c */
1302 u32 sbq_prod_idx; /* current sw prod idx */
1303 u32 sbq_curr_idx; /* next entry we expect */
1304 u32 sbq_clean_idx; /* beginning of new descs */
1305 u32 sbq_free_cnt; /* free buffer desc cnt */
1306
1307 /* Misc. handler elements. */
b2014ff8 1308 u32 type; /* Type of queue, tx, rx. */
c4e84bde
RM		 1309 u32 irq; /* Which vector this ring is assigned. */
1310 u32 cpu; /* Which CPU this should run on. */
1311 char name[IFNAMSIZ + 5];
1312 struct napi_struct napi;
c4e84bde
RM		 1313 u8 reserved;
1314 struct ql_adapter *qdev;
1315};
1316
1317/*
1318 * RSS Initialization Control Block
1319 */
1320struct hash_id {
1321 u8 value[4];
1322};
1323
1324struct nic_stats {
1325 /*
1326 * These stats come from offset 200h to 278h
1327 * in the XGMAC register.
1328 */
1329 u64 tx_pkts;
1330 u64 tx_bytes;
1331 u64 tx_mcast_pkts;
1332 u64 tx_bcast_pkts;
1333 u64 tx_ucast_pkts;
1334 u64 tx_ctl_pkts;
1335 u64 tx_pause_pkts;
1336 u64 tx_64_pkt;
1337 u64 tx_65_to_127_pkt;
1338 u64 tx_128_to_255_pkt;
1339 u64 tx_256_511_pkt;
1340 u64 tx_512_to_1023_pkt;
1341 u64 tx_1024_to_1518_pkt;
1342 u64 tx_1519_to_max_pkt;
1343 u64 tx_undersize_pkt;
1344 u64 tx_oversize_pkt;
1345
1346 /*
1347 * These stats come from offset 300h to 3C8h
1348 * in the XGMAC register.
1349 */
1350 u64 rx_bytes;
1351 u64 rx_bytes_ok;
1352 u64 rx_pkts;
1353 u64 rx_pkts_ok;
1354 u64 rx_bcast_pkts;
1355 u64 rx_mcast_pkts;
1356 u64 rx_ucast_pkts;
1357 u64 rx_undersize_pkts;
1358 u64 rx_oversize_pkts;
1359 u64 rx_jabber_pkts;
1360 u64 rx_undersize_fcerr_pkts;
1361 u64 rx_drop_events;
1362 u64 rx_fcerr_pkts;
1363 u64 rx_align_err;
1364 u64 rx_symbol_err;
1365 u64 rx_mac_err;
1366 u64 rx_ctl_pkts;
1367 u64 rx_pause_pkts;
1368 u64 rx_64_pkts;
1369 u64 rx_65_to_127_pkts;
1370 u64 rx_128_255_pkts;
1371 u64 rx_256_511_pkts;
1372 u64 rx_512_to_1023_pkts;
1373 u64 rx_1024_to_1518_pkts;
1374 u64 rx_1519_to_max_pkts;
1375 u64 rx_len_err_pkts;
6abd2346
RM		 1376 /*
1377 * These stats come from offset 500h to 5C8h
1378 * in the XGMAC register.
1379 */
1380 u64 tx_cbfc_pause_frames0;
1381 u64 tx_cbfc_pause_frames1;
1382 u64 tx_cbfc_pause_frames2;
1383 u64 tx_cbfc_pause_frames3;
1384 u64 tx_cbfc_pause_frames4;
1385 u64 tx_cbfc_pause_frames5;
1386 u64 tx_cbfc_pause_frames6;
1387 u64 tx_cbfc_pause_frames7;
1388 u64 rx_cbfc_pause_frames0;
1389 u64 rx_cbfc_pause_frames1;
1390 u64 rx_cbfc_pause_frames2;
1391 u64 rx_cbfc_pause_frames3;
1392 u64 rx_cbfc_pause_frames4;
1393 u64 rx_cbfc_pause_frames5;
1394 u64 rx_cbfc_pause_frames6;
1395 u64 rx_cbfc_pause_frames7;
1396 u64 rx_nic_fifo_drop;
c4e84bde
RM		 1397};
1398
1399/*
1400 * intr_context structure is used during initialization
1401 * to hook the interrupts. It is also used in a single
1402 * irq environment as a context to the ISR.
1403 */
1404struct intr_context {
1405 struct ql_adapter *qdev;
1406 u32 intr;
39aa8165 1407 u32 irq_mask; /* Mask of which rings the vector services. */
c4e84bde
RM		 1408 u32 hooked;
1409 u32 intr_en_mask; /* value/mask used to enable this intr */
1410 u32 intr_dis_mask; /* value/mask used to disable this intr */
1411 u32 intr_read_mask; /* value/mask used to read this intr */
1412 char name[IFNAMSIZ * 2];
1413 atomic_t irq_cnt; /* irq_cnt is used in single vector
1414 * environment. It's incremented for each
1415 * irq handler that is scheduled. When each
1416 * handler finishes it decrements irq_cnt and
1417 * enables interrupts if it's zero. */
1418 irq_handler_t handler;
1419};
1420
1421/* adapter flags definitions. */
1422enum {
fbcbe56c
RM		 1423 QL_ADAPTER_UP = 0, /* Adapter has been brought up. */
1424 QL_LEGACY_ENABLED = 1,
1425 QL_MSI_ENABLED = 2,
1426 QL_MSIX_ENABLED = 3,
1427 QL_DMA64 = 4,
1428 QL_PROMISCUOUS = 5,
1429 QL_ALLMULTI = 6,
1430 QL_PORT_CFG = 7,
1431 QL_CAM_RT_SET = 8,
c4e84bde
RM		 1432};
1433
1434/* link_status bit definitions */
1435enum {
b82808b7
RM		 1436 STS_LOOPBACK_MASK = 0x00000700,
1437 STS_LOOPBACK_PCS = 0x00000100,
1438 STS_LOOPBACK_HSS = 0x00000200,
1439 STS_LOOPBACK_EXT = 0x00000300,
1440 STS_PAUSE_MASK = 0x000000c0,
1441 STS_PAUSE_STD = 0x00000040,
1442 STS_PAUSE_PRI = 0x00000080,
1443 STS_SPEED_MASK = 0x00000038,
1444 STS_SPEED_100Mb = 0x00000000,
1445 STS_SPEED_1Gb = 0x00000008,
1446 STS_SPEED_10Gb = 0x00000010,
1447 STS_LINK_TYPE_MASK = 0x00000007,
1448 STS_LINK_TYPE_XFI = 0x00000001,
1449 STS_LINK_TYPE_XAUI = 0x00000002,
1450 STS_LINK_TYPE_XFI_BP = 0x00000003,
1451 STS_LINK_TYPE_XAUI_BP = 0x00000004,
1452 STS_LINK_TYPE_10GBASET = 0x00000005,
1453};
1454
1455/* link_config bit definitions */
1456enum {
1457 CFG_JUMBO_FRAME_SIZE = 0x00010000,
1458 CFG_PAUSE_MASK = 0x00000060,
1459 CFG_PAUSE_STD = 0x00000020,
1460 CFG_PAUSE_PRI = 0x00000040,
1461 CFG_DCBX = 0x00000010,
1462 CFG_LOOPBACK_MASK = 0x00000007,
1463 CFG_LOOPBACK_PCS = 0x00000002,
1464 CFG_LOOPBACK_HSS = 0x00000004,
1465 CFG_LOOPBACK_EXT = 0x00000006,
1466 CFG_DEFAULT_MAX_FRAME_SIZE = 0x00002580,
c4e84bde
RM		 1467};
1468
b0c2aadf
RM		 1469struct nic_operations {
1470
1471 int (*get_flash) (struct ql_adapter *);
1472 int (*port_initialize) (struct ql_adapter *);
1473};
1474
c4e84bde
RM		 1475/*
1476 * The main Adapter structure definition.
1477 * This structure has all fields relevant to the hardware.
1478 */
1479struct ql_adapter {
1480 struct ricb ricb;
1481 unsigned long flags;
1482 u32 wol;
1483
1484 struct nic_stats nic_stats;
1485
1486 struct vlan_group *vlgrp;
1487
1488 /* PCI Configuration information for this device */
1489 struct pci_dev *pdev;
1490 struct net_device *ndev; /* Parent NET device */
1491
1492 /* Hardware information */
1493 u32 chip_rev_id;
cfec0cbc 1494 u32 fw_rev_id;
c4e84bde 1495 u32 func; /* PCI function for this adapter */
e4552f51
RM		 1496 u32 alt_func; /* PCI function for alternate adapter */
1497 u32 port; /* Port number this adapter */
c4e84bde
RM		 1498
1499 spinlock_t adapter_lock;
1500 spinlock_t hw_lock;
1501 spinlock_t stats_lock;
c4e84bde
RM		 1502
1503 /* PCI Bus Relative Register Addresses */
1504 void __iomem *reg_base;
1505 void __iomem *doorbell_area;
1506 u32 doorbell_area_size;
1507
1508 u32 msg_enable;
1509
1510 /* Page for Shadow Registers */
1511 void *rx_ring_shadow_reg_area;
1512 dma_addr_t rx_ring_shadow_reg_dma;
1513 void *tx_ring_shadow_reg_area;
1514 dma_addr_t tx_ring_shadow_reg_dma;
1515
1516 u32 mailbox_in;
1517 u32 mailbox_out;
bcc2cb3b 1518 struct mbox_params idc_mbc;
c4e84bde
RM		 1519
1520 int tx_ring_size;
1521 int rx_ring_size;
1522 u32 intr_count;
1523 struct msix_entry *msi_x_entry;
1524 struct intr_context intr_context[MAX_RX_RINGS];
1525
c4e84bde 1526 int tx_ring_count; /* One per online CPU. */
39aa8165 1527 u32 rss_ring_count; /* One per irq vector. */
c4e84bde
RM		 1528 /*
1529 * rx_ring_count =
c4e84bde 1530 * (CPU count * outbound completion rx_ring) +
39aa8165 1531 * (irq_vector_cnt * inbound (RSS) completion rx_ring)
c4e84bde
RM		 1532 */
1533 int rx_ring_count;
1534 int ring_mem_size;
1535 void *ring_mem;
683d46a9
RM		 1536
1537 struct rx_ring rx_ring[MAX_RX_RINGS];
1538 struct tx_ring tx_ring[MAX_TX_RINGS];
7c734359 1539 unsigned int lbq_buf_order;
683d46a9 1540
c4e84bde 1541 int rx_csum;
c4e84bde
RM		 1542 u32 default_rx_queue;
1543
1544 u16 rx_coalesce_usecs; /* cqicb->int_delay */
1545 u16 rx_max_coalesced_frames; /* cqicb->pkt_int_delay */
1546 u16 tx_coalesce_usecs; /* cqicb->int_delay */
1547 u16 tx_max_coalesced_frames; /* cqicb->pkt_int_delay */
1548
1549 u32 xg_sem_mask;
1550 u32 port_link_up;
1551 u32 port_init;
1552 u32 link_status;
bcc2cb3b
RM		 1553 u32 link_config;
1554 u32 max_frame_size;
c4e84bde 1555
b0c2aadf 1556 union flash_params flash;
c4e84bde 1557
c4e84bde
RM		 1558 struct workqueue_struct *workqueue;
1559 struct delayed_work asic_reset_work;
1560 struct delayed_work mpi_reset_work;
1561 struct delayed_work mpi_work;
bcc2cb3b 1562 struct delayed_work mpi_port_cfg_work;
2ee1e272 1563 struct delayed_work mpi_idc_work;
bcc2cb3b 1564 struct completion ide_completion;
b0c2aadf
RM		 1565 struct nic_operations *nic_ops;
1566 u16 device_id;
c4e84bde
RM		 1567};
1568
1569/*
1570 * Typical Register accessor for memory mapped device.
1571 */
1572static inline u32 ql_read32(const struct ql_adapter *qdev, int reg)
1573{
1574 return readl(qdev->reg_base + reg);
1575}
1576
1577/*
1578 * Typical Register accessor for memory mapped device.
1579 */
1580static inline void ql_write32(const struct ql_adapter *qdev, int reg, u32 val)
1581{
1582 writel(val, qdev->reg_base + reg);
1583}
1584
1585/*
1586 * Doorbell Registers:
1587 * Doorbell registers are virtual registers in the PCI memory space.
1588 * The space is allocated by the chip during PCI initialization. The
1589 * device driver finds the doorbell address in BAR 3 in PCI config space.
1590 * The registers are used to control outbound and inbound queues. For
1591 * example, the producer index for an outbound queue. Each queue uses
1592 * 1 4k chunk of memory. The lower half of the space is for outbound
1593 * queues. The upper half is for inbound queues.
1594 */
1595static inline void ql_write_db_reg(u32 val, void __iomem *addr)
1596{
1597 writel(val, addr);
1598 mmiowb();
1599}
1600
ba7cd3ba
RM		 1601/*
1602 * Shadow Registers:
1603 * Outbound queues have a consumer index that is maintained by the chip.
1604 * Inbound queues have a producer index that is maintained by the chip.
1605 * For lower overhead, these registers are "shadowed" to host memory
1606 * which allows the device driver to track the queue progress without
1607 * PCI reads. When an entry is placed on an inbound queue, the chip will
1608 * update the relevant index register and then copy the value to the
1609 * shadow register in host memory.
1610 */
1611static inline u32 ql_read_sh_reg(__le32 *addr)
1612{
1613 u32 reg;
1614 reg = le32_to_cpu(*addr);
1615 rmb();
1616 return reg;
1617}
1618
c4e84bde
RM		 1619extern char qlge_driver_name[];
1620extern const char qlge_driver_version[];
1621extern const struct ethtool_ops qlge_ethtool_ops;
1622
1623extern int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask);
1624extern void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask);
1625extern int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
1626extern int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
1627 u32 *value);
1628extern int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value);
1629extern int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
1630 u16 q_id);
1631void ql_queue_fw_error(struct ql_adapter *qdev);
1632void ql_mpi_work(struct work_struct *work);
1633void ql_mpi_reset_work(struct work_struct *work);
1634int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 ebit);
1635void ql_queue_asic_error(struct ql_adapter *qdev);
bb0d215c 1636u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr);
c4e84bde
RM		 1637void ql_set_ethtool_ops(struct net_device *ndev);
1638int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data);
2ee1e272 1639void ql_mpi_idc_work(struct work_struct *work);
bcc2cb3b 1640void ql_mpi_port_cfg_work(struct work_struct *work);
cdca8d02 1641int ql_mb_get_fw_state(struct ql_adapter *qdev);
2ee1e272 1642int ql_cam_route_initialize(struct ql_adapter *qdev);
e4552f51 1643int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
cfec0cbc 1644int ql_mb_about_fw(struct ql_adapter *qdev);
6a473308
RM		 1645void ql_link_on(struct ql_adapter *qdev);
1646void ql_link_off(struct ql_adapter *qdev);
84087f4d
RM		 1647int ql_mb_set_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 control);
1648int ql_wait_fifo_empty(struct ql_adapter *qdev);
c4e84bde
RM		 1649
1650#if 1
1651#define QL_ALL_DUMP
1652#define QL_REG_DUMP
1653#define QL_DEV_DUMP
1654#define QL_CB_DUMP
1655/* #define QL_IB_DUMP */
1656/* #define QL_OB_DUMP */
1657#endif
1658
1659#ifdef QL_REG_DUMP
1660extern void ql_dump_xgmac_control_regs(struct ql_adapter *qdev);
1661extern void ql_dump_routing_entries(struct ql_adapter *qdev);
1662extern void ql_dump_regs(struct ql_adapter *qdev);
1663#define QL_DUMP_REGS(qdev) ql_dump_regs(qdev)
1664#define QL_DUMP_ROUTE(qdev) ql_dump_routing_entries(qdev)
1665#define QL_DUMP_XGMAC_CONTROL_REGS(qdev) ql_dump_xgmac_control_regs(qdev)
1666#else
1667#define QL_DUMP_REGS(qdev)
1668#define QL_DUMP_ROUTE(qdev)
1669#define QL_DUMP_XGMAC_CONTROL_REGS(qdev)
1670#endif
1671
1672#ifdef QL_STAT_DUMP
1673extern void ql_dump_stat(struct ql_adapter *qdev);
1674#define QL_DUMP_STAT(qdev) ql_dump_stat(qdev)
1675#else
1676#define QL_DUMP_STAT(qdev)
1677#endif
1678
1679#ifdef QL_DEV_DUMP
1680extern void ql_dump_qdev(struct ql_adapter *qdev);
1681#define QL_DUMP_QDEV(qdev) ql_dump_qdev(qdev)
1682#else
1683#define QL_DUMP_QDEV(qdev)
1684#endif
1685
1686#ifdef QL_CB_DUMP
1687extern void ql_dump_wqicb(struct wqicb *wqicb);
1688extern void ql_dump_tx_ring(struct tx_ring *tx_ring);
1689extern void ql_dump_ricb(struct ricb *ricb);
1690extern void ql_dump_cqicb(struct cqicb *cqicb);
1691extern void ql_dump_rx_ring(struct rx_ring *rx_ring);
1692extern void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id);
1693#define QL_DUMP_RICB(ricb) ql_dump_ricb(ricb)
1694#define QL_DUMP_WQICB(wqicb) ql_dump_wqicb(wqicb)
1695#define QL_DUMP_TX_RING(tx_ring) ql_dump_tx_ring(tx_ring)
1696#define QL_DUMP_CQICB(cqicb) ql_dump_cqicb(cqicb)
1697#define QL_DUMP_RX_RING(rx_ring) ql_dump_rx_ring(rx_ring)
1698#define QL_DUMP_HW_CB(qdev, size, bit, q_id) \
1699 ql_dump_hw_cb(qdev, size, bit, q_id)
1700#else
1701#define QL_DUMP_RICB(ricb)
1702#define QL_DUMP_WQICB(wqicb)
1703#define QL_DUMP_TX_RING(tx_ring)
1704#define QL_DUMP_CQICB(cqicb)
1705#define QL_DUMP_RX_RING(rx_ring)
1706#define QL_DUMP_HW_CB(qdev, size, bit, q_id)
1707#endif
1708
1709#ifdef QL_OB_DUMP
1710extern void ql_dump_tx_desc(struct tx_buf_desc *tbd);
1711extern void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb);
1712extern void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp);
1713#define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) ql_dump_ob_mac_iocb(ob_mac_iocb)
1714#define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) ql_dump_ob_mac_rsp(ob_mac_rsp)
1715#else
1716#define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb)
1717#define QL_DUMP_OB_MAC_RSP(ob_mac_rsp)
1718#endif
1719
1720#ifdef QL_IB_DUMP
1721extern void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp);
1722#define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) ql_dump_ib_mac_rsp(ib_mac_rsp)
1723#else
1724#define QL_DUMP_IB_MAC_RSP(ib_mac_rsp)
1725#endif
1726
1727#ifdef QL_ALL_DUMP
1728extern void ql_dump_all(struct ql_adapter *qdev);
1729#define QL_DUMP_ALL(qdev) ql_dump_all(qdev)
1730#else
1731#define QL_DUMP_ALL(qdev)
1732#endif
1733
1734#endif /* _QLGE_H_ */
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