]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/qlcnic/qlcnic_hw.c
qlcnic: update oncard memory size check
[net-next-2.6.git] / drivers / net / qlcnic / qlcnic_hw.c
CommitLineData
af19b491
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1/*
2 * Copyright (C) 2009 - QLogic Corporation.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called "COPYING".
22 *
23 */
24
25#include "qlcnic.h"
26
27#include <net/ip.h>
28
29#define MASK(n) ((1ULL<<(n))-1)
30#define OCM_WIN_P3P(addr) (addr & 0xffc0000)
31
32#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
33
34#define CRB_BLK(off) ((off >> 20) & 0x3f)
35#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
36#define CRB_WINDOW_2M (0x130060)
37#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
38#define CRB_INDIRECT_2M (0x1e0000UL)
39
40
41#ifndef readq
42static inline u64 readq(void __iomem *addr)
43{
44 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
45}
46#endif
47
48#ifndef writeq
49static inline void writeq(u64 val, void __iomem *addr)
50{
51 writel(((u32) (val)), (addr));
52 writel(((u32) (val >> 32)), (addr + 4));
53}
54#endif
55
af19b491
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56#define PCI_OFFSET_FIRST_RANGE(adapter, off) \
57 ((adapter)->ahw.pci_base0 + (off))
58
59static void __iomem *pci_base_offset(struct qlcnic_adapter *adapter,
60 unsigned long off)
61{
62 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
63 return PCI_OFFSET_FIRST_RANGE(adapter, off);
64
65 return NULL;
66}
67
68static const struct crb_128M_2M_block_map
69crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
70 {{{0, 0, 0, 0} } }, /* 0: PCI */
71 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
72 {1, 0x0110000, 0x0120000, 0x130000},
73 {1, 0x0120000, 0x0122000, 0x124000},
74 {1, 0x0130000, 0x0132000, 0x126000},
75 {1, 0x0140000, 0x0142000, 0x128000},
76 {1, 0x0150000, 0x0152000, 0x12a000},
77 {1, 0x0160000, 0x0170000, 0x110000},
78 {1, 0x0170000, 0x0172000, 0x12e000},
79 {0, 0x0000000, 0x0000000, 0x000000},
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {1, 0x01e0000, 0x01e0800, 0x122000},
86 {0, 0x0000000, 0x0000000, 0x000000} } },
87 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
88 {{{0, 0, 0, 0} } }, /* 3: */
89 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
90 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
91 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
92 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
93 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {1, 0x08f0000, 0x08f2000, 0x172000} } },
109 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {1, 0x09f0000, 0x09f2000, 0x176000} } },
125 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
141 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
157 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
158 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
159 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
160 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
161 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
162 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
163 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
164 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
165 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
166 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
167 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
168 {{{0, 0, 0, 0} } }, /* 23: */
169 {{{0, 0, 0, 0} } }, /* 24: */
170 {{{0, 0, 0, 0} } }, /* 25: */
171 {{{0, 0, 0, 0} } }, /* 26: */
172 {{{0, 0, 0, 0} } }, /* 27: */
173 {{{0, 0, 0, 0} } }, /* 28: */
174 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
175 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
176 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
177 {{{0} } }, /* 32: PCI */
178 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
179 {1, 0x2110000, 0x2120000, 0x130000},
180 {1, 0x2120000, 0x2122000, 0x124000},
181 {1, 0x2130000, 0x2132000, 0x126000},
182 {1, 0x2140000, 0x2142000, 0x128000},
183 {1, 0x2150000, 0x2152000, 0x12a000},
184 {1, 0x2160000, 0x2170000, 0x110000},
185 {1, 0x2170000, 0x2172000, 0x12e000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000} } },
194 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
195 {{{0} } }, /* 35: */
196 {{{0} } }, /* 36: */
197 {{{0} } }, /* 37: */
198 {{{0} } }, /* 38: */
199 {{{0} } }, /* 39: */
200 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
201 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
202 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
203 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
204 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
205 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
206 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
207 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
208 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
209 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
210 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
211 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
212 {{{0} } }, /* 52: */
213 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
214 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
215 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
216 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
217 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
218 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
219 {{{0} } }, /* 59: I2C0 */
220 {{{0} } }, /* 60: I2C1 */
221 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
222 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
223 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
224};
225
226/*
227 * top 12 bits of crb internal address (hub, agent)
228 */
229static const unsigned crb_hub_agt[64] = {
230 0,
231 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
232 QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
233 QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
234 0,
235 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
236 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
237 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
238 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
239 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
240 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
241 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
242 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
243 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
244 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
245 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
246 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
247 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
248 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
249 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
250 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
251 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
252 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
253 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
254 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
255 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
256 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
257 0,
258 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
259 QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
260 0,
261 QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
262 0,
263 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
264 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
265 0,
266 0,
267 0,
268 0,
269 0,
270 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
271 0,
272 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
273 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
274 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
275 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
276 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
277 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
278 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
279 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
280 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
281 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
282 0,
283 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
284 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
285 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
286 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
287 0,
288 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
289 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
290 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
291 0,
292 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
293 0,
294};
295
296/* PCI Windowing for DDR regions. */
297
298#define QLCNIC_PCIE_SEM_TIMEOUT 10000
299
300int
301qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
302{
303 int done = 0, timeout = 0;
304
305 while (!done) {
306 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
307 if (done == 1)
308 break;
309 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT)
310 return -EIO;
311 msleep(1);
312 }
313
314 if (id_reg)
315 QLCWR32(adapter, id_reg, adapter->portnum);
316
317 return 0;
318}
319
320void
321qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
322{
323 QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
324}
325
326static int
327qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
328 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
329{
330 u32 i, producer, consumer;
331 struct qlcnic_cmd_buffer *pbuf;
332 struct cmd_desc_type0 *cmd_desc;
333 struct qlcnic_host_tx_ring *tx_ring;
334
335 i = 0;
336
337 if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
338 return -EIO;
339
340 tx_ring = adapter->tx_ring;
341 __netif_tx_lock_bh(tx_ring->txq);
342
343 producer = tx_ring->producer;
344 consumer = tx_ring->sw_consumer;
345
346 if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
347 netif_tx_stop_queue(tx_ring->txq);
348 __netif_tx_unlock_bh(tx_ring->txq);
8bfe8b91 349 adapter->stats.xmit_off++;
af19b491
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350 return -EBUSY;
351 }
352
353 do {
354 cmd_desc = &cmd_desc_arr[i];
355
356 pbuf = &tx_ring->cmd_buf_arr[producer];
357 pbuf->skb = NULL;
358 pbuf->frag_count = 0;
359
360 memcpy(&tx_ring->desc_head[producer],
361 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
362
363 producer = get_next_index(producer, tx_ring->num_desc);
364 i++;
365
366 } while (i != nr_desc);
367
368 tx_ring->producer = producer;
369
370 qlcnic_update_cmd_producer(adapter, tx_ring);
371
372 __netif_tx_unlock_bh(tx_ring->txq);
373
374 return 0;
375}
376
377static int
378qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
379 unsigned op)
380{
381 struct qlcnic_nic_req req;
382 struct qlcnic_mac_req *mac_req;
383 u64 word;
384
385 memset(&req, 0, sizeof(struct qlcnic_nic_req));
386 req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
387
388 word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
389 req.req_hdr = cpu_to_le64(word);
390
391 mac_req = (struct qlcnic_mac_req *)&req.words[0];
392 mac_req->op = op;
393 memcpy(mac_req->mac_addr, addr, 6);
394
395 return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
396}
397
9ab17b39 398static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, u8 *addr)
af19b491
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399{
400 struct list_head *head;
401 struct qlcnic_mac_list_s *cur;
402
403 /* look up if already exists */
9ab17b39 404 list_for_each(head, &adapter->mac_list) {
af19b491 405 cur = list_entry(head, struct qlcnic_mac_list_s, list);
9ab17b39 406 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
af19b491 407 return 0;
af19b491
AKS
408 }
409
410 cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
411 if (cur == NULL) {
412 dev_err(&adapter->netdev->dev,
413 "failed to add mac address filter\n");
414 return -ENOMEM;
415 }
416 memcpy(cur->mac_addr, addr, ETH_ALEN);
417 list_add_tail(&cur->list, &adapter->mac_list);
418
419 return qlcnic_sre_macaddr_change(adapter,
420 cur->mac_addr, QLCNIC_MAC_ADD);
421}
422
423void qlcnic_set_multi(struct net_device *netdev)
424{
425 struct qlcnic_adapter *adapter = netdev_priv(netdev);
426 struct dev_mc_list *mc_ptr;
427 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
428 u32 mode = VPORT_MISS_MODE_DROP;
af19b491 429
9ab17b39
SC
430 qlcnic_nic_add_mac(adapter, adapter->mac_addr);
431 qlcnic_nic_add_mac(adapter, bcast_addr);
af19b491
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432
433 if (netdev->flags & IFF_PROMISC) {
434 mode = VPORT_MISS_MODE_ACCEPT_ALL;
435 goto send_fw_cmd;
436 }
437
438 if ((netdev->flags & IFF_ALLMULTI) ||
4cd24eaf 439 (netdev_mc_count(netdev) > adapter->max_mc_count)) {
af19b491
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440 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
441 goto send_fw_cmd;
442 }
443
4cd24eaf 444 if (!netdev_mc_empty(netdev)) {
f9dcbcc9 445 netdev_for_each_mc_addr(mc_ptr, netdev) {
9ab17b39 446 qlcnic_nic_add_mac(adapter, mc_ptr->dmi_addr);
af19b491
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447 }
448 }
449
450send_fw_cmd:
451 qlcnic_nic_set_promisc(adapter, mode);
af19b491
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452}
453
454int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
455{
456 struct qlcnic_nic_req req;
457 u64 word;
458
459 memset(&req, 0, sizeof(struct qlcnic_nic_req));
460
461 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
462
463 word = QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
464 ((u64)adapter->portnum << 16);
465 req.req_hdr = cpu_to_le64(word);
466
467 req.words[0] = cpu_to_le64(mode);
468
469 return qlcnic_send_cmd_descs(adapter,
470 (struct cmd_desc_type0 *)&req, 1);
471}
472
473void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
474{
475 struct qlcnic_mac_list_s *cur;
476 struct list_head *head = &adapter->mac_list;
477
478 while (!list_empty(head)) {
479 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
480 qlcnic_sre_macaddr_change(adapter,
481 cur->mac_addr, QLCNIC_MAC_DEL);
482 list_del(&cur->list);
483 kfree(cur);
484 }
485}
486
487#define QLCNIC_CONFIG_INTR_COALESCE 3
488
489/*
490 * Send the interrupt coalescing parameter set by ethtool to the card.
491 */
492int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
493{
494 struct qlcnic_nic_req req;
495 u64 word[6];
496 int rv, i;
497
498 memset(&req, 0, sizeof(struct qlcnic_nic_req));
499
500 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
501
502 word[0] = QLCNIC_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
503 req.req_hdr = cpu_to_le64(word[0]);
504
505 memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
506 for (i = 0; i < 6; i++)
507 req.words[i] = cpu_to_le64(word[i]);
508
509 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
510 if (rv != 0)
511 dev_err(&adapter->netdev->dev,
512 "Could not send interrupt coalescing parameters\n");
513
514 return rv;
515}
516
517int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
518{
519 struct qlcnic_nic_req req;
520 u64 word;
521 int rv;
522
523 if ((adapter->flags & QLCNIC_LRO_ENABLED) == enable)
524 return 0;
525
526 memset(&req, 0, sizeof(struct qlcnic_nic_req));
527
528 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
529
530 word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
531 req.req_hdr = cpu_to_le64(word);
532
533 req.words[0] = cpu_to_le64(enable);
534
535 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
536 if (rv != 0)
537 dev_err(&adapter->netdev->dev,
538 "Could not send configure hw lro request\n");
539
540 adapter->flags ^= QLCNIC_LRO_ENABLED;
541
542 return rv;
543}
544
545int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, int enable)
546{
547 struct qlcnic_nic_req req;
548 u64 word;
549 int rv;
550
551 if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
552 return 0;
553
554 memset(&req, 0, sizeof(struct qlcnic_nic_req));
555
556 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
557
558 word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
559 ((u64)adapter->portnum << 16);
560 req.req_hdr = cpu_to_le64(word);
561
562 req.words[0] = cpu_to_le64(enable);
563
564 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
565 if (rv != 0)
566 dev_err(&adapter->netdev->dev,
567 "Could not send configure bridge mode request\n");
568
569 adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
570
571 return rv;
572}
573
574
575#define RSS_HASHTYPE_IP_TCP 0x3
576
577int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
578{
579 struct qlcnic_nic_req req;
580 u64 word;
581 int i, rv;
582
583 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
584 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
585 0x255b0ec26d5a56daULL };
586
587
588 memset(&req, 0, sizeof(struct qlcnic_nic_req));
589 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
590
591 word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
592 req.req_hdr = cpu_to_le64(word);
593
594 /*
595 * RSS request:
596 * bits 3-0: hash_method
597 * 5-4: hash_type_ipv4
598 * 7-6: hash_type_ipv6
599 * 8: enable
600 * 9: use indirection table
601 * 47-10: reserved
602 * 63-48: indirection table mask
603 */
604 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
605 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
606 ((u64)(enable & 0x1) << 8) |
607 ((0x7ULL) << 48);
608 req.words[0] = cpu_to_le64(word);
609 for (i = 0; i < 5; i++)
610 req.words[i+1] = cpu_to_le64(key[i]);
611
612 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
613 if (rv != 0)
614 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
615
616 return rv;
617}
618
619int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd)
620{
621 struct qlcnic_nic_req req;
622 u64 word;
623 int rv;
624
625 memset(&req, 0, sizeof(struct qlcnic_nic_req));
626 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
627
628 word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
629 req.req_hdr = cpu_to_le64(word);
630
631 req.words[0] = cpu_to_le64(cmd);
632 req.words[1] = cpu_to_le64(ip);
633
634 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
635 if (rv != 0)
636 dev_err(&adapter->netdev->dev,
637 "could not notify %s IP 0x%x reuqest\n",
638 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
639
640 return rv;
641}
642
643int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
644{
645 struct qlcnic_nic_req req;
646 u64 word;
647 int rv;
648
649 memset(&req, 0, sizeof(struct qlcnic_nic_req));
650 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
651
652 word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
653 req.req_hdr = cpu_to_le64(word);
654 req.words[0] = cpu_to_le64(enable | (enable << 8));
655
656 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
657 if (rv != 0)
658 dev_err(&adapter->netdev->dev,
659 "could not configure link notification\n");
660
661 return rv;
662}
663
664int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
665{
666 struct qlcnic_nic_req req;
667 u64 word;
668 int rv;
669
670 memset(&req, 0, sizeof(struct qlcnic_nic_req));
671 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
672
673 word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
674 ((u64)adapter->portnum << 16) |
675 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
676
677 req.req_hdr = cpu_to_le64(word);
678
679 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
680 if (rv != 0)
681 dev_err(&adapter->netdev->dev,
682 "could not cleanup lro flows\n");
683
684 return rv;
685}
686
687/*
688 * qlcnic_change_mtu - Change the Maximum Transfer Unit
689 * @returns 0 on success, negative on failure
690 */
691
692int qlcnic_change_mtu(struct net_device *netdev, int mtu)
693{
694 struct qlcnic_adapter *adapter = netdev_priv(netdev);
695 int rc = 0;
696
697 if (mtu > P3_MAX_MTU) {
698 dev_err(&adapter->netdev->dev, "mtu > %d bytes unsupported\n",
699 P3_MAX_MTU);
700 return -EINVAL;
701 }
702
703 rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
704
705 if (!rc)
706 netdev->mtu = mtu;
707
708 return rc;
709}
710
711int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u64 *mac)
712{
713 u32 crbaddr, mac_hi, mac_lo;
714 int pci_func = adapter->ahw.pci_func;
715
716 crbaddr = CRB_MAC_BLOCK_START +
717 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
718
719 mac_lo = QLCRD32(adapter, crbaddr);
720 mac_hi = QLCRD32(adapter, crbaddr+4);
721
722 if (pci_func & 1)
723 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
724 else
725 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
726
727 return 0;
728}
729
730/*
731 * Changes the CRB window to the specified window.
732 */
733 /* Returns < 0 if off is not valid,
734 * 1 if window access is needed. 'off' is set to offset from
735 * CRB space in 128M pci map
736 * 0 if no window access is needed. 'off' is set to 2M addr
737 * In: 'off' is offset from base in 128M pci map
738 */
739static int
740qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
741 ulong off, void __iomem **addr)
742{
743 const struct crb_128M_2M_sub_block_map *m;
744
745 if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
746 return -EINVAL;
747
748 off -= QLCNIC_PCI_CRBSPACE;
749
750 /*
751 * Try direct map
752 */
753 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
754
755 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
756 *addr = adapter->ahw.pci_base0 + m->start_2M +
757 (off - m->start_128M);
758 return 0;
759 }
760
761 /*
762 * Not in direct map, use crb window
763 */
764 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
765 return 1;
766}
767
768/*
769 * In: 'off' is offset from CRB space in 128M pci map
770 * Out: 'off' is 2M pci map addr
771 * side effect: lock crb window
772 */
773static void
774qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
775{
776 u32 window;
777 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
778
779 off -= QLCNIC_PCI_CRBSPACE;
780
781 window = CRB_HI(off);
782
783 if (adapter->ahw.crb_win == window)
784 return;
785
786 writel(window, addr);
787 if (readl(addr) != window) {
788 if (printk_ratelimit())
789 dev_warn(&adapter->pdev->dev,
790 "failed to set CRB window to %d off 0x%lx\n",
791 window, off);
792 }
793 adapter->ahw.crb_win = window;
794}
795
796int
797qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
798{
799 unsigned long flags;
800 int rv;
801 void __iomem *addr = NULL;
802
803 rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
804
805 if (rv == 0) {
806 writel(data, addr);
807 return 0;
808 }
809
810 if (rv > 0) {
811 /* indirect access */
812 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
813 crb_win_lock(adapter);
814 qlcnic_pci_set_crbwindow_2M(adapter, off);
815 writel(data, addr);
816 crb_win_unlock(adapter);
817 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
818 return 0;
819 }
820
821 dev_err(&adapter->pdev->dev,
822 "%s: invalid offset: 0x%016lx\n", __func__, off);
823 dump_stack();
824 return -EIO;
825}
826
827u32
828qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
829{
830 unsigned long flags;
831 int rv;
832 u32 data;
833 void __iomem *addr = NULL;
834
835 rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
836
837 if (rv == 0)
838 return readl(addr);
839
840 if (rv > 0) {
841 /* indirect access */
842 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
843 crb_win_lock(adapter);
844 qlcnic_pci_set_crbwindow_2M(adapter, off);
845 data = readl(addr);
846 crb_win_unlock(adapter);
847 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
848 return data;
849 }
850
851 dev_err(&adapter->pdev->dev,
852 "%s: invalid offset: 0x%016lx\n", __func__, off);
853 dump_stack();
854 return -1;
855}
856
857
858void __iomem *
859qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
860{
861 void __iomem *addr = NULL;
862
863 WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
864
865 return addr;
866}
867
868
869static int
870qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
871 u64 addr, u32 *start)
872{
873 u32 window;
874 struct pci_dev *pdev = adapter->pdev;
875
876 if ((addr & 0x00ff800) == 0xff800) {
877 if (printk_ratelimit())
878 dev_warn(&pdev->dev, "QM access not handled\n");
879 return -EIO;
880 }
881
882 window = OCM_WIN_P3P(addr);
883
884 writel(window, adapter->ahw.ocm_win_crb);
885 /* read back to flush */
886 readl(adapter->ahw.ocm_win_crb);
887
888 adapter->ahw.ocm_win = window;
889 *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
890 return 0;
891}
892
893static int
894qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
895 u64 *data, int op)
896{
897 void __iomem *addr, *mem_ptr = NULL;
898 resource_size_t mem_base;
899 int ret;
900 u32 start;
901
902 mutex_lock(&adapter->ahw.mem_lock);
903
904 ret = qlcnic_pci_set_window_2M(adapter, off, &start);
905 if (ret != 0)
906 goto unlock;
907
908 addr = pci_base_offset(adapter, start);
909 if (addr)
910 goto noremap;
911
912 mem_base = pci_resource_start(adapter->pdev, 0) + (start & PAGE_MASK);
913
914 mem_ptr = ioremap(mem_base, PAGE_SIZE);
915 if (mem_ptr == NULL) {
916 ret = -EIO;
917 goto unlock;
918 }
919
920 addr = mem_ptr + (start & (PAGE_SIZE - 1));
921
922noremap:
923 if (op == 0) /* read */
924 *data = readq(addr);
925 else /* write */
926 writeq(*data, addr);
927
928unlock:
929 mutex_unlock(&adapter->ahw.mem_lock);
930
931 if (mem_ptr)
932 iounmap(mem_ptr);
933 return ret;
934}
935
897e8c7c
DP
936void
937qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
938{
939 void __iomem *addr = adapter->ahw.pci_base0 +
940 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
941
942 mutex_lock(&adapter->ahw.mem_lock);
943 *data = readq(addr);
944 mutex_unlock(&adapter->ahw.mem_lock);
945}
946
947void
948qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
949{
950 void __iomem *addr = adapter->ahw.pci_base0 +
951 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
952
953 mutex_lock(&adapter->ahw.mem_lock);
954 writeq(data, addr);
955 mutex_unlock(&adapter->ahw.mem_lock);
956}
957
af19b491
AKS
958#define MAX_CTL_CHECK 1000
959
960int
961qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
962 u64 off, u64 data)
963{
964 int i, j, ret;
965 u32 temp, off8;
af19b491
AKS
966 void __iomem *mem_crb;
967
968 /* Only 64-bit aligned access */
969 if (off & 7)
970 return -EIO;
971
972 /* P3 onward, test agent base for MIU and SIU is same */
973 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
b47acacd 974 QLCNIC_ADDR_QDR_NET_MAX)) {
af19b491
AKS
975 mem_crb = qlcnic_get_ioaddr(adapter,
976 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
977 goto correct;
978 }
979
980 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
981 mem_crb = qlcnic_get_ioaddr(adapter,
982 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
983 goto correct;
984 }
985
986 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
987 return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
988
989 return -EIO;
990
991correct:
b47acacd 992 off8 = off & ~0xf;
af19b491
AKS
993
994 mutex_lock(&adapter->ahw.mem_lock);
995
996 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
997 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
998
999 i = 0;
b47acacd
DP
1000 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1001 writel((TA_CTL_START | TA_CTL_ENABLE),
1002 (mem_crb + TEST_AGT_CTRL));
af19b491 1003
b47acacd
DP
1004 for (j = 0; j < MAX_CTL_CHECK; j++) {
1005 temp = readl(mem_crb + TEST_AGT_CTRL);
1006 if ((temp & TA_CTL_BUSY) == 0)
1007 break;
1008 }
af19b491 1009
b47acacd
DP
1010 if (j >= MAX_CTL_CHECK) {
1011 ret = -EIO;
1012 goto done;
af19b491
AKS
1013 }
1014
b47acacd
DP
1015 i = (off & 0xf) ? 0 : 2;
1016 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1017 mem_crb + MIU_TEST_AGT_WRDATA(i));
1018 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1019 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1020 i = (off & 0xf) ? 2 : 0;
1021
af19b491
AKS
1022 writel(data & 0xffffffff,
1023 mem_crb + MIU_TEST_AGT_WRDATA(i));
1024 writel((data >> 32) & 0xffffffff,
1025 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1026
1027 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1028 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1029 (mem_crb + TEST_AGT_CTRL));
1030
1031 for (j = 0; j < MAX_CTL_CHECK; j++) {
1032 temp = readl(mem_crb + TEST_AGT_CTRL);
1033 if ((temp & TA_CTL_BUSY) == 0)
1034 break;
1035 }
1036
1037 if (j >= MAX_CTL_CHECK) {
1038 if (printk_ratelimit())
1039 dev_err(&adapter->pdev->dev,
1040 "failed to write through agent\n");
1041 ret = -EIO;
1042 } else
1043 ret = 0;
1044
1045done:
1046 mutex_unlock(&adapter->ahw.mem_lock);
1047
1048 return ret;
1049}
1050
1051int
1052qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
1053 u64 off, u64 *data)
1054{
1055 int j, ret;
1056 u32 temp, off8;
b47acacd 1057 u64 val;
af19b491
AKS
1058 void __iomem *mem_crb;
1059
1060 /* Only 64-bit aligned access */
1061 if (off & 7)
1062 return -EIO;
1063
1064 /* P3 onward, test agent base for MIU and SIU is same */
1065 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
b47acacd 1066 QLCNIC_ADDR_QDR_NET_MAX)) {
af19b491
AKS
1067 mem_crb = qlcnic_get_ioaddr(adapter,
1068 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1069 goto correct;
1070 }
1071
1072 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1073 mem_crb = qlcnic_get_ioaddr(adapter,
1074 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1075 goto correct;
1076 }
1077
1078 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
1079 return qlcnic_pci_mem_access_direct(adapter,
1080 off, data, 0);
1081 }
1082
1083 return -EIO;
1084
1085correct:
b47acacd 1086 off8 = off & ~0xf;
af19b491
AKS
1087
1088 mutex_lock(&adapter->ahw.mem_lock);
1089
1090 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1091 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1092 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1093 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1094
1095 for (j = 0; j < MAX_CTL_CHECK; j++) {
1096 temp = readl(mem_crb + TEST_AGT_CTRL);
1097 if ((temp & TA_CTL_BUSY) == 0)
1098 break;
1099 }
1100
1101 if (j >= MAX_CTL_CHECK) {
1102 if (printk_ratelimit())
1103 dev_err(&adapter->pdev->dev,
1104 "failed to read through agent\n");
1105 ret = -EIO;
1106 } else {
1107 off8 = MIU_TEST_AGT_RDDATA_LO;
b47acacd 1108 if (off & 0xf)
af19b491
AKS
1109 off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1110
1111 temp = readl(mem_crb + off8 + 4);
1112 val = (u64)temp << 32;
1113 val |= readl(mem_crb + off8);
1114 *data = val;
1115 ret = 0;
1116 }
1117
1118 mutex_unlock(&adapter->ahw.mem_lock);
1119
1120 return ret;
1121}
1122
1123int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1124{
1125 int offset, board_type, magic;
1126 struct pci_dev *pdev = adapter->pdev;
1127
1128 offset = QLCNIC_FW_MAGIC_OFFSET;
1129 if (qlcnic_rom_fast_read(adapter, offset, &magic))
1130 return -EIO;
1131
1132 if (magic != QLCNIC_BDINFO_MAGIC) {
1133 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1134 magic);
1135 return -EIO;
1136 }
1137
1138 offset = QLCNIC_BRDTYPE_OFFSET;
1139 if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1140 return -EIO;
1141
1142 adapter->ahw.board_type = board_type;
1143
1144 if (board_type == QLCNIC_BRDTYPE_P3_4_GB_MM) {
1145 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1146 if ((gpio & 0x8000) == 0)
1147 board_type = QLCNIC_BRDTYPE_P3_10G_TP;
1148 }
1149
1150 switch (board_type) {
1151 case QLCNIC_BRDTYPE_P3_HMEZ:
1152 case QLCNIC_BRDTYPE_P3_XG_LOM:
1153 case QLCNIC_BRDTYPE_P3_10G_CX4:
1154 case QLCNIC_BRDTYPE_P3_10G_CX4_LP:
1155 case QLCNIC_BRDTYPE_P3_IMEZ:
1156 case QLCNIC_BRDTYPE_P3_10G_SFP_PLUS:
1157 case QLCNIC_BRDTYPE_P3_10G_SFP_CT:
1158 case QLCNIC_BRDTYPE_P3_10G_SFP_QT:
1159 case QLCNIC_BRDTYPE_P3_10G_XFP:
1160 case QLCNIC_BRDTYPE_P3_10000_BASE_T:
1161 adapter->ahw.port_type = QLCNIC_XGBE;
1162 break;
1163 case QLCNIC_BRDTYPE_P3_REF_QG:
1164 case QLCNIC_BRDTYPE_P3_4_GB:
1165 case QLCNIC_BRDTYPE_P3_4_GB_MM:
1166 adapter->ahw.port_type = QLCNIC_GBE;
1167 break;
1168 case QLCNIC_BRDTYPE_P3_10G_TP:
1169 adapter->ahw.port_type = (adapter->portnum < 2) ?
1170 QLCNIC_XGBE : QLCNIC_GBE;
1171 break;
1172 default:
1173 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1174 adapter->ahw.port_type = QLCNIC_XGBE;
1175 break;
1176 }
1177
1178 return 0;
1179}
1180
1181int
1182qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1183{
1184 u32 wol_cfg;
1185
1186 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1187 if (wol_cfg & (1UL << adapter->portnum)) {
1188 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1189 if (wol_cfg & (1 << adapter->portnum))
1190 return 1;
1191 }
1192
1193 return 0;
1194}
897d3596
SC
1195
1196int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1197{
1198 struct qlcnic_nic_req req;
1199 int rv;
1200 u64 word;
1201
1202 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1203 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1204
1205 word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1206 req.req_hdr = cpu_to_le64(word);
1207
1208 req.words[0] = cpu_to_le64((u64)rate << 32);
1209 req.words[1] = cpu_to_le64(state);
1210
1211 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1212 if (rv)
1213 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1214
1215 return rv;
1216}
cdaff185
AKS
1217
1218static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u32 flag)
1219{
1220 struct qlcnic_nic_req req;
1221 int rv;
1222 u64 word;
1223
1224 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1225 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1226
1227 word = QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
1228 ((u64)adapter->portnum << 16);
1229 req.req_hdr = cpu_to_le64(word);
1230 req.words[0] = cpu_to_le64(flag);
1231
1232 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1233 if (rv)
1234 dev_err(&adapter->pdev->dev,
1235 "%sting loopback mode failed.\n",
1236 flag ? "Set" : "Reset");
1237 return rv;
1238}
1239
1240int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter)
1241{
1242 if (qlcnic_set_fw_loopback(adapter, 1))
1243 return -EIO;
1244
1245 if (qlcnic_nic_set_promisc(adapter,
1246 VPORT_MISS_MODE_ACCEPT_ALL)) {
1247 qlcnic_set_fw_loopback(adapter, 0);
1248 return -EIO;
1249 }
1250
1251 msleep(1000);
1252 return 0;
1253}
1254
1255void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter)
1256{
1257 int mode = VPORT_MISS_MODE_DROP;
1258 struct net_device *netdev = adapter->netdev;
1259
1260 qlcnic_set_fw_loopback(adapter, 0);
1261
1262 if (netdev->flags & IFF_PROMISC)
1263 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1264 else if (netdev->flags & IFF_ALLMULTI)
1265 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1266
1267 qlcnic_nic_set_promisc(adapter, mode);
1268}