git://bbs.cooldavid.org / net-next-2.6.git / blame
| Commit | Line | Data |
|---|---|---|
| af19b491 AKS |
1 | /* |
| 2 | * Copyright (C) 2009 - QLogic Corporation. | |
| 3 | * All rights reserved. | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or | |
| 6 | * modify it under the terms of the GNU General Public License | |
| 7 | * as published by the Free Software Foundation; either version 2 | |
| 8 | * of the License, or (at your option) any later version. | |
| 9 | * | |
| 10 | * This program is distributed in the hope that it will be useful, but | |
| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | * GNU General Public License for more details. | |
| 14 | * | |
| 15 | * You should have received a copy of the GNU General Public License | |
| 16 | * along with this program; if not, write to the Free Software | |
| 17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
| 18 | * MA 02111-1307, USA. | |
| 19 | * | |
| 20 | * The full GNU General Public License is included in this distribution | |
| 21 | * in the file called "COPYING". | |
| 22 | * | |
| 23 | */ | |
| 24 | ||
| 25 | #ifndef __QLCNIC_HDR_H_ | |
| 26 | #define __QLCNIC_HDR_H_ | |
| 27 | ||
| 28 | #include <linux/kernel.h> | |
| 29 | #include <linux/types.h> | |
| 30 | ||
| 31 | /* | |
| 32 | * The basic unit of access when reading/writing control registers. | |
| 33 | */ | |
| 34 | ||
| 35 | enum { | |
| 36 | QLCNIC_HW_H0_CH_HUB_ADR = 0x05, | |
| 37 | QLCNIC_HW_H1_CH_HUB_ADR = 0x0E, | |
| 38 | QLCNIC_HW_H2_CH_HUB_ADR = 0x03, | |
| 39 | QLCNIC_HW_H3_CH_HUB_ADR = 0x01, | |
| 40 | QLCNIC_HW_H4_CH_HUB_ADR = 0x06, | |
| 41 | QLCNIC_HW_H5_CH_HUB_ADR = 0x07, | |
| 42 | QLCNIC_HW_H6_CH_HUB_ADR = 0x08 | |
| 43 | }; | |
| 44 | ||
| 45 | /* Hub 0 */ | |
| 46 | enum { | |
| 47 | QLCNIC_HW_MN_CRB_AGT_ADR = 0x15, | |
| 48 | QLCNIC_HW_MS_CRB_AGT_ADR = 0x25 | |
| 49 | }; | |
| 50 | ||
| 51 | /* Hub 1 */ | |
| 52 | enum { | |
| 53 | QLCNIC_HW_PS_CRB_AGT_ADR = 0x73, | |
| 54 | QLCNIC_HW_SS_CRB_AGT_ADR = 0x20, | |
| 55 | QLCNIC_HW_RPMX3_CRB_AGT_ADR = 0x0b, | |
| 56 | QLCNIC_HW_QMS_CRB_AGT_ADR = 0x00, | |
| 57 | QLCNIC_HW_SQGS0_CRB_AGT_ADR = 0x01, | |
| 58 | QLCNIC_HW_SQGS1_CRB_AGT_ADR = 0x02, | |
| 59 | QLCNIC_HW_SQGS2_CRB_AGT_ADR = 0x03, | |
| 60 | QLCNIC_HW_SQGS3_CRB_AGT_ADR = 0x04, | |
| 61 | QLCNIC_HW_C2C0_CRB_AGT_ADR = 0x58, | |
| 62 | QLCNIC_HW_C2C1_CRB_AGT_ADR = 0x59, | |
| 63 | QLCNIC_HW_C2C2_CRB_AGT_ADR = 0x5a, | |
| 64 | QLCNIC_HW_RPMX2_CRB_AGT_ADR = 0x0a, | |
| 65 | QLCNIC_HW_RPMX4_CRB_AGT_ADR = 0x0c, | |
| 66 | QLCNIC_HW_RPMX7_CRB_AGT_ADR = 0x0f, | |
| 67 | QLCNIC_HW_RPMX9_CRB_AGT_ADR = 0x12, | |
| 68 | QLCNIC_HW_SMB_CRB_AGT_ADR = 0x18 | |
| 69 | }; | |
| 70 | ||
| 71 | /* Hub 2 */ | |
| 72 | enum { | |
| 73 | QLCNIC_HW_NIU_CRB_AGT_ADR = 0x31, | |
| 74 | QLCNIC_HW_I2C0_CRB_AGT_ADR = 0x19, | |
| 75 | QLCNIC_HW_I2C1_CRB_AGT_ADR = 0x29, | |
| 76 | ||
| 77 | QLCNIC_HW_SN_CRB_AGT_ADR = 0x10, | |
| 78 | QLCNIC_HW_I2Q_CRB_AGT_ADR = 0x20, | |
| 79 | QLCNIC_HW_LPC_CRB_AGT_ADR = 0x22, | |
| 80 | QLCNIC_HW_ROMUSB_CRB_AGT_ADR = 0x21, | |
| 81 | QLCNIC_HW_QM_CRB_AGT_ADR = 0x66, | |
| 82 | QLCNIC_HW_SQG0_CRB_AGT_ADR = 0x60, | |
| 83 | QLCNIC_HW_SQG1_CRB_AGT_ADR = 0x61, | |
| 84 | QLCNIC_HW_SQG2_CRB_AGT_ADR = 0x62, | |
| 85 | QLCNIC_HW_SQG3_CRB_AGT_ADR = 0x63, | |
| 86 | QLCNIC_HW_RPMX1_CRB_AGT_ADR = 0x09, | |
| 87 | QLCNIC_HW_RPMX5_CRB_AGT_ADR = 0x0d, | |
| 88 | QLCNIC_HW_RPMX6_CRB_AGT_ADR = 0x0e, | |
| 89 | QLCNIC_HW_RPMX8_CRB_AGT_ADR = 0x11 | |
| 90 | }; | |
| 91 | ||
| 92 | /* Hub 3 */ | |
| 93 | enum { | |
| 94 | QLCNIC_HW_PH_CRB_AGT_ADR = 0x1A, | |
| 95 | QLCNIC_HW_SRE_CRB_AGT_ADR = 0x50, | |
| 96 | QLCNIC_HW_EG_CRB_AGT_ADR = 0x51, | |
| 97 | QLCNIC_HW_RPMX0_CRB_AGT_ADR = 0x08 | |
| 98 | }; | |
| 99 | ||
| 100 | /* Hub 4 */ | |
| 101 | enum { | |
| 102 | QLCNIC_HW_PEGN0_CRB_AGT_ADR = 0x40, | |
| 103 | QLCNIC_HW_PEGN1_CRB_AGT_ADR, | |
| 104 | QLCNIC_HW_PEGN2_CRB_AGT_ADR, | |
| 105 | QLCNIC_HW_PEGN3_CRB_AGT_ADR, | |
| 106 | QLCNIC_HW_PEGNI_CRB_AGT_ADR, | |
| 107 | QLCNIC_HW_PEGND_CRB_AGT_ADR, | |
| 108 | QLCNIC_HW_PEGNC_CRB_AGT_ADR, | |
| 109 | QLCNIC_HW_PEGR0_CRB_AGT_ADR, | |
| 110 | QLCNIC_HW_PEGR1_CRB_AGT_ADR, | |
| 111 | QLCNIC_HW_PEGR2_CRB_AGT_ADR, | |
| 112 | QLCNIC_HW_PEGR3_CRB_AGT_ADR, | |
| 113 | QLCNIC_HW_PEGN4_CRB_AGT_ADR | |
| 114 | }; | |
| 115 | ||
| 116 | /* Hub 5 */ | |
| 117 | enum { | |
| 118 | QLCNIC_HW_PEGS0_CRB_AGT_ADR = 0x40, | |
| 119 | QLCNIC_HW_PEGS1_CRB_AGT_ADR, | |
| 120 | QLCNIC_HW_PEGS2_CRB_AGT_ADR, | |
| 121 | QLCNIC_HW_PEGS3_CRB_AGT_ADR, | |
| 122 | QLCNIC_HW_PEGSI_CRB_AGT_ADR, | |
| 123 | QLCNIC_HW_PEGSD_CRB_AGT_ADR, | |
| 124 | QLCNIC_HW_PEGSC_CRB_AGT_ADR | |
| 125 | }; | |
| 126 | ||
| 127 | /* Hub 6 */ | |
| 128 | enum { | |
| 129 | QLCNIC_HW_CAS0_CRB_AGT_ADR = 0x46, | |
| 130 | QLCNIC_HW_CAS1_CRB_AGT_ADR = 0x47, | |
| 131 | QLCNIC_HW_CAS2_CRB_AGT_ADR = 0x48, | |
| 132 | QLCNIC_HW_CAS3_CRB_AGT_ADR = 0x49, | |
| 133 | QLCNIC_HW_NCM_CRB_AGT_ADR = 0x16, | |
| 134 | QLCNIC_HW_TMR_CRB_AGT_ADR = 0x17, | |
| 135 | QLCNIC_HW_XDMA_CRB_AGT_ADR = 0x05, | |
| 136 | QLCNIC_HW_OCM0_CRB_AGT_ADR = 0x06, | |
| 137 | QLCNIC_HW_OCM1_CRB_AGT_ADR = 0x07 | |
| 138 | }; | |
| 139 | ||
| 140 | /* Floaters - non existent modules */ | |
| 141 | #define QLCNIC_HW_EFC_RPMX0_CRB_AGT_ADR 0x67 | |
| 142 | ||
| 143 | /* This field defines PCI/X adr [25:20] of agents on the CRB */ | |
| 144 | enum { | |
| 145 | QLCNIC_HW_PX_MAP_CRB_PH = 0, | |
| 146 | QLCNIC_HW_PX_MAP_CRB_PS, | |
| 147 | QLCNIC_HW_PX_MAP_CRB_MN, | |
| 148 | QLCNIC_HW_PX_MAP_CRB_MS, | |
| 149 | QLCNIC_HW_PX_MAP_CRB_PGR1, | |
| 150 | QLCNIC_HW_PX_MAP_CRB_SRE, | |
| 151 | QLCNIC_HW_PX_MAP_CRB_NIU, | |
| 152 | QLCNIC_HW_PX_MAP_CRB_QMN, | |
| 153 | QLCNIC_HW_PX_MAP_CRB_SQN0, | |
| 154 | QLCNIC_HW_PX_MAP_CRB_SQN1, | |
| 155 | QLCNIC_HW_PX_MAP_CRB_SQN2, | |
| 156 | QLCNIC_HW_PX_MAP_CRB_SQN3, | |
| 157 | QLCNIC_HW_PX_MAP_CRB_QMS, | |
| 158 | QLCNIC_HW_PX_MAP_CRB_SQS0, | |
| 159 | QLCNIC_HW_PX_MAP_CRB_SQS1, | |
| 160 | QLCNIC_HW_PX_MAP_CRB_SQS2, | |
| 161 | QLCNIC_HW_PX_MAP_CRB_SQS3, | |
| 162 | QLCNIC_HW_PX_MAP_CRB_PGN0, | |
| 163 | QLCNIC_HW_PX_MAP_CRB_PGN1, | |
| 164 | QLCNIC_HW_PX_MAP_CRB_PGN2, | |
| 165 | QLCNIC_HW_PX_MAP_CRB_PGN3, | |
| 166 | QLCNIC_HW_PX_MAP_CRB_PGND, | |
| 167 | QLCNIC_HW_PX_MAP_CRB_PGNI, | |
| 168 | QLCNIC_HW_PX_MAP_CRB_PGS0, | |
| 169 | QLCNIC_HW_PX_MAP_CRB_PGS1, | |
| 170 | QLCNIC_HW_PX_MAP_CRB_PGS2, | |
| 171 | QLCNIC_HW_PX_MAP_CRB_PGS3, | |
| 172 | QLCNIC_HW_PX_MAP_CRB_PGSD, | |
| 173 | QLCNIC_HW_PX_MAP_CRB_PGSI, | |
| 174 | QLCNIC_HW_PX_MAP_CRB_SN, | |
| 175 | QLCNIC_HW_PX_MAP_CRB_PGR2, | |
| 176 | QLCNIC_HW_PX_MAP_CRB_EG, | |
| 177 | QLCNIC_HW_PX_MAP_CRB_PH2, | |
| 178 | QLCNIC_HW_PX_MAP_CRB_PS2, | |
| 179 | QLCNIC_HW_PX_MAP_CRB_CAM, | |
| 180 | QLCNIC_HW_PX_MAP_CRB_CAS0, | |
| 181 | QLCNIC_HW_PX_MAP_CRB_CAS1, | |
| 182 | QLCNIC_HW_PX_MAP_CRB_CAS2, | |
| 183 | QLCNIC_HW_PX_MAP_CRB_C2C0, | |
| 184 | QLCNIC_HW_PX_MAP_CRB_C2C1, | |
| 185 | QLCNIC_HW_PX_MAP_CRB_TIMR, | |
| 186 | QLCNIC_HW_PX_MAP_CRB_PGR3, | |
| 187 | QLCNIC_HW_PX_MAP_CRB_RPMX1, | |
| 188 | QLCNIC_HW_PX_MAP_CRB_RPMX2, | |
| 189 | QLCNIC_HW_PX_MAP_CRB_RPMX3, | |
| 190 | QLCNIC_HW_PX_MAP_CRB_RPMX4, | |
| 191 | QLCNIC_HW_PX_MAP_CRB_RPMX5, | |
| 192 | QLCNIC_HW_PX_MAP_CRB_RPMX6, | |
| 193 | QLCNIC_HW_PX_MAP_CRB_RPMX7, | |
| 194 | QLCNIC_HW_PX_MAP_CRB_XDMA, | |
| 195 | QLCNIC_HW_PX_MAP_CRB_I2Q, | |
| 196 | QLCNIC_HW_PX_MAP_CRB_ROMUSB, | |
| 197 | QLCNIC_HW_PX_MAP_CRB_CAS3, | |
| 198 | QLCNIC_HW_PX_MAP_CRB_RPMX0, | |
| 199 | QLCNIC_HW_PX_MAP_CRB_RPMX8, | |
| 200 | QLCNIC_HW_PX_MAP_CRB_RPMX9, | |
| 201 | QLCNIC_HW_PX_MAP_CRB_OCM0, | |
| 202 | QLCNIC_HW_PX_MAP_CRB_OCM1, | |
| 203 | QLCNIC_HW_PX_MAP_CRB_SMB, | |
| 204 | QLCNIC_HW_PX_MAP_CRB_I2C0, | |
| 205 | QLCNIC_HW_PX_MAP_CRB_I2C1, | |
| 206 | QLCNIC_HW_PX_MAP_CRB_LPC, | |
| 207 | QLCNIC_HW_PX_MAP_CRB_PGNC, | |
| 208 | QLCNIC_HW_PX_MAP_CRB_PGR0 | |
| 209 | }; | |
| 210 | ||
| 211 | /* This field defines CRB adr [31:20] of the agents */ | |
| 212 | ||
| 213 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_MN \ | |
| 214 | ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MN_CRB_AGT_ADR) | |
| 215 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PH \ | |
| 216 | ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_PH_CRB_AGT_ADR) | |
| 217 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_MS \ | |
| 218 | ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MS_CRB_AGT_ADR) | |
| 219 | ||
| 220 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PS \ | |
| 221 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_PS_CRB_AGT_ADR) | |
| 222 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SS \ | |
| 223 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SS_CRB_AGT_ADR) | |
| 224 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3 \ | |
| 225 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX3_CRB_AGT_ADR) | |
| 226 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_QMS \ | |
| 227 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_QMS_CRB_AGT_ADR) | |
| 228 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS0 \ | |
| 229 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS0_CRB_AGT_ADR) | |
| 230 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS1 \ | |
| 231 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS1_CRB_AGT_ADR) | |
| 232 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS2 \ | |
| 233 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS2_CRB_AGT_ADR) | |
| 234 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS3 \ | |
| 235 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS3_CRB_AGT_ADR) | |
| 236 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C0 \ | |
| 237 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C0_CRB_AGT_ADR) | |
| 238 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C1 \ | |
| 239 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C1_CRB_AGT_ADR) | |
| 240 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2 \ | |
| 241 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX2_CRB_AGT_ADR) | |
| 242 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4 \ | |
| 243 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX4_CRB_AGT_ADR) | |
| 244 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7 \ | |
| 245 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX7_CRB_AGT_ADR) | |
| 246 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9 \ | |
| 247 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX9_CRB_AGT_ADR) | |
| 248 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SMB \ | |
| 249 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SMB_CRB_AGT_ADR) | |
| 250 | ||
| 251 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_NIU \ | |
| 252 | ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_NIU_CRB_AGT_ADR) | |
| 253 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0 \ | |
| 254 | ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C0_CRB_AGT_ADR) | |
| 255 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1 \ | |
| 256 | ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C1_CRB_AGT_ADR) | |
| 257 | ||
| 258 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SRE \ | |
| 259 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SRE_CRB_AGT_ADR) | |
| 260 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_EG \ | |
| 261 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_EG_CRB_AGT_ADR) | |
| 262 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0 \ | |
| 263 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX0_CRB_AGT_ADR) | |
| 264 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_QMN \ | |
| 265 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_QM_CRB_AGT_ADR) | |
| 266 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0 \ | |
| 267 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG0_CRB_AGT_ADR) | |
| 268 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1 \ | |
| 269 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG1_CRB_AGT_ADR) | |
| 270 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2 \ | |
| 271 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG2_CRB_AGT_ADR) | |
| 272 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3 \ | |
| 273 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG3_CRB_AGT_ADR) | |
| 274 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1 \ | |
| 275 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX1_CRB_AGT_ADR) | |
| 276 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5 \ | |
| 277 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX5_CRB_AGT_ADR) | |
| 278 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6 \ | |
| 279 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX6_CRB_AGT_ADR) | |
| 280 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8 \ | |
| 281 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX8_CRB_AGT_ADR) | |
| 282 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS0 \ | |
| 283 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS0_CRB_AGT_ADR) | |
| 284 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS1 \ | |
| 285 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS1_CRB_AGT_ADR) | |
| 286 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS2 \ | |
| 287 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS2_CRB_AGT_ADR) | |
| 288 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS3 \ | |
| 289 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS3_CRB_AGT_ADR) | |
| 290 | ||
| 291 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI \ | |
| 292 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNI_CRB_AGT_ADR) | |
| 293 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGND \ | |
| 294 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGND_CRB_AGT_ADR) | |
| 295 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0 \ | |
| 296 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN0_CRB_AGT_ADR) | |
| 297 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1 \ | |
| 298 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN1_CRB_AGT_ADR) | |
| 299 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2 \ | |
| 300 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN2_CRB_AGT_ADR) | |
| 301 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3 \ | |
| 302 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN3_CRB_AGT_ADR) | |
| 303 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4 \ | |
| 304 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN4_CRB_AGT_ADR) | |
| 305 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC \ | |
| 306 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNC_CRB_AGT_ADR) | |
| 307 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR0 \ | |
| 308 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR0_CRB_AGT_ADR) | |
| 309 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR1 \ | |
| 310 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR1_CRB_AGT_ADR) | |
| 311 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR2 \ | |
| 312 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR2_CRB_AGT_ADR) | |
| 313 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR3 \ | |
| 314 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR3_CRB_AGT_ADR) | |
| 315 | ||
| 316 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI \ | |
| 317 | ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSI_CRB_AGT_ADR) | |
| 318 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSD \ | |
| 319 | ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSD_CRB_AGT_ADR) | |
| 320 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0 \ | |
| 321 | ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS0_CRB_AGT_ADR) | |
| 322 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1 \ | |
| 323 | ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS1_CRB_AGT_ADR) | |
| 324 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2 \ | |
| 325 | ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS2_CRB_AGT_ADR) | |
| 326 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3 \ | |
| 327 | ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS3_CRB_AGT_ADR) | |
| 328 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSC \ | |
| 329 | ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSC_CRB_AGT_ADR) | |
| 330 | ||
| 331 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAM \ | |
| 332 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_NCM_CRB_AGT_ADR) | |
| 333 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR \ | |
| 334 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_TMR_CRB_AGT_ADR) | |
| 335 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA \ | |
| 336 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_XDMA_CRB_AGT_ADR) | |
| 337 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SN \ | |
| 338 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_SN_CRB_AGT_ADR) | |
| 339 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q \ | |
| 340 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_I2Q_CRB_AGT_ADR) | |
| 341 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB \ | |
| 342 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_ROMUSB_CRB_AGT_ADR) | |
| 343 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0 \ | |
| 344 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM0_CRB_AGT_ADR) | |
| 345 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM1 \ | |
| 346 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM1_CRB_AGT_ADR) | |
| 347 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_LPC \ | |
| 348 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_LPC_CRB_AGT_ADR) | |
| 349 | ||
| 350 | #define QLCNIC_SRE_MISC (QLCNIC_CRB_SRE + 0x0002c) | |
| 351 | ||
| 352 | #define QLCNIC_I2Q_CLR_PCI_HI (QLCNIC_CRB_I2Q + 0x00034) | |
| 353 | ||
| 354 | #define ROMUSB_GLB (QLCNIC_CRB_ROMUSB + 0x00000) | |
| 355 | #define ROMUSB_ROM (QLCNIC_CRB_ROMUSB + 0x10000) | |
| 356 | ||
| 357 | #define QLCNIC_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004) | |
| 358 | #define QLCNIC_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008) | |
| 359 | #define QLCNIC_ROMUSB_GLB_PAD_GPIO_I (ROMUSB_GLB + 0x000c) | |
| 360 | #define QLCNIC_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038) | |
| 361 | #define QLCNIC_ROMUSB_GLB_TEST_MUX_SEL (ROMUSB_GLB + 0x0044) | |
| 362 | #define QLCNIC_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c) | |
| 363 | #define QLCNIC_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00A8) | |
| 364 | ||
| 365 | #define QLCNIC_ROMUSB_GPIO(n) (ROMUSB_GLB + 0x60 + (4 * (n))) | |
| 366 | ||
| 367 | #define QLCNIC_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004) | |
| 368 | #define QLCNIC_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008) | |
| 369 | #define QLCNIC_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c) | |
| 370 | #define QLCNIC_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010) | |
| 371 | #define QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014) | |
| 372 | #define QLCNIC_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018) | |
| 373 | ||
| 374 | /* Lock IDs for ROM lock */ | |
| 375 | #define ROM_LOCK_DRIVER 0x0d417340 | |
| 376 | ||
| 377 | /****************************************************************************** | |
| 378 | * | |
| 379 | * Definitions specific to M25P flash | |
| 380 | * | |
| 381 | ******************************************************************************* | |
| 382 | */ | |
| 383 | ||
| 384 | /* all are 1MB windows */ | |
| 385 | ||
| 386 | #define QLCNIC_PCI_CRB_WINDOWSIZE 0x00100000 | |
| 387 | #define QLCNIC_PCI_CRB_WINDOW(A) \ | |
| 388 | (QLCNIC_PCI_CRBSPACE + (A)*QLCNIC_PCI_CRB_WINDOWSIZE) | |
| 389 | ||
| 390 | #define QLCNIC_CRB_NIU QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_NIU) | |
| 391 | #define QLCNIC_CRB_SRE QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SRE) | |
| 392 | #define QLCNIC_CRB_ROMUSB \ | |
| 393 | QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_ROMUSB) | |
| 394 | #define QLCNIC_CRB_I2Q QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2Q) | |
| 395 | #define QLCNIC_CRB_I2C0 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2C0) | |
| 396 | #define QLCNIC_CRB_SMB QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SMB) | |
| 397 | #define QLCNIC_CRB_MAX QLCNIC_PCI_CRB_WINDOW(64) | |
| 398 | ||
| 399 | #define QLCNIC_CRB_PCIX_HOST QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH) | |
| 400 | #define QLCNIC_CRB_PCIX_HOST2 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH2) | |
| 401 | #define QLCNIC_CRB_PEG_NET_0 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN0) | |
| 402 | #define QLCNIC_CRB_PEG_NET_1 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN1) | |
| 403 | #define QLCNIC_CRB_PEG_NET_2 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN2) | |
| 404 | #define QLCNIC_CRB_PEG_NET_3 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN3) | |
| 405 | #define QLCNIC_CRB_PEG_NET_4 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SQS2) | |
| 406 | #define QLCNIC_CRB_PEG_NET_D QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGND) | |
| 407 | #define QLCNIC_CRB_PEG_NET_I QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGNI) | |
| 408 | #define QLCNIC_CRB_DDR_NET QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_MN) | |
| 409 | #define QLCNIC_CRB_QDR_NET QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SN) | |
| 410 | ||
| 411 | #define QLCNIC_CRB_PCIX_MD QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PS) | |
| 412 | #define QLCNIC_CRB_PCIE QLCNIC_CRB_PCIX_MD | |
| 413 | ||
| 414 | #define ISR_INT_VECTOR (QLCNIC_PCIX_PS_REG(PCIX_INT_VECTOR)) | |
| 415 | #define ISR_INT_MASK (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK)) | |
| 416 | #define ISR_INT_MASK_SLOW (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK)) | |
| 417 | #define ISR_INT_TARGET_STATUS (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS)) | |
| 418 | #define ISR_INT_TARGET_MASK (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK)) | |
| 419 | #define ISR_INT_TARGET_STATUS_F1 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F1)) | |
| 420 | #define ISR_INT_TARGET_MASK_F1 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F1)) | |
| 421 | #define ISR_INT_TARGET_STATUS_F2 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F2)) | |
| 422 | #define ISR_INT_TARGET_MASK_F2 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F2)) | |
| 423 | #define ISR_INT_TARGET_STATUS_F3 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F3)) | |
| 424 | #define ISR_INT_TARGET_MASK_F3 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F3)) | |
| 425 | #define ISR_INT_TARGET_STATUS_F4 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F4)) | |
| 426 | #define ISR_INT_TARGET_MASK_F4 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F4)) | |
| 427 | #define ISR_INT_TARGET_STATUS_F5 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F5)) | |
| 428 | #define ISR_INT_TARGET_MASK_F5 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F5)) | |
| 429 | #define ISR_INT_TARGET_STATUS_F6 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F6)) | |
| 430 | #define ISR_INT_TARGET_MASK_F6 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F6)) | |
| 431 | #define ISR_INT_TARGET_STATUS_F7 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F7)) | |
| 432 | #define ISR_INT_TARGET_MASK_F7 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F7)) | |
| 433 | ||
| 434 | #define QLCNIC_PCI_MN_2M (0) | |
| 435 | #define QLCNIC_PCI_MS_2M (0x80000) | |
| 436 | #define QLCNIC_PCI_OCM0_2M (0x000c0000UL) | |
| 437 | #define QLCNIC_PCI_CRBSPACE (0x06000000UL) | |
| 897e8c7c DP |
438 | #define QLCNIC_PCI_CAMQM (0x04800000UL) |
| 439 | #define QLCNIC_PCI_CAMQM_END (0x04800800UL) | |
| af19b491 AKS |
440 | #define QLCNIC_PCI_2MB_SIZE (0x00200000UL) |
| 441 | #define QLCNIC_PCI_CAMQM_2M_BASE (0x000ff800UL) | |
| af19b491 AKS |
442 | |
| 443 | #define QLCNIC_CRB_CAM QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_CAM) | |
| 444 | ||
| 445 | #define QLCNIC_ADDR_DDR_NET (0x0000000000000000ULL) | |
| 446 | #define QLCNIC_ADDR_DDR_NET_MAX (0x000000000fffffffULL) | |
| 447 | #define QLCNIC_ADDR_OCM0 (0x0000000200000000ULL) | |
| 448 | #define QLCNIC_ADDR_OCM0_MAX (0x00000002000fffffULL) | |
| 449 | #define QLCNIC_ADDR_OCM1 (0x0000000200400000ULL) | |
| 450 | #define QLCNIC_ADDR_OCM1_MAX (0x00000002004fffffULL) | |
| 451 | #define QLCNIC_ADDR_QDR_NET (0x0000000300000000ULL) | |
| b47acacd | 452 | #define QLCNIC_ADDR_QDR_NET_MAX (0x0000000307ffffffULL) |
| af19b491 AKS |
453 | |
| 454 | /* | |
| 455 | * Register offsets for MN | |
| 456 | */ | |
| 457 | #define QLCNIC_MIU_CONTROL (0x000) | |
| 458 | #define QLCNIC_MIU_MN_CONTROL (QLCNIC_CRB_DDR_NET+QLCNIC_MIU_CONTROL) | |
| 459 | ||
| 460 | /* 200ms delay in each loop */ | |
| 461 | #define QLCNIC_NIU_PHY_WAITLEN 200000 | |
| 462 | /* 10 seconds before we give up */ | |
| 463 | #define QLCNIC_NIU_PHY_WAITMAX 50 | |
| 464 | #define QLCNIC_NIU_MAX_GBE_PORTS 4 | |
| 465 | #define QLCNIC_NIU_MAX_XG_PORTS 2 | |
| 466 | ||
| 467 | #define QLCNIC_NIU_MODE (QLCNIC_CRB_NIU + 0x00000) | |
| 468 | #define QLCNIC_NIU_GB_PAUSE_CTL (QLCNIC_CRB_NIU + 0x0030c) | |
| 469 | #define QLCNIC_NIU_XG_PAUSE_CTL (QLCNIC_CRB_NIU + 0x00098) | |
| 470 | ||
| 471 | #define QLCNIC_NIU_GB_MAC_CONFIG_0(I) \ | |
| 472 | (QLCNIC_CRB_NIU + 0x30000 + (I)*0x10000) | |
| 473 | #define QLCNIC_NIU_GB_MAC_CONFIG_1(I) \ | |
| 474 | (QLCNIC_CRB_NIU + 0x30004 + (I)*0x10000) | |
| 475 | ||
| 476 | ||
| 477 | #define TEST_AGT_CTRL (0x00) | |
| 478 | ||
| 479 | #define TA_CTL_START 1 | |
| 480 | #define TA_CTL_ENABLE 2 | |
| 481 | #define TA_CTL_WRITE 4 | |
| 482 | #define TA_CTL_BUSY 8 | |
| 483 | ||
| 484 | /* | |
| 485 | * Register offsets for MN | |
| 486 | */ | |
| 487 | #define MIU_TEST_AGT_BASE (0x90) | |
| 488 | ||
| 489 | #define MIU_TEST_AGT_ADDR_LO (0x04) | |
| 490 | #define MIU_TEST_AGT_ADDR_HI (0x08) | |
| 491 | #define MIU_TEST_AGT_WRDATA_LO (0x10) | |
| 492 | #define MIU_TEST_AGT_WRDATA_HI (0x14) | |
| 493 | #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x20) | |
| 494 | #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x24) | |
| 495 | #define MIU_TEST_AGT_WRDATA(i) (0x10+(0x10*((i)>>1))+(4*((i)&1))) | |
| 496 | #define MIU_TEST_AGT_RDDATA_LO (0x18) | |
| 497 | #define MIU_TEST_AGT_RDDATA_HI (0x1c) | |
| 498 | #define MIU_TEST_AGT_RDDATA_UPPER_LO (0x28) | |
| 499 | #define MIU_TEST_AGT_RDDATA_UPPER_HI (0x2c) | |
| 500 | #define MIU_TEST_AGT_RDDATA(i) (0x18+(0x10*((i)>>1))+(4*((i)&1))) | |
| 501 | ||
| 502 | #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8 | |
| 503 | #define MIU_TEST_AGT_UPPER_ADDR(off) (0) | |
| 504 | ||
| 505 | /* | |
| 506 | * Register offsets for MS | |
| 507 | */ | |
| 508 | #define SIU_TEST_AGT_BASE (0x60) | |
| 509 | ||
| 510 | #define SIU_TEST_AGT_ADDR_LO (0x04) | |
| 511 | #define SIU_TEST_AGT_ADDR_HI (0x18) | |
| 512 | #define SIU_TEST_AGT_WRDATA_LO (0x08) | |
| 513 | #define SIU_TEST_AGT_WRDATA_HI (0x0c) | |
| 514 | #define SIU_TEST_AGT_WRDATA(i) (0x08+(4*(i))) | |
| 515 | #define SIU_TEST_AGT_RDDATA_LO (0x10) | |
| 516 | #define SIU_TEST_AGT_RDDATA_HI (0x14) | |
| 517 | #define SIU_TEST_AGT_RDDATA(i) (0x10+(4*(i))) | |
| 518 | ||
| 519 | #define SIU_TEST_AGT_ADDR_MASK 0x3ffff8 | |
| 520 | #define SIU_TEST_AGT_UPPER_ADDR(off) ((off)>>22) | |
| 521 | ||
| 522 | /* XG Link status */ | |
| 523 | #define XG_LINK_UP 0x10 | |
| 524 | #define XG_LINK_DOWN 0x20 | |
| 525 | ||
| 526 | #define XG_LINK_UP_P3 0x01 | |
| 527 | #define XG_LINK_DOWN_P3 0x02 | |
| 528 | #define XG_LINK_STATE_P3_MASK 0xf | |
| 529 | #define XG_LINK_STATE_P3(pcifn, val) \ | |
| 530 | (((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3_MASK) | |
| 531 | ||
| 532 | #define P3_LINK_SPEED_MHZ 100 | |
| 533 | #define P3_LINK_SPEED_MASK 0xff | |
| 534 | #define P3_LINK_SPEED_REG(pcifn) \ | |
| 535 | (CRB_PF_LINK_SPEED_1 + (((pcifn) / 4) * 4)) | |
| 536 | #define P3_LINK_SPEED_VAL(pcifn, reg) \ | |
| 537 | (((reg) >> (8 * ((pcifn) & 0x3))) & P3_LINK_SPEED_MASK) | |
| 538 | ||
| 539 | #define QLCNIC_CAM_RAM_BASE (QLCNIC_CRB_CAM + 0x02000) | |
| 540 | #define QLCNIC_CAM_RAM(reg) (QLCNIC_CAM_RAM_BASE + (reg)) | |
| 541 | #define QLCNIC_FW_VERSION_MAJOR (QLCNIC_CAM_RAM(0x150)) | |
| 542 | #define QLCNIC_FW_VERSION_MINOR (QLCNIC_CAM_RAM(0x154)) | |
| 543 | #define QLCNIC_FW_VERSION_SUB (QLCNIC_CAM_RAM(0x158)) | |
| 544 | #define QLCNIC_ROM_LOCK_ID (QLCNIC_CAM_RAM(0x100)) | |
| 545 | #define QLCNIC_PHY_LOCK_ID (QLCNIC_CAM_RAM(0x120)) | |
| 546 | #define QLCNIC_CRB_WIN_LOCK_ID (QLCNIC_CAM_RAM(0x124)) | |
| 547 | ||
| 548 | #define NIC_CRB_BASE (QLCNIC_CAM_RAM(0x200)) | |
| 549 | #define NIC_CRB_BASE_2 (QLCNIC_CAM_RAM(0x700)) | |
| 550 | #define QLCNIC_REG(X) (NIC_CRB_BASE+(X)) | |
| 551 | #define QLCNIC_REG_2(X) (NIC_CRB_BASE_2+(X)) | |
| 552 | ||
| 553 | #define QLCNIC_CDRP_CRB_OFFSET (QLCNIC_REG(0x18)) | |
| 554 | #define QLCNIC_ARG1_CRB_OFFSET (QLCNIC_REG(0x1c)) | |
| 555 | #define QLCNIC_ARG2_CRB_OFFSET (QLCNIC_REG(0x20)) | |
| 556 | #define QLCNIC_ARG3_CRB_OFFSET (QLCNIC_REG(0x24)) | |
| 557 | #define QLCNIC_SIGN_CRB_OFFSET (QLCNIC_REG(0x28)) | |
| 558 | ||
| 559 | #define CRB_CMDPEG_STATE (QLCNIC_REG(0x50)) | |
| 560 | #define CRB_RCVPEG_STATE (QLCNIC_REG(0x13c)) | |
| 561 | ||
| 562 | #define CRB_XG_STATE_P3 (QLCNIC_REG(0x98)) | |
| 563 | #define CRB_PF_LINK_SPEED_1 (QLCNIC_REG(0xe8)) | |
| 564 | #define CRB_PF_LINK_SPEED_2 (QLCNIC_REG(0xec)) | |
| 565 | ||
| 566 | #define CRB_MPORT_MODE (QLCNIC_REG(0xc4)) | |
| 567 | #define CRB_DMA_SHIFT (QLCNIC_REG(0xcc)) | |
| 568 | ||
| 569 | #define CRB_TEMP_STATE (QLCNIC_REG(0x1b4)) | |
| 570 | ||
| 571 | #define CRB_V2P_0 (QLCNIC_REG(0x290)) | |
| 572 | #define CRB_V2P(port) (CRB_V2P_0+((port)*4)) | |
| 573 | #define CRB_DRIVER_VERSION (QLCNIC_REG(0x2a0)) | |
| 574 | ||
| 575 | #define CRB_SW_INT_MASK_0 (QLCNIC_REG(0x1d8)) | |
| 576 | #define CRB_SW_INT_MASK_1 (QLCNIC_REG(0x1e0)) | |
| 577 | #define CRB_SW_INT_MASK_2 (QLCNIC_REG(0x1e4)) | |
| 578 | #define CRB_SW_INT_MASK_3 (QLCNIC_REG(0x1e8)) | |
| 579 | ||
| 580 | #define CRB_FW_CAPABILITIES_1 (QLCNIC_CAM_RAM(0x128)) | |
| 581 | #define CRB_MAC_BLOCK_START (QLCNIC_CAM_RAM(0x1c0)) | |
| 582 | ||
| 583 | /* | |
| 584 | * capabilities register, can be used to selectively enable/disable features | |
| 585 | * for backward compability | |
| 586 | */ | |
| 587 | #define CRB_NIC_CAPABILITIES_HOST QLCNIC_REG(0x1a8) | |
| 588 | #define CRB_NIC_CAPABILITIES_FW QLCNIC_REG(0x1dc) | |
| 589 | #define CRB_NIC_MSI_MODE_HOST QLCNIC_REG(0x270) | |
| 590 | #define CRB_NIC_MSI_MODE_FW QLCNIC_REG(0x274) | |
| 591 | ||
| 592 | #define INTR_SCHEME_PERPORT 0x1 | |
| 593 | #define MSI_MODE_MULTIFUNC 0x1 | |
| 594 | ||
| 595 | /* used for ethtool tests */ | |
| 596 | #define CRB_SCRATCHPAD_TEST QLCNIC_REG(0x280) | |
| 597 | ||
| 598 | /* | |
| 599 | * CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address | |
| 600 | * which can be read by the Phantom host to get producer/consumer indexes from | |
| 601 | * Phantom/Casper. If it is not HOST_SHARED_MEMORY, then the following | |
| 602 | * registers will be used for the addresses of the ring's shared memory | |
| 603 | * on the Phantom. | |
| 604 | */ | |
| 605 | ||
| 606 | #define qlcnic_get_temp_val(x) ((x) >> 16) | |
| 607 | #define qlcnic_get_temp_state(x) ((x) & 0xffff) | |
| 608 | #define qlcnic_encode_temp(val, state) (((val) << 16) | (state)) | |
| 609 | ||
| 610 | /* | |
| 611 | * Temperature control. | |
| 612 | */ | |
| 613 | enum { | |
| 614 | QLCNIC_TEMP_NORMAL = 0x1, /* Normal operating range */ | |
| 615 | QLCNIC_TEMP_WARN, /* Sound alert, temperature getting high */ | |
| 616 | QLCNIC_TEMP_PANIC /* Fatal error, hardware has shut down. */ | |
| 617 | }; | |
| 618 | ||
| 619 | /* Lock IDs for PHY lock */ | |
| 620 | #define PHY_LOCK_DRIVER 0x44524956 | |
| 621 | ||
| 622 | /* Used for PS PCI Memory access */ | |
| 623 | #define PCIX_PS_OP_ADDR_LO (0x10000) | |
| 624 | /* via CRB (PS side only) */ | |
| 625 | #define PCIX_PS_OP_ADDR_HI (0x10004) | |
| 626 | ||
| 627 | #define PCIX_INT_VECTOR (0x10100) | |
| 628 | #define PCIX_INT_MASK (0x10104) | |
| 629 | ||
| 630 | #define PCIX_OCM_WINDOW (0x10800) | |
| 631 | #define PCIX_OCM_WINDOW_REG(func) (PCIX_OCM_WINDOW + 0x20 * (func)) | |
| 632 | ||
| 633 | #define PCIX_TARGET_STATUS (0x10118) | |
| 634 | #define PCIX_TARGET_STATUS_F1 (0x10160) | |
| 635 | #define PCIX_TARGET_STATUS_F2 (0x10164) | |
| 636 | #define PCIX_TARGET_STATUS_F3 (0x10168) | |
| 637 | #define PCIX_TARGET_STATUS_F4 (0x10360) | |
| 638 | #define PCIX_TARGET_STATUS_F5 (0x10364) | |
| 639 | #define PCIX_TARGET_STATUS_F6 (0x10368) | |
| 640 | #define PCIX_TARGET_STATUS_F7 (0x1036c) | |
| 641 | ||
| 642 | #define PCIX_TARGET_MASK (0x10128) | |
| 643 | #define PCIX_TARGET_MASK_F1 (0x10170) | |
| 644 | #define PCIX_TARGET_MASK_F2 (0x10174) | |
| 645 | #define PCIX_TARGET_MASK_F3 (0x10178) | |
| 646 | #define PCIX_TARGET_MASK_F4 (0x10370) | |
| 647 | #define PCIX_TARGET_MASK_F5 (0x10374) | |
| 648 | #define PCIX_TARGET_MASK_F6 (0x10378) | |
| 649 | #define PCIX_TARGET_MASK_F7 (0x1037c) | |
| 650 | ||
| 651 | #define PCIX_MSI_F(i) (0x13000+((i)*4)) | |
| 652 | ||
| 653 | #define QLCNIC_PCIX_PH_REG(reg) (QLCNIC_CRB_PCIE + (reg)) | |
| 654 | #define QLCNIC_PCIX_PS_REG(reg) (QLCNIC_CRB_PCIX_MD + (reg)) | |
| 655 | #define QLCNIC_PCIE_REG(reg) (QLCNIC_CRB_PCIE + (reg)) | |
| 656 | ||
| 657 | #define PCIE_SEM0_LOCK (0x1c000) | |
| 658 | #define PCIE_SEM0_UNLOCK (0x1c004) | |
| 659 | #define PCIE_SEM_LOCK(N) (PCIE_SEM0_LOCK + 8*(N)) | |
| 660 | #define PCIE_SEM_UNLOCK(N) (PCIE_SEM0_UNLOCK + 8*(N)) | |
| 661 | ||
| 662 | #define PCIE_SETUP_FUNCTION (0x12040) | |
| 663 | #define PCIE_SETUP_FUNCTION2 (0x12048) | |
| 664 | #define PCIE_MISCCFG_RC (0x1206c) | |
| 665 | #define PCIE_TGT_SPLIT_CHICKEN (0x12080) | |
| 666 | #define PCIE_CHICKEN3 (0x120c8) | |
| 667 | ||
| 668 | #define ISR_INT_STATE_REG (QLCNIC_PCIX_PS_REG(PCIE_MISCCFG_RC)) | |
| 669 | #define PCIE_MAX_MASTER_SPLIT (0x14048) | |
| 670 | ||
| 671 | #define QLCNIC_PORT_MODE_NONE 0 | |
| 672 | #define QLCNIC_PORT_MODE_XG 1 | |
| 673 | #define QLCNIC_PORT_MODE_GB 2 | |
| 674 | #define QLCNIC_PORT_MODE_802_3_AP 3 | |
| 675 | #define QLCNIC_PORT_MODE_AUTO_NEG 4 | |
| 676 | #define QLCNIC_PORT_MODE_AUTO_NEG_1G 5 | |
| 677 | #define QLCNIC_PORT_MODE_AUTO_NEG_XG 6 | |
| 678 | #define QLCNIC_PORT_MODE_ADDR (QLCNIC_CAM_RAM(0x24)) | |
| 679 | #define QLCNIC_WOL_PORT_MODE (QLCNIC_CAM_RAM(0x198)) | |
| 680 | ||
| 681 | #define QLCNIC_WOL_CONFIG_NV (QLCNIC_CAM_RAM(0x184)) | |
| 682 | #define QLCNIC_WOL_CONFIG (QLCNIC_CAM_RAM(0x188)) | |
| 683 | ||
| 684 | #define QLCNIC_PEG_TUNE_MN_PRESENT 0x1 | |
| 685 | #define QLCNIC_PEG_TUNE_CAPABILITY (QLCNIC_CAM_RAM(0x02c)) | |
| 686 | ||
| 687 | #define QLCNIC_DMA_WATCHDOG_CTRL (QLCNIC_CAM_RAM(0x14)) | |
| 688 | #define QLCNIC_PEG_ALIVE_COUNTER (QLCNIC_CAM_RAM(0xb0)) | |
| 689 | #define QLCNIC_PEG_HALT_STATUS1 (QLCNIC_CAM_RAM(0xa8)) | |
| 690 | #define QLCNIC_PEG_HALT_STATUS2 (QLCNIC_CAM_RAM(0xac)) | |
| 691 | #define QLCNIC_CRB_DEV_REF_COUNT (QLCNIC_CAM_RAM(0x138)) | |
| 692 | #define QLCNIC_CRB_DEV_STATE (QLCNIC_CAM_RAM(0x140)) | |
| 693 | ||
| 694 | #define QLCNIC_CRB_DRV_STATE (QLCNIC_CAM_RAM(0x144)) | |
| 695 | #define QLCNIC_CRB_DRV_SCRATCH (QLCNIC_CAM_RAM(0x148)) | |
| 696 | #define QLCNIC_CRB_DEV_PARTITION_INFO (QLCNIC_CAM_RAM(0x14c)) | |
| 697 | #define QLCNIC_CRB_DRV_IDC_VER (QLCNIC_CAM_RAM(0x14c)) | |
| aa5e18c0 SC |
698 | #define QLCNIC_ROM_DEV_INIT_TIMEOUT (0x3e885c) |
| 699 | #define QLCNIC_ROM_DRV_RESET_TIMEOUT (0x3e8860) | |
| af19b491 AKS |
700 | |
| 701 | /* Device State */ | |
| 702 | #define QLCNIC_DEV_COLD 1 | |
| 703 | #define QLCNIC_DEV_INITALIZING 2 | |
| 704 | #define QLCNIC_DEV_READY 3 | |
| 705 | #define QLCNIC_DEV_NEED_RESET 4 | |
| 706 | #define QLCNIC_DEV_NEED_QUISCENT 5 | |
| 707 | #define QLCNIC_DEV_FAILED 6 | |
| 708 | ||
| 709 | #define QLCNIC_RCODE_DRIVER_INFO 0x20000000 | |
| 710 | #define QLCNIC_RCODE_DRIVER_CAN_RELOAD 0x40000000 | |
| 711 | #define QLCNIC_RCODE_FATAL_ERROR 0x80000000 | |
| 712 | #define QLCNIC_FWERROR_PEGNUM(code) ((code) & 0xff) | |
| 713 | #define QLCNIC_FWERROR_CODE(code) ((code >> 8) & 0xfffff) | |
| 714 | ||
| 715 | #define FW_POLL_DELAY (2 * HZ) | |
| 716 | #define FW_FAIL_THRESH 3 | |
| 717 | #define FW_POLL_THRESH 10 | |
| 718 | ||
| 719 | #define ISR_MSI_INT_TRIGGER(FUNC) (QLCNIC_PCIX_PS_REG(PCIX_MSI_F(FUNC))) | |
| 720 | #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) | |
| 721 | ||
| 722 | /* | |
| 723 | * PCI Interrupt Vector Values. | |
| 724 | */ | |
| 725 | #define PCIX_INT_VECTOR_BIT_F0 0x0080 | |
| 726 | #define PCIX_INT_VECTOR_BIT_F1 0x0100 | |
| 727 | #define PCIX_INT_VECTOR_BIT_F2 0x0200 | |
| 728 | #define PCIX_INT_VECTOR_BIT_F3 0x0400 | |
| 729 | #define PCIX_INT_VECTOR_BIT_F4 0x0800 | |
| 730 | #define PCIX_INT_VECTOR_BIT_F5 0x1000 | |
| 731 | #define PCIX_INT_VECTOR_BIT_F6 0x2000 | |
| 732 | #define PCIX_INT_VECTOR_BIT_F7 0x4000 | |
| 733 | ||
| 734 | struct qlcnic_legacy_intr_set { | |
| 735 | u32 int_vec_bit; | |
| 736 | u32 tgt_status_reg; | |
| 737 | u32 tgt_mask_reg; | |
| 738 | u32 pci_int_reg; | |
| 739 | }; | |
| 740 | ||
| 741 | #define QLCNIC_LEGACY_INTR_CONFIG \ | |
| 742 | { \ | |
| 743 | { \ | |
| 744 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \ | |
| 745 | .tgt_status_reg = ISR_INT_TARGET_STATUS, \ | |
| 746 | .tgt_mask_reg = ISR_INT_TARGET_MASK, \ | |
| 747 | .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \ | |
| 748 | \ | |
| 749 | { \ | |
| 750 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \ | |
| 751 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \ | |
| 752 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \ | |
| 753 | .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \ | |
| 754 | \ | |
| 755 | { \ | |
| 756 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \ | |
| 757 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \ | |
| 758 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \ | |
| 759 | .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \ | |
| 760 | \ | |
| 761 | { \ | |
| 762 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \ | |
| 763 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \ | |
| 764 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \ | |
| 765 | .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \ | |
| 766 | \ | |
| 767 | { \ | |
| 768 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \ | |
| 769 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \ | |
| 770 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \ | |
| 771 | .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \ | |
| 772 | \ | |
| 773 | { \ | |
| 774 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \ | |
| 775 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \ | |
| 776 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \ | |
| 777 | .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \ | |
| 778 | \ | |
| 779 | { \ | |
| 780 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \ | |
| 781 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \ | |
| 782 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \ | |
| 783 | .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \ | |
| 784 | \ | |
| 785 | { \ | |
| 786 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \ | |
| 787 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \ | |
| 788 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \ | |
| 789 | .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \ | |
| 790 | } | |
| 791 | ||
| 792 | /* NIU REGS */ | |
| 793 | ||
| 794 | #define _qlcnic_crb_get_bit(var, bit) ((var >> bit) & 0x1) | |
| 795 | ||
| 796 | /* | |
| 797 | * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3) | |
| 798 | * | |
| 799 | * Bit 0 : enable_tx => 1:enable frame xmit, 0:disable | |
| 800 | * Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream | |
| 801 | * Bit 2 : enable_rx => 1:enable frame recv, 0:disable | |
| 802 | * Bit 3 : rx_synced => R/O: recv enable synched to recv stream | |
| 803 | * Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable | |
| 804 | * Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore | |
| 805 | * Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal | |
| 806 | * Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op | |
| 807 | * Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op | |
| 808 | * Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op | |
| 809 | * Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op | |
| 810 | * Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op | |
| 811 | */ | |
| 812 | #define qlcnic_gb_rx_flowctl(config_word) \ | |
| 813 | ((config_word) |= 1 << 5) | |
| 814 | #define qlcnic_gb_get_rx_flowctl(config_word) \ | |
| 815 | _qlcnic_crb_get_bit((config_word), 5) | |
| 816 | #define qlcnic_gb_unset_rx_flowctl(config_word) \ | |
| 817 | ((config_word) &= ~(1 << 5)) | |
| 818 | ||
| 819 | /* | |
| 820 | * NIU GB Pause Ctl Register | |
| 821 | */ | |
| 822 | ||
| 823 | #define qlcnic_gb_set_gb0_mask(config_word) \ | |
| 824 | ((config_word) |= 1 << 0) | |
| 825 | #define qlcnic_gb_set_gb1_mask(config_word) \ | |
| 826 | ((config_word) |= 1 << 2) | |
| 827 | #define qlcnic_gb_set_gb2_mask(config_word) \ | |
| 828 | ((config_word) |= 1 << 4) | |
| 829 | #define qlcnic_gb_set_gb3_mask(config_word) \ | |
| 830 | ((config_word) |= 1 << 6) | |
| 831 | ||
| 832 | #define qlcnic_gb_get_gb0_mask(config_word) \ | |
| 833 | _qlcnic_crb_get_bit((config_word), 0) | |
| 834 | #define qlcnic_gb_get_gb1_mask(config_word) \ | |
| 835 | _qlcnic_crb_get_bit((config_word), 2) | |
| 836 | #define qlcnic_gb_get_gb2_mask(config_word) \ | |
| 837 | _qlcnic_crb_get_bit((config_word), 4) | |
| 838 | #define qlcnic_gb_get_gb3_mask(config_word) \ | |
| 839 | _qlcnic_crb_get_bit((config_word), 6) | |
| 840 | ||
| 841 | #define qlcnic_gb_unset_gb0_mask(config_word) \ | |
| 842 | ((config_word) &= ~(1 << 0)) | |
| 843 | #define qlcnic_gb_unset_gb1_mask(config_word) \ | |
| 844 | ((config_word) &= ~(1 << 2)) | |
| 845 | #define qlcnic_gb_unset_gb2_mask(config_word) \ | |
| 846 | ((config_word) &= ~(1 << 4)) | |
| 847 | #define qlcnic_gb_unset_gb3_mask(config_word) \ | |
| 848 | ((config_word) &= ~(1 << 6)) | |
| 849 | ||
| 850 | /* | |
| 851 | * NIU XG Pause Ctl Register | |
| 852 | * | |
| 853 | * Bit 0 : xg0_mask => 1:disable tx pause frames | |
| 854 | * Bit 1 : xg0_request => 1:request single pause frame | |
| 855 | * Bit 2 : xg0_on_off => 1:request is pause on, 0:off | |
| 856 | * Bit 3 : xg1_mask => 1:disable tx pause frames | |
| 857 | * Bit 4 : xg1_request => 1:request single pause frame | |
| 858 | * Bit 5 : xg1_on_off => 1:request is pause on, 0:off | |
| 859 | */ | |
| 860 | ||
| 861 | #define qlcnic_xg_set_xg0_mask(config_word) \ | |
| 862 | ((config_word) |= 1 << 0) | |
| 863 | #define qlcnic_xg_set_xg1_mask(config_word) \ | |
| 864 | ((config_word) |= 1 << 3) | |
| 865 | ||
| 866 | #define qlcnic_xg_get_xg0_mask(config_word) \ | |
| 867 | _qlcnic_crb_get_bit((config_word), 0) | |
| 868 | #define qlcnic_xg_get_xg1_mask(config_word) \ | |
| 869 | _qlcnic_crb_get_bit((config_word), 3) | |
| 870 | ||
| 871 | #define qlcnic_xg_unset_xg0_mask(config_word) \ | |
| 872 | ((config_word) &= ~(1 << 0)) | |
| 873 | #define qlcnic_xg_unset_xg1_mask(config_word) \ | |
| 874 | ((config_word) &= ~(1 << 3)) | |
| 875 | ||
| 876 | /* | |
| 877 | * NIU XG Pause Ctl Register | |
| 878 | * | |
| 879 | * Bit 0 : xg0_mask => 1:disable tx pause frames | |
| 880 | * Bit 1 : xg0_request => 1:request single pause frame | |
| 881 | * Bit 2 : xg0_on_off => 1:request is pause on, 0:off | |
| 882 | * Bit 3 : xg1_mask => 1:disable tx pause frames | |
| 883 | * Bit 4 : xg1_request => 1:request single pause frame | |
| 884 | * Bit 5 : xg1_on_off => 1:request is pause on, 0:off | |
| 885 | */ | |
| 886 | ||
| 887 | /* | |
| 888 | * PHY-Specific MII control/status registers. | |
| 889 | */ | |
| 890 | #define QLCNIC_NIU_GB_MII_MGMT_ADDR_AUTONEG 4 | |
| 891 | #define QLCNIC_NIU_GB_MII_MGMT_ADDR_PHY_STATUS 17 | |
| 892 | ||
| 893 | /* | |
| 894 | * PHY-Specific Status Register (reg 17). | |
| 895 | * | |
| 896 | * Bit 0 : jabber => 1:jabber detected, 0:not | |
| 897 | * Bit 1 : polarity => 1:polarity reversed, 0:normal | |
| 898 | * Bit 2 : recvpause => 1:receive pause enabled, 0:disabled | |
| 899 | * Bit 3 : xmitpause => 1:transmit pause enabled, 0:disabled | |
| 900 | * Bit 4 : energydetect => 1:sleep, 0:active | |
| 901 | * Bit 5 : downshift => 1:downshift, 0:no downshift | |
| 902 | * Bit 6 : crossover => 1:MDIX (crossover), 0:MDI (no crossover) | |
| 903 | * Bits 7-9 : cablelen => not valid in 10Mb/s mode | |
| 904 | * 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m | |
| 905 | * Bit 10 : link => 1:link up, 0:link down | |
| 906 | * Bit 11 : resolved => 1:speed and duplex resolved, 0:not yet | |
| 907 | * Bit 12 : pagercvd => 1:page received, 0:page not received | |
| 908 | * Bit 13 : duplex => 1:full duplex, 0:half duplex | |
| 909 | * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd | |
| 910 | */ | |
| 911 | ||
| 912 | #define qlcnic_get_phy_speed(config_word) (((config_word) >> 14) & 0x03) | |
| 913 | ||
| 914 | #define qlcnic_set_phy_speed(config_word, val) \ | |
| 915 | ((config_word) |= ((val & 0x03) << 14)) | |
| 916 | #define qlcnic_set_phy_duplex(config_word) \ | |
| 917 | ((config_word) |= 1 << 13) | |
| 918 | #define qlcnic_clear_phy_duplex(config_word) \ | |
| 919 | ((config_word) &= ~(1 << 13)) | |
| 920 | ||
| 921 | #define qlcnic_get_phy_link(config_word) \ | |
| 922 | _qlcnic_crb_get_bit(config_word, 10) | |
| 923 | #define qlcnic_get_phy_duplex(config_word) \ | |
| 924 | _qlcnic_crb_get_bit(config_word, 13) | |
| 925 | ||
| 926 | #define QLCNIC_NIU_NON_PROMISC_MODE 0 | |
| 927 | #define QLCNIC_NIU_PROMISC_MODE 1 | |
| 928 | #define QLCNIC_NIU_ALLMULTI_MODE 2 | |
| 929 | ||
| 930 | struct crb_128M_2M_sub_block_map { | |
| 931 | unsigned valid; | |
| 932 | unsigned start_128M; | |
| 933 | unsigned end_128M; | |
| 934 | unsigned start_2M; | |
| 935 | }; | |
| 936 | ||
| 937 | struct crb_128M_2M_block_map{ | |
| 938 | struct crb_128M_2M_sub_block_map sub_block[16]; | |
| 939 | }; | |
| 940 | #endif /* __QLCNIC_HDR_H_ */ |