]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/qla3xxx.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tg3: Refine phylib support
[net-next-2.6.git] / drivers / net / qla3xxx.c
CommitLineData
5a4faa87
RM		 1/*
2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla3xxx for copyright and licensing details.
6 */
7
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/list.h>
13#include <linux/pci.h>
14#include <linux/dma-mapping.h>
15#include <linux/sched.h>
16#include <linux/slab.h>
17#include <linux/dmapool.h>
18#include <linux/mempool.h>
19#include <linux/spinlock.h>
20#include <linux/kthread.h>
21#include <linux/interrupt.h>
22#include <linux/errno.h>
23#include <linux/ioport.h>
24#include <linux/ip.h>
bd36b0ac 25#include <linux/in.h>
5a4faa87
RM		 26#include <linux/if_arp.h>
27#include <linux/if_ether.h>
28#include <linux/netdevice.h>
29#include <linux/etherdevice.h>
30#include <linux/ethtool.h>
31#include <linux/skbuff.h>
32#include <linux/rtnetlink.h>
33#include <linux/if_vlan.h>
5a4faa87
RM		 34#include <linux/delay.h>
35#include <linux/mm.h>
36
37#include "qla3xxx.h"
38
39#define DRV_NAME "qla3xxx"
40#define DRV_STRING "QLogic ISP3XXX Network Driver"
b08c42b2 41#define DRV_VERSION "v2.03.00-k5"
5a4faa87
RM		 42#define PFX DRV_NAME " "
43
44static const char ql3xxx_driver_name[] = DRV_NAME;
45static const char ql3xxx_driver_version[] = DRV_VERSION;
46
47MODULE_AUTHOR("QLogic Corporation");
48MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
49MODULE_LICENSE("GPL");
50MODULE_VERSION(DRV_VERSION);
51
52static const u32 default_msg
53 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
54 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
55
56static int debug = -1; /* defaults above */
57module_param(debug, int, 0);
58MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
59
60static int msi;
61module_param(msi, int, 0);
62MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
63
64static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
65 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
bd36b0ac 66 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
5a4faa87
RM		 67 /* required last entry */
68 {0,}
69};
70
71MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
72
3efedf2e
RM		 73/*
74 * These are the known PHY's which are used
75 */
76typedef enum {
77 PHY_TYPE_UNKNOWN = 0,
78 PHY_VITESSE_VSC8211,
79 PHY_AGERE_ET1011C,
80 MAX_PHY_DEV_TYPES
81} PHY_DEVICE_et;
82
83typedef struct {
9ddf7774 84 PHY_DEVICE_et phyDevice;
3efedf2e
RM		 85 u32 phyIdOUI;
86 u16 phyIdModel;
87 char *name;
88} PHY_DEVICE_INFO_t;
89
b1fc1fa9 90static const PHY_DEVICE_INFO_t PHY_DEVICES[] =
3efedf2e
RM		 91 {{PHY_TYPE_UNKNOWN, 0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
92 {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
93 {PHY_AGERE_ET1011C, 0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
94};
95
96
5a4faa87
RM		 97/*
98 * Caller must take hw_lock.
99 */
100static int ql_sem_spinlock(struct ql3_adapter *qdev,
101 u32 sem_mask, u32 sem_bits)
102{
103 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
104 u32 value;
105 unsigned int seconds = 3;
106
107 do {
108 writel((sem_mask | sem_bits),
109 &port_regs->CommonRegs.semaphoreReg);
110 value = readl(&port_regs->CommonRegs.semaphoreReg);
111 if ((value & (sem_mask >> 16)) == sem_bits)
112 return 0;
113 ssleep(1);
114 } while(--seconds);
115 return -1;
116}
117
118static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
119{
120 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
121 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
122 readl(&port_regs->CommonRegs.semaphoreReg);
123}
124
125static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
126{
127 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
128 u32 value;
129
130 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
131 value = readl(&port_regs->CommonRegs.semaphoreReg);
132 return ((value & (sem_mask >> 16)) == sem_bits);
133}
134
135/*
136 * Caller holds hw_lock.
137 */
138static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
139{
140 int i = 0;
141
142 while (1) {
143 if (!ql_sem_lock(qdev,
144 QL_DRVR_SEM_MASK,
145 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
146 * 2) << 1)) {
147 if (i < 10) {
148 ssleep(1);
149 i++;
150 } else {
151 printk(KERN_ERR PFX "%s: Timed out waiting for "
152 "driver lock...\n",
153 qdev->ndev->name);
154 return 0;
155 }
156 } else {
157 printk(KERN_DEBUG PFX
158 "%s: driver lock acquired.\n",
159 qdev->ndev->name);
160 return 1;
161 }
162 }
163}
164
165static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
166{
167 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
168
169 writel(((ISP_CONTROL_NP_MASK << 16) | page),
170 &port_regs->CommonRegs.ispControlStatus);
171 readl(&port_regs->CommonRegs.ispControlStatus);
172 qdev->current_page = page;
173}
174
175static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
176 u32 __iomem * reg)
177{
178 u32 value;
179 unsigned long hw_flags;
180
181 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
182 value = readl(reg);
183 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
184
185 return value;
186}
187
188static u32 ql_read_common_reg(struct ql3_adapter *qdev,
189 u32 __iomem * reg)
190{
191 return readl(reg);
192}
193
194static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
195{
196 u32 value;
197 unsigned long hw_flags;
198
199 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
200
201 if (qdev->current_page != 0)
202 ql_set_register_page(qdev,0);
203 value = readl(reg);
204
205 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
206 return value;
207}
208
209static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
210{
211 if (qdev->current_page != 0)
212 ql_set_register_page(qdev,0);
213 return readl(reg);
214}
215
216static void ql_write_common_reg_l(struct ql3_adapter *qdev,
ee111d11 217 u32 __iomem *reg, u32 value)
5a4faa87
RM		 218{
219 unsigned long hw_flags;
220
221 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
ee111d11 222 writel(value, reg);
5a4faa87
RM		 223 readl(reg);
224 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
225 return;
226}
227
228static void ql_write_common_reg(struct ql3_adapter *qdev,
ee111d11 229 u32 __iomem *reg, u32 value)
5a4faa87 230{
ee111d11 231 writel(value, reg);
5a4faa87
RM		 232 readl(reg);
233 return;
234}
235
80b02e59
RM		 236static void ql_write_nvram_reg(struct ql3_adapter *qdev,
237 u32 __iomem *reg, u32 value)
238{
239 writel(value, reg);
240 readl(reg);
241 udelay(1);
242 return;
243}
244
5a4faa87 245static void ql_write_page0_reg(struct ql3_adapter *qdev,
ee111d11 246 u32 __iomem *reg, u32 value)
5a4faa87
RM		 247{
248 if (qdev->current_page != 0)
249 ql_set_register_page(qdev,0);
ee111d11 250 writel(value, reg);
5a4faa87
RM		 251 readl(reg);
252 return;
253}
254
255/*
256 * Caller holds hw_lock. Only called during init.
257 */
258static void ql_write_page1_reg(struct ql3_adapter *qdev,
ee111d11 259 u32 __iomem *reg, u32 value)
5a4faa87
RM		 260{
261 if (qdev->current_page != 1)
262 ql_set_register_page(qdev,1);
ee111d11 263 writel(value, reg);
5a4faa87
RM		 264 readl(reg);
265 return;
266}
267
268/*
269 * Caller holds hw_lock. Only called during init.
270 */
271static void ql_write_page2_reg(struct ql3_adapter *qdev,
ee111d11 272 u32 __iomem *reg, u32 value)
5a4faa87
RM		 273{
274 if (qdev->current_page != 2)
275 ql_set_register_page(qdev,2);
ee111d11 276 writel(value, reg);
5a4faa87
RM		 277 readl(reg);
278 return;
279}
280
281static void ql_disable_interrupts(struct ql3_adapter *qdev)
282{
283 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
284
285 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
286 (ISP_IMR_ENABLE_INT << 16));
287
288}
289
290static void ql_enable_interrupts(struct ql3_adapter *qdev)
291{
292 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
293
294 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
295 ((0xff << 16) | ISP_IMR_ENABLE_INT));
296
297}
298
299static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
300 struct ql_rcv_buf_cb *lrg_buf_cb)
301{
0f8ab89e
BL		 302 dma_addr_t map;
303 int err;
5a4faa87
RM		 304 lrg_buf_cb->next = NULL;
305
306 if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
307 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
308 } else {
309 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
310 qdev->lrg_buf_free_tail = lrg_buf_cb;
311 }
312
313 if (!lrg_buf_cb->skb) {
cd238faa
BL		 314 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
315 qdev->lrg_buffer_len);
5a4faa87 316 if (unlikely(!lrg_buf_cb->skb)) {
cd238faa 317 printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
5a4faa87
RM		 318 qdev->ndev->name);
319 qdev->lrg_buf_skb_check++;
320 } else {
321 /*
322 * We save some space to copy the ethhdr from first
323 * buffer
324 */
325 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
326 map = pci_map_single(qdev->pdev,
327 lrg_buf_cb->skb->data,
328 qdev->lrg_buffer_len -
329 QL_HEADER_SPACE,
330 PCI_DMA_FROMDEVICE);
8d8bb39b 331 err = pci_dma_mapping_error(qdev->pdev, map);
0f8ab89e 332 if(err) {
9ddf7774 333 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
0f8ab89e
BL		 334 qdev->ndev->name, err);
335 dev_kfree_skb(lrg_buf_cb->skb);
336 lrg_buf_cb->skb = NULL;
337
338 qdev->lrg_buf_skb_check++;
339 return;
340 }
341
5a4faa87
RM		 342 lrg_buf_cb->buf_phy_addr_low =
343 cpu_to_le32(LS_64BITS(map));
344 lrg_buf_cb->buf_phy_addr_high =
345 cpu_to_le32(MS_64BITS(map));
346 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
347 pci_unmap_len_set(lrg_buf_cb, maplen,
348 qdev->lrg_buffer_len -
349 QL_HEADER_SPACE);
350 }
351 }
352
353 qdev->lrg_buf_free_count++;
354}
355
356static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
357 *qdev)
358{
359 struct ql_rcv_buf_cb *lrg_buf_cb;
360
361 if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
362 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
363 qdev->lrg_buf_free_tail = NULL;
364 qdev->lrg_buf_free_count--;
365 }
366
367 return lrg_buf_cb;
368}
369
370static u32 addrBits = EEPROM_NO_ADDR_BITS;
371static u32 dataBits = EEPROM_NO_DATA_BITS;
372
373static void fm93c56a_deselect(struct ql3_adapter *qdev);
374static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
375 unsigned short *value);
376
377/*
378 * Caller holds hw_lock.
379 */
380static void fm93c56a_select(struct ql3_adapter *qdev)
381{
382 struct ql3xxx_port_registers __iomem *port_regs =
383 qdev->mem_map_registers;
384
385 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
80b02e59 386 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87 387 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
80b02e59 388 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 389 ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
390}
391
392/*
393 * Caller holds hw_lock.
394 */
395static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
396{
397 int i;
398 u32 mask;
399 u32 dataBit;
400 u32 previousBit;
401 struct ql3xxx_port_registers __iomem *port_regs =
402 qdev->mem_map_registers;
403
404 /* Clock in a zero, then do the start bit */
80b02e59 405 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 406 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
407 AUBURN_EEPROM_DO_1);
80b02e59 408 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 409 ISP_NVRAM_MASK | qdev->
410 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
411 AUBURN_EEPROM_CLK_RISE);
80b02e59 412 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 413 ISP_NVRAM_MASK | qdev->
414 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
415 AUBURN_EEPROM_CLK_FALL);
416
417 mask = 1 << (FM93C56A_CMD_BITS - 1);
418 /* Force the previous data bit to be different */
419 previousBit = 0xffff;
420 for (i = 0; i < FM93C56A_CMD_BITS; i++) {
421 dataBit =
422 (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
423 if (previousBit != dataBit) {
424 /*
425 * If the bit changed, then change the DO state to
426 * match
427 */
80b02e59 428 ql_write_nvram_reg(qdev,
5a4faa87
RM		 429 &port_regs->CommonRegs.
430 serialPortInterfaceReg,
431 ISP_NVRAM_MASK | qdev->
432 eeprom_cmd_data | dataBit);
433 previousBit = dataBit;
434 }
80b02e59 435 ql_write_nvram_reg(qdev,
5a4faa87
RM		 436 &port_regs->CommonRegs.
437 serialPortInterfaceReg,
438 ISP_NVRAM_MASK | qdev->
439 eeprom_cmd_data | dataBit |
440 AUBURN_EEPROM_CLK_RISE);
80b02e59 441 ql_write_nvram_reg(qdev,
5a4faa87
RM		 442 &port_regs->CommonRegs.
443 serialPortInterfaceReg,
444 ISP_NVRAM_MASK | qdev->
445 eeprom_cmd_data | dataBit |
446 AUBURN_EEPROM_CLK_FALL);
447 cmd = cmd << 1;
448 }
449
450 mask = 1 << (addrBits - 1);
451 /* Force the previous data bit to be different */
452 previousBit = 0xffff;
453 for (i = 0; i < addrBits; i++) {
454 dataBit =
455 (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
456 AUBURN_EEPROM_DO_0;
457 if (previousBit != dataBit) {
458 /*
459 * If the bit changed, then change the DO state to
460 * match
461 */
80b02e59 462 ql_write_nvram_reg(qdev,
5a4faa87
RM		 463 &port_regs->CommonRegs.
464 serialPortInterfaceReg,
465 ISP_NVRAM_MASK | qdev->
466 eeprom_cmd_data | dataBit);
467 previousBit = dataBit;
468 }
80b02e59 469 ql_write_nvram_reg(qdev,
5a4faa87
RM		 470 &port_regs->CommonRegs.
471 serialPortInterfaceReg,
472 ISP_NVRAM_MASK | qdev->
473 eeprom_cmd_data | dataBit |
474 AUBURN_EEPROM_CLK_RISE);
80b02e59 475 ql_write_nvram_reg(qdev,
5a4faa87
RM		 476 &port_regs->CommonRegs.
477 serialPortInterfaceReg,
478 ISP_NVRAM_MASK | qdev->
479 eeprom_cmd_data | dataBit |
480 AUBURN_EEPROM_CLK_FALL);
481 eepromAddr = eepromAddr << 1;
482 }
483}
484
485/*
486 * Caller holds hw_lock.
487 */
488static void fm93c56a_deselect(struct ql3_adapter *qdev)
489{
490 struct ql3xxx_port_registers __iomem *port_regs =
491 qdev->mem_map_registers;
492 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
80b02e59 493 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
5a4faa87
RM		 494 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
495}
496
497/*
498 * Caller holds hw_lock.
499 */
500static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
501{
502 int i;
503 u32 data = 0;
504 u32 dataBit;
505 struct ql3xxx_port_registers __iomem *port_regs =
506 qdev->mem_map_registers;
507
508 /* Read the data bits */
509 /* The first bit is a dummy. Clock right over it. */
510 for (i = 0; i < dataBits; i++) {
80b02e59 511 ql_write_nvram_reg(qdev,
5a4faa87
RM		 512 &port_regs->CommonRegs.
513 serialPortInterfaceReg,
514 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
515 AUBURN_EEPROM_CLK_RISE);
80b02e59 516 ql_write_nvram_reg(qdev,
5a4faa87
RM		 517 &port_regs->CommonRegs.
518 serialPortInterfaceReg,
519 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
520 AUBURN_EEPROM_CLK_FALL);
521 dataBit =
522 (ql_read_common_reg
523 (qdev,
524 &port_regs->CommonRegs.
525 serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
526 data = (data << 1) | dataBit;
527 }
528 *value = (u16) data;
529}
530
531/*
532 * Caller holds hw_lock.
533 */
534static void eeprom_readword(struct ql3_adapter *qdev,
535 u32 eepromAddr, unsigned short *value)
536{
537 fm93c56a_select(qdev);
538 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
539 fm93c56a_datain(qdev, value);
540 fm93c56a_deselect(qdev);
541}
542
804d8541
AV		 543static void ql_set_mac_addr(struct net_device *ndev, u16 *addr)
544{
545 __le16 *p = (__le16 *)ndev->dev_addr;
546 p[0] = cpu_to_le16(addr[0]);
547 p[1] = cpu_to_le16(addr[1]);
548 p[2] = cpu_to_le16(addr[2]);
5a4faa87
RM		 549}
550
551static int ql_get_nvram_params(struct ql3_adapter *qdev)
552{
553 u16 *pEEPROMData;
554 u16 checksum = 0;
555 u32 index;
556 unsigned long hw_flags;
557
558 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
559
560 pEEPROMData = (u16 *) & qdev->nvram_data;
561 qdev->eeprom_cmd_data = 0;
562 if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
563 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
564 2) << 10)) {
565 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
566 __func__);
567 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
568 return -1;
569 }
570
571 for (index = 0; index < EEPROM_SIZE; index++) {
572 eeprom_readword(qdev, index, pEEPROMData);
573 checksum += *pEEPROMData;
574 pEEPROMData++;
575 }
576 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
577
578 if (checksum != 0) {
579 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
580 qdev->ndev->name, checksum);
581 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
582 return -1;
583 }
584
5a4faa87
RM		 585 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
586 return checksum;
587}
588
589static const u32 PHYAddr[2] = {
590 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
591};
592
593static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
594{
595 struct ql3xxx_port_registers __iomem *port_regs =
596 qdev->mem_map_registers;
597 u32 temp;
598 int count = 1000;
599
600 while (count) {
601 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
602 if (!(temp & MAC_MII_STATUS_BSY))
603 return 0;
604 udelay(10);
605 count--;
606 }
607 return -1;
608}
609
610static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
611{
612 struct ql3xxx_port_registers __iomem *port_regs =
613 qdev->mem_map_registers;
614 u32 scanControl;
615
616 if (qdev->numPorts > 1) {
617 /* Auto scan will cycle through multiple ports */
618 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
619 } else {
620 scanControl = MAC_MII_CONTROL_SC;
621 }
622
623 /*
624 * Scan register 1 of PHY/PETBI,
625 * Set up to scan both devices
626 * The autoscan starts from the first register, completes
627 * the last one before rolling over to the first
628 */
629 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
630 PHYAddr[0] | MII_SCAN_REGISTER);
631
632 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
633 (scanControl) |
634 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
635}
636
637static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
638{
639 u8 ret;
640 struct ql3xxx_port_registers __iomem *port_regs =
641 qdev->mem_map_registers;
642
643 /* See if scan mode is enabled before we turn it off */
644 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
645 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
646 /* Scan is enabled */
647 ret = 1;
648 } else {
649 /* Scan is disabled */
650 ret = 0;
651 }
652
653 /*
654 * When disabling scan mode you must first change the MII register
655 * address
656 */
657 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
658 PHYAddr[0] | MII_SCAN_REGISTER);
659
660 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
661 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
662 MAC_MII_CONTROL_RC) << 16));
663
664 return ret;
665}
666
667static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
3efedf2e 668 u16 regAddr, u16 value, u32 phyAddr)
5a4faa87
RM		 669{
670 struct ql3xxx_port_registers __iomem *port_regs =
671 qdev->mem_map_registers;
672 u8 scanWasEnabled;
673
674 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
675
676 if (ql_wait_for_mii_ready(qdev)) {
677 if (netif_msg_link(qdev))
678 printk(KERN_WARNING PFX
679 "%s Timed out waiting for management port to "
680 "get free before issuing command.\n",
681 qdev->ndev->name);
682 return -1;
683 }
684
685 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
3efedf2e 686 phyAddr | regAddr);
5a4faa87
RM		 687
688 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
689
690 /* Wait for write to complete 9/10/04 SJP */
691 if (ql_wait_for_mii_ready(qdev)) {
692 if (netif_msg_link(qdev))
693 printk(KERN_WARNING PFX
2450022a 694 "%s: Timed out waiting for management port to "
5a4faa87
RM		 695 "get free before issuing command.\n",
696 qdev->ndev->name);
697 return -1;
698 }
699
700 if (scanWasEnabled)
701 ql_mii_enable_scan_mode(qdev);
702
703 return 0;
704}
705
706static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
3efedf2e 707 u16 * value, u32 phyAddr)
5a4faa87
RM		 708{
709 struct ql3xxx_port_registers __iomem *port_regs =
710 qdev->mem_map_registers;
711 u8 scanWasEnabled;
712 u32 temp;
713
714 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
715
716 if (ql_wait_for_mii_ready(qdev)) {
717 if (netif_msg_link(qdev))
718 printk(KERN_WARNING PFX
719 "%s: Timed out waiting for management port to "
720 "get free before issuing command.\n",
721 qdev->ndev->name);
722 return -1;
723 }
724
725 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
3efedf2e 726 phyAddr | regAddr);
5a4faa87
RM		 727
728 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
729 (MAC_MII_CONTROL_RC << 16));
730
731 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
732 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
733
734 /* Wait for the read to complete */
735 if (ql_wait_for_mii_ready(qdev)) {
736 if (netif_msg_link(qdev))
737 printk(KERN_WARNING PFX
738 "%s: Timed out waiting for management port to "
739 "get free after issuing command.\n",
740 qdev->ndev->name);
741 return -1;
742 }
743
744 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
745 *value = (u16) temp;
746
747 if (scanWasEnabled)
748 ql_mii_enable_scan_mode(qdev);
749
750 return 0;
751}
752
753static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
754{
755 struct ql3xxx_port_registers __iomem *port_regs =
756 qdev->mem_map_registers;
757
758 ql_mii_disable_scan_mode(qdev);
759
760 if (ql_wait_for_mii_ready(qdev)) {
761 if (netif_msg_link(qdev))
762 printk(KERN_WARNING PFX
763 "%s: Timed out waiting for management port to "
764 "get free before issuing command.\n",
765 qdev->ndev->name);
766 return -1;
767 }
768
769 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
770 qdev->PHYAddr | regAddr);
771
772 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
773
774 /* Wait for write to complete. */
775 if (ql_wait_for_mii_ready(qdev)) {
776 if (netif_msg_link(qdev))
777 printk(KERN_WARNING PFX
778 "%s: Timed out waiting for management port to "
779 "get free before issuing command.\n",
780 qdev->ndev->name);
781 return -1;
782 }
783
784 ql_mii_enable_scan_mode(qdev);
785
786 return 0;
787}
788
789static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
790{
791 u32 temp;
792 struct ql3xxx_port_registers __iomem *port_regs =
793 qdev->mem_map_registers;
794
795 ql_mii_disable_scan_mode(qdev);
796
797 if (ql_wait_for_mii_ready(qdev)) {
798 if (netif_msg_link(qdev))
799 printk(KERN_WARNING PFX
800 "%s: Timed out waiting for management port to "
801 "get free before issuing command.\n",
802 qdev->ndev->name);
803 return -1;
804 }
805
806 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
807 qdev->PHYAddr | regAddr);
808
809 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
810 (MAC_MII_CONTROL_RC << 16));
811
812 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
813 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
814
815 /* Wait for the read to complete */
816 if (ql_wait_for_mii_ready(qdev)) {
817 if (netif_msg_link(qdev))
818 printk(KERN_WARNING PFX
819 "%s: Timed out waiting for management port to "
820 "get free before issuing command.\n",
821 qdev->ndev->name);
822 return -1;
823 }
824
825 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
826 *value = (u16) temp;
827
828 ql_mii_enable_scan_mode(qdev);
829
830 return 0;
831}
832
833static void ql_petbi_reset(struct ql3_adapter *qdev)
834{
835 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
836}
837
838static void ql_petbi_start_neg(struct ql3_adapter *qdev)
839{
840 u16 reg;
841
842 /* Enable Auto-negotiation sense */
843 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
844 reg |= PETBI_TBI_AUTO_SENSE;
845 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
846
847 ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
848 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
849
850 ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
851 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
852 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
853
854}
855
3efedf2e 856static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
5a4faa87
RM		 857{
858 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
3efedf2e 859 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 860}
861
3efedf2e 862static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
5a4faa87
RM		 863{
864 u16 reg;
865
866 /* Enable Auto-negotiation sense */
9ddf7774 867 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg,
3efedf2e 868 PHYAddr[qdev->mac_index]);
5a4faa87 869 reg |= PETBI_TBI_AUTO_SENSE;
9ddf7774 870 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg,
3efedf2e 871 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 872
873 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
9ddf7774 874 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
3efedf2e 875 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 876
877 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
878 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
879 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
3efedf2e 880 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 881}
882
883static void ql_petbi_init(struct ql3_adapter *qdev)
884{
885 ql_petbi_reset(qdev);
886 ql_petbi_start_neg(qdev);
887}
888
3efedf2e 889static void ql_petbi_init_ex(struct ql3_adapter *qdev)
5a4faa87 890{
3efedf2e
RM		 891 ql_petbi_reset_ex(qdev);
892 ql_petbi_start_neg_ex(qdev);
5a4faa87
RM		 893}
894
895static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
896{
897 u16 reg;
898
899 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
900 return 0;
901
902 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
903}
904
3efedf2e
RM		 905static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
906{
907 printk(KERN_INFO "%s: enabling Agere specific PHY\n", qdev->ndev->name);
908 /* power down device bit 11 = 1 */
909 ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
910 /* enable diagnostic mode bit 2 = 1 */
911 ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
912 /* 1000MB amplitude adjust (see Agere errata) */
913 ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
914 /* 1000MB amplitude adjust (see Agere errata) */
915 ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
916 /* 100MB amplitude adjust (see Agere errata) */
917 ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
918 /* 100MB amplitude adjust (see Agere errata) */
919 ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
920 /* 10MB amplitude adjust (see Agere errata) */
921 ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
922 /* 10MB amplitude adjust (see Agere errata) */
923 ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
924 /* point to hidden reg 0x2806 */
925 ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
926 /* Write new PHYAD w/bit 5 set */
927 ql_mii_write_reg_ex(qdev, 0x11, 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
9ddf7774 928 /*
3efedf2e
RM		 929 * Disable diagnostic mode bit 2 = 0
930 * Power up device bit 11 = 0
931 * Link up (on) and activity (blink)
932 */
933 ql_mii_write_reg(qdev, 0x12, 0x840a);
934 ql_mii_write_reg(qdev, 0x00, 0x1140);
935 ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
936}
937
9ddf7774 938static PHY_DEVICE_et getPhyType (struct ql3_adapter *qdev,
3efedf2e
RM		 939 u16 phyIdReg0, u16 phyIdReg1)
940{
941 PHY_DEVICE_et result = PHY_TYPE_UNKNOWN;
9ddf7774 942 u32 oui;
3efedf2e 943 u16 model;
9ddf7774 944 int i;
3efedf2e
RM		 945
946 if (phyIdReg0 == 0xffff) {
947 return result;
948 }
9ddf7774 949
3efedf2e
RM		 950 if (phyIdReg1 == 0xffff) {
951 return result;
952 }
953
954 /* oui is split between two registers */
955 oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
956
957 model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
958
959 /* Scan table for this PHY */
960 for(i = 0; i < MAX_PHY_DEV_TYPES; i++) {
961 if ((oui == PHY_DEVICES[i].phyIdOUI) && (model == PHY_DEVICES[i].phyIdModel))
962 {
963 result = PHY_DEVICES[i].phyDevice;
964
965 printk(KERN_INFO "%s: Phy: %s\n",
966 qdev->ndev->name, PHY_DEVICES[i].name);
9ddf7774 967
3efedf2e
RM		 968 break;
969 }
970 }
971
972 return result;
973}
974
5a4faa87
RM		 975static int ql_phy_get_speed(struct ql3_adapter *qdev)
976{
977 u16 reg;
978
3efedf2e
RM		 979 switch(qdev->phyType) {
980 case PHY_AGERE_ET1011C:
981 {
982 if (ql_mii_read_reg(qdev, 0x1A, &reg) < 0)
983 return 0;
984
985 reg = (reg >> 8) & 3;
986 break;
987 }
988 default:
5a4faa87
RM		 989 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
990 return 0;
991
992 reg = (((reg & 0x18) >> 3) & 3);
3efedf2e 993 }
5a4faa87 994
3efedf2e
RM		 995 switch(reg) {
996 case 2:
5a4faa87 997 return SPEED_1000;
3efedf2e 998 case 1:
5a4faa87 999 return SPEED_100;
3efedf2e 1000 case 0:
5a4faa87 1001 return SPEED_10;
3efedf2e 1002 default:
5a4faa87 1003 return -1;
3efedf2e 1004 }
5a4faa87
RM		 1005}
1006
1007static int ql_is_full_dup(struct ql3_adapter *qdev)
1008{
1009 u16 reg;
1010
3efedf2e
RM		 1011 switch(qdev->phyType) {
1012 case PHY_AGERE_ET1011C:
1013 {
1014 if (ql_mii_read_reg(qdev, 0x1A, &reg))
1015 return 0;
9ddf7774 1016
3efedf2e
RM		 1017 return ((reg & 0x0080) && (reg & 0x1000)) != 0;
1018 }
1019 case PHY_VITESSE_VSC8211:
1020 default:
1021 {
1022 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
1023 return 0;
1024 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
1025 }
1026 }
5a4faa87
RM		 1027}
1028
1029static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
1030{
1031 u16 reg;
1032
1033 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
1034 return 0;
1035
1036 return (reg & PHY_NEG_PAUSE) != 0;
1037}
1038
3efedf2e
RM		 1039static int PHY_Setup(struct ql3_adapter *qdev)
1040{
1041 u16 reg1;
1042 u16 reg2;
1043 bool agereAddrChangeNeeded = false;
1044 u32 miiAddr = 0;
1045 int err;
1046
1047 /* Determine the PHY we are using by reading the ID's */
1048 err = ql_mii_read_reg(qdev, PHY_ID_0_REG, &reg1);
1049 if(err != 0) {
1050 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1051 qdev->ndev->name);
1052 return err;
1053 }
1054
1055 err = ql_mii_read_reg(qdev, PHY_ID_1_REG, &reg2);
1056 if(err != 0) {
1057 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n",
1058 qdev->ndev->name);
1059 return err;
1060 }
1061
1062 /* Check if we have a Agere PHY */
1063 if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
1064
9ddf7774 1065 /* Determine which MII address we should be using
3efedf2e
RM		 1066 determined by the index of the card */
1067 if (qdev->mac_index == 0) {
1068 miiAddr = MII_AGERE_ADDR_1;
1069 } else {
1070 miiAddr = MII_AGERE_ADDR_2;
1071 }
9ddf7774 1072
3efedf2e
RM		 1073 err =ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, &reg1, miiAddr);
1074 if(err != 0) {
1075 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1076 qdev->ndev->name);
9ddf7774 1077 return err;
3efedf2e
RM		 1078 }
1079
1080 err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, &reg2, miiAddr);
1081 if(err != 0) {
1082 printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n",
1083 qdev->ndev->name);
1084 return err;
1085 }
9ddf7774 1086
3efedf2e 1087 /* We need to remember to initialize the Agere PHY */
9ddf7774 1088 agereAddrChangeNeeded = true;
3efedf2e
RM		 1089 }
1090
1091 /* Determine the particular PHY we have on board to apply
1092 PHY specific initializations */
1093 qdev->phyType = getPhyType(qdev, reg1, reg2);
1094
1095 if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1096 /* need this here so address gets changed */
9ddf7774 1097 phyAgereSpecificInit(qdev, miiAddr);
3efedf2e
RM		 1098 } else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
1099 printk(KERN_ERR "%s: PHY is unknown\n", qdev->ndev->name);
1100 return -EIO;
1101 }
1102
1103 return 0;
1104}
1105
5a4faa87
RM		 1106/*
1107 * Caller holds hw_lock.
1108 */
1109static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1110{
1111 struct ql3xxx_port_registers __iomem *port_regs =
1112 qdev->mem_map_registers;
1113 u32 value;
1114
1115 if (enable)
1116 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1117 else
1118 value = (MAC_CONFIG_REG_PE << 16);
1119
1120 if (qdev->mac_index)
1121 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1122 else
1123 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1124}
1125
1126/*
1127 * Caller holds hw_lock.
1128 */
1129static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1130{
1131 struct ql3xxx_port_registers __iomem *port_regs =
1132 qdev->mem_map_registers;
1133 u32 value;
1134
1135 if (enable)
1136 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1137 else
1138 value = (MAC_CONFIG_REG_SR << 16);
1139
1140 if (qdev->mac_index)
1141 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1142 else
1143 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1144}
1145
1146/*
1147 * Caller holds hw_lock.
1148 */
1149static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1150{
1151 struct ql3xxx_port_registers __iomem *port_regs =
1152 qdev->mem_map_registers;
1153 u32 value;
1154
1155 if (enable)
1156 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1157 else
1158 value = (MAC_CONFIG_REG_GM << 16);
1159
1160 if (qdev->mac_index)
1161 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1162 else
1163 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1164}
1165
1166/*
1167 * Caller holds hw_lock.
1168 */
1169static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1170{
1171 struct ql3xxx_port_registers __iomem *port_regs =
1172 qdev->mem_map_registers;
1173 u32 value;
1174
1175 if (enable)
1176 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1177 else
1178 value = (MAC_CONFIG_REG_FD << 16);
1179
1180 if (qdev->mac_index)
1181 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1182 else
1183 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1184}
1185
1186/*
1187 * Caller holds hw_lock.
1188 */
1189static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1190{
1191 struct ql3xxx_port_registers __iomem *port_regs =
1192 qdev->mem_map_registers;
1193 u32 value;
1194
1195 if (enable)
1196 value =
1197 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1198 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1199 else
1200 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1201
1202 if (qdev->mac_index)
1203 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1204 else
1205 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1206}
1207
1208/*
1209 * Caller holds hw_lock.
1210 */
1211static int ql_is_fiber(struct ql3_adapter *qdev)
1212{
1213 struct ql3xxx_port_registers __iomem *port_regs =
1214 qdev->mem_map_registers;
1215 u32 bitToCheck = 0;
1216 u32 temp;
1217
1218 switch (qdev->mac_index) {
1219 case 0:
1220 bitToCheck = PORT_STATUS_SM0;
1221 break;
1222 case 1:
1223 bitToCheck = PORT_STATUS_SM1;
1224 break;
1225 }
1226
1227 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1228 return (temp & bitToCheck) != 0;
1229}
1230
1231static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1232{
1233 u16 reg;
1234 ql_mii_read_reg(qdev, 0x00, &reg);
1235 return (reg & 0x1000) != 0;
1236}
1237
1238/*
1239 * Caller holds hw_lock.
1240 */
1241static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1242{
1243 struct ql3xxx_port_registers __iomem *port_regs =
1244 qdev->mem_map_registers;
1245 u32 bitToCheck = 0;
1246 u32 temp;
1247
1248 switch (qdev->mac_index) {
1249 case 0:
1250 bitToCheck = PORT_STATUS_AC0;
1251 break;
1252 case 1:
1253 bitToCheck = PORT_STATUS_AC1;
1254 break;
1255 }
1256
1257 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1258 if (temp & bitToCheck) {
1259 if (netif_msg_link(qdev))
1260 printk(KERN_INFO PFX
1261 "%s: Auto-Negotiate complete.\n",
1262 qdev->ndev->name);
1263 return 1;
1264 } else {
1265 if (netif_msg_link(qdev))
1266 printk(KERN_WARNING PFX
1267 "%s: Auto-Negotiate incomplete.\n",
1268 qdev->ndev->name);
1269 return 0;
1270 }
1271}
1272
1273/*
1274 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1275 */
1276static int ql_is_neg_pause(struct ql3_adapter *qdev)
1277{
1278 if (ql_is_fiber(qdev))
1279 return ql_is_petbi_neg_pause(qdev);
1280 else
1281 return ql_is_phy_neg_pause(qdev);
1282}
1283
1284static int ql_auto_neg_error(struct ql3_adapter *qdev)
1285{
1286 struct ql3xxx_port_registers __iomem *port_regs =
1287 qdev->mem_map_registers;
1288 u32 bitToCheck = 0;
1289 u32 temp;
1290
1291 switch (qdev->mac_index) {
1292 case 0:
1293 bitToCheck = PORT_STATUS_AE0;
1294 break;
1295 case 1:
1296 bitToCheck = PORT_STATUS_AE1;
1297 break;
1298 }
1299 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1300 return (temp & bitToCheck) != 0;
1301}
1302
1303static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1304{
1305 if (ql_is_fiber(qdev))
1306 return SPEED_1000;
1307 else
1308 return ql_phy_get_speed(qdev);
1309}
1310
1311static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1312{
1313 if (ql_is_fiber(qdev))
1314 return 1;
1315 else
1316 return ql_is_full_dup(qdev);
1317}
1318
1319/*
1320 * Caller holds hw_lock.
1321 */
1322static int ql_link_down_detect(struct ql3_adapter *qdev)
1323{
1324 struct ql3xxx_port_registers __iomem *port_regs =
1325 qdev->mem_map_registers;
1326 u32 bitToCheck = 0;
1327 u32 temp;
1328
1329 switch (qdev->mac_index) {
1330 case 0:
1331 bitToCheck = ISP_CONTROL_LINK_DN_0;
1332 break;
1333 case 1:
1334 bitToCheck = ISP_CONTROL_LINK_DN_1;
1335 break;
1336 }
1337
1338 temp =
1339 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1340 return (temp & bitToCheck) != 0;
1341}
1342
1343/*
1344 * Caller holds hw_lock.
1345 */
1346static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1347{
1348 struct ql3xxx_port_registers __iomem *port_regs =
1349 qdev->mem_map_registers;
1350
1351 switch (qdev->mac_index) {
1352 case 0:
1353 ql_write_common_reg(qdev,
1354 &port_regs->CommonRegs.ispControlStatus,
1355 (ISP_CONTROL_LINK_DN_0) |
1356 (ISP_CONTROL_LINK_DN_0 << 16));
1357 break;
1358
1359 case 1:
1360 ql_write_common_reg(qdev,
1361 &port_regs->CommonRegs.ispControlStatus,
1362 (ISP_CONTROL_LINK_DN_1) |
1363 (ISP_CONTROL_LINK_DN_1 << 16));
1364 break;
1365
1366 default:
1367 return 1;
1368 }
1369
1370 return 0;
1371}
1372
1373/*
1374 * Caller holds hw_lock.
1375 */
3efedf2e 1376static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
5a4faa87
RM		 1377{
1378 struct ql3xxx_port_registers __iomem *port_regs =
1379 qdev->mem_map_registers;
1380 u32 bitToCheck = 0;
1381 u32 temp;
1382
3efedf2e 1383 switch (qdev->mac_index) {
5a4faa87
RM		 1384 case 0:
1385 bitToCheck = PORT_STATUS_F1_ENABLED;
1386 break;
1387 case 1:
1388 bitToCheck = PORT_STATUS_F3_ENABLED;
1389 break;
1390 default:
1391 break;
1392 }
1393
1394 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1395 if (temp & bitToCheck) {
1396 if (netif_msg_link(qdev))
1397 printk(KERN_DEBUG PFX
1398 "%s: is not link master.\n", qdev->ndev->name);
1399 return 0;
1400 } else {
1401 if (netif_msg_link(qdev))
1402 printk(KERN_DEBUG PFX
1403 "%s: is link master.\n", qdev->ndev->name);
1404 return 1;
1405 }
1406}
1407
3efedf2e 1408static void ql_phy_reset_ex(struct ql3_adapter *qdev)
5a4faa87 1409{
9ddf7774 1410 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
3efedf2e 1411 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 1412}
1413
3efedf2e 1414static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
5a4faa87
RM		 1415{
1416 u16 reg;
3efedf2e
RM		 1417 u16 portConfiguration;
1418
1419 if(qdev->phyType == PHY_AGERE_ET1011C) {
1420 /* turn off external loopback */
9ddf7774 1421 ql_mii_write_reg(qdev, 0x13, 0x0000);
3efedf2e 1422 }
5a4faa87 1423
3efedf2e
RM		 1424 if(qdev->mac_index == 0)
1425 portConfiguration = qdev->nvram_data.macCfg_port0.portConfiguration;
1426 else
1427 portConfiguration = qdev->nvram_data.macCfg_port1.portConfiguration;
1428
1429 /* Some HBA's in the field are set to 0 and they need to
1430 be reinterpreted with a default value */
1431 if(portConfiguration == 0)
1432 portConfiguration = PORT_CONFIG_DEFAULT;
1433
1434 /* Set the 1000 advertisements */
9ddf7774 1435 ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, &reg,
3efedf2e
RM		 1436 PHYAddr[qdev->mac_index]);
1437 reg &= ~PHY_GIG_ALL_PARAMS;
1438
ad4c9a09 1439 if(portConfiguration & PORT_CONFIG_1000MB_SPEED) {
7d2e3cb7 1440 if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED)
ad4c9a09 1441 reg |= PHY_GIG_ADV_1000F;
7d2e3cb7 1442 else
ad4c9a09 1443 reg |= PHY_GIG_ADV_1000H;
3efedf2e
RM		 1444 }
1445
9ddf7774 1446 ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg,
3efedf2e
RM		 1447 PHYAddr[qdev->mac_index]);
1448
1449 /* Set the 10/100 & pause negotiation advertisements */
1450 ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, &reg,
1451 PHYAddr[qdev->mac_index]);
1452 reg &= ~PHY_NEG_ALL_PARAMS;
1453
1454 if(portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
1455 reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1456
1457 if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1458 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1459 reg |= PHY_NEG_ADV_100F;
9ddf7774 1460
3efedf2e
RM		 1461 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1462 reg |= PHY_NEG_ADV_10F;
1463 }
1464
1465 if(portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1466 if(portConfiguration & PORT_CONFIG_100MB_SPEED)
1467 reg |= PHY_NEG_ADV_100H;
9ddf7774 1468
3efedf2e
RM		 1469 if(portConfiguration & PORT_CONFIG_10MB_SPEED)
1470 reg |= PHY_NEG_ADV_10H;
1471 }
1472
1473 if(portConfiguration &
1474 PORT_CONFIG_1000MB_SPEED) {
9ddf7774 1475 reg |= 1;
3efedf2e
RM		 1476 }
1477
9ddf7774 1478 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg,
3efedf2e 1479 PHYAddr[qdev->mac_index]);
5a4faa87 1480
3efedf2e 1481 ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, PHYAddr[qdev->mac_index]);
9ddf7774
JG		 1482
1483 ql_mii_write_reg_ex(qdev, CONTROL_REG,
3efedf2e
RM		 1484 reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1485 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 1486}
1487
3efedf2e 1488static void ql_phy_init_ex(struct ql3_adapter *qdev)
5a4faa87 1489{
3efedf2e
RM		 1490 ql_phy_reset_ex(qdev);
1491 PHY_Setup(qdev);
1492 ql_phy_start_neg_ex(qdev);
5a4faa87
RM		 1493}
1494
1495/*
1496 * Caller holds hw_lock.
1497 */
1498static u32 ql_get_link_state(struct ql3_adapter *qdev)
1499{
1500 struct ql3xxx_port_registers __iomem *port_regs =
1501 qdev->mem_map_registers;
1502 u32 bitToCheck = 0;
1503 u32 temp, linkState;
1504
1505 switch (qdev->mac_index) {
1506 case 0:
1507 bitToCheck = PORT_STATUS_UP0;
1508 break;
1509 case 1:
1510 bitToCheck = PORT_STATUS_UP1;
1511 break;
1512 }
1513 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1514 if (temp & bitToCheck) {
1515 linkState = LS_UP;
1516 } else {
1517 linkState = LS_DOWN;
1518 if (netif_msg_link(qdev))
1519 printk(KERN_WARNING PFX
1520 "%s: Link is down.\n", qdev->ndev->name);
1521 }
1522 return linkState;
1523}
1524
1525static int ql_port_start(struct ql3_adapter *qdev)
1526{
1527 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1528 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3efedf2e
RM		 1529 2) << 7)) {
1530 printk(KERN_ERR "%s: Could not get hw lock for GIO\n",
1531 qdev->ndev->name);
5a4faa87 1532 return -1;
3efedf2e 1533 }
5a4faa87
RM		 1534
1535 if (ql_is_fiber(qdev)) {
1536 ql_petbi_init(qdev);
1537 } else {
1538 /* Copper port */
3efedf2e 1539 ql_phy_init_ex(qdev);
5a4faa87
RM		 1540 }
1541
1542 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1543 return 0;
1544}
1545
1546static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1547{
1548
1549 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1550 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1551 2) << 7))
1552 return -1;
1553
1554 if (!ql_auto_neg_error(qdev)) {
1555 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1556 /* configure the MAC */
1557 if (netif_msg_link(qdev))
1558 printk(KERN_DEBUG PFX
1559 "%s: Configuring link.\n",
1560 qdev->ndev->
1561 name);
1562 ql_mac_cfg_soft_reset(qdev, 1);
1563 ql_mac_cfg_gig(qdev,
1564 (ql_get_link_speed
1565 (qdev) ==
1566 SPEED_1000));
1567 ql_mac_cfg_full_dup(qdev,
1568 ql_is_link_full_dup
1569 (qdev));
1570 ql_mac_cfg_pause(qdev,
1571 ql_is_neg_pause
1572 (qdev));
1573 ql_mac_cfg_soft_reset(qdev, 0);
1574
1575 /* enable the MAC */
1576 if (netif_msg_link(qdev))
1577 printk(KERN_DEBUG PFX
1578 "%s: Enabling mac.\n",
1579 qdev->ndev->
1580 name);
1581 ql_mac_enable(qdev, 1);
1582 }
1583
1584 if (netif_msg_link(qdev))
1585 printk(KERN_DEBUG PFX
1586 "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1587 qdev->ndev->name);
1588 qdev->port_link_state = LS_UP;
1589 netif_start_queue(qdev->ndev);
1590 netif_carrier_on(qdev->ndev);
1591 if (netif_msg_link(qdev))
1592 printk(KERN_INFO PFX
1593 "%s: Link is up at %d Mbps, %s duplex.\n",
1594 qdev->ndev->name,
1595 ql_get_link_speed(qdev),
1596 ql_is_link_full_dup(qdev)
1597 ? "full" : "half");
1598
1599 } else { /* Remote error detected */
1600
1601 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1602 if (netif_msg_link(qdev))
1603 printk(KERN_DEBUG PFX
1604 "%s: Remote error detected. "
1605 "Calling ql_port_start().\n",
1606 qdev->ndev->
1607 name);
1608 /*
1609 * ql_port_start() is shared code and needs
1610 * to lock the PHY on it's own.
1611 */
1612 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1613 if(ql_port_start(qdev)) {/* Restart port */
1614 return -1;
1615 } else
1616 return 0;
1617 }
1618 }
1619 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1620 return 0;
1621}
1622
3e23b7d3 1623static void ql_link_state_machine_work(struct work_struct *work)
5a4faa87 1624{
3e23b7d3
RM		 1625 struct ql3_adapter *qdev =
1626 container_of(work, struct ql3_adapter, link_state_work.work);
1627
5a4faa87
RM		 1628 u32 curr_link_state;
1629 unsigned long hw_flags;
1630
1631 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1632
1633 curr_link_state = ql_get_link_state(qdev);
1634
1635 if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1636 if (netif_msg_link(qdev))
1637 printk(KERN_INFO PFX
1638 "%s: Reset in progress, skip processing link "
1639 "state.\n", qdev->ndev->name);
04f10773 1640
9ddf7774 1641 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3e23b7d3
RM		 1642
1643 /* Restart timer on 2 second interval. */
1644 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);\
1645
5a4faa87
RM		 1646 return;
1647 }
1648
1649 switch (qdev->port_link_state) {
1650 default:
1651 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1652 ql_port_start(qdev);
1653 }
1654 qdev->port_link_state = LS_DOWN;
1655 /* Fall Through */
1656
1657 case LS_DOWN:
1658 if (netif_msg_link(qdev))
1659 printk(KERN_DEBUG PFX
1660 "%s: port_link_state = LS_DOWN.\n",
1661 qdev->ndev->name);
1662 if (curr_link_state == LS_UP) {
1663 if (netif_msg_link(qdev))
1664 printk(KERN_DEBUG PFX
1665 "%s: curr_link_state = LS_UP.\n",
1666 qdev->ndev->name);
1667 if (ql_is_auto_neg_complete(qdev))
1668 ql_finish_auto_neg(qdev);
1669
1670 if (qdev->port_link_state == LS_UP)
1671 ql_link_down_detect_clear(qdev);
1672
1673 }
1674 break;
1675
1676 case LS_UP:
1677 /*
1678 * See if the link is currently down or went down and came
1679 * back up
1680 */
1681 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1682 if (netif_msg_link(qdev))
1683 printk(KERN_INFO PFX "%s: Link is down.\n",
1684 qdev->ndev->name);
1685 qdev->port_link_state = LS_DOWN;
1686 }
1687 break;
1688 }
1689 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3e23b7d3
RM		 1690
1691 /* Restart timer on 2 second interval. */
1692 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
5a4faa87
RM		 1693}
1694
1695/*
1696 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1697 */
1698static void ql_get_phy_owner(struct ql3_adapter *qdev)
1699{
3efedf2e 1700 if (ql_this_adapter_controls_port(qdev))
5a4faa87
RM		 1701 set_bit(QL_LINK_MASTER,&qdev->flags);
1702 else
1703 clear_bit(QL_LINK_MASTER,&qdev->flags);
1704}
1705
1706/*
1707 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1708 */
1709static void ql_init_scan_mode(struct ql3_adapter *qdev)
1710{
1711 ql_mii_enable_scan_mode(qdev);
1712
1713 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
3efedf2e
RM		 1714 if (ql_this_adapter_controls_port(qdev))
1715 ql_petbi_init_ex(qdev);
5a4faa87 1716 } else {
3efedf2e
RM		 1717 if (ql_this_adapter_controls_port(qdev))
1718 ql_phy_init_ex(qdev);
5a4faa87
RM		 1719 }
1720}
1721
1722/*
1723 * MII_Setup needs to be called before taking the PHY out of reset so that the
1724 * management interface clock speed can be set properly. It would be better if
1725 * we had a way to disable MDC until after the PHY is out of reset, but we
1726 * don't have that capability.
1727 */
1728static int ql_mii_setup(struct ql3_adapter *qdev)
1729{
1730 u32 reg;
1731 struct ql3xxx_port_registers __iomem *port_regs =
1732 qdev->mem_map_registers;
1733
1734 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1735 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1736 2) << 7))
1737 return -1;
1738
bd36b0ac 1739 if (qdev->device_id == QL3032_DEVICE_ID)
9ddf7774 1740 ql_write_page0_reg(qdev,
bd36b0ac
RM		 1741 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1742
5a4faa87
RM		 1743 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1744 reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1745
1746 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1747 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1748
1749 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1750 return 0;
1751}
1752
1753static u32 ql_supported_modes(struct ql3_adapter *qdev)
1754{
1755 u32 supported;
1756
1757 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1758 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1759 | SUPPORTED_Autoneg;
1760 } else {
1761 supported = SUPPORTED_10baseT_Half
1762 | SUPPORTED_10baseT_Full
1763 | SUPPORTED_100baseT_Half
1764 | SUPPORTED_100baseT_Full
1765 | SUPPORTED_1000baseT_Half
1766 | SUPPORTED_1000baseT_Full
1767 | SUPPORTED_Autoneg | SUPPORTED_TP;
1768 }
1769
1770 return supported;
1771}
1772
1773static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1774{
1775 int status;
1776 unsigned long hw_flags;
1777 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1778 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1779 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
04f10773
BL		 1780 2) << 7)) {
1781 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87 1782 return 0;
04f10773 1783 }
5a4faa87
RM		 1784 status = ql_is_auto_cfg(qdev);
1785 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1786 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1787 return status;
1788}
1789
1790static u32 ql_get_speed(struct ql3_adapter *qdev)
1791{
1792 u32 status;
1793 unsigned long hw_flags;
1794 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1795 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1796 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
04f10773
BL		 1797 2) << 7)) {
1798 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87 1799 return 0;
04f10773 1800 }
5a4faa87
RM		 1801 status = ql_get_link_speed(qdev);
1802 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1803 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1804 return status;
1805}
1806
1807static int ql_get_full_dup(struct ql3_adapter *qdev)
1808{
1809 int status;
1810 unsigned long hw_flags;
1811 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1812 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1813 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
04f10773
BL		 1814 2) << 7)) {
1815 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87 1816 return 0;
04f10773 1817 }
5a4faa87
RM		 1818 status = ql_is_link_full_dup(qdev);
1819 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1820 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1821 return status;
1822}
1823
1824
1825static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1826{
1827 struct ql3_adapter *qdev = netdev_priv(ndev);
1828
1829 ecmd->transceiver = XCVR_INTERNAL;
1830 ecmd->supported = ql_supported_modes(qdev);
1831
1832 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1833 ecmd->port = PORT_FIBRE;
1834 } else {
1835 ecmd->port = PORT_TP;
1836 ecmd->phy_address = qdev->PHYAddr;
1837 }
1838 ecmd->advertising = ql_supported_modes(qdev);
1839 ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1840 ecmd->speed = ql_get_speed(qdev);
1841 ecmd->duplex = ql_get_full_dup(qdev);
1842 return 0;
1843}
1844
1845static void ql_get_drvinfo(struct net_device *ndev,
1846 struct ethtool_drvinfo *drvinfo)
1847{
1848 struct ql3_adapter *qdev = netdev_priv(ndev);
1849 strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1850 strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1851 strncpy(drvinfo->fw_version, "N/A", 32);
1852 strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
5a4faa87
RM		 1853 drvinfo->regdump_len = 0;
1854 drvinfo->eedump_len = 0;
1855}
1856
1857static u32 ql_get_msglevel(struct net_device *ndev)
1858{
1859 struct ql3_adapter *qdev = netdev_priv(ndev);
1860 return qdev->msg_enable;
1861}
1862
1863static void ql_set_msglevel(struct net_device *ndev, u32 value)
1864{
1865 struct ql3_adapter *qdev = netdev_priv(ndev);
1866 qdev->msg_enable = value;
1867}
1868
ec826383
RM		 1869static void ql_get_pauseparam(struct net_device *ndev,
1870 struct ethtool_pauseparam *pause)
1871{
1872 struct ql3_adapter *qdev = netdev_priv(ndev);
1873 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1874
1875 u32 reg;
1876 if(qdev->mac_index == 0)
1877 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1878 else
1879 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1880
1881 pause->autoneg = ql_get_auto_cfg_status(qdev);
1882 pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1883 pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1884}
1885
7282d491 1886static const struct ethtool_ops ql3xxx_ethtool_ops = {
5a4faa87
RM		 1887 .get_settings = ql_get_settings,
1888 .get_drvinfo = ql_get_drvinfo,
5a4faa87
RM		 1889 .get_link = ethtool_op_get_link,
1890 .get_msglevel = ql_get_msglevel,
1891 .set_msglevel = ql_set_msglevel,
ec826383 1892 .get_pauseparam = ql_get_pauseparam,
5a4faa87
RM		 1893};
1894
1895static int ql_populate_free_queue(struct ql3_adapter *qdev)
1896{
1897 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
0f8ab89e
BL		 1898 dma_addr_t map;
1899 int err;
5a4faa87
RM		 1900
1901 while (lrg_buf_cb) {
1902 if (!lrg_buf_cb->skb) {
cd238faa
BL		 1903 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1904 qdev->lrg_buffer_len);
5a4faa87
RM		 1905 if (unlikely(!lrg_buf_cb->skb)) {
1906 printk(KERN_DEBUG PFX
cd238faa 1907 "%s: Failed netdev_alloc_skb().\n",
5a4faa87
RM		 1908 qdev->ndev->name);
1909 break;
1910 } else {
1911 /*
1912 * We save some space to copy the ethhdr from
1913 * first buffer
1914 */
1915 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1916 map = pci_map_single(qdev->pdev,
1917 lrg_buf_cb->skb->data,
1918 qdev->lrg_buffer_len -
1919 QL_HEADER_SPACE,
1920 PCI_DMA_FROMDEVICE);
0f8ab89e 1921
8d8bb39b 1922 err = pci_dma_mapping_error(qdev->pdev, map);
0f8ab89e 1923 if(err) {
9ddf7774 1924 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
0f8ab89e
BL		 1925 qdev->ndev->name, err);
1926 dev_kfree_skb(lrg_buf_cb->skb);
1927 lrg_buf_cb->skb = NULL;
1928 break;
1929 }
1930
1931
5a4faa87
RM		 1932 lrg_buf_cb->buf_phy_addr_low =
1933 cpu_to_le32(LS_64BITS(map));
1934 lrg_buf_cb->buf_phy_addr_high =
1935 cpu_to_le32(MS_64BITS(map));
1936 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1937 pci_unmap_len_set(lrg_buf_cb, maplen,
1938 qdev->lrg_buffer_len -
1939 QL_HEADER_SPACE);
1940 --qdev->lrg_buf_skb_check;
1941 if (!qdev->lrg_buf_skb_check)
1942 return 1;
1943 }
1944 }
1945 lrg_buf_cb = lrg_buf_cb->next;
1946 }
1947 return 0;
1948}
1949
f67cac01
RM		 1950/*
1951 * Caller holds hw_lock.
1952 */
1953static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1954{
1955 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1956 if (qdev->small_buf_release_cnt >= 16) {
1957 while (qdev->small_buf_release_cnt >= 16) {
1958 qdev->small_buf_q_producer_index++;
1959
1960 if (qdev->small_buf_q_producer_index ==
1961 NUM_SBUFQ_ENTRIES)
1962 qdev->small_buf_q_producer_index = 0;
1963 qdev->small_buf_release_cnt -= 8;
1964 }
1965 wmb();
1966 writel(qdev->small_buf_q_producer_index,
1967 &port_regs->CommonRegs.rxSmallQProducerIndex);
1968 }
1969}
1970
5a4faa87
RM		 1971/*
1972 * Caller holds hw_lock.
1973 */
1974static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1975{
1976 struct bufq_addr_element *lrg_buf_q_ele;
1977 int i;
1978 struct ql_rcv_buf_cb *lrg_buf_cb;
1979 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1980
1981 if ((qdev->lrg_buf_free_count >= 8)
1982 && (qdev->lrg_buf_release_cnt >= 16)) {
1983
1984 if (qdev->lrg_buf_skb_check)
1985 if (!ql_populate_free_queue(qdev))
1986 return;
1987
1988 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1989
1990 while ((qdev->lrg_buf_release_cnt >= 16)
1991 && (qdev->lrg_buf_free_count >= 8)) {
1992
1993 for (i = 0; i < 8; i++) {
1994 lrg_buf_cb =
1995 ql_get_from_lrg_buf_free_list(qdev);
1996 lrg_buf_q_ele->addr_high =
1997 lrg_buf_cb->buf_phy_addr_high;
1998 lrg_buf_q_ele->addr_low =
1999 lrg_buf_cb->buf_phy_addr_low;
2000 lrg_buf_q_ele++;
2001
2002 qdev->lrg_buf_release_cnt--;
2003 }
2004
2005 qdev->lrg_buf_q_producer_index++;
2006
1357bfcf 2007 if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
5a4faa87
RM		 2008 qdev->lrg_buf_q_producer_index = 0;
2009
2010 if (qdev->lrg_buf_q_producer_index ==
1357bfcf 2011 (qdev->num_lbufq_entries - 1)) {
5a4faa87
RM		 2012 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
2013 }
2014 }
f67cac01 2015 wmb();
5a4faa87 2016 qdev->lrg_buf_next_free = lrg_buf_q_ele;
f67cac01
RM		 2017 writel(qdev->lrg_buf_q_producer_index,
2018 &port_regs->CommonRegs.rxLargeQProducerIndex);
5a4faa87
RM		 2019 }
2020}
2021
2022static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
2023 struct ob_mac_iocb_rsp *mac_rsp)
2024{
2025 struct ql_tx_buf_cb *tx_cb;
bd36b0ac 2026 int i;
e8f4df24 2027 int retval = 0;
5a4faa87 2028
e8f4df24
BL		 2029 if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2030 printk(KERN_WARNING "Frame short but, frame was padded and sent.\n");
2031 }
9ddf7774 2032
5a4faa87 2033 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
e8f4df24
BL		 2034
2035 /* Check the transmit response flags for any errors */
2036 if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
2037 printk(KERN_ERR "Frame too short to be legal, frame not sent.\n");
2038
09f75cd7 2039 qdev->ndev->stats.tx_errors++;
e8f4df24
BL		 2040 retval = -EIO;
2041 goto frame_not_sent;
2042 }
2043
2044 if(tx_cb->seg_count == 0) {
2045 printk(KERN_ERR "tx_cb->seg_count == 0: %d\n", mac_rsp->transaction_id);
2046
09f75cd7 2047 qdev->ndev->stats.tx_errors++;
e8f4df24
BL		 2048 retval = -EIO;
2049 goto invalid_seg_count;
2050 }
2051
5a4faa87 2052 pci_unmap_single(qdev->pdev,
bd36b0ac
RM		 2053 pci_unmap_addr(&tx_cb->map[0], mapaddr),
2054 pci_unmap_len(&tx_cb->map[0], maplen),
2055 PCI_DMA_TODEVICE);
2056 tx_cb->seg_count--;
2057 if (tx_cb->seg_count) {
2058 for (i = 1; i < tx_cb->seg_count; i++) {
2059 pci_unmap_page(qdev->pdev,
2060 pci_unmap_addr(&tx_cb->map[i],
2061 mapaddr),
2062 pci_unmap_len(&tx_cb->map[i], maplen),
2063 PCI_DMA_TODEVICE);
2064 }
2065 }
09f75cd7
JG		 2066 qdev->ndev->stats.tx_packets++;
2067 qdev->ndev->stats.tx_bytes += tx_cb->skb->len;
e8f4df24
BL		 2068
2069frame_not_sent:
bd36b0ac 2070 dev_kfree_skb_irq(tx_cb->skb);
5a4faa87 2071 tx_cb->skb = NULL;
e8f4df24
BL		 2072
2073invalid_seg_count:
5a4faa87
RM		 2074 atomic_inc(&qdev->tx_count);
2075}
2076
3664006a 2077static void ql_get_sbuf(struct ql3_adapter *qdev)
97916330
RM		 2078{
2079 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
2080 qdev->small_buf_index = 0;
2081 qdev->small_buf_release_cnt++;
2082}
2083
3664006a 2084static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
97916330
RM		 2085{
2086 struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
2087 lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
2088 qdev->lrg_buf_release_cnt++;
2089 if (++qdev->lrg_buf_index == qdev->num_large_buffers)
2090 qdev->lrg_buf_index = 0;
2091 return(lrg_buf_cb);
2092}
2093
bd36b0ac
RM		 2094/*
2095 * The difference between 3022 and 3032 for inbound completions:
9ddf7774
JG		 2096 * 3022 uses two buffers per completion. The first buffer contains
2097 * (some) header info, the second the remainder of the headers plus
2098 * the data. For this chip we reserve some space at the top of the
2099 * receive buffer so that the header info in buffer one can be
2100 * prepended to the buffer two. Buffer two is the sent up while
bd36b0ac 2101 * buffer one is returned to the hardware to be reused.
9ddf7774 2102 * 3032 receives all of it's data and headers in one buffer for a
bd36b0ac
RM		 2103 * simpler process. 3032 also supports checksum verification as
2104 * can be seen in ql_process_macip_rx_intr().
2105 */
5a4faa87
RM		 2106static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
2107 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2108{
5a4faa87
RM		 2109 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2110 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
5a4faa87
RM		 2111 struct sk_buff *skb;
2112 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2113
2114 /*
2115 * Get the inbound address list (small buffer).
2116 */
97916330 2117 ql_get_sbuf(qdev);
5a4faa87 2118
97916330
RM		 2119 if (qdev->device_id == QL3022_DEVICE_ID)
2120 lrg_buf_cb1 = ql_get_lbuf(qdev);
5a4faa87
RM		 2121
2122 /* start of second buffer */
97916330 2123 lrg_buf_cb2 = ql_get_lbuf(qdev);
5a4faa87
RM		 2124 skb = lrg_buf_cb2->skb;
2125
09f75cd7
JG		 2126 qdev->ndev->stats.rx_packets++;
2127 qdev->ndev->stats.rx_bytes += length;
5a4faa87
RM		 2128
2129 skb_put(skb, length);
2130 pci_unmap_single(qdev->pdev,
2131 pci_unmap_addr(lrg_buf_cb2, mapaddr),
2132 pci_unmap_len(lrg_buf_cb2, maplen),
2133 PCI_DMA_FROMDEVICE);
2134 prefetch(skb->data);
5a4faa87
RM		 2135 skb->ip_summed = CHECKSUM_NONE;
2136 skb->protocol = eth_type_trans(skb, qdev->ndev);
2137
2138 netif_receive_skb(skb);
2139 qdev->ndev->last_rx = jiffies;
2140 lrg_buf_cb2->skb = NULL;
2141
bd36b0ac
RM		 2142 if (qdev->device_id == QL3022_DEVICE_ID)
2143 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
5a4faa87
RM		 2144 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2145}
2146
2147static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2148 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2149{
5a4faa87
RM		 2150 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2151 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
bd36b0ac 2152 struct sk_buff *skb1 = NULL, *skb2;
5a4faa87
RM		 2153 struct net_device *ndev = qdev->ndev;
2154 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2155 u16 size = 0;
2156
2157 /*
2158 * Get the inbound address list (small buffer).
2159 */
2160
97916330 2161 ql_get_sbuf(qdev);
5a4faa87 2162
bd36b0ac
RM		 2163 if (qdev->device_id == QL3022_DEVICE_ID) {
2164 /* start of first buffer on 3022 */
97916330 2165 lrg_buf_cb1 = ql_get_lbuf(qdev);
bd36b0ac 2166 skb1 = lrg_buf_cb1->skb;
bd36b0ac
RM		 2167 size = ETH_HLEN;
2168 if (*((u16 *) skb1->data) != 0xFFFF)
2169 size += VLAN_ETH_HLEN - ETH_HLEN;
2170 }
5a4faa87
RM		 2171
2172 /* start of second buffer */
97916330 2173 lrg_buf_cb2 = ql_get_lbuf(qdev);
5a4faa87 2174 skb2 = lrg_buf_cb2->skb;
5a4faa87 2175
5a4faa87
RM		 2176 skb_put(skb2, length); /* Just the second buffer length here. */
2177 pci_unmap_single(qdev->pdev,
2178 pci_unmap_addr(lrg_buf_cb2, mapaddr),
2179 pci_unmap_len(lrg_buf_cb2, maplen),
2180 PCI_DMA_FROMDEVICE);
2181 prefetch(skb2->data);
2182
5a4faa87 2183 skb2->ip_summed = CHECKSUM_NONE;
bd36b0ac
RM		 2184 if (qdev->device_id == QL3022_DEVICE_ID) {
2185 /*
2186 * Copy the ethhdr from first buffer to second. This
2187 * is necessary for 3022 IP completions.
2188 */
d626f62b
ACM		 2189 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
2190 skb_push(skb2, size), size);
bd36b0ac
RM		 2191 } else {
2192 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
9ddf7774
JG		 2193 if (checksum &
2194 (IB_IP_IOCB_RSP_3032_ICE |
2195 IB_IP_IOCB_RSP_3032_CE)) {
bd36b0ac
RM		 2196 printk(KERN_ERR
2197 "%s: Bad checksum for this %s packet, checksum = %x.\n",
2198 __func__,
9ddf7774 2199 ((checksum &
bd36b0ac
RM		 2200 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
2201 "UDP"),checksum);
b3b1514c
RM		 2202 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2203 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
2204 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
bd36b0ac 2205 skb2->ip_summed = CHECKSUM_UNNECESSARY;
b3b1514c 2206 }
bd36b0ac 2207 }
5a4faa87
RM		 2208 skb2->protocol = eth_type_trans(skb2, qdev->ndev);
2209
2210 netif_receive_skb(skb2);
09f75cd7
JG		 2211 ndev->stats.rx_packets++;
2212 ndev->stats.rx_bytes += length;
5a4faa87
RM		 2213 ndev->last_rx = jiffies;
2214 lrg_buf_cb2->skb = NULL;
2215
bd36b0ac
RM		 2216 if (qdev->device_id == QL3022_DEVICE_ID)
2217 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
5a4faa87
RM		 2218 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2219}
2220
2221static int ql_tx_rx_clean(struct ql3_adapter *qdev,
2222 int *tx_cleaned, int *rx_cleaned, int work_to_do)
2223{
5a4faa87
RM		 2224 struct net_rsp_iocb *net_rsp;
2225 struct net_device *ndev = qdev->ndev;
63b66d12 2226 int work_done = 0;
5a4faa87
RM		 2227
2228 /* While there are entries in the completion queue. */
f67cac01 2229 while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
63b66d12 2230 qdev->rsp_consumer_index) && (work_done < work_to_do)) {
5a4faa87
RM		 2231
2232 net_rsp = qdev->rsp_current;
b323e0e4 2233 rmb();
50626297
RM		 2234 /*
2235 * Fix 4032 chipe undocumented "feature" where bit-8 is set if the
2236 * inbound completion is for a VLAN.
2237 */
2238 if (qdev->device_id == QL3032_DEVICE_ID)
2239 net_rsp->opcode &= 0x7f;
5a4faa87
RM		 2240 switch (net_rsp->opcode) {
2241
2242 case OPCODE_OB_MAC_IOCB_FN0:
2243 case OPCODE_OB_MAC_IOCB_FN2:
2244 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
2245 net_rsp);
2246 (*tx_cleaned)++;
2247 break;
2248
2249 case OPCODE_IB_MAC_IOCB:
bd36b0ac 2250 case OPCODE_IB_3032_MAC_IOCB:
5a4faa87
RM		 2251 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2252 net_rsp);
2253 (*rx_cleaned)++;
2254 break;
2255
2256 case OPCODE_IB_IP_IOCB:
bd36b0ac 2257 case OPCODE_IB_3032_IP_IOCB:
5a4faa87
RM		 2258 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2259 net_rsp);
2260 (*rx_cleaned)++;
2261 break;
2262 default:
2263 {
2264 u32 *tmp = (u32 *) net_rsp;
2265 printk(KERN_ERR PFX
2266 "%s: Hit default case, not "
2267 "handled!\n"
2268 " dropping the packet, opcode = "
2269 "%x.\n",
2270 ndev->name, net_rsp->opcode);
2271 printk(KERN_ERR PFX
2272 "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
2273 (unsigned long int)tmp[0],
2274 (unsigned long int)tmp[1],
2275 (unsigned long int)tmp[2],
2276 (unsigned long int)tmp[3]);
2277 }
2278 }
2279
2280 qdev->rsp_consumer_index++;
2281
2282 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2283 qdev->rsp_consumer_index = 0;
2284 qdev->rsp_current = qdev->rsp_q_virt_addr;
2285 } else {
2286 qdev->rsp_current++;
2287 }
63b66d12
RM		 2288
2289 work_done = *tx_cleaned + *rx_cleaned;
5a4faa87
RM		 2290 }
2291
f67cac01 2292 return work_done;
5a4faa87
RM		 2293}
2294
bea3348e 2295static int ql_poll(struct napi_struct *napi, int budget)
5a4faa87 2296{
bea3348e
SH		 2297 struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi);
2298 struct net_device *ndev = qdev->ndev;
5a4faa87 2299 int rx_cleaned = 0, tx_cleaned = 0;
63b66d12
RM		 2300 unsigned long hw_flags;
2301 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
5a4faa87 2302
bea3348e 2303 ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, budget);
5a4faa87 2304
4ec24119 2305 if (tx_cleaned + rx_cleaned != budget) {
63b66d12 2306 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
bea3348e 2307 __netif_rx_complete(ndev, napi);
f67cac01
RM		 2308 ql_update_small_bufq_prod_index(qdev);
2309 ql_update_lrg_bufq_prod_index(qdev);
2310 writel(qdev->rsp_consumer_index,
2311 &port_regs->CommonRegs.rspQConsumerIndex);
63b66d12
RM		 2312 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2313
5a4faa87 2314 ql_enable_interrupts(qdev);
5a4faa87 2315 }
bea3348e 2316 return tx_cleaned + rx_cleaned;
5a4faa87
RM		 2317}
2318
7d12e780 2319static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
5a4faa87
RM		 2320{
2321
2322 struct net_device *ndev = dev_id;
2323 struct ql3_adapter *qdev = netdev_priv(ndev);
2324 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2325 u32 value;
2326 int handled = 1;
2327 u32 var;
2328
2329 port_regs = qdev->mem_map_registers;
2330
2331 value =
2332 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2333
2334 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2335 spin_lock(&qdev->adapter_lock);
2336 netif_stop_queue(qdev->ndev);
2337 netif_carrier_off(qdev->ndev);
2338 ql_disable_interrupts(qdev);
2339 qdev->port_link_state = LS_DOWN;
2340 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2341
2342 if (value & ISP_CONTROL_FE) {
2343 /*
2344 * Chip Fatal Error.
2345 */
2346 var =
2347 ql_read_page0_reg_l(qdev,
2348 &port_regs->PortFatalErrStatus);
2349 printk(KERN_WARNING PFX
2350 "%s: Resetting chip. PortFatalErrStatus "
2351 "register = 0x%x\n", ndev->name, var);
2352 set_bit(QL_RESET_START,&qdev->flags) ;
2353 } else {
2354 /*
2355 * Soft Reset Requested.
2356 */
2357 set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2358 printk(KERN_ERR PFX
2359 "%s: Another function issued a reset to the "
2360 "chip. ISR value = %x.\n", ndev->name, value);
2361 }
c4028958 2362 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
5a4faa87
RM		 2363 spin_unlock(&qdev->adapter_lock);
2364 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
e8f4df24 2365 ql_disable_interrupts(qdev);
bea3348e
SH		 2366 if (likely(netif_rx_schedule_prep(ndev, &qdev->napi))) {
2367 __netif_rx_schedule(ndev, &qdev->napi);
63b66d12 2368 }
5a4faa87
RM		 2369 } else {
2370 return IRQ_NONE;
2371 }
2372
2373 return IRQ_RETVAL(handled);
2374}
2375
bd36b0ac 2376/*
9ddf7774 2377 * Get the total number of segments needed for the
bd36b0ac
RM		 2378 * given number of fragments. This is necessary because
2379 * outbound address lists (OAL) will be used when more than
9ddf7774 2380 * two frags are given. Each address list has 5 addr/len
bd36b0ac 2381 * pairs. The 5th pair in each AOL is used to point to
9ddf7774 2382 * the next AOL if more frags are coming.
bd36b0ac
RM		 2383 * That is why the frags:segment count ratio is not linear.
2384 */
e8f4df24
BL		 2385static int ql_get_seg_count(struct ql3_adapter *qdev,
2386 unsigned short frags)
bd36b0ac 2387{
e8f4df24
BL		 2388 if (qdev->device_id == QL3022_DEVICE_ID)
2389 return 1;
2390
bd36b0ac
RM		 2391 switch(frags) {
2392 case 0: return 1; /* just the skb->data seg */
2393 case 1: return 2; /* skb->data + 1 frag */
2394 case 2: return 3; /* skb->data + 2 frags */
2395 case 3: return 5; /* skb->data + 1 frag + 1 AOL containting 2 frags */
2396 case 4: return 6;
2397 case 5: return 7;
2398 case 6: return 8;
2399 case 7: return 10;
2400 case 8: return 11;
2401 case 9: return 12;
2402 case 10: return 13;
2403 case 11: return 15;
2404 case 12: return 16;
2405 case 13: return 17;
2406 case 14: return 18;
2407 case 15: return 20;
2408 case 16: return 21;
2409 case 17: return 22;
2410 case 18: return 23;
2411 }
2412 return -1;
2413}
2414
91e745aa 2415static void ql_hw_csum_setup(const struct sk_buff *skb,
bd36b0ac
RM		 2416 struct ob_mac_iocb_req *mac_iocb_ptr)
2417{
91e745aa 2418 const struct iphdr *ip = ip_hdr(skb);
bd36b0ac 2419
91e745aa
SH		 2420 mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2421 mac_iocb_ptr->ip_hdr_len = ip->ihl;
bd36b0ac 2422
91e745aa
SH		 2423 if (ip->protocol == IPPROTO_TCP) {
2424 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
3e71f6dd 2425 OB_3032MAC_IOCB_REQ_IC;
91e745aa
SH		 2426 } else {
2427 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
3e71f6dd 2428 OB_3032MAC_IOCB_REQ_IC;
bd36b0ac 2429 }
91e745aa 2430
bd36b0ac
RM		 2431}
2432
2433/*
3e71f6dd
RM		 2434 * Map the buffers for this transmit. This will return
2435 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
bd36b0ac 2436 */
3e71f6dd
RM		 2437static int ql_send_map(struct ql3_adapter *qdev,
2438 struct ob_mac_iocb_req *mac_iocb_ptr,
2439 struct ql_tx_buf_cb *tx_cb,
2440 struct sk_buff *skb)
5a4faa87 2441{
bd36b0ac
RM		 2442 struct oal *oal;
2443 struct oal_entry *oal_entry;
63f77926 2444 int len = skb_headlen(skb);
0f8ab89e
BL		 2445 dma_addr_t map;
2446 int err;
2447 int completed_segs, i;
bd36b0ac
RM		 2448 int seg_cnt, seg = 0;
2449 int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
5a4faa87 2450
b6967eb9 2451 seg_cnt = tx_cb->seg_count;
3e71f6dd
RM		 2452 /*
2453 * Map the skb buffer first.
2454 */
bd36b0ac 2455 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
0f8ab89e 2456
8d8bb39b 2457 err = pci_dma_mapping_error(qdev->pdev, map);
0f8ab89e 2458 if(err) {
9ddf7774 2459 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
0f8ab89e
BL		 2460 qdev->ndev->name, err);
2461
2462 return NETDEV_TX_BUSY;
2463 }
9ddf7774 2464
bd36b0ac
RM		 2465 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2466 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2467 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2468 oal_entry->len = cpu_to_le32(len);
2469 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2470 pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2471 seg++;
2472
e8f4df24 2473 if (seg_cnt == 1) {
bd36b0ac 2474 /* Terminate the last segment. */
b39b5a2b 2475 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
bd36b0ac 2476 } else {
bd36b0ac 2477 oal = tx_cb->oal;
0f8ab89e
BL		 2478 for (completed_segs=0; completed_segs<frag_cnt; completed_segs++,seg++) {
2479 skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
bd36b0ac
RM		 2480 oal_entry++;
2481 if ((seg == 2 && seg_cnt > 3) || /* Check for continuation */
2482 (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */
2483 (seg == 12 && seg_cnt > 13) || /* but necessary. */
2484 (seg == 17 && seg_cnt > 18)) {
2485 /* Continuation entry points to outbound address list. */
2486 map = pci_map_single(qdev->pdev, oal,
2487 sizeof(struct oal),
2488 PCI_DMA_TODEVICE);
0f8ab89e 2489
8d8bb39b 2490 err = pci_dma_mapping_error(qdev->pdev, map);
0f8ab89e
BL		 2491 if(err) {
2492
9ddf7774 2493 printk(KERN_ERR "%s: PCI mapping outbound address list with error: %d\n",
0f8ab89e
BL		 2494 qdev->ndev->name, err);
2495 goto map_error;
2496 }
2497
bd36b0ac
RM		 2498 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2499 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2500 oal_entry->len =
2501 cpu_to_le32(sizeof(struct oal) |
2502 OAL_CONT_ENTRY);
2503 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2504 map);
2505 pci_unmap_len_set(&tx_cb->map[seg], maplen,
b6967eb9 2506 sizeof(struct oal));
bd36b0ac
RM		 2507 oal_entry = (struct oal_entry *)oal;
2508 oal++;
2509 seg++;
2510 }
5a4faa87 2511
bd36b0ac
RM		 2512 map =
2513 pci_map_page(qdev->pdev, frag->page,
2514 frag->page_offset, frag->size,
2515 PCI_DMA_TODEVICE);
0f8ab89e 2516
8d8bb39b 2517 err = pci_dma_mapping_error(qdev->pdev, map);
0f8ab89e 2518 if(err) {
9ddf7774 2519 printk(KERN_ERR "%s: PCI mapping frags failed with error: %d\n",
0f8ab89e
BL		 2520 qdev->ndev->name, err);
2521 goto map_error;
2522 }
2523
bd36b0ac
RM		 2524 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2525 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2526 oal_entry->len = cpu_to_le32(frag->size);
2527 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2528 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2529 frag->size);
2530 }
2531 /* Terminate the last segment. */
b39b5a2b 2532 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
bd36b0ac 2533 }
0f8ab89e 2534
3e71f6dd 2535 return NETDEV_TX_OK;
0f8ab89e
BL		 2536
2537map_error:
2538 /* A PCI mapping failed and now we will need to back out
9ddf7774 2539 * We need to traverse through the oal's and associated pages which
0f8ab89e
BL		 2540 * have been mapped and now we must unmap them to clean up properly
2541 */
9ddf7774 2542
0f8ab89e
BL		 2543 seg = 1;
2544 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2545 oal = tx_cb->oal;
2546 for (i=0; i<completed_segs; i++,seg++) {
2547 oal_entry++;
2548
2549 if((seg == 2 && seg_cnt > 3) || /* Check for continuation */
2550 (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */
2551 (seg == 12 && seg_cnt > 13) || /* but necessary. */
2552 (seg == 17 && seg_cnt > 18)) {
2553 pci_unmap_single(qdev->pdev,
2554 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2555 pci_unmap_len(&tx_cb->map[seg], maplen),
2556 PCI_DMA_TODEVICE);
2557 oal++;
2558 seg++;
2559 }
2560
2561 pci_unmap_page(qdev->pdev,
2562 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2563 pci_unmap_len(&tx_cb->map[seg], maplen),
2564 PCI_DMA_TODEVICE);
2565 }
2566
2567 pci_unmap_single(qdev->pdev,
2568 pci_unmap_addr(&tx_cb->map[0], mapaddr),
2569 pci_unmap_addr(&tx_cb->map[0], maplen),
2570 PCI_DMA_TODEVICE);
2571
2572 return NETDEV_TX_BUSY;
2573
3e71f6dd
RM		 2574}
2575
2576/*
2577 * The difference between 3022 and 3032 sends:
2578 * 3022 only supports a simple single segment transmission.
2579 * 3032 supports checksumming and scatter/gather lists (fragments).
9ddf7774
JG		 2580 * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2581 * in the IOCB plus a chain of outbound address lists (OAL) that
2582 * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
2583 * will used to point to an OAL when more ALP entries are required.
2584 * The IOCB is always the top of the chain followed by one or more
3e71f6dd
RM		 2585 * OALs (when necessary).
2586 */
2587static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2588{
2589 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2590 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2591 struct ql_tx_buf_cb *tx_cb;
2592 u32 tot_len = skb->len;
2593 struct ob_mac_iocb_req *mac_iocb_ptr;
2594
2595 if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
3e71f6dd
RM		 2596 return NETDEV_TX_BUSY;
2597 }
9ddf7774 2598
3e71f6dd 2599 tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
e8f4df24
BL		 2600 if((tx_cb->seg_count = ql_get_seg_count(qdev,
2601 (skb_shinfo(skb)->nr_frags))) == -1) {
3e71f6dd
RM		 2602 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2603 return NETDEV_TX_OK;
2604 }
9ddf7774 2605
3e71f6dd 2606 mac_iocb_ptr = tx_cb->queue_entry;
d8a759ff 2607 memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
3e71f6dd
RM		 2608 mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2609 mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2610 mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2611 mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2612 mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2613 tx_cb->skb = skb;
e8f4df24
BL		 2614 if (qdev->device_id == QL3032_DEVICE_ID &&
2615 skb->ip_summed == CHECKSUM_PARTIAL)
3e71f6dd 2616 ql_hw_csum_setup(skb, mac_iocb_ptr);
9ddf7774 2617
3e71f6dd
RM		 2618 if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) {
2619 printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__);
2620 return NETDEV_TX_BUSY;
2621 }
9ddf7774 2622
bd36b0ac 2623 wmb();
5a4faa87
RM		 2624 qdev->req_producer_index++;
2625 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2626 qdev->req_producer_index = 0;
2627 wmb();
2628 ql_write_common_reg_l(qdev,
ee111d11 2629 &port_regs->CommonRegs.reqQProducerIndex,
5a4faa87
RM		 2630 qdev->req_producer_index);
2631
2632 ndev->trans_start = jiffies;
2633 if (netif_msg_tx_queued(qdev))
2634 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2635 ndev->name, qdev->req_producer_index, skb->len);
2636
bd36b0ac 2637 atomic_dec(&qdev->tx_count);
5a4faa87
RM		 2638 return NETDEV_TX_OK;
2639}
bd36b0ac 2640
5a4faa87
RM		 2641static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2642{
2643 qdev->req_q_size =
2644 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2645
2646 qdev->req_q_virt_addr =
2647 pci_alloc_consistent(qdev->pdev,
2648 (size_t) qdev->req_q_size,
2649 &qdev->req_q_phy_addr);
2650
2651 if ((qdev->req_q_virt_addr == NULL) ||
2652 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2653 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2654 qdev->ndev->name);
2655 return -ENOMEM;
2656 }
2657
2658 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2659
2660 qdev->rsp_q_virt_addr =
2661 pci_alloc_consistent(qdev->pdev,
2662 (size_t) qdev->rsp_q_size,
2663 &qdev->rsp_q_phy_addr);
2664
2665 if ((qdev->rsp_q_virt_addr == NULL) ||
2666 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2667 printk(KERN_ERR PFX
2668 "%s: rspQ allocation failed\n",
2669 qdev->ndev->name);
2670 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2671 qdev->req_q_virt_addr,
2672 qdev->req_q_phy_addr);
2673 return -ENOMEM;
2674 }
2675
2676 set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2677
2678 return 0;
2679}
2680
2681static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2682{
2683 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2684 printk(KERN_INFO PFX
2685 "%s: Already done.\n", qdev->ndev->name);
2686 return;
2687 }
2688
2689 pci_free_consistent(qdev->pdev,
2690 qdev->req_q_size,
2691 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2692
2693 qdev->req_q_virt_addr = NULL;
2694
2695 pci_free_consistent(qdev->pdev,
2696 qdev->rsp_q_size,
2697 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2698
2699 qdev->rsp_q_virt_addr = NULL;
2700
2701 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2702}
2703
2704static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2705{
2706 /* Create Large Buffer Queue */
2707 qdev->lrg_buf_q_size =
1357bfcf 2708 qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
5a4faa87
RM		 2709 if (qdev->lrg_buf_q_size < PAGE_SIZE)
2710 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2711 else
2712 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2713
1357bfcf
RM		 2714 qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2715 if (qdev->lrg_buf == NULL) {
2716 printk(KERN_ERR PFX
2717 "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2718 return -ENOMEM;
2719 }
9ddf7774 2720
5a4faa87
RM		 2721 qdev->lrg_buf_q_alloc_virt_addr =
2722 pci_alloc_consistent(qdev->pdev,
2723 qdev->lrg_buf_q_alloc_size,
2724 &qdev->lrg_buf_q_alloc_phy_addr);
2725
2726 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2727 printk(KERN_ERR PFX
2728 "%s: lBufQ failed\n", qdev->ndev->name);
2729 return -ENOMEM;
2730 }
2731 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2732 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2733
2734 /* Create Small Buffer Queue */
2735 qdev->small_buf_q_size =
2736 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2737 if (qdev->small_buf_q_size < PAGE_SIZE)
2738 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2739 else
2740 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2741
2742 qdev->small_buf_q_alloc_virt_addr =
2743 pci_alloc_consistent(qdev->pdev,
2744 qdev->small_buf_q_alloc_size,
2745 &qdev->small_buf_q_alloc_phy_addr);
2746
2747 if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2748 printk(KERN_ERR PFX
2749 "%s: Small Buffer Queue allocation failed.\n",
2750 qdev->ndev->name);
2751 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2752 qdev->lrg_buf_q_alloc_virt_addr,
2753 qdev->lrg_buf_q_alloc_phy_addr);
2754 return -ENOMEM;
2755 }
2756
2757 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2758 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2759 set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2760 return 0;
2761}
2762
2763static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2764{
2765 if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2766 printk(KERN_INFO PFX
2767 "%s: Already done.\n", qdev->ndev->name);
2768 return;
2769 }
1357bfcf 2770 if(qdev->lrg_buf) kfree(qdev->lrg_buf);
5a4faa87
RM		 2771 pci_free_consistent(qdev->pdev,
2772 qdev->lrg_buf_q_alloc_size,
2773 qdev->lrg_buf_q_alloc_virt_addr,
2774 qdev->lrg_buf_q_alloc_phy_addr);
2775
2776 qdev->lrg_buf_q_virt_addr = NULL;
2777
2778 pci_free_consistent(qdev->pdev,
2779 qdev->small_buf_q_alloc_size,
2780 qdev->small_buf_q_alloc_virt_addr,
2781 qdev->small_buf_q_alloc_phy_addr);
2782
2783 qdev->small_buf_q_virt_addr = NULL;
2784
2785 clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2786}
2787
2788static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2789{
2790 int i;
2791 struct bufq_addr_element *small_buf_q_entry;
2792
2793 /* Currently we allocate on one of memory and use it for smallbuffers */
2794 qdev->small_buf_total_size =
2795 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2796 QL_SMALL_BUFFER_SIZE);
2797
2798 qdev->small_buf_virt_addr =
2799 pci_alloc_consistent(qdev->pdev,
2800 qdev->small_buf_total_size,
2801 &qdev->small_buf_phy_addr);
2802
2803 if (qdev->small_buf_virt_addr == NULL) {
2804 printk(KERN_ERR PFX
2805 "%s: Failed to get small buffer memory.\n",
2806 qdev->ndev->name);
2807 return -ENOMEM;
2808 }
2809
2810 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2811 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2812
2813 small_buf_q_entry = qdev->small_buf_q_virt_addr;
2814
5a4faa87
RM		 2815 /* Initialize the small buffer queue. */
2816 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2817 small_buf_q_entry->addr_high =
2818 cpu_to_le32(qdev->small_buf_phy_addr_high);
2819 small_buf_q_entry->addr_low =
2820 cpu_to_le32(qdev->small_buf_phy_addr_low +
2821 (i * QL_SMALL_BUFFER_SIZE));
2822 small_buf_q_entry++;
2823 }
2824 qdev->small_buf_index = 0;
2825 set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2826 return 0;
2827}
2828
2829static void ql_free_small_buffers(struct ql3_adapter *qdev)
2830{
2831 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2832 printk(KERN_INFO PFX
2833 "%s: Already done.\n", qdev->ndev->name);
2834 return;
2835 }
2836 if (qdev->small_buf_virt_addr != NULL) {
2837 pci_free_consistent(qdev->pdev,
2838 qdev->small_buf_total_size,
2839 qdev->small_buf_virt_addr,
2840 qdev->small_buf_phy_addr);
2841
2842 qdev->small_buf_virt_addr = NULL;
2843 }
2844}
2845
2846static void ql_free_large_buffers(struct ql3_adapter *qdev)
2847{
2848 int i = 0;
2849 struct ql_rcv_buf_cb *lrg_buf_cb;
2850
1357bfcf 2851 for (i = 0; i < qdev->num_large_buffers; i++) {
5a4faa87
RM		 2852 lrg_buf_cb = &qdev->lrg_buf[i];
2853 if (lrg_buf_cb->skb) {
2854 dev_kfree_skb(lrg_buf_cb->skb);
2855 pci_unmap_single(qdev->pdev,
2856 pci_unmap_addr(lrg_buf_cb, mapaddr),
2857 pci_unmap_len(lrg_buf_cb, maplen),
2858 PCI_DMA_FROMDEVICE);
2859 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2860 } else {
2861 break;
2862 }
2863 }
2864}
2865
2866static void ql_init_large_buffers(struct ql3_adapter *qdev)
2867{
2868 int i;
2869 struct ql_rcv_buf_cb *lrg_buf_cb;
2870 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2871
1357bfcf 2872 for (i = 0; i < qdev->num_large_buffers; i++) {
5a4faa87
RM		 2873 lrg_buf_cb = &qdev->lrg_buf[i];
2874 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2875 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2876 buf_addr_ele++;
2877 }
2878 qdev->lrg_buf_index = 0;
2879 qdev->lrg_buf_skb_check = 0;
2880}
2881
2882static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2883{
2884 int i;
2885 struct ql_rcv_buf_cb *lrg_buf_cb;
2886 struct sk_buff *skb;
0f8ab89e
BL		 2887 dma_addr_t map;
2888 int err;
5a4faa87 2889
1357bfcf 2890 for (i = 0; i < qdev->num_large_buffers; i++) {
cd238faa
BL		 2891 skb = netdev_alloc_skb(qdev->ndev,
2892 qdev->lrg_buffer_len);
5a4faa87
RM		 2893 if (unlikely(!skb)) {
2894 /* Better luck next round */
2895 printk(KERN_ERR PFX
2896 "%s: large buff alloc failed, "
2897 "for %d bytes at index %d.\n",
2898 qdev->ndev->name,
2899 qdev->lrg_buffer_len * 2, i);
2900 ql_free_large_buffers(qdev);
2901 return -ENOMEM;
2902 } else {
2903
2904 lrg_buf_cb = &qdev->lrg_buf[i];
2905 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2906 lrg_buf_cb->index = i;
2907 lrg_buf_cb->skb = skb;
2908 /*
2909 * We save some space to copy the ethhdr from first
2910 * buffer
2911 */
2912 skb_reserve(skb, QL_HEADER_SPACE);
2913 map = pci_map_single(qdev->pdev,
2914 skb->data,
2915 qdev->lrg_buffer_len -
2916 QL_HEADER_SPACE,
2917 PCI_DMA_FROMDEVICE);
0f8ab89e 2918
8d8bb39b 2919 err = pci_dma_mapping_error(qdev->pdev, map);
0f8ab89e
BL		 2920 if(err) {
2921 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2922 qdev->ndev->name, err);
2923 ql_free_large_buffers(qdev);
2924 return -ENOMEM;
2925 }
2926
5a4faa87
RM		 2927 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2928 pci_unmap_len_set(lrg_buf_cb, maplen,
2929 qdev->lrg_buffer_len -
2930 QL_HEADER_SPACE);
2931 lrg_buf_cb->buf_phy_addr_low =
2932 cpu_to_le32(LS_64BITS(map));
2933 lrg_buf_cb->buf_phy_addr_high =
2934 cpu_to_le32(MS_64BITS(map));
2935 }
2936 }
2937 return 0;
2938}
2939
bd36b0ac
RM		 2940static void ql_free_send_free_list(struct ql3_adapter *qdev)
2941{
2942 struct ql_tx_buf_cb *tx_cb;
2943 int i;
2944
2945 tx_cb = &qdev->tx_buf[0];
2946 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2947 if (tx_cb->oal) {
2948 kfree(tx_cb->oal);
2949 tx_cb->oal = NULL;
2950 }
2951 tx_cb++;
2952 }
2953}
2954
2955static int ql_create_send_free_list(struct ql3_adapter *qdev)
5a4faa87
RM		 2956{
2957 struct ql_tx_buf_cb *tx_cb;
2958 int i;
2959 struct ob_mac_iocb_req *req_q_curr =
2960 qdev->req_q_virt_addr;
2961
2962 /* Create free list of transmit buffers */
2963 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
bd36b0ac 2964
5a4faa87
RM		 2965 tx_cb = &qdev->tx_buf[i];
2966 tx_cb->skb = NULL;
2967 tx_cb->queue_entry = req_q_curr;
2968 req_q_curr++;
bd36b0ac
RM		 2969 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2970 if (tx_cb->oal == NULL)
2971 return -1;
5a4faa87 2972 }
bd36b0ac 2973 return 0;
5a4faa87
RM		 2974}
2975
2976static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2977{
1357bfcf
RM		 2978 if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2979 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
5a4faa87 2980 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
1357bfcf 2981 }
5a4faa87 2982 else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
1357bfcf
RM		 2983 /*
2984 * Bigger buffers, so less of them.
2985 */
2986 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
5a4faa87
RM		 2987 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2988 } else {
2989 printk(KERN_ERR PFX
2990 "%s: Invalid mtu size. Only 1500 and 9000 are accepted.\n",
2991 qdev->ndev->name);
2992 return -ENOMEM;
2993 }
1357bfcf 2994 qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
5a4faa87
RM		 2995 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2996 qdev->max_frame_size =
2997 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2998
2999 /*
3000 * First allocate a page of shared memory and use it for shadow
3001 * locations of Network Request Queue Consumer Address Register and
3002 * Network Completion Queue Producer Index Register
3003 */
3004 qdev->shadow_reg_virt_addr =
3005 pci_alloc_consistent(qdev->pdev,
3006 PAGE_SIZE, &qdev->shadow_reg_phy_addr);
3007
3008 if (qdev->shadow_reg_virt_addr != NULL) {
3009 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
3010 qdev->req_consumer_index_phy_addr_high =
3011 MS_64BITS(qdev->shadow_reg_phy_addr);
3012 qdev->req_consumer_index_phy_addr_low =
3013 LS_64BITS(qdev->shadow_reg_phy_addr);
3014
3015 qdev->prsp_producer_index =
804d8541 3016 (__le32 *) (((u8 *) qdev->preq_consumer_index) + 8);
5a4faa87
RM		 3017 qdev->rsp_producer_index_phy_addr_high =
3018 qdev->req_consumer_index_phy_addr_high;
3019 qdev->rsp_producer_index_phy_addr_low =
3020 qdev->req_consumer_index_phy_addr_low + 8;
3021 } else {
3022 printk(KERN_ERR PFX
3023 "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
3024 return -ENOMEM;
3025 }
3026
3027 if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
3028 printk(KERN_ERR PFX
3029 "%s: ql_alloc_net_req_rsp_queues failed.\n",
3030 qdev->ndev->name);
3031 goto err_req_rsp;
3032 }
3033
3034 if (ql_alloc_buffer_queues(qdev) != 0) {
3035 printk(KERN_ERR PFX
3036 "%s: ql_alloc_buffer_queues failed.\n",
3037 qdev->ndev->name);
3038 goto err_buffer_queues;
3039 }
3040
3041 if (ql_alloc_small_buffers(qdev) != 0) {
3042 printk(KERN_ERR PFX
3043 "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
3044 goto err_small_buffers;
3045 }
3046
3047 if (ql_alloc_large_buffers(qdev) != 0) {
3048 printk(KERN_ERR PFX
3049 "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
3050 goto err_small_buffers;
3051 }
3052
3053 /* Initialize the large buffer queue. */
3054 ql_init_large_buffers(qdev);
bd36b0ac
RM		 3055 if (ql_create_send_free_list(qdev))
3056 goto err_free_list;
5a4faa87
RM		 3057
3058 qdev->rsp_current = qdev->rsp_q_virt_addr;
3059
3060 return 0;
bd36b0ac
RM		 3061err_free_list:
3062 ql_free_send_free_list(qdev);
5a4faa87
RM		 3063err_small_buffers:
3064 ql_free_buffer_queues(qdev);
3065err_buffer_queues:
3066 ql_free_net_req_rsp_queues(qdev);
3067err_req_rsp:
3068 pci_free_consistent(qdev->pdev,
3069 PAGE_SIZE,
3070 qdev->shadow_reg_virt_addr,
3071 qdev->shadow_reg_phy_addr);
3072
3073 return -ENOMEM;
3074}
3075
3076static void ql_free_mem_resources(struct ql3_adapter *qdev)
3077{
bd36b0ac 3078 ql_free_send_free_list(qdev);
5a4faa87
RM		 3079 ql_free_large_buffers(qdev);
3080 ql_free_small_buffers(qdev);
3081 ql_free_buffer_queues(qdev);
3082 ql_free_net_req_rsp_queues(qdev);
3083 if (qdev->shadow_reg_virt_addr != NULL) {
3084 pci_free_consistent(qdev->pdev,
3085 PAGE_SIZE,
3086 qdev->shadow_reg_virt_addr,
3087 qdev->shadow_reg_phy_addr);
3088 qdev->shadow_reg_virt_addr = NULL;
3089 }
3090}
3091
3092static int ql_init_misc_registers(struct ql3_adapter *qdev)
3093{
ee111d11
AV		 3094 struct ql3xxx_local_ram_registers __iomem *local_ram =
3095 (void __iomem *)qdev->mem_map_registers;
5a4faa87
RM		 3096
3097 if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
3098 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3099 2) << 4))
3100 return -1;
3101
3102 ql_write_page2_reg(qdev,
3103 &local_ram->bufletSize, qdev->nvram_data.bufletSize);
3104
3105 ql_write_page2_reg(qdev,
3106 &local_ram->maxBufletCount,
3107 qdev->nvram_data.bufletCount);
3108
3109 ql_write_page2_reg(qdev,
3110 &local_ram->freeBufletThresholdLow,
3111 (qdev->nvram_data.tcpWindowThreshold25 << 16) |
3112 (qdev->nvram_data.tcpWindowThreshold0));
3113
3114 ql_write_page2_reg(qdev,
3115 &local_ram->freeBufletThresholdHigh,
3116 qdev->nvram_data.tcpWindowThreshold50);
3117
3118 ql_write_page2_reg(qdev,
3119 &local_ram->ipHashTableBase,
3120 (qdev->nvram_data.ipHashTableBaseHi << 16) |
3121 qdev->nvram_data.ipHashTableBaseLo);
3122 ql_write_page2_reg(qdev,
3123 &local_ram->ipHashTableCount,
3124 qdev->nvram_data.ipHashTableSize);
3125 ql_write_page2_reg(qdev,
3126 &local_ram->tcpHashTableBase,
3127 (qdev->nvram_data.tcpHashTableBaseHi << 16) |
3128 qdev->nvram_data.tcpHashTableBaseLo);
3129 ql_write_page2_reg(qdev,
3130 &local_ram->tcpHashTableCount,
3131 qdev->nvram_data.tcpHashTableSize);
3132 ql_write_page2_reg(qdev,
3133 &local_ram->ncbBase,
3134 (qdev->nvram_data.ncbTableBaseHi << 16) |
3135 qdev->nvram_data.ncbTableBaseLo);
3136 ql_write_page2_reg(qdev,
3137 &local_ram->maxNcbCount,
3138 qdev->nvram_data.ncbTableSize);
3139 ql_write_page2_reg(qdev,
3140 &local_ram->drbBase,
3141 (qdev->nvram_data.drbTableBaseHi << 16) |
3142 qdev->nvram_data.drbTableBaseLo);
3143 ql_write_page2_reg(qdev,
3144 &local_ram->maxDrbCount,
3145 qdev->nvram_data.drbTableSize);
3146 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
3147 return 0;
3148}
3149
3150static int ql_adapter_initialize(struct ql3_adapter *qdev)
3151{
3152 u32 value;
3153 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3154 struct ql3xxx_host_memory_registers __iomem *hmem_regs =
ee111d11 3155 (void __iomem *)port_regs;
5a4faa87
RM		 3156 u32 delay = 10;
3157 int status = 0;
3158
3159 if(ql_mii_setup(qdev))
3160 return -1;
3161
3162 /* Bring out PHY out of reset */
3163 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3164 (ISP_SERIAL_PORT_IF_WE |
3165 (ISP_SERIAL_PORT_IF_WE << 16)));
3166
3167 qdev->port_link_state = LS_DOWN;
3168 netif_carrier_off(qdev->ndev);
3169
3170 /* V2 chip fix for ARS-39168. */
3171 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
3172 (ISP_SERIAL_PORT_IF_SDE |
3173 (ISP_SERIAL_PORT_IF_SDE << 16)));
3174
3175 /* Request Queue Registers */
3176 *((u32 *) (qdev->preq_consumer_index)) = 0;
3177 atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
3178 qdev->req_producer_index = 0;
3179
3180 ql_write_page1_reg(qdev,
3181 &hmem_regs->reqConsumerIndexAddrHigh,
3182 qdev->req_consumer_index_phy_addr_high);
3183 ql_write_page1_reg(qdev,
3184 &hmem_regs->reqConsumerIndexAddrLow,
3185 qdev->req_consumer_index_phy_addr_low);
3186
3187 ql_write_page1_reg(qdev,
3188 &hmem_regs->reqBaseAddrHigh,
3189 MS_64BITS(qdev->req_q_phy_addr));
3190 ql_write_page1_reg(qdev,
3191 &hmem_regs->reqBaseAddrLow,
3192 LS_64BITS(qdev->req_q_phy_addr));
3193 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3194
3195 /* Response Queue Registers */
804d8541 3196 *((__le16 *) (qdev->prsp_producer_index)) = 0;
5a4faa87
RM		 3197 qdev->rsp_consumer_index = 0;
3198 qdev->rsp_current = qdev->rsp_q_virt_addr;
3199
3200 ql_write_page1_reg(qdev,
3201 &hmem_regs->rspProducerIndexAddrHigh,
3202 qdev->rsp_producer_index_phy_addr_high);
3203
3204 ql_write_page1_reg(qdev,
3205 &hmem_regs->rspProducerIndexAddrLow,
3206 qdev->rsp_producer_index_phy_addr_low);
3207
3208 ql_write_page1_reg(qdev,
3209 &hmem_regs->rspBaseAddrHigh,
3210 MS_64BITS(qdev->rsp_q_phy_addr));
3211
3212 ql_write_page1_reg(qdev,
3213 &hmem_regs->rspBaseAddrLow,
3214 LS_64BITS(qdev->rsp_q_phy_addr));
3215
3216 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3217
3218 /* Large Buffer Queue */
3219 ql_write_page1_reg(qdev,
3220 &hmem_regs->rxLargeQBaseAddrHigh,
3221 MS_64BITS(qdev->lrg_buf_q_phy_addr));
3222
3223 ql_write_page1_reg(qdev,
3224 &hmem_regs->rxLargeQBaseAddrLow,
3225 LS_64BITS(qdev->lrg_buf_q_phy_addr));
3226
1357bfcf 3227 ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
5a4faa87
RM		 3228
3229 ql_write_page1_reg(qdev,
3230 &hmem_regs->rxLargeBufferLength,
3231 qdev->lrg_buffer_len);
3232
3233 /* Small Buffer Queue */
3234 ql_write_page1_reg(qdev,
3235 &hmem_regs->rxSmallQBaseAddrHigh,
3236 MS_64BITS(qdev->small_buf_q_phy_addr));
3237
3238 ql_write_page1_reg(qdev,
3239 &hmem_regs->rxSmallQBaseAddrLow,
3240 LS_64BITS(qdev->small_buf_q_phy_addr));
3241
3242 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3243 ql_write_page1_reg(qdev,
3244 &hmem_regs->rxSmallBufferLength,
3245 QL_SMALL_BUFFER_SIZE);
3246
3247 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3248 qdev->small_buf_release_cnt = 8;
1357bfcf 3249 qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
5a4faa87
RM		 3250 qdev->lrg_buf_release_cnt = 8;
3251 qdev->lrg_buf_next_free =
3252 (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
3253 qdev->small_buf_index = 0;
3254 qdev->lrg_buf_index = 0;
3255 qdev->lrg_buf_free_count = 0;
3256 qdev->lrg_buf_free_head = NULL;
3257 qdev->lrg_buf_free_tail = NULL;
3258
3259 ql_write_common_reg(qdev,
ee111d11 3260 &port_regs->CommonRegs.
5a4faa87
RM		 3261 rxSmallQProducerIndex,
3262 qdev->small_buf_q_producer_index);
3263 ql_write_common_reg(qdev,
ee111d11 3264 &port_regs->CommonRegs.
5a4faa87
RM		 3265 rxLargeQProducerIndex,
3266 qdev->lrg_buf_q_producer_index);
3267
3268 /*
3269 * Find out if the chip has already been initialized. If it has, then
3270 * we skip some of the initialization.
3271 */
3272 clear_bit(QL_LINK_MASTER, &qdev->flags);
3273 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3274 if ((value & PORT_STATUS_IC) == 0) {
3275
3276 /* Chip has not been configured yet, so let it rip. */
3277 if(ql_init_misc_registers(qdev)) {
3278 status = -1;
3279 goto out;
3280 }
3281
5a4faa87
RM		 3282 value = qdev->nvram_data.tcpMaxWindowSize;
3283 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3284
3285 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3286
3287 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3288 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3289 * 2) << 13)) {
3290 status = -1;
3291 goto out;
3292 }
3293 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3294 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3295 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3296 16) | (INTERNAL_CHIP_SD |
3297 INTERNAL_CHIP_WE)));
3298 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3299 }
3300
b3b1514c
RM		 3301 if (qdev->mac_index)
3302 ql_write_page0_reg(qdev,
3303 &port_regs->mac1MaxFrameLengthReg,
3304 qdev->max_frame_size);
3305 else
3306 ql_write_page0_reg(qdev,
3307 &port_regs->mac0MaxFrameLengthReg,
3308 qdev->max_frame_size);
5a4faa87
RM		 3309
3310 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3311 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3312 2) << 7)) {
3313 status = -1;
3314 goto out;
3315 }
3316
3efedf2e 3317 PHY_Setup(qdev);
5a4faa87
RM		 3318 ql_init_scan_mode(qdev);
3319 ql_get_phy_owner(qdev);
3320
3321 /* Load the MAC Configuration */
3322
3323 /* Program lower 32 bits of the MAC address */
3324 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3325 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3326 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3327 ((qdev->ndev->dev_addr[2] << 24)
3328 | (qdev->ndev->dev_addr[3] << 16)
3329 | (qdev->ndev->dev_addr[4] << 8)
3330 | qdev->ndev->dev_addr[5]));
3331
3332 /* Program top 16 bits of the MAC address */
3333 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3334 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3335 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3336 ((qdev->ndev->dev_addr[0] << 8)
3337 | qdev->ndev->dev_addr[1]));
3338
3339 /* Enable Primary MAC */
3340 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3341 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3342 MAC_ADDR_INDIRECT_PTR_REG_PE));
3343
3344 /* Clear Primary and Secondary IP addresses */
3345 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3346 ((IP_ADDR_INDEX_REG_MASK << 16) |
3347 (qdev->mac_index << 2)));
3348 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3349
3350 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3351 ((IP_ADDR_INDEX_REG_MASK << 16) |
3352 ((qdev->mac_index << 2) + 1)));
3353 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3354
3355 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3356
3357 /* Indicate Configuration Complete */
3358 ql_write_page0_reg(qdev,
3359 &port_regs->portControl,
3360 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3361
3362 do {
3363 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3364 if (value & PORT_STATUS_IC)
3365 break;
3366 msleep(500);
3367 } while (--delay);
3368
3369 if (delay == 0) {
3370 printk(KERN_ERR PFX
3371 "%s: Hw Initialization timeout.\n", qdev->ndev->name);
3372 status = -1;
3373 goto out;
3374 }
3375
3376 /* Enable Ethernet Function */
bd36b0ac
RM		 3377 if (qdev->device_id == QL3032_DEVICE_ID) {
3378 value =
3379 (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
b3b1514c
RM		 3380 QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3381 QL3032_PORT_CONTROL_ET);
bd36b0ac
RM		 3382 ql_write_page0_reg(qdev, &port_regs->functionControl,
3383 ((value << 16) | value));
3384 } else {
3385 value =
3386 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3387 PORT_CONTROL_HH);
3388 ql_write_page0_reg(qdev, &port_regs->portControl,
3389 ((value << 16) | value));
3390 }
3391
5a4faa87
RM		 3392
3393out:
3394 return status;
3395}
3396
3397/*
3398 * Caller holds hw_lock.
3399 */
3400static int ql_adapter_reset(struct ql3_adapter *qdev)
3401{
3402 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3403 int status = 0;
3404 u16 value;
3405 int max_wait_time;
3406
3407 set_bit(QL_RESET_ACTIVE, &qdev->flags);
3408 clear_bit(QL_RESET_DONE, &qdev->flags);
3409
3410 /*
3411 * Issue soft reset to chip.
3412 */
3413 printk(KERN_DEBUG PFX
3414 "%s: Issue soft reset to chip.\n",
3415 qdev->ndev->name);
3416 ql_write_common_reg(qdev,
ee111d11 3417 &port_regs->CommonRegs.ispControlStatus,
5a4faa87
RM		 3418 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3419
3420 /* Wait 3 seconds for reset to complete. */
3421 printk(KERN_DEBUG PFX
3422 "%s: Wait 10 milliseconds for reset to complete.\n",
3423 qdev->ndev->name);
3424
3425 /* Wait until the firmware tells us the Soft Reset is done */
3426 max_wait_time = 5;
3427 do {
3428 value =
3429 ql_read_common_reg(qdev,
3430 &port_regs->CommonRegs.ispControlStatus);
3431 if ((value & ISP_CONTROL_SR) == 0)
3432 break;
3433
3434 ssleep(1);
3435 } while ((--max_wait_time));
3436
3437 /*
3438 * Also, make sure that the Network Reset Interrupt bit has been
3439 * cleared after the soft reset has taken place.
3440 */
3441 value =
3442 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3443 if (value & ISP_CONTROL_RI) {
3444 printk(KERN_DEBUG PFX
3445 "ql_adapter_reset: clearing RI after reset.\n");
3446 ql_write_common_reg(qdev,
ee111d11 3447 &port_regs->CommonRegs.
5a4faa87
RM		 3448 ispControlStatus,
3449 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3450 }
3451
3452 if (max_wait_time == 0) {
3453 /* Issue Force Soft Reset */
3454 ql_write_common_reg(qdev,
ee111d11 3455 &port_regs->CommonRegs.
5a4faa87
RM		 3456 ispControlStatus,
3457 ((ISP_CONTROL_FSR << 16) |
3458 ISP_CONTROL_FSR));
3459 /*
3460 * Wait until the firmware tells us the Force Soft Reset is
3461 * done
3462 */
3463 max_wait_time = 5;
3464 do {
3465 value =
3466 ql_read_common_reg(qdev,
3467 &port_regs->CommonRegs.
3468 ispControlStatus);
3469 if ((value & ISP_CONTROL_FSR) == 0) {
3470 break;
3471 }
3472 ssleep(1);
3473 } while ((--max_wait_time));
3474 }
3475 if (max_wait_time == 0)
3476 status = 1;
3477
3478 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3479 set_bit(QL_RESET_DONE, &qdev->flags);
3480 return status;
3481}
3482
3483static void ql_set_mac_info(struct ql3_adapter *qdev)
3484{
3485 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3486 u32 value, port_status;
3487 u8 func_number;
3488
3489 /* Get the function number */
3490 value =
3491 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3492 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3493 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3494 switch (value & ISP_CONTROL_FN_MASK) {
3495 case ISP_CONTROL_FN0_NET:
3496 qdev->mac_index = 0;
3497 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
5a4faa87
RM		 3498 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3499 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3500 if (port_status & PORT_STATUS_SM0)
3501 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3502 else
3503 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3504 break;
3505
3506 case ISP_CONTROL_FN1_NET:
3507 qdev->mac_index = 1;
3508 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
5a4faa87
RM		 3509 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3510 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3511 if (port_status & PORT_STATUS_SM1)
3512 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3513 else
3514 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3515 break;
3516
3517 case ISP_CONTROL_FN0_SCSI:
3518 case ISP_CONTROL_FN1_SCSI:
3519 default:
3520 printk(KERN_DEBUG PFX
3521 "%s: Invalid function number, ispControlStatus = 0x%x\n",
3522 qdev->ndev->name,value);
3523 break;
3524 }
804d8541 3525 qdev->numPorts = qdev->nvram_data.version_and_numPorts >> 8;
5a4faa87
RM		 3526}
3527
3528static void ql_display_dev_info(struct net_device *ndev)
3529{
3530 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3531 struct pci_dev *pdev = qdev->pdev;
3532
3533 printk(KERN_INFO PFX
bd36b0ac
RM		 3534 "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3535 DRV_NAME, qdev->index, qdev->chip_rev_id,
3536 (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3537 qdev->pci_slot);
5a4faa87
RM		 3538 printk(KERN_INFO PFX
3539 "%s Interface.\n",
3540 test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3541
3542 /*
3543 * Print PCI bus width/type.
3544 */
3545 printk(KERN_INFO PFX
3546 "Bus interface is %s %s.\n",
3547 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3548 ((qdev->pci_x) ? "PCI-X" : "PCI"));
3549
3550 printk(KERN_INFO PFX
3551 "mem IO base address adjusted = 0x%p\n",
3552 qdev->mem_map_registers);
3553 printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3554
3555 if (netif_msg_probe(qdev))
3556 printk(KERN_INFO PFX
e174961c
JB		 3557 "%s: MAC address %pM\n",
3558 ndev->name, ndev->dev_addr);
5a4faa87
RM		 3559}
3560
3561static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3562{
3563 struct net_device *ndev = qdev->ndev;
3564 int retval = 0;
3565
3566 netif_stop_queue(ndev);
3567 netif_carrier_off(ndev);
3568
3569 clear_bit(QL_ADAPTER_UP,&qdev->flags);
3570 clear_bit(QL_LINK_MASTER,&qdev->flags);
3571
3572 ql_disable_interrupts(qdev);
3573
3574 free_irq(qdev->pdev->irq, ndev);
3575
3576 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3577 printk(KERN_INFO PFX
3578 "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3579 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3580 pci_disable_msi(qdev->pdev);
3581 }
3582
3583 del_timer_sync(&qdev->adapter_timer);
3584
bea3348e 3585 napi_disable(&qdev->napi);
5a4faa87
RM		 3586
3587 if (do_reset) {
3588 int soft_reset;
3589 unsigned long hw_flags;
3590
3591 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3592 if (ql_wait_for_drvr_lock(qdev)) {
3593 if ((soft_reset = ql_adapter_reset(qdev))) {
3594 printk(KERN_ERR PFX
3595 "%s: ql_adapter_reset(%d) FAILED!\n",
3596 ndev->name, qdev->index);
3597 }
3598 printk(KERN_ERR PFX
3599 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3600 } else {
3601 printk(KERN_ERR PFX
3602 "%s: Could not acquire driver lock to do "
3603 "reset!\n", ndev->name);
3604 retval = -1;
3605 }
3606 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3607 }
3608 ql_free_mem_resources(qdev);
3609 return retval;
3610}
3611
3612static int ql_adapter_up(struct ql3_adapter *qdev)
3613{
3614 struct net_device *ndev = qdev->ndev;
3615 int err;
38515e90 3616 unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
5a4faa87
RM		 3617 unsigned long hw_flags;
3618
3619 if (ql_alloc_mem_resources(qdev)) {
3620 printk(KERN_ERR PFX
3621 "%s Unable to allocate buffers.\n", ndev->name);
3622 return -ENOMEM;
3623 }
3624
3625 if (qdev->msi) {
3626 if (pci_enable_msi(qdev->pdev)) {
3627 printk(KERN_ERR PFX
3628 "%s: User requested MSI, but MSI failed to "
3629 "initialize. Continuing without MSI.\n",
3630 qdev->ndev->name);
3631 qdev->msi = 0;
3632 } else {
3633 printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3634 set_bit(QL_MSI_ENABLED,&qdev->flags);
38515e90 3635 irq_flags &= ~IRQF_SHARED;
5a4faa87
RM		 3636 }
3637 }
3638
3639 if ((err = request_irq(qdev->pdev->irq,
3640 ql3xxx_isr,
3641 irq_flags, ndev->name, ndev))) {
3642 printk(KERN_ERR PFX
3643 "%s: Failed to reserve interrupt %d already in use.\n",
3644 ndev->name, qdev->pdev->irq);
3645 goto err_irq;
3646 }
3647
3648 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3649
3650 if ((err = ql_wait_for_drvr_lock(qdev))) {
3651 if ((err = ql_adapter_initialize(qdev))) {
3652 printk(KERN_ERR PFX
3653 "%s: Unable to initialize adapter.\n",
3654 ndev->name);
3655 goto err_init;
3656 }
3657 printk(KERN_ERR PFX
3658 "%s: Releaseing driver lock.\n",ndev->name);
3659 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3660 } else {
3661 printk(KERN_ERR PFX
3662 "%s: Could not aquire driver lock.\n",
3663 ndev->name);
3664 goto err_lock;
3665 }
3666
3667 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3668
3669 set_bit(QL_ADAPTER_UP,&qdev->flags);
3670
3671 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3672
bea3348e 3673 napi_enable(&qdev->napi);
5a4faa87
RM		 3674 ql_enable_interrupts(qdev);
3675 return 0;
3676
3677err_init:
3678 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3679err_lock:
04f10773 3680 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87
RM		 3681 free_irq(qdev->pdev->irq, ndev);
3682err_irq:
3683 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3684 printk(KERN_INFO PFX
3685 "%s: calling pci_disable_msi().\n",
3686 qdev->ndev->name);
3687 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3688 pci_disable_msi(qdev->pdev);
3689 }
3690 return err;
3691}
3692
3693static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3694{
3695 if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3696 printk(KERN_ERR PFX
3697 "%s: Driver up/down cycle failed, "
3698 "closing device\n",qdev->ndev->name);
c81ec80b 3699 rtnl_lock();
5a4faa87 3700 dev_close(qdev->ndev);
c81ec80b 3701 rtnl_unlock();
5a4faa87
RM		 3702 return -1;
3703 }
3704 return 0;
3705}
3706
3707static int ql3xxx_close(struct net_device *ndev)
3708{
3709 struct ql3_adapter *qdev = netdev_priv(ndev);
3710
3711 /*
3712 * Wait for device to recover from a reset.
3713 * (Rarely happens, but possible.)
3714 */
3715 while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3716 msleep(50);
3717
3718 ql_adapter_down(qdev,QL_DO_RESET);
3719 return 0;
3720}
3721
3722static int ql3xxx_open(struct net_device *ndev)
3723{
3724 struct ql3_adapter *qdev = netdev_priv(ndev);
3725 return (ql_adapter_up(qdev));
3726}
3727
5a4faa87
RM		 3728static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3729{
3730 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3731 struct ql3xxx_port_registers __iomem *port_regs =
3732 qdev->mem_map_registers;
3733 struct sockaddr *addr = p;
3734 unsigned long hw_flags;
3735
3736 if (netif_running(ndev))
3737 return -EBUSY;
3738
3739 if (!is_valid_ether_addr(addr->sa_data))
3740 return -EADDRNOTAVAIL;
3741
3742 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3743
3744 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3745 /* Program lower 32 bits of the MAC address */
3746 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3747 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3748 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3749 ((ndev->dev_addr[2] << 24) | (ndev->
3750 dev_addr[3] << 16) |
3751 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3752
3753 /* Program top 16 bits of the MAC address */
3754 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3755 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3756 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3757 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3758 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3759
3760 return 0;
3761}
3762
3763static void ql3xxx_tx_timeout(struct net_device *ndev)
3764{
3765 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3766
3767 printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3768 /*
3769 * Stop the queues, we've got a problem.
3770 */
3771 netif_stop_queue(ndev);
3772
3773 /*
3774 * Wake up the worker to process this event.
3775 */
c4028958 3776 queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
5a4faa87
RM		 3777}
3778
c4028958 3779static void ql_reset_work(struct work_struct *work)
5a4faa87 3780{
c4028958
DH		 3781 struct ql3_adapter *qdev =
3782 container_of(work, struct ql3_adapter, reset_work.work);
5a4faa87
RM		 3783 struct net_device *ndev = qdev->ndev;
3784 u32 value;
3785 struct ql_tx_buf_cb *tx_cb;
3786 int max_wait_time, i;
3787 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3788 unsigned long hw_flags;
3789
3790 if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3791 clear_bit(QL_LINK_MASTER,&qdev->flags);
3792
3793 /*
3794 * Loop through the active list and return the skb.
3795 */
3796 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
bd36b0ac 3797 int j;
5a4faa87
RM		 3798 tx_cb = &qdev->tx_buf[i];
3799 if (tx_cb->skb) {
5a4faa87
RM		 3800 printk(KERN_DEBUG PFX
3801 "%s: Freeing lost SKB.\n",
3802 qdev->ndev->name);
3803 pci_unmap_single(qdev->pdev,
bd36b0ac
RM		 3804 pci_unmap_addr(&tx_cb->map[0], mapaddr),
3805 pci_unmap_len(&tx_cb->map[0], maplen),
3806 PCI_DMA_TODEVICE);
3807 for(j=1;j<tx_cb->seg_count;j++) {
3808 pci_unmap_page(qdev->pdev,
3809 pci_unmap_addr(&tx_cb->map[j],mapaddr),
3810 pci_unmap_len(&tx_cb->map[j],maplen),
3811 PCI_DMA_TODEVICE);
3812 }
5a4faa87
RM		 3813 dev_kfree_skb(tx_cb->skb);
3814 tx_cb->skb = NULL;
3815 }
3816 }
3817
3818 printk(KERN_ERR PFX
3819 "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3820 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3821 ql_write_common_reg(qdev,
3822 &port_regs->CommonRegs.
3823 ispControlStatus,
3824 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3825 /*
3826 * Wait the for Soft Reset to Complete.
3827 */
3828 max_wait_time = 10;
3829 do {
3830 value = ql_read_common_reg(qdev,
3831 &port_regs->CommonRegs.
3832
3833 ispControlStatus);
3834 if ((value & ISP_CONTROL_SR) == 0) {
3835 printk(KERN_DEBUG PFX
3836 "%s: reset completed.\n",
3837 qdev->ndev->name);
3838 break;
3839 }
3840
3841 if (value & ISP_CONTROL_RI) {
3842 printk(KERN_DEBUG PFX
3843 "%s: clearing NRI after reset.\n",
3844 qdev->ndev->name);
3845 ql_write_common_reg(qdev,
ee111d11 3846 &port_regs->
5a4faa87
RM		 3847 CommonRegs.
3848 ispControlStatus,
3849 ((ISP_CONTROL_RI <<
3850 16) | ISP_CONTROL_RI));
3851 }
3852
3853 ssleep(1);
3854 } while (--max_wait_time);
3855 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3856
3857 if (value & ISP_CONTROL_SR) {
3858
3859 /*
3860 * Set the reset flags and clear the board again.
3861 * Nothing else to do...
3862 */
3863 printk(KERN_ERR PFX
3864 "%s: Timed out waiting for reset to "
3865 "complete.\n", ndev->name);
3866 printk(KERN_ERR PFX
3867 "%s: Do a reset.\n", ndev->name);
3868 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3869 clear_bit(QL_RESET_START,&qdev->flags);
3870 ql_cycle_adapter(qdev,QL_DO_RESET);
3871 return;
3872 }
3873
3874 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3875 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3876 clear_bit(QL_RESET_START,&qdev->flags);
3877 ql_cycle_adapter(qdev,QL_NO_RESET);
3878 }
3879}
3880
c4028958 3881static void ql_tx_timeout_work(struct work_struct *work)
5a4faa87 3882{
c4028958
DH		 3883 struct ql3_adapter *qdev =
3884 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3885
3886 ql_cycle_adapter(qdev, QL_DO_RESET);
5a4faa87
RM		 3887}
3888
3889static void ql_get_board_info(struct ql3_adapter *qdev)
3890{
3891 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3892 u32 value;
3893
3894 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3895
3896 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3897 if (value & PORT_STATUS_64)
3898 qdev->pci_width = 64;
3899 else
3900 qdev->pci_width = 32;
3901 if (value & PORT_STATUS_X)
3902 qdev->pci_x = 1;
3903 else
3904 qdev->pci_x = 0;
3905 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3906}
3907
3908static void ql3xxx_timer(unsigned long ptr)
3909{
3910 struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3e23b7d3 3911 queue_delayed_work(qdev->workqueue, &qdev->link_state_work, 0);
5a4faa87
RM		 3912}
3913
3914static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3915 const struct pci_device_id *pci_entry)
3916{
3917 struct net_device *ndev = NULL;
3918 struct ql3_adapter *qdev = NULL;
3919 static int cards_found = 0;
3920 int pci_using_dac, err;
3921
3922 err = pci_enable_device(pdev);
3923 if (err) {
3924 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3925 pci_name(pdev));
3926 goto err_out;
3927 }
3928
3929 err = pci_request_regions(pdev, DRV_NAME);
3930 if (err) {
3931 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3932 pci_name(pdev));
3933 goto err_out_disable_pdev;
3934 }
3935
3936 pci_set_master(pdev);
3937
3938 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3939 pci_using_dac = 1;
3940 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3941 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3942 pci_using_dac = 0;
3943 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3944 }
3945
3946 if (err) {
3947 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3948 pci_name(pdev));
3949 goto err_out_free_regions;
3950 }
3951
3952 ndev = alloc_etherdev(sizeof(struct ql3_adapter));
546faf07
BL		 3953 if (!ndev) {
3954 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
3955 pci_name(pdev));
3956 err = -ENOMEM;
5a4faa87 3957 goto err_out_free_regions;
546faf07 3958 }
5a4faa87 3959
5a4faa87
RM		 3960 SET_NETDEV_DEV(ndev, &pdev->dev);
3961
5a4faa87
RM		 3962 pci_set_drvdata(pdev, ndev);
3963
3964 qdev = netdev_priv(ndev);
3965 qdev->index = cards_found;
3966 qdev->ndev = ndev;
3967 qdev->pdev = pdev;
bd36b0ac 3968 qdev->device_id = pci_entry->device;
5a4faa87
RM		 3969 qdev->port_link_state = LS_DOWN;
3970 if (msi)
3971 qdev->msi = 1;
3972
3973 qdev->msg_enable = netif_msg_init(debug, default_msg);
3974
bd36b0ac
RM		 3975 if (pci_using_dac)
3976 ndev->features |= NETIF_F_HIGHDMA;
3977 if (qdev->device_id == QL3032_DEVICE_ID)
e68a8c10 3978 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
bd36b0ac 3979
275f165f 3980 qdev->mem_map_registers = pci_ioremap_bar(pdev, 1);
5a4faa87
RM		 3981 if (!qdev->mem_map_registers) {
3982 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3983 pci_name(pdev));
546faf07 3984 err = -EIO;
5a4faa87
RM		 3985 goto err_out_free_ndev;
3986 }
3987
3988 spin_lock_init(&qdev->adapter_lock);
3989 spin_lock_init(&qdev->hw_lock);
3990
3991 /* Set driver entry points */
3992 ndev->open = ql3xxx_open;
3993 ndev->hard_start_xmit = ql3xxx_send;
3994 ndev->stop = ql3xxx_close;
49ef26eb
RM		 3995 /* ndev->set_multicast_list
3996 * This device is one side of a two-function adapter
3997 * (NIC and iSCSI). Promiscuous mode setting/clearing is
3998 * not allowed from the NIC side.
3999 */
5a4faa87
RM		 4000 SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
4001 ndev->set_mac_address = ql3xxx_set_mac_address;
4002 ndev->tx_timeout = ql3xxx_tx_timeout;
4003 ndev->watchdog_timeo = 5 * HZ;
4004
bea3348e 4005 netif_napi_add(ndev, &qdev->napi, ql_poll, 64);
5a4faa87
RM		 4006
4007 ndev->irq = pdev->irq;
4008
4009 /* make sure the EEPROM is good */
4010 if (ql_get_nvram_params(qdev)) {
4011 printk(KERN_ALERT PFX
4012 "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
4013 qdev->index);
546faf07 4014 err = -EIO;
5a4faa87
RM		 4015 goto err_out_iounmap;
4016 }
4017
4018 ql_set_mac_info(qdev);
4019
4020 /* Validate and set parameters */
4021 if (qdev->mac_index) {
cb8bac12 4022 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
804d8541 4023 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn2.macAddress);
5a4faa87 4024 } else {
cb8bac12 4025 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
804d8541 4026 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn0.macAddress);
5a4faa87
RM		 4027 }
4028 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
4029
4030 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
4031
5a4faa87
RM		 4032 /* Record PCI bus information. */
4033 ql_get_board_info(qdev);
4034
4035 /*
4036 * Set the Maximum Memory Read Byte Count value. We do this to handle
4037 * jumbo frames.
4038 */
4039 if (qdev->pci_x) {
4040 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
4041 }
4042
4043 err = register_netdev(ndev);
4044 if (err) {
4045 printk(KERN_ERR PFX "%s: cannot register net device\n",
4046 pci_name(pdev));
4047 goto err_out_iounmap;
4048 }
4049
4050 /* we're going to reset, so assume we have no link for now */
4051
4052 netif_carrier_off(ndev);
4053 netif_stop_queue(ndev);
4054
4055 qdev->workqueue = create_singlethread_workqueue(ndev->name);
c4028958
DH		 4056 INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
4057 INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3e23b7d3 4058 INIT_DELAYED_WORK(&qdev->link_state_work, ql_link_state_machine_work);
5a4faa87
RM		 4059
4060 init_timer(&qdev->adapter_timer);
4061 qdev->adapter_timer.function = ql3xxx_timer;
4062 qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
4063 qdev->adapter_timer.data = (unsigned long)qdev;
4064
4065 if(!cards_found) {
4066 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
4067 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
4068 DRV_NAME, DRV_VERSION);
4069 }
4070 ql_display_dev_info(ndev);
4071
4072 cards_found++;
4073 return 0;
4074
4075err_out_iounmap:
4076 iounmap(qdev->mem_map_registers);
4077err_out_free_ndev:
4078 free_netdev(ndev);
4079err_out_free_regions:
4080 pci_release_regions(pdev);
4081err_out_disable_pdev:
4082 pci_disable_device(pdev);
4083 pci_set_drvdata(pdev, NULL);
4084err_out:
4085 return err;
4086}
4087
4088static void __devexit ql3xxx_remove(struct pci_dev *pdev)
4089{
4090 struct net_device *ndev = pci_get_drvdata(pdev);
4091 struct ql3_adapter *qdev = netdev_priv(ndev);
4092
4093 unregister_netdev(ndev);
4094 qdev = netdev_priv(ndev);
4095
4096 ql_disable_interrupts(qdev);
4097
4098 if (qdev->workqueue) {
4099 cancel_delayed_work(&qdev->reset_work);
4100 cancel_delayed_work(&qdev->tx_timeout_work);
4101 destroy_workqueue(qdev->workqueue);
4102 qdev->workqueue = NULL;
4103 }
4104
855fc73b 4105 iounmap(qdev->mem_map_registers);
5a4faa87
RM		 4106 pci_release_regions(pdev);
4107 pci_set_drvdata(pdev, NULL);
4108 free_netdev(ndev);
4109}
4110
4111static struct pci_driver ql3xxx_driver = {
4112
4113 .name = DRV_NAME,
4114 .id_table = ql3xxx_pci_tbl,
4115 .probe = ql3xxx_probe,
4116 .remove = __devexit_p(ql3xxx_remove),
4117};
4118
4119static int __init ql3xxx_init_module(void)
4120{
4121 return pci_register_driver(&ql3xxx_driver);
4122}
4123
4124static void __exit ql3xxx_exit(void)
4125{
4126 pci_unregister_driver(&ql3xxx_driver);
4127}
4128
4129module_init(ql3xxx_init_module);
4130module_exit(ql3xxx_exit);
Clone of davem's net-next-2.6 tree