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net: Remove unused netdev arg from some NAPI interfaces.
[net-next-2.6.git] / drivers / net / pcnet32.c
CommitLineData
1da177e4
LT		 1/* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2/*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15/**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24#define DRV_NAME "pcnet32"
01935d7d
DF		 25#define DRV_VERSION "1.35"
26#define DRV_RELDATE "21.Apr.2008"
1da177e4
LT		 27#define PFX DRV_NAME ": "
28
4a5e8e29
JG		 29static const char *const version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
1da177e4
LT		 31
32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/string.h>
35#include <linux/errno.h>
36#include <linux/ioport.h>
37#include <linux/slab.h>
38#include <linux/interrupt.h>
39#include <linux/pci.h>
40#include <linux/delay.h>
41#include <linux/init.h>
42#include <linux/ethtool.h>
43#include <linux/mii.h>
44#include <linux/crc32.h>
45#include <linux/netdevice.h>
46#include <linux/etherdevice.h>
47#include <linux/skbuff.h>
48#include <linux/spinlock.h>
49#include <linux/moduleparam.h>
50#include <linux/bitops.h>
51
52#include <asm/dma.h>
53#include <asm/io.h>
54#include <asm/uaccess.h>
55#include <asm/irq.h>
56
57/*
58 * PCI device identifiers for "new style" Linux PCI Device Drivers
59 */
60static struct pci_device_id pcnet32_pci_tbl[] = {
f2622a2b
DF		 61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
4a5e8e29
JG		 63
64 /*
65 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
66 * the incorrect vendor id.
67 */
f2622a2b
DF		 68 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
69 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
4a5e8e29
JG		 70
71 { } /* terminate list */
1da177e4
LT		 72};
73
4a5e8e29 74MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
1da177e4
LT		 75
76static int cards_found;
77
78/*
79 * VLB I/O addresses
80 */
81static unsigned int pcnet32_portlist[] __initdata =
4a5e8e29 82 { 0x300, 0x320, 0x340, 0x360, 0 };
1da177e4
LT		 83
84static int pcnet32_debug = 0;
4a5e8e29
JG		 85static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
86static int pcnet32vlb; /* check for VLB cards ? */
1da177e4
LT		 87
88static struct net_device *pcnet32_dev;
89
90static int max_interrupt_work = 2;
91static int rx_copybreak = 200;
92
93#define PCNET32_PORT_AUI 0x00
94#define PCNET32_PORT_10BT 0x01
95#define PCNET32_PORT_GPSI 0x02
96#define PCNET32_PORT_MII 0x03
97
98#define PCNET32_PORT_PORTSEL 0x03
99#define PCNET32_PORT_ASEL 0x04
100#define PCNET32_PORT_100 0x40
101#define PCNET32_PORT_FD 0x80
102
103#define PCNET32_DMA_MASK 0xffffffff
104
105#define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
106#define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
107
108/*
109 * table to translate option values from tulip
110 * to internal options
111 */
f71e1309 112static const unsigned char options_mapping[] = {
4a5e8e29
JG		 113 PCNET32_PORT_ASEL, /* 0 Auto-select */
114 PCNET32_PORT_AUI, /* 1 BNC/AUI */
115 PCNET32_PORT_AUI, /* 2 AUI/BNC */
116 PCNET32_PORT_ASEL, /* 3 not supported */
117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
118 PCNET32_PORT_ASEL, /* 5 not supported */
119 PCNET32_PORT_ASEL, /* 6 not supported */
120 PCNET32_PORT_ASEL, /* 7 not supported */
121 PCNET32_PORT_ASEL, /* 8 not supported */
122 PCNET32_PORT_MII, /* 9 MII 10baseT */
123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
124 PCNET32_PORT_MII, /* 11 MII (autosel) */
125 PCNET32_PORT_10BT, /* 12 10BaseT */
126 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
127 /* 14 MII 100BaseTx-FD */
128 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
129 PCNET32_PORT_ASEL /* 15 not supported */
1da177e4
LT		 130};
131
132static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
4a5e8e29 133 "Loopback test (offline)"
1da177e4 134};
4a5e8e29 135
4c3616cd 136#define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test)
1da177e4 137
ac62ef04 138#define PCNET32_NUM_REGS 136
1da177e4 139
4a5e8e29 140#define MAX_UNITS 8 /* More are supported, limit only on options */
1da177e4
LT		 141static int options[MAX_UNITS];
142static int full_duplex[MAX_UNITS];
143static int homepna[MAX_UNITS];
144
145/*
146 * Theory of Operation
147 *
148 * This driver uses the same software structure as the normal lance
149 * driver. So look for a verbose description in lance.c. The differences
150 * to the normal lance driver is the use of the 32bit mode of PCnet32
151 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
152 * 16MB limitation and we don't need bounce buffers.
153 */
154
1da177e4
LT		 155/*
156 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
157 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
158 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
159 */
160#ifndef PCNET32_LOG_TX_BUFFERS
eabf0415
HWL		 161#define PCNET32_LOG_TX_BUFFERS 4
162#define PCNET32_LOG_RX_BUFFERS 5
163#define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
164#define PCNET32_LOG_MAX_RX_BUFFERS 9
1da177e4
LT		 165#endif
166
167#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
eabf0415 168#define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
1da177e4
LT		 169
170#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
eabf0415 171#define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
1da177e4 172
232c5640
DF		 173#define PKT_BUF_SKB 1544
174/* actual buffer length after being aligned */
175#define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN)
176/* chip wants twos complement of the (aligned) buffer length */
177#define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB)
1da177e4
LT		 178
179/* Offsets from base I/O address. */
180#define PCNET32_WIO_RDP 0x10
181#define PCNET32_WIO_RAP 0x12
182#define PCNET32_WIO_RESET 0x14
183#define PCNET32_WIO_BDP 0x16
184
185#define PCNET32_DWIO_RDP 0x10
186#define PCNET32_DWIO_RAP 0x14
187#define PCNET32_DWIO_RESET 0x18
188#define PCNET32_DWIO_BDP 0x1C
189
190#define PCNET32_TOTAL_SIZE 0x20
191
06c87850
DF		 192#define CSR0 0
193#define CSR0_INIT 0x1
194#define CSR0_START 0x2
195#define CSR0_STOP 0x4
196#define CSR0_TXPOLL 0x8
197#define CSR0_INTEN 0x40
198#define CSR0_IDON 0x0100
199#define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
200#define PCNET32_INIT_LOW 1
201#define PCNET32_INIT_HIGH 2
202#define CSR3 3
203#define CSR4 4
204#define CSR5 5
205#define CSR5_SUSPEND 0x0001
206#define CSR15 15
207#define PCNET32_MC_FILTER 8
208
8d916266
DF		 209#define PCNET32_79C970A 0x2621
210
1da177e4
LT		 211/* The PCNET32 Rx and Tx ring descriptors. */
212struct pcnet32_rx_head {
3e33545b
AV		 213 __le32 base;
214 __le16 buf_length; /* two`s complement of length */
215 __le16 status;
216 __le32 msg_length;
217 __le32 reserved;
1da177e4
LT		 218};
219
220struct pcnet32_tx_head {
3e33545b
AV		 221 __le32 base;
222 __le16 length; /* two`s complement of length */
223 __le16 status;
224 __le32 misc;
225 __le32 reserved;
1da177e4
LT		 226};
227
228/* The PCNET32 32-Bit initialization block, described in databook. */
229struct pcnet32_init_block {
3e33545b
AV		 230 __le16 mode;
231 __le16 tlen_rlen;
0b5bf225 232 u8 phys_addr[6];
3e33545b
AV		 233 __le16 reserved;
234 __le32 filter[2];
4a5e8e29 235 /* Receive and transmit ring base, along with extra bits. */
3e33545b
AV		 236 __le32 rx_ring;
237 __le32 tx_ring;
1da177e4
LT		 238};
239
240/* PCnet32 access functions */
241struct pcnet32_access {
4a5e8e29
JG		 242 u16 (*read_csr) (unsigned long, int);
243 void (*write_csr) (unsigned long, int, u16);
244 u16 (*read_bcr) (unsigned long, int);
245 void (*write_bcr) (unsigned long, int, u16);
246 u16 (*read_rap) (unsigned long);
247 void (*write_rap) (unsigned long, u16);
248 void (*reset) (unsigned long);
1da177e4
LT		 249};
250
251/*
76209926
HWL		 252 * The first field of pcnet32_private is read by the ethernet device
253 * so the structure should be allocated using pci_alloc_consistent().
1da177e4
LT		 254 */
255struct pcnet32_private {
6ecb7667 256 struct pcnet32_init_block *init_block;
4a5e8e29 257 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
0b5bf225
JG		 258 struct pcnet32_rx_head *rx_ring;
259 struct pcnet32_tx_head *tx_ring;
6ecb7667
DF		 260 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,
261 returned by pci_alloc_consistent */
0b5bf225
JG		 262 struct pci_dev *pci_dev;
263 const char *name;
4a5e8e29 264 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
0b5bf225
JG		 265 struct sk_buff **tx_skbuff;
266 struct sk_buff **rx_skbuff;
267 dma_addr_t *tx_dma_addr;
268 dma_addr_t *rx_dma_addr;
269 struct pcnet32_access a;
270 spinlock_t lock; /* Guard lock */
271 unsigned int cur_rx, cur_tx; /* The next free ring entry */
272 unsigned int rx_ring_size; /* current rx ring size */
273 unsigned int tx_ring_size; /* current tx ring size */
274 unsigned int rx_mod_mask; /* rx ring modular mask */
275 unsigned int tx_mod_mask; /* tx ring modular mask */
276 unsigned short rx_len_bits;
277 unsigned short tx_len_bits;
278 dma_addr_t rx_ring_dma_addr;
279 dma_addr_t tx_ring_dma_addr;
280 unsigned int dirty_rx, /* ring entries to be freed. */
281 dirty_tx;
282
bea3348e
SH		 283 struct net_device *dev;
284 struct napi_struct napi;
0b5bf225
JG		 285 char tx_full;
286 char phycount; /* number of phys found */
287 int options;
288 unsigned int shared_irq:1, /* shared irq possible */
289 dxsuflo:1, /* disable transmit stop on uflo */
290 mii:1; /* mii port available */
291 struct net_device *next;
292 struct mii_if_info mii_if;
293 struct timer_list watchdog_timer;
294 struct timer_list blink_timer;
295 u32 msg_enable; /* debug message level */
4a5e8e29
JG		 296
297 /* each bit indicates an available PHY */
0b5bf225 298 u32 phymask;
8d916266 299 unsigned short chip_version; /* which variant this is */
1da177e4
LT		 300};
301
4a5e8e29
JG		 302static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
303static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
304static int pcnet32_open(struct net_device *);
305static int pcnet32_init_ring(struct net_device *);
306static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
4a5e8e29 307static void pcnet32_tx_timeout(struct net_device *dev);
7d12e780 308static irqreturn_t pcnet32_interrupt(int, void *);
4a5e8e29 309static int pcnet32_close(struct net_device *);
1da177e4
LT		 310static struct net_device_stats *pcnet32_get_stats(struct net_device *);
311static void pcnet32_load_multicast(struct net_device *dev);
312static void pcnet32_set_multicast_list(struct net_device *);
4a5e8e29 313static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
1da177e4
LT		 314static void pcnet32_watchdog(struct net_device *);
315static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
4a5e8e29
JG		 316static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
317 int val);
1da177e4
LT		 318static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
319static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29
JG		 320 struct ethtool_test *eth_test, u64 * data);
321static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
1da177e4
LT		 322static int pcnet32_phys_id(struct net_device *dev, u32 data);
323static void pcnet32_led_blink_callback(struct net_device *dev);
324static int pcnet32_get_regs_len(struct net_device *dev);
325static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 326 void *ptr);
1bcd3153 327static void pcnet32_purge_tx_ring(struct net_device *dev);
b166cfba 328static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
eabf0415 329static void pcnet32_free_ring(struct net_device *dev);
ac62ef04 330static void pcnet32_check_media(struct net_device *dev, int verbose);
eabf0415 331
4a5e8e29 332static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
1da177e4 333{
4a5e8e29
JG		 334 outw(index, addr + PCNET32_WIO_RAP);
335 return inw(addr + PCNET32_WIO_RDP);
1da177e4
LT		 336}
337
4a5e8e29 338static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 339{
4a5e8e29
JG		 340 outw(index, addr + PCNET32_WIO_RAP);
341 outw(val, addr + PCNET32_WIO_RDP);
1da177e4
LT		 342}
343
4a5e8e29 344static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
1da177e4 345{
4a5e8e29
JG		 346 outw(index, addr + PCNET32_WIO_RAP);
347 return inw(addr + PCNET32_WIO_BDP);
1da177e4
LT		 348}
349
4a5e8e29 350static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 351{
4a5e8e29
JG		 352 outw(index, addr + PCNET32_WIO_RAP);
353 outw(val, addr + PCNET32_WIO_BDP);
1da177e4
LT		 354}
355
4a5e8e29 356static u16 pcnet32_wio_read_rap(unsigned long addr)
1da177e4 357{
4a5e8e29 358 return inw(addr + PCNET32_WIO_RAP);
1da177e4
LT		 359}
360
4a5e8e29 361static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
1da177e4 362{
4a5e8e29 363 outw(val, addr + PCNET32_WIO_RAP);
1da177e4
LT		 364}
365
4a5e8e29 366static void pcnet32_wio_reset(unsigned long addr)
1da177e4 367{
4a5e8e29 368 inw(addr + PCNET32_WIO_RESET);
1da177e4
LT		 369}
370
4a5e8e29 371static int pcnet32_wio_check(unsigned long addr)
1da177e4 372{
4a5e8e29
JG		 373 outw(88, addr + PCNET32_WIO_RAP);
374 return (inw(addr + PCNET32_WIO_RAP) == 88);
1da177e4
LT		 375}
376
377static struct pcnet32_access pcnet32_wio = {
4a5e8e29
JG		 378 .read_csr = pcnet32_wio_read_csr,
379 .write_csr = pcnet32_wio_write_csr,
380 .read_bcr = pcnet32_wio_read_bcr,
381 .write_bcr = pcnet32_wio_write_bcr,
382 .read_rap = pcnet32_wio_read_rap,
383 .write_rap = pcnet32_wio_write_rap,
384 .reset = pcnet32_wio_reset
1da177e4
LT		 385};
386
4a5e8e29 387static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
1da177e4 388{
4a5e8e29
JG		 389 outl(index, addr + PCNET32_DWIO_RAP);
390 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
1da177e4
LT		 391}
392
4a5e8e29 393static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 394{
4a5e8e29
JG		 395 outl(index, addr + PCNET32_DWIO_RAP);
396 outl(val, addr + PCNET32_DWIO_RDP);
1da177e4
LT		 397}
398
4a5e8e29 399static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
1da177e4 400{
4a5e8e29
JG		 401 outl(index, addr + PCNET32_DWIO_RAP);
402 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
1da177e4
LT		 403}
404
4a5e8e29 405static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 406{
4a5e8e29
JG		 407 outl(index, addr + PCNET32_DWIO_RAP);
408 outl(val, addr + PCNET32_DWIO_BDP);
1da177e4
LT		 409}
410
4a5e8e29 411static u16 pcnet32_dwio_read_rap(unsigned long addr)
1da177e4 412{
4a5e8e29 413 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
1da177e4
LT		 414}
415
4a5e8e29 416static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
1da177e4 417{
4a5e8e29 418 outl(val, addr + PCNET32_DWIO_RAP);
1da177e4
LT		 419}
420
4a5e8e29 421static void pcnet32_dwio_reset(unsigned long addr)
1da177e4 422{
4a5e8e29 423 inl(addr + PCNET32_DWIO_RESET);
1da177e4
LT		 424}
425
4a5e8e29 426static int pcnet32_dwio_check(unsigned long addr)
1da177e4 427{
4a5e8e29
JG		 428 outl(88, addr + PCNET32_DWIO_RAP);
429 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
1da177e4
LT		 430}
431
432static struct pcnet32_access pcnet32_dwio = {
4a5e8e29
JG		 433 .read_csr = pcnet32_dwio_read_csr,
434 .write_csr = pcnet32_dwio_write_csr,
435 .read_bcr = pcnet32_dwio_read_bcr,
436 .write_bcr = pcnet32_dwio_write_bcr,
437 .read_rap = pcnet32_dwio_read_rap,
438 .write_rap = pcnet32_dwio_write_rap,
439 .reset = pcnet32_dwio_reset
1da177e4
LT		 440};
441
06c87850
DF		 442static void pcnet32_netif_stop(struct net_device *dev)
443{
bea3348e 444 struct pcnet32_private *lp = netdev_priv(dev);
01935d7d 445
06c87850 446 dev->trans_start = jiffies;
bea3348e 447 napi_disable(&lp->napi);
06c87850
DF		 448 netif_tx_disable(dev);
449}
450
451static void pcnet32_netif_start(struct net_device *dev)
452{
bea3348e 453 struct pcnet32_private *lp = netdev_priv(dev);
d1d08d12
DM		 454 ulong ioaddr = dev->base_addr;
455 u16 val;
01935d7d 456
06c87850 457 netif_wake_queue(dev);
d1d08d12
DM		 458 val = lp->a.read_csr(ioaddr, CSR3);
459 val &= 0x00ff;
460 lp->a.write_csr(ioaddr, CSR3, val);
bea3348e 461 napi_enable(&lp->napi);
06c87850
DF		 462}
463
464/*
465 * Allocate space for the new sized tx ring.
466 * Free old resources
467 * Save new resources.
468 * Any failure keeps old resources.
469 * Must be called with lp->lock held.
470 */
471static void pcnet32_realloc_tx_ring(struct net_device *dev,
472 struct pcnet32_private *lp,
473 unsigned int size)
474{
475 dma_addr_t new_ring_dma_addr;
476 dma_addr_t *new_dma_addr_list;
477 struct pcnet32_tx_head *new_tx_ring;
478 struct sk_buff **new_skb_list;
479
480 pcnet32_purge_tx_ring(dev);
481
482 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
483 sizeof(struct pcnet32_tx_head) *
484 (1 << size),
485 &new_ring_dma_addr);
486 if (new_tx_ring == NULL) {
487 if (netif_msg_drv(lp))
488 printk("\n" KERN_ERR
489 "%s: Consistent memory allocation failed.\n",
490 dev->name);
491 return;
492 }
493 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
494
495 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
496 GFP_ATOMIC);
497 if (!new_dma_addr_list) {
498 if (netif_msg_drv(lp))
499 printk("\n" KERN_ERR
500 "%s: Memory allocation failed.\n", dev->name);
501 goto free_new_tx_ring;
502 }
503
504 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
505 GFP_ATOMIC);
506 if (!new_skb_list) {
507 if (netif_msg_drv(lp))
508 printk("\n" KERN_ERR
509 "%s: Memory allocation failed.\n", dev->name);
510 goto free_new_lists;
511 }
512
513 kfree(lp->tx_skbuff);
514 kfree(lp->tx_dma_addr);
515 pci_free_consistent(lp->pci_dev,
516 sizeof(struct pcnet32_tx_head) *
517 lp->tx_ring_size, lp->tx_ring,
518 lp->tx_ring_dma_addr);
519
520 lp->tx_ring_size = (1 << size);
521 lp->tx_mod_mask = lp->tx_ring_size - 1;
522 lp->tx_len_bits = (size << 12);
523 lp->tx_ring = new_tx_ring;
524 lp->tx_ring_dma_addr = new_ring_dma_addr;
525 lp->tx_dma_addr = new_dma_addr_list;
526 lp->tx_skbuff = new_skb_list;
527 return;
528
529 free_new_lists:
530 kfree(new_dma_addr_list);
531 free_new_tx_ring:
532 pci_free_consistent(lp->pci_dev,
533 sizeof(struct pcnet32_tx_head) *
534 (1 << size),
535 new_tx_ring,
536 new_ring_dma_addr);
537 return;
538}
539
540/*
541 * Allocate space for the new sized rx ring.
542 * Re-use old receive buffers.
543 * alloc extra buffers
544 * free unneeded buffers
545 * free unneeded buffers
546 * Save new resources.
547 * Any failure keeps old resources.
548 * Must be called with lp->lock held.
549 */
550static void pcnet32_realloc_rx_ring(struct net_device *dev,
551 struct pcnet32_private *lp,
552 unsigned int size)
553{
554 dma_addr_t new_ring_dma_addr;
555 dma_addr_t *new_dma_addr_list;
556 struct pcnet32_rx_head *new_rx_ring;
557 struct sk_buff **new_skb_list;
558 int new, overlap;
559
560 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
561 sizeof(struct pcnet32_rx_head) *
562 (1 << size),
563 &new_ring_dma_addr);
564 if (new_rx_ring == NULL) {
565 if (netif_msg_drv(lp))
566 printk("\n" KERN_ERR
567 "%s: Consistent memory allocation failed.\n",
568 dev->name);
569 return;
570 }
571 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
572
573 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
574 GFP_ATOMIC);
575 if (!new_dma_addr_list) {
576 if (netif_msg_drv(lp))
577 printk("\n" KERN_ERR
578 "%s: Memory allocation failed.\n", dev->name);
579 goto free_new_rx_ring;
580 }
581
582 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
583 GFP_ATOMIC);
584 if (!new_skb_list) {
585 if (netif_msg_drv(lp))
586 printk("\n" KERN_ERR
587 "%s: Memory allocation failed.\n", dev->name);
588 goto free_new_lists;
589 }
590
591 /* first copy the current receive buffers */
592 overlap = min(size, lp->rx_ring_size);
593 for (new = 0; new < overlap; new++) {
594 new_rx_ring[new] = lp->rx_ring[new];
595 new_dma_addr_list[new] = lp->rx_dma_addr[new];
596 new_skb_list[new] = lp->rx_skbuff[new];
597 }
598 /* now allocate any new buffers needed */
599 for (; new < size; new++ ) {
600 struct sk_buff *rx_skbuff;
232c5640 601 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SKB);
06c87850
DF		 602 if (!(rx_skbuff = new_skb_list[new])) {
603 /* keep the original lists and buffers */
604 if (netif_msg_drv(lp))
605 printk(KERN_ERR
606 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
607 dev->name);
608 goto free_all_new;
609 }
232c5640 610 skb_reserve(rx_skbuff, NET_IP_ALIGN);
06c87850
DF		 611
612 new_dma_addr_list[new] =
613 pci_map_single(lp->pci_dev, rx_skbuff->data,
232c5640 614 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
3e33545b 615 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
232c5640 616 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
3e33545b 617 new_rx_ring[new].status = cpu_to_le16(0x8000);
06c87850
DF		 618 }
619 /* and free any unneeded buffers */
620 for (; new < lp->rx_ring_size; new++) {
621 if (lp->rx_skbuff[new]) {
622 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
232c5640 623 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
06c87850
DF		 624 dev_kfree_skb(lp->rx_skbuff[new]);
625 }
626 }
627
628 kfree(lp->rx_skbuff);
629 kfree(lp->rx_dma_addr);
630 pci_free_consistent(lp->pci_dev,
631 sizeof(struct pcnet32_rx_head) *
632 lp->rx_ring_size, lp->rx_ring,
633 lp->rx_ring_dma_addr);
634
635 lp->rx_ring_size = (1 << size);
636 lp->rx_mod_mask = lp->rx_ring_size - 1;
637 lp->rx_len_bits = (size << 4);
638 lp->rx_ring = new_rx_ring;
639 lp->rx_ring_dma_addr = new_ring_dma_addr;
640 lp->rx_dma_addr = new_dma_addr_list;
641 lp->rx_skbuff = new_skb_list;
642 return;
643
644 free_all_new:
645 for (; --new >= lp->rx_ring_size; ) {
646 if (new_skb_list[new]) {
647 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
232c5640 648 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
06c87850
DF		 649 dev_kfree_skb(new_skb_list[new]);
650 }
651 }
652 kfree(new_skb_list);
653 free_new_lists:
654 kfree(new_dma_addr_list);
655 free_new_rx_ring:
656 pci_free_consistent(lp->pci_dev,
657 sizeof(struct pcnet32_rx_head) *
658 (1 << size),
659 new_rx_ring,
660 new_ring_dma_addr);
661 return;
662}
663
ac5bfe40
DF		 664static void pcnet32_purge_rx_ring(struct net_device *dev)
665{
1e56a4b4 666 struct pcnet32_private *lp = netdev_priv(dev);
ac5bfe40
DF		 667 int i;
668
669 /* free all allocated skbuffs */
670 for (i = 0; i < lp->rx_ring_size; i++) {
671 lp->rx_ring[i].status = 0; /* CPU owns buffer */
672 wmb(); /* Make sure adapter sees owner change */
673 if (lp->rx_skbuff[i]) {
674 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
232c5640 675 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
ac5bfe40
DF		 676 dev_kfree_skb_any(lp->rx_skbuff[i]);
677 }
678 lp->rx_skbuff[i] = NULL;
679 lp->rx_dma_addr[i] = 0;
680 }
681}
682
1da177e4
LT		 683#ifdef CONFIG_NET_POLL_CONTROLLER
684static void pcnet32_poll_controller(struct net_device *dev)
685{
4a5e8e29 686 disable_irq(dev->irq);
7d12e780 687 pcnet32_interrupt(0, dev);
4a5e8e29 688 enable_irq(dev->irq);
1da177e4
LT		 689}
690#endif
691
1da177e4
LT		 692static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
693{
1e56a4b4 694 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 695 unsigned long flags;
696 int r = -EOPNOTSUPP;
1da177e4 697
4a5e8e29
JG		 698 if (lp->mii) {
699 spin_lock_irqsave(&lp->lock, flags);
700 mii_ethtool_gset(&lp->mii_if, cmd);
701 spin_unlock_irqrestore(&lp->lock, flags);
702 r = 0;
703 }
704 return r;
1da177e4
LT		 705}
706
707static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
708{
1e56a4b4 709 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 710 unsigned long flags;
711 int r = -EOPNOTSUPP;
1da177e4 712
4a5e8e29
JG		 713 if (lp->mii) {
714 spin_lock_irqsave(&lp->lock, flags);
715 r = mii_ethtool_sset(&lp->mii_if, cmd);
716 spin_unlock_irqrestore(&lp->lock, flags);
717 }
718 return r;
1da177e4
LT		 719}
720
4a5e8e29
JG		 721static void pcnet32_get_drvinfo(struct net_device *dev,
722 struct ethtool_drvinfo *info)
1da177e4 723{
1e56a4b4 724 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 725
726 strcpy(info->driver, DRV_NAME);
727 strcpy(info->version, DRV_VERSION);
728 if (lp->pci_dev)
729 strcpy(info->bus_info, pci_name(lp->pci_dev));
730 else
731 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
1da177e4
LT		 732}
733
734static u32 pcnet32_get_link(struct net_device *dev)
735{
1e56a4b4 736 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 737 unsigned long flags;
738 int r;
1da177e4 739
4a5e8e29
JG		 740 spin_lock_irqsave(&lp->lock, flags);
741 if (lp->mii) {
742 r = mii_link_ok(&lp->mii_if);
8d916266 743 } else if (lp->chip_version >= PCNET32_79C970A) {
4a5e8e29
JG		 744 ulong ioaddr = dev->base_addr; /* card base I/O address */
745 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
8d916266
DF		 746 } else { /* can not detect link on really old chips */
747 r = 1;
4a5e8e29
JG		 748 }
749 spin_unlock_irqrestore(&lp->lock, flags);
750
751 return r;
1da177e4
LT		 752}
753
754static u32 pcnet32_get_msglevel(struct net_device *dev)
755{
1e56a4b4 756 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 757 return lp->msg_enable;
1da177e4
LT		 758}
759
760static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
761{
1e56a4b4 762 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 763 lp->msg_enable = value;
1da177e4
LT		 764}
765
766static int pcnet32_nway_reset(struct net_device *dev)
767{
1e56a4b4 768 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 769 unsigned long flags;
770 int r = -EOPNOTSUPP;
1da177e4 771
4a5e8e29
JG		 772 if (lp->mii) {
773 spin_lock_irqsave(&lp->lock, flags);
774 r = mii_nway_restart(&lp->mii_if);
775 spin_unlock_irqrestore(&lp->lock, flags);
776 }
777 return r;
1da177e4
LT		 778}
779
4a5e8e29
JG		 780static void pcnet32_get_ringparam(struct net_device *dev,
781 struct ethtool_ringparam *ering)
1da177e4 782{
1e56a4b4 783 struct pcnet32_private *lp = netdev_priv(dev);
1da177e4 784
6dcd60c2
DF		 785 ering->tx_max_pending = TX_MAX_RING_SIZE;
786 ering->tx_pending = lp->tx_ring_size;
787 ering->rx_max_pending = RX_MAX_RING_SIZE;
788 ering->rx_pending = lp->rx_ring_size;
eabf0415
HWL		 789}
790
4a5e8e29
JG		 791static int pcnet32_set_ringparam(struct net_device *dev,
792 struct ethtool_ringparam *ering)
eabf0415 793{
1e56a4b4 794 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 795 unsigned long flags;
06c87850
DF		 796 unsigned int size;
797 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 798 int i;
799
800 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
801 return -EINVAL;
802
803 if (netif_running(dev))
06c87850 804 pcnet32_netif_stop(dev);
4a5e8e29
JG		 805
806 spin_lock_irqsave(&lp->lock, flags);
06c87850
DF		 807 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
808
809 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
4a5e8e29
JG		 810
811 /* set the minimum ring size to 4, to allow the loopback test to work
812 * unchanged.
813 */
814 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
06c87850 815 if (size <= (1 << i))
4a5e8e29
JG		 816 break;
817 }
06c87850
DF		 818 if ((1 << i) != lp->tx_ring_size)
819 pcnet32_realloc_tx_ring(dev, lp, i);
b368a3fb 820
06c87850 821 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
4a5e8e29 822 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
06c87850 823 if (size <= (1 << i))
4a5e8e29
JG		 824 break;
825 }
06c87850
DF		 826 if ((1 << i) != lp->rx_ring_size)
827 pcnet32_realloc_rx_ring(dev, lp, i);
b368a3fb 828
bea3348e 829 lp->napi.weight = lp->rx_ring_size / 2;
06c87850
DF		 830
831 if (netif_running(dev)) {
832 pcnet32_netif_start(dev);
833 pcnet32_restart(dev, CSR0_NORMAL);
4a5e8e29 834 }
eabf0415 835
4a5e8e29 836 spin_unlock_irqrestore(&lp->lock, flags);
eabf0415 837
06c87850
DF		 838 if (netif_msg_drv(lp))
839 printk(KERN_INFO
4a5e8e29
JG		 840 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
841 lp->rx_ring_size, lp->tx_ring_size);
eabf0415 842
4a5e8e29 843 return 0;
1da177e4
LT		 844}
845
4a5e8e29
JG		 846static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
847 u8 * data)
1da177e4 848{
4a5e8e29 849 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
1da177e4
LT		 850}
851
b9f2c044 852static int pcnet32_get_sset_count(struct net_device *dev, int sset)
1da177e4 853{
b9f2c044
JG		 854 switch (sset) {
855 case ETH_SS_TEST:
856 return PCNET32_TEST_LEN;
857 default:
858 return -EOPNOTSUPP;
859 }
1da177e4
LT		 860}
861
862static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29 863 struct ethtool_test *test, u64 * data)
1da177e4 864{
1e56a4b4 865 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 866 int rc;
867
868 if (test->flags == ETH_TEST_FL_OFFLINE) {
869 rc = pcnet32_loopback_test(dev, data);
870 if (rc) {
871 if (netif_msg_hw(lp))
872 printk(KERN_DEBUG "%s: Loopback test failed.\n",
873 dev->name);
874 test->flags |= ETH_TEST_FL_FAILED;
875 } else if (netif_msg_hw(lp))
876 printk(KERN_DEBUG "%s: Loopback test passed.\n",
877 dev->name);
1da177e4 878 } else if (netif_msg_hw(lp))
4a5e8e29
JG		 879 printk(KERN_DEBUG
880 "%s: No tests to run (specify 'Offline' on ethtool).",
881 dev->name);
882} /* end pcnet32_ethtool_test */
1da177e4 883
4a5e8e29 884static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
1da177e4 885{
1e56a4b4 886 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 887 struct pcnet32_access *a = &lp->a; /* access to registers */
888 ulong ioaddr = dev->base_addr; /* card base I/O address */
889 struct sk_buff *skb; /* sk buff */
890 int x, i; /* counters */
891 int numbuffs = 4; /* number of TX/RX buffers and descs */
892 u16 status = 0x8300; /* TX ring status */
3e33545b 893 __le16 teststatus; /* test of ring status */
4a5e8e29
JG		 894 int rc; /* return code */
895 int size; /* size of packets */
896 unsigned char *packet; /* source packet data */
897 static const int data_len = 60; /* length of source packets */
898 unsigned long flags;
899 unsigned long ticks;
900
4a5e8e29
JG		 901 rc = 1; /* default to fail */
902
903 if (netif_running(dev))
7de745e5 904 pcnet32_netif_stop(dev);
4a5e8e29
JG		 905
906 spin_lock_irqsave(&lp->lock, flags);
ac5bfe40
DF		 907 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
908
909 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
4a5e8e29
JG		 910
911 /* Reset the PCNET32 */
912 lp->a.reset(ioaddr);
b368a3fb 913 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
4a5e8e29
JG		 914
915 /* switch pcnet32 to 32bit mode */
916 lp->a.write_bcr(ioaddr, 20, 2);
917
4a5e8e29
JG		 918 /* purge & init rings but don't actually restart */
919 pcnet32_restart(dev, 0x0000);
920
ac5bfe40 921 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 922
923 /* Initialize Transmit buffers. */
924 size = data_len + 15;
925 for (x = 0; x < numbuffs; x++) {
926 if (!(skb = dev_alloc_skb(size))) {
927 if (netif_msg_hw(lp))
928 printk(KERN_DEBUG
929 "%s: Cannot allocate skb at line: %d!\n",
930 dev->name, __LINE__);
931 goto clean_up;
932 } else {
933 packet = skb->data;
934 skb_put(skb, size); /* create space for data */
935 lp->tx_skbuff[x] = skb;
3e33545b 936 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
4a5e8e29
JG		 937 lp->tx_ring[x].misc = 0;
938
939 /* put DA and SA into the skb */
940 for (i = 0; i < 6; i++)
941 *packet++ = dev->dev_addr[i];
942 for (i = 0; i < 6; i++)
943 *packet++ = dev->dev_addr[i];
944 /* type */
945 *packet++ = 0x08;
946 *packet++ = 0x06;
947 /* packet number */
948 *packet++ = x;
949 /* fill packet with data */
950 for (i = 0; i < data_len; i++)
951 *packet++ = i;
952
953 lp->tx_dma_addr[x] =
954 pci_map_single(lp->pci_dev, skb->data, skb->len,
955 PCI_DMA_TODEVICE);
3e33545b 956 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
4a5e8e29 957 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 958 lp->tx_ring[x].status = cpu_to_le16(status);
4a5e8e29 959 }
1da177e4 960 }
1da177e4 961
ac5bfe40
DF		 962 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
963 a->write_bcr(ioaddr, 32, x | 0x0002);
4a5e8e29 964
ac5bfe40
DF		 965 /* set int loopback in CSR15 */
966 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
967 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
4a5e8e29 968
3e33545b 969 teststatus = cpu_to_le16(0x8000);
ac5bfe40 970 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
4a5e8e29
JG		 971
972 /* Check status of descriptors */
973 for (x = 0; x < numbuffs; x++) {
974 ticks = 0;
975 rmb();
976 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
977 spin_unlock_irqrestore(&lp->lock, flags);
ac5bfe40 978 msleep(1);
4a5e8e29
JG		 979 spin_lock_irqsave(&lp->lock, flags);
980 rmb();
981 ticks++;
982 }
983 if (ticks == 200) {
984 if (netif_msg_hw(lp))
985 printk("%s: Desc %d failed to reset!\n",
986 dev->name, x);
987 break;
988 }
989 }
990
ac5bfe40 991 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 992 wmb();
993 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
994 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
995
996 for (x = 0; x < numbuffs; x++) {
997 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
998 skb = lp->rx_skbuff[x];
999 for (i = 0; i < size; i++) {
1000 printk("%02x ", *(skb->data + i));
1001 }
1002 printk("\n");
1003 }
1004 }
1da177e4 1005
4a5e8e29
JG		 1006 x = 0;
1007 rc = 0;
1008 while (x < numbuffs && !rc) {
1009 skb = lp->rx_skbuff[x];
1010 packet = lp->tx_skbuff[x]->data;
1011 for (i = 0; i < size; i++) {
1012 if (*(skb->data + i) != packet[i]) {
1013 if (netif_msg_hw(lp))
1014 printk(KERN_DEBUG
1015 "%s: Error in compare! %2x - %02x %02x\n",
1016 dev->name, i, *(skb->data + i),
1017 packet[i]);
1018 rc = 1;
1019 break;
1020 }
1021 }
1022 x++;
1023 }
1da177e4 1024
4a5e8e29 1025 clean_up:
ac5bfe40 1026 *data1 = rc;
4a5e8e29 1027 pcnet32_purge_tx_ring(dev);
1da177e4 1028
ac5bfe40
DF		 1029 x = a->read_csr(ioaddr, CSR15);
1030 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1da177e4 1031
ac5bfe40
DF		 1032 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1033 a->write_bcr(ioaddr, 32, (x & ~0x0002));
4a5e8e29 1034
7de745e5
DF		 1035 if (netif_running(dev)) {
1036 pcnet32_netif_start(dev);
1037 pcnet32_restart(dev, CSR0_NORMAL);
1038 } else {
1039 pcnet32_purge_rx_ring(dev);
1040 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1041 }
1042 spin_unlock_irqrestore(&lp->lock, flags);
4a5e8e29
JG		 1043
1044 return (rc);
1045} /* end pcnet32_loopback_test */
1da177e4
LT		 1046
1047static void pcnet32_led_blink_callback(struct net_device *dev)
1048{
1e56a4b4 1049 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1050 struct pcnet32_access *a = &lp->a;
1051 ulong ioaddr = dev->base_addr;
1052 unsigned long flags;
1053 int i;
1054
1055 spin_lock_irqsave(&lp->lock, flags);
1056 for (i = 4; i < 8; i++) {
1057 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1058 }
1059 spin_unlock_irqrestore(&lp->lock, flags);
1060
1061 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1da177e4
LT		 1062}
1063
1064static int pcnet32_phys_id(struct net_device *dev, u32 data)
1065{
1e56a4b4 1066 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1067 struct pcnet32_access *a = &lp->a;
1068 ulong ioaddr = dev->base_addr;
1069 unsigned long flags;
1070 int i, regs[4];
1071
1072 if (!lp->blink_timer.function) {
1073 init_timer(&lp->blink_timer);
1074 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1075 lp->blink_timer.data = (unsigned long)dev;
1076 }
1077
1078 /* Save the current value of the bcrs */
1079 spin_lock_irqsave(&lp->lock, flags);
1080 for (i = 4; i < 8; i++) {
1081 regs[i - 4] = a->read_bcr(ioaddr, i);
1082 }
1083 spin_unlock_irqrestore(&lp->lock, flags);
1084
1085 mod_timer(&lp->blink_timer, jiffies);
1086 set_current_state(TASK_INTERRUPTIBLE);
1087
3e33545b 1088 /* AV: the limit here makes no sense whatsoever */
4a5e8e29
JG		 1089 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1090 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1091
1092 msleep_interruptible(data * 1000);
1093 del_timer_sync(&lp->blink_timer);
1094
1095 /* Restore the original value of the bcrs */
1096 spin_lock_irqsave(&lp->lock, flags);
1097 for (i = 4; i < 8; i++) {
1098 a->write_bcr(ioaddr, i, regs[i - 4]);
1099 }
1100 spin_unlock_irqrestore(&lp->lock, flags);
1101
1102 return 0;
1da177e4
LT		 1103}
1104
df27f4a6
DF		 1105/*
1106 * lp->lock must be held.
1107 */
1108static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1109 int can_sleep)
1110{
1111 int csr5;
1e56a4b4 1112 struct pcnet32_private *lp = netdev_priv(dev);
df27f4a6
DF		 1113 struct pcnet32_access *a = &lp->a;
1114 ulong ioaddr = dev->base_addr;
1115 int ticks;
1116
8d916266
DF		 1117 /* really old chips have to be stopped. */
1118 if (lp->chip_version < PCNET32_79C970A)
1119 return 0;
1120
df27f4a6
DF		 1121 /* set SUSPEND (SPND) - CSR5 bit 0 */
1122 csr5 = a->read_csr(ioaddr, CSR5);
1123 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1124
1125 /* poll waiting for bit to be set */
1126 ticks = 0;
1127 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1128 spin_unlock_irqrestore(&lp->lock, *flags);
1129 if (can_sleep)
1130 msleep(1);
1131 else
1132 mdelay(1);
1133 spin_lock_irqsave(&lp->lock, *flags);
1134 ticks++;
1135 if (ticks > 200) {
1136 if (netif_msg_hw(lp))
1137 printk(KERN_DEBUG
1138 "%s: Error getting into suspend!\n",
1139 dev->name);
1140 return 0;
1141 }
1142 }
1143 return 1;
1144}
1145
3904c324
DF		 1146/*
1147 * process one receive descriptor entry
1148 */
1149
1150static void pcnet32_rx_entry(struct net_device *dev,
1151 struct pcnet32_private *lp,
1152 struct pcnet32_rx_head *rxp,
1153 int entry)
1154{
1155 int status = (short)le16_to_cpu(rxp->status) >> 8;
1156 int rx_in_place = 0;
1157 struct sk_buff *skb;
1158 short pkt_len;
1159
1160 if (status != 0x03) { /* There was an error. */
1161 /*
1162 * There is a tricky error noted by John Murphy,
1163 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1164 * buffers it's possible for a jabber packet to use two
1165 * buffers, with only the last correctly noting the error.
1166 */
1167 if (status & 0x01) /* Only count a general error at the */
4f1e5ba0 1168 dev->stats.rx_errors++; /* end of a packet. */
3904c324 1169 if (status & 0x20)
4f1e5ba0 1170 dev->stats.rx_frame_errors++;
3904c324 1171 if (status & 0x10)
4f1e5ba0 1172 dev->stats.rx_over_errors++;
3904c324 1173 if (status & 0x08)
4f1e5ba0 1174 dev->stats.rx_crc_errors++;
3904c324 1175 if (status & 0x04)
4f1e5ba0 1176 dev->stats.rx_fifo_errors++;
3904c324
DF		 1177 return;
1178 }
1179
1180 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1181
1182 /* Discard oversize frames. */
232c5640 1183 if (unlikely(pkt_len > PKT_BUF_SIZE)) {
3904c324
DF		 1184 if (netif_msg_drv(lp))
1185 printk(KERN_ERR "%s: Impossible packet size %d!\n",
1186 dev->name, pkt_len);
4f1e5ba0 1187 dev->stats.rx_errors++;
3904c324
DF		 1188 return;
1189 }
1190 if (pkt_len < 60) {
1191 if (netif_msg_rx_err(lp))
1192 printk(KERN_ERR "%s: Runt packet!\n", dev->name);
4f1e5ba0 1193 dev->stats.rx_errors++;
3904c324
DF		 1194 return;
1195 }
1196
1197 if (pkt_len > rx_copybreak) {
1198 struct sk_buff *newskb;
1199
232c5640
DF		 1200 if ((newskb = dev_alloc_skb(PKT_BUF_SKB))) {
1201 skb_reserve(newskb, NET_IP_ALIGN);
3904c324
DF		 1202 skb = lp->rx_skbuff[entry];
1203 pci_unmap_single(lp->pci_dev,
1204 lp->rx_dma_addr[entry],
232c5640 1205 PKT_BUF_SIZE,
3904c324
DF		 1206 PCI_DMA_FROMDEVICE);
1207 skb_put(skb, pkt_len);
1208 lp->rx_skbuff[entry] = newskb;
3904c324
DF		 1209 lp->rx_dma_addr[entry] =
1210 pci_map_single(lp->pci_dev,
1211 newskb->data,
232c5640 1212 PKT_BUF_SIZE,
3904c324 1213 PCI_DMA_FROMDEVICE);
3e33545b 1214 rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
3904c324
DF		 1215 rx_in_place = 1;
1216 } else
1217 skb = NULL;
1218 } else {
232c5640 1219 skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN);
3904c324
DF		 1220 }
1221
1222 if (skb == NULL) {
1223 if (netif_msg_drv(lp))
1224 printk(KERN_ERR
1225 "%s: Memory squeeze, dropping packet.\n",
1226 dev->name);
4f1e5ba0 1227 dev->stats.rx_dropped++;
3904c324
DF		 1228 return;
1229 }
1230 skb->dev = dev;
1231 if (!rx_in_place) {
232c5640 1232 skb_reserve(skb, NET_IP_ALIGN);
3904c324
DF		 1233 skb_put(skb, pkt_len); /* Make room */
1234 pci_dma_sync_single_for_cpu(lp->pci_dev,
1235 lp->rx_dma_addr[entry],
b2cbbd8e 1236 pkt_len,
3904c324 1237 PCI_DMA_FROMDEVICE);
8c7b7faa 1238 skb_copy_to_linear_data(skb,
3904c324 1239 (unsigned char *)(lp->rx_skbuff[entry]->data),
8c7b7faa 1240 pkt_len);
3904c324
DF		 1241 pci_dma_sync_single_for_device(lp->pci_dev,
1242 lp->rx_dma_addr[entry],
b2cbbd8e 1243 pkt_len,
3904c324
DF		 1244 PCI_DMA_FROMDEVICE);
1245 }
4f1e5ba0 1246 dev->stats.rx_bytes += skb->len;
3904c324 1247 skb->protocol = eth_type_trans(skb, dev);
7de745e5 1248 netif_receive_skb(skb);
4f1e5ba0 1249 dev->stats.rx_packets++;
3904c324
DF		 1250 return;
1251}
1252
bea3348e 1253static int pcnet32_rx(struct net_device *dev, int budget)
9691edd2 1254{
1e56a4b4 1255 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2 1256 int entry = lp->cur_rx & lp->rx_mod_mask;
3904c324
DF		 1257 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1258 int npackets = 0;
9691edd2
DF		 1259
1260 /* If we own the next entry, it's a new packet. Send it up. */
bea3348e 1261 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
3904c324
DF		 1262 pcnet32_rx_entry(dev, lp, rxp, entry);
1263 npackets += 1;
9691edd2 1264 /*
3904c324
DF		 1265 * The docs say that the buffer length isn't touched, but Andrew
1266 * Boyd of QNX reports that some revs of the 79C965 clear it.
9691edd2 1267 */
232c5640 1268 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
3904c324 1269 wmb(); /* Make sure owner changes after others are visible */
3e33545b 1270 rxp->status = cpu_to_le16(0x8000);
9691edd2 1271 entry = (++lp->cur_rx) & lp->rx_mod_mask;
3904c324 1272 rxp = &lp->rx_ring[entry];
9691edd2
DF		 1273 }
1274
7de745e5 1275 return npackets;
9691edd2
DF		 1276}
1277
7de745e5 1278static int pcnet32_tx(struct net_device *dev)
9691edd2 1279{
1e56a4b4 1280 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2
DF		 1281 unsigned int dirty_tx = lp->dirty_tx;
1282 int delta;
1283 int must_restart = 0;
1284
1285 while (dirty_tx != lp->cur_tx) {
1286 int entry = dirty_tx & lp->tx_mod_mask;
1287 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1288
1289 if (status < 0)
1290 break; /* It still hasn't been Txed */
1291
1292 lp->tx_ring[entry].base = 0;
1293
1294 if (status & 0x4000) {
3904c324 1295 /* There was a major error, log it. */
9691edd2 1296 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
4f1e5ba0 1297 dev->stats.tx_errors++;
9691edd2
DF		 1298 if (netif_msg_tx_err(lp))
1299 printk(KERN_ERR
1300 "%s: Tx error status=%04x err_status=%08x\n",
1301 dev->name, status,
1302 err_status);
1303 if (err_status & 0x04000000)
4f1e5ba0 1304 dev->stats.tx_aborted_errors++;
9691edd2 1305 if (err_status & 0x08000000)
4f1e5ba0 1306 dev->stats.tx_carrier_errors++;
9691edd2 1307 if (err_status & 0x10000000)
4f1e5ba0 1308 dev->stats.tx_window_errors++;
9691edd2
DF		 1309#ifndef DO_DXSUFLO
1310 if (err_status & 0x40000000) {
4f1e5ba0 1311 dev->stats.tx_fifo_errors++;
9691edd2
DF		 1312 /* Ackk! On FIFO errors the Tx unit is turned off! */
1313 /* Remove this verbosity later! */
1314 if (netif_msg_tx_err(lp))
1315 printk(KERN_ERR
7de745e5
DF		 1316 "%s: Tx FIFO error!\n",
1317 dev->name);
9691edd2
DF		 1318 must_restart = 1;
1319 }
1320#else
1321 if (err_status & 0x40000000) {
4f1e5ba0 1322 dev->stats.tx_fifo_errors++;
9691edd2
DF		 1323 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1324 /* Ackk! On FIFO errors the Tx unit is turned off! */
1325 /* Remove this verbosity later! */
3904c324 1326 if (netif_msg_tx_err(lp))
9691edd2 1327 printk(KERN_ERR
7de745e5
DF		 1328 "%s: Tx FIFO error!\n",
1329 dev->name);
9691edd2
DF		 1330 must_restart = 1;
1331 }
1332 }
1333#endif
1334 } else {
1335 if (status & 0x1800)
4f1e5ba0
DF		 1336 dev->stats.collisions++;
1337 dev->stats.tx_packets++;
9691edd2
DF		 1338 }
1339
1340 /* We must free the original skb */
1341 if (lp->tx_skbuff[entry]) {
1342 pci_unmap_single(lp->pci_dev,
1343 lp->tx_dma_addr[entry],
1344 lp->tx_skbuff[entry]->
1345 len, PCI_DMA_TODEVICE);
3904c324 1346 dev_kfree_skb_any(lp->tx_skbuff[entry]);
9691edd2
DF		 1347 lp->tx_skbuff[entry] = NULL;
1348 lp->tx_dma_addr[entry] = 0;
1349 }
1350 dirty_tx++;
1351 }
1352
3904c324 1353 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
9691edd2
DF		 1354 if (delta > lp->tx_ring_size) {
1355 if (netif_msg_drv(lp))
1356 printk(KERN_ERR
1357 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1358 dev->name, dirty_tx, lp->cur_tx,
1359 lp->tx_full);
1360 dirty_tx += lp->tx_ring_size;
1361 delta -= lp->tx_ring_size;
1362 }
1363
1364 if (lp->tx_full &&
1365 netif_queue_stopped(dev) &&
1366 delta < lp->tx_ring_size - 2) {
1367 /* The ring is no longer full, clear tbusy. */
1368 lp->tx_full = 0;
1369 netif_wake_queue(dev);
1370 }
1371 lp->dirty_tx = dirty_tx;
1372
1373 return must_restart;
1374}
1375
bea3348e 1376static int pcnet32_poll(struct napi_struct *napi, int budget)
7de745e5 1377{
bea3348e
SH		 1378 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1379 struct net_device *dev = lp->dev;
7de745e5
DF		 1380 unsigned long ioaddr = dev->base_addr;
1381 unsigned long flags;
bea3348e 1382 int work_done;
7de745e5
DF		 1383 u16 val;
1384
bea3348e 1385 work_done = pcnet32_rx(dev, budget);
7de745e5
DF		 1386
1387 spin_lock_irqsave(&lp->lock, flags);
1388 if (pcnet32_tx(dev)) {
1389 /* reset the chip to clear the error condition, then restart */
1390 lp->a.reset(ioaddr);
1391 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1392 pcnet32_restart(dev, CSR0_START);
1393 netif_wake_queue(dev);
1394 }
1395 spin_unlock_irqrestore(&lp->lock, flags);
1396
bea3348e
SH		 1397 if (work_done < budget) {
1398 spin_lock_irqsave(&lp->lock, flags);
7de745e5 1399
908a7a16 1400 __netif_rx_complete(napi);
7de745e5 1401
bea3348e
SH		 1402 /* clear interrupt masks */
1403 val = lp->a.read_csr(ioaddr, CSR3);
1404 val &= 0x00ff;
1405 lp->a.write_csr(ioaddr, CSR3, val);
7de745e5 1406
bea3348e
SH		 1407 /* Set interrupt enable. */
1408 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
1409 mmiowb();
1410 spin_unlock_irqrestore(&lp->lock, flags);
1411 }
1412 return work_done;
7de745e5 1413}
7de745e5 1414
ac62ef04
DF		 1415#define PCNET32_REGS_PER_PHY 32
1416#define PCNET32_MAX_PHYS 32
1da177e4
LT		 1417static int pcnet32_get_regs_len(struct net_device *dev)
1418{
1e56a4b4 1419 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 1420 int j = lp->phycount * PCNET32_REGS_PER_PHY;
ac62ef04 1421
4a5e8e29 1422 return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1da177e4
LT		 1423}
1424
1425static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 1426 void *ptr)
1da177e4 1427{
4a5e8e29
JG		 1428 int i, csr0;
1429 u16 *buff = ptr;
1e56a4b4 1430 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1431 struct pcnet32_access *a = &lp->a;
1432 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 1433 unsigned long flags;
1434
1435 spin_lock_irqsave(&lp->lock, flags);
1436
df27f4a6
DF		 1437 csr0 = a->read_csr(ioaddr, CSR0);
1438 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1439 pcnet32_suspend(dev, &flags, 1);
1da177e4 1440
4a5e8e29
JG		 1441 /* read address PROM */
1442 for (i = 0; i < 16; i += 2)
1443 *buff++ = inw(ioaddr + i);
1444
1445 /* read control and status registers */
1446 for (i = 0; i < 90; i++) {
1447 *buff++ = a->read_csr(ioaddr, i);
1448 }
1449
1450 *buff++ = a->read_csr(ioaddr, 112);
1451 *buff++ = a->read_csr(ioaddr, 114);
1da177e4 1452
4a5e8e29
JG		 1453 /* read bus configuration registers */
1454 for (i = 0; i < 30; i++) {
1455 *buff++ = a->read_bcr(ioaddr, i);
1456 }
1457 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1458 for (i = 31; i < 36; i++) {
1459 *buff++ = a->read_bcr(ioaddr, i);
1460 }
1461
1462 /* read mii phy registers */
1463 if (lp->mii) {
1464 int j;
1465 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1466 if (lp->phymask & (1 << j)) {
1467 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1468 lp->a.write_bcr(ioaddr, 33,
1469 (j << 5) | i);
1470 *buff++ = lp->a.read_bcr(ioaddr, 34);
1471 }
1472 }
1473 }
1474 }
1475
df27f4a6
DF		 1476 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1477 int csr5;
1478
4a5e8e29 1479 /* clear SUSPEND (SPND) - CSR5 bit 0 */
df27f4a6
DF		 1480 csr5 = a->read_csr(ioaddr, CSR5);
1481 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
4a5e8e29
JG		 1482 }
1483
1484 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 1485}
1486
7282d491 1487static const struct ethtool_ops pcnet32_ethtool_ops = {
4a5e8e29
JG		 1488 .get_settings = pcnet32_get_settings,
1489 .set_settings = pcnet32_set_settings,
1490 .get_drvinfo = pcnet32_get_drvinfo,
1491 .get_msglevel = pcnet32_get_msglevel,
1492 .set_msglevel = pcnet32_set_msglevel,
1493 .nway_reset = pcnet32_nway_reset,
1494 .get_link = pcnet32_get_link,
1495 .get_ringparam = pcnet32_get_ringparam,
1496 .set_ringparam = pcnet32_set_ringparam,
4a5e8e29 1497 .get_strings = pcnet32_get_strings,
4a5e8e29
JG		 1498 .self_test = pcnet32_ethtool_test,
1499 .phys_id = pcnet32_phys_id,
1500 .get_regs_len = pcnet32_get_regs_len,
1501 .get_regs = pcnet32_get_regs,
b9f2c044 1502 .get_sset_count = pcnet32_get_sset_count,
1da177e4
LT		 1503};
1504
1505/* only probes for non-PCI devices, the rest are handled by
1506 * pci_register_driver via pcnet32_probe_pci */
1507
dcaf9769 1508static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1da177e4 1509{
4a5e8e29
JG		 1510 unsigned int *port, ioaddr;
1511
1512 /* search for PCnet32 VLB cards at known addresses */
1513 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1514 if (request_region
1515 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1516 /* check if there is really a pcnet chip on that ioaddr */
1517 if ((inb(ioaddr + 14) == 0x57)
1518 && (inb(ioaddr + 15) == 0x57)) {
1519 pcnet32_probe1(ioaddr, 0, NULL);
1520 } else {
1521 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1522 }
1523 }
1524 }
1da177e4
LT		 1525}
1526
1da177e4
LT		 1527static int __devinit
1528pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1529{
4a5e8e29
JG		 1530 unsigned long ioaddr;
1531 int err;
1532
1533 err = pci_enable_device(pdev);
1534 if (err < 0) {
1535 if (pcnet32_debug & NETIF_MSG_PROBE)
1536 printk(KERN_ERR PFX
1537 "failed to enable device -- err=%d\n", err);
1538 return err;
1539 }
1540 pci_set_master(pdev);
1541
1542 ioaddr = pci_resource_start(pdev, 0);
1543 if (!ioaddr) {
1544 if (pcnet32_debug & NETIF_MSG_PROBE)
1545 printk(KERN_ERR PFX
1546 "card has no PCI IO resources, aborting\n");
1547 return -ENODEV;
1548 }
1da177e4 1549
4a5e8e29
JG		 1550 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1551 if (pcnet32_debug & NETIF_MSG_PROBE)
1552 printk(KERN_ERR PFX
1553 "architecture does not support 32bit PCI busmaster DMA\n");
1554 return -ENODEV;
1555 }
1556 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1557 NULL) {
1558 if (pcnet32_debug & NETIF_MSG_PROBE)
1559 printk(KERN_ERR PFX
1560 "io address range already allocated\n");
1561 return -EBUSY;
1562 }
1da177e4 1563
4a5e8e29
JG		 1564 err = pcnet32_probe1(ioaddr, 1, pdev);
1565 if (err < 0) {
1566 pci_disable_device(pdev);
1567 }
1568 return err;
1da177e4
LT		 1569}
1570
1da177e4
LT		 1571/* pcnet32_probe1
1572 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1573 * pdev will be NULL when called from pcnet32_probe_vlbus.
1574 */
1575static int __devinit
1576pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1577{
4a5e8e29 1578 struct pcnet32_private *lp;
4a5e8e29
JG		 1579 int i, media;
1580 int fdx, mii, fset, dxsuflo;
1581 int chip_version;
1582 char *chipname;
1583 struct net_device *dev;
1584 struct pcnet32_access *a = NULL;
1585 u8 promaddr[6];
1586 int ret = -ENODEV;
1587
1588 /* reset the chip */
1589 pcnet32_wio_reset(ioaddr);
1590
1591 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1592 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1593 a = &pcnet32_wio;
1594 } else {
1595 pcnet32_dwio_reset(ioaddr);
1596 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1597 && pcnet32_dwio_check(ioaddr)) {
1598 a = &pcnet32_dwio;
1599 } else
1600 goto err_release_region;
1601 }
1602
1603 chip_version =
1604 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1605 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1606 printk(KERN_INFO " PCnet chip version is %#x.\n",
1607 chip_version);
1608 if ((chip_version & 0xfff) != 0x003) {
1609 if (pcnet32_debug & NETIF_MSG_PROBE)
1610 printk(KERN_INFO PFX "Unsupported chip version.\n");
1611 goto err_release_region;
1612 }
1613
1614 /* initialize variables */
1615 fdx = mii = fset = dxsuflo = 0;
1616 chip_version = (chip_version >> 12) & 0xffff;
1617
1618 switch (chip_version) {
1619 case 0x2420:
1620 chipname = "PCnet/PCI 79C970"; /* PCI */
1621 break;
1622 case 0x2430:
1623 if (shared)
1624 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1625 else
1626 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1627 break;
1628 case 0x2621:
1629 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1630 fdx = 1;
1631 break;
1632 case 0x2623:
1633 chipname = "PCnet/FAST 79C971"; /* PCI */
1634 fdx = 1;
1635 mii = 1;
1636 fset = 1;
1637 break;
1638 case 0x2624:
1639 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1640 fdx = 1;
1641 mii = 1;
1642 fset = 1;
1643 break;
1644 case 0x2625:
1645 chipname = "PCnet/FAST III 79C973"; /* PCI */
1646 fdx = 1;
1647 mii = 1;
1648 break;
1649 case 0x2626:
1650 chipname = "PCnet/Home 79C978"; /* PCI */
1651 fdx = 1;
1652 /*
1653 * This is based on specs published at www.amd.com. This section
1654 * assumes that a card with a 79C978 wants to go into standard
1655 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1656 * and the module option homepna=1 can select this instead.
1657 */
1658 media = a->read_bcr(ioaddr, 49);
1659 media &= ~3; /* default to 10Mb ethernet */
1660 if (cards_found < MAX_UNITS && homepna[cards_found])
1661 media |= 1; /* switch to home wiring mode */
1662 if (pcnet32_debug & NETIF_MSG_PROBE)
1663 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1664 (media & 1) ? "1" : "10");
1665 a->write_bcr(ioaddr, 49, media);
1666 break;
1667 case 0x2627:
1668 chipname = "PCnet/FAST III 79C975"; /* PCI */
1669 fdx = 1;
1670 mii = 1;
1671 break;
1672 case 0x2628:
1673 chipname = "PCnet/PRO 79C976";
1674 fdx = 1;
1675 mii = 1;
1676 break;
1677 default:
1678 if (pcnet32_debug & NETIF_MSG_PROBE)
1679 printk(KERN_INFO PFX
1680 "PCnet version %#x, no PCnet32 chip.\n",
1681 chip_version);
1682 goto err_release_region;
1683 }
1684
1da177e4 1685 /*
4a5e8e29
JG		 1686 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1687 * starting until the packet is loaded. Strike one for reliability, lose
1688 * one for latency - although on PCI this isnt a big loss. Older chips
1689 * have FIFO's smaller than a packet, so you can't do this.
1690 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1da177e4 1691 */
4a5e8e29
JG		 1692
1693 if (fset) {
1694 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1695 a->write_csr(ioaddr, 80,
1696 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1697 dxsuflo = 1;
1698 }
1699
6ecb7667 1700 dev = alloc_etherdev(sizeof(*lp));
4a5e8e29
JG		 1701 if (!dev) {
1702 if (pcnet32_debug & NETIF_MSG_PROBE)
1703 printk(KERN_ERR PFX "Memory allocation failed.\n");
1704 ret = -ENOMEM;
1705 goto err_release_region;
1706 }
1707 SET_NETDEV_DEV(dev, &pdev->dev);
1708
1da177e4 1709 if (pcnet32_debug & NETIF_MSG_PROBE)
4a5e8e29
JG		 1710 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1711
1712 /* In most chips, after a chip reset, the ethernet address is read from the
1713 * station address PROM at the base address and programmed into the
1714 * "Physical Address Registers" CSR12-14.
1715 * As a precautionary measure, we read the PROM values and complain if
bc0e1fc9
LV		 1716 * they disagree with the CSRs. If they miscompare, and the PROM addr
1717 * is valid, then the PROM addr is used.
4a5e8e29
JG		 1718 */
1719 for (i = 0; i < 3; i++) {
1720 unsigned int val;
1721 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1722 /* There may be endianness issues here. */
1723 dev->dev_addr[2 * i] = val & 0x0ff;
1724 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1725 }
1726
1727 /* read PROM address and compare with CSR address */
1da177e4 1728 for (i = 0; i < 6; i++)
4a5e8e29
JG		 1729 promaddr[i] = inb(ioaddr + i);
1730
1731 if (memcmp(promaddr, dev->dev_addr, 6)
1732 || !is_valid_ether_addr(dev->dev_addr)) {
1733 if (is_valid_ether_addr(promaddr)) {
1734 if (pcnet32_debug & NETIF_MSG_PROBE) {
1735 printk(" warning: CSR address invalid,\n");
1736 printk(KERN_INFO
1737 " using instead PROM address of");
1738 }
1739 memcpy(dev->dev_addr, promaddr, 6);
1740 }
1741 }
1742 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1743
1744 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1745 if (!is_valid_ether_addr(dev->perm_addr))
1746 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1747
1748 if (pcnet32_debug & NETIF_MSG_PROBE) {
e174961c 1749 printk(" %pM", dev->dev_addr);
4a5e8e29
JG		 1750
1751 /* Version 0x2623 and 0x2624 */
1752 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1753 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1754 printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
1755 switch (i >> 10) {
1756 case 0:
1757 printk(" 20 bytes,");
1758 break;
1759 case 1:
1760 printk(" 64 bytes,");
1761 break;
1762 case 2:
1763 printk(" 128 bytes,");
1764 break;
1765 case 3:
1766 printk("~220 bytes,");
1767 break;
1768 }
1769 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1770 printk(" BCR18(%x):", i & 0xffff);
1771 if (i & (1 << 5))
1772 printk("BurstWrEn ");
1773 if (i & (1 << 6))
1774 printk("BurstRdEn ");
1775 if (i & (1 << 7))
1776 printk("DWordIO ");
1777 if (i & (1 << 11))
1778 printk("NoUFlow ");
1779 i = a->read_bcr(ioaddr, 25);
1780 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
1781 i = a->read_bcr(ioaddr, 26);
1782 printk(" SRAM_BND=0x%04x,", i << 8);
1783 i = a->read_bcr(ioaddr, 27);
1784 if (i & (1 << 14))
1785 printk("LowLatRx");
1786 }
1787 }
1788
1789 dev->base_addr = ioaddr;
1e56a4b4 1790 lp = netdev_priv(dev);
4a5e8e29 1791 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
6ecb7667
DF		 1792 if ((lp->init_block =
1793 pci_alloc_consistent(pdev, sizeof(*lp->init_block), &lp->init_dma_addr)) == NULL) {
4a5e8e29
JG		 1794 if (pcnet32_debug & NETIF_MSG_PROBE)
1795 printk(KERN_ERR PFX
1796 "Consistent memory allocation failed.\n");
1797 ret = -ENOMEM;
1798 goto err_free_netdev;
1799 }
4a5e8e29
JG		 1800 lp->pci_dev = pdev;
1801
bea3348e
SH		 1802 lp->dev = dev;
1803
4a5e8e29
JG		 1804 spin_lock_init(&lp->lock);
1805
4a5e8e29 1806 SET_NETDEV_DEV(dev, &pdev->dev);
4a5e8e29
JG		 1807 lp->name = chipname;
1808 lp->shared_irq = shared;
1809 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1810 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1811 lp->tx_mod_mask = lp->tx_ring_size - 1;
1812 lp->rx_mod_mask = lp->rx_ring_size - 1;
1813 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1814 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1815 lp->mii_if.full_duplex = fdx;
1816 lp->mii_if.phy_id_mask = 0x1f;
1817 lp->mii_if.reg_num_mask = 0x1f;
1818 lp->dxsuflo = dxsuflo;
1819 lp->mii = mii;
8d916266 1820 lp->chip_version = chip_version;
4a5e8e29
JG		 1821 lp->msg_enable = pcnet32_debug;
1822 if ((cards_found >= MAX_UNITS)
1823 || (options[cards_found] > sizeof(options_mapping)))
1824 lp->options = PCNET32_PORT_ASEL;
1825 else
1826 lp->options = options_mapping[options[cards_found]];
1827 lp->mii_if.dev = dev;
1828 lp->mii_if.mdio_read = mdio_read;
1829 lp->mii_if.mdio_write = mdio_write;
1830
feff348f
DF		 1831 /* napi.weight is used in both the napi and non-napi cases */
1832 lp->napi.weight = lp->rx_ring_size / 2;
1833
bea3348e 1834 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
bea3348e 1835
4a5e8e29
JG		 1836 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1837 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1838 lp->options |= PCNET32_PORT_FD;
1839
1840 if (!a) {
1841 if (pcnet32_debug & NETIF_MSG_PROBE)
1842 printk(KERN_ERR PFX "No access methods\n");
1843 ret = -ENODEV;
1844 goto err_free_consistent;
1845 }
1846 lp->a = *a;
1847
1848 /* prior to register_netdev, dev->name is not yet correct */
1849 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1850 ret = -ENOMEM;
1851 goto err_free_ring;
1852 }
1853 /* detect special T1/E1 WAN card by checking for MAC address */
1854 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1da177e4 1855 && dev->dev_addr[2] == 0x75)
4a5e8e29 1856 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1da177e4 1857
3e33545b 1858 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */
6ecb7667 1859 lp->init_block->tlen_rlen =
3e33545b 1860 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
4a5e8e29 1861 for (i = 0; i < 6; i++)
6ecb7667
DF		 1862 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1863 lp->init_block->filter[0] = 0x00000000;
1864 lp->init_block->filter[1] = 0x00000000;
3e33545b
AV		 1865 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1866 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
4a5e8e29
JG		 1867
1868 /* switch pcnet32 to 32bit mode */
1869 a->write_bcr(ioaddr, 20, 2);
1870
6ecb7667
DF		 1871 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1872 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29
JG		 1873
1874 if (pdev) { /* use the IRQ provided by PCI */
1875 dev->irq = pdev->irq;
1876 if (pcnet32_debug & NETIF_MSG_PROBE)
1877 printk(" assigned IRQ %d.\n", dev->irq);
1878 } else {
1879 unsigned long irq_mask = probe_irq_on();
1880
1881 /*
1882 * To auto-IRQ we enable the initialization-done and DMA error
1883 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1884 * boards will work.
1885 */
1886 /* Trigger an initialization just for the interrupt. */
b368a3fb 1887 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
4a5e8e29
JG		 1888 mdelay(1);
1889
1890 dev->irq = probe_irq_off(irq_mask);
1891 if (!dev->irq) {
1892 if (pcnet32_debug & NETIF_MSG_PROBE)
1893 printk(", failed to detect IRQ line.\n");
1894 ret = -ENODEV;
1895 goto err_free_ring;
1896 }
1897 if (pcnet32_debug & NETIF_MSG_PROBE)
1898 printk(", probed IRQ %d.\n", dev->irq);
1899 }
1da177e4 1900
4a5e8e29
JG		 1901 /* Set the mii phy_id so that we can query the link state */
1902 if (lp->mii) {
1903 /* lp->phycount and lp->phymask are set to 0 by memset above */
1904
1905 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1906 /* scan for PHYs */
1907 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1908 unsigned short id1, id2;
1909
1910 id1 = mdio_read(dev, i, MII_PHYSID1);
1911 if (id1 == 0xffff)
1912 continue;
1913 id2 = mdio_read(dev, i, MII_PHYSID2);
1914 if (id2 == 0xffff)
1915 continue;
1916 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1917 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1918 lp->phycount++;
1919 lp->phymask |= (1 << i);
1920 lp->mii_if.phy_id = i;
1921 if (pcnet32_debug & NETIF_MSG_PROBE)
1922 printk(KERN_INFO PFX
1923 "Found PHY %04x:%04x at address %d.\n",
1924 id1, id2, i);
1925 }
1926 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1927 if (lp->phycount > 1) {
1928 lp->options |= PCNET32_PORT_MII;
1929 }
1da177e4 1930 }
4a5e8e29
JG		 1931
1932 init_timer(&lp->watchdog_timer);
1933 lp->watchdog_timer.data = (unsigned long)dev;
1934 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1935
1936 /* The PCNET32-specific entries in the device structure. */
1937 dev->open = &pcnet32_open;
1938 dev->hard_start_xmit = &pcnet32_start_xmit;
1939 dev->stop = &pcnet32_close;
1940 dev->get_stats = &pcnet32_get_stats;
1941 dev->set_multicast_list = &pcnet32_set_multicast_list;
1942 dev->do_ioctl = &pcnet32_ioctl;
1943 dev->ethtool_ops = &pcnet32_ethtool_ops;
1944 dev->tx_timeout = pcnet32_tx_timeout;
1945 dev->watchdog_timeo = (5 * HZ);
1da177e4
LT		 1946
1947#ifdef CONFIG_NET_POLL_CONTROLLER
4a5e8e29 1948 dev->poll_controller = pcnet32_poll_controller;
1da177e4
LT		 1949#endif
1950
4a5e8e29
JG		 1951 /* Fill in the generic fields of the device structure. */
1952 if (register_netdev(dev))
1953 goto err_free_ring;
1954
1955 if (pdev) {
1956 pci_set_drvdata(pdev, dev);
1957 } else {
1958 lp->next = pcnet32_dev;
1959 pcnet32_dev = dev;
1960 }
1961
1962 if (pcnet32_debug & NETIF_MSG_PROBE)
1963 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1964 cards_found++;
1965
1966 /* enable LED writes */
1967 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1da177e4 1968
4a5e8e29
JG		 1969 return 0;
1970
1971 err_free_ring:
1972 pcnet32_free_ring(dev);
1973 err_free_consistent:
7d2e3cb7 1974 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 1975 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 1976 err_free_netdev:
1977 free_netdev(dev);
1978 err_release_region:
1979 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1980 return ret;
1981}
1da177e4 1982
a88c844c 1983/* if any allocation fails, caller must also call pcnet32_free_ring */
b166cfba 1984static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
eabf0415 1985{
1e56a4b4 1986 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 1987
4a5e8e29
JG		 1988 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1989 sizeof(struct pcnet32_tx_head) *
1990 lp->tx_ring_size,
1991 &lp->tx_ring_dma_addr);
1992 if (lp->tx_ring == NULL) {
12fa30f3 1993 if (netif_msg_drv(lp))
4a5e8e29
JG		 1994 printk("\n" KERN_ERR PFX
1995 "%s: Consistent memory allocation failed.\n",
1996 name);
1997 return -ENOMEM;
1998 }
eabf0415 1999
4a5e8e29
JG		 2000 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
2001 sizeof(struct pcnet32_rx_head) *
2002 lp->rx_ring_size,
2003 &lp->rx_ring_dma_addr);
2004 if (lp->rx_ring == NULL) {
12fa30f3 2005 if (netif_msg_drv(lp))
4a5e8e29
JG		 2006 printk("\n" KERN_ERR PFX
2007 "%s: Consistent memory allocation failed.\n",
2008 name);
2009 return -ENOMEM;
2010 }
eabf0415 2011
12fa30f3 2012 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 2013 GFP_ATOMIC);
2014 if (!lp->tx_dma_addr) {
12fa30f3 2015 if (netif_msg_drv(lp))
4a5e8e29
JG		 2016 printk("\n" KERN_ERR PFX
2017 "%s: Memory allocation failed.\n", name);
2018 return -ENOMEM;
2019 }
4a5e8e29 2020
12fa30f3 2021 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 2022 GFP_ATOMIC);
2023 if (!lp->rx_dma_addr) {
12fa30f3 2024 if (netif_msg_drv(lp))
4a5e8e29
JG		 2025 printk("\n" KERN_ERR PFX
2026 "%s: Memory allocation failed.\n", name);
2027 return -ENOMEM;
2028 }
4a5e8e29 2029
12fa30f3 2030 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 2031 GFP_ATOMIC);
2032 if (!lp->tx_skbuff) {
12fa30f3 2033 if (netif_msg_drv(lp))
4a5e8e29
JG		 2034 printk("\n" KERN_ERR PFX
2035 "%s: Memory allocation failed.\n", name);
2036 return -ENOMEM;
2037 }
4a5e8e29 2038
12fa30f3 2039 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 2040 GFP_ATOMIC);
2041 if (!lp->rx_skbuff) {
12fa30f3 2042 if (netif_msg_drv(lp))
4a5e8e29
JG		 2043 printk("\n" KERN_ERR PFX
2044 "%s: Memory allocation failed.\n", name);
2045 return -ENOMEM;
2046 }
4a5e8e29
JG		 2047
2048 return 0;
2049}
eabf0415
HWL		 2050
2051static void pcnet32_free_ring(struct net_device *dev)
2052{
1e56a4b4 2053 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 2054
4a5e8e29
JG		 2055 kfree(lp->tx_skbuff);
2056 lp->tx_skbuff = NULL;
eabf0415 2057
4a5e8e29
JG		 2058 kfree(lp->rx_skbuff);
2059 lp->rx_skbuff = NULL;
eabf0415 2060
4a5e8e29
JG		 2061 kfree(lp->tx_dma_addr);
2062 lp->tx_dma_addr = NULL;
eabf0415 2063
4a5e8e29
JG		 2064 kfree(lp->rx_dma_addr);
2065 lp->rx_dma_addr = NULL;
eabf0415 2066
4a5e8e29
JG		 2067 if (lp->tx_ring) {
2068 pci_free_consistent(lp->pci_dev,
2069 sizeof(struct pcnet32_tx_head) *
2070 lp->tx_ring_size, lp->tx_ring,
2071 lp->tx_ring_dma_addr);
2072 lp->tx_ring = NULL;
2073 }
eabf0415 2074
4a5e8e29
JG		 2075 if (lp->rx_ring) {
2076 pci_free_consistent(lp->pci_dev,
2077 sizeof(struct pcnet32_rx_head) *
2078 lp->rx_ring_size, lp->rx_ring,
2079 lp->rx_ring_dma_addr);
2080 lp->rx_ring = NULL;
2081 }
eabf0415
HWL		 2082}
2083
4a5e8e29 2084static int pcnet32_open(struct net_device *dev)
1da177e4 2085{
1e56a4b4 2086 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2087 unsigned long ioaddr = dev->base_addr;
2088 u16 val;
2089 int i;
2090 int rc;
2091 unsigned long flags;
2092
2093 if (request_irq(dev->irq, &pcnet32_interrupt,
1fb9df5d 2094 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
4a5e8e29
JG		 2095 (void *)dev)) {
2096 return -EAGAIN;
2097 }
2098
2099 spin_lock_irqsave(&lp->lock, flags);
2100 /* Check for a valid station address */
2101 if (!is_valid_ether_addr(dev->dev_addr)) {
2102 rc = -EINVAL;
2103 goto err_free_irq;
2104 }
2105
2106 /* Reset the PCNET32 */
2107 lp->a.reset(ioaddr);
2108
2109 /* switch pcnet32 to 32bit mode */
2110 lp->a.write_bcr(ioaddr, 20, 2);
2111
2112 if (netif_msg_ifup(lp))
2113 printk(KERN_DEBUG
2114 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2115 dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
2116 (u32) (lp->rx_ring_dma_addr),
6ecb7667 2117 (u32) (lp->init_dma_addr));
4a5e8e29
JG		 2118
2119 /* set/reset autoselect bit */
2120 val = lp->a.read_bcr(ioaddr, 2) & ~2;
2121 if (lp->options & PCNET32_PORT_ASEL)
1da177e4 2122 val |= 2;
4a5e8e29
JG		 2123 lp->a.write_bcr(ioaddr, 2, val);
2124
2125 /* handle full duplex setting */
2126 if (lp->mii_if.full_duplex) {
2127 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2128 if (lp->options & PCNET32_PORT_FD) {
2129 val |= 1;
2130 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2131 val |= 2;
2132 } else if (lp->options & PCNET32_PORT_ASEL) {
2133 /* workaround of xSeries250, turn on for 79C975 only */
8d916266 2134 if (lp->chip_version == 0x2627)
4a5e8e29
JG		 2135 val |= 3;
2136 }
2137 lp->a.write_bcr(ioaddr, 9, val);
2138 }
2139
2140 /* set/reset GPSI bit in test register */
2141 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2142 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2143 val |= 0x10;
2144 lp->a.write_csr(ioaddr, 124, val);
2145
2146 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2147 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2964bbd7
DF		 2148 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2149 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
ac62ef04 2150 if (lp->options & PCNET32_PORT_ASEL) {
4a5e8e29
JG		 2151 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2152 if (netif_msg_link(lp))
2153 printk(KERN_DEBUG
2154 "%s: Setting 100Mb-Full Duplex.\n",
2155 dev->name);
2156 }
2157 }
2158 if (lp->phycount < 2) {
2159 /*
2160 * 24 Jun 2004 according AMD, in order to change the PHY,
2161 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2162 * duplex, and/or enable auto negotiation, and clear DANAS
2163 */
2164 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2165 lp->a.write_bcr(ioaddr, 32,
2166 lp->a.read_bcr(ioaddr, 32) | 0x0080);
2167 /* disable Auto Negotiation, set 10Mpbs, HD */
2168 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2169 if (lp->options & PCNET32_PORT_FD)
2170 val |= 0x10;
2171 if (lp->options & PCNET32_PORT_100)
2172 val |= 0x08;
2173 lp->a.write_bcr(ioaddr, 32, val);
2174 } else {
2175 if (lp->options & PCNET32_PORT_ASEL) {
2176 lp->a.write_bcr(ioaddr, 32,
2177 lp->a.read_bcr(ioaddr,
2178 32) | 0x0080);
2179 /* enable auto negotiate, setup, disable fd */
2180 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2181 val |= 0x20;
2182 lp->a.write_bcr(ioaddr, 32, val);
2183 }
2184 }
2185 } else {
2186 int first_phy = -1;
2187 u16 bmcr;
2188 u32 bcr9;
2189 struct ethtool_cmd ecmd;
2190
2191 /*
2192 * There is really no good other way to handle multiple PHYs
2193 * other than turning off all automatics
2194 */
2195 val = lp->a.read_bcr(ioaddr, 2);
2196 lp->a.write_bcr(ioaddr, 2, val & ~2);
2197 val = lp->a.read_bcr(ioaddr, 32);
2198 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2199
2200 if (!(lp->options & PCNET32_PORT_ASEL)) {
2201 /* setup ecmd */
2202 ecmd.port = PORT_MII;
2203 ecmd.transceiver = XCVR_INTERNAL;
2204 ecmd.autoneg = AUTONEG_DISABLE;
2205 ecmd.speed =
2206 lp->
2207 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2208 bcr9 = lp->a.read_bcr(ioaddr, 9);
2209
2210 if (lp->options & PCNET32_PORT_FD) {
2211 ecmd.duplex = DUPLEX_FULL;
2212 bcr9 |= (1 << 0);
2213 } else {
2214 ecmd.duplex = DUPLEX_HALF;
2215 bcr9 |= ~(1 << 0);
2216 }
2217 lp->a.write_bcr(ioaddr, 9, bcr9);
ac62ef04 2218 }
4a5e8e29
JG		 2219
2220 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2221 if (lp->phymask & (1 << i)) {
2222 /* isolate all but the first PHY */
2223 bmcr = mdio_read(dev, i, MII_BMCR);
2224 if (first_phy == -1) {
2225 first_phy = i;
2226 mdio_write(dev, i, MII_BMCR,
2227 bmcr & ~BMCR_ISOLATE);
2228 } else {
2229 mdio_write(dev, i, MII_BMCR,
2230 bmcr | BMCR_ISOLATE);
2231 }
2232 /* use mii_ethtool_sset to setup PHY */
2233 lp->mii_if.phy_id = i;
2234 ecmd.phy_address = i;
2235 if (lp->options & PCNET32_PORT_ASEL) {
2236 mii_ethtool_gset(&lp->mii_if, &ecmd);
2237 ecmd.autoneg = AUTONEG_ENABLE;
2238 }
2239 mii_ethtool_sset(&lp->mii_if, &ecmd);
2240 }
2241 }
2242 lp->mii_if.phy_id = first_phy;
2243 if (netif_msg_link(lp))
2244 printk(KERN_INFO "%s: Using PHY number %d.\n",
2245 dev->name, first_phy);
2246 }
1da177e4
LT		 2247
2248#ifdef DO_DXSUFLO
4a5e8e29 2249 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
b368a3fb 2250 val = lp->a.read_csr(ioaddr, CSR3);
4a5e8e29 2251 val |= 0x40;
b368a3fb 2252 lp->a.write_csr(ioaddr, CSR3, val);
4a5e8e29 2253 }
1da177e4
LT		 2254#endif
2255
6ecb7667 2256 lp->init_block->mode =
3e33545b 2257 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
4a5e8e29
JG		 2258 pcnet32_load_multicast(dev);
2259
2260 if (pcnet32_init_ring(dev)) {
2261 rc = -ENOMEM;
2262 goto err_free_ring;
2263 }
2264
bea3348e 2265 napi_enable(&lp->napi);
bea3348e 2266
4a5e8e29 2267 /* Re-initialize the PCNET32, and start it when done. */
6ecb7667
DF		 2268 lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2269 lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29 2270
b368a3fb
DF		 2271 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2272 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2273
2274 netif_start_queue(dev);
2275
8d916266
DF		 2276 if (lp->chip_version >= PCNET32_79C970A) {
2277 /* Print the link status and start the watchdog */
2278 pcnet32_check_media(dev, 1);
2279 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2280 }
4a5e8e29
JG		 2281
2282 i = 0;
2283 while (i++ < 100)
b368a3fb 2284 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29
JG		 2285 break;
2286 /*
2287 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2288 * reports that doing so triggers a bug in the '974.
2289 */
b368a3fb 2290 lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
4a5e8e29
JG		 2291
2292 if (netif_msg_ifup(lp))
2293 printk(KERN_DEBUG
2294 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2295 dev->name, i,
6ecb7667 2296 (u32) (lp->init_dma_addr),
b368a3fb 2297 lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2298
2299 spin_unlock_irqrestore(&lp->lock, flags);
2300
2301 return 0; /* Always succeed */
2302
2303 err_free_ring:
2304 /* free any allocated skbuffs */
ac5bfe40 2305 pcnet32_purge_rx_ring(dev);
4a5e8e29 2306
4a5e8e29
JG		 2307 /*
2308 * Switch back to 16bit mode to avoid problems with dumb
2309 * DOS packet driver after a warm reboot
2310 */
2311 lp->a.write_bcr(ioaddr, 20, 4);
2312
2313 err_free_irq:
2314 spin_unlock_irqrestore(&lp->lock, flags);
2315 free_irq(dev->irq, dev);
2316 return rc;
1da177e4
LT		 2317}
2318
2319/*
2320 * The LANCE has been halted for one reason or another (busmaster memory
2321 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2322 * etc.). Modern LANCE variants always reload their ring-buffer
2323 * configuration when restarted, so we must reinitialize our ring
2324 * context before restarting. As part of this reinitialization,
2325 * find all packets still on the Tx ring and pretend that they had been
2326 * sent (in effect, drop the packets on the floor) - the higher-level
2327 * protocols will time out and retransmit. It'd be better to shuffle
2328 * these skbs to a temp list and then actually re-Tx them after
2329 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2330 */
2331
4a5e8e29 2332static void pcnet32_purge_tx_ring(struct net_device *dev)
1da177e4 2333{
1e56a4b4 2334 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2335 int i;
1da177e4 2336
4a5e8e29
JG		 2337 for (i = 0; i < lp->tx_ring_size; i++) {
2338 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2339 wmb(); /* Make sure adapter sees owner change */
2340 if (lp->tx_skbuff[i]) {
2341 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2342 lp->tx_skbuff[i]->len,
2343 PCI_DMA_TODEVICE);
2344 dev_kfree_skb_any(lp->tx_skbuff[i]);
2345 }
2346 lp->tx_skbuff[i] = NULL;
2347 lp->tx_dma_addr[i] = 0;
2348 }
2349}
1da177e4
LT		 2350
2351/* Initialize the PCNET32 Rx and Tx rings. */
4a5e8e29 2352static int pcnet32_init_ring(struct net_device *dev)
1da177e4 2353{
1e56a4b4 2354 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2355 int i;
2356
2357 lp->tx_full = 0;
2358 lp->cur_rx = lp->cur_tx = 0;
2359 lp->dirty_rx = lp->dirty_tx = 0;
2360
2361 for (i = 0; i < lp->rx_ring_size; i++) {
2362 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2363 if (rx_skbuff == NULL) {
2364 if (!
2365 (rx_skbuff = lp->rx_skbuff[i] =
232c5640 2366 dev_alloc_skb(PKT_BUF_SKB))) {
4a5e8e29 2367 /* there is not much, we can do at this point */
b368a3fb 2368 if (netif_msg_drv(lp))
4a5e8e29
JG		 2369 printk(KERN_ERR
2370 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2371 dev->name);
2372 return -1;
2373 }
232c5640 2374 skb_reserve(rx_skbuff, NET_IP_ALIGN);
4a5e8e29
JG		 2375 }
2376
2377 rmb();
2378 if (lp->rx_dma_addr[i] == 0)
2379 lp->rx_dma_addr[i] =
2380 pci_map_single(lp->pci_dev, rx_skbuff->data,
232c5640 2381 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
3e33545b 2382 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
232c5640 2383 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
4a5e8e29 2384 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 2385 lp->rx_ring[i].status = cpu_to_le16(0x8000);
4a5e8e29
JG		 2386 }
2387 /* The Tx buffer address is filled in as needed, but we do need to clear
2388 * the upper ownership bit. */
2389 for (i = 0; i < lp->tx_ring_size; i++) {
2390 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2391 wmb(); /* Make sure adapter sees owner change */
2392 lp->tx_ring[i].base = 0;
2393 lp->tx_dma_addr[i] = 0;
2394 }
2395
6ecb7667 2396 lp->init_block->tlen_rlen =
3e33545b 2397 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
4a5e8e29 2398 for (i = 0; i < 6; i++)
6ecb7667 2399 lp->init_block->phys_addr[i] = dev->dev_addr[i];
3e33545b
AV		 2400 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2401 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
4a5e8e29
JG		 2402 wmb(); /* Make sure all changes are visible */
2403 return 0;
1da177e4
LT		 2404}
2405
2406/* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2407 * then flush the pending transmit operations, re-initialize the ring,
2408 * and tell the chip to initialize.
2409 */
4a5e8e29 2410static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1da177e4 2411{
1e56a4b4 2412 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2413 unsigned long ioaddr = dev->base_addr;
2414 int i;
1da177e4 2415
4a5e8e29
JG		 2416 /* wait for stop */
2417 for (i = 0; i < 100; i++)
b368a3fb 2418 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
4a5e8e29 2419 break;
1da177e4 2420
4a5e8e29
JG		 2421 if (i >= 100 && netif_msg_drv(lp))
2422 printk(KERN_ERR
2423 "%s: pcnet32_restart timed out waiting for stop.\n",
2424 dev->name);
1da177e4 2425
4a5e8e29
JG		 2426 pcnet32_purge_tx_ring(dev);
2427 if (pcnet32_init_ring(dev))
2428 return;
1da177e4 2429
4a5e8e29 2430 /* ReInit Ring */
b368a3fb 2431 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2432 i = 0;
2433 while (i++ < 1000)
b368a3fb 2434 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29 2435 break;
1da177e4 2436
b368a3fb 2437 lp->a.write_csr(ioaddr, CSR0, csr0_bits);
1da177e4
LT		 2438}
2439
4a5e8e29 2440static void pcnet32_tx_timeout(struct net_device *dev)
1da177e4 2441{
1e56a4b4 2442 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2443 unsigned long ioaddr = dev->base_addr, flags;
2444
2445 spin_lock_irqsave(&lp->lock, flags);
2446 /* Transmitter timeout, serious problems. */
2447 if (pcnet32_debug & NETIF_MSG_DRV)
2448 printk(KERN_ERR
2449 "%s: transmit timed out, status %4.4x, resetting.\n",
b368a3fb
DF		 2450 dev->name, lp->a.read_csr(ioaddr, CSR0));
2451 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
4f1e5ba0 2452 dev->stats.tx_errors++;
4a5e8e29
JG		 2453 if (netif_msg_tx_err(lp)) {
2454 int i;
2455 printk(KERN_DEBUG
2456 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2457 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2458 lp->cur_rx);
2459 for (i = 0; i < lp->rx_ring_size; i++)
2460 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2461 le32_to_cpu(lp->rx_ring[i].base),
2462 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2463 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2464 le16_to_cpu(lp->rx_ring[i].status));
2465 for (i = 0; i < lp->tx_ring_size; i++)
2466 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2467 le32_to_cpu(lp->tx_ring[i].base),
2468 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2469 le32_to_cpu(lp->tx_ring[i].misc),
2470 le16_to_cpu(lp->tx_ring[i].status));
2471 printk("\n");
2472 }
b368a3fb 2473 pcnet32_restart(dev, CSR0_NORMAL);
1da177e4 2474
4a5e8e29
JG		 2475 dev->trans_start = jiffies;
2476 netif_wake_queue(dev);
1da177e4 2477
4a5e8e29
JG		 2478 spin_unlock_irqrestore(&lp->lock, flags);
2479}
2480
2481static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 2482{
1e56a4b4 2483 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2484 unsigned long ioaddr = dev->base_addr;
2485 u16 status;
2486 int entry;
2487 unsigned long flags;
1da177e4 2488
4a5e8e29 2489 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2490
4a5e8e29
JG		 2491 if (netif_msg_tx_queued(lp)) {
2492 printk(KERN_DEBUG
2493 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
b368a3fb 2494 dev->name, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29 2495 }
1da177e4 2496
4a5e8e29
JG		 2497 /* Default status -- will not enable Successful-TxDone
2498 * interrupt when that option is available to us.
2499 */
2500 status = 0x8300;
1da177e4 2501
4a5e8e29 2502 /* Fill in a Tx ring entry */
1da177e4 2503
4a5e8e29
JG		 2504 /* Mask to ring buffer boundary. */
2505 entry = lp->cur_tx & lp->tx_mod_mask;
1da177e4 2506
4a5e8e29
JG		 2507 /* Caution: the write order is important here, set the status
2508 * with the "ownership" bits last. */
1da177e4 2509
3e33545b 2510 lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
1da177e4 2511
4a5e8e29 2512 lp->tx_ring[entry].misc = 0x00000000;
1da177e4 2513
4a5e8e29
JG		 2514 lp->tx_skbuff[entry] = skb;
2515 lp->tx_dma_addr[entry] =
2516 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
3e33545b 2517 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
4a5e8e29 2518 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 2519 lp->tx_ring[entry].status = cpu_to_le16(status);
1da177e4 2520
4a5e8e29 2521 lp->cur_tx++;
4f1e5ba0 2522 dev->stats.tx_bytes += skb->len;
1da177e4 2523
4a5e8e29 2524 /* Trigger an immediate send poll. */
b368a3fb 2525 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
1da177e4 2526
4a5e8e29 2527 dev->trans_start = jiffies;
1da177e4 2528
4a5e8e29
JG		 2529 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2530 lp->tx_full = 1;
2531 netif_stop_queue(dev);
2532 }
2533 spin_unlock_irqrestore(&lp->lock, flags);
2534 return 0;
1da177e4
LT		 2535}
2536
2537/* The PCNET32 interrupt handler. */
2538static irqreturn_t
7d12e780 2539pcnet32_interrupt(int irq, void *dev_id)
1da177e4 2540{
4a5e8e29
JG		 2541 struct net_device *dev = dev_id;
2542 struct pcnet32_private *lp;
2543 unsigned long ioaddr;
5c99346a 2544 u16 csr0;
4a5e8e29 2545 int boguscnt = max_interrupt_work;
4a5e8e29 2546
4a5e8e29 2547 ioaddr = dev->base_addr;
1e56a4b4 2548 lp = netdev_priv(dev);
1da177e4 2549
4a5e8e29
JG		 2550 spin_lock(&lp->lock);
2551
3904c324
DF		 2552 csr0 = lp->a.read_csr(ioaddr, CSR0);
2553 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
4a5e8e29
JG		 2554 if (csr0 == 0xffff) {
2555 break; /* PCMCIA remove happened */
2556 }
2557 /* Acknowledge all of the current interrupt sources ASAP. */
3904c324 2558 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
4a5e8e29 2559
4a5e8e29
JG		 2560 if (netif_msg_intr(lp))
2561 printk(KERN_DEBUG
2562 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
3904c324 2563 dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29 2564
4a5e8e29
JG		 2565 /* Log misc errors. */
2566 if (csr0 & 0x4000)
4f1e5ba0 2567 dev->stats.tx_errors++; /* Tx babble. */
4a5e8e29
JG		 2568 if (csr0 & 0x1000) {
2569 /*
3904c324
DF		 2570 * This happens when our receive ring is full. This
2571 * shouldn't be a problem as we will see normal rx
2572 * interrupts for the frames in the receive ring. But
2573 * there are some PCI chipsets (I can reproduce this
2574 * on SP3G with Intel saturn chipset) which have
2575 * sometimes problems and will fill up the receive
2576 * ring with error descriptors. In this situation we
2577 * don't get a rx interrupt, but a missed frame
7de745e5 2578 * interrupt sooner or later.
4a5e8e29 2579 */
4f1e5ba0 2580 dev->stats.rx_errors++; /* Missed a Rx frame. */
4a5e8e29
JG		 2581 }
2582 if (csr0 & 0x0800) {
2583 if (netif_msg_drv(lp))
2584 printk(KERN_ERR
2585 "%s: Bus master arbitration failure, status %4.4x.\n",
2586 dev->name, csr0);
2587 /* unlike for the lance, there is no restart needed */
1da177e4 2588 }
908a7a16 2589 if (netif_rx_schedule_prep(&lp->napi)) {
7de745e5
DF		 2590 u16 val;
2591 /* set interrupt masks */
2592 val = lp->a.read_csr(ioaddr, CSR3);
2593 val |= 0x5f00;
2594 lp->a.write_csr(ioaddr, CSR3, val);
2595 mmiowb();
908a7a16 2596 __netif_rx_schedule(&lp->napi);
7de745e5
DF		 2597 break;
2598 }
3904c324 2599 csr0 = lp->a.read_csr(ioaddr, CSR0);
4a5e8e29
JG		 2600 }
2601
4a5e8e29
JG		 2602 if (netif_msg_intr(lp))
2603 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
b368a3fb 2604 dev->name, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2605
2606 spin_unlock(&lp->lock);
2607
2608 return IRQ_HANDLED;
1da177e4
LT		 2609}
2610
4a5e8e29 2611static int pcnet32_close(struct net_device *dev)
1da177e4 2612{
4a5e8e29 2613 unsigned long ioaddr = dev->base_addr;
1e56a4b4 2614 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2615 unsigned long flags;
1da177e4 2616
4a5e8e29 2617 del_timer_sync(&lp->watchdog_timer);
1da177e4 2618
4a5e8e29 2619 netif_stop_queue(dev);
bea3348e 2620 napi_disable(&lp->napi);
1da177e4 2621
4a5e8e29 2622 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2623
4f1e5ba0 2624 dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
1da177e4 2625
4a5e8e29
JG		 2626 if (netif_msg_ifdown(lp))
2627 printk(KERN_DEBUG
2628 "%s: Shutting down ethercard, status was %2.2x.\n",
b368a3fb 2629 dev->name, lp->a.read_csr(ioaddr, CSR0));
1da177e4 2630
4a5e8e29 2631 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
b368a3fb 2632 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
1da177e4 2633
4a5e8e29
JG		 2634 /*
2635 * Switch back to 16bit mode to avoid problems with dumb
2636 * DOS packet driver after a warm reboot
2637 */
2638 lp->a.write_bcr(ioaddr, 20, 4);
1da177e4 2639
4a5e8e29 2640 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2641
4a5e8e29 2642 free_irq(dev->irq, dev);
1da177e4 2643
4a5e8e29 2644 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2645
ac5bfe40
DF		 2646 pcnet32_purge_rx_ring(dev);
2647 pcnet32_purge_tx_ring(dev);
1da177e4 2648
4a5e8e29 2649 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2650
4a5e8e29 2651 return 0;
1da177e4
LT		 2652}
2653
4a5e8e29 2654static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
1da177e4 2655{
1e56a4b4 2656 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2657 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2658 unsigned long flags;
2659
2660 spin_lock_irqsave(&lp->lock, flags);
4f1e5ba0 2661 dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
4a5e8e29
JG		 2662 spin_unlock_irqrestore(&lp->lock, flags);
2663
4f1e5ba0 2664 return &dev->stats;
1da177e4
LT		 2665}
2666
2667/* taken from the sunlance driver, which it took from the depca driver */
4a5e8e29 2668static void pcnet32_load_multicast(struct net_device *dev)
1da177e4 2669{
1e56a4b4 2670 struct pcnet32_private *lp = netdev_priv(dev);
6ecb7667 2671 volatile struct pcnet32_init_block *ib = lp->init_block;
3e33545b 2672 volatile __le16 *mcast_table = (__le16 *)ib->filter;
4a5e8e29 2673 struct dev_mc_list *dmi = dev->mc_list;
df27f4a6 2674 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2675 char *addrs;
2676 int i;
2677 u32 crc;
2678
2679 /* set all multicast bits */
2680 if (dev->flags & IFF_ALLMULTI) {
3e33545b
AV		 2681 ib->filter[0] = cpu_to_le32(~0U);
2682 ib->filter[1] = cpu_to_le32(~0U);
df27f4a6
DF		 2683 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2684 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2685 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2686 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
4a5e8e29
JG		 2687 return;
2688 }
2689 /* clear the multicast filter */
2690 ib->filter[0] = 0;
2691 ib->filter[1] = 0;
2692
2693 /* Add addresses */
2694 for (i = 0; i < dev->mc_count; i++) {
2695 addrs = dmi->dmi_addr;
2696 dmi = dmi->next;
2697
2698 /* multicast address? */
2699 if (!(*addrs & 1))
2700 continue;
2701
2702 crc = ether_crc_le(6, addrs);
2703 crc = crc >> 26;
3e33545b 2704 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
4a5e8e29 2705 }
df27f4a6
DF		 2706 for (i = 0; i < 4; i++)
2707 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2708 le16_to_cpu(mcast_table[i]));
1da177e4 2709 return;
1da177e4
LT		 2710}
2711
1da177e4
LT		 2712/*
2713 * Set or clear the multicast filter for this adaptor.
2714 */
2715static void pcnet32_set_multicast_list(struct net_device *dev)
2716{
4a5e8e29 2717 unsigned long ioaddr = dev->base_addr, flags;
1e56a4b4 2718 struct pcnet32_private *lp = netdev_priv(dev);
df27f4a6 2719 int csr15, suspended;
4a5e8e29
JG		 2720
2721 spin_lock_irqsave(&lp->lock, flags);
df27f4a6
DF		 2722 suspended = pcnet32_suspend(dev, &flags, 0);
2723 csr15 = lp->a.read_csr(ioaddr, CSR15);
4a5e8e29
JG		 2724 if (dev->flags & IFF_PROMISC) {
2725 /* Log any net taps. */
2726 if (netif_msg_hw(lp))
2727 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2728 dev->name);
6ecb7667 2729 lp->init_block->mode =
3e33545b 2730 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
4a5e8e29 2731 7);
df27f4a6 2732 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
4a5e8e29 2733 } else {
6ecb7667 2734 lp->init_block->mode =
3e33545b 2735 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
df27f4a6 2736 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
4a5e8e29
JG		 2737 pcnet32_load_multicast(dev);
2738 }
2739
df27f4a6
DF		 2740 if (suspended) {
2741 int csr5;
2742 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2743 csr5 = lp->a.read_csr(ioaddr, CSR5);
2744 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
b368a3fb 2745 } else {
df27f4a6
DF		 2746 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2747 pcnet32_restart(dev, CSR0_NORMAL);
2748 netif_wake_queue(dev);
2749 }
4a5e8e29
JG		 2750
2751 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 2752}
2753
2754/* This routine assumes that the lp->lock is held */
2755static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2756{
1e56a4b4 2757 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2758 unsigned long ioaddr = dev->base_addr;
2759 u16 val_out;
1da177e4 2760
4a5e8e29
JG		 2761 if (!lp->mii)
2762 return 0;
1da177e4 2763
4a5e8e29
JG		 2764 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2765 val_out = lp->a.read_bcr(ioaddr, 34);
1da177e4 2766
4a5e8e29 2767 return val_out;
1da177e4
LT		 2768}
2769
2770/* This routine assumes that the lp->lock is held */
2771static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2772{
1e56a4b4 2773 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2774 unsigned long ioaddr = dev->base_addr;
1da177e4 2775
4a5e8e29
JG		 2776 if (!lp->mii)
2777 return;
1da177e4 2778
4a5e8e29
JG		 2779 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2780 lp->a.write_bcr(ioaddr, 34, val);
1da177e4
LT		 2781}
2782
2783static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2784{
1e56a4b4 2785 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2786 int rc;
2787 unsigned long flags;
1da177e4 2788
4a5e8e29
JG		 2789 /* SIOC[GS]MIIxxx ioctls */
2790 if (lp->mii) {
2791 spin_lock_irqsave(&lp->lock, flags);
2792 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2793 spin_unlock_irqrestore(&lp->lock, flags);
2794 } else {
2795 rc = -EOPNOTSUPP;
2796 }
1da177e4 2797
4a5e8e29 2798 return rc;
1da177e4
LT		 2799}
2800
ac62ef04
DF		 2801static int pcnet32_check_otherphy(struct net_device *dev)
2802{
1e56a4b4 2803 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2804 struct mii_if_info mii = lp->mii_if;
2805 u16 bmcr;
2806 int i;
ac62ef04 2807
4a5e8e29
JG		 2808 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2809 if (i == lp->mii_if.phy_id)
2810 continue; /* skip active phy */
2811 if (lp->phymask & (1 << i)) {
2812 mii.phy_id = i;
2813 if (mii_link_ok(&mii)) {
2814 /* found PHY with active link */
2815 if (netif_msg_link(lp))
2816 printk(KERN_INFO
2817 "%s: Using PHY number %d.\n",
2818 dev->name, i);
2819
2820 /* isolate inactive phy */
2821 bmcr =
2822 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2823 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2824 bmcr | BMCR_ISOLATE);
2825
2826 /* de-isolate new phy */
2827 bmcr = mdio_read(dev, i, MII_BMCR);
2828 mdio_write(dev, i, MII_BMCR,
2829 bmcr & ~BMCR_ISOLATE);
2830
2831 /* set new phy address */
2832 lp->mii_if.phy_id = i;
2833 return 1;
2834 }
2835 }
ac62ef04 2836 }
4a5e8e29 2837 return 0;
ac62ef04
DF		 2838}
2839
2840/*
2841 * Show the status of the media. Similar to mii_check_media however it
2842 * correctly shows the link speed for all (tested) pcnet32 variants.
2843 * Devices with no mii just report link state without speed.
2844 *
2845 * Caller is assumed to hold and release the lp->lock.
2846 */
2847
2848static void pcnet32_check_media(struct net_device *dev, int verbose)
2849{
1e56a4b4 2850 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2851 int curr_link;
2852 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2853 u32 bcr9;
2854
ac62ef04 2855 if (lp->mii) {
4a5e8e29 2856 curr_link = mii_link_ok(&lp->mii_if);
ac62ef04 2857 } else {
4a5e8e29
JG		 2858 ulong ioaddr = dev->base_addr; /* card base I/O address */
2859 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2860 }
2861 if (!curr_link) {
2862 if (prev_link || verbose) {
2863 netif_carrier_off(dev);
2864 if (netif_msg_link(lp))
2865 printk(KERN_INFO "%s: link down\n", dev->name);
2866 }
2867 if (lp->phycount > 1) {
2868 curr_link = pcnet32_check_otherphy(dev);
2869 prev_link = 0;
2870 }
2871 } else if (verbose || !prev_link) {
2872 netif_carrier_on(dev);
2873 if (lp->mii) {
2874 if (netif_msg_link(lp)) {
2875 struct ethtool_cmd ecmd;
2876 mii_ethtool_gset(&lp->mii_if, &ecmd);
2877 printk(KERN_INFO
2878 "%s: link up, %sMbps, %s-duplex\n",
2879 dev->name,
2880 (ecmd.speed == SPEED_100) ? "100" : "10",
2881 (ecmd.duplex ==
2882 DUPLEX_FULL) ? "full" : "half");
2883 }
2884 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2885 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2886 if (lp->mii_if.full_duplex)
2887 bcr9 |= (1 << 0);
2888 else
2889 bcr9 &= ~(1 << 0);
2890 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2891 }
2892 } else {
2893 if (netif_msg_link(lp))
2894 printk(KERN_INFO "%s: link up\n", dev->name);
2895 }
ac62ef04 2896 }
ac62ef04
DF		 2897}
2898
2899/*
2900 * Check for loss of link and link establishment.
2901 * Can not use mii_check_media because it does nothing if mode is forced.
2902 */
2903
1da177e4
LT		 2904static void pcnet32_watchdog(struct net_device *dev)
2905{
1e56a4b4 2906 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2907 unsigned long flags;
1da177e4 2908
4a5e8e29
JG		 2909 /* Print the link status if it has changed */
2910 spin_lock_irqsave(&lp->lock, flags);
2911 pcnet32_check_media(dev, 0);
2912 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2913
4a5e8e29 2914 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1da177e4
LT		 2915}
2916
917270c6
DF		 2917static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2918{
2919 struct net_device *dev = pci_get_drvdata(pdev);
2920
2921 if (netif_running(dev)) {
2922 netif_device_detach(dev);
2923 pcnet32_close(dev);
2924 }
2925 pci_save_state(pdev);
2926 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2927 return 0;
2928}
2929
2930static int pcnet32_pm_resume(struct pci_dev *pdev)
2931{
2932 struct net_device *dev = pci_get_drvdata(pdev);
2933
2934 pci_set_power_state(pdev, PCI_D0);
2935 pci_restore_state(pdev);
2936
2937 if (netif_running(dev)) {
2938 pcnet32_open(dev);
2939 netif_device_attach(dev);
2940 }
2941 return 0;
2942}
2943
1da177e4
LT		 2944static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2945{
4a5e8e29
JG		 2946 struct net_device *dev = pci_get_drvdata(pdev);
2947
2948 if (dev) {
1e56a4b4 2949 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2950
2951 unregister_netdev(dev);
2952 pcnet32_free_ring(dev);
2953 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
7d2e3cb7 2954 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 2955 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 2956 free_netdev(dev);
2957 pci_disable_device(pdev);
2958 pci_set_drvdata(pdev, NULL);
2959 }
1da177e4
LT		 2960}
2961
2962static struct pci_driver pcnet32_driver = {
4a5e8e29
JG		 2963 .name = DRV_NAME,
2964 .probe = pcnet32_probe_pci,
2965 .remove = __devexit_p(pcnet32_remove_one),
2966 .id_table = pcnet32_pci_tbl,
917270c6
DF		 2967 .suspend = pcnet32_pm_suspend,
2968 .resume = pcnet32_pm_resume,
1da177e4
LT		 2969};
2970
2971/* An additional parameter that may be passed in... */
2972static int debug = -1;
2973static int tx_start_pt = -1;
2974static int pcnet32_have_pci;
2975
2976module_param(debug, int, 0);
2977MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2978module_param(max_interrupt_work, int, 0);
4a5e8e29
JG		 2979MODULE_PARM_DESC(max_interrupt_work,
2980 DRV_NAME " maximum events handled per interrupt");
1da177e4 2981module_param(rx_copybreak, int, 0);
4a5e8e29
JG		 2982MODULE_PARM_DESC(rx_copybreak,
2983 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 2984module_param(tx_start_pt, int, 0);
2985MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2986module_param(pcnet32vlb, int, 0);
2987MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2988module_param_array(options, int, NULL, 0);
2989MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2990module_param_array(full_duplex, int, NULL, 0);
2991MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2992/* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2993module_param_array(homepna, int, NULL, 0);
4a5e8e29
JG		 2994MODULE_PARM_DESC(homepna,
2995 DRV_NAME
2996 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
1da177e4
LT		 2997
2998MODULE_AUTHOR("Thomas Bogendoerfer");
2999MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3000MODULE_LICENSE("GPL");
3001
3002#define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3003
3004static int __init pcnet32_init_module(void)
3005{
4a5e8e29 3006 printk(KERN_INFO "%s", version);
1da177e4 3007
4a5e8e29 3008 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
1da177e4 3009
4a5e8e29
JG		 3010 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3011 tx_start = tx_start_pt;
1da177e4 3012
4a5e8e29 3013 /* find the PCI devices */
29917620 3014 if (!pci_register_driver(&pcnet32_driver))
4a5e8e29 3015 pcnet32_have_pci = 1;
1da177e4 3016
4a5e8e29
JG		 3017 /* should we find any remaining VLbus devices ? */
3018 if (pcnet32vlb)
dcaf9769 3019 pcnet32_probe_vlbus(pcnet32_portlist);
1da177e4 3020
4a5e8e29
JG		 3021 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3022 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
1da177e4 3023
4a5e8e29 3024 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
1da177e4
LT		 3025}
3026
3027static void __exit pcnet32_cleanup_module(void)
3028{
4a5e8e29
JG		 3029 struct net_device *next_dev;
3030
3031 while (pcnet32_dev) {
1e56a4b4 3032 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
4a5e8e29
JG		 3033 next_dev = lp->next;
3034 unregister_netdev(pcnet32_dev);
3035 pcnet32_free_ring(pcnet32_dev);
3036 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
7d2e3cb7 3037 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 3038 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 3039 free_netdev(pcnet32_dev);
3040 pcnet32_dev = next_dev;
3041 }
1da177e4 3042
4a5e8e29
JG		 3043 if (pcnet32_have_pci)
3044 pci_unregister_driver(&pcnet32_driver);
1da177e4
LT		 3045}
3046
3047module_init(pcnet32_init_module);
3048module_exit(pcnet32_cleanup_module);
3049
3050/*
3051 * Local variables:
3052 * c-indent-level: 4
3053 * tab-width: 8
3054 * End:
3055 */
Clone of davem's net-next-2.6 tree