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[net-next-2.6.git] / drivers / net / pcnet32.c
CommitLineData
1da177e4
LT		 1/* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2/*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15/**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
13ff83b9
JP		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
1da177e4 26#define DRV_NAME "pcnet32"
01935d7d
DF		 27#define DRV_VERSION "1.35"
28#define DRV_RELDATE "21.Apr.2008"
1da177e4
LT		 29#define PFX DRV_NAME ": "
30
4a5e8e29
JG		 31static const char *const version =
32 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
1da177e4
LT		 33
34#include <linux/module.h>
35#include <linux/kernel.h>
d43c36dc 36#include <linux/sched.h>
1da177e4
LT		 37#include <linux/string.h>
38#include <linux/errno.h>
39#include <linux/ioport.h>
40#include <linux/slab.h>
41#include <linux/interrupt.h>
42#include <linux/pci.h>
43#include <linux/delay.h>
44#include <linux/init.h>
45#include <linux/ethtool.h>
46#include <linux/mii.h>
47#include <linux/crc32.h>
48#include <linux/netdevice.h>
49#include <linux/etherdevice.h>
1f044931 50#include <linux/if_ether.h>
1da177e4
LT		 51#include <linux/skbuff.h>
52#include <linux/spinlock.h>
53#include <linux/moduleparam.h>
54#include <linux/bitops.h>
9e3f8063
JP		 55#include <linux/io.h>
56#include <linux/uaccess.h>
1da177e4
LT		 57
58#include <asm/dma.h>
1da177e4
LT		 59#include <asm/irq.h>
60
61/*
62 * PCI device identifiers for "new style" Linux PCI Device Drivers
63 */
a3aa1884 64static DEFINE_PCI_DEVICE_TABLE(pcnet32_pci_tbl) = {
f2622a2b
DF		 65 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
4a5e8e29
JG		 67
68 /*
69 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
70 * the incorrect vendor id.
71 */
f2622a2b
DF		 72 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
73 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
4a5e8e29
JG		 74
75 { } /* terminate list */
1da177e4
LT		 76};
77
4a5e8e29 78MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
1da177e4
LT		 79
80static int cards_found;
81
82/*
83 * VLB I/O addresses
84 */
85static unsigned int pcnet32_portlist[] __initdata =
4a5e8e29 86 { 0x300, 0x320, 0x340, 0x360, 0 };
1da177e4 87
9e3f8063 88static int pcnet32_debug;
4a5e8e29
JG		 89static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
90static int pcnet32vlb; /* check for VLB cards ? */
1da177e4
LT		 91
92static struct net_device *pcnet32_dev;
93
94static int max_interrupt_work = 2;
95static int rx_copybreak = 200;
96
97#define PCNET32_PORT_AUI 0x00
98#define PCNET32_PORT_10BT 0x01
99#define PCNET32_PORT_GPSI 0x02
100#define PCNET32_PORT_MII 0x03
101
102#define PCNET32_PORT_PORTSEL 0x03
103#define PCNET32_PORT_ASEL 0x04
104#define PCNET32_PORT_100 0x40
105#define PCNET32_PORT_FD 0x80
106
107#define PCNET32_DMA_MASK 0xffffffff
108
109#define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
110#define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
111
112/*
113 * table to translate option values from tulip
114 * to internal options
115 */
f71e1309 116static const unsigned char options_mapping[] = {
4a5e8e29
JG		 117 PCNET32_PORT_ASEL, /* 0 Auto-select */
118 PCNET32_PORT_AUI, /* 1 BNC/AUI */
119 PCNET32_PORT_AUI, /* 2 AUI/BNC */
120 PCNET32_PORT_ASEL, /* 3 not supported */
121 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
122 PCNET32_PORT_ASEL, /* 5 not supported */
123 PCNET32_PORT_ASEL, /* 6 not supported */
124 PCNET32_PORT_ASEL, /* 7 not supported */
125 PCNET32_PORT_ASEL, /* 8 not supported */
126 PCNET32_PORT_MII, /* 9 MII 10baseT */
127 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
128 PCNET32_PORT_MII, /* 11 MII (autosel) */
129 PCNET32_PORT_10BT, /* 12 10BaseT */
130 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
131 /* 14 MII 100BaseTx-FD */
132 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
133 PCNET32_PORT_ASEL /* 15 not supported */
1da177e4
LT		 134};
135
136static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
4a5e8e29 137 "Loopback test (offline)"
1da177e4 138};
4a5e8e29 139
4c3616cd 140#define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test)
1da177e4 141
ac62ef04 142#define PCNET32_NUM_REGS 136
1da177e4 143
4a5e8e29 144#define MAX_UNITS 8 /* More are supported, limit only on options */
1da177e4
LT		 145static int options[MAX_UNITS];
146static int full_duplex[MAX_UNITS];
147static int homepna[MAX_UNITS];
148
149/*
150 * Theory of Operation
151 *
152 * This driver uses the same software structure as the normal lance
153 * driver. So look for a verbose description in lance.c. The differences
154 * to the normal lance driver is the use of the 32bit mode of PCnet32
155 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
156 * 16MB limitation and we don't need bounce buffers.
157 */
158
1da177e4
LT		 159/*
160 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
161 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
162 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
163 */
164#ifndef PCNET32_LOG_TX_BUFFERS
eabf0415
HWL		 165#define PCNET32_LOG_TX_BUFFERS 4
166#define PCNET32_LOG_RX_BUFFERS 5
167#define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
168#define PCNET32_LOG_MAX_RX_BUFFERS 9
1da177e4
LT		 169#endif
170
171#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
eabf0415 172#define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
1da177e4
LT		 173
174#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
eabf0415 175#define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
1da177e4 176
232c5640
DF		 177#define PKT_BUF_SKB 1544
178/* actual buffer length after being aligned */
179#define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN)
180/* chip wants twos complement of the (aligned) buffer length */
181#define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB)
1da177e4
LT		 182
183/* Offsets from base I/O address. */
184#define PCNET32_WIO_RDP 0x10
185#define PCNET32_WIO_RAP 0x12
186#define PCNET32_WIO_RESET 0x14
187#define PCNET32_WIO_BDP 0x16
188
189#define PCNET32_DWIO_RDP 0x10
190#define PCNET32_DWIO_RAP 0x14
191#define PCNET32_DWIO_RESET 0x18
192#define PCNET32_DWIO_BDP 0x1C
193
194#define PCNET32_TOTAL_SIZE 0x20
195
06c87850
DF		 196#define CSR0 0
197#define CSR0_INIT 0x1
198#define CSR0_START 0x2
199#define CSR0_STOP 0x4
200#define CSR0_TXPOLL 0x8
201#define CSR0_INTEN 0x40
202#define CSR0_IDON 0x0100
203#define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
204#define PCNET32_INIT_LOW 1
205#define PCNET32_INIT_HIGH 2
206#define CSR3 3
207#define CSR4 4
208#define CSR5 5
209#define CSR5_SUSPEND 0x0001
210#define CSR15 15
211#define PCNET32_MC_FILTER 8
212
8d916266
DF		 213#define PCNET32_79C970A 0x2621
214
1da177e4
LT		 215/* The PCNET32 Rx and Tx ring descriptors. */
216struct pcnet32_rx_head {
3e33545b
AV		 217 __le32 base;
218 __le16 buf_length; /* two`s complement of length */
219 __le16 status;
220 __le32 msg_length;
221 __le32 reserved;
1da177e4
LT		 222};
223
224struct pcnet32_tx_head {
3e33545b
AV		 225 __le32 base;
226 __le16 length; /* two`s complement of length */
227 __le16 status;
228 __le32 misc;
229 __le32 reserved;
1da177e4
LT		 230};
231
232/* The PCNET32 32-Bit initialization block, described in databook. */
233struct pcnet32_init_block {
3e33545b
AV		 234 __le16 mode;
235 __le16 tlen_rlen;
0b5bf225 236 u8 phys_addr[6];
3e33545b
AV		 237 __le16 reserved;
238 __le32 filter[2];
4a5e8e29 239 /* Receive and transmit ring base, along with extra bits. */
3e33545b
AV		 240 __le32 rx_ring;
241 __le32 tx_ring;
1da177e4
LT		 242};
243
244/* PCnet32 access functions */
245struct pcnet32_access {
4a5e8e29
JG		 246 u16 (*read_csr) (unsigned long, int);
247 void (*write_csr) (unsigned long, int, u16);
248 u16 (*read_bcr) (unsigned long, int);
249 void (*write_bcr) (unsigned long, int, u16);
250 u16 (*read_rap) (unsigned long);
251 void (*write_rap) (unsigned long, u16);
252 void (*reset) (unsigned long);
1da177e4
LT		 253};
254
255/*
76209926
HWL		 256 * The first field of pcnet32_private is read by the ethernet device
257 * so the structure should be allocated using pci_alloc_consistent().
1da177e4
LT		 258 */
259struct pcnet32_private {
6ecb7667 260 struct pcnet32_init_block *init_block;
4a5e8e29 261 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
0b5bf225
JG		 262 struct pcnet32_rx_head *rx_ring;
263 struct pcnet32_tx_head *tx_ring;
6ecb7667
DF		 264 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,
265 returned by pci_alloc_consistent */
0b5bf225
JG		 266 struct pci_dev *pci_dev;
267 const char *name;
4a5e8e29 268 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
0b5bf225
JG		 269 struct sk_buff **tx_skbuff;
270 struct sk_buff **rx_skbuff;
271 dma_addr_t *tx_dma_addr;
272 dma_addr_t *rx_dma_addr;
273 struct pcnet32_access a;
274 spinlock_t lock; /* Guard lock */
275 unsigned int cur_rx, cur_tx; /* The next free ring entry */
276 unsigned int rx_ring_size; /* current rx ring size */
277 unsigned int tx_ring_size; /* current tx ring size */
278 unsigned int rx_mod_mask; /* rx ring modular mask */
279 unsigned int tx_mod_mask; /* tx ring modular mask */
280 unsigned short rx_len_bits;
281 unsigned short tx_len_bits;
282 dma_addr_t rx_ring_dma_addr;
283 dma_addr_t tx_ring_dma_addr;
284 unsigned int dirty_rx, /* ring entries to be freed. */
285 dirty_tx;
286
bea3348e
SH		 287 struct net_device *dev;
288 struct napi_struct napi;
0b5bf225
JG		 289 char tx_full;
290 char phycount; /* number of phys found */
291 int options;
292 unsigned int shared_irq:1, /* shared irq possible */
293 dxsuflo:1, /* disable transmit stop on uflo */
294 mii:1; /* mii port available */
295 struct net_device *next;
296 struct mii_if_info mii_if;
297 struct timer_list watchdog_timer;
298 struct timer_list blink_timer;
299 u32 msg_enable; /* debug message level */
4a5e8e29
JG		 300
301 /* each bit indicates an available PHY */
0b5bf225 302 u32 phymask;
8d916266 303 unsigned short chip_version; /* which variant this is */
1da177e4
LT		 304};
305
4a5e8e29
JG		 306static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
307static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
308static int pcnet32_open(struct net_device *);
309static int pcnet32_init_ring(struct net_device *);
61357325
SH		 310static netdev_tx_t pcnet32_start_xmit(struct sk_buff *,
311 struct net_device *);
4a5e8e29 312static void pcnet32_tx_timeout(struct net_device *dev);
7d12e780 313static irqreturn_t pcnet32_interrupt(int, void *);
4a5e8e29 314static int pcnet32_close(struct net_device *);
1da177e4
LT		 315static struct net_device_stats *pcnet32_get_stats(struct net_device *);
316static void pcnet32_load_multicast(struct net_device *dev);
317static void pcnet32_set_multicast_list(struct net_device *);
4a5e8e29 318static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
1da177e4
LT		 319static void pcnet32_watchdog(struct net_device *);
320static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
4a5e8e29
JG		 321static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
322 int val);
1da177e4
LT		 323static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
324static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29
JG		 325 struct ethtool_test *eth_test, u64 * data);
326static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
1da177e4
LT		 327static int pcnet32_phys_id(struct net_device *dev, u32 data);
328static void pcnet32_led_blink_callback(struct net_device *dev);
329static int pcnet32_get_regs_len(struct net_device *dev);
330static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 331 void *ptr);
1bcd3153 332static void pcnet32_purge_tx_ring(struct net_device *dev);
b166cfba 333static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
eabf0415 334static void pcnet32_free_ring(struct net_device *dev);
ac62ef04 335static void pcnet32_check_media(struct net_device *dev, int verbose);
eabf0415 336
4a5e8e29 337static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
1da177e4 338{
4a5e8e29
JG		 339 outw(index, addr + PCNET32_WIO_RAP);
340 return inw(addr + PCNET32_WIO_RDP);
1da177e4
LT		 341}
342
4a5e8e29 343static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 344{
4a5e8e29
JG		 345 outw(index, addr + PCNET32_WIO_RAP);
346 outw(val, addr + PCNET32_WIO_RDP);
1da177e4
LT		 347}
348
4a5e8e29 349static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
1da177e4 350{
4a5e8e29
JG		 351 outw(index, addr + PCNET32_WIO_RAP);
352 return inw(addr + PCNET32_WIO_BDP);
1da177e4
LT		 353}
354
4a5e8e29 355static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 356{
4a5e8e29
JG		 357 outw(index, addr + PCNET32_WIO_RAP);
358 outw(val, addr + PCNET32_WIO_BDP);
1da177e4
LT		 359}
360
4a5e8e29 361static u16 pcnet32_wio_read_rap(unsigned long addr)
1da177e4 362{
4a5e8e29 363 return inw(addr + PCNET32_WIO_RAP);
1da177e4
LT		 364}
365
4a5e8e29 366static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
1da177e4 367{
4a5e8e29 368 outw(val, addr + PCNET32_WIO_RAP);
1da177e4
LT		 369}
370
4a5e8e29 371static void pcnet32_wio_reset(unsigned long addr)
1da177e4 372{
4a5e8e29 373 inw(addr + PCNET32_WIO_RESET);
1da177e4
LT		 374}
375
4a5e8e29 376static int pcnet32_wio_check(unsigned long addr)
1da177e4 377{
4a5e8e29 378 outw(88, addr + PCNET32_WIO_RAP);
807540ba 379 return inw(addr + PCNET32_WIO_RAP) == 88;
1da177e4
LT		 380}
381
382static struct pcnet32_access pcnet32_wio = {
4a5e8e29
JG		 383 .read_csr = pcnet32_wio_read_csr,
384 .write_csr = pcnet32_wio_write_csr,
385 .read_bcr = pcnet32_wio_read_bcr,
386 .write_bcr = pcnet32_wio_write_bcr,
387 .read_rap = pcnet32_wio_read_rap,
388 .write_rap = pcnet32_wio_write_rap,
389 .reset = pcnet32_wio_reset
1da177e4
LT		 390};
391
4a5e8e29 392static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
1da177e4 393{
4a5e8e29 394 outl(index, addr + PCNET32_DWIO_RAP);
9e3f8063 395 return inl(addr + PCNET32_DWIO_RDP) & 0xffff;
1da177e4
LT		 396}
397
4a5e8e29 398static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 399{
4a5e8e29
JG		 400 outl(index, addr + PCNET32_DWIO_RAP);
401 outl(val, addr + PCNET32_DWIO_RDP);
1da177e4
LT		 402}
403
4a5e8e29 404static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
1da177e4 405{
4a5e8e29 406 outl(index, addr + PCNET32_DWIO_RAP);
9e3f8063 407 return inl(addr + PCNET32_DWIO_BDP) & 0xffff;
1da177e4
LT		 408}
409
4a5e8e29 410static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 411{
4a5e8e29
JG		 412 outl(index, addr + PCNET32_DWIO_RAP);
413 outl(val, addr + PCNET32_DWIO_BDP);
1da177e4
LT		 414}
415
4a5e8e29 416static u16 pcnet32_dwio_read_rap(unsigned long addr)
1da177e4 417{
9e3f8063 418 return inl(addr + PCNET32_DWIO_RAP) & 0xffff;
1da177e4
LT		 419}
420
4a5e8e29 421static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
1da177e4 422{
4a5e8e29 423 outl(val, addr + PCNET32_DWIO_RAP);
1da177e4
LT		 424}
425
4a5e8e29 426static void pcnet32_dwio_reset(unsigned long addr)
1da177e4 427{
4a5e8e29 428 inl(addr + PCNET32_DWIO_RESET);
1da177e4
LT		 429}
430
4a5e8e29 431static int pcnet32_dwio_check(unsigned long addr)
1da177e4 432{
4a5e8e29 433 outl(88, addr + PCNET32_DWIO_RAP);
807540ba 434 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88;
1da177e4
LT		 435}
436
437static struct pcnet32_access pcnet32_dwio = {
4a5e8e29
JG		 438 .read_csr = pcnet32_dwio_read_csr,
439 .write_csr = pcnet32_dwio_write_csr,
440 .read_bcr = pcnet32_dwio_read_bcr,
441 .write_bcr = pcnet32_dwio_write_bcr,
442 .read_rap = pcnet32_dwio_read_rap,
443 .write_rap = pcnet32_dwio_write_rap,
444 .reset = pcnet32_dwio_reset
1da177e4
LT		 445};
446
06c87850
DF		 447static void pcnet32_netif_stop(struct net_device *dev)
448{
bea3348e 449 struct pcnet32_private *lp = netdev_priv(dev);
01935d7d 450
1ae5dc34 451 dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 452 napi_disable(&lp->napi);
06c87850
DF		 453 netif_tx_disable(dev);
454}
455
456static void pcnet32_netif_start(struct net_device *dev)
457{
bea3348e 458 struct pcnet32_private *lp = netdev_priv(dev);
d1d08d12
DM		 459 ulong ioaddr = dev->base_addr;
460 u16 val;
01935d7d 461
06c87850 462 netif_wake_queue(dev);
d1d08d12
DM		 463 val = lp->a.read_csr(ioaddr, CSR3);
464 val &= 0x00ff;
465 lp->a.write_csr(ioaddr, CSR3, val);
bea3348e 466 napi_enable(&lp->napi);
06c87850
DF		 467}
468
469/*
470 * Allocate space for the new sized tx ring.
471 * Free old resources
472 * Save new resources.
473 * Any failure keeps old resources.
474 * Must be called with lp->lock held.
475 */
476static void pcnet32_realloc_tx_ring(struct net_device *dev,
477 struct pcnet32_private *lp,
478 unsigned int size)
479{
480 dma_addr_t new_ring_dma_addr;
481 dma_addr_t *new_dma_addr_list;
482 struct pcnet32_tx_head *new_tx_ring;
483 struct sk_buff **new_skb_list;
484
485 pcnet32_purge_tx_ring(dev);
486
487 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
488 sizeof(struct pcnet32_tx_head) *
489 (1 << size),
490 &new_ring_dma_addr);
491 if (new_tx_ring == NULL) {
13ff83b9 492 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
06c87850
DF		 493 return;
494 }
495 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
496
497 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
498 GFP_ATOMIC);
499 if (!new_dma_addr_list) {
13ff83b9 500 netif_err(lp, drv, dev, "Memory allocation failed\n");
06c87850
DF		 501 goto free_new_tx_ring;
502 }
503
504 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
505 GFP_ATOMIC);
506 if (!new_skb_list) {
13ff83b9 507 netif_err(lp, drv, dev, "Memory allocation failed\n");
06c87850
DF		 508 goto free_new_lists;
509 }
510
511 kfree(lp->tx_skbuff);
512 kfree(lp->tx_dma_addr);
513 pci_free_consistent(lp->pci_dev,
514 sizeof(struct pcnet32_tx_head) *
515 lp->tx_ring_size, lp->tx_ring,
516 lp->tx_ring_dma_addr);
517
518 lp->tx_ring_size = (1 << size);
519 lp->tx_mod_mask = lp->tx_ring_size - 1;
520 lp->tx_len_bits = (size << 12);
521 lp->tx_ring = new_tx_ring;
522 lp->tx_ring_dma_addr = new_ring_dma_addr;
523 lp->tx_dma_addr = new_dma_addr_list;
524 lp->tx_skbuff = new_skb_list;
525 return;
526
9e3f8063 527free_new_lists:
06c87850 528 kfree(new_dma_addr_list);
9e3f8063 529free_new_tx_ring:
06c87850
DF		 530 pci_free_consistent(lp->pci_dev,
531 sizeof(struct pcnet32_tx_head) *
532 (1 << size),
533 new_tx_ring,
534 new_ring_dma_addr);
06c87850
DF		 535}
536
537/*
538 * Allocate space for the new sized rx ring.
539 * Re-use old receive buffers.
540 * alloc extra buffers
541 * free unneeded buffers
542 * free unneeded buffers
543 * Save new resources.
544 * Any failure keeps old resources.
545 * Must be called with lp->lock held.
546 */
547static void pcnet32_realloc_rx_ring(struct net_device *dev,
548 struct pcnet32_private *lp,
549 unsigned int size)
550{
551 dma_addr_t new_ring_dma_addr;
552 dma_addr_t *new_dma_addr_list;
553 struct pcnet32_rx_head *new_rx_ring;
554 struct sk_buff **new_skb_list;
555 int new, overlap;
556
557 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
558 sizeof(struct pcnet32_rx_head) *
559 (1 << size),
560 &new_ring_dma_addr);
561 if (new_rx_ring == NULL) {
13ff83b9 562 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
06c87850
DF		 563 return;
564 }
565 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
566
567 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
568 GFP_ATOMIC);
569 if (!new_dma_addr_list) {
13ff83b9 570 netif_err(lp, drv, dev, "Memory allocation failed\n");
06c87850
DF		 571 goto free_new_rx_ring;
572 }
573
574 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
575 GFP_ATOMIC);
576 if (!new_skb_list) {
13ff83b9 577 netif_err(lp, drv, dev, "Memory allocation failed\n");
06c87850
DF		 578 goto free_new_lists;
579 }
580
581 /* first copy the current receive buffers */
582 overlap = min(size, lp->rx_ring_size);
583 for (new = 0; new < overlap; new++) {
584 new_rx_ring[new] = lp->rx_ring[new];
585 new_dma_addr_list[new] = lp->rx_dma_addr[new];
586 new_skb_list[new] = lp->rx_skbuff[new];
587 }
588 /* now allocate any new buffers needed */
9e3f8063 589 for (; new < size; new++) {
06c87850 590 struct sk_buff *rx_skbuff;
232c5640 591 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SKB);
9e3f8063
JP		 592 rx_skbuff = new_skb_list[new];
593 if (!rx_skbuff) {
06c87850 594 /* keep the original lists and buffers */
13ff83b9
JP		 595 netif_err(lp, drv, dev, "%s dev_alloc_skb failed\n",
596 __func__);
06c87850
DF		 597 goto free_all_new;
598 }
232c5640 599 skb_reserve(rx_skbuff, NET_IP_ALIGN);
06c87850
DF		 600
601 new_dma_addr_list[new] =
602 pci_map_single(lp->pci_dev, rx_skbuff->data,
232c5640 603 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
3e33545b 604 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
232c5640 605 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
3e33545b 606 new_rx_ring[new].status = cpu_to_le16(0x8000);
06c87850
DF		 607 }
608 /* and free any unneeded buffers */
609 for (; new < lp->rx_ring_size; new++) {
610 if (lp->rx_skbuff[new]) {
611 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
232c5640 612 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
06c87850
DF		 613 dev_kfree_skb(lp->rx_skbuff[new]);
614 }
615 }
616
617 kfree(lp->rx_skbuff);
618 kfree(lp->rx_dma_addr);
619 pci_free_consistent(lp->pci_dev,
620 sizeof(struct pcnet32_rx_head) *
621 lp->rx_ring_size, lp->rx_ring,
622 lp->rx_ring_dma_addr);
623
624 lp->rx_ring_size = (1 << size);
625 lp->rx_mod_mask = lp->rx_ring_size - 1;
626 lp->rx_len_bits = (size << 4);
627 lp->rx_ring = new_rx_ring;
628 lp->rx_ring_dma_addr = new_ring_dma_addr;
629 lp->rx_dma_addr = new_dma_addr_list;
630 lp->rx_skbuff = new_skb_list;
631 return;
632
9e3f8063
JP		 633free_all_new:
634 while (--new >= lp->rx_ring_size) {
06c87850
DF		 635 if (new_skb_list[new]) {
636 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
232c5640 637 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
06c87850
DF		 638 dev_kfree_skb(new_skb_list[new]);
639 }
640 }
641 kfree(new_skb_list);
9e3f8063 642free_new_lists:
06c87850 643 kfree(new_dma_addr_list);
9e3f8063 644free_new_rx_ring:
06c87850
DF		 645 pci_free_consistent(lp->pci_dev,
646 sizeof(struct pcnet32_rx_head) *
647 (1 << size),
648 new_rx_ring,
649 new_ring_dma_addr);
06c87850
DF		 650}
651
ac5bfe40
DF		 652static void pcnet32_purge_rx_ring(struct net_device *dev)
653{
1e56a4b4 654 struct pcnet32_private *lp = netdev_priv(dev);
ac5bfe40
DF		 655 int i;
656
657 /* free all allocated skbuffs */
658 for (i = 0; i < lp->rx_ring_size; i++) {
659 lp->rx_ring[i].status = 0; /* CPU owns buffer */
660 wmb(); /* Make sure adapter sees owner change */
661 if (lp->rx_skbuff[i]) {
662 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
232c5640 663 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
ac5bfe40
DF		 664 dev_kfree_skb_any(lp->rx_skbuff[i]);
665 }
666 lp->rx_skbuff[i] = NULL;
667 lp->rx_dma_addr[i] = 0;
668 }
669}
670
1da177e4
LT		 671#ifdef CONFIG_NET_POLL_CONTROLLER
672static void pcnet32_poll_controller(struct net_device *dev)
673{
4a5e8e29 674 disable_irq(dev->irq);
7d12e780 675 pcnet32_interrupt(0, dev);
4a5e8e29 676 enable_irq(dev->irq);
1da177e4
LT		 677}
678#endif
679
1da177e4
LT		 680static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
681{
1e56a4b4 682 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 683 unsigned long flags;
684 int r = -EOPNOTSUPP;
1da177e4 685
4a5e8e29
JG		 686 if (lp->mii) {
687 spin_lock_irqsave(&lp->lock, flags);
688 mii_ethtool_gset(&lp->mii_if, cmd);
689 spin_unlock_irqrestore(&lp->lock, flags);
690 r = 0;
691 }
692 return r;
1da177e4
LT		 693}
694
695static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
696{
1e56a4b4 697 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 698 unsigned long flags;
699 int r = -EOPNOTSUPP;
1da177e4 700
4a5e8e29
JG		 701 if (lp->mii) {
702 spin_lock_irqsave(&lp->lock, flags);
703 r = mii_ethtool_sset(&lp->mii_if, cmd);
704 spin_unlock_irqrestore(&lp->lock, flags);
705 }
706 return r;
1da177e4
LT		 707}
708
4a5e8e29
JG		 709static void pcnet32_get_drvinfo(struct net_device *dev,
710 struct ethtool_drvinfo *info)
1da177e4 711{
1e56a4b4 712 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 713
714 strcpy(info->driver, DRV_NAME);
715 strcpy(info->version, DRV_VERSION);
716 if (lp->pci_dev)
717 strcpy(info->bus_info, pci_name(lp->pci_dev));
718 else
719 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
1da177e4
LT		 720}
721
722static u32 pcnet32_get_link(struct net_device *dev)
723{
1e56a4b4 724 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 725 unsigned long flags;
726 int r;
1da177e4 727
4a5e8e29
JG		 728 spin_lock_irqsave(&lp->lock, flags);
729 if (lp->mii) {
730 r = mii_link_ok(&lp->mii_if);
8d916266 731 } else if (lp->chip_version >= PCNET32_79C970A) {
4a5e8e29
JG		 732 ulong ioaddr = dev->base_addr; /* card base I/O address */
733 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
8d916266
DF		 734 } else { /* can not detect link on really old chips */
735 r = 1;
4a5e8e29
JG		 736 }
737 spin_unlock_irqrestore(&lp->lock, flags);
738
739 return r;
1da177e4
LT		 740}
741
742static u32 pcnet32_get_msglevel(struct net_device *dev)
743{
1e56a4b4 744 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 745 return lp->msg_enable;
1da177e4
LT		 746}
747
748static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
749{
1e56a4b4 750 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 751 lp->msg_enable = value;
1da177e4
LT		 752}
753
754static int pcnet32_nway_reset(struct net_device *dev)
755{
1e56a4b4 756 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 757 unsigned long flags;
758 int r = -EOPNOTSUPP;
1da177e4 759
4a5e8e29
JG		 760 if (lp->mii) {
761 spin_lock_irqsave(&lp->lock, flags);
762 r = mii_nway_restart(&lp->mii_if);
763 spin_unlock_irqrestore(&lp->lock, flags);
764 }
765 return r;
1da177e4
LT		 766}
767
4a5e8e29
JG		 768static void pcnet32_get_ringparam(struct net_device *dev,
769 struct ethtool_ringparam *ering)
1da177e4 770{
1e56a4b4 771 struct pcnet32_private *lp = netdev_priv(dev);
1da177e4 772
6dcd60c2
DF		 773 ering->tx_max_pending = TX_MAX_RING_SIZE;
774 ering->tx_pending = lp->tx_ring_size;
775 ering->rx_max_pending = RX_MAX_RING_SIZE;
776 ering->rx_pending = lp->rx_ring_size;
eabf0415
HWL		 777}
778
4a5e8e29
JG		 779static int pcnet32_set_ringparam(struct net_device *dev,
780 struct ethtool_ringparam *ering)
eabf0415 781{
1e56a4b4 782 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 783 unsigned long flags;
06c87850
DF		 784 unsigned int size;
785 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 786 int i;
787
788 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
789 return -EINVAL;
790
791 if (netif_running(dev))
06c87850 792 pcnet32_netif_stop(dev);
4a5e8e29
JG		 793
794 spin_lock_irqsave(&lp->lock, flags);
06c87850
DF		 795 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
796
797 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
4a5e8e29
JG		 798
799 /* set the minimum ring size to 4, to allow the loopback test to work
800 * unchanged.
801 */
802 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
06c87850 803 if (size <= (1 << i))
4a5e8e29
JG		 804 break;
805 }
06c87850
DF		 806 if ((1 << i) != lp->tx_ring_size)
807 pcnet32_realloc_tx_ring(dev, lp, i);
b368a3fb 808
06c87850 809 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
4a5e8e29 810 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
06c87850 811 if (size <= (1 << i))
4a5e8e29
JG		 812 break;
813 }
06c87850
DF		 814 if ((1 << i) != lp->rx_ring_size)
815 pcnet32_realloc_rx_ring(dev, lp, i);
b368a3fb 816
bea3348e 817 lp->napi.weight = lp->rx_ring_size / 2;
06c87850
DF		 818
819 if (netif_running(dev)) {
820 pcnet32_netif_start(dev);
821 pcnet32_restart(dev, CSR0_NORMAL);
4a5e8e29 822 }
eabf0415 823
4a5e8e29 824 spin_unlock_irqrestore(&lp->lock, flags);
eabf0415 825
13ff83b9
JP		 826 netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n",
827 lp->rx_ring_size, lp->tx_ring_size);
eabf0415 828
4a5e8e29 829 return 0;
1da177e4
LT		 830}
831
4a5e8e29 832static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
9e3f8063 833 u8 *data)
1da177e4 834{
4a5e8e29 835 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
1da177e4
LT		 836}
837
b9f2c044 838static int pcnet32_get_sset_count(struct net_device *dev, int sset)
1da177e4 839{
b9f2c044
JG		 840 switch (sset) {
841 case ETH_SS_TEST:
842 return PCNET32_TEST_LEN;
843 default:
844 return -EOPNOTSUPP;
845 }
1da177e4
LT		 846}
847
848static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29 849 struct ethtool_test *test, u64 * data)
1da177e4 850{
1e56a4b4 851 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 852 int rc;
853
854 if (test->flags == ETH_TEST_FL_OFFLINE) {
855 rc = pcnet32_loopback_test(dev, data);
856 if (rc) {
13ff83b9
JP		 857 netif_printk(lp, hw, KERN_DEBUG, dev,
858 "Loopback test failed\n");
4a5e8e29 859 test->flags |= ETH_TEST_FL_FAILED;
13ff83b9
JP		 860 } else
861 netif_printk(lp, hw, KERN_DEBUG, dev,
862 "Loopback test passed\n");
863 } else
864 netif_printk(lp, hw, KERN_DEBUG, dev,
865 "No tests to run (specify 'Offline' on ethtool)\n");
4a5e8e29 866} /* end pcnet32_ethtool_test */
1da177e4 867
4a5e8e29 868static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
1da177e4 869{
1e56a4b4 870 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 871 struct pcnet32_access *a = &lp->a; /* access to registers */
872 ulong ioaddr = dev->base_addr; /* card base I/O address */
873 struct sk_buff *skb; /* sk buff */
874 int x, i; /* counters */
875 int numbuffs = 4; /* number of TX/RX buffers and descs */
876 u16 status = 0x8300; /* TX ring status */
3e33545b 877 __le16 teststatus; /* test of ring status */
4a5e8e29
JG		 878 int rc; /* return code */
879 int size; /* size of packets */
880 unsigned char *packet; /* source packet data */
881 static const int data_len = 60; /* length of source packets */
882 unsigned long flags;
883 unsigned long ticks;
884
4a5e8e29
JG		 885 rc = 1; /* default to fail */
886
887 if (netif_running(dev))
7de745e5 888 pcnet32_netif_stop(dev);
4a5e8e29
JG		 889
890 spin_lock_irqsave(&lp->lock, flags);
ac5bfe40
DF		 891 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
892
893 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
4a5e8e29
JG		 894
895 /* Reset the PCNET32 */
896 lp->a.reset(ioaddr);
b368a3fb 897 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
4a5e8e29
JG		 898
899 /* switch pcnet32 to 32bit mode */
900 lp->a.write_bcr(ioaddr, 20, 2);
901
4a5e8e29
JG		 902 /* purge & init rings but don't actually restart */
903 pcnet32_restart(dev, 0x0000);
904
ac5bfe40 905 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 906
907 /* Initialize Transmit buffers. */
908 size = data_len + 15;
909 for (x = 0; x < numbuffs; x++) {
9e3f8063
JP		 910 skb = dev_alloc_skb(size);
911 if (!skb) {
13ff83b9
JP		 912 netif_printk(lp, hw, KERN_DEBUG, dev,
913 "Cannot allocate skb at line: %d!\n",
914 __LINE__);
4a5e8e29 915 goto clean_up;
4a5e8e29 916 }
9e3f8063
JP		 917 packet = skb->data;
918 skb_put(skb, size); /* create space for data */
919 lp->tx_skbuff[x] = skb;
920 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
921 lp->tx_ring[x].misc = 0;
922
923 /* put DA and SA into the skb */
924 for (i = 0; i < 6; i++)
925 *packet++ = dev->dev_addr[i];
926 for (i = 0; i < 6; i++)
927 *packet++ = dev->dev_addr[i];
928 /* type */
929 *packet++ = 0x08;
930 *packet++ = 0x06;
931 /* packet number */
932 *packet++ = x;
933 /* fill packet with data */
934 for (i = 0; i < data_len; i++)
935 *packet++ = i;
936
937 lp->tx_dma_addr[x] =
938 pci_map_single(lp->pci_dev, skb->data, skb->len,
939 PCI_DMA_TODEVICE);
940 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
941 wmb(); /* Make sure owner changes after all others are visible */
942 lp->tx_ring[x].status = cpu_to_le16(status);
1da177e4 943 }
1da177e4 944
ac5bfe40
DF		 945 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
946 a->write_bcr(ioaddr, 32, x | 0x0002);
4a5e8e29 947
ac5bfe40
DF		 948 /* set int loopback in CSR15 */
949 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
950 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
4a5e8e29 951
3e33545b 952 teststatus = cpu_to_le16(0x8000);
ac5bfe40 953 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
4a5e8e29
JG		 954
955 /* Check status of descriptors */
956 for (x = 0; x < numbuffs; x++) {
957 ticks = 0;
958 rmb();
959 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
960 spin_unlock_irqrestore(&lp->lock, flags);
ac5bfe40 961 msleep(1);
4a5e8e29
JG		 962 spin_lock_irqsave(&lp->lock, flags);
963 rmb();
964 ticks++;
965 }
966 if (ticks == 200) {
13ff83b9 967 netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x);
4a5e8e29
JG		 968 break;
969 }
970 }
971
ac5bfe40 972 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 973 wmb();
974 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
13ff83b9 975 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n");
4a5e8e29
JG		 976
977 for (x = 0; x < numbuffs; x++) {
13ff83b9 978 netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x);
4a5e8e29 979 skb = lp->rx_skbuff[x];
9e3f8063 980 for (i = 0; i < size; i++)
13ff83b9 981 pr_cont(" %02x", *(skb->data + i));
13ff83b9 982 pr_cont("\n");
4a5e8e29
JG		 983 }
984 }
1da177e4 985
4a5e8e29
JG		 986 x = 0;
987 rc = 0;
988 while (x < numbuffs && !rc) {
989 skb = lp->rx_skbuff[x];
990 packet = lp->tx_skbuff[x]->data;
991 for (i = 0; i < size; i++) {
992 if (*(skb->data + i) != packet[i]) {
13ff83b9
JP		 993 netif_printk(lp, hw, KERN_DEBUG, dev,
994 "Error in compare! %2x - %02x %02x\n",
995 i, *(skb->data + i), packet[i]);
4a5e8e29
JG		 996 rc = 1;
997 break;
998 }
999 }
1000 x++;
1001 }
1da177e4 1002
9e3f8063 1003clean_up:
ac5bfe40 1004 *data1 = rc;
4a5e8e29 1005 pcnet32_purge_tx_ring(dev);
1da177e4 1006
ac5bfe40
DF		 1007 x = a->read_csr(ioaddr, CSR15);
1008 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1da177e4 1009
ac5bfe40
DF		 1010 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1011 a->write_bcr(ioaddr, 32, (x & ~0x0002));
4a5e8e29 1012
7de745e5
DF		 1013 if (netif_running(dev)) {
1014 pcnet32_netif_start(dev);
1015 pcnet32_restart(dev, CSR0_NORMAL);
1016 } else {
1017 pcnet32_purge_rx_ring(dev);
1018 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1019 }
1020 spin_unlock_irqrestore(&lp->lock, flags);
4a5e8e29 1021
9e3f8063 1022 return rc;
4a5e8e29 1023} /* end pcnet32_loopback_test */
1da177e4
LT		 1024
1025static void pcnet32_led_blink_callback(struct net_device *dev)
1026{
1e56a4b4 1027 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1028 struct pcnet32_access *a = &lp->a;
1029 ulong ioaddr = dev->base_addr;
1030 unsigned long flags;
1031 int i;
1032
1033 spin_lock_irqsave(&lp->lock, flags);
9e3f8063 1034 for (i = 4; i < 8; i++)
4a5e8e29 1035 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
4a5e8e29
JG		 1036 spin_unlock_irqrestore(&lp->lock, flags);
1037
1038 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1da177e4
LT		 1039}
1040
1041static int pcnet32_phys_id(struct net_device *dev, u32 data)
1042{
1e56a4b4 1043 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1044 struct pcnet32_access *a = &lp->a;
1045 ulong ioaddr = dev->base_addr;
1046 unsigned long flags;
1047 int i, regs[4];
1048
1049 if (!lp->blink_timer.function) {
1050 init_timer(&lp->blink_timer);
1051 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1052 lp->blink_timer.data = (unsigned long)dev;
1053 }
1054
1055 /* Save the current value of the bcrs */
1056 spin_lock_irqsave(&lp->lock, flags);
9e3f8063 1057 for (i = 4; i < 8; i++)
4a5e8e29 1058 regs[i - 4] = a->read_bcr(ioaddr, i);
4a5e8e29
JG		 1059 spin_unlock_irqrestore(&lp->lock, flags);
1060
1061 mod_timer(&lp->blink_timer, jiffies);
1062 set_current_state(TASK_INTERRUPTIBLE);
1063
3e33545b 1064 /* AV: the limit here makes no sense whatsoever */
4a5e8e29
JG		 1065 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1066 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1067
1068 msleep_interruptible(data * 1000);
1069 del_timer_sync(&lp->blink_timer);
1070
1071 /* Restore the original value of the bcrs */
1072 spin_lock_irqsave(&lp->lock, flags);
9e3f8063 1073 for (i = 4; i < 8; i++)
4a5e8e29 1074 a->write_bcr(ioaddr, i, regs[i - 4]);
4a5e8e29
JG		 1075 spin_unlock_irqrestore(&lp->lock, flags);
1076
1077 return 0;
1da177e4
LT		 1078}
1079
df27f4a6
DF		 1080/*
1081 * lp->lock must be held.
1082 */
1083static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1084 int can_sleep)
1085{
1086 int csr5;
1e56a4b4 1087 struct pcnet32_private *lp = netdev_priv(dev);
df27f4a6
DF		 1088 struct pcnet32_access *a = &lp->a;
1089 ulong ioaddr = dev->base_addr;
1090 int ticks;
1091
8d916266
DF		 1092 /* really old chips have to be stopped. */
1093 if (lp->chip_version < PCNET32_79C970A)
1094 return 0;
1095
df27f4a6
DF		 1096 /* set SUSPEND (SPND) - CSR5 bit 0 */
1097 csr5 = a->read_csr(ioaddr, CSR5);
1098 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1099
1100 /* poll waiting for bit to be set */
1101 ticks = 0;
1102 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1103 spin_unlock_irqrestore(&lp->lock, *flags);
1104 if (can_sleep)
1105 msleep(1);
1106 else
1107 mdelay(1);
1108 spin_lock_irqsave(&lp->lock, *flags);
1109 ticks++;
1110 if (ticks > 200) {
13ff83b9
JP		 1111 netif_printk(lp, hw, KERN_DEBUG, dev,
1112 "Error getting into suspend!\n");
df27f4a6
DF		 1113 return 0;
1114 }
1115 }
1116 return 1;
1117}
1118
3904c324
DF		 1119/*
1120 * process one receive descriptor entry
1121 */
1122
1123static void pcnet32_rx_entry(struct net_device *dev,
1124 struct pcnet32_private *lp,
1125 struct pcnet32_rx_head *rxp,
1126 int entry)
1127{
1128 int status = (short)le16_to_cpu(rxp->status) >> 8;
1129 int rx_in_place = 0;
1130 struct sk_buff *skb;
1131 short pkt_len;
1132
1133 if (status != 0x03) { /* There was an error. */
1134 /*
1135 * There is a tricky error noted by John Murphy,
1136 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1137 * buffers it's possible for a jabber packet to use two
1138 * buffers, with only the last correctly noting the error.
1139 */
1140 if (status & 0x01) /* Only count a general error at the */
4f1e5ba0 1141 dev->stats.rx_errors++; /* end of a packet. */
3904c324 1142 if (status & 0x20)
4f1e5ba0 1143 dev->stats.rx_frame_errors++;
3904c324 1144 if (status & 0x10)
4f1e5ba0 1145 dev->stats.rx_over_errors++;
3904c324 1146 if (status & 0x08)
4f1e5ba0 1147 dev->stats.rx_crc_errors++;
3904c324 1148 if (status & 0x04)
4f1e5ba0 1149 dev->stats.rx_fifo_errors++;
3904c324
DF		 1150 return;
1151 }
1152
1153 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1154
1155 /* Discard oversize frames. */
232c5640 1156 if (unlikely(pkt_len > PKT_BUF_SIZE)) {
13ff83b9
JP		 1157 netif_err(lp, drv, dev, "Impossible packet size %d!\n",
1158 pkt_len);
4f1e5ba0 1159 dev->stats.rx_errors++;
3904c324
DF		 1160 return;
1161 }
1162 if (pkt_len < 60) {
13ff83b9 1163 netif_err(lp, rx_err, dev, "Runt packet!\n");
4f1e5ba0 1164 dev->stats.rx_errors++;
3904c324
DF		 1165 return;
1166 }
1167
1168 if (pkt_len > rx_copybreak) {
1169 struct sk_buff *newskb;
1170
9e3f8063
JP		 1171 newskb = dev_alloc_skb(PKT_BUF_SKB);
1172 if (newskb) {
232c5640 1173 skb_reserve(newskb, NET_IP_ALIGN);
3904c324
DF		 1174 skb = lp->rx_skbuff[entry];
1175 pci_unmap_single(lp->pci_dev,
1176 lp->rx_dma_addr[entry],
232c5640 1177 PKT_BUF_SIZE,
3904c324
DF		 1178 PCI_DMA_FROMDEVICE);
1179 skb_put(skb, pkt_len);
1180 lp->rx_skbuff[entry] = newskb;
3904c324
DF		 1181 lp->rx_dma_addr[entry] =
1182 pci_map_single(lp->pci_dev,
1183 newskb->data,
232c5640 1184 PKT_BUF_SIZE,
3904c324 1185 PCI_DMA_FROMDEVICE);
3e33545b 1186 rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
3904c324
DF		 1187 rx_in_place = 1;
1188 } else
1189 skb = NULL;
9e3f8063 1190 } else
232c5640 1191 skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN);
3904c324
DF		 1192
1193 if (skb == NULL) {
13ff83b9 1194 netif_err(lp, drv, dev, "Memory squeeze, dropping packet\n");
4f1e5ba0 1195 dev->stats.rx_dropped++;
3904c324
DF		 1196 return;
1197 }
3904c324 1198 if (!rx_in_place) {
232c5640 1199 skb_reserve(skb, NET_IP_ALIGN);
3904c324
DF		 1200 skb_put(skb, pkt_len); /* Make room */
1201 pci_dma_sync_single_for_cpu(lp->pci_dev,
1202 lp->rx_dma_addr[entry],
b2cbbd8e 1203 pkt_len,
3904c324 1204 PCI_DMA_FROMDEVICE);
8c7b7faa 1205 skb_copy_to_linear_data(skb,
3904c324 1206 (unsigned char *)(lp->rx_skbuff[entry]->data),
8c7b7faa 1207 pkt_len);
3904c324
DF		 1208 pci_dma_sync_single_for_device(lp->pci_dev,
1209 lp->rx_dma_addr[entry],
b2cbbd8e 1210 pkt_len,
3904c324
DF		 1211 PCI_DMA_FROMDEVICE);
1212 }
4f1e5ba0 1213 dev->stats.rx_bytes += skb->len;
3904c324 1214 skb->protocol = eth_type_trans(skb, dev);
7de745e5 1215 netif_receive_skb(skb);
4f1e5ba0 1216 dev->stats.rx_packets++;
3904c324
DF		 1217}
1218
bea3348e 1219static int pcnet32_rx(struct net_device *dev, int budget)
9691edd2 1220{
1e56a4b4 1221 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2 1222 int entry = lp->cur_rx & lp->rx_mod_mask;
3904c324
DF		 1223 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1224 int npackets = 0;
9691edd2
DF		 1225
1226 /* If we own the next entry, it's a new packet. Send it up. */
bea3348e 1227 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
3904c324
DF		 1228 pcnet32_rx_entry(dev, lp, rxp, entry);
1229 npackets += 1;
9691edd2 1230 /*
3904c324
DF		 1231 * The docs say that the buffer length isn't touched, but Andrew
1232 * Boyd of QNX reports that some revs of the 79C965 clear it.
9691edd2 1233 */
232c5640 1234 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
3904c324 1235 wmb(); /* Make sure owner changes after others are visible */
3e33545b 1236 rxp->status = cpu_to_le16(0x8000);
9691edd2 1237 entry = (++lp->cur_rx) & lp->rx_mod_mask;
3904c324 1238 rxp = &lp->rx_ring[entry];
9691edd2
DF		 1239 }
1240
7de745e5 1241 return npackets;
9691edd2
DF		 1242}
1243
7de745e5 1244static int pcnet32_tx(struct net_device *dev)
9691edd2 1245{
1e56a4b4 1246 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2
DF		 1247 unsigned int dirty_tx = lp->dirty_tx;
1248 int delta;
1249 int must_restart = 0;
1250
1251 while (dirty_tx != lp->cur_tx) {
1252 int entry = dirty_tx & lp->tx_mod_mask;
1253 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1254
1255 if (status < 0)
1256 break; /* It still hasn't been Txed */
1257
1258 lp->tx_ring[entry].base = 0;
1259
1260 if (status & 0x4000) {
3904c324 1261 /* There was a major error, log it. */
9691edd2 1262 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
4f1e5ba0 1263 dev->stats.tx_errors++;
13ff83b9
JP		 1264 netif_err(lp, tx_err, dev,
1265 "Tx error status=%04x err_status=%08x\n",
1266 status, err_status);
9691edd2 1267 if (err_status & 0x04000000)
4f1e5ba0 1268 dev->stats.tx_aborted_errors++;
9691edd2 1269 if (err_status & 0x08000000)
4f1e5ba0 1270 dev->stats.tx_carrier_errors++;
9691edd2 1271 if (err_status & 0x10000000)
4f1e5ba0 1272 dev->stats.tx_window_errors++;
9691edd2
DF		 1273#ifndef DO_DXSUFLO
1274 if (err_status & 0x40000000) {
4f1e5ba0 1275 dev->stats.tx_fifo_errors++;
9691edd2
DF		 1276 /* Ackk! On FIFO errors the Tx unit is turned off! */
1277 /* Remove this verbosity later! */
13ff83b9 1278 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
9691edd2
DF		 1279 must_restart = 1;
1280 }
1281#else
1282 if (err_status & 0x40000000) {
4f1e5ba0 1283 dev->stats.tx_fifo_errors++;
9691edd2
DF		 1284 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1285 /* Ackk! On FIFO errors the Tx unit is turned off! */
1286 /* Remove this verbosity later! */
13ff83b9 1287 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
9691edd2
DF		 1288 must_restart = 1;
1289 }
1290 }
1291#endif
1292 } else {
1293 if (status & 0x1800)
4f1e5ba0
DF		 1294 dev->stats.collisions++;
1295 dev->stats.tx_packets++;
9691edd2
DF		 1296 }
1297
1298 /* We must free the original skb */
1299 if (lp->tx_skbuff[entry]) {
1300 pci_unmap_single(lp->pci_dev,
1301 lp->tx_dma_addr[entry],
1302 lp->tx_skbuff[entry]->
1303 len, PCI_DMA_TODEVICE);
3904c324 1304 dev_kfree_skb_any(lp->tx_skbuff[entry]);
9691edd2
DF		 1305 lp->tx_skbuff[entry] = NULL;
1306 lp->tx_dma_addr[entry] = 0;
1307 }
1308 dirty_tx++;
1309 }
1310
3904c324 1311 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
9691edd2 1312 if (delta > lp->tx_ring_size) {
13ff83b9
JP		 1313 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1314 dirty_tx, lp->cur_tx, lp->tx_full);
9691edd2
DF		 1315 dirty_tx += lp->tx_ring_size;
1316 delta -= lp->tx_ring_size;
1317 }
1318
1319 if (lp->tx_full &&
1320 netif_queue_stopped(dev) &&
1321 delta < lp->tx_ring_size - 2) {
1322 /* The ring is no longer full, clear tbusy. */
1323 lp->tx_full = 0;
1324 netif_wake_queue(dev);
1325 }
1326 lp->dirty_tx = dirty_tx;
1327
1328 return must_restart;
1329}
1330
bea3348e 1331static int pcnet32_poll(struct napi_struct *napi, int budget)
7de745e5 1332{
bea3348e
SH		 1333 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1334 struct net_device *dev = lp->dev;
7de745e5
DF		 1335 unsigned long ioaddr = dev->base_addr;
1336 unsigned long flags;
bea3348e 1337 int work_done;
7de745e5
DF		 1338 u16 val;
1339
bea3348e 1340 work_done = pcnet32_rx(dev, budget);
7de745e5
DF		 1341
1342 spin_lock_irqsave(&lp->lock, flags);
1343 if (pcnet32_tx(dev)) {
1344 /* reset the chip to clear the error condition, then restart */
1345 lp->a.reset(ioaddr);
1346 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1347 pcnet32_restart(dev, CSR0_START);
1348 netif_wake_queue(dev);
1349 }
1350 spin_unlock_irqrestore(&lp->lock, flags);
1351
bea3348e
SH		 1352 if (work_done < budget) {
1353 spin_lock_irqsave(&lp->lock, flags);
7de745e5 1354
288379f0 1355 __napi_complete(napi);
7de745e5 1356
bea3348e
SH		 1357 /* clear interrupt masks */
1358 val = lp->a.read_csr(ioaddr, CSR3);
1359 val &= 0x00ff;
1360 lp->a.write_csr(ioaddr, CSR3, val);
7de745e5 1361
bea3348e
SH		 1362 /* Set interrupt enable. */
1363 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
ce105a08 1364
bea3348e
SH		 1365 spin_unlock_irqrestore(&lp->lock, flags);
1366 }
1367 return work_done;
7de745e5 1368}
7de745e5 1369
ac62ef04
DF		 1370#define PCNET32_REGS_PER_PHY 32
1371#define PCNET32_MAX_PHYS 32
1da177e4
LT		 1372static int pcnet32_get_regs_len(struct net_device *dev)
1373{
1e56a4b4 1374 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 1375 int j = lp->phycount * PCNET32_REGS_PER_PHY;
ac62ef04 1376
9e3f8063 1377 return (PCNET32_NUM_REGS + j) * sizeof(u16);
1da177e4
LT		 1378}
1379
1380static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 1381 void *ptr)
1da177e4 1382{
4a5e8e29
JG		 1383 int i, csr0;
1384 u16 *buff = ptr;
1e56a4b4 1385 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1386 struct pcnet32_access *a = &lp->a;
1387 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 1388 unsigned long flags;
1389
1390 spin_lock_irqsave(&lp->lock, flags);
1391
df27f4a6
DF		 1392 csr0 = a->read_csr(ioaddr, CSR0);
1393 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1394 pcnet32_suspend(dev, &flags, 1);
1da177e4 1395
4a5e8e29
JG		 1396 /* read address PROM */
1397 for (i = 0; i < 16; i += 2)
1398 *buff++ = inw(ioaddr + i);
1399
1400 /* read control and status registers */
9e3f8063 1401 for (i = 0; i < 90; i++)
4a5e8e29 1402 *buff++ = a->read_csr(ioaddr, i);
4a5e8e29
JG		 1403
1404 *buff++ = a->read_csr(ioaddr, 112);
1405 *buff++ = a->read_csr(ioaddr, 114);
1da177e4 1406
4a5e8e29 1407 /* read bus configuration registers */
9e3f8063 1408 for (i = 0; i < 30; i++)
4a5e8e29 1409 *buff++ = a->read_bcr(ioaddr, i);
9e3f8063 1410
4a5e8e29 1411 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
9e3f8063
JP		 1412
1413 for (i = 31; i < 36; i++)
4a5e8e29 1414 *buff++ = a->read_bcr(ioaddr, i);
4a5e8e29
JG		 1415
1416 /* read mii phy registers */
1417 if (lp->mii) {
1418 int j;
1419 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1420 if (lp->phymask & (1 << j)) {
1421 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1422 lp->a.write_bcr(ioaddr, 33,
1423 (j << 5) | i);
1424 *buff++ = lp->a.read_bcr(ioaddr, 34);
1425 }
1426 }
1427 }
1428 }
1429
df27f4a6
DF		 1430 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1431 int csr5;
1432
4a5e8e29 1433 /* clear SUSPEND (SPND) - CSR5 bit 0 */
df27f4a6
DF		 1434 csr5 = a->read_csr(ioaddr, CSR5);
1435 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
4a5e8e29
JG		 1436 }
1437
1438 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 1439}
1440
7282d491 1441static const struct ethtool_ops pcnet32_ethtool_ops = {
4a5e8e29
JG		 1442 .get_settings = pcnet32_get_settings,
1443 .set_settings = pcnet32_set_settings,
1444 .get_drvinfo = pcnet32_get_drvinfo,
1445 .get_msglevel = pcnet32_get_msglevel,
1446 .set_msglevel = pcnet32_set_msglevel,
1447 .nway_reset = pcnet32_nway_reset,
1448 .get_link = pcnet32_get_link,
1449 .get_ringparam = pcnet32_get_ringparam,
1450 .set_ringparam = pcnet32_set_ringparam,
4a5e8e29 1451 .get_strings = pcnet32_get_strings,
4a5e8e29
JG		 1452 .self_test = pcnet32_ethtool_test,
1453 .phys_id = pcnet32_phys_id,
1454 .get_regs_len = pcnet32_get_regs_len,
1455 .get_regs = pcnet32_get_regs,
b9f2c044 1456 .get_sset_count = pcnet32_get_sset_count,
1da177e4
LT		 1457};
1458
1459/* only probes for non-PCI devices, the rest are handled by
1460 * pci_register_driver via pcnet32_probe_pci */
1461
dcaf9769 1462static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1da177e4 1463{
4a5e8e29
JG		 1464 unsigned int *port, ioaddr;
1465
1466 /* search for PCnet32 VLB cards at known addresses */
1467 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1468 if (request_region
1469 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1470 /* check if there is really a pcnet chip on that ioaddr */
8e95a202
JP		 1471 if ((inb(ioaddr + 14) == 0x57) &&
1472 (inb(ioaddr + 15) == 0x57)) {
4a5e8e29
JG		 1473 pcnet32_probe1(ioaddr, 0, NULL);
1474 } else {
1475 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1476 }
1477 }
1478 }
1da177e4
LT		 1479}
1480
1da177e4
LT		 1481static int __devinit
1482pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1483{
4a5e8e29
JG		 1484 unsigned long ioaddr;
1485 int err;
1486
1487 err = pci_enable_device(pdev);
1488 if (err < 0) {
1489 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1490 pr_err("failed to enable device -- err=%d\n", err);
4a5e8e29
JG		 1491 return err;
1492 }
1493 pci_set_master(pdev);
1494
1495 ioaddr = pci_resource_start(pdev, 0);
1496 if (!ioaddr) {
1497 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1498 pr_err("card has no PCI IO resources, aborting\n");
4a5e8e29
JG		 1499 return -ENODEV;
1500 }
1da177e4 1501
4a5e8e29
JG		 1502 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1503 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1504 pr_err("architecture does not support 32bit PCI busmaster DMA\n");
4a5e8e29
JG		 1505 return -ENODEV;
1506 }
9e3f8063 1507 if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) {
4a5e8e29 1508 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1509 pr_err("io address range already allocated\n");
4a5e8e29
JG		 1510 return -EBUSY;
1511 }
1da177e4 1512
4a5e8e29 1513 err = pcnet32_probe1(ioaddr, 1, pdev);
9e3f8063 1514 if (err < 0)
4a5e8e29 1515 pci_disable_device(pdev);
9e3f8063 1516
4a5e8e29 1517 return err;
1da177e4
LT		 1518}
1519
3bc124dd
SH		 1520static const struct net_device_ops pcnet32_netdev_ops = {
1521 .ndo_open = pcnet32_open,
1522 .ndo_stop = pcnet32_close,
1523 .ndo_start_xmit = pcnet32_start_xmit,
1524 .ndo_tx_timeout = pcnet32_tx_timeout,
1525 .ndo_get_stats = pcnet32_get_stats,
1526 .ndo_set_multicast_list = pcnet32_set_multicast_list,
1527 .ndo_do_ioctl = pcnet32_ioctl,
1528 .ndo_change_mtu = eth_change_mtu,
1529 .ndo_set_mac_address = eth_mac_addr,
1530 .ndo_validate_addr = eth_validate_addr,
1531#ifdef CONFIG_NET_POLL_CONTROLLER
1532 .ndo_poll_controller = pcnet32_poll_controller,
1533#endif
1534};
1535
1da177e4
LT		 1536/* pcnet32_probe1
1537 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1538 * pdev will be NULL when called from pcnet32_probe_vlbus.
1539 */
1540static int __devinit
1541pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1542{
4a5e8e29 1543 struct pcnet32_private *lp;
4a5e8e29
JG		 1544 int i, media;
1545 int fdx, mii, fset, dxsuflo;
1546 int chip_version;
1547 char *chipname;
1548 struct net_device *dev;
1549 struct pcnet32_access *a = NULL;
1550 u8 promaddr[6];
1551 int ret = -ENODEV;
1552
1553 /* reset the chip */
1554 pcnet32_wio_reset(ioaddr);
1555
1556 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1557 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1558 a = &pcnet32_wio;
1559 } else {
1560 pcnet32_dwio_reset(ioaddr);
8e95a202
JP		 1561 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 &&
1562 pcnet32_dwio_check(ioaddr)) {
4a5e8e29 1563 a = &pcnet32_dwio;
df4e7f72
DF		 1564 } else {
1565 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1566 pr_err("No access methods\n");
4a5e8e29 1567 goto err_release_region;
df4e7f72 1568 }
4a5e8e29
JG		 1569 }
1570
1571 chip_version =
1572 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1573 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
13ff83b9 1574 pr_info(" PCnet chip version is %#x\n", chip_version);
4a5e8e29
JG		 1575 if ((chip_version & 0xfff) != 0x003) {
1576 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1577 pr_info("Unsupported chip version\n");
4a5e8e29
JG		 1578 goto err_release_region;
1579 }
1580
1581 /* initialize variables */
1582 fdx = mii = fset = dxsuflo = 0;
1583 chip_version = (chip_version >> 12) & 0xffff;
1584
1585 switch (chip_version) {
1586 case 0x2420:
1587 chipname = "PCnet/PCI 79C970"; /* PCI */
1588 break;
1589 case 0x2430:
1590 if (shared)
1591 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1592 else
1593 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1594 break;
1595 case 0x2621:
1596 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1597 fdx = 1;
1598 break;
1599 case 0x2623:
1600 chipname = "PCnet/FAST 79C971"; /* PCI */
1601 fdx = 1;
1602 mii = 1;
1603 fset = 1;
1604 break;
1605 case 0x2624:
1606 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1607 fdx = 1;
1608 mii = 1;
1609 fset = 1;
1610 break;
1611 case 0x2625:
1612 chipname = "PCnet/FAST III 79C973"; /* PCI */
1613 fdx = 1;
1614 mii = 1;
1615 break;
1616 case 0x2626:
1617 chipname = "PCnet/Home 79C978"; /* PCI */
1618 fdx = 1;
1619 /*
1620 * This is based on specs published at www.amd.com. This section
1621 * assumes that a card with a 79C978 wants to go into standard
1622 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1623 * and the module option homepna=1 can select this instead.
1624 */
1625 media = a->read_bcr(ioaddr, 49);
1626 media &= ~3; /* default to 10Mb ethernet */
1627 if (cards_found < MAX_UNITS && homepna[cards_found])
1628 media |= 1; /* switch to home wiring mode */
1629 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1630 printk(KERN_DEBUG PFX "media set to %sMbit mode\n",
4a5e8e29
JG		 1631 (media & 1) ? "1" : "10");
1632 a->write_bcr(ioaddr, 49, media);
1633 break;
1634 case 0x2627:
1635 chipname = "PCnet/FAST III 79C975"; /* PCI */
1636 fdx = 1;
1637 mii = 1;
1638 break;
1639 case 0x2628:
1640 chipname = "PCnet/PRO 79C976";
1641 fdx = 1;
1642 mii = 1;
1643 break;
1644 default:
1645 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9
JP		 1646 pr_info("PCnet version %#x, no PCnet32 chip\n",
1647 chip_version);
4a5e8e29
JG		 1648 goto err_release_region;
1649 }
1650
1da177e4 1651 /*
4a5e8e29
JG		 1652 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1653 * starting until the packet is loaded. Strike one for reliability, lose
1654 * one for latency - although on PCI this isnt a big loss. Older chips
1655 * have FIFO's smaller than a packet, so you can't do this.
1656 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1da177e4 1657 */
4a5e8e29
JG		 1658
1659 if (fset) {
1660 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1661 a->write_csr(ioaddr, 80,
1662 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1663 dxsuflo = 1;
1664 }
1665
6ecb7667 1666 dev = alloc_etherdev(sizeof(*lp));
4a5e8e29
JG		 1667 if (!dev) {
1668 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1669 pr_err("Memory allocation failed\n");
4a5e8e29
JG		 1670 ret = -ENOMEM;
1671 goto err_release_region;
1672 }
63097b3a
DF		 1673
1674 if (pdev)
1675 SET_NETDEV_DEV(dev, &pdev->dev);
4a5e8e29 1676
1da177e4 1677 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1678 pr_info("%s at %#3lx,", chipname, ioaddr);
4a5e8e29
JG		 1679
1680 /* In most chips, after a chip reset, the ethernet address is read from the
1681 * station address PROM at the base address and programmed into the
1682 * "Physical Address Registers" CSR12-14.
1683 * As a precautionary measure, we read the PROM values and complain if
bc0e1fc9
LV		 1684 * they disagree with the CSRs. If they miscompare, and the PROM addr
1685 * is valid, then the PROM addr is used.
4a5e8e29
JG		 1686 */
1687 for (i = 0; i < 3; i++) {
1688 unsigned int val;
1689 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1690 /* There may be endianness issues here. */
1691 dev->dev_addr[2 * i] = val & 0x0ff;
1692 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1693 }
1694
1695 /* read PROM address and compare with CSR address */
1da177e4 1696 for (i = 0; i < 6; i++)
4a5e8e29
JG		 1697 promaddr[i] = inb(ioaddr + i);
1698
8e95a202
JP		 1699 if (memcmp(promaddr, dev->dev_addr, 6) ||
1700 !is_valid_ether_addr(dev->dev_addr)) {
4a5e8e29
JG		 1701 if (is_valid_ether_addr(promaddr)) {
1702 if (pcnet32_debug & NETIF_MSG_PROBE) {
13ff83b9
JP		 1703 pr_cont(" warning: CSR address invalid,\n");
1704 pr_info(" using instead PROM address of");
4a5e8e29
JG		 1705 }
1706 memcpy(dev->dev_addr, promaddr, 6);
1707 }
1708 }
1709 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1710
1711 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1712 if (!is_valid_ether_addr(dev->perm_addr))
1f044931 1713 memset(dev->dev_addr, 0, ETH_ALEN);
4a5e8e29
JG		 1714
1715 if (pcnet32_debug & NETIF_MSG_PROBE) {
13ff83b9 1716 pr_cont(" %pM", dev->dev_addr);
4a5e8e29
JG		 1717
1718 /* Version 0x2623 and 0x2624 */
1719 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1720 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
13ff83b9 1721 pr_info(" tx_start_pt(0x%04x):", i);
4a5e8e29
JG		 1722 switch (i >> 10) {
1723 case 0:
13ff83b9 1724 pr_cont(" 20 bytes,");
4a5e8e29
JG		 1725 break;
1726 case 1:
13ff83b9 1727 pr_cont(" 64 bytes,");
4a5e8e29
JG		 1728 break;
1729 case 2:
13ff83b9 1730 pr_cont(" 128 bytes,");
4a5e8e29
JG		 1731 break;
1732 case 3:
13ff83b9 1733 pr_cont("~220 bytes,");
4a5e8e29
JG		 1734 break;
1735 }
1736 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
13ff83b9 1737 pr_cont(" BCR18(%x):", i & 0xffff);
4a5e8e29 1738 if (i & (1 << 5))
13ff83b9 1739 pr_cont("BurstWrEn ");
4a5e8e29 1740 if (i & (1 << 6))
13ff83b9 1741 pr_cont("BurstRdEn ");
4a5e8e29 1742 if (i & (1 << 7))
13ff83b9 1743 pr_cont("DWordIO ");
4a5e8e29 1744 if (i & (1 << 11))
13ff83b9 1745 pr_cont("NoUFlow ");
4a5e8e29 1746 i = a->read_bcr(ioaddr, 25);
13ff83b9 1747 pr_info(" SRAMSIZE=0x%04x,", i << 8);
4a5e8e29 1748 i = a->read_bcr(ioaddr, 26);
13ff83b9 1749 pr_cont(" SRAM_BND=0x%04x,", i << 8);
4a5e8e29
JG		 1750 i = a->read_bcr(ioaddr, 27);
1751 if (i & (1 << 14))
13ff83b9 1752 pr_cont("LowLatRx");
4a5e8e29
JG		 1753 }
1754 }
1755
1756 dev->base_addr = ioaddr;
1e56a4b4 1757 lp = netdev_priv(dev);
4a5e8e29 1758 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
9e3f8063
JP		 1759 lp->init_block = pci_alloc_consistent(pdev, sizeof(*lp->init_block),
1760 &lp->init_dma_addr);
1761 if (!lp->init_block) {
4a5e8e29 1762 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1763 pr_err("Consistent memory allocation failed\n");
4a5e8e29
JG		 1764 ret = -ENOMEM;
1765 goto err_free_netdev;
1766 }
4a5e8e29
JG		 1767 lp->pci_dev = pdev;
1768
bea3348e
SH		 1769 lp->dev = dev;
1770
4a5e8e29
JG		 1771 spin_lock_init(&lp->lock);
1772
4a5e8e29
JG		 1773 lp->name = chipname;
1774 lp->shared_irq = shared;
1775 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1776 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1777 lp->tx_mod_mask = lp->tx_ring_size - 1;
1778 lp->rx_mod_mask = lp->rx_ring_size - 1;
1779 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1780 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1781 lp->mii_if.full_duplex = fdx;
1782 lp->mii_if.phy_id_mask = 0x1f;
1783 lp->mii_if.reg_num_mask = 0x1f;
1784 lp->dxsuflo = dxsuflo;
1785 lp->mii = mii;
8d916266 1786 lp->chip_version = chip_version;
4a5e8e29 1787 lp->msg_enable = pcnet32_debug;
8e95a202
JP		 1788 if ((cards_found >= MAX_UNITS) ||
1789 (options[cards_found] >= sizeof(options_mapping)))
4a5e8e29
JG		 1790 lp->options = PCNET32_PORT_ASEL;
1791 else
1792 lp->options = options_mapping[options[cards_found]];
1793 lp->mii_if.dev = dev;
1794 lp->mii_if.mdio_read = mdio_read;
1795 lp->mii_if.mdio_write = mdio_write;
1796
feff348f
DF		 1797 /* napi.weight is used in both the napi and non-napi cases */
1798 lp->napi.weight = lp->rx_ring_size / 2;
1799
bea3348e 1800 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
bea3348e 1801
4a5e8e29
JG		 1802 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1803 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1804 lp->options |= PCNET32_PORT_FD;
1805
4a5e8e29
JG		 1806 lp->a = *a;
1807
1808 /* prior to register_netdev, dev->name is not yet correct */
1809 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1810 ret = -ENOMEM;
1811 goto err_free_ring;
1812 }
1813 /* detect special T1/E1 WAN card by checking for MAC address */
8e95a202
JP		 1814 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 &&
1815 dev->dev_addr[2] == 0x75)
4a5e8e29 1816 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1da177e4 1817
3e33545b 1818 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */
6ecb7667 1819 lp->init_block->tlen_rlen =
3e33545b 1820 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
4a5e8e29 1821 for (i = 0; i < 6; i++)
6ecb7667
DF		 1822 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1823 lp->init_block->filter[0] = 0x00000000;
1824 lp->init_block->filter[1] = 0x00000000;
3e33545b
AV		 1825 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1826 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
4a5e8e29
JG		 1827
1828 /* switch pcnet32 to 32bit mode */
1829 a->write_bcr(ioaddr, 20, 2);
1830
6ecb7667
DF		 1831 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1832 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29
JG		 1833
1834 if (pdev) { /* use the IRQ provided by PCI */
1835 dev->irq = pdev->irq;
1836 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1837 pr_cont(" assigned IRQ %d\n", dev->irq);
4a5e8e29
JG		 1838 } else {
1839 unsigned long irq_mask = probe_irq_on();
1840
1841 /*
1842 * To auto-IRQ we enable the initialization-done and DMA error
1843 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1844 * boards will work.
1845 */
1846 /* Trigger an initialization just for the interrupt. */
b368a3fb 1847 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
4a5e8e29
JG		 1848 mdelay(1);
1849
1850 dev->irq = probe_irq_off(irq_mask);
1851 if (!dev->irq) {
1852 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1853 pr_cont(", failed to detect IRQ line\n");
4a5e8e29
JG		 1854 ret = -ENODEV;
1855 goto err_free_ring;
1856 }
1857 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1858 pr_cont(", probed IRQ %d\n", dev->irq);
4a5e8e29 1859 }
1da177e4 1860
4a5e8e29
JG		 1861 /* Set the mii phy_id so that we can query the link state */
1862 if (lp->mii) {
1863 /* lp->phycount and lp->phymask are set to 0 by memset above */
1864
1865 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1866 /* scan for PHYs */
1867 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1868 unsigned short id1, id2;
1869
1870 id1 = mdio_read(dev, i, MII_PHYSID1);
1871 if (id1 == 0xffff)
1872 continue;
1873 id2 = mdio_read(dev, i, MII_PHYSID2);
1874 if (id2 == 0xffff)
1875 continue;
1876 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1877 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1878 lp->phycount++;
1879 lp->phymask |= (1 << i);
1880 lp->mii_if.phy_id = i;
1881 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9
JP		 1882 pr_info("Found PHY %04x:%04x at address %d\n",
1883 id1, id2, i);
4a5e8e29
JG		 1884 }
1885 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
9e3f8063 1886 if (lp->phycount > 1)
4a5e8e29 1887 lp->options |= PCNET32_PORT_MII;
1da177e4 1888 }
4a5e8e29
JG		 1889
1890 init_timer(&lp->watchdog_timer);
1891 lp->watchdog_timer.data = (unsigned long)dev;
1892 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1893
1894 /* The PCNET32-specific entries in the device structure. */
3bc124dd 1895 dev->netdev_ops = &pcnet32_netdev_ops;
4a5e8e29 1896 dev->ethtool_ops = &pcnet32_ethtool_ops;
4a5e8e29 1897 dev->watchdog_timeo = (5 * HZ);
1da177e4 1898
4a5e8e29
JG		 1899 /* Fill in the generic fields of the device structure. */
1900 if (register_netdev(dev))
1901 goto err_free_ring;
1902
1903 if (pdev) {
1904 pci_set_drvdata(pdev, dev);
1905 } else {
1906 lp->next = pcnet32_dev;
1907 pcnet32_dev = dev;
1908 }
1909
1910 if (pcnet32_debug & NETIF_MSG_PROBE)
13ff83b9 1911 pr_info("%s: registered as %s\n", dev->name, lp->name);
4a5e8e29
JG		 1912 cards_found++;
1913
1914 /* enable LED writes */
1915 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1da177e4 1916
4a5e8e29
JG		 1917 return 0;
1918
df4e7f72 1919err_free_ring:
4a5e8e29 1920 pcnet32_free_ring(dev);
7d2e3cb7 1921 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 1922 lp->init_block, lp->init_dma_addr);
df4e7f72 1923err_free_netdev:
4a5e8e29 1924 free_netdev(dev);
df4e7f72 1925err_release_region:
4a5e8e29
JG		 1926 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1927 return ret;
1928}
1da177e4 1929
a88c844c 1930/* if any allocation fails, caller must also call pcnet32_free_ring */
b166cfba 1931static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
eabf0415 1932{
1e56a4b4 1933 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 1934
4a5e8e29
JG		 1935 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1936 sizeof(struct pcnet32_tx_head) *
1937 lp->tx_ring_size,
1938 &lp->tx_ring_dma_addr);
1939 if (lp->tx_ring == NULL) {
13ff83b9 1940 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
4a5e8e29
JG		 1941 return -ENOMEM;
1942 }
eabf0415 1943
4a5e8e29
JG		 1944 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1945 sizeof(struct pcnet32_rx_head) *
1946 lp->rx_ring_size,
1947 &lp->rx_ring_dma_addr);
1948 if (lp->rx_ring == NULL) {
13ff83b9 1949 netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
4a5e8e29
JG		 1950 return -ENOMEM;
1951 }
eabf0415 1952
12fa30f3 1953 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 1954 GFP_ATOMIC);
1955 if (!lp->tx_dma_addr) {
13ff83b9 1956 netif_err(lp, drv, dev, "Memory allocation failed\n");
4a5e8e29
JG		 1957 return -ENOMEM;
1958 }
4a5e8e29 1959
12fa30f3 1960 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 1961 GFP_ATOMIC);
1962 if (!lp->rx_dma_addr) {
13ff83b9 1963 netif_err(lp, drv, dev, "Memory allocation failed\n");
4a5e8e29
JG		 1964 return -ENOMEM;
1965 }
4a5e8e29 1966
12fa30f3 1967 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 1968 GFP_ATOMIC);
1969 if (!lp->tx_skbuff) {
13ff83b9 1970 netif_err(lp, drv, dev, "Memory allocation failed\n");
4a5e8e29
JG		 1971 return -ENOMEM;
1972 }
4a5e8e29 1973
12fa30f3 1974 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 1975 GFP_ATOMIC);
1976 if (!lp->rx_skbuff) {
13ff83b9 1977 netif_err(lp, drv, dev, "Memory allocation failed\n");
4a5e8e29
JG		 1978 return -ENOMEM;
1979 }
4a5e8e29
JG		 1980
1981 return 0;
1982}
eabf0415
HWL		 1983
1984static void pcnet32_free_ring(struct net_device *dev)
1985{
1e56a4b4 1986 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 1987
4a5e8e29
JG		 1988 kfree(lp->tx_skbuff);
1989 lp->tx_skbuff = NULL;
eabf0415 1990
4a5e8e29
JG		 1991 kfree(lp->rx_skbuff);
1992 lp->rx_skbuff = NULL;
eabf0415 1993
4a5e8e29
JG		 1994 kfree(lp->tx_dma_addr);
1995 lp->tx_dma_addr = NULL;
eabf0415 1996
4a5e8e29
JG		 1997 kfree(lp->rx_dma_addr);
1998 lp->rx_dma_addr = NULL;
eabf0415 1999
4a5e8e29
JG		 2000 if (lp->tx_ring) {
2001 pci_free_consistent(lp->pci_dev,
2002 sizeof(struct pcnet32_tx_head) *
2003 lp->tx_ring_size, lp->tx_ring,
2004 lp->tx_ring_dma_addr);
2005 lp->tx_ring = NULL;
2006 }
eabf0415 2007
4a5e8e29
JG		 2008 if (lp->rx_ring) {
2009 pci_free_consistent(lp->pci_dev,
2010 sizeof(struct pcnet32_rx_head) *
2011 lp->rx_ring_size, lp->rx_ring,
2012 lp->rx_ring_dma_addr);
2013 lp->rx_ring = NULL;
2014 }
eabf0415
HWL		 2015}
2016
4a5e8e29 2017static int pcnet32_open(struct net_device *dev)
1da177e4 2018{
1e56a4b4 2019 struct pcnet32_private *lp = netdev_priv(dev);
63097b3a 2020 struct pci_dev *pdev = lp->pci_dev;
4a5e8e29
JG		 2021 unsigned long ioaddr = dev->base_addr;
2022 u16 val;
2023 int i;
2024 int rc;
2025 unsigned long flags;
2026
a0607fd3 2027 if (request_irq(dev->irq, pcnet32_interrupt,
1fb9df5d 2028 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
4a5e8e29
JG		 2029 (void *)dev)) {
2030 return -EAGAIN;
2031 }
2032
2033 spin_lock_irqsave(&lp->lock, flags);
2034 /* Check for a valid station address */
2035 if (!is_valid_ether_addr(dev->dev_addr)) {
2036 rc = -EINVAL;
2037 goto err_free_irq;
2038 }
2039
2040 /* Reset the PCNET32 */
2041 lp->a.reset(ioaddr);
2042
2043 /* switch pcnet32 to 32bit mode */
2044 lp->a.write_bcr(ioaddr, 20, 2);
2045
13ff83b9
JP		 2046 netif_printk(lp, ifup, KERN_DEBUG, dev,
2047 "%s() irq %d tx/rx rings %#x/%#x init %#x\n",
2048 __func__, dev->irq, (u32) (lp->tx_ring_dma_addr),
2049 (u32) (lp->rx_ring_dma_addr),
2050 (u32) (lp->init_dma_addr));
4a5e8e29
JG		 2051
2052 /* set/reset autoselect bit */
2053 val = lp->a.read_bcr(ioaddr, 2) & ~2;
2054 if (lp->options & PCNET32_PORT_ASEL)
1da177e4 2055 val |= 2;
4a5e8e29
JG		 2056 lp->a.write_bcr(ioaddr, 2, val);
2057
2058 /* handle full duplex setting */
2059 if (lp->mii_if.full_duplex) {
2060 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2061 if (lp->options & PCNET32_PORT_FD) {
2062 val |= 1;
2063 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2064 val |= 2;
2065 } else if (lp->options & PCNET32_PORT_ASEL) {
2066 /* workaround of xSeries250, turn on for 79C975 only */
8d916266 2067 if (lp->chip_version == 0x2627)
4a5e8e29
JG		 2068 val |= 3;
2069 }
2070 lp->a.write_bcr(ioaddr, 9, val);
2071 }
2072
2073 /* set/reset GPSI bit in test register */
2074 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2075 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2076 val |= 0x10;
2077 lp->a.write_csr(ioaddr, 124, val);
2078
2079 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
63097b3a
DF		 2080 if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2081 (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2082 pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
ac62ef04 2083 if (lp->options & PCNET32_PORT_ASEL) {
4a5e8e29 2084 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
13ff83b9
JP		 2085 netif_printk(lp, link, KERN_DEBUG, dev,
2086 "Setting 100Mb-Full Duplex\n");
4a5e8e29
JG		 2087 }
2088 }
2089 if (lp->phycount < 2) {
2090 /*
2091 * 24 Jun 2004 according AMD, in order to change the PHY,
2092 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2093 * duplex, and/or enable auto negotiation, and clear DANAS
2094 */
2095 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2096 lp->a.write_bcr(ioaddr, 32,
2097 lp->a.read_bcr(ioaddr, 32) | 0x0080);
2098 /* disable Auto Negotiation, set 10Mpbs, HD */
2099 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2100 if (lp->options & PCNET32_PORT_FD)
2101 val |= 0x10;
2102 if (lp->options & PCNET32_PORT_100)
2103 val |= 0x08;
2104 lp->a.write_bcr(ioaddr, 32, val);
2105 } else {
2106 if (lp->options & PCNET32_PORT_ASEL) {
2107 lp->a.write_bcr(ioaddr, 32,
2108 lp->a.read_bcr(ioaddr,
2109 32) | 0x0080);
2110 /* enable auto negotiate, setup, disable fd */
2111 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2112 val |= 0x20;
2113 lp->a.write_bcr(ioaddr, 32, val);
2114 }
2115 }
2116 } else {
2117 int first_phy = -1;
2118 u16 bmcr;
2119 u32 bcr9;
2120 struct ethtool_cmd ecmd;
2121
2122 /*
2123 * There is really no good other way to handle multiple PHYs
2124 * other than turning off all automatics
2125 */
2126 val = lp->a.read_bcr(ioaddr, 2);
2127 lp->a.write_bcr(ioaddr, 2, val & ~2);
2128 val = lp->a.read_bcr(ioaddr, 32);
2129 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2130
2131 if (!(lp->options & PCNET32_PORT_ASEL)) {
2132 /* setup ecmd */
2133 ecmd.port = PORT_MII;
2134 ecmd.transceiver = XCVR_INTERNAL;
2135 ecmd.autoneg = AUTONEG_DISABLE;
2136 ecmd.speed =
2137 lp->
2138 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2139 bcr9 = lp->a.read_bcr(ioaddr, 9);
2140
2141 if (lp->options & PCNET32_PORT_FD) {
2142 ecmd.duplex = DUPLEX_FULL;
2143 bcr9 |= (1 << 0);
2144 } else {
2145 ecmd.duplex = DUPLEX_HALF;
2146 bcr9 |= ~(1 << 0);
2147 }
2148 lp->a.write_bcr(ioaddr, 9, bcr9);
ac62ef04 2149 }
4a5e8e29
JG		 2150
2151 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2152 if (lp->phymask & (1 << i)) {
2153 /* isolate all but the first PHY */
2154 bmcr = mdio_read(dev, i, MII_BMCR);
2155 if (first_phy == -1) {
2156 first_phy = i;
2157 mdio_write(dev, i, MII_BMCR,
2158 bmcr & ~BMCR_ISOLATE);
2159 } else {
2160 mdio_write(dev, i, MII_BMCR,
2161 bmcr | BMCR_ISOLATE);
2162 }
2163 /* use mii_ethtool_sset to setup PHY */
2164 lp->mii_if.phy_id = i;
2165 ecmd.phy_address = i;
2166 if (lp->options & PCNET32_PORT_ASEL) {
2167 mii_ethtool_gset(&lp->mii_if, &ecmd);
2168 ecmd.autoneg = AUTONEG_ENABLE;
2169 }
2170 mii_ethtool_sset(&lp->mii_if, &ecmd);
2171 }
2172 }
2173 lp->mii_if.phy_id = first_phy;
13ff83b9 2174 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy);
4a5e8e29 2175 }
1da177e4
LT		 2176
2177#ifdef DO_DXSUFLO
4a5e8e29 2178 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
b368a3fb 2179 val = lp->a.read_csr(ioaddr, CSR3);
4a5e8e29 2180 val |= 0x40;
b368a3fb 2181 lp->a.write_csr(ioaddr, CSR3, val);
4a5e8e29 2182 }
1da177e4
LT		 2183#endif
2184
6ecb7667 2185 lp->init_block->mode =
3e33545b 2186 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
4a5e8e29
JG		 2187 pcnet32_load_multicast(dev);
2188
2189 if (pcnet32_init_ring(dev)) {
2190 rc = -ENOMEM;
2191 goto err_free_ring;
2192 }
2193
bea3348e 2194 napi_enable(&lp->napi);
bea3348e 2195
4a5e8e29 2196 /* Re-initialize the PCNET32, and start it when done. */
6ecb7667
DF		 2197 lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2198 lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29 2199
b368a3fb
DF		 2200 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2201 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2202
2203 netif_start_queue(dev);
2204
8d916266
DF		 2205 if (lp->chip_version >= PCNET32_79C970A) {
2206 /* Print the link status and start the watchdog */
2207 pcnet32_check_media(dev, 1);
283a21d3 2208 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT);
8d916266 2209 }
4a5e8e29
JG		 2210
2211 i = 0;
2212 while (i++ < 100)
b368a3fb 2213 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29
JG		 2214 break;
2215 /*
2216 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2217 * reports that doing so triggers a bug in the '974.
2218 */
b368a3fb 2219 lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
4a5e8e29 2220
13ff83b9
JP		 2221 netif_printk(lp, ifup, KERN_DEBUG, dev,
2222 "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n",
2223 i,
2224 (u32) (lp->init_dma_addr),
2225 lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2226
2227 spin_unlock_irqrestore(&lp->lock, flags);
2228
2229 return 0; /* Always succeed */
2230
9e3f8063 2231err_free_ring:
4a5e8e29 2232 /* free any allocated skbuffs */
ac5bfe40 2233 pcnet32_purge_rx_ring(dev);
4a5e8e29 2234
4a5e8e29
JG		 2235 /*
2236 * Switch back to 16bit mode to avoid problems with dumb
2237 * DOS packet driver after a warm reboot
2238 */
2239 lp->a.write_bcr(ioaddr, 20, 4);
2240
9e3f8063 2241err_free_irq:
4a5e8e29
JG		 2242 spin_unlock_irqrestore(&lp->lock, flags);
2243 free_irq(dev->irq, dev);
2244 return rc;
1da177e4
LT		 2245}
2246
2247/*
2248 * The LANCE has been halted for one reason or another (busmaster memory
2249 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2250 * etc.). Modern LANCE variants always reload their ring-buffer
2251 * configuration when restarted, so we must reinitialize our ring
2252 * context before restarting. As part of this reinitialization,
2253 * find all packets still on the Tx ring and pretend that they had been
2254 * sent (in effect, drop the packets on the floor) - the higher-level
2255 * protocols will time out and retransmit. It'd be better to shuffle
2256 * these skbs to a temp list and then actually re-Tx them after
2257 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2258 */
2259
4a5e8e29 2260static void pcnet32_purge_tx_ring(struct net_device *dev)
1da177e4 2261{
1e56a4b4 2262 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2263 int i;
1da177e4 2264
4a5e8e29
JG		 2265 for (i = 0; i < lp->tx_ring_size; i++) {
2266 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2267 wmb(); /* Make sure adapter sees owner change */
2268 if (lp->tx_skbuff[i]) {
2269 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2270 lp->tx_skbuff[i]->len,
2271 PCI_DMA_TODEVICE);
2272 dev_kfree_skb_any(lp->tx_skbuff[i]);
2273 }
2274 lp->tx_skbuff[i] = NULL;
2275 lp->tx_dma_addr[i] = 0;
2276 }
2277}
1da177e4
LT		 2278
2279/* Initialize the PCNET32 Rx and Tx rings. */
4a5e8e29 2280static int pcnet32_init_ring(struct net_device *dev)
1da177e4 2281{
1e56a4b4 2282 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2283 int i;
2284
2285 lp->tx_full = 0;
2286 lp->cur_rx = lp->cur_tx = 0;
2287 lp->dirty_rx = lp->dirty_tx = 0;
2288
2289 for (i = 0; i < lp->rx_ring_size; i++) {
2290 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2291 if (rx_skbuff == NULL) {
9e3f8063
JP		 2292 lp->rx_skbuff[i] = dev_alloc_skb(PKT_BUF_SKB);
2293 rx_skbuff = lp->rx_skbuff[i];
2294 if (!rx_skbuff) {
2295 /* there is not much we can do at this point */
13ff83b9
JP		 2296 netif_err(lp, drv, dev, "%s dev_alloc_skb failed\n",
2297 __func__);
4a5e8e29
JG		 2298 return -1;
2299 }
232c5640 2300 skb_reserve(rx_skbuff, NET_IP_ALIGN);
4a5e8e29
JG		 2301 }
2302
2303 rmb();
2304 if (lp->rx_dma_addr[i] == 0)
2305 lp->rx_dma_addr[i] =
2306 pci_map_single(lp->pci_dev, rx_skbuff->data,
232c5640 2307 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
3e33545b 2308 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
232c5640 2309 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
4a5e8e29 2310 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 2311 lp->rx_ring[i].status = cpu_to_le16(0x8000);
4a5e8e29
JG		 2312 }
2313 /* The Tx buffer address is filled in as needed, but we do need to clear
2314 * the upper ownership bit. */
2315 for (i = 0; i < lp->tx_ring_size; i++) {
2316 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2317 wmb(); /* Make sure adapter sees owner change */
2318 lp->tx_ring[i].base = 0;
2319 lp->tx_dma_addr[i] = 0;
2320 }
2321
6ecb7667 2322 lp->init_block->tlen_rlen =
3e33545b 2323 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
4a5e8e29 2324 for (i = 0; i < 6; i++)
6ecb7667 2325 lp->init_block->phys_addr[i] = dev->dev_addr[i];
3e33545b
AV		 2326 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2327 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
4a5e8e29
JG		 2328 wmb(); /* Make sure all changes are visible */
2329 return 0;
1da177e4
LT		 2330}
2331
2332/* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2333 * then flush the pending transmit operations, re-initialize the ring,
2334 * and tell the chip to initialize.
2335 */
4a5e8e29 2336static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1da177e4 2337{
1e56a4b4 2338 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2339 unsigned long ioaddr = dev->base_addr;
2340 int i;
1da177e4 2341
4a5e8e29
JG		 2342 /* wait for stop */
2343 for (i = 0; i < 100; i++)
b368a3fb 2344 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
4a5e8e29 2345 break;
1da177e4 2346
13ff83b9
JP		 2347 if (i >= 100)
2348 netif_err(lp, drv, dev, "%s timed out waiting for stop\n",
2349 __func__);
1da177e4 2350
4a5e8e29
JG		 2351 pcnet32_purge_tx_ring(dev);
2352 if (pcnet32_init_ring(dev))
2353 return;
1da177e4 2354
4a5e8e29 2355 /* ReInit Ring */
b368a3fb 2356 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2357 i = 0;
2358 while (i++ < 1000)
b368a3fb 2359 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29 2360 break;
1da177e4 2361
b368a3fb 2362 lp->a.write_csr(ioaddr, CSR0, csr0_bits);
1da177e4
LT		 2363}
2364
4a5e8e29 2365static void pcnet32_tx_timeout(struct net_device *dev)
1da177e4 2366{
1e56a4b4 2367 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2368 unsigned long ioaddr = dev->base_addr, flags;
2369
2370 spin_lock_irqsave(&lp->lock, flags);
2371 /* Transmitter timeout, serious problems. */
2372 if (pcnet32_debug & NETIF_MSG_DRV)
13ff83b9 2373 pr_err("%s: transmit timed out, status %4.4x, resetting\n",
b368a3fb
DF		 2374 dev->name, lp->a.read_csr(ioaddr, CSR0));
2375 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
4f1e5ba0 2376 dev->stats.tx_errors++;
4a5e8e29
JG		 2377 if (netif_msg_tx_err(lp)) {
2378 int i;
2379 printk(KERN_DEBUG
2380 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2381 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2382 lp->cur_rx);
2383 for (i = 0; i < lp->rx_ring_size; i++)
2384 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2385 le32_to_cpu(lp->rx_ring[i].base),
2386 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2387 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2388 le16_to_cpu(lp->rx_ring[i].status));
2389 for (i = 0; i < lp->tx_ring_size; i++)
2390 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2391 le32_to_cpu(lp->tx_ring[i].base),
2392 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2393 le32_to_cpu(lp->tx_ring[i].misc),
2394 le16_to_cpu(lp->tx_ring[i].status));
2395 printk("\n");
2396 }
b368a3fb 2397 pcnet32_restart(dev, CSR0_NORMAL);
1da177e4 2398
1ae5dc34 2399 dev->trans_start = jiffies; /* prevent tx timeout */
4a5e8e29 2400 netif_wake_queue(dev);
1da177e4 2401
4a5e8e29
JG		 2402 spin_unlock_irqrestore(&lp->lock, flags);
2403}
2404
61357325
SH		 2405static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb,
2406 struct net_device *dev)
1da177e4 2407{
1e56a4b4 2408 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2409 unsigned long ioaddr = dev->base_addr;
2410 u16 status;
2411 int entry;
2412 unsigned long flags;
1da177e4 2413
4a5e8e29 2414 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2415
13ff83b9
JP		 2416 netif_printk(lp, tx_queued, KERN_DEBUG, dev,
2417 "%s() called, csr0 %4.4x\n",
2418 __func__, lp->a.read_csr(ioaddr, CSR0));
1da177e4 2419
4a5e8e29
JG		 2420 /* Default status -- will not enable Successful-TxDone
2421 * interrupt when that option is available to us.
2422 */
2423 status = 0x8300;
1da177e4 2424
4a5e8e29 2425 /* Fill in a Tx ring entry */
1da177e4 2426
4a5e8e29
JG		 2427 /* Mask to ring buffer boundary. */
2428 entry = lp->cur_tx & lp->tx_mod_mask;
1da177e4 2429
4a5e8e29
JG		 2430 /* Caution: the write order is important here, set the status
2431 * with the "ownership" bits last. */
1da177e4 2432
3e33545b 2433 lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
1da177e4 2434
4a5e8e29 2435 lp->tx_ring[entry].misc = 0x00000000;
1da177e4 2436
4a5e8e29
JG		 2437 lp->tx_skbuff[entry] = skb;
2438 lp->tx_dma_addr[entry] =
2439 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
3e33545b 2440 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
4a5e8e29 2441 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 2442 lp->tx_ring[entry].status = cpu_to_le16(status);
1da177e4 2443
4a5e8e29 2444 lp->cur_tx++;
4f1e5ba0 2445 dev->stats.tx_bytes += skb->len;
1da177e4 2446
4a5e8e29 2447 /* Trigger an immediate send poll. */
b368a3fb 2448 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
1da177e4 2449
4a5e8e29
JG		 2450 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2451 lp->tx_full = 1;
2452 netif_stop_queue(dev);
2453 }
2454 spin_unlock_irqrestore(&lp->lock, flags);
6ed10654 2455 return NETDEV_TX_OK;
1da177e4
LT		 2456}
2457
2458/* The PCNET32 interrupt handler. */
2459static irqreturn_t
7d12e780 2460pcnet32_interrupt(int irq, void *dev_id)
1da177e4 2461{
4a5e8e29
JG		 2462 struct net_device *dev = dev_id;
2463 struct pcnet32_private *lp;
2464 unsigned long ioaddr;
5c99346a 2465 u16 csr0;
4a5e8e29 2466 int boguscnt = max_interrupt_work;
4a5e8e29 2467
4a5e8e29 2468 ioaddr = dev->base_addr;
1e56a4b4 2469 lp = netdev_priv(dev);
1da177e4 2470
4a5e8e29
JG		 2471 spin_lock(&lp->lock);
2472
3904c324
DF		 2473 csr0 = lp->a.read_csr(ioaddr, CSR0);
2474 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
9e3f8063 2475 if (csr0 == 0xffff)
4a5e8e29 2476 break; /* PCMCIA remove happened */
4a5e8e29 2477 /* Acknowledge all of the current interrupt sources ASAP. */
3904c324 2478 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
4a5e8e29 2479
13ff83b9
JP		 2480 netif_printk(lp, intr, KERN_DEBUG, dev,
2481 "interrupt csr0=%#2.2x new csr=%#2.2x\n",
2482 csr0, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29 2483
4a5e8e29
JG		 2484 /* Log misc errors. */
2485 if (csr0 & 0x4000)
4f1e5ba0 2486 dev->stats.tx_errors++; /* Tx babble. */
4a5e8e29
JG		 2487 if (csr0 & 0x1000) {
2488 /*
3904c324
DF		 2489 * This happens when our receive ring is full. This
2490 * shouldn't be a problem as we will see normal rx
2491 * interrupts for the frames in the receive ring. But
2492 * there are some PCI chipsets (I can reproduce this
2493 * on SP3G with Intel saturn chipset) which have
2494 * sometimes problems and will fill up the receive
2495 * ring with error descriptors. In this situation we
2496 * don't get a rx interrupt, but a missed frame
7de745e5 2497 * interrupt sooner or later.
4a5e8e29 2498 */
4f1e5ba0 2499 dev->stats.rx_errors++; /* Missed a Rx frame. */
4a5e8e29
JG		 2500 }
2501 if (csr0 & 0x0800) {
13ff83b9
JP		 2502 netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n",
2503 csr0);
4a5e8e29 2504 /* unlike for the lance, there is no restart needed */
1da177e4 2505 }
288379f0 2506 if (napi_schedule_prep(&lp->napi)) {
7de745e5
DF		 2507 u16 val;
2508 /* set interrupt masks */
2509 val = lp->a.read_csr(ioaddr, CSR3);
2510 val |= 0x5f00;
2511 lp->a.write_csr(ioaddr, CSR3, val);
ce105a08 2512
288379f0 2513 __napi_schedule(&lp->napi);
7de745e5
DF		 2514 break;
2515 }
3904c324 2516 csr0 = lp->a.read_csr(ioaddr, CSR0);
4a5e8e29
JG		 2517 }
2518
13ff83b9
JP		 2519 netif_printk(lp, intr, KERN_DEBUG, dev,
2520 "exiting interrupt, csr0=%#4.4x\n",
2521 lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2522
2523 spin_unlock(&lp->lock);
2524
2525 return IRQ_HANDLED;
1da177e4
LT		 2526}
2527
4a5e8e29 2528static int pcnet32_close(struct net_device *dev)
1da177e4 2529{
4a5e8e29 2530 unsigned long ioaddr = dev->base_addr;
1e56a4b4 2531 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2532 unsigned long flags;
1da177e4 2533
4a5e8e29 2534 del_timer_sync(&lp->watchdog_timer);
1da177e4 2535
4a5e8e29 2536 netif_stop_queue(dev);
bea3348e 2537 napi_disable(&lp->napi);
1da177e4 2538
4a5e8e29 2539 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2540
4f1e5ba0 2541 dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
1da177e4 2542
13ff83b9
JP		 2543 netif_printk(lp, ifdown, KERN_DEBUG, dev,
2544 "Shutting down ethercard, status was %2.2x\n",
2545 lp->a.read_csr(ioaddr, CSR0));
1da177e4 2546
4a5e8e29 2547 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
b368a3fb 2548 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
1da177e4 2549
4a5e8e29
JG		 2550 /*
2551 * Switch back to 16bit mode to avoid problems with dumb
2552 * DOS packet driver after a warm reboot
2553 */
2554 lp->a.write_bcr(ioaddr, 20, 4);
1da177e4 2555
4a5e8e29 2556 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2557
4a5e8e29 2558 free_irq(dev->irq, dev);
1da177e4 2559
4a5e8e29 2560 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2561
ac5bfe40
DF		 2562 pcnet32_purge_rx_ring(dev);
2563 pcnet32_purge_tx_ring(dev);
1da177e4 2564
4a5e8e29 2565 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2566
4a5e8e29 2567 return 0;
1da177e4
LT		 2568}
2569
4a5e8e29 2570static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
1da177e4 2571{
1e56a4b4 2572 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2573 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2574 unsigned long flags;
2575
2576 spin_lock_irqsave(&lp->lock, flags);
4f1e5ba0 2577 dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
4a5e8e29
JG		 2578 spin_unlock_irqrestore(&lp->lock, flags);
2579
4f1e5ba0 2580 return &dev->stats;
1da177e4
LT		 2581}
2582
2583/* taken from the sunlance driver, which it took from the depca driver */
4a5e8e29 2584static void pcnet32_load_multicast(struct net_device *dev)
1da177e4 2585{
1e56a4b4 2586 struct pcnet32_private *lp = netdev_priv(dev);
6ecb7667 2587 volatile struct pcnet32_init_block *ib = lp->init_block;
3e33545b 2588 volatile __le16 *mcast_table = (__le16 *)ib->filter;
22bedad3 2589 struct netdev_hw_addr *ha;
df27f4a6 2590 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2591 char *addrs;
2592 int i;
2593 u32 crc;
2594
2595 /* set all multicast bits */
2596 if (dev->flags & IFF_ALLMULTI) {
3e33545b
AV		 2597 ib->filter[0] = cpu_to_le32(~0U);
2598 ib->filter[1] = cpu_to_le32(~0U);
df27f4a6
DF		 2599 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2600 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2601 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2602 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
4a5e8e29
JG		 2603 return;
2604 }
2605 /* clear the multicast filter */
2606 ib->filter[0] = 0;
2607 ib->filter[1] = 0;
2608
2609 /* Add addresses */
22bedad3
JP		 2610 netdev_for_each_mc_addr(ha, dev) {
2611 addrs = ha->addr;
4a5e8e29
JG		 2612
2613 /* multicast address? */
2614 if (!(*addrs & 1))
2615 continue;
2616
2617 crc = ether_crc_le(6, addrs);
2618 crc = crc >> 26;
3e33545b 2619 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
4a5e8e29 2620 }
df27f4a6
DF		 2621 for (i = 0; i < 4; i++)
2622 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2623 le16_to_cpu(mcast_table[i]));
1da177e4
LT		 2624}
2625
1da177e4
LT		 2626/*
2627 * Set or clear the multicast filter for this adaptor.
2628 */
2629static void pcnet32_set_multicast_list(struct net_device *dev)
2630{
4a5e8e29 2631 unsigned long ioaddr = dev->base_addr, flags;
1e56a4b4 2632 struct pcnet32_private *lp = netdev_priv(dev);
df27f4a6 2633 int csr15, suspended;
4a5e8e29
JG		 2634
2635 spin_lock_irqsave(&lp->lock, flags);
df27f4a6
DF		 2636 suspended = pcnet32_suspend(dev, &flags, 0);
2637 csr15 = lp->a.read_csr(ioaddr, CSR15);
4a5e8e29
JG		 2638 if (dev->flags & IFF_PROMISC) {
2639 /* Log any net taps. */
13ff83b9 2640 netif_info(lp, hw, dev, "Promiscuous mode enabled\n");
6ecb7667 2641 lp->init_block->mode =
3e33545b 2642 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
4a5e8e29 2643 7);
df27f4a6 2644 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
4a5e8e29 2645 } else {
6ecb7667 2646 lp->init_block->mode =
3e33545b 2647 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
df27f4a6 2648 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
4a5e8e29
JG		 2649 pcnet32_load_multicast(dev);
2650 }
2651
df27f4a6
DF		 2652 if (suspended) {
2653 int csr5;
2654 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2655 csr5 = lp->a.read_csr(ioaddr, CSR5);
2656 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
b368a3fb 2657 } else {
df27f4a6
DF		 2658 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2659 pcnet32_restart(dev, CSR0_NORMAL);
2660 netif_wake_queue(dev);
2661 }
4a5e8e29
JG		 2662
2663 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 2664}
2665
2666/* This routine assumes that the lp->lock is held */
2667static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2668{
1e56a4b4 2669 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2670 unsigned long ioaddr = dev->base_addr;
2671 u16 val_out;
1da177e4 2672
4a5e8e29
JG		 2673 if (!lp->mii)
2674 return 0;
1da177e4 2675
4a5e8e29
JG		 2676 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2677 val_out = lp->a.read_bcr(ioaddr, 34);
1da177e4 2678
4a5e8e29 2679 return val_out;
1da177e4
LT		 2680}
2681
2682/* This routine assumes that the lp->lock is held */
2683static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2684{
1e56a4b4 2685 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2686 unsigned long ioaddr = dev->base_addr;
1da177e4 2687
4a5e8e29
JG		 2688 if (!lp->mii)
2689 return;
1da177e4 2690
4a5e8e29
JG		 2691 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2692 lp->a.write_bcr(ioaddr, 34, val);
1da177e4
LT		 2693}
2694
2695static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2696{
1e56a4b4 2697 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2698 int rc;
2699 unsigned long flags;
1da177e4 2700
4a5e8e29
JG		 2701 /* SIOC[GS]MIIxxx ioctls */
2702 if (lp->mii) {
2703 spin_lock_irqsave(&lp->lock, flags);
2704 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2705 spin_unlock_irqrestore(&lp->lock, flags);
2706 } else {
2707 rc = -EOPNOTSUPP;
2708 }
1da177e4 2709
4a5e8e29 2710 return rc;
1da177e4
LT		 2711}
2712
ac62ef04
DF		 2713static int pcnet32_check_otherphy(struct net_device *dev)
2714{
1e56a4b4 2715 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2716 struct mii_if_info mii = lp->mii_if;
2717 u16 bmcr;
2718 int i;
ac62ef04 2719
4a5e8e29
JG		 2720 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2721 if (i == lp->mii_if.phy_id)
2722 continue; /* skip active phy */
2723 if (lp->phymask & (1 << i)) {
2724 mii.phy_id = i;
2725 if (mii_link_ok(&mii)) {
2726 /* found PHY with active link */
13ff83b9
JP		 2727 netif_info(lp, link, dev, "Using PHY number %d\n",
2728 i);
4a5e8e29
JG		 2729
2730 /* isolate inactive phy */
2731 bmcr =
2732 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2733 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2734 bmcr | BMCR_ISOLATE);
2735
2736 /* de-isolate new phy */
2737 bmcr = mdio_read(dev, i, MII_BMCR);
2738 mdio_write(dev, i, MII_BMCR,
2739 bmcr & ~BMCR_ISOLATE);
2740
2741 /* set new phy address */
2742 lp->mii_if.phy_id = i;
2743 return 1;
2744 }
2745 }
ac62ef04 2746 }
4a5e8e29 2747 return 0;
ac62ef04
DF		 2748}
2749
2750/*
2751 * Show the status of the media. Similar to mii_check_media however it
2752 * correctly shows the link speed for all (tested) pcnet32 variants.
2753 * Devices with no mii just report link state without speed.
2754 *
2755 * Caller is assumed to hold and release the lp->lock.
2756 */
2757
2758static void pcnet32_check_media(struct net_device *dev, int verbose)
2759{
1e56a4b4 2760 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2761 int curr_link;
2762 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2763 u32 bcr9;
2764
ac62ef04 2765 if (lp->mii) {
4a5e8e29 2766 curr_link = mii_link_ok(&lp->mii_if);
ac62ef04 2767 } else {
4a5e8e29
JG		 2768 ulong ioaddr = dev->base_addr; /* card base I/O address */
2769 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2770 }
2771 if (!curr_link) {
2772 if (prev_link || verbose) {
2773 netif_carrier_off(dev);
13ff83b9 2774 netif_info(lp, link, dev, "link down\n");
4a5e8e29
JG		 2775 }
2776 if (lp->phycount > 1) {
2777 curr_link = pcnet32_check_otherphy(dev);
2778 prev_link = 0;
2779 }
2780 } else if (verbose || !prev_link) {
2781 netif_carrier_on(dev);
2782 if (lp->mii) {
2783 if (netif_msg_link(lp)) {
2784 struct ethtool_cmd ecmd;
2785 mii_ethtool_gset(&lp->mii_if, &ecmd);
13ff83b9
JP		 2786 netdev_info(dev, "link up, %sMbps, %s-duplex\n",
2787 (ecmd.speed == SPEED_100)
2788 ? "100" : "10",
2789 (ecmd.duplex == DUPLEX_FULL)
2790 ? "full" : "half");
4a5e8e29
JG		 2791 }
2792 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2793 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2794 if (lp->mii_if.full_duplex)
2795 bcr9 |= (1 << 0);
2796 else
2797 bcr9 &= ~(1 << 0);
2798 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2799 }
2800 } else {
13ff83b9 2801 netif_info(lp, link, dev, "link up\n");
4a5e8e29 2802 }
ac62ef04 2803 }
ac62ef04
DF		 2804}
2805
2806/*
2807 * Check for loss of link and link establishment.
2808 * Can not use mii_check_media because it does nothing if mode is forced.
2809 */
2810
1da177e4
LT		 2811static void pcnet32_watchdog(struct net_device *dev)
2812{
1e56a4b4 2813 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2814 unsigned long flags;
1da177e4 2815
4a5e8e29
JG		 2816 /* Print the link status if it has changed */
2817 spin_lock_irqsave(&lp->lock, flags);
2818 pcnet32_check_media(dev, 0);
2819 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2820
283a21d3 2821 mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT));
1da177e4
LT		 2822}
2823
917270c6
DF		 2824static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2825{
2826 struct net_device *dev = pci_get_drvdata(pdev);
2827
2828 if (netif_running(dev)) {
2829 netif_device_detach(dev);
2830 pcnet32_close(dev);
2831 }
2832 pci_save_state(pdev);
2833 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2834 return 0;
2835}
2836
2837static int pcnet32_pm_resume(struct pci_dev *pdev)
2838{
2839 struct net_device *dev = pci_get_drvdata(pdev);
2840
2841 pci_set_power_state(pdev, PCI_D0);
2842 pci_restore_state(pdev);
2843
2844 if (netif_running(dev)) {
2845 pcnet32_open(dev);
2846 netif_device_attach(dev);
2847 }
2848 return 0;
2849}
2850
1da177e4
LT		 2851static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2852{
4a5e8e29
JG		 2853 struct net_device *dev = pci_get_drvdata(pdev);
2854
2855 if (dev) {
1e56a4b4 2856 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2857
2858 unregister_netdev(dev);
2859 pcnet32_free_ring(dev);
2860 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
7d2e3cb7 2861 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 2862 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 2863 free_netdev(dev);
2864 pci_disable_device(pdev);
2865 pci_set_drvdata(pdev, NULL);
2866 }
1da177e4
LT		 2867}
2868
2869static struct pci_driver pcnet32_driver = {
4a5e8e29
JG		 2870 .name = DRV_NAME,
2871 .probe = pcnet32_probe_pci,
2872 .remove = __devexit_p(pcnet32_remove_one),
2873 .id_table = pcnet32_pci_tbl,
917270c6
DF		 2874 .suspend = pcnet32_pm_suspend,
2875 .resume = pcnet32_pm_resume,
1da177e4
LT		 2876};
2877
2878/* An additional parameter that may be passed in... */
2879static int debug = -1;
2880static int tx_start_pt = -1;
2881static int pcnet32_have_pci;
2882
2883module_param(debug, int, 0);
2884MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2885module_param(max_interrupt_work, int, 0);
4a5e8e29
JG		 2886MODULE_PARM_DESC(max_interrupt_work,
2887 DRV_NAME " maximum events handled per interrupt");
1da177e4 2888module_param(rx_copybreak, int, 0);
4a5e8e29
JG		 2889MODULE_PARM_DESC(rx_copybreak,
2890 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 2891module_param(tx_start_pt, int, 0);
2892MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2893module_param(pcnet32vlb, int, 0);
2894MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2895module_param_array(options, int, NULL, 0);
2896MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2897module_param_array(full_duplex, int, NULL, 0);
2898MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2899/* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2900module_param_array(homepna, int, NULL, 0);
4a5e8e29
JG		 2901MODULE_PARM_DESC(homepna,
2902 DRV_NAME
2903 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
1da177e4
LT		 2904
2905MODULE_AUTHOR("Thomas Bogendoerfer");
2906MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2907MODULE_LICENSE("GPL");
2908
2909#define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2910
2911static int __init pcnet32_init_module(void)
2912{
13ff83b9 2913 pr_info("%s", version);
1da177e4 2914
4a5e8e29 2915 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
1da177e4 2916
4a5e8e29
JG		 2917 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2918 tx_start = tx_start_pt;
1da177e4 2919
4a5e8e29 2920 /* find the PCI devices */
29917620 2921 if (!pci_register_driver(&pcnet32_driver))
4a5e8e29 2922 pcnet32_have_pci = 1;
1da177e4 2923
4a5e8e29
JG		 2924 /* should we find any remaining VLbus devices ? */
2925 if (pcnet32vlb)
dcaf9769 2926 pcnet32_probe_vlbus(pcnet32_portlist);
1da177e4 2927
4a5e8e29 2928 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
13ff83b9 2929 pr_info("%d cards_found\n", cards_found);
1da177e4 2930
4a5e8e29 2931 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
1da177e4
LT		 2932}
2933
2934static void __exit pcnet32_cleanup_module(void)
2935{
4a5e8e29
JG		 2936 struct net_device *next_dev;
2937
2938 while (pcnet32_dev) {
1e56a4b4 2939 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
4a5e8e29
JG		 2940 next_dev = lp->next;
2941 unregister_netdev(pcnet32_dev);
2942 pcnet32_free_ring(pcnet32_dev);
2943 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
7d2e3cb7 2944 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 2945 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 2946 free_netdev(pcnet32_dev);
2947 pcnet32_dev = next_dev;
2948 }
1da177e4 2949
4a5e8e29
JG		 2950 if (pcnet32_have_pci)
2951 pci_unregister_driver(&pcnet32_driver);
1da177e4
LT		 2952}
2953
2954module_init(pcnet32_init_module);
2955module_exit(pcnet32_cleanup_module);
2956
2957/*
2958 * Local variables:
2959 * c-indent-level: 4
2960 * tab-width: 8
2961 * End:
2962 */
Clone of davem's net-next-2.6 tree