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tg3: Add support code around kernel interrupt API
[net-next-2.6.git] / drivers / net / pcnet32.c
CommitLineData
1da177e4
LT		 1/* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2/*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15/**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24#define DRV_NAME "pcnet32"
01935d7d
DF		 25#define DRV_VERSION "1.35"
26#define DRV_RELDATE "21.Apr.2008"
1da177e4
LT		 27#define PFX DRV_NAME ": "
28
4a5e8e29
JG		 29static const char *const version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
1da177e4
LT		 31
32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/string.h>
35#include <linux/errno.h>
36#include <linux/ioport.h>
37#include <linux/slab.h>
38#include <linux/interrupt.h>
39#include <linux/pci.h>
40#include <linux/delay.h>
41#include <linux/init.h>
42#include <linux/ethtool.h>
43#include <linux/mii.h>
44#include <linux/crc32.h>
45#include <linux/netdevice.h>
46#include <linux/etherdevice.h>
47#include <linux/skbuff.h>
48#include <linux/spinlock.h>
49#include <linux/moduleparam.h>
50#include <linux/bitops.h>
51
52#include <asm/dma.h>
53#include <asm/io.h>
54#include <asm/uaccess.h>
55#include <asm/irq.h>
56
57/*
58 * PCI device identifiers for "new style" Linux PCI Device Drivers
59 */
60static struct pci_device_id pcnet32_pci_tbl[] = {
f2622a2b
DF		 61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
4a5e8e29
JG		 63
64 /*
65 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
66 * the incorrect vendor id.
67 */
f2622a2b
DF		 68 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
69 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
4a5e8e29
JG		 70
71 { } /* terminate list */
1da177e4
LT		 72};
73
4a5e8e29 74MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
1da177e4
LT		 75
76static int cards_found;
77
78/*
79 * VLB I/O addresses
80 */
81static unsigned int pcnet32_portlist[] __initdata =
4a5e8e29 82 { 0x300, 0x320, 0x340, 0x360, 0 };
1da177e4
LT		 83
84static int pcnet32_debug = 0;
4a5e8e29
JG		 85static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
86static int pcnet32vlb; /* check for VLB cards ? */
1da177e4
LT		 87
88static struct net_device *pcnet32_dev;
89
90static int max_interrupt_work = 2;
91static int rx_copybreak = 200;
92
93#define PCNET32_PORT_AUI 0x00
94#define PCNET32_PORT_10BT 0x01
95#define PCNET32_PORT_GPSI 0x02
96#define PCNET32_PORT_MII 0x03
97
98#define PCNET32_PORT_PORTSEL 0x03
99#define PCNET32_PORT_ASEL 0x04
100#define PCNET32_PORT_100 0x40
101#define PCNET32_PORT_FD 0x80
102
103#define PCNET32_DMA_MASK 0xffffffff
104
105#define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
106#define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
107
108/*
109 * table to translate option values from tulip
110 * to internal options
111 */
f71e1309 112static const unsigned char options_mapping[] = {
4a5e8e29
JG		 113 PCNET32_PORT_ASEL, /* 0 Auto-select */
114 PCNET32_PORT_AUI, /* 1 BNC/AUI */
115 PCNET32_PORT_AUI, /* 2 AUI/BNC */
116 PCNET32_PORT_ASEL, /* 3 not supported */
117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
118 PCNET32_PORT_ASEL, /* 5 not supported */
119 PCNET32_PORT_ASEL, /* 6 not supported */
120 PCNET32_PORT_ASEL, /* 7 not supported */
121 PCNET32_PORT_ASEL, /* 8 not supported */
122 PCNET32_PORT_MII, /* 9 MII 10baseT */
123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
124 PCNET32_PORT_MII, /* 11 MII (autosel) */
125 PCNET32_PORT_10BT, /* 12 10BaseT */
126 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
127 /* 14 MII 100BaseTx-FD */
128 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
129 PCNET32_PORT_ASEL /* 15 not supported */
1da177e4
LT		 130};
131
132static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
4a5e8e29 133 "Loopback test (offline)"
1da177e4 134};
4a5e8e29 135
4c3616cd 136#define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test)
1da177e4 137
ac62ef04 138#define PCNET32_NUM_REGS 136
1da177e4 139
4a5e8e29 140#define MAX_UNITS 8 /* More are supported, limit only on options */
1da177e4
LT		 141static int options[MAX_UNITS];
142static int full_duplex[MAX_UNITS];
143static int homepna[MAX_UNITS];
144
145/*
146 * Theory of Operation
147 *
148 * This driver uses the same software structure as the normal lance
149 * driver. So look for a verbose description in lance.c. The differences
150 * to the normal lance driver is the use of the 32bit mode of PCnet32
151 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
152 * 16MB limitation and we don't need bounce buffers.
153 */
154
1da177e4
LT		 155/*
156 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
157 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
158 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
159 */
160#ifndef PCNET32_LOG_TX_BUFFERS
eabf0415
HWL		 161#define PCNET32_LOG_TX_BUFFERS 4
162#define PCNET32_LOG_RX_BUFFERS 5
163#define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
164#define PCNET32_LOG_MAX_RX_BUFFERS 9
1da177e4
LT		 165#endif
166
167#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
eabf0415 168#define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
1da177e4
LT		 169
170#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
eabf0415 171#define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
1da177e4 172
232c5640
DF		 173#define PKT_BUF_SKB 1544
174/* actual buffer length after being aligned */
175#define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN)
176/* chip wants twos complement of the (aligned) buffer length */
177#define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB)
1da177e4
LT		 178
179/* Offsets from base I/O address. */
180#define PCNET32_WIO_RDP 0x10
181#define PCNET32_WIO_RAP 0x12
182#define PCNET32_WIO_RESET 0x14
183#define PCNET32_WIO_BDP 0x16
184
185#define PCNET32_DWIO_RDP 0x10
186#define PCNET32_DWIO_RAP 0x14
187#define PCNET32_DWIO_RESET 0x18
188#define PCNET32_DWIO_BDP 0x1C
189
190#define PCNET32_TOTAL_SIZE 0x20
191
06c87850
DF		 192#define CSR0 0
193#define CSR0_INIT 0x1
194#define CSR0_START 0x2
195#define CSR0_STOP 0x4
196#define CSR0_TXPOLL 0x8
197#define CSR0_INTEN 0x40
198#define CSR0_IDON 0x0100
199#define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
200#define PCNET32_INIT_LOW 1
201#define PCNET32_INIT_HIGH 2
202#define CSR3 3
203#define CSR4 4
204#define CSR5 5
205#define CSR5_SUSPEND 0x0001
206#define CSR15 15
207#define PCNET32_MC_FILTER 8
208
8d916266
DF		 209#define PCNET32_79C970A 0x2621
210
1da177e4
LT		 211/* The PCNET32 Rx and Tx ring descriptors. */
212struct pcnet32_rx_head {
3e33545b
AV		 213 __le32 base;
214 __le16 buf_length; /* two`s complement of length */
215 __le16 status;
216 __le32 msg_length;
217 __le32 reserved;
1da177e4
LT		 218};
219
220struct pcnet32_tx_head {
3e33545b
AV		 221 __le32 base;
222 __le16 length; /* two`s complement of length */
223 __le16 status;
224 __le32 misc;
225 __le32 reserved;
1da177e4
LT		 226};
227
228/* The PCNET32 32-Bit initialization block, described in databook. */
229struct pcnet32_init_block {
3e33545b
AV		 230 __le16 mode;
231 __le16 tlen_rlen;
0b5bf225 232 u8 phys_addr[6];
3e33545b
AV		 233 __le16 reserved;
234 __le32 filter[2];
4a5e8e29 235 /* Receive and transmit ring base, along with extra bits. */
3e33545b
AV		 236 __le32 rx_ring;
237 __le32 tx_ring;
1da177e4
LT		 238};
239
240/* PCnet32 access functions */
241struct pcnet32_access {
4a5e8e29
JG		 242 u16 (*read_csr) (unsigned long, int);
243 void (*write_csr) (unsigned long, int, u16);
244 u16 (*read_bcr) (unsigned long, int);
245 void (*write_bcr) (unsigned long, int, u16);
246 u16 (*read_rap) (unsigned long);
247 void (*write_rap) (unsigned long, u16);
248 void (*reset) (unsigned long);
1da177e4
LT		 249};
250
251/*
76209926
HWL		 252 * The first field of pcnet32_private is read by the ethernet device
253 * so the structure should be allocated using pci_alloc_consistent().
1da177e4
LT		 254 */
255struct pcnet32_private {
6ecb7667 256 struct pcnet32_init_block *init_block;
4a5e8e29 257 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
0b5bf225
JG		 258 struct pcnet32_rx_head *rx_ring;
259 struct pcnet32_tx_head *tx_ring;
6ecb7667
DF		 260 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,
261 returned by pci_alloc_consistent */
0b5bf225
JG		 262 struct pci_dev *pci_dev;
263 const char *name;
4a5e8e29 264 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
0b5bf225
JG		 265 struct sk_buff **tx_skbuff;
266 struct sk_buff **rx_skbuff;
267 dma_addr_t *tx_dma_addr;
268 dma_addr_t *rx_dma_addr;
269 struct pcnet32_access a;
270 spinlock_t lock; /* Guard lock */
271 unsigned int cur_rx, cur_tx; /* The next free ring entry */
272 unsigned int rx_ring_size; /* current rx ring size */
273 unsigned int tx_ring_size; /* current tx ring size */
274 unsigned int rx_mod_mask; /* rx ring modular mask */
275 unsigned int tx_mod_mask; /* tx ring modular mask */
276 unsigned short rx_len_bits;
277 unsigned short tx_len_bits;
278 dma_addr_t rx_ring_dma_addr;
279 dma_addr_t tx_ring_dma_addr;
280 unsigned int dirty_rx, /* ring entries to be freed. */
281 dirty_tx;
282
bea3348e
SH		 283 struct net_device *dev;
284 struct napi_struct napi;
0b5bf225
JG		 285 char tx_full;
286 char phycount; /* number of phys found */
287 int options;
288 unsigned int shared_irq:1, /* shared irq possible */
289 dxsuflo:1, /* disable transmit stop on uflo */
290 mii:1; /* mii port available */
291 struct net_device *next;
292 struct mii_if_info mii_if;
293 struct timer_list watchdog_timer;
294 struct timer_list blink_timer;
295 u32 msg_enable; /* debug message level */
4a5e8e29
JG		 296
297 /* each bit indicates an available PHY */
0b5bf225 298 u32 phymask;
8d916266 299 unsigned short chip_version; /* which variant this is */
1da177e4
LT		 300};
301
4a5e8e29
JG		 302static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
303static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
304static int pcnet32_open(struct net_device *);
305static int pcnet32_init_ring(struct net_device *);
61357325
SH		 306static netdev_tx_t pcnet32_start_xmit(struct sk_buff *,
307 struct net_device *);
4a5e8e29 308static void pcnet32_tx_timeout(struct net_device *dev);
7d12e780 309static irqreturn_t pcnet32_interrupt(int, void *);
4a5e8e29 310static int pcnet32_close(struct net_device *);
1da177e4
LT		 311static struct net_device_stats *pcnet32_get_stats(struct net_device *);
312static void pcnet32_load_multicast(struct net_device *dev);
313static void pcnet32_set_multicast_list(struct net_device *);
4a5e8e29 314static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
1da177e4
LT		 315static void pcnet32_watchdog(struct net_device *);
316static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
4a5e8e29
JG		 317static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
318 int val);
1da177e4
LT		 319static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
320static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29
JG		 321 struct ethtool_test *eth_test, u64 * data);
322static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
1da177e4
LT		 323static int pcnet32_phys_id(struct net_device *dev, u32 data);
324static void pcnet32_led_blink_callback(struct net_device *dev);
325static int pcnet32_get_regs_len(struct net_device *dev);
326static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 327 void *ptr);
1bcd3153 328static void pcnet32_purge_tx_ring(struct net_device *dev);
b166cfba 329static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
eabf0415 330static void pcnet32_free_ring(struct net_device *dev);
ac62ef04 331static void pcnet32_check_media(struct net_device *dev, int verbose);
eabf0415 332
4a5e8e29 333static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
1da177e4 334{
4a5e8e29
JG		 335 outw(index, addr + PCNET32_WIO_RAP);
336 return inw(addr + PCNET32_WIO_RDP);
1da177e4
LT		 337}
338
4a5e8e29 339static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 340{
4a5e8e29
JG		 341 outw(index, addr + PCNET32_WIO_RAP);
342 outw(val, addr + PCNET32_WIO_RDP);
1da177e4
LT		 343}
344
4a5e8e29 345static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
1da177e4 346{
4a5e8e29
JG		 347 outw(index, addr + PCNET32_WIO_RAP);
348 return inw(addr + PCNET32_WIO_BDP);
1da177e4
LT		 349}
350
4a5e8e29 351static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 352{
4a5e8e29
JG		 353 outw(index, addr + PCNET32_WIO_RAP);
354 outw(val, addr + PCNET32_WIO_BDP);
1da177e4
LT		 355}
356
4a5e8e29 357static u16 pcnet32_wio_read_rap(unsigned long addr)
1da177e4 358{
4a5e8e29 359 return inw(addr + PCNET32_WIO_RAP);
1da177e4
LT		 360}
361
4a5e8e29 362static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
1da177e4 363{
4a5e8e29 364 outw(val, addr + PCNET32_WIO_RAP);
1da177e4
LT		 365}
366
4a5e8e29 367static void pcnet32_wio_reset(unsigned long addr)
1da177e4 368{
4a5e8e29 369 inw(addr + PCNET32_WIO_RESET);
1da177e4
LT		 370}
371
4a5e8e29 372static int pcnet32_wio_check(unsigned long addr)
1da177e4 373{
4a5e8e29
JG		 374 outw(88, addr + PCNET32_WIO_RAP);
375 return (inw(addr + PCNET32_WIO_RAP) == 88);
1da177e4
LT		 376}
377
378static struct pcnet32_access pcnet32_wio = {
4a5e8e29
JG		 379 .read_csr = pcnet32_wio_read_csr,
380 .write_csr = pcnet32_wio_write_csr,
381 .read_bcr = pcnet32_wio_read_bcr,
382 .write_bcr = pcnet32_wio_write_bcr,
383 .read_rap = pcnet32_wio_read_rap,
384 .write_rap = pcnet32_wio_write_rap,
385 .reset = pcnet32_wio_reset
1da177e4
LT		 386};
387
4a5e8e29 388static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
1da177e4 389{
4a5e8e29
JG		 390 outl(index, addr + PCNET32_DWIO_RAP);
391 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
1da177e4
LT		 392}
393
4a5e8e29 394static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 395{
4a5e8e29
JG		 396 outl(index, addr + PCNET32_DWIO_RAP);
397 outl(val, addr + PCNET32_DWIO_RDP);
1da177e4
LT		 398}
399
4a5e8e29 400static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
1da177e4 401{
4a5e8e29
JG		 402 outl(index, addr + PCNET32_DWIO_RAP);
403 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
1da177e4
LT		 404}
405
4a5e8e29 406static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 407{
4a5e8e29
JG		 408 outl(index, addr + PCNET32_DWIO_RAP);
409 outl(val, addr + PCNET32_DWIO_BDP);
1da177e4
LT		 410}
411
4a5e8e29 412static u16 pcnet32_dwio_read_rap(unsigned long addr)
1da177e4 413{
4a5e8e29 414 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
1da177e4
LT		 415}
416
4a5e8e29 417static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
1da177e4 418{
4a5e8e29 419 outl(val, addr + PCNET32_DWIO_RAP);
1da177e4
LT		 420}
421
4a5e8e29 422static void pcnet32_dwio_reset(unsigned long addr)
1da177e4 423{
4a5e8e29 424 inl(addr + PCNET32_DWIO_RESET);
1da177e4
LT		 425}
426
4a5e8e29 427static int pcnet32_dwio_check(unsigned long addr)
1da177e4 428{
4a5e8e29
JG		 429 outl(88, addr + PCNET32_DWIO_RAP);
430 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
1da177e4
LT		 431}
432
433static struct pcnet32_access pcnet32_dwio = {
4a5e8e29
JG		 434 .read_csr = pcnet32_dwio_read_csr,
435 .write_csr = pcnet32_dwio_write_csr,
436 .read_bcr = pcnet32_dwio_read_bcr,
437 .write_bcr = pcnet32_dwio_write_bcr,
438 .read_rap = pcnet32_dwio_read_rap,
439 .write_rap = pcnet32_dwio_write_rap,
440 .reset = pcnet32_dwio_reset
1da177e4
LT		 441};
442
06c87850
DF		 443static void pcnet32_netif_stop(struct net_device *dev)
444{
bea3348e 445 struct pcnet32_private *lp = netdev_priv(dev);
01935d7d 446
06c87850 447 dev->trans_start = jiffies;
bea3348e 448 napi_disable(&lp->napi);
06c87850
DF		 449 netif_tx_disable(dev);
450}
451
452static void pcnet32_netif_start(struct net_device *dev)
453{
bea3348e 454 struct pcnet32_private *lp = netdev_priv(dev);
d1d08d12
DM		 455 ulong ioaddr = dev->base_addr;
456 u16 val;
01935d7d 457
06c87850 458 netif_wake_queue(dev);
d1d08d12
DM		 459 val = lp->a.read_csr(ioaddr, CSR3);
460 val &= 0x00ff;
461 lp->a.write_csr(ioaddr, CSR3, val);
bea3348e 462 napi_enable(&lp->napi);
06c87850
DF		 463}
464
465/*
466 * Allocate space for the new sized tx ring.
467 * Free old resources
468 * Save new resources.
469 * Any failure keeps old resources.
470 * Must be called with lp->lock held.
471 */
472static void pcnet32_realloc_tx_ring(struct net_device *dev,
473 struct pcnet32_private *lp,
474 unsigned int size)
475{
476 dma_addr_t new_ring_dma_addr;
477 dma_addr_t *new_dma_addr_list;
478 struct pcnet32_tx_head *new_tx_ring;
479 struct sk_buff **new_skb_list;
480
481 pcnet32_purge_tx_ring(dev);
482
483 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
484 sizeof(struct pcnet32_tx_head) *
485 (1 << size),
486 &new_ring_dma_addr);
487 if (new_tx_ring == NULL) {
488 if (netif_msg_drv(lp))
ad361c98 489 printk(KERN_ERR
06c87850
DF		 490 "%s: Consistent memory allocation failed.\n",
491 dev->name);
492 return;
493 }
494 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
495
496 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
497 GFP_ATOMIC);
498 if (!new_dma_addr_list) {
499 if (netif_msg_drv(lp))
ad361c98 500 printk(KERN_ERR
06c87850
DF		 501 "%s: Memory allocation failed.\n", dev->name);
502 goto free_new_tx_ring;
503 }
504
505 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
506 GFP_ATOMIC);
507 if (!new_skb_list) {
508 if (netif_msg_drv(lp))
ad361c98 509 printk(KERN_ERR
06c87850
DF		 510 "%s: Memory allocation failed.\n", dev->name);
511 goto free_new_lists;
512 }
513
514 kfree(lp->tx_skbuff);
515 kfree(lp->tx_dma_addr);
516 pci_free_consistent(lp->pci_dev,
517 sizeof(struct pcnet32_tx_head) *
518 lp->tx_ring_size, lp->tx_ring,
519 lp->tx_ring_dma_addr);
520
521 lp->tx_ring_size = (1 << size);
522 lp->tx_mod_mask = lp->tx_ring_size - 1;
523 lp->tx_len_bits = (size << 12);
524 lp->tx_ring = new_tx_ring;
525 lp->tx_ring_dma_addr = new_ring_dma_addr;
526 lp->tx_dma_addr = new_dma_addr_list;
527 lp->tx_skbuff = new_skb_list;
528 return;
529
530 free_new_lists:
531 kfree(new_dma_addr_list);
532 free_new_tx_ring:
533 pci_free_consistent(lp->pci_dev,
534 sizeof(struct pcnet32_tx_head) *
535 (1 << size),
536 new_tx_ring,
537 new_ring_dma_addr);
538 return;
539}
540
541/*
542 * Allocate space for the new sized rx ring.
543 * Re-use old receive buffers.
544 * alloc extra buffers
545 * free unneeded buffers
546 * free unneeded buffers
547 * Save new resources.
548 * Any failure keeps old resources.
549 * Must be called with lp->lock held.
550 */
551static void pcnet32_realloc_rx_ring(struct net_device *dev,
552 struct pcnet32_private *lp,
553 unsigned int size)
554{
555 dma_addr_t new_ring_dma_addr;
556 dma_addr_t *new_dma_addr_list;
557 struct pcnet32_rx_head *new_rx_ring;
558 struct sk_buff **new_skb_list;
559 int new, overlap;
560
561 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
562 sizeof(struct pcnet32_rx_head) *
563 (1 << size),
564 &new_ring_dma_addr);
565 if (new_rx_ring == NULL) {
566 if (netif_msg_drv(lp))
ad361c98 567 printk(KERN_ERR
06c87850
DF		 568 "%s: Consistent memory allocation failed.\n",
569 dev->name);
570 return;
571 }
572 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
573
574 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
575 GFP_ATOMIC);
576 if (!new_dma_addr_list) {
577 if (netif_msg_drv(lp))
ad361c98 578 printk(KERN_ERR
06c87850
DF		 579 "%s: Memory allocation failed.\n", dev->name);
580 goto free_new_rx_ring;
581 }
582
583 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
584 GFP_ATOMIC);
585 if (!new_skb_list) {
586 if (netif_msg_drv(lp))
ad361c98 587 printk(KERN_ERR
06c87850
DF		 588 "%s: Memory allocation failed.\n", dev->name);
589 goto free_new_lists;
590 }
591
592 /* first copy the current receive buffers */
593 overlap = min(size, lp->rx_ring_size);
594 for (new = 0; new < overlap; new++) {
595 new_rx_ring[new] = lp->rx_ring[new];
596 new_dma_addr_list[new] = lp->rx_dma_addr[new];
597 new_skb_list[new] = lp->rx_skbuff[new];
598 }
599 /* now allocate any new buffers needed */
600 for (; new < size; new++ ) {
601 struct sk_buff *rx_skbuff;
232c5640 602 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SKB);
06c87850
DF		 603 if (!(rx_skbuff = new_skb_list[new])) {
604 /* keep the original lists and buffers */
605 if (netif_msg_drv(lp))
606 printk(KERN_ERR
607 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
608 dev->name);
609 goto free_all_new;
610 }
232c5640 611 skb_reserve(rx_skbuff, NET_IP_ALIGN);
06c87850
DF		 612
613 new_dma_addr_list[new] =
614 pci_map_single(lp->pci_dev, rx_skbuff->data,
232c5640 615 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
3e33545b 616 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
232c5640 617 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
3e33545b 618 new_rx_ring[new].status = cpu_to_le16(0x8000);
06c87850
DF		 619 }
620 /* and free any unneeded buffers */
621 for (; new < lp->rx_ring_size; new++) {
622 if (lp->rx_skbuff[new]) {
623 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
232c5640 624 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
06c87850
DF		 625 dev_kfree_skb(lp->rx_skbuff[new]);
626 }
627 }
628
629 kfree(lp->rx_skbuff);
630 kfree(lp->rx_dma_addr);
631 pci_free_consistent(lp->pci_dev,
632 sizeof(struct pcnet32_rx_head) *
633 lp->rx_ring_size, lp->rx_ring,
634 lp->rx_ring_dma_addr);
635
636 lp->rx_ring_size = (1 << size);
637 lp->rx_mod_mask = lp->rx_ring_size - 1;
638 lp->rx_len_bits = (size << 4);
639 lp->rx_ring = new_rx_ring;
640 lp->rx_ring_dma_addr = new_ring_dma_addr;
641 lp->rx_dma_addr = new_dma_addr_list;
642 lp->rx_skbuff = new_skb_list;
643 return;
644
645 free_all_new:
646 for (; --new >= lp->rx_ring_size; ) {
647 if (new_skb_list[new]) {
648 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
232c5640 649 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
06c87850
DF		 650 dev_kfree_skb(new_skb_list[new]);
651 }
652 }
653 kfree(new_skb_list);
654 free_new_lists:
655 kfree(new_dma_addr_list);
656 free_new_rx_ring:
657 pci_free_consistent(lp->pci_dev,
658 sizeof(struct pcnet32_rx_head) *
659 (1 << size),
660 new_rx_ring,
661 new_ring_dma_addr);
662 return;
663}
664
ac5bfe40
DF		 665static void pcnet32_purge_rx_ring(struct net_device *dev)
666{
1e56a4b4 667 struct pcnet32_private *lp = netdev_priv(dev);
ac5bfe40
DF		 668 int i;
669
670 /* free all allocated skbuffs */
671 for (i = 0; i < lp->rx_ring_size; i++) {
672 lp->rx_ring[i].status = 0; /* CPU owns buffer */
673 wmb(); /* Make sure adapter sees owner change */
674 if (lp->rx_skbuff[i]) {
675 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
232c5640 676 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
ac5bfe40
DF		 677 dev_kfree_skb_any(lp->rx_skbuff[i]);
678 }
679 lp->rx_skbuff[i] = NULL;
680 lp->rx_dma_addr[i] = 0;
681 }
682}
683
1da177e4
LT		 684#ifdef CONFIG_NET_POLL_CONTROLLER
685static void pcnet32_poll_controller(struct net_device *dev)
686{
4a5e8e29 687 disable_irq(dev->irq);
7d12e780 688 pcnet32_interrupt(0, dev);
4a5e8e29 689 enable_irq(dev->irq);
1da177e4
LT		 690}
691#endif
692
1da177e4
LT		 693static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
694{
1e56a4b4 695 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 696 unsigned long flags;
697 int r = -EOPNOTSUPP;
1da177e4 698
4a5e8e29
JG		 699 if (lp->mii) {
700 spin_lock_irqsave(&lp->lock, flags);
701 mii_ethtool_gset(&lp->mii_if, cmd);
702 spin_unlock_irqrestore(&lp->lock, flags);
703 r = 0;
704 }
705 return r;
1da177e4
LT		 706}
707
708static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
709{
1e56a4b4 710 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 711 unsigned long flags;
712 int r = -EOPNOTSUPP;
1da177e4 713
4a5e8e29
JG		 714 if (lp->mii) {
715 spin_lock_irqsave(&lp->lock, flags);
716 r = mii_ethtool_sset(&lp->mii_if, cmd);
717 spin_unlock_irqrestore(&lp->lock, flags);
718 }
719 return r;
1da177e4
LT		 720}
721
4a5e8e29
JG		 722static void pcnet32_get_drvinfo(struct net_device *dev,
723 struct ethtool_drvinfo *info)
1da177e4 724{
1e56a4b4 725 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 726
727 strcpy(info->driver, DRV_NAME);
728 strcpy(info->version, DRV_VERSION);
729 if (lp->pci_dev)
730 strcpy(info->bus_info, pci_name(lp->pci_dev));
731 else
732 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
1da177e4
LT		 733}
734
735static u32 pcnet32_get_link(struct net_device *dev)
736{
1e56a4b4 737 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 738 unsigned long flags;
739 int r;
1da177e4 740
4a5e8e29
JG		 741 spin_lock_irqsave(&lp->lock, flags);
742 if (lp->mii) {
743 r = mii_link_ok(&lp->mii_if);
8d916266 744 } else if (lp->chip_version >= PCNET32_79C970A) {
4a5e8e29
JG		 745 ulong ioaddr = dev->base_addr; /* card base I/O address */
746 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
8d916266
DF		 747 } else { /* can not detect link on really old chips */
748 r = 1;
4a5e8e29
JG		 749 }
750 spin_unlock_irqrestore(&lp->lock, flags);
751
752 return r;
1da177e4
LT		 753}
754
755static u32 pcnet32_get_msglevel(struct net_device *dev)
756{
1e56a4b4 757 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 758 return lp->msg_enable;
1da177e4
LT		 759}
760
761static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
762{
1e56a4b4 763 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 764 lp->msg_enable = value;
1da177e4
LT		 765}
766
767static int pcnet32_nway_reset(struct net_device *dev)
768{
1e56a4b4 769 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 770 unsigned long flags;
771 int r = -EOPNOTSUPP;
1da177e4 772
4a5e8e29
JG		 773 if (lp->mii) {
774 spin_lock_irqsave(&lp->lock, flags);
775 r = mii_nway_restart(&lp->mii_if);
776 spin_unlock_irqrestore(&lp->lock, flags);
777 }
778 return r;
1da177e4
LT		 779}
780
4a5e8e29
JG		 781static void pcnet32_get_ringparam(struct net_device *dev,
782 struct ethtool_ringparam *ering)
1da177e4 783{
1e56a4b4 784 struct pcnet32_private *lp = netdev_priv(dev);
1da177e4 785
6dcd60c2
DF		 786 ering->tx_max_pending = TX_MAX_RING_SIZE;
787 ering->tx_pending = lp->tx_ring_size;
788 ering->rx_max_pending = RX_MAX_RING_SIZE;
789 ering->rx_pending = lp->rx_ring_size;
eabf0415
HWL		 790}
791
4a5e8e29
JG		 792static int pcnet32_set_ringparam(struct net_device *dev,
793 struct ethtool_ringparam *ering)
eabf0415 794{
1e56a4b4 795 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 796 unsigned long flags;
06c87850
DF		 797 unsigned int size;
798 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 799 int i;
800
801 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
802 return -EINVAL;
803
804 if (netif_running(dev))
06c87850 805 pcnet32_netif_stop(dev);
4a5e8e29
JG		 806
807 spin_lock_irqsave(&lp->lock, flags);
06c87850
DF		 808 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
809
810 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
4a5e8e29
JG		 811
812 /* set the minimum ring size to 4, to allow the loopback test to work
813 * unchanged.
814 */
815 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
06c87850 816 if (size <= (1 << i))
4a5e8e29
JG		 817 break;
818 }
06c87850
DF		 819 if ((1 << i) != lp->tx_ring_size)
820 pcnet32_realloc_tx_ring(dev, lp, i);
b368a3fb 821
06c87850 822 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
4a5e8e29 823 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
06c87850 824 if (size <= (1 << i))
4a5e8e29
JG		 825 break;
826 }
06c87850
DF		 827 if ((1 << i) != lp->rx_ring_size)
828 pcnet32_realloc_rx_ring(dev, lp, i);
b368a3fb 829
bea3348e 830 lp->napi.weight = lp->rx_ring_size / 2;
06c87850
DF		 831
832 if (netif_running(dev)) {
833 pcnet32_netif_start(dev);
834 pcnet32_restart(dev, CSR0_NORMAL);
4a5e8e29 835 }
eabf0415 836
4a5e8e29 837 spin_unlock_irqrestore(&lp->lock, flags);
eabf0415 838
06c87850
DF		 839 if (netif_msg_drv(lp))
840 printk(KERN_INFO
4a5e8e29
JG		 841 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
842 lp->rx_ring_size, lp->tx_ring_size);
eabf0415 843
4a5e8e29 844 return 0;
1da177e4
LT		 845}
846
4a5e8e29
JG		 847static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
848 u8 * data)
1da177e4 849{
4a5e8e29 850 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
1da177e4
LT		 851}
852
b9f2c044 853static int pcnet32_get_sset_count(struct net_device *dev, int sset)
1da177e4 854{
b9f2c044
JG		 855 switch (sset) {
856 case ETH_SS_TEST:
857 return PCNET32_TEST_LEN;
858 default:
859 return -EOPNOTSUPP;
860 }
1da177e4
LT		 861}
862
863static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29 864 struct ethtool_test *test, u64 * data)
1da177e4 865{
1e56a4b4 866 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 867 int rc;
868
869 if (test->flags == ETH_TEST_FL_OFFLINE) {
870 rc = pcnet32_loopback_test(dev, data);
871 if (rc) {
872 if (netif_msg_hw(lp))
873 printk(KERN_DEBUG "%s: Loopback test failed.\n",
874 dev->name);
875 test->flags |= ETH_TEST_FL_FAILED;
876 } else if (netif_msg_hw(lp))
877 printk(KERN_DEBUG "%s: Loopback test passed.\n",
878 dev->name);
1da177e4 879 } else if (netif_msg_hw(lp))
4a5e8e29
JG		 880 printk(KERN_DEBUG
881 "%s: No tests to run (specify 'Offline' on ethtool).",
882 dev->name);
883} /* end pcnet32_ethtool_test */
1da177e4 884
4a5e8e29 885static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
1da177e4 886{
1e56a4b4 887 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 888 struct pcnet32_access *a = &lp->a; /* access to registers */
889 ulong ioaddr = dev->base_addr; /* card base I/O address */
890 struct sk_buff *skb; /* sk buff */
891 int x, i; /* counters */
892 int numbuffs = 4; /* number of TX/RX buffers and descs */
893 u16 status = 0x8300; /* TX ring status */
3e33545b 894 __le16 teststatus; /* test of ring status */
4a5e8e29
JG		 895 int rc; /* return code */
896 int size; /* size of packets */
897 unsigned char *packet; /* source packet data */
898 static const int data_len = 60; /* length of source packets */
899 unsigned long flags;
900 unsigned long ticks;
901
4a5e8e29
JG		 902 rc = 1; /* default to fail */
903
904 if (netif_running(dev))
7de745e5 905 pcnet32_netif_stop(dev);
4a5e8e29
JG		 906
907 spin_lock_irqsave(&lp->lock, flags);
ac5bfe40
DF		 908 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
909
910 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
4a5e8e29
JG		 911
912 /* Reset the PCNET32 */
913 lp->a.reset(ioaddr);
b368a3fb 914 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
4a5e8e29
JG		 915
916 /* switch pcnet32 to 32bit mode */
917 lp->a.write_bcr(ioaddr, 20, 2);
918
4a5e8e29
JG		 919 /* purge & init rings but don't actually restart */
920 pcnet32_restart(dev, 0x0000);
921
ac5bfe40 922 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 923
924 /* Initialize Transmit buffers. */
925 size = data_len + 15;
926 for (x = 0; x < numbuffs; x++) {
927 if (!(skb = dev_alloc_skb(size))) {
928 if (netif_msg_hw(lp))
929 printk(KERN_DEBUG
930 "%s: Cannot allocate skb at line: %d!\n",
931 dev->name, __LINE__);
932 goto clean_up;
933 } else {
934 packet = skb->data;
935 skb_put(skb, size); /* create space for data */
936 lp->tx_skbuff[x] = skb;
3e33545b 937 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
4a5e8e29
JG		 938 lp->tx_ring[x].misc = 0;
939
940 /* put DA and SA into the skb */
941 for (i = 0; i < 6; i++)
942 *packet++ = dev->dev_addr[i];
943 for (i = 0; i < 6; i++)
944 *packet++ = dev->dev_addr[i];
945 /* type */
946 *packet++ = 0x08;
947 *packet++ = 0x06;
948 /* packet number */
949 *packet++ = x;
950 /* fill packet with data */
951 for (i = 0; i < data_len; i++)
952 *packet++ = i;
953
954 lp->tx_dma_addr[x] =
955 pci_map_single(lp->pci_dev, skb->data, skb->len,
956 PCI_DMA_TODEVICE);
3e33545b 957 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
4a5e8e29 958 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 959 lp->tx_ring[x].status = cpu_to_le16(status);
4a5e8e29 960 }
1da177e4 961 }
1da177e4 962
ac5bfe40
DF		 963 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
964 a->write_bcr(ioaddr, 32, x | 0x0002);
4a5e8e29 965
ac5bfe40
DF		 966 /* set int loopback in CSR15 */
967 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
968 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
4a5e8e29 969
3e33545b 970 teststatus = cpu_to_le16(0x8000);
ac5bfe40 971 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
4a5e8e29
JG		 972
973 /* Check status of descriptors */
974 for (x = 0; x < numbuffs; x++) {
975 ticks = 0;
976 rmb();
977 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
978 spin_unlock_irqrestore(&lp->lock, flags);
ac5bfe40 979 msleep(1);
4a5e8e29
JG		 980 spin_lock_irqsave(&lp->lock, flags);
981 rmb();
982 ticks++;
983 }
984 if (ticks == 200) {
985 if (netif_msg_hw(lp))
986 printk("%s: Desc %d failed to reset!\n",
987 dev->name, x);
988 break;
989 }
990 }
991
ac5bfe40 992 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 993 wmb();
994 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
995 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
996
997 for (x = 0; x < numbuffs; x++) {
998 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
999 skb = lp->rx_skbuff[x];
1000 for (i = 0; i < size; i++) {
1001 printk("%02x ", *(skb->data + i));
1002 }
1003 printk("\n");
1004 }
1005 }
1da177e4 1006
4a5e8e29
JG		 1007 x = 0;
1008 rc = 0;
1009 while (x < numbuffs && !rc) {
1010 skb = lp->rx_skbuff[x];
1011 packet = lp->tx_skbuff[x]->data;
1012 for (i = 0; i < size; i++) {
1013 if (*(skb->data + i) != packet[i]) {
1014 if (netif_msg_hw(lp))
1015 printk(KERN_DEBUG
1016 "%s: Error in compare! %2x - %02x %02x\n",
1017 dev->name, i, *(skb->data + i),
1018 packet[i]);
1019 rc = 1;
1020 break;
1021 }
1022 }
1023 x++;
1024 }
1da177e4 1025
4a5e8e29 1026 clean_up:
ac5bfe40 1027 *data1 = rc;
4a5e8e29 1028 pcnet32_purge_tx_ring(dev);
1da177e4 1029
ac5bfe40
DF		 1030 x = a->read_csr(ioaddr, CSR15);
1031 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1da177e4 1032
ac5bfe40
DF		 1033 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1034 a->write_bcr(ioaddr, 32, (x & ~0x0002));
4a5e8e29 1035
7de745e5
DF		 1036 if (netif_running(dev)) {
1037 pcnet32_netif_start(dev);
1038 pcnet32_restart(dev, CSR0_NORMAL);
1039 } else {
1040 pcnet32_purge_rx_ring(dev);
1041 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1042 }
1043 spin_unlock_irqrestore(&lp->lock, flags);
4a5e8e29
JG		 1044
1045 return (rc);
1046} /* end pcnet32_loopback_test */
1da177e4
LT		 1047
1048static void pcnet32_led_blink_callback(struct net_device *dev)
1049{
1e56a4b4 1050 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1051 struct pcnet32_access *a = &lp->a;
1052 ulong ioaddr = dev->base_addr;
1053 unsigned long flags;
1054 int i;
1055
1056 spin_lock_irqsave(&lp->lock, flags);
1057 for (i = 4; i < 8; i++) {
1058 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1059 }
1060 spin_unlock_irqrestore(&lp->lock, flags);
1061
1062 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1da177e4
LT		 1063}
1064
1065static int pcnet32_phys_id(struct net_device *dev, u32 data)
1066{
1e56a4b4 1067 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1068 struct pcnet32_access *a = &lp->a;
1069 ulong ioaddr = dev->base_addr;
1070 unsigned long flags;
1071 int i, regs[4];
1072
1073 if (!lp->blink_timer.function) {
1074 init_timer(&lp->blink_timer);
1075 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1076 lp->blink_timer.data = (unsigned long)dev;
1077 }
1078
1079 /* Save the current value of the bcrs */
1080 spin_lock_irqsave(&lp->lock, flags);
1081 for (i = 4; i < 8; i++) {
1082 regs[i - 4] = a->read_bcr(ioaddr, i);
1083 }
1084 spin_unlock_irqrestore(&lp->lock, flags);
1085
1086 mod_timer(&lp->blink_timer, jiffies);
1087 set_current_state(TASK_INTERRUPTIBLE);
1088
3e33545b 1089 /* AV: the limit here makes no sense whatsoever */
4a5e8e29
JG		 1090 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1091 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1092
1093 msleep_interruptible(data * 1000);
1094 del_timer_sync(&lp->blink_timer);
1095
1096 /* Restore the original value of the bcrs */
1097 spin_lock_irqsave(&lp->lock, flags);
1098 for (i = 4; i < 8; i++) {
1099 a->write_bcr(ioaddr, i, regs[i - 4]);
1100 }
1101 spin_unlock_irqrestore(&lp->lock, flags);
1102
1103 return 0;
1da177e4
LT		 1104}
1105
df27f4a6
DF		 1106/*
1107 * lp->lock must be held.
1108 */
1109static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1110 int can_sleep)
1111{
1112 int csr5;
1e56a4b4 1113 struct pcnet32_private *lp = netdev_priv(dev);
df27f4a6
DF		 1114 struct pcnet32_access *a = &lp->a;
1115 ulong ioaddr = dev->base_addr;
1116 int ticks;
1117
8d916266
DF		 1118 /* really old chips have to be stopped. */
1119 if (lp->chip_version < PCNET32_79C970A)
1120 return 0;
1121
df27f4a6
DF		 1122 /* set SUSPEND (SPND) - CSR5 bit 0 */
1123 csr5 = a->read_csr(ioaddr, CSR5);
1124 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1125
1126 /* poll waiting for bit to be set */
1127 ticks = 0;
1128 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1129 spin_unlock_irqrestore(&lp->lock, *flags);
1130 if (can_sleep)
1131 msleep(1);
1132 else
1133 mdelay(1);
1134 spin_lock_irqsave(&lp->lock, *flags);
1135 ticks++;
1136 if (ticks > 200) {
1137 if (netif_msg_hw(lp))
1138 printk(KERN_DEBUG
1139 "%s: Error getting into suspend!\n",
1140 dev->name);
1141 return 0;
1142 }
1143 }
1144 return 1;
1145}
1146
3904c324
DF		 1147/*
1148 * process one receive descriptor entry
1149 */
1150
1151static void pcnet32_rx_entry(struct net_device *dev,
1152 struct pcnet32_private *lp,
1153 struct pcnet32_rx_head *rxp,
1154 int entry)
1155{
1156 int status = (short)le16_to_cpu(rxp->status) >> 8;
1157 int rx_in_place = 0;
1158 struct sk_buff *skb;
1159 short pkt_len;
1160
1161 if (status != 0x03) { /* There was an error. */
1162 /*
1163 * There is a tricky error noted by John Murphy,
1164 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1165 * buffers it's possible for a jabber packet to use two
1166 * buffers, with only the last correctly noting the error.
1167 */
1168 if (status & 0x01) /* Only count a general error at the */
4f1e5ba0 1169 dev->stats.rx_errors++; /* end of a packet. */
3904c324 1170 if (status & 0x20)
4f1e5ba0 1171 dev->stats.rx_frame_errors++;
3904c324 1172 if (status & 0x10)
4f1e5ba0 1173 dev->stats.rx_over_errors++;
3904c324 1174 if (status & 0x08)
4f1e5ba0 1175 dev->stats.rx_crc_errors++;
3904c324 1176 if (status & 0x04)
4f1e5ba0 1177 dev->stats.rx_fifo_errors++;
3904c324
DF		 1178 return;
1179 }
1180
1181 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1182
1183 /* Discard oversize frames. */
232c5640 1184 if (unlikely(pkt_len > PKT_BUF_SIZE)) {
3904c324
DF		 1185 if (netif_msg_drv(lp))
1186 printk(KERN_ERR "%s: Impossible packet size %d!\n",
1187 dev->name, pkt_len);
4f1e5ba0 1188 dev->stats.rx_errors++;
3904c324
DF		 1189 return;
1190 }
1191 if (pkt_len < 60) {
1192 if (netif_msg_rx_err(lp))
1193 printk(KERN_ERR "%s: Runt packet!\n", dev->name);
4f1e5ba0 1194 dev->stats.rx_errors++;
3904c324
DF		 1195 return;
1196 }
1197
1198 if (pkt_len > rx_copybreak) {
1199 struct sk_buff *newskb;
1200
232c5640
DF		 1201 if ((newskb = dev_alloc_skb(PKT_BUF_SKB))) {
1202 skb_reserve(newskb, NET_IP_ALIGN);
3904c324
DF		 1203 skb = lp->rx_skbuff[entry];
1204 pci_unmap_single(lp->pci_dev,
1205 lp->rx_dma_addr[entry],
232c5640 1206 PKT_BUF_SIZE,
3904c324
DF		 1207 PCI_DMA_FROMDEVICE);
1208 skb_put(skb, pkt_len);
1209 lp->rx_skbuff[entry] = newskb;
3904c324
DF		 1210 lp->rx_dma_addr[entry] =
1211 pci_map_single(lp->pci_dev,
1212 newskb->data,
232c5640 1213 PKT_BUF_SIZE,
3904c324 1214 PCI_DMA_FROMDEVICE);
3e33545b 1215 rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
3904c324
DF		 1216 rx_in_place = 1;
1217 } else
1218 skb = NULL;
1219 } else {
232c5640 1220 skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN);
3904c324
DF		 1221 }
1222
1223 if (skb == NULL) {
1224 if (netif_msg_drv(lp))
1225 printk(KERN_ERR
1226 "%s: Memory squeeze, dropping packet.\n",
1227 dev->name);
4f1e5ba0 1228 dev->stats.rx_dropped++;
3904c324
DF		 1229 return;
1230 }
3904c324 1231 if (!rx_in_place) {
232c5640 1232 skb_reserve(skb, NET_IP_ALIGN);
3904c324
DF		 1233 skb_put(skb, pkt_len); /* Make room */
1234 pci_dma_sync_single_for_cpu(lp->pci_dev,
1235 lp->rx_dma_addr[entry],
b2cbbd8e 1236 pkt_len,
3904c324 1237 PCI_DMA_FROMDEVICE);
8c7b7faa 1238 skb_copy_to_linear_data(skb,
3904c324 1239 (unsigned char *)(lp->rx_skbuff[entry]->data),
8c7b7faa 1240 pkt_len);
3904c324
DF		 1241 pci_dma_sync_single_for_device(lp->pci_dev,
1242 lp->rx_dma_addr[entry],
b2cbbd8e 1243 pkt_len,
3904c324
DF		 1244 PCI_DMA_FROMDEVICE);
1245 }
4f1e5ba0 1246 dev->stats.rx_bytes += skb->len;
3904c324 1247 skb->protocol = eth_type_trans(skb, dev);
7de745e5 1248 netif_receive_skb(skb);
4f1e5ba0 1249 dev->stats.rx_packets++;
3904c324
DF		 1250 return;
1251}
1252
bea3348e 1253static int pcnet32_rx(struct net_device *dev, int budget)
9691edd2 1254{
1e56a4b4 1255 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2 1256 int entry = lp->cur_rx & lp->rx_mod_mask;
3904c324
DF		 1257 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1258 int npackets = 0;
9691edd2
DF		 1259
1260 /* If we own the next entry, it's a new packet. Send it up. */
bea3348e 1261 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
3904c324
DF		 1262 pcnet32_rx_entry(dev, lp, rxp, entry);
1263 npackets += 1;
9691edd2 1264 /*
3904c324
DF		 1265 * The docs say that the buffer length isn't touched, but Andrew
1266 * Boyd of QNX reports that some revs of the 79C965 clear it.
9691edd2 1267 */
232c5640 1268 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
3904c324 1269 wmb(); /* Make sure owner changes after others are visible */
3e33545b 1270 rxp->status = cpu_to_le16(0x8000);
9691edd2 1271 entry = (++lp->cur_rx) & lp->rx_mod_mask;
3904c324 1272 rxp = &lp->rx_ring[entry];
9691edd2
DF		 1273 }
1274
7de745e5 1275 return npackets;
9691edd2
DF		 1276}
1277
7de745e5 1278static int pcnet32_tx(struct net_device *dev)
9691edd2 1279{
1e56a4b4 1280 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2
DF		 1281 unsigned int dirty_tx = lp->dirty_tx;
1282 int delta;
1283 int must_restart = 0;
1284
1285 while (dirty_tx != lp->cur_tx) {
1286 int entry = dirty_tx & lp->tx_mod_mask;
1287 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1288
1289 if (status < 0)
1290 break; /* It still hasn't been Txed */
1291
1292 lp->tx_ring[entry].base = 0;
1293
1294 if (status & 0x4000) {
3904c324 1295 /* There was a major error, log it. */
9691edd2 1296 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
4f1e5ba0 1297 dev->stats.tx_errors++;
9691edd2
DF		 1298 if (netif_msg_tx_err(lp))
1299 printk(KERN_ERR
1300 "%s: Tx error status=%04x err_status=%08x\n",
1301 dev->name, status,
1302 err_status);
1303 if (err_status & 0x04000000)
4f1e5ba0 1304 dev->stats.tx_aborted_errors++;
9691edd2 1305 if (err_status & 0x08000000)
4f1e5ba0 1306 dev->stats.tx_carrier_errors++;
9691edd2 1307 if (err_status & 0x10000000)
4f1e5ba0 1308 dev->stats.tx_window_errors++;
9691edd2
DF		 1309#ifndef DO_DXSUFLO
1310 if (err_status & 0x40000000) {
4f1e5ba0 1311 dev->stats.tx_fifo_errors++;
9691edd2
DF		 1312 /* Ackk! On FIFO errors the Tx unit is turned off! */
1313 /* Remove this verbosity later! */
1314 if (netif_msg_tx_err(lp))
1315 printk(KERN_ERR
7de745e5
DF		 1316 "%s: Tx FIFO error!\n",
1317 dev->name);
9691edd2
DF		 1318 must_restart = 1;
1319 }
1320#else
1321 if (err_status & 0x40000000) {
4f1e5ba0 1322 dev->stats.tx_fifo_errors++;
9691edd2
DF		 1323 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1324 /* Ackk! On FIFO errors the Tx unit is turned off! */
1325 /* Remove this verbosity later! */
3904c324 1326 if (netif_msg_tx_err(lp))
9691edd2 1327 printk(KERN_ERR
7de745e5
DF		 1328 "%s: Tx FIFO error!\n",
1329 dev->name);
9691edd2
DF		 1330 must_restart = 1;
1331 }
1332 }
1333#endif
1334 } else {
1335 if (status & 0x1800)
4f1e5ba0
DF		 1336 dev->stats.collisions++;
1337 dev->stats.tx_packets++;
9691edd2
DF		 1338 }
1339
1340 /* We must free the original skb */
1341 if (lp->tx_skbuff[entry]) {
1342 pci_unmap_single(lp->pci_dev,
1343 lp->tx_dma_addr[entry],
1344 lp->tx_skbuff[entry]->
1345 len, PCI_DMA_TODEVICE);
3904c324 1346 dev_kfree_skb_any(lp->tx_skbuff[entry]);
9691edd2
DF		 1347 lp->tx_skbuff[entry] = NULL;
1348 lp->tx_dma_addr[entry] = 0;
1349 }
1350 dirty_tx++;
1351 }
1352
3904c324 1353 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
9691edd2
DF		 1354 if (delta > lp->tx_ring_size) {
1355 if (netif_msg_drv(lp))
1356 printk(KERN_ERR
1357 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1358 dev->name, dirty_tx, lp->cur_tx,
1359 lp->tx_full);
1360 dirty_tx += lp->tx_ring_size;
1361 delta -= lp->tx_ring_size;
1362 }
1363
1364 if (lp->tx_full &&
1365 netif_queue_stopped(dev) &&
1366 delta < lp->tx_ring_size - 2) {
1367 /* The ring is no longer full, clear tbusy. */
1368 lp->tx_full = 0;
1369 netif_wake_queue(dev);
1370 }
1371 lp->dirty_tx = dirty_tx;
1372
1373 return must_restart;
1374}
1375
bea3348e 1376static int pcnet32_poll(struct napi_struct *napi, int budget)
7de745e5 1377{
bea3348e
SH		 1378 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1379 struct net_device *dev = lp->dev;
7de745e5
DF		 1380 unsigned long ioaddr = dev->base_addr;
1381 unsigned long flags;
bea3348e 1382 int work_done;
7de745e5
DF		 1383 u16 val;
1384
bea3348e 1385 work_done = pcnet32_rx(dev, budget);
7de745e5
DF		 1386
1387 spin_lock_irqsave(&lp->lock, flags);
1388 if (pcnet32_tx(dev)) {
1389 /* reset the chip to clear the error condition, then restart */
1390 lp->a.reset(ioaddr);
1391 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1392 pcnet32_restart(dev, CSR0_START);
1393 netif_wake_queue(dev);
1394 }
1395 spin_unlock_irqrestore(&lp->lock, flags);
1396
bea3348e
SH		 1397 if (work_done < budget) {
1398 spin_lock_irqsave(&lp->lock, flags);
7de745e5 1399
288379f0 1400 __napi_complete(napi);
7de745e5 1401
bea3348e
SH		 1402 /* clear interrupt masks */
1403 val = lp->a.read_csr(ioaddr, CSR3);
1404 val &= 0x00ff;
1405 lp->a.write_csr(ioaddr, CSR3, val);
7de745e5 1406
bea3348e
SH		 1407 /* Set interrupt enable. */
1408 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
ce105a08 1409
bea3348e
SH		 1410 spin_unlock_irqrestore(&lp->lock, flags);
1411 }
1412 return work_done;
7de745e5 1413}
7de745e5 1414
ac62ef04
DF		 1415#define PCNET32_REGS_PER_PHY 32
1416#define PCNET32_MAX_PHYS 32
1da177e4
LT		 1417static int pcnet32_get_regs_len(struct net_device *dev)
1418{
1e56a4b4 1419 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 1420 int j = lp->phycount * PCNET32_REGS_PER_PHY;
ac62ef04 1421
4a5e8e29 1422 return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1da177e4
LT		 1423}
1424
1425static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 1426 void *ptr)
1da177e4 1427{
4a5e8e29
JG		 1428 int i, csr0;
1429 u16 *buff = ptr;
1e56a4b4 1430 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1431 struct pcnet32_access *a = &lp->a;
1432 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 1433 unsigned long flags;
1434
1435 spin_lock_irqsave(&lp->lock, flags);
1436
df27f4a6
DF		 1437 csr0 = a->read_csr(ioaddr, CSR0);
1438 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1439 pcnet32_suspend(dev, &flags, 1);
1da177e4 1440
4a5e8e29
JG		 1441 /* read address PROM */
1442 for (i = 0; i < 16; i += 2)
1443 *buff++ = inw(ioaddr + i);
1444
1445 /* read control and status registers */
1446 for (i = 0; i < 90; i++) {
1447 *buff++ = a->read_csr(ioaddr, i);
1448 }
1449
1450 *buff++ = a->read_csr(ioaddr, 112);
1451 *buff++ = a->read_csr(ioaddr, 114);
1da177e4 1452
4a5e8e29
JG		 1453 /* read bus configuration registers */
1454 for (i = 0; i < 30; i++) {
1455 *buff++ = a->read_bcr(ioaddr, i);
1456 }
1457 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1458 for (i = 31; i < 36; i++) {
1459 *buff++ = a->read_bcr(ioaddr, i);
1460 }
1461
1462 /* read mii phy registers */
1463 if (lp->mii) {
1464 int j;
1465 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1466 if (lp->phymask & (1 << j)) {
1467 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1468 lp->a.write_bcr(ioaddr, 33,
1469 (j << 5) | i);
1470 *buff++ = lp->a.read_bcr(ioaddr, 34);
1471 }
1472 }
1473 }
1474 }
1475
df27f4a6
DF		 1476 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1477 int csr5;
1478
4a5e8e29 1479 /* clear SUSPEND (SPND) - CSR5 bit 0 */
df27f4a6
DF		 1480 csr5 = a->read_csr(ioaddr, CSR5);
1481 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
4a5e8e29
JG		 1482 }
1483
1484 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 1485}
1486
7282d491 1487static const struct ethtool_ops pcnet32_ethtool_ops = {
4a5e8e29
JG		 1488 .get_settings = pcnet32_get_settings,
1489 .set_settings = pcnet32_set_settings,
1490 .get_drvinfo = pcnet32_get_drvinfo,
1491 .get_msglevel = pcnet32_get_msglevel,
1492 .set_msglevel = pcnet32_set_msglevel,
1493 .nway_reset = pcnet32_nway_reset,
1494 .get_link = pcnet32_get_link,
1495 .get_ringparam = pcnet32_get_ringparam,
1496 .set_ringparam = pcnet32_set_ringparam,
4a5e8e29 1497 .get_strings = pcnet32_get_strings,
4a5e8e29
JG		 1498 .self_test = pcnet32_ethtool_test,
1499 .phys_id = pcnet32_phys_id,
1500 .get_regs_len = pcnet32_get_regs_len,
1501 .get_regs = pcnet32_get_regs,
b9f2c044 1502 .get_sset_count = pcnet32_get_sset_count,
1da177e4
LT		 1503};
1504
1505/* only probes for non-PCI devices, the rest are handled by
1506 * pci_register_driver via pcnet32_probe_pci */
1507
dcaf9769 1508static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1da177e4 1509{
4a5e8e29
JG		 1510 unsigned int *port, ioaddr;
1511
1512 /* search for PCnet32 VLB cards at known addresses */
1513 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1514 if (request_region
1515 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1516 /* check if there is really a pcnet chip on that ioaddr */
1517 if ((inb(ioaddr + 14) == 0x57)
1518 && (inb(ioaddr + 15) == 0x57)) {
1519 pcnet32_probe1(ioaddr, 0, NULL);
1520 } else {
1521 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1522 }
1523 }
1524 }
1da177e4
LT		 1525}
1526
1da177e4
LT		 1527static int __devinit
1528pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1529{
4a5e8e29
JG		 1530 unsigned long ioaddr;
1531 int err;
1532
1533 err = pci_enable_device(pdev);
1534 if (err < 0) {
1535 if (pcnet32_debug & NETIF_MSG_PROBE)
1536 printk(KERN_ERR PFX
1537 "failed to enable device -- err=%d\n", err);
1538 return err;
1539 }
1540 pci_set_master(pdev);
1541
1542 ioaddr = pci_resource_start(pdev, 0);
1543 if (!ioaddr) {
1544 if (pcnet32_debug & NETIF_MSG_PROBE)
1545 printk(KERN_ERR PFX
1546 "card has no PCI IO resources, aborting\n");
1547 return -ENODEV;
1548 }
1da177e4 1549
4a5e8e29
JG		 1550 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1551 if (pcnet32_debug & NETIF_MSG_PROBE)
1552 printk(KERN_ERR PFX
1553 "architecture does not support 32bit PCI busmaster DMA\n");
1554 return -ENODEV;
1555 }
1556 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1557 NULL) {
1558 if (pcnet32_debug & NETIF_MSG_PROBE)
1559 printk(KERN_ERR PFX
1560 "io address range already allocated\n");
1561 return -EBUSY;
1562 }
1da177e4 1563
4a5e8e29
JG		 1564 err = pcnet32_probe1(ioaddr, 1, pdev);
1565 if (err < 0) {
1566 pci_disable_device(pdev);
1567 }
1568 return err;
1da177e4
LT		 1569}
1570
3bc124dd
SH		 1571static const struct net_device_ops pcnet32_netdev_ops = {
1572 .ndo_open = pcnet32_open,
1573 .ndo_stop = pcnet32_close,
1574 .ndo_start_xmit = pcnet32_start_xmit,
1575 .ndo_tx_timeout = pcnet32_tx_timeout,
1576 .ndo_get_stats = pcnet32_get_stats,
1577 .ndo_set_multicast_list = pcnet32_set_multicast_list,
1578 .ndo_do_ioctl = pcnet32_ioctl,
1579 .ndo_change_mtu = eth_change_mtu,
1580 .ndo_set_mac_address = eth_mac_addr,
1581 .ndo_validate_addr = eth_validate_addr,
1582#ifdef CONFIG_NET_POLL_CONTROLLER
1583 .ndo_poll_controller = pcnet32_poll_controller,
1584#endif
1585};
1586
1da177e4
LT		 1587/* pcnet32_probe1
1588 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1589 * pdev will be NULL when called from pcnet32_probe_vlbus.
1590 */
1591static int __devinit
1592pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1593{
4a5e8e29 1594 struct pcnet32_private *lp;
4a5e8e29
JG		 1595 int i, media;
1596 int fdx, mii, fset, dxsuflo;
1597 int chip_version;
1598 char *chipname;
1599 struct net_device *dev;
1600 struct pcnet32_access *a = NULL;
1601 u8 promaddr[6];
1602 int ret = -ENODEV;
1603
1604 /* reset the chip */
1605 pcnet32_wio_reset(ioaddr);
1606
1607 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1608 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1609 a = &pcnet32_wio;
1610 } else {
1611 pcnet32_dwio_reset(ioaddr);
1612 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1613 && pcnet32_dwio_check(ioaddr)) {
1614 a = &pcnet32_dwio;
df4e7f72
DF		 1615 } else {
1616 if (pcnet32_debug & NETIF_MSG_PROBE)
1617 printk(KERN_ERR PFX "No access methods\n");
4a5e8e29 1618 goto err_release_region;
df4e7f72 1619 }
4a5e8e29
JG		 1620 }
1621
1622 chip_version =
1623 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1624 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1625 printk(KERN_INFO " PCnet chip version is %#x.\n",
1626 chip_version);
1627 if ((chip_version & 0xfff) != 0x003) {
1628 if (pcnet32_debug & NETIF_MSG_PROBE)
1629 printk(KERN_INFO PFX "Unsupported chip version.\n");
1630 goto err_release_region;
1631 }
1632
1633 /* initialize variables */
1634 fdx = mii = fset = dxsuflo = 0;
1635 chip_version = (chip_version >> 12) & 0xffff;
1636
1637 switch (chip_version) {
1638 case 0x2420:
1639 chipname = "PCnet/PCI 79C970"; /* PCI */
1640 break;
1641 case 0x2430:
1642 if (shared)
1643 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1644 else
1645 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1646 break;
1647 case 0x2621:
1648 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1649 fdx = 1;
1650 break;
1651 case 0x2623:
1652 chipname = "PCnet/FAST 79C971"; /* PCI */
1653 fdx = 1;
1654 mii = 1;
1655 fset = 1;
1656 break;
1657 case 0x2624:
1658 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1659 fdx = 1;
1660 mii = 1;
1661 fset = 1;
1662 break;
1663 case 0x2625:
1664 chipname = "PCnet/FAST III 79C973"; /* PCI */
1665 fdx = 1;
1666 mii = 1;
1667 break;
1668 case 0x2626:
1669 chipname = "PCnet/Home 79C978"; /* PCI */
1670 fdx = 1;
1671 /*
1672 * This is based on specs published at www.amd.com. This section
1673 * assumes that a card with a 79C978 wants to go into standard
1674 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1675 * and the module option homepna=1 can select this instead.
1676 */
1677 media = a->read_bcr(ioaddr, 49);
1678 media &= ~3; /* default to 10Mb ethernet */
1679 if (cards_found < MAX_UNITS && homepna[cards_found])
1680 media |= 1; /* switch to home wiring mode */
1681 if (pcnet32_debug & NETIF_MSG_PROBE)
1682 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1683 (media & 1) ? "1" : "10");
1684 a->write_bcr(ioaddr, 49, media);
1685 break;
1686 case 0x2627:
1687 chipname = "PCnet/FAST III 79C975"; /* PCI */
1688 fdx = 1;
1689 mii = 1;
1690 break;
1691 case 0x2628:
1692 chipname = "PCnet/PRO 79C976";
1693 fdx = 1;
1694 mii = 1;
1695 break;
1696 default:
1697 if (pcnet32_debug & NETIF_MSG_PROBE)
1698 printk(KERN_INFO PFX
1699 "PCnet version %#x, no PCnet32 chip.\n",
1700 chip_version);
1701 goto err_release_region;
1702 }
1703
1da177e4 1704 /*
4a5e8e29
JG		 1705 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1706 * starting until the packet is loaded. Strike one for reliability, lose
1707 * one for latency - although on PCI this isnt a big loss. Older chips
1708 * have FIFO's smaller than a packet, so you can't do this.
1709 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1da177e4 1710 */
4a5e8e29
JG		 1711
1712 if (fset) {
1713 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1714 a->write_csr(ioaddr, 80,
1715 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1716 dxsuflo = 1;
1717 }
1718
6ecb7667 1719 dev = alloc_etherdev(sizeof(*lp));
4a5e8e29
JG		 1720 if (!dev) {
1721 if (pcnet32_debug & NETIF_MSG_PROBE)
1722 printk(KERN_ERR PFX "Memory allocation failed.\n");
1723 ret = -ENOMEM;
1724 goto err_release_region;
1725 }
63097b3a
DF		 1726
1727 if (pdev)
1728 SET_NETDEV_DEV(dev, &pdev->dev);
4a5e8e29 1729
1da177e4 1730 if (pcnet32_debug & NETIF_MSG_PROBE)
4a5e8e29
JG		 1731 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1732
1733 /* In most chips, after a chip reset, the ethernet address is read from the
1734 * station address PROM at the base address and programmed into the
1735 * "Physical Address Registers" CSR12-14.
1736 * As a precautionary measure, we read the PROM values and complain if
bc0e1fc9
LV		 1737 * they disagree with the CSRs. If they miscompare, and the PROM addr
1738 * is valid, then the PROM addr is used.
4a5e8e29
JG		 1739 */
1740 for (i = 0; i < 3; i++) {
1741 unsigned int val;
1742 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1743 /* There may be endianness issues here. */
1744 dev->dev_addr[2 * i] = val & 0x0ff;
1745 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1746 }
1747
1748 /* read PROM address and compare with CSR address */
1da177e4 1749 for (i = 0; i < 6; i++)
4a5e8e29
JG		 1750 promaddr[i] = inb(ioaddr + i);
1751
1752 if (memcmp(promaddr, dev->dev_addr, 6)
1753 || !is_valid_ether_addr(dev->dev_addr)) {
1754 if (is_valid_ether_addr(promaddr)) {
1755 if (pcnet32_debug & NETIF_MSG_PROBE) {
1756 printk(" warning: CSR address invalid,\n");
1757 printk(KERN_INFO
1758 " using instead PROM address of");
1759 }
1760 memcpy(dev->dev_addr, promaddr, 6);
1761 }
1762 }
1763 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1764
1765 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1766 if (!is_valid_ether_addr(dev->perm_addr))
1767 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1768
1769 if (pcnet32_debug & NETIF_MSG_PROBE) {
e174961c 1770 printk(" %pM", dev->dev_addr);
4a5e8e29
JG		 1771
1772 /* Version 0x2623 and 0x2624 */
1773 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1774 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
ad361c98 1775 printk(KERN_INFO " tx_start_pt(0x%04x):", i);
4a5e8e29
JG		 1776 switch (i >> 10) {
1777 case 0:
ad361c98 1778 printk(KERN_CONT " 20 bytes,");
4a5e8e29
JG		 1779 break;
1780 case 1:
ad361c98 1781 printk(KERN_CONT " 64 bytes,");
4a5e8e29
JG		 1782 break;
1783 case 2:
ad361c98 1784 printk(KERN_CONT " 128 bytes,");
4a5e8e29
JG		 1785 break;
1786 case 3:
ad361c98 1787 printk(KERN_CONT "~220 bytes,");
4a5e8e29
JG		 1788 break;
1789 }
1790 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
ad361c98 1791 printk(KERN_CONT " BCR18(%x):", i & 0xffff);
4a5e8e29 1792 if (i & (1 << 5))
ad361c98 1793 printk(KERN_CONT "BurstWrEn ");
4a5e8e29 1794 if (i & (1 << 6))
ad361c98 1795 printk(KERN_CONT "BurstRdEn ");
4a5e8e29 1796 if (i & (1 << 7))
ad361c98 1797 printk(KERN_CONT "DWordIO ");
4a5e8e29 1798 if (i & (1 << 11))
ad361c98 1799 printk(KERN_CONT "NoUFlow ");
4a5e8e29 1800 i = a->read_bcr(ioaddr, 25);
ad361c98 1801 printk(KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
4a5e8e29 1802 i = a->read_bcr(ioaddr, 26);
ad361c98 1803 printk(KERN_CONT " SRAM_BND=0x%04x,", i << 8);
4a5e8e29
JG		 1804 i = a->read_bcr(ioaddr, 27);
1805 if (i & (1 << 14))
ad361c98 1806 printk(KERN_CONT "LowLatRx");
4a5e8e29
JG		 1807 }
1808 }
1809
1810 dev->base_addr = ioaddr;
1e56a4b4 1811 lp = netdev_priv(dev);
4a5e8e29 1812 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
6ecb7667
DF		 1813 if ((lp->init_block =
1814 pci_alloc_consistent(pdev, sizeof(*lp->init_block), &lp->init_dma_addr)) == NULL) {
4a5e8e29
JG		 1815 if (pcnet32_debug & NETIF_MSG_PROBE)
1816 printk(KERN_ERR PFX
1817 "Consistent memory allocation failed.\n");
1818 ret = -ENOMEM;
1819 goto err_free_netdev;
1820 }
4a5e8e29
JG		 1821 lp->pci_dev = pdev;
1822
bea3348e
SH		 1823 lp->dev = dev;
1824
4a5e8e29
JG		 1825 spin_lock_init(&lp->lock);
1826
4a5e8e29
JG		 1827 lp->name = chipname;
1828 lp->shared_irq = shared;
1829 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1830 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1831 lp->tx_mod_mask = lp->tx_ring_size - 1;
1832 lp->rx_mod_mask = lp->rx_ring_size - 1;
1833 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1834 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1835 lp->mii_if.full_duplex = fdx;
1836 lp->mii_if.phy_id_mask = 0x1f;
1837 lp->mii_if.reg_num_mask = 0x1f;
1838 lp->dxsuflo = dxsuflo;
1839 lp->mii = mii;
8d916266 1840 lp->chip_version = chip_version;
4a5e8e29
JG		 1841 lp->msg_enable = pcnet32_debug;
1842 if ((cards_found >= MAX_UNITS)
5e33b719 1843 || (options[cards_found] >= sizeof(options_mapping)))
4a5e8e29
JG		 1844 lp->options = PCNET32_PORT_ASEL;
1845 else
1846 lp->options = options_mapping[options[cards_found]];
1847 lp->mii_if.dev = dev;
1848 lp->mii_if.mdio_read = mdio_read;
1849 lp->mii_if.mdio_write = mdio_write;
1850
feff348f
DF		 1851 /* napi.weight is used in both the napi and non-napi cases */
1852 lp->napi.weight = lp->rx_ring_size / 2;
1853
bea3348e 1854 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
bea3348e 1855
4a5e8e29
JG		 1856 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1857 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1858 lp->options |= PCNET32_PORT_FD;
1859
4a5e8e29
JG		 1860 lp->a = *a;
1861
1862 /* prior to register_netdev, dev->name is not yet correct */
1863 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1864 ret = -ENOMEM;
1865 goto err_free_ring;
1866 }
1867 /* detect special T1/E1 WAN card by checking for MAC address */
1868 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1da177e4 1869 && dev->dev_addr[2] == 0x75)
4a5e8e29 1870 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1da177e4 1871
3e33545b 1872 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */
6ecb7667 1873 lp->init_block->tlen_rlen =
3e33545b 1874 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
4a5e8e29 1875 for (i = 0; i < 6; i++)
6ecb7667
DF		 1876 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1877 lp->init_block->filter[0] = 0x00000000;
1878 lp->init_block->filter[1] = 0x00000000;
3e33545b
AV		 1879 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1880 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
4a5e8e29
JG		 1881
1882 /* switch pcnet32 to 32bit mode */
1883 a->write_bcr(ioaddr, 20, 2);
1884
6ecb7667
DF		 1885 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1886 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29
JG		 1887
1888 if (pdev) { /* use the IRQ provided by PCI */
1889 dev->irq = pdev->irq;
1890 if (pcnet32_debug & NETIF_MSG_PROBE)
1891 printk(" assigned IRQ %d.\n", dev->irq);
1892 } else {
1893 unsigned long irq_mask = probe_irq_on();
1894
1895 /*
1896 * To auto-IRQ we enable the initialization-done and DMA error
1897 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1898 * boards will work.
1899 */
1900 /* Trigger an initialization just for the interrupt. */
b368a3fb 1901 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
4a5e8e29
JG		 1902 mdelay(1);
1903
1904 dev->irq = probe_irq_off(irq_mask);
1905 if (!dev->irq) {
1906 if (pcnet32_debug & NETIF_MSG_PROBE)
1907 printk(", failed to detect IRQ line.\n");
1908 ret = -ENODEV;
1909 goto err_free_ring;
1910 }
1911 if (pcnet32_debug & NETIF_MSG_PROBE)
1912 printk(", probed IRQ %d.\n", dev->irq);
1913 }
1da177e4 1914
4a5e8e29
JG		 1915 /* Set the mii phy_id so that we can query the link state */
1916 if (lp->mii) {
1917 /* lp->phycount and lp->phymask are set to 0 by memset above */
1918
1919 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1920 /* scan for PHYs */
1921 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1922 unsigned short id1, id2;
1923
1924 id1 = mdio_read(dev, i, MII_PHYSID1);
1925 if (id1 == 0xffff)
1926 continue;
1927 id2 = mdio_read(dev, i, MII_PHYSID2);
1928 if (id2 == 0xffff)
1929 continue;
1930 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1931 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1932 lp->phycount++;
1933 lp->phymask |= (1 << i);
1934 lp->mii_if.phy_id = i;
1935 if (pcnet32_debug & NETIF_MSG_PROBE)
1936 printk(KERN_INFO PFX
1937 "Found PHY %04x:%04x at address %d.\n",
1938 id1, id2, i);
1939 }
1940 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1941 if (lp->phycount > 1) {
1942 lp->options |= PCNET32_PORT_MII;
1943 }
1da177e4 1944 }
4a5e8e29
JG		 1945
1946 init_timer(&lp->watchdog_timer);
1947 lp->watchdog_timer.data = (unsigned long)dev;
1948 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1949
1950 /* The PCNET32-specific entries in the device structure. */
3bc124dd 1951 dev->netdev_ops = &pcnet32_netdev_ops;
4a5e8e29 1952 dev->ethtool_ops = &pcnet32_ethtool_ops;
4a5e8e29 1953 dev->watchdog_timeo = (5 * HZ);
1da177e4 1954
4a5e8e29
JG		 1955 /* Fill in the generic fields of the device structure. */
1956 if (register_netdev(dev))
1957 goto err_free_ring;
1958
1959 if (pdev) {
1960 pci_set_drvdata(pdev, dev);
1961 } else {
1962 lp->next = pcnet32_dev;
1963 pcnet32_dev = dev;
1964 }
1965
1966 if (pcnet32_debug & NETIF_MSG_PROBE)
1967 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1968 cards_found++;
1969
1970 /* enable LED writes */
1971 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1da177e4 1972
4a5e8e29
JG		 1973 return 0;
1974
df4e7f72 1975err_free_ring:
4a5e8e29 1976 pcnet32_free_ring(dev);
7d2e3cb7 1977 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 1978 lp->init_block, lp->init_dma_addr);
df4e7f72 1979err_free_netdev:
4a5e8e29 1980 free_netdev(dev);
df4e7f72 1981err_release_region:
4a5e8e29
JG		 1982 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1983 return ret;
1984}
1da177e4 1985
a88c844c 1986/* if any allocation fails, caller must also call pcnet32_free_ring */
b166cfba 1987static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
eabf0415 1988{
1e56a4b4 1989 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 1990
4a5e8e29
JG		 1991 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1992 sizeof(struct pcnet32_tx_head) *
1993 lp->tx_ring_size,
1994 &lp->tx_ring_dma_addr);
1995 if (lp->tx_ring == NULL) {
12fa30f3 1996 if (netif_msg_drv(lp))
ad361c98 1997 printk(KERN_ERR PFX
4a5e8e29
JG		 1998 "%s: Consistent memory allocation failed.\n",
1999 name);
2000 return -ENOMEM;
2001 }
eabf0415 2002
4a5e8e29
JG		 2003 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
2004 sizeof(struct pcnet32_rx_head) *
2005 lp->rx_ring_size,
2006 &lp->rx_ring_dma_addr);
2007 if (lp->rx_ring == NULL) {
12fa30f3 2008 if (netif_msg_drv(lp))
ad361c98 2009 printk(KERN_ERR PFX
4a5e8e29
JG		 2010 "%s: Consistent memory allocation failed.\n",
2011 name);
2012 return -ENOMEM;
2013 }
eabf0415 2014
12fa30f3 2015 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 2016 GFP_ATOMIC);
2017 if (!lp->tx_dma_addr) {
12fa30f3 2018 if (netif_msg_drv(lp))
ad361c98 2019 printk(KERN_ERR PFX
4a5e8e29
JG		 2020 "%s: Memory allocation failed.\n", name);
2021 return -ENOMEM;
2022 }
4a5e8e29 2023
12fa30f3 2024 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 2025 GFP_ATOMIC);
2026 if (!lp->rx_dma_addr) {
12fa30f3 2027 if (netif_msg_drv(lp))
ad361c98 2028 printk(KERN_ERR PFX
4a5e8e29
JG		 2029 "%s: Memory allocation failed.\n", name);
2030 return -ENOMEM;
2031 }
4a5e8e29 2032
12fa30f3 2033 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 2034 GFP_ATOMIC);
2035 if (!lp->tx_skbuff) {
12fa30f3 2036 if (netif_msg_drv(lp))
ad361c98 2037 printk(KERN_ERR PFX
4a5e8e29
JG		 2038 "%s: Memory allocation failed.\n", name);
2039 return -ENOMEM;
2040 }
4a5e8e29 2041
12fa30f3 2042 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 2043 GFP_ATOMIC);
2044 if (!lp->rx_skbuff) {
12fa30f3 2045 if (netif_msg_drv(lp))
ad361c98 2046 printk(KERN_ERR PFX
4a5e8e29
JG		 2047 "%s: Memory allocation failed.\n", name);
2048 return -ENOMEM;
2049 }
4a5e8e29
JG		 2050
2051 return 0;
2052}
eabf0415
HWL		 2053
2054static void pcnet32_free_ring(struct net_device *dev)
2055{
1e56a4b4 2056 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 2057
4a5e8e29
JG		 2058 kfree(lp->tx_skbuff);
2059 lp->tx_skbuff = NULL;
eabf0415 2060
4a5e8e29
JG		 2061 kfree(lp->rx_skbuff);
2062 lp->rx_skbuff = NULL;
eabf0415 2063
4a5e8e29
JG		 2064 kfree(lp->tx_dma_addr);
2065 lp->tx_dma_addr = NULL;
eabf0415 2066
4a5e8e29
JG		 2067 kfree(lp->rx_dma_addr);
2068 lp->rx_dma_addr = NULL;
eabf0415 2069
4a5e8e29
JG		 2070 if (lp->tx_ring) {
2071 pci_free_consistent(lp->pci_dev,
2072 sizeof(struct pcnet32_tx_head) *
2073 lp->tx_ring_size, lp->tx_ring,
2074 lp->tx_ring_dma_addr);
2075 lp->tx_ring = NULL;
2076 }
eabf0415 2077
4a5e8e29
JG		 2078 if (lp->rx_ring) {
2079 pci_free_consistent(lp->pci_dev,
2080 sizeof(struct pcnet32_rx_head) *
2081 lp->rx_ring_size, lp->rx_ring,
2082 lp->rx_ring_dma_addr);
2083 lp->rx_ring = NULL;
2084 }
eabf0415
HWL		 2085}
2086
4a5e8e29 2087static int pcnet32_open(struct net_device *dev)
1da177e4 2088{
1e56a4b4 2089 struct pcnet32_private *lp = netdev_priv(dev);
63097b3a 2090 struct pci_dev *pdev = lp->pci_dev;
4a5e8e29
JG		 2091 unsigned long ioaddr = dev->base_addr;
2092 u16 val;
2093 int i;
2094 int rc;
2095 unsigned long flags;
2096
2097 if (request_irq(dev->irq, &pcnet32_interrupt,
1fb9df5d 2098 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
4a5e8e29
JG		 2099 (void *)dev)) {
2100 return -EAGAIN;
2101 }
2102
2103 spin_lock_irqsave(&lp->lock, flags);
2104 /* Check for a valid station address */
2105 if (!is_valid_ether_addr(dev->dev_addr)) {
2106 rc = -EINVAL;
2107 goto err_free_irq;
2108 }
2109
2110 /* Reset the PCNET32 */
2111 lp->a.reset(ioaddr);
2112
2113 /* switch pcnet32 to 32bit mode */
2114 lp->a.write_bcr(ioaddr, 20, 2);
2115
2116 if (netif_msg_ifup(lp))
2117 printk(KERN_DEBUG
2118 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2119 dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
2120 (u32) (lp->rx_ring_dma_addr),
6ecb7667 2121 (u32) (lp->init_dma_addr));
4a5e8e29
JG		 2122
2123 /* set/reset autoselect bit */
2124 val = lp->a.read_bcr(ioaddr, 2) & ~2;
2125 if (lp->options & PCNET32_PORT_ASEL)
1da177e4 2126 val |= 2;
4a5e8e29
JG		 2127 lp->a.write_bcr(ioaddr, 2, val);
2128
2129 /* handle full duplex setting */
2130 if (lp->mii_if.full_duplex) {
2131 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2132 if (lp->options & PCNET32_PORT_FD) {
2133 val |= 1;
2134 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2135 val |= 2;
2136 } else if (lp->options & PCNET32_PORT_ASEL) {
2137 /* workaround of xSeries250, turn on for 79C975 only */
8d916266 2138 if (lp->chip_version == 0x2627)
4a5e8e29
JG		 2139 val |= 3;
2140 }
2141 lp->a.write_bcr(ioaddr, 9, val);
2142 }
2143
2144 /* set/reset GPSI bit in test register */
2145 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2146 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2147 val |= 0x10;
2148 lp->a.write_csr(ioaddr, 124, val);
2149
2150 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
63097b3a
DF		 2151 if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2152 (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2153 pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
ac62ef04 2154 if (lp->options & PCNET32_PORT_ASEL) {
4a5e8e29
JG		 2155 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2156 if (netif_msg_link(lp))
2157 printk(KERN_DEBUG
2158 "%s: Setting 100Mb-Full Duplex.\n",
2159 dev->name);
2160 }
2161 }
2162 if (lp->phycount < 2) {
2163 /*
2164 * 24 Jun 2004 according AMD, in order to change the PHY,
2165 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2166 * duplex, and/or enable auto negotiation, and clear DANAS
2167 */
2168 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2169 lp->a.write_bcr(ioaddr, 32,
2170 lp->a.read_bcr(ioaddr, 32) | 0x0080);
2171 /* disable Auto Negotiation, set 10Mpbs, HD */
2172 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2173 if (lp->options & PCNET32_PORT_FD)
2174 val |= 0x10;
2175 if (lp->options & PCNET32_PORT_100)
2176 val |= 0x08;
2177 lp->a.write_bcr(ioaddr, 32, val);
2178 } else {
2179 if (lp->options & PCNET32_PORT_ASEL) {
2180 lp->a.write_bcr(ioaddr, 32,
2181 lp->a.read_bcr(ioaddr,
2182 32) | 0x0080);
2183 /* enable auto negotiate, setup, disable fd */
2184 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2185 val |= 0x20;
2186 lp->a.write_bcr(ioaddr, 32, val);
2187 }
2188 }
2189 } else {
2190 int first_phy = -1;
2191 u16 bmcr;
2192 u32 bcr9;
2193 struct ethtool_cmd ecmd;
2194
2195 /*
2196 * There is really no good other way to handle multiple PHYs
2197 * other than turning off all automatics
2198 */
2199 val = lp->a.read_bcr(ioaddr, 2);
2200 lp->a.write_bcr(ioaddr, 2, val & ~2);
2201 val = lp->a.read_bcr(ioaddr, 32);
2202 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2203
2204 if (!(lp->options & PCNET32_PORT_ASEL)) {
2205 /* setup ecmd */
2206 ecmd.port = PORT_MII;
2207 ecmd.transceiver = XCVR_INTERNAL;
2208 ecmd.autoneg = AUTONEG_DISABLE;
2209 ecmd.speed =
2210 lp->
2211 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2212 bcr9 = lp->a.read_bcr(ioaddr, 9);
2213
2214 if (lp->options & PCNET32_PORT_FD) {
2215 ecmd.duplex = DUPLEX_FULL;
2216 bcr9 |= (1 << 0);
2217 } else {
2218 ecmd.duplex = DUPLEX_HALF;
2219 bcr9 |= ~(1 << 0);
2220 }
2221 lp->a.write_bcr(ioaddr, 9, bcr9);
ac62ef04 2222 }
4a5e8e29
JG		 2223
2224 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2225 if (lp->phymask & (1 << i)) {
2226 /* isolate all but the first PHY */
2227 bmcr = mdio_read(dev, i, MII_BMCR);
2228 if (first_phy == -1) {
2229 first_phy = i;
2230 mdio_write(dev, i, MII_BMCR,
2231 bmcr & ~BMCR_ISOLATE);
2232 } else {
2233 mdio_write(dev, i, MII_BMCR,
2234 bmcr | BMCR_ISOLATE);
2235 }
2236 /* use mii_ethtool_sset to setup PHY */
2237 lp->mii_if.phy_id = i;
2238 ecmd.phy_address = i;
2239 if (lp->options & PCNET32_PORT_ASEL) {
2240 mii_ethtool_gset(&lp->mii_if, &ecmd);
2241 ecmd.autoneg = AUTONEG_ENABLE;
2242 }
2243 mii_ethtool_sset(&lp->mii_if, &ecmd);
2244 }
2245 }
2246 lp->mii_if.phy_id = first_phy;
2247 if (netif_msg_link(lp))
2248 printk(KERN_INFO "%s: Using PHY number %d.\n",
2249 dev->name, first_phy);
2250 }
1da177e4
LT		 2251
2252#ifdef DO_DXSUFLO
4a5e8e29 2253 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
b368a3fb 2254 val = lp->a.read_csr(ioaddr, CSR3);
4a5e8e29 2255 val |= 0x40;
b368a3fb 2256 lp->a.write_csr(ioaddr, CSR3, val);
4a5e8e29 2257 }
1da177e4
LT		 2258#endif
2259
6ecb7667 2260 lp->init_block->mode =
3e33545b 2261 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
4a5e8e29
JG		 2262 pcnet32_load_multicast(dev);
2263
2264 if (pcnet32_init_ring(dev)) {
2265 rc = -ENOMEM;
2266 goto err_free_ring;
2267 }
2268
bea3348e 2269 napi_enable(&lp->napi);
bea3348e 2270
4a5e8e29 2271 /* Re-initialize the PCNET32, and start it when done. */
6ecb7667
DF		 2272 lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2273 lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29 2274
b368a3fb
DF		 2275 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2276 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2277
2278 netif_start_queue(dev);
2279
8d916266
DF		 2280 if (lp->chip_version >= PCNET32_79C970A) {
2281 /* Print the link status and start the watchdog */
2282 pcnet32_check_media(dev, 1);
283a21d3 2283 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT);
8d916266 2284 }
4a5e8e29
JG		 2285
2286 i = 0;
2287 while (i++ < 100)
b368a3fb 2288 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29
JG		 2289 break;
2290 /*
2291 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2292 * reports that doing so triggers a bug in the '974.
2293 */
b368a3fb 2294 lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
4a5e8e29
JG		 2295
2296 if (netif_msg_ifup(lp))
2297 printk(KERN_DEBUG
2298 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2299 dev->name, i,
6ecb7667 2300 (u32) (lp->init_dma_addr),
b368a3fb 2301 lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2302
2303 spin_unlock_irqrestore(&lp->lock, flags);
2304
2305 return 0; /* Always succeed */
2306
2307 err_free_ring:
2308 /* free any allocated skbuffs */
ac5bfe40 2309 pcnet32_purge_rx_ring(dev);
4a5e8e29 2310
4a5e8e29
JG		 2311 /*
2312 * Switch back to 16bit mode to avoid problems with dumb
2313 * DOS packet driver after a warm reboot
2314 */
2315 lp->a.write_bcr(ioaddr, 20, 4);
2316
2317 err_free_irq:
2318 spin_unlock_irqrestore(&lp->lock, flags);
2319 free_irq(dev->irq, dev);
2320 return rc;
1da177e4
LT		 2321}
2322
2323/*
2324 * The LANCE has been halted for one reason or another (busmaster memory
2325 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2326 * etc.). Modern LANCE variants always reload their ring-buffer
2327 * configuration when restarted, so we must reinitialize our ring
2328 * context before restarting. As part of this reinitialization,
2329 * find all packets still on the Tx ring and pretend that they had been
2330 * sent (in effect, drop the packets on the floor) - the higher-level
2331 * protocols will time out and retransmit. It'd be better to shuffle
2332 * these skbs to a temp list and then actually re-Tx them after
2333 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2334 */
2335
4a5e8e29 2336static void pcnet32_purge_tx_ring(struct net_device *dev)
1da177e4 2337{
1e56a4b4 2338 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2339 int i;
1da177e4 2340
4a5e8e29
JG		 2341 for (i = 0; i < lp->tx_ring_size; i++) {
2342 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2343 wmb(); /* Make sure adapter sees owner change */
2344 if (lp->tx_skbuff[i]) {
2345 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2346 lp->tx_skbuff[i]->len,
2347 PCI_DMA_TODEVICE);
2348 dev_kfree_skb_any(lp->tx_skbuff[i]);
2349 }
2350 lp->tx_skbuff[i] = NULL;
2351 lp->tx_dma_addr[i] = 0;
2352 }
2353}
1da177e4
LT		 2354
2355/* Initialize the PCNET32 Rx and Tx rings. */
4a5e8e29 2356static int pcnet32_init_ring(struct net_device *dev)
1da177e4 2357{
1e56a4b4 2358 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2359 int i;
2360
2361 lp->tx_full = 0;
2362 lp->cur_rx = lp->cur_tx = 0;
2363 lp->dirty_rx = lp->dirty_tx = 0;
2364
2365 for (i = 0; i < lp->rx_ring_size; i++) {
2366 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2367 if (rx_skbuff == NULL) {
2368 if (!
2369 (rx_skbuff = lp->rx_skbuff[i] =
232c5640 2370 dev_alloc_skb(PKT_BUF_SKB))) {
4a5e8e29 2371 /* there is not much, we can do at this point */
b368a3fb 2372 if (netif_msg_drv(lp))
4a5e8e29
JG		 2373 printk(KERN_ERR
2374 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2375 dev->name);
2376 return -1;
2377 }
232c5640 2378 skb_reserve(rx_skbuff, NET_IP_ALIGN);
4a5e8e29
JG		 2379 }
2380
2381 rmb();
2382 if (lp->rx_dma_addr[i] == 0)
2383 lp->rx_dma_addr[i] =
2384 pci_map_single(lp->pci_dev, rx_skbuff->data,
232c5640 2385 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
3e33545b 2386 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
232c5640 2387 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
4a5e8e29 2388 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 2389 lp->rx_ring[i].status = cpu_to_le16(0x8000);
4a5e8e29
JG		 2390 }
2391 /* The Tx buffer address is filled in as needed, but we do need to clear
2392 * the upper ownership bit. */
2393 for (i = 0; i < lp->tx_ring_size; i++) {
2394 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2395 wmb(); /* Make sure adapter sees owner change */
2396 lp->tx_ring[i].base = 0;
2397 lp->tx_dma_addr[i] = 0;
2398 }
2399
6ecb7667 2400 lp->init_block->tlen_rlen =
3e33545b 2401 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
4a5e8e29 2402 for (i = 0; i < 6; i++)
6ecb7667 2403 lp->init_block->phys_addr[i] = dev->dev_addr[i];
3e33545b
AV		 2404 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2405 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
4a5e8e29
JG		 2406 wmb(); /* Make sure all changes are visible */
2407 return 0;
1da177e4
LT		 2408}
2409
2410/* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2411 * then flush the pending transmit operations, re-initialize the ring,
2412 * and tell the chip to initialize.
2413 */
4a5e8e29 2414static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1da177e4 2415{
1e56a4b4 2416 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2417 unsigned long ioaddr = dev->base_addr;
2418 int i;
1da177e4 2419
4a5e8e29
JG		 2420 /* wait for stop */
2421 for (i = 0; i < 100; i++)
b368a3fb 2422 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
4a5e8e29 2423 break;
1da177e4 2424
4a5e8e29
JG		 2425 if (i >= 100 && netif_msg_drv(lp))
2426 printk(KERN_ERR
2427 "%s: pcnet32_restart timed out waiting for stop.\n",
2428 dev->name);
1da177e4 2429
4a5e8e29
JG		 2430 pcnet32_purge_tx_ring(dev);
2431 if (pcnet32_init_ring(dev))
2432 return;
1da177e4 2433
4a5e8e29 2434 /* ReInit Ring */
b368a3fb 2435 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2436 i = 0;
2437 while (i++ < 1000)
b368a3fb 2438 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29 2439 break;
1da177e4 2440
b368a3fb 2441 lp->a.write_csr(ioaddr, CSR0, csr0_bits);
1da177e4
LT		 2442}
2443
4a5e8e29 2444static void pcnet32_tx_timeout(struct net_device *dev)
1da177e4 2445{
1e56a4b4 2446 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2447 unsigned long ioaddr = dev->base_addr, flags;
2448
2449 spin_lock_irqsave(&lp->lock, flags);
2450 /* Transmitter timeout, serious problems. */
2451 if (pcnet32_debug & NETIF_MSG_DRV)
2452 printk(KERN_ERR
2453 "%s: transmit timed out, status %4.4x, resetting.\n",
b368a3fb
DF		 2454 dev->name, lp->a.read_csr(ioaddr, CSR0));
2455 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
4f1e5ba0 2456 dev->stats.tx_errors++;
4a5e8e29
JG		 2457 if (netif_msg_tx_err(lp)) {
2458 int i;
2459 printk(KERN_DEBUG
2460 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2461 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2462 lp->cur_rx);
2463 for (i = 0; i < lp->rx_ring_size; i++)
2464 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2465 le32_to_cpu(lp->rx_ring[i].base),
2466 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2467 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2468 le16_to_cpu(lp->rx_ring[i].status));
2469 for (i = 0; i < lp->tx_ring_size; i++)
2470 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2471 le32_to_cpu(lp->tx_ring[i].base),
2472 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2473 le32_to_cpu(lp->tx_ring[i].misc),
2474 le16_to_cpu(lp->tx_ring[i].status));
2475 printk("\n");
2476 }
b368a3fb 2477 pcnet32_restart(dev, CSR0_NORMAL);
1da177e4 2478
4a5e8e29
JG		 2479 dev->trans_start = jiffies;
2480 netif_wake_queue(dev);
1da177e4 2481
4a5e8e29
JG		 2482 spin_unlock_irqrestore(&lp->lock, flags);
2483}
2484
61357325
SH		 2485static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb,
2486 struct net_device *dev)
1da177e4 2487{
1e56a4b4 2488 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2489 unsigned long ioaddr = dev->base_addr;
2490 u16 status;
2491 int entry;
2492 unsigned long flags;
1da177e4 2493
4a5e8e29 2494 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2495
4a5e8e29
JG		 2496 if (netif_msg_tx_queued(lp)) {
2497 printk(KERN_DEBUG
2498 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
b368a3fb 2499 dev->name, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29 2500 }
1da177e4 2501
4a5e8e29
JG		 2502 /* Default status -- will not enable Successful-TxDone
2503 * interrupt when that option is available to us.
2504 */
2505 status = 0x8300;
1da177e4 2506
4a5e8e29 2507 /* Fill in a Tx ring entry */
1da177e4 2508
4a5e8e29
JG		 2509 /* Mask to ring buffer boundary. */
2510 entry = lp->cur_tx & lp->tx_mod_mask;
1da177e4 2511
4a5e8e29
JG		 2512 /* Caution: the write order is important here, set the status
2513 * with the "ownership" bits last. */
1da177e4 2514
3e33545b 2515 lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
1da177e4 2516
4a5e8e29 2517 lp->tx_ring[entry].misc = 0x00000000;
1da177e4 2518
4a5e8e29
JG		 2519 lp->tx_skbuff[entry] = skb;
2520 lp->tx_dma_addr[entry] =
2521 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
3e33545b 2522 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
4a5e8e29 2523 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 2524 lp->tx_ring[entry].status = cpu_to_le16(status);
1da177e4 2525
4a5e8e29 2526 lp->cur_tx++;
4f1e5ba0 2527 dev->stats.tx_bytes += skb->len;
1da177e4 2528
4a5e8e29 2529 /* Trigger an immediate send poll. */
b368a3fb 2530 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
1da177e4 2531
4a5e8e29 2532 dev->trans_start = jiffies;
1da177e4 2533
4a5e8e29
JG		 2534 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2535 lp->tx_full = 1;
2536 netif_stop_queue(dev);
2537 }
2538 spin_unlock_irqrestore(&lp->lock, flags);
6ed10654 2539 return NETDEV_TX_OK;
1da177e4
LT		 2540}
2541
2542/* The PCNET32 interrupt handler. */
2543static irqreturn_t
7d12e780 2544pcnet32_interrupt(int irq, void *dev_id)
1da177e4 2545{
4a5e8e29
JG		 2546 struct net_device *dev = dev_id;
2547 struct pcnet32_private *lp;
2548 unsigned long ioaddr;
5c99346a 2549 u16 csr0;
4a5e8e29 2550 int boguscnt = max_interrupt_work;
4a5e8e29 2551
4a5e8e29 2552 ioaddr = dev->base_addr;
1e56a4b4 2553 lp = netdev_priv(dev);
1da177e4 2554
4a5e8e29
JG		 2555 spin_lock(&lp->lock);
2556
3904c324
DF		 2557 csr0 = lp->a.read_csr(ioaddr, CSR0);
2558 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
4a5e8e29
JG		 2559 if (csr0 == 0xffff) {
2560 break; /* PCMCIA remove happened */
2561 }
2562 /* Acknowledge all of the current interrupt sources ASAP. */
3904c324 2563 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
4a5e8e29 2564
4a5e8e29
JG		 2565 if (netif_msg_intr(lp))
2566 printk(KERN_DEBUG
2567 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
3904c324 2568 dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29 2569
4a5e8e29
JG		 2570 /* Log misc errors. */
2571 if (csr0 & 0x4000)
4f1e5ba0 2572 dev->stats.tx_errors++; /* Tx babble. */
4a5e8e29
JG		 2573 if (csr0 & 0x1000) {
2574 /*
3904c324
DF		 2575 * This happens when our receive ring is full. This
2576 * shouldn't be a problem as we will see normal rx
2577 * interrupts for the frames in the receive ring. But
2578 * there are some PCI chipsets (I can reproduce this
2579 * on SP3G with Intel saturn chipset) which have
2580 * sometimes problems and will fill up the receive
2581 * ring with error descriptors. In this situation we
2582 * don't get a rx interrupt, but a missed frame
7de745e5 2583 * interrupt sooner or later.
4a5e8e29 2584 */
4f1e5ba0 2585 dev->stats.rx_errors++; /* Missed a Rx frame. */
4a5e8e29
JG		 2586 }
2587 if (csr0 & 0x0800) {
2588 if (netif_msg_drv(lp))
2589 printk(KERN_ERR
2590 "%s: Bus master arbitration failure, status %4.4x.\n",
2591 dev->name, csr0);
2592 /* unlike for the lance, there is no restart needed */
1da177e4 2593 }
288379f0 2594 if (napi_schedule_prep(&lp->napi)) {
7de745e5
DF		 2595 u16 val;
2596 /* set interrupt masks */
2597 val = lp->a.read_csr(ioaddr, CSR3);
2598 val |= 0x5f00;
2599 lp->a.write_csr(ioaddr, CSR3, val);
ce105a08 2600
288379f0 2601 __napi_schedule(&lp->napi);
7de745e5
DF		 2602 break;
2603 }
3904c324 2604 csr0 = lp->a.read_csr(ioaddr, CSR0);
4a5e8e29
JG		 2605 }
2606
4a5e8e29
JG		 2607 if (netif_msg_intr(lp))
2608 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
b368a3fb 2609 dev->name, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2610
2611 spin_unlock(&lp->lock);
2612
2613 return IRQ_HANDLED;
1da177e4
LT		 2614}
2615
4a5e8e29 2616static int pcnet32_close(struct net_device *dev)
1da177e4 2617{
4a5e8e29 2618 unsigned long ioaddr = dev->base_addr;
1e56a4b4 2619 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2620 unsigned long flags;
1da177e4 2621
4a5e8e29 2622 del_timer_sync(&lp->watchdog_timer);
1da177e4 2623
4a5e8e29 2624 netif_stop_queue(dev);
bea3348e 2625 napi_disable(&lp->napi);
1da177e4 2626
4a5e8e29 2627 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2628
4f1e5ba0 2629 dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
1da177e4 2630
4a5e8e29
JG		 2631 if (netif_msg_ifdown(lp))
2632 printk(KERN_DEBUG
2633 "%s: Shutting down ethercard, status was %2.2x.\n",
b368a3fb 2634 dev->name, lp->a.read_csr(ioaddr, CSR0));
1da177e4 2635
4a5e8e29 2636 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
b368a3fb 2637 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
1da177e4 2638
4a5e8e29
JG		 2639 /*
2640 * Switch back to 16bit mode to avoid problems with dumb
2641 * DOS packet driver after a warm reboot
2642 */
2643 lp->a.write_bcr(ioaddr, 20, 4);
1da177e4 2644
4a5e8e29 2645 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2646
4a5e8e29 2647 free_irq(dev->irq, dev);
1da177e4 2648
4a5e8e29 2649 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2650
ac5bfe40
DF		 2651 pcnet32_purge_rx_ring(dev);
2652 pcnet32_purge_tx_ring(dev);
1da177e4 2653
4a5e8e29 2654 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2655
4a5e8e29 2656 return 0;
1da177e4
LT		 2657}
2658
4a5e8e29 2659static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
1da177e4 2660{
1e56a4b4 2661 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2662 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2663 unsigned long flags;
2664
2665 spin_lock_irqsave(&lp->lock, flags);
4f1e5ba0 2666 dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
4a5e8e29
JG		 2667 spin_unlock_irqrestore(&lp->lock, flags);
2668
4f1e5ba0 2669 return &dev->stats;
1da177e4
LT		 2670}
2671
2672/* taken from the sunlance driver, which it took from the depca driver */
4a5e8e29 2673static void pcnet32_load_multicast(struct net_device *dev)
1da177e4 2674{
1e56a4b4 2675 struct pcnet32_private *lp = netdev_priv(dev);
6ecb7667 2676 volatile struct pcnet32_init_block *ib = lp->init_block;
3e33545b 2677 volatile __le16 *mcast_table = (__le16 *)ib->filter;
4a5e8e29 2678 struct dev_mc_list *dmi = dev->mc_list;
df27f4a6 2679 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2680 char *addrs;
2681 int i;
2682 u32 crc;
2683
2684 /* set all multicast bits */
2685 if (dev->flags & IFF_ALLMULTI) {
3e33545b
AV		 2686 ib->filter[0] = cpu_to_le32(~0U);
2687 ib->filter[1] = cpu_to_le32(~0U);
df27f4a6
DF		 2688 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2689 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2690 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2691 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
4a5e8e29
JG		 2692 return;
2693 }
2694 /* clear the multicast filter */
2695 ib->filter[0] = 0;
2696 ib->filter[1] = 0;
2697
2698 /* Add addresses */
2699 for (i = 0; i < dev->mc_count; i++) {
2700 addrs = dmi->dmi_addr;
2701 dmi = dmi->next;
2702
2703 /* multicast address? */
2704 if (!(*addrs & 1))
2705 continue;
2706
2707 crc = ether_crc_le(6, addrs);
2708 crc = crc >> 26;
3e33545b 2709 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
4a5e8e29 2710 }
df27f4a6
DF		 2711 for (i = 0; i < 4; i++)
2712 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2713 le16_to_cpu(mcast_table[i]));
1da177e4 2714 return;
1da177e4
LT		 2715}
2716
1da177e4
LT		 2717/*
2718 * Set or clear the multicast filter for this adaptor.
2719 */
2720static void pcnet32_set_multicast_list(struct net_device *dev)
2721{
4a5e8e29 2722 unsigned long ioaddr = dev->base_addr, flags;
1e56a4b4 2723 struct pcnet32_private *lp = netdev_priv(dev);
df27f4a6 2724 int csr15, suspended;
4a5e8e29
JG		 2725
2726 spin_lock_irqsave(&lp->lock, flags);
df27f4a6
DF		 2727 suspended = pcnet32_suspend(dev, &flags, 0);
2728 csr15 = lp->a.read_csr(ioaddr, CSR15);
4a5e8e29
JG		 2729 if (dev->flags & IFF_PROMISC) {
2730 /* Log any net taps. */
2731 if (netif_msg_hw(lp))
2732 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2733 dev->name);
6ecb7667 2734 lp->init_block->mode =
3e33545b 2735 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
4a5e8e29 2736 7);
df27f4a6 2737 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
4a5e8e29 2738 } else {
6ecb7667 2739 lp->init_block->mode =
3e33545b 2740 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
df27f4a6 2741 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
4a5e8e29
JG		 2742 pcnet32_load_multicast(dev);
2743 }
2744
df27f4a6
DF		 2745 if (suspended) {
2746 int csr5;
2747 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2748 csr5 = lp->a.read_csr(ioaddr, CSR5);
2749 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
b368a3fb 2750 } else {
df27f4a6
DF		 2751 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2752 pcnet32_restart(dev, CSR0_NORMAL);
2753 netif_wake_queue(dev);
2754 }
4a5e8e29
JG		 2755
2756 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 2757}
2758
2759/* This routine assumes that the lp->lock is held */
2760static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2761{
1e56a4b4 2762 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2763 unsigned long ioaddr = dev->base_addr;
2764 u16 val_out;
1da177e4 2765
4a5e8e29
JG		 2766 if (!lp->mii)
2767 return 0;
1da177e4 2768
4a5e8e29
JG		 2769 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2770 val_out = lp->a.read_bcr(ioaddr, 34);
1da177e4 2771
4a5e8e29 2772 return val_out;
1da177e4
LT		 2773}
2774
2775/* This routine assumes that the lp->lock is held */
2776static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2777{
1e56a4b4 2778 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2779 unsigned long ioaddr = dev->base_addr;
1da177e4 2780
4a5e8e29
JG		 2781 if (!lp->mii)
2782 return;
1da177e4 2783
4a5e8e29
JG		 2784 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2785 lp->a.write_bcr(ioaddr, 34, val);
1da177e4
LT		 2786}
2787
2788static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2789{
1e56a4b4 2790 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2791 int rc;
2792 unsigned long flags;
1da177e4 2793
4a5e8e29
JG		 2794 /* SIOC[GS]MIIxxx ioctls */
2795 if (lp->mii) {
2796 spin_lock_irqsave(&lp->lock, flags);
2797 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2798 spin_unlock_irqrestore(&lp->lock, flags);
2799 } else {
2800 rc = -EOPNOTSUPP;
2801 }
1da177e4 2802
4a5e8e29 2803 return rc;
1da177e4
LT		 2804}
2805
ac62ef04
DF		 2806static int pcnet32_check_otherphy(struct net_device *dev)
2807{
1e56a4b4 2808 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2809 struct mii_if_info mii = lp->mii_if;
2810 u16 bmcr;
2811 int i;
ac62ef04 2812
4a5e8e29
JG		 2813 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2814 if (i == lp->mii_if.phy_id)
2815 continue; /* skip active phy */
2816 if (lp->phymask & (1 << i)) {
2817 mii.phy_id = i;
2818 if (mii_link_ok(&mii)) {
2819 /* found PHY with active link */
2820 if (netif_msg_link(lp))
2821 printk(KERN_INFO
2822 "%s: Using PHY number %d.\n",
2823 dev->name, i);
2824
2825 /* isolate inactive phy */
2826 bmcr =
2827 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2828 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2829 bmcr | BMCR_ISOLATE);
2830
2831 /* de-isolate new phy */
2832 bmcr = mdio_read(dev, i, MII_BMCR);
2833 mdio_write(dev, i, MII_BMCR,
2834 bmcr & ~BMCR_ISOLATE);
2835
2836 /* set new phy address */
2837 lp->mii_if.phy_id = i;
2838 return 1;
2839 }
2840 }
ac62ef04 2841 }
4a5e8e29 2842 return 0;
ac62ef04
DF		 2843}
2844
2845/*
2846 * Show the status of the media. Similar to mii_check_media however it
2847 * correctly shows the link speed for all (tested) pcnet32 variants.
2848 * Devices with no mii just report link state without speed.
2849 *
2850 * Caller is assumed to hold and release the lp->lock.
2851 */
2852
2853static void pcnet32_check_media(struct net_device *dev, int verbose)
2854{
1e56a4b4 2855 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2856 int curr_link;
2857 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2858 u32 bcr9;
2859
ac62ef04 2860 if (lp->mii) {
4a5e8e29 2861 curr_link = mii_link_ok(&lp->mii_if);
ac62ef04 2862 } else {
4a5e8e29
JG		 2863 ulong ioaddr = dev->base_addr; /* card base I/O address */
2864 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2865 }
2866 if (!curr_link) {
2867 if (prev_link || verbose) {
2868 netif_carrier_off(dev);
2869 if (netif_msg_link(lp))
2870 printk(KERN_INFO "%s: link down\n", dev->name);
2871 }
2872 if (lp->phycount > 1) {
2873 curr_link = pcnet32_check_otherphy(dev);
2874 prev_link = 0;
2875 }
2876 } else if (verbose || !prev_link) {
2877 netif_carrier_on(dev);
2878 if (lp->mii) {
2879 if (netif_msg_link(lp)) {
2880 struct ethtool_cmd ecmd;
2881 mii_ethtool_gset(&lp->mii_if, &ecmd);
2882 printk(KERN_INFO
2883 "%s: link up, %sMbps, %s-duplex\n",
2884 dev->name,
2885 (ecmd.speed == SPEED_100) ? "100" : "10",
2886 (ecmd.duplex ==
2887 DUPLEX_FULL) ? "full" : "half");
2888 }
2889 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2890 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2891 if (lp->mii_if.full_duplex)
2892 bcr9 |= (1 << 0);
2893 else
2894 bcr9 &= ~(1 << 0);
2895 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2896 }
2897 } else {
2898 if (netif_msg_link(lp))
2899 printk(KERN_INFO "%s: link up\n", dev->name);
2900 }
ac62ef04 2901 }
ac62ef04
DF		 2902}
2903
2904/*
2905 * Check for loss of link and link establishment.
2906 * Can not use mii_check_media because it does nothing if mode is forced.
2907 */
2908
1da177e4
LT		 2909static void pcnet32_watchdog(struct net_device *dev)
2910{
1e56a4b4 2911 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2912 unsigned long flags;
1da177e4 2913
4a5e8e29
JG		 2914 /* Print the link status if it has changed */
2915 spin_lock_irqsave(&lp->lock, flags);
2916 pcnet32_check_media(dev, 0);
2917 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2918
283a21d3 2919 mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT));
1da177e4
LT		 2920}
2921
917270c6
DF		 2922static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2923{
2924 struct net_device *dev = pci_get_drvdata(pdev);
2925
2926 if (netif_running(dev)) {
2927 netif_device_detach(dev);
2928 pcnet32_close(dev);
2929 }
2930 pci_save_state(pdev);
2931 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2932 return 0;
2933}
2934
2935static int pcnet32_pm_resume(struct pci_dev *pdev)
2936{
2937 struct net_device *dev = pci_get_drvdata(pdev);
2938
2939 pci_set_power_state(pdev, PCI_D0);
2940 pci_restore_state(pdev);
2941
2942 if (netif_running(dev)) {
2943 pcnet32_open(dev);
2944 netif_device_attach(dev);
2945 }
2946 return 0;
2947}
2948
1da177e4
LT		 2949static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2950{
4a5e8e29
JG		 2951 struct net_device *dev = pci_get_drvdata(pdev);
2952
2953 if (dev) {
1e56a4b4 2954 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2955
2956 unregister_netdev(dev);
2957 pcnet32_free_ring(dev);
2958 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
7d2e3cb7 2959 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 2960 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 2961 free_netdev(dev);
2962 pci_disable_device(pdev);
2963 pci_set_drvdata(pdev, NULL);
2964 }
1da177e4
LT		 2965}
2966
2967static struct pci_driver pcnet32_driver = {
4a5e8e29
JG		 2968 .name = DRV_NAME,
2969 .probe = pcnet32_probe_pci,
2970 .remove = __devexit_p(pcnet32_remove_one),
2971 .id_table = pcnet32_pci_tbl,
917270c6
DF		 2972 .suspend = pcnet32_pm_suspend,
2973 .resume = pcnet32_pm_resume,
1da177e4
LT		 2974};
2975
2976/* An additional parameter that may be passed in... */
2977static int debug = -1;
2978static int tx_start_pt = -1;
2979static int pcnet32_have_pci;
2980
2981module_param(debug, int, 0);
2982MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2983module_param(max_interrupt_work, int, 0);
4a5e8e29
JG		 2984MODULE_PARM_DESC(max_interrupt_work,
2985 DRV_NAME " maximum events handled per interrupt");
1da177e4 2986module_param(rx_copybreak, int, 0);
4a5e8e29
JG		 2987MODULE_PARM_DESC(rx_copybreak,
2988 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 2989module_param(tx_start_pt, int, 0);
2990MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2991module_param(pcnet32vlb, int, 0);
2992MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2993module_param_array(options, int, NULL, 0);
2994MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2995module_param_array(full_duplex, int, NULL, 0);
2996MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2997/* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2998module_param_array(homepna, int, NULL, 0);
4a5e8e29
JG		 2999MODULE_PARM_DESC(homepna,
3000 DRV_NAME
3001 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
1da177e4
LT		 3002
3003MODULE_AUTHOR("Thomas Bogendoerfer");
3004MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3005MODULE_LICENSE("GPL");
3006
3007#define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3008
3009static int __init pcnet32_init_module(void)
3010{
4a5e8e29 3011 printk(KERN_INFO "%s", version);
1da177e4 3012
4a5e8e29 3013 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
1da177e4 3014
4a5e8e29
JG		 3015 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3016 tx_start = tx_start_pt;
1da177e4 3017
4a5e8e29 3018 /* find the PCI devices */
29917620 3019 if (!pci_register_driver(&pcnet32_driver))
4a5e8e29 3020 pcnet32_have_pci = 1;
1da177e4 3021
4a5e8e29
JG		 3022 /* should we find any remaining VLbus devices ? */
3023 if (pcnet32vlb)
dcaf9769 3024 pcnet32_probe_vlbus(pcnet32_portlist);
1da177e4 3025
4a5e8e29
JG		 3026 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3027 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
1da177e4 3028
4a5e8e29 3029 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
1da177e4
LT		 3030}
3031
3032static void __exit pcnet32_cleanup_module(void)
3033{
4a5e8e29
JG		 3034 struct net_device *next_dev;
3035
3036 while (pcnet32_dev) {
1e56a4b4 3037 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
4a5e8e29
JG		 3038 next_dev = lp->next;
3039 unregister_netdev(pcnet32_dev);
3040 pcnet32_free_ring(pcnet32_dev);
3041 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
7d2e3cb7 3042 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 3043 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 3044 free_netdev(pcnet32_dev);
3045 pcnet32_dev = next_dev;
3046 }
1da177e4 3047
4a5e8e29
JG		 3048 if (pcnet32_have_pci)
3049 pci_unregister_driver(&pcnet32_driver);
1da177e4
LT		 3050}
3051
3052module_init(pcnet32_init_module);
3053module_exit(pcnet32_cleanup_module);
3054
3055/*
3056 * Local variables:
3057 * c-indent-level: 4
3058 * tab-width: 8
3059 * End:
3060 */
Clone of davem's net-next-2.6 tree