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tg3: Refine phylib support
[net-next-2.6.git] / drivers / net / pcnet32.c
CommitLineData
1da177e4
LT		 1/* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2/*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15/**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24#define DRV_NAME "pcnet32"
01935d7d
DF		 25#define DRV_VERSION "1.35"
26#define DRV_RELDATE "21.Apr.2008"
1da177e4
LT		 27#define PFX DRV_NAME ": "
28
4a5e8e29
JG		 29static const char *const version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
1da177e4
LT		 31
32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/string.h>
35#include <linux/errno.h>
36#include <linux/ioport.h>
37#include <linux/slab.h>
38#include <linux/interrupt.h>
39#include <linux/pci.h>
40#include <linux/delay.h>
41#include <linux/init.h>
42#include <linux/ethtool.h>
43#include <linux/mii.h>
44#include <linux/crc32.h>
45#include <linux/netdevice.h>
46#include <linux/etherdevice.h>
47#include <linux/skbuff.h>
48#include <linux/spinlock.h>
49#include <linux/moduleparam.h>
50#include <linux/bitops.h>
51
52#include <asm/dma.h>
53#include <asm/io.h>
54#include <asm/uaccess.h>
55#include <asm/irq.h>
56
57/*
58 * PCI device identifiers for "new style" Linux PCI Device Drivers
59 */
60static struct pci_device_id pcnet32_pci_tbl[] = {
f2622a2b
DF		 61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
4a5e8e29
JG		 63
64 /*
65 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
66 * the incorrect vendor id.
67 */
f2622a2b
DF		 68 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
69 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
4a5e8e29
JG		 70
71 { } /* terminate list */
1da177e4
LT		 72};
73
4a5e8e29 74MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
1da177e4
LT		 75
76static int cards_found;
77
78/*
79 * VLB I/O addresses
80 */
81static unsigned int pcnet32_portlist[] __initdata =
4a5e8e29 82 { 0x300, 0x320, 0x340, 0x360, 0 };
1da177e4
LT		 83
84static int pcnet32_debug = 0;
4a5e8e29
JG		 85static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
86static int pcnet32vlb; /* check for VLB cards ? */
1da177e4
LT		 87
88static struct net_device *pcnet32_dev;
89
90static int max_interrupt_work = 2;
91static int rx_copybreak = 200;
92
93#define PCNET32_PORT_AUI 0x00
94#define PCNET32_PORT_10BT 0x01
95#define PCNET32_PORT_GPSI 0x02
96#define PCNET32_PORT_MII 0x03
97
98#define PCNET32_PORT_PORTSEL 0x03
99#define PCNET32_PORT_ASEL 0x04
100#define PCNET32_PORT_100 0x40
101#define PCNET32_PORT_FD 0x80
102
103#define PCNET32_DMA_MASK 0xffffffff
104
105#define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
106#define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
107
108/*
109 * table to translate option values from tulip
110 * to internal options
111 */
f71e1309 112static const unsigned char options_mapping[] = {
4a5e8e29
JG		 113 PCNET32_PORT_ASEL, /* 0 Auto-select */
114 PCNET32_PORT_AUI, /* 1 BNC/AUI */
115 PCNET32_PORT_AUI, /* 2 AUI/BNC */
116 PCNET32_PORT_ASEL, /* 3 not supported */
117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
118 PCNET32_PORT_ASEL, /* 5 not supported */
119 PCNET32_PORT_ASEL, /* 6 not supported */
120 PCNET32_PORT_ASEL, /* 7 not supported */
121 PCNET32_PORT_ASEL, /* 8 not supported */
122 PCNET32_PORT_MII, /* 9 MII 10baseT */
123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
124 PCNET32_PORT_MII, /* 11 MII (autosel) */
125 PCNET32_PORT_10BT, /* 12 10BaseT */
126 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
127 /* 14 MII 100BaseTx-FD */
128 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
129 PCNET32_PORT_ASEL /* 15 not supported */
1da177e4
LT		 130};
131
132static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
4a5e8e29 133 "Loopback test (offline)"
1da177e4 134};
4a5e8e29 135
4c3616cd 136#define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test)
1da177e4 137
ac62ef04 138#define PCNET32_NUM_REGS 136
1da177e4 139
4a5e8e29 140#define MAX_UNITS 8 /* More are supported, limit only on options */
1da177e4
LT		 141static int options[MAX_UNITS];
142static int full_duplex[MAX_UNITS];
143static int homepna[MAX_UNITS];
144
145/*
146 * Theory of Operation
147 *
148 * This driver uses the same software structure as the normal lance
149 * driver. So look for a verbose description in lance.c. The differences
150 * to the normal lance driver is the use of the 32bit mode of PCnet32
151 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
152 * 16MB limitation and we don't need bounce buffers.
153 */
154
1da177e4
LT		 155/*
156 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
157 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
158 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
159 */
160#ifndef PCNET32_LOG_TX_BUFFERS
eabf0415
HWL		 161#define PCNET32_LOG_TX_BUFFERS 4
162#define PCNET32_LOG_RX_BUFFERS 5
163#define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
164#define PCNET32_LOG_MAX_RX_BUFFERS 9
1da177e4
LT		 165#endif
166
167#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
eabf0415 168#define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
1da177e4
LT		 169
170#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
eabf0415 171#define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
1da177e4 172
232c5640
DF		 173#define PKT_BUF_SKB 1544
174/* actual buffer length after being aligned */
175#define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN)
176/* chip wants twos complement of the (aligned) buffer length */
177#define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB)
1da177e4
LT		 178
179/* Offsets from base I/O address. */
180#define PCNET32_WIO_RDP 0x10
181#define PCNET32_WIO_RAP 0x12
182#define PCNET32_WIO_RESET 0x14
183#define PCNET32_WIO_BDP 0x16
184
185#define PCNET32_DWIO_RDP 0x10
186#define PCNET32_DWIO_RAP 0x14
187#define PCNET32_DWIO_RESET 0x18
188#define PCNET32_DWIO_BDP 0x1C
189
190#define PCNET32_TOTAL_SIZE 0x20
191
06c87850
DF		 192#define CSR0 0
193#define CSR0_INIT 0x1
194#define CSR0_START 0x2
195#define CSR0_STOP 0x4
196#define CSR0_TXPOLL 0x8
197#define CSR0_INTEN 0x40
198#define CSR0_IDON 0x0100
199#define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
200#define PCNET32_INIT_LOW 1
201#define PCNET32_INIT_HIGH 2
202#define CSR3 3
203#define CSR4 4
204#define CSR5 5
205#define CSR5_SUSPEND 0x0001
206#define CSR15 15
207#define PCNET32_MC_FILTER 8
208
8d916266
DF		 209#define PCNET32_79C970A 0x2621
210
1da177e4
LT		 211/* The PCNET32 Rx and Tx ring descriptors. */
212struct pcnet32_rx_head {
3e33545b
AV		 213 __le32 base;
214 __le16 buf_length; /* two`s complement of length */
215 __le16 status;
216 __le32 msg_length;
217 __le32 reserved;
1da177e4
LT		 218};
219
220struct pcnet32_tx_head {
3e33545b
AV		 221 __le32 base;
222 __le16 length; /* two`s complement of length */
223 __le16 status;
224 __le32 misc;
225 __le32 reserved;
1da177e4
LT		 226};
227
228/* The PCNET32 32-Bit initialization block, described in databook. */
229struct pcnet32_init_block {
3e33545b
AV		 230 __le16 mode;
231 __le16 tlen_rlen;
0b5bf225 232 u8 phys_addr[6];
3e33545b
AV		 233 __le16 reserved;
234 __le32 filter[2];
4a5e8e29 235 /* Receive and transmit ring base, along with extra bits. */
3e33545b
AV		 236 __le32 rx_ring;
237 __le32 tx_ring;
1da177e4
LT		 238};
239
240/* PCnet32 access functions */
241struct pcnet32_access {
4a5e8e29
JG		 242 u16 (*read_csr) (unsigned long, int);
243 void (*write_csr) (unsigned long, int, u16);
244 u16 (*read_bcr) (unsigned long, int);
245 void (*write_bcr) (unsigned long, int, u16);
246 u16 (*read_rap) (unsigned long);
247 void (*write_rap) (unsigned long, u16);
248 void (*reset) (unsigned long);
1da177e4
LT		 249};
250
251/*
76209926
HWL		 252 * The first field of pcnet32_private is read by the ethernet device
253 * so the structure should be allocated using pci_alloc_consistent().
1da177e4
LT		 254 */
255struct pcnet32_private {
6ecb7667 256 struct pcnet32_init_block *init_block;
4a5e8e29 257 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
0b5bf225
JG		 258 struct pcnet32_rx_head *rx_ring;
259 struct pcnet32_tx_head *tx_ring;
6ecb7667
DF		 260 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,
261 returned by pci_alloc_consistent */
0b5bf225
JG		 262 struct pci_dev *pci_dev;
263 const char *name;
4a5e8e29 264 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
0b5bf225
JG		 265 struct sk_buff **tx_skbuff;
266 struct sk_buff **rx_skbuff;
267 dma_addr_t *tx_dma_addr;
268 dma_addr_t *rx_dma_addr;
269 struct pcnet32_access a;
270 spinlock_t lock; /* Guard lock */
271 unsigned int cur_rx, cur_tx; /* The next free ring entry */
272 unsigned int rx_ring_size; /* current rx ring size */
273 unsigned int tx_ring_size; /* current tx ring size */
274 unsigned int rx_mod_mask; /* rx ring modular mask */
275 unsigned int tx_mod_mask; /* tx ring modular mask */
276 unsigned short rx_len_bits;
277 unsigned short tx_len_bits;
278 dma_addr_t rx_ring_dma_addr;
279 dma_addr_t tx_ring_dma_addr;
280 unsigned int dirty_rx, /* ring entries to be freed. */
281 dirty_tx;
282
bea3348e
SH		 283 struct net_device *dev;
284 struct napi_struct napi;
0b5bf225
JG		 285 char tx_full;
286 char phycount; /* number of phys found */
287 int options;
288 unsigned int shared_irq:1, /* shared irq possible */
289 dxsuflo:1, /* disable transmit stop on uflo */
290 mii:1; /* mii port available */
291 struct net_device *next;
292 struct mii_if_info mii_if;
293 struct timer_list watchdog_timer;
294 struct timer_list blink_timer;
295 u32 msg_enable; /* debug message level */
4a5e8e29
JG		 296
297 /* each bit indicates an available PHY */
0b5bf225 298 u32 phymask;
8d916266 299 unsigned short chip_version; /* which variant this is */
1da177e4
LT		 300};
301
4a5e8e29
JG		 302static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
303static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
304static int pcnet32_open(struct net_device *);
305static int pcnet32_init_ring(struct net_device *);
306static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
4a5e8e29 307static void pcnet32_tx_timeout(struct net_device *dev);
7d12e780 308static irqreturn_t pcnet32_interrupt(int, void *);
4a5e8e29 309static int pcnet32_close(struct net_device *);
1da177e4
LT		 310static struct net_device_stats *pcnet32_get_stats(struct net_device *);
311static void pcnet32_load_multicast(struct net_device *dev);
312static void pcnet32_set_multicast_list(struct net_device *);
4a5e8e29 313static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
1da177e4
LT		 314static void pcnet32_watchdog(struct net_device *);
315static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
4a5e8e29
JG		 316static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
317 int val);
1da177e4
LT		 318static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
319static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29
JG		 320 struct ethtool_test *eth_test, u64 * data);
321static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
1da177e4
LT		 322static int pcnet32_phys_id(struct net_device *dev, u32 data);
323static void pcnet32_led_blink_callback(struct net_device *dev);
324static int pcnet32_get_regs_len(struct net_device *dev);
325static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 326 void *ptr);
1bcd3153 327static void pcnet32_purge_tx_ring(struct net_device *dev);
b166cfba 328static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
eabf0415 329static void pcnet32_free_ring(struct net_device *dev);
ac62ef04 330static void pcnet32_check_media(struct net_device *dev, int verbose);
eabf0415 331
4a5e8e29 332static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
1da177e4 333{
4a5e8e29
JG		 334 outw(index, addr + PCNET32_WIO_RAP);
335 return inw(addr + PCNET32_WIO_RDP);
1da177e4
LT		 336}
337
4a5e8e29 338static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 339{
4a5e8e29
JG		 340 outw(index, addr + PCNET32_WIO_RAP);
341 outw(val, addr + PCNET32_WIO_RDP);
1da177e4
LT		 342}
343
4a5e8e29 344static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
1da177e4 345{
4a5e8e29
JG		 346 outw(index, addr + PCNET32_WIO_RAP);
347 return inw(addr + PCNET32_WIO_BDP);
1da177e4
LT		 348}
349
4a5e8e29 350static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 351{
4a5e8e29
JG		 352 outw(index, addr + PCNET32_WIO_RAP);
353 outw(val, addr + PCNET32_WIO_BDP);
1da177e4
LT		 354}
355
4a5e8e29 356static u16 pcnet32_wio_read_rap(unsigned long addr)
1da177e4 357{
4a5e8e29 358 return inw(addr + PCNET32_WIO_RAP);
1da177e4
LT		 359}
360
4a5e8e29 361static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
1da177e4 362{
4a5e8e29 363 outw(val, addr + PCNET32_WIO_RAP);
1da177e4
LT		 364}
365
4a5e8e29 366static void pcnet32_wio_reset(unsigned long addr)
1da177e4 367{
4a5e8e29 368 inw(addr + PCNET32_WIO_RESET);
1da177e4
LT		 369}
370
4a5e8e29 371static int pcnet32_wio_check(unsigned long addr)
1da177e4 372{
4a5e8e29
JG		 373 outw(88, addr + PCNET32_WIO_RAP);
374 return (inw(addr + PCNET32_WIO_RAP) == 88);
1da177e4
LT		 375}
376
377static struct pcnet32_access pcnet32_wio = {
4a5e8e29
JG		 378 .read_csr = pcnet32_wio_read_csr,
379 .write_csr = pcnet32_wio_write_csr,
380 .read_bcr = pcnet32_wio_read_bcr,
381 .write_bcr = pcnet32_wio_write_bcr,
382 .read_rap = pcnet32_wio_read_rap,
383 .write_rap = pcnet32_wio_write_rap,
384 .reset = pcnet32_wio_reset
1da177e4
LT		 385};
386
4a5e8e29 387static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
1da177e4 388{
4a5e8e29
JG		 389 outl(index, addr + PCNET32_DWIO_RAP);
390 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
1da177e4
LT		 391}
392
4a5e8e29 393static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 394{
4a5e8e29
JG		 395 outl(index, addr + PCNET32_DWIO_RAP);
396 outl(val, addr + PCNET32_DWIO_RDP);
1da177e4
LT		 397}
398
4a5e8e29 399static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
1da177e4 400{
4a5e8e29
JG		 401 outl(index, addr + PCNET32_DWIO_RAP);
402 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
1da177e4
LT		 403}
404
4a5e8e29 405static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 406{
4a5e8e29
JG		 407 outl(index, addr + PCNET32_DWIO_RAP);
408 outl(val, addr + PCNET32_DWIO_BDP);
1da177e4
LT		 409}
410
4a5e8e29 411static u16 pcnet32_dwio_read_rap(unsigned long addr)
1da177e4 412{
4a5e8e29 413 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
1da177e4
LT		 414}
415
4a5e8e29 416static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
1da177e4 417{
4a5e8e29 418 outl(val, addr + PCNET32_DWIO_RAP);
1da177e4
LT		 419}
420
4a5e8e29 421static void pcnet32_dwio_reset(unsigned long addr)
1da177e4 422{
4a5e8e29 423 inl(addr + PCNET32_DWIO_RESET);
1da177e4
LT		 424}
425
4a5e8e29 426static int pcnet32_dwio_check(unsigned long addr)
1da177e4 427{
4a5e8e29
JG		 428 outl(88, addr + PCNET32_DWIO_RAP);
429 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
1da177e4
LT		 430}
431
432static struct pcnet32_access pcnet32_dwio = {
4a5e8e29
JG		 433 .read_csr = pcnet32_dwio_read_csr,
434 .write_csr = pcnet32_dwio_write_csr,
435 .read_bcr = pcnet32_dwio_read_bcr,
436 .write_bcr = pcnet32_dwio_write_bcr,
437 .read_rap = pcnet32_dwio_read_rap,
438 .write_rap = pcnet32_dwio_write_rap,
439 .reset = pcnet32_dwio_reset
1da177e4
LT		 440};
441
06c87850
DF		 442static void pcnet32_netif_stop(struct net_device *dev)
443{
bea3348e 444 struct pcnet32_private *lp = netdev_priv(dev);
01935d7d 445
06c87850 446 dev->trans_start = jiffies;
bea3348e 447 napi_disable(&lp->napi);
06c87850
DF		 448 netif_tx_disable(dev);
449}
450
451static void pcnet32_netif_start(struct net_device *dev)
452{
bea3348e 453 struct pcnet32_private *lp = netdev_priv(dev);
d1d08d12
DM		 454 ulong ioaddr = dev->base_addr;
455 u16 val;
01935d7d 456
06c87850 457 netif_wake_queue(dev);
d1d08d12
DM		 458 val = lp->a.read_csr(ioaddr, CSR3);
459 val &= 0x00ff;
460 lp->a.write_csr(ioaddr, CSR3, val);
bea3348e 461 napi_enable(&lp->napi);
06c87850
DF		 462}
463
464/*
465 * Allocate space for the new sized tx ring.
466 * Free old resources
467 * Save new resources.
468 * Any failure keeps old resources.
469 * Must be called with lp->lock held.
470 */
471static void pcnet32_realloc_tx_ring(struct net_device *dev,
472 struct pcnet32_private *lp,
473 unsigned int size)
474{
475 dma_addr_t new_ring_dma_addr;
476 dma_addr_t *new_dma_addr_list;
477 struct pcnet32_tx_head *new_tx_ring;
478 struct sk_buff **new_skb_list;
479
480 pcnet32_purge_tx_ring(dev);
481
482 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
483 sizeof(struct pcnet32_tx_head) *
484 (1 << size),
485 &new_ring_dma_addr);
486 if (new_tx_ring == NULL) {
487 if (netif_msg_drv(lp))
488 printk("\n" KERN_ERR
489 "%s: Consistent memory allocation failed.\n",
490 dev->name);
491 return;
492 }
493 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
494
495 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
496 GFP_ATOMIC);
497 if (!new_dma_addr_list) {
498 if (netif_msg_drv(lp))
499 printk("\n" KERN_ERR
500 "%s: Memory allocation failed.\n", dev->name);
501 goto free_new_tx_ring;
502 }
503
504 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
505 GFP_ATOMIC);
506 if (!new_skb_list) {
507 if (netif_msg_drv(lp))
508 printk("\n" KERN_ERR
509 "%s: Memory allocation failed.\n", dev->name);
510 goto free_new_lists;
511 }
512
513 kfree(lp->tx_skbuff);
514 kfree(lp->tx_dma_addr);
515 pci_free_consistent(lp->pci_dev,
516 sizeof(struct pcnet32_tx_head) *
517 lp->tx_ring_size, lp->tx_ring,
518 lp->tx_ring_dma_addr);
519
520 lp->tx_ring_size = (1 << size);
521 lp->tx_mod_mask = lp->tx_ring_size - 1;
522 lp->tx_len_bits = (size << 12);
523 lp->tx_ring = new_tx_ring;
524 lp->tx_ring_dma_addr = new_ring_dma_addr;
525 lp->tx_dma_addr = new_dma_addr_list;
526 lp->tx_skbuff = new_skb_list;
527 return;
528
529 free_new_lists:
530 kfree(new_dma_addr_list);
531 free_new_tx_ring:
532 pci_free_consistent(lp->pci_dev,
533 sizeof(struct pcnet32_tx_head) *
534 (1 << size),
535 new_tx_ring,
536 new_ring_dma_addr);
537 return;
538}
539
540/*
541 * Allocate space for the new sized rx ring.
542 * Re-use old receive buffers.
543 * alloc extra buffers
544 * free unneeded buffers
545 * free unneeded buffers
546 * Save new resources.
547 * Any failure keeps old resources.
548 * Must be called with lp->lock held.
549 */
550static void pcnet32_realloc_rx_ring(struct net_device *dev,
551 struct pcnet32_private *lp,
552 unsigned int size)
553{
554 dma_addr_t new_ring_dma_addr;
555 dma_addr_t *new_dma_addr_list;
556 struct pcnet32_rx_head *new_rx_ring;
557 struct sk_buff **new_skb_list;
558 int new, overlap;
559
560 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
561 sizeof(struct pcnet32_rx_head) *
562 (1 << size),
563 &new_ring_dma_addr);
564 if (new_rx_ring == NULL) {
565 if (netif_msg_drv(lp))
566 printk("\n" KERN_ERR
567 "%s: Consistent memory allocation failed.\n",
568 dev->name);
569 return;
570 }
571 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
572
573 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
574 GFP_ATOMIC);
575 if (!new_dma_addr_list) {
576 if (netif_msg_drv(lp))
577 printk("\n" KERN_ERR
578 "%s: Memory allocation failed.\n", dev->name);
579 goto free_new_rx_ring;
580 }
581
582 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
583 GFP_ATOMIC);
584 if (!new_skb_list) {
585 if (netif_msg_drv(lp))
586 printk("\n" KERN_ERR
587 "%s: Memory allocation failed.\n", dev->name);
588 goto free_new_lists;
589 }
590
591 /* first copy the current receive buffers */
592 overlap = min(size, lp->rx_ring_size);
593 for (new = 0; new < overlap; new++) {
594 new_rx_ring[new] = lp->rx_ring[new];
595 new_dma_addr_list[new] = lp->rx_dma_addr[new];
596 new_skb_list[new] = lp->rx_skbuff[new];
597 }
598 /* now allocate any new buffers needed */
599 for (; new < size; new++ ) {
600 struct sk_buff *rx_skbuff;
232c5640 601 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SKB);
06c87850
DF		 602 if (!(rx_skbuff = new_skb_list[new])) {
603 /* keep the original lists and buffers */
604 if (netif_msg_drv(lp))
605 printk(KERN_ERR
606 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
607 dev->name);
608 goto free_all_new;
609 }
232c5640 610 skb_reserve(rx_skbuff, NET_IP_ALIGN);
06c87850
DF		 611
612 new_dma_addr_list[new] =
613 pci_map_single(lp->pci_dev, rx_skbuff->data,
232c5640 614 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
3e33545b 615 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
232c5640 616 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
3e33545b 617 new_rx_ring[new].status = cpu_to_le16(0x8000);
06c87850
DF		 618 }
619 /* and free any unneeded buffers */
620 for (; new < lp->rx_ring_size; new++) {
621 if (lp->rx_skbuff[new]) {
622 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
232c5640 623 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
06c87850
DF		 624 dev_kfree_skb(lp->rx_skbuff[new]);
625 }
626 }
627
628 kfree(lp->rx_skbuff);
629 kfree(lp->rx_dma_addr);
630 pci_free_consistent(lp->pci_dev,
631 sizeof(struct pcnet32_rx_head) *
632 lp->rx_ring_size, lp->rx_ring,
633 lp->rx_ring_dma_addr);
634
635 lp->rx_ring_size = (1 << size);
636 lp->rx_mod_mask = lp->rx_ring_size - 1;
637 lp->rx_len_bits = (size << 4);
638 lp->rx_ring = new_rx_ring;
639 lp->rx_ring_dma_addr = new_ring_dma_addr;
640 lp->rx_dma_addr = new_dma_addr_list;
641 lp->rx_skbuff = new_skb_list;
642 return;
643
644 free_all_new:
645 for (; --new >= lp->rx_ring_size; ) {
646 if (new_skb_list[new]) {
647 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
232c5640 648 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
06c87850
DF		 649 dev_kfree_skb(new_skb_list[new]);
650 }
651 }
652 kfree(new_skb_list);
653 free_new_lists:
654 kfree(new_dma_addr_list);
655 free_new_rx_ring:
656 pci_free_consistent(lp->pci_dev,
657 sizeof(struct pcnet32_rx_head) *
658 (1 << size),
659 new_rx_ring,
660 new_ring_dma_addr);
661 return;
662}
663
ac5bfe40
DF		 664static void pcnet32_purge_rx_ring(struct net_device *dev)
665{
1e56a4b4 666 struct pcnet32_private *lp = netdev_priv(dev);
ac5bfe40
DF		 667 int i;
668
669 /* free all allocated skbuffs */
670 for (i = 0; i < lp->rx_ring_size; i++) {
671 lp->rx_ring[i].status = 0; /* CPU owns buffer */
672 wmb(); /* Make sure adapter sees owner change */
673 if (lp->rx_skbuff[i]) {
674 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
232c5640 675 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
ac5bfe40
DF		 676 dev_kfree_skb_any(lp->rx_skbuff[i]);
677 }
678 lp->rx_skbuff[i] = NULL;
679 lp->rx_dma_addr[i] = 0;
680 }
681}
682
1da177e4
LT		 683#ifdef CONFIG_NET_POLL_CONTROLLER
684static void pcnet32_poll_controller(struct net_device *dev)
685{
4a5e8e29 686 disable_irq(dev->irq);
7d12e780 687 pcnet32_interrupt(0, dev);
4a5e8e29 688 enable_irq(dev->irq);
1da177e4
LT		 689}
690#endif
691
1da177e4
LT		 692static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
693{
1e56a4b4 694 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 695 unsigned long flags;
696 int r = -EOPNOTSUPP;
1da177e4 697
4a5e8e29
JG		 698 if (lp->mii) {
699 spin_lock_irqsave(&lp->lock, flags);
700 mii_ethtool_gset(&lp->mii_if, cmd);
701 spin_unlock_irqrestore(&lp->lock, flags);
702 r = 0;
703 }
704 return r;
1da177e4
LT		 705}
706
707static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
708{
1e56a4b4 709 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 710 unsigned long flags;
711 int r = -EOPNOTSUPP;
1da177e4 712
4a5e8e29
JG		 713 if (lp->mii) {
714 spin_lock_irqsave(&lp->lock, flags);
715 r = mii_ethtool_sset(&lp->mii_if, cmd);
716 spin_unlock_irqrestore(&lp->lock, flags);
717 }
718 return r;
1da177e4
LT		 719}
720
4a5e8e29
JG		 721static void pcnet32_get_drvinfo(struct net_device *dev,
722 struct ethtool_drvinfo *info)
1da177e4 723{
1e56a4b4 724 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 725
726 strcpy(info->driver, DRV_NAME);
727 strcpy(info->version, DRV_VERSION);
728 if (lp->pci_dev)
729 strcpy(info->bus_info, pci_name(lp->pci_dev));
730 else
731 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
1da177e4
LT		 732}
733
734static u32 pcnet32_get_link(struct net_device *dev)
735{
1e56a4b4 736 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 737 unsigned long flags;
738 int r;
1da177e4 739
4a5e8e29
JG		 740 spin_lock_irqsave(&lp->lock, flags);
741 if (lp->mii) {
742 r = mii_link_ok(&lp->mii_if);
8d916266 743 } else if (lp->chip_version >= PCNET32_79C970A) {
4a5e8e29
JG		 744 ulong ioaddr = dev->base_addr; /* card base I/O address */
745 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
8d916266
DF		 746 } else { /* can not detect link on really old chips */
747 r = 1;
4a5e8e29
JG		 748 }
749 spin_unlock_irqrestore(&lp->lock, flags);
750
751 return r;
1da177e4
LT		 752}
753
754static u32 pcnet32_get_msglevel(struct net_device *dev)
755{
1e56a4b4 756 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 757 return lp->msg_enable;
1da177e4
LT		 758}
759
760static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
761{
1e56a4b4 762 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 763 lp->msg_enable = value;
1da177e4
LT		 764}
765
766static int pcnet32_nway_reset(struct net_device *dev)
767{
1e56a4b4 768 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 769 unsigned long flags;
770 int r = -EOPNOTSUPP;
1da177e4 771
4a5e8e29
JG		 772 if (lp->mii) {
773 spin_lock_irqsave(&lp->lock, flags);
774 r = mii_nway_restart(&lp->mii_if);
775 spin_unlock_irqrestore(&lp->lock, flags);
776 }
777 return r;
1da177e4
LT		 778}
779
4a5e8e29
JG		 780static void pcnet32_get_ringparam(struct net_device *dev,
781 struct ethtool_ringparam *ering)
1da177e4 782{
1e56a4b4 783 struct pcnet32_private *lp = netdev_priv(dev);
1da177e4 784
6dcd60c2
DF		 785 ering->tx_max_pending = TX_MAX_RING_SIZE;
786 ering->tx_pending = lp->tx_ring_size;
787 ering->rx_max_pending = RX_MAX_RING_SIZE;
788 ering->rx_pending = lp->rx_ring_size;
eabf0415
HWL		 789}
790
4a5e8e29
JG		 791static int pcnet32_set_ringparam(struct net_device *dev,
792 struct ethtool_ringparam *ering)
eabf0415 793{
1e56a4b4 794 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 795 unsigned long flags;
06c87850
DF		 796 unsigned int size;
797 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 798 int i;
799
800 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
801 return -EINVAL;
802
803 if (netif_running(dev))
06c87850 804 pcnet32_netif_stop(dev);
4a5e8e29
JG		 805
806 spin_lock_irqsave(&lp->lock, flags);
06c87850
DF		 807 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
808
809 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
4a5e8e29
JG		 810
811 /* set the minimum ring size to 4, to allow the loopback test to work
812 * unchanged.
813 */
814 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
06c87850 815 if (size <= (1 << i))
4a5e8e29
JG		 816 break;
817 }
06c87850
DF		 818 if ((1 << i) != lp->tx_ring_size)
819 pcnet32_realloc_tx_ring(dev, lp, i);
b368a3fb 820
06c87850 821 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
4a5e8e29 822 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
06c87850 823 if (size <= (1 << i))
4a5e8e29
JG		 824 break;
825 }
06c87850
DF		 826 if ((1 << i) != lp->rx_ring_size)
827 pcnet32_realloc_rx_ring(dev, lp, i);
b368a3fb 828
bea3348e 829 lp->napi.weight = lp->rx_ring_size / 2;
06c87850
DF		 830
831 if (netif_running(dev)) {
832 pcnet32_netif_start(dev);
833 pcnet32_restart(dev, CSR0_NORMAL);
4a5e8e29 834 }
eabf0415 835
4a5e8e29 836 spin_unlock_irqrestore(&lp->lock, flags);
eabf0415 837
06c87850
DF		 838 if (netif_msg_drv(lp))
839 printk(KERN_INFO
4a5e8e29
JG		 840 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
841 lp->rx_ring_size, lp->tx_ring_size);
eabf0415 842
4a5e8e29 843 return 0;
1da177e4
LT		 844}
845
4a5e8e29
JG		 846static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
847 u8 * data)
1da177e4 848{
4a5e8e29 849 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
1da177e4
LT		 850}
851
b9f2c044 852static int pcnet32_get_sset_count(struct net_device *dev, int sset)
1da177e4 853{
b9f2c044
JG		 854 switch (sset) {
855 case ETH_SS_TEST:
856 return PCNET32_TEST_LEN;
857 default:
858 return -EOPNOTSUPP;
859 }
1da177e4
LT		 860}
861
862static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29 863 struct ethtool_test *test, u64 * data)
1da177e4 864{
1e56a4b4 865 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 866 int rc;
867
868 if (test->flags == ETH_TEST_FL_OFFLINE) {
869 rc = pcnet32_loopback_test(dev, data);
870 if (rc) {
871 if (netif_msg_hw(lp))
872 printk(KERN_DEBUG "%s: Loopback test failed.\n",
873 dev->name);
874 test->flags |= ETH_TEST_FL_FAILED;
875 } else if (netif_msg_hw(lp))
876 printk(KERN_DEBUG "%s: Loopback test passed.\n",
877 dev->name);
1da177e4 878 } else if (netif_msg_hw(lp))
4a5e8e29
JG		 879 printk(KERN_DEBUG
880 "%s: No tests to run (specify 'Offline' on ethtool).",
881 dev->name);
882} /* end pcnet32_ethtool_test */
1da177e4 883
4a5e8e29 884static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
1da177e4 885{
1e56a4b4 886 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 887 struct pcnet32_access *a = &lp->a; /* access to registers */
888 ulong ioaddr = dev->base_addr; /* card base I/O address */
889 struct sk_buff *skb; /* sk buff */
890 int x, i; /* counters */
891 int numbuffs = 4; /* number of TX/RX buffers and descs */
892 u16 status = 0x8300; /* TX ring status */
3e33545b 893 __le16 teststatus; /* test of ring status */
4a5e8e29
JG		 894 int rc; /* return code */
895 int size; /* size of packets */
896 unsigned char *packet; /* source packet data */
897 static const int data_len = 60; /* length of source packets */
898 unsigned long flags;
899 unsigned long ticks;
900
4a5e8e29
JG		 901 rc = 1; /* default to fail */
902
903 if (netif_running(dev))
7de745e5 904 pcnet32_netif_stop(dev);
4a5e8e29
JG		 905
906 spin_lock_irqsave(&lp->lock, flags);
ac5bfe40
DF		 907 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
908
909 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
4a5e8e29
JG		 910
911 /* Reset the PCNET32 */
912 lp->a.reset(ioaddr);
b368a3fb 913 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
4a5e8e29
JG		 914
915 /* switch pcnet32 to 32bit mode */
916 lp->a.write_bcr(ioaddr, 20, 2);
917
4a5e8e29
JG		 918 /* purge & init rings but don't actually restart */
919 pcnet32_restart(dev, 0x0000);
920
ac5bfe40 921 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 922
923 /* Initialize Transmit buffers. */
924 size = data_len + 15;
925 for (x = 0; x < numbuffs; x++) {
926 if (!(skb = dev_alloc_skb(size))) {
927 if (netif_msg_hw(lp))
928 printk(KERN_DEBUG
929 "%s: Cannot allocate skb at line: %d!\n",
930 dev->name, __LINE__);
931 goto clean_up;
932 } else {
933 packet = skb->data;
934 skb_put(skb, size); /* create space for data */
935 lp->tx_skbuff[x] = skb;
3e33545b 936 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
4a5e8e29
JG		 937 lp->tx_ring[x].misc = 0;
938
939 /* put DA and SA into the skb */
940 for (i = 0; i < 6; i++)
941 *packet++ = dev->dev_addr[i];
942 for (i = 0; i < 6; i++)
943 *packet++ = dev->dev_addr[i];
944 /* type */
945 *packet++ = 0x08;
946 *packet++ = 0x06;
947 /* packet number */
948 *packet++ = x;
949 /* fill packet with data */
950 for (i = 0; i < data_len; i++)
951 *packet++ = i;
952
953 lp->tx_dma_addr[x] =
954 pci_map_single(lp->pci_dev, skb->data, skb->len,
955 PCI_DMA_TODEVICE);
3e33545b 956 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
4a5e8e29 957 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 958 lp->tx_ring[x].status = cpu_to_le16(status);
4a5e8e29 959 }
1da177e4 960 }
1da177e4 961
ac5bfe40
DF		 962 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
963 a->write_bcr(ioaddr, 32, x | 0x0002);
4a5e8e29 964
ac5bfe40
DF		 965 /* set int loopback in CSR15 */
966 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
967 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
4a5e8e29 968
3e33545b 969 teststatus = cpu_to_le16(0x8000);
ac5bfe40 970 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
4a5e8e29
JG		 971
972 /* Check status of descriptors */
973 for (x = 0; x < numbuffs; x++) {
974 ticks = 0;
975 rmb();
976 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
977 spin_unlock_irqrestore(&lp->lock, flags);
ac5bfe40 978 msleep(1);
4a5e8e29
JG		 979 spin_lock_irqsave(&lp->lock, flags);
980 rmb();
981 ticks++;
982 }
983 if (ticks == 200) {
984 if (netif_msg_hw(lp))
985 printk("%s: Desc %d failed to reset!\n",
986 dev->name, x);
987 break;
988 }
989 }
990
ac5bfe40 991 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 992 wmb();
993 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
994 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
995
996 for (x = 0; x < numbuffs; x++) {
997 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
998 skb = lp->rx_skbuff[x];
999 for (i = 0; i < size; i++) {
1000 printk("%02x ", *(skb->data + i));
1001 }
1002 printk("\n");
1003 }
1004 }
1da177e4 1005
4a5e8e29
JG		 1006 x = 0;
1007 rc = 0;
1008 while (x < numbuffs && !rc) {
1009 skb = lp->rx_skbuff[x];
1010 packet = lp->tx_skbuff[x]->data;
1011 for (i = 0; i < size; i++) {
1012 if (*(skb->data + i) != packet[i]) {
1013 if (netif_msg_hw(lp))
1014 printk(KERN_DEBUG
1015 "%s: Error in compare! %2x - %02x %02x\n",
1016 dev->name, i, *(skb->data + i),
1017 packet[i]);
1018 rc = 1;
1019 break;
1020 }
1021 }
1022 x++;
1023 }
1da177e4 1024
4a5e8e29 1025 clean_up:
ac5bfe40 1026 *data1 = rc;
4a5e8e29 1027 pcnet32_purge_tx_ring(dev);
1da177e4 1028
ac5bfe40
DF		 1029 x = a->read_csr(ioaddr, CSR15);
1030 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1da177e4 1031
ac5bfe40
DF		 1032 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1033 a->write_bcr(ioaddr, 32, (x & ~0x0002));
4a5e8e29 1034
7de745e5
DF		 1035 if (netif_running(dev)) {
1036 pcnet32_netif_start(dev);
1037 pcnet32_restart(dev, CSR0_NORMAL);
1038 } else {
1039 pcnet32_purge_rx_ring(dev);
1040 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1041 }
1042 spin_unlock_irqrestore(&lp->lock, flags);
4a5e8e29
JG		 1043
1044 return (rc);
1045} /* end pcnet32_loopback_test */
1da177e4
LT		 1046
1047static void pcnet32_led_blink_callback(struct net_device *dev)
1048{
1e56a4b4 1049 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1050 struct pcnet32_access *a = &lp->a;
1051 ulong ioaddr = dev->base_addr;
1052 unsigned long flags;
1053 int i;
1054
1055 spin_lock_irqsave(&lp->lock, flags);
1056 for (i = 4; i < 8; i++) {
1057 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1058 }
1059 spin_unlock_irqrestore(&lp->lock, flags);
1060
1061 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1da177e4
LT		 1062}
1063
1064static int pcnet32_phys_id(struct net_device *dev, u32 data)
1065{
1e56a4b4 1066 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1067 struct pcnet32_access *a = &lp->a;
1068 ulong ioaddr = dev->base_addr;
1069 unsigned long flags;
1070 int i, regs[4];
1071
1072 if (!lp->blink_timer.function) {
1073 init_timer(&lp->blink_timer);
1074 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1075 lp->blink_timer.data = (unsigned long)dev;
1076 }
1077
1078 /* Save the current value of the bcrs */
1079 spin_lock_irqsave(&lp->lock, flags);
1080 for (i = 4; i < 8; i++) {
1081 regs[i - 4] = a->read_bcr(ioaddr, i);
1082 }
1083 spin_unlock_irqrestore(&lp->lock, flags);
1084
1085 mod_timer(&lp->blink_timer, jiffies);
1086 set_current_state(TASK_INTERRUPTIBLE);
1087
3e33545b 1088 /* AV: the limit here makes no sense whatsoever */
4a5e8e29
JG		 1089 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1090 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1091
1092 msleep_interruptible(data * 1000);
1093 del_timer_sync(&lp->blink_timer);
1094
1095 /* Restore the original value of the bcrs */
1096 spin_lock_irqsave(&lp->lock, flags);
1097 for (i = 4; i < 8; i++) {
1098 a->write_bcr(ioaddr, i, regs[i - 4]);
1099 }
1100 spin_unlock_irqrestore(&lp->lock, flags);
1101
1102 return 0;
1da177e4
LT		 1103}
1104
df27f4a6
DF		 1105/*
1106 * lp->lock must be held.
1107 */
1108static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1109 int can_sleep)
1110{
1111 int csr5;
1e56a4b4 1112 struct pcnet32_private *lp = netdev_priv(dev);
df27f4a6
DF		 1113 struct pcnet32_access *a = &lp->a;
1114 ulong ioaddr = dev->base_addr;
1115 int ticks;
1116
8d916266
DF		 1117 /* really old chips have to be stopped. */
1118 if (lp->chip_version < PCNET32_79C970A)
1119 return 0;
1120
df27f4a6
DF		 1121 /* set SUSPEND (SPND) - CSR5 bit 0 */
1122 csr5 = a->read_csr(ioaddr, CSR5);
1123 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1124
1125 /* poll waiting for bit to be set */
1126 ticks = 0;
1127 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1128 spin_unlock_irqrestore(&lp->lock, *flags);
1129 if (can_sleep)
1130 msleep(1);
1131 else
1132 mdelay(1);
1133 spin_lock_irqsave(&lp->lock, *flags);
1134 ticks++;
1135 if (ticks > 200) {
1136 if (netif_msg_hw(lp))
1137 printk(KERN_DEBUG
1138 "%s: Error getting into suspend!\n",
1139 dev->name);
1140 return 0;
1141 }
1142 }
1143 return 1;
1144}
1145
3904c324
DF		 1146/*
1147 * process one receive descriptor entry
1148 */
1149
1150static void pcnet32_rx_entry(struct net_device *dev,
1151 struct pcnet32_private *lp,
1152 struct pcnet32_rx_head *rxp,
1153 int entry)
1154{
1155 int status = (short)le16_to_cpu(rxp->status) >> 8;
1156 int rx_in_place = 0;
1157 struct sk_buff *skb;
1158 short pkt_len;
1159
1160 if (status != 0x03) { /* There was an error. */
1161 /*
1162 * There is a tricky error noted by John Murphy,
1163 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1164 * buffers it's possible for a jabber packet to use two
1165 * buffers, with only the last correctly noting the error.
1166 */
1167 if (status & 0x01) /* Only count a general error at the */
4f1e5ba0 1168 dev->stats.rx_errors++; /* end of a packet. */
3904c324 1169 if (status & 0x20)
4f1e5ba0 1170 dev->stats.rx_frame_errors++;
3904c324 1171 if (status & 0x10)
4f1e5ba0 1172 dev->stats.rx_over_errors++;
3904c324 1173 if (status & 0x08)
4f1e5ba0 1174 dev->stats.rx_crc_errors++;
3904c324 1175 if (status & 0x04)
4f1e5ba0 1176 dev->stats.rx_fifo_errors++;
3904c324
DF		 1177 return;
1178 }
1179
1180 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1181
1182 /* Discard oversize frames. */
232c5640 1183 if (unlikely(pkt_len > PKT_BUF_SIZE)) {
3904c324
DF		 1184 if (netif_msg_drv(lp))
1185 printk(KERN_ERR "%s: Impossible packet size %d!\n",
1186 dev->name, pkt_len);
4f1e5ba0 1187 dev->stats.rx_errors++;
3904c324
DF		 1188 return;
1189 }
1190 if (pkt_len < 60) {
1191 if (netif_msg_rx_err(lp))
1192 printk(KERN_ERR "%s: Runt packet!\n", dev->name);
4f1e5ba0 1193 dev->stats.rx_errors++;
3904c324
DF		 1194 return;
1195 }
1196
1197 if (pkt_len > rx_copybreak) {
1198 struct sk_buff *newskb;
1199
232c5640
DF		 1200 if ((newskb = dev_alloc_skb(PKT_BUF_SKB))) {
1201 skb_reserve(newskb, NET_IP_ALIGN);
3904c324
DF		 1202 skb = lp->rx_skbuff[entry];
1203 pci_unmap_single(lp->pci_dev,
1204 lp->rx_dma_addr[entry],
232c5640 1205 PKT_BUF_SIZE,
3904c324
DF		 1206 PCI_DMA_FROMDEVICE);
1207 skb_put(skb, pkt_len);
1208 lp->rx_skbuff[entry] = newskb;
3904c324
DF		 1209 lp->rx_dma_addr[entry] =
1210 pci_map_single(lp->pci_dev,
1211 newskb->data,
232c5640 1212 PKT_BUF_SIZE,
3904c324 1213 PCI_DMA_FROMDEVICE);
3e33545b 1214 rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
3904c324
DF		 1215 rx_in_place = 1;
1216 } else
1217 skb = NULL;
1218 } else {
232c5640 1219 skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN);
3904c324
DF		 1220 }
1221
1222 if (skb == NULL) {
1223 if (netif_msg_drv(lp))
1224 printk(KERN_ERR
1225 "%s: Memory squeeze, dropping packet.\n",
1226 dev->name);
4f1e5ba0 1227 dev->stats.rx_dropped++;
3904c324
DF		 1228 return;
1229 }
1230 skb->dev = dev;
1231 if (!rx_in_place) {
232c5640 1232 skb_reserve(skb, NET_IP_ALIGN);
3904c324
DF		 1233 skb_put(skb, pkt_len); /* Make room */
1234 pci_dma_sync_single_for_cpu(lp->pci_dev,
1235 lp->rx_dma_addr[entry],
b2cbbd8e 1236 pkt_len,
3904c324 1237 PCI_DMA_FROMDEVICE);
8c7b7faa 1238 skb_copy_to_linear_data(skb,
3904c324 1239 (unsigned char *)(lp->rx_skbuff[entry]->data),
8c7b7faa 1240 pkt_len);
3904c324
DF		 1241 pci_dma_sync_single_for_device(lp->pci_dev,
1242 lp->rx_dma_addr[entry],
b2cbbd8e 1243 pkt_len,
3904c324
DF		 1244 PCI_DMA_FROMDEVICE);
1245 }
4f1e5ba0 1246 dev->stats.rx_bytes += skb->len;
3904c324 1247 skb->protocol = eth_type_trans(skb, dev);
7de745e5 1248 netif_receive_skb(skb);
3904c324 1249 dev->last_rx = jiffies;
4f1e5ba0 1250 dev->stats.rx_packets++;
3904c324
DF		 1251 return;
1252}
1253
bea3348e 1254static int pcnet32_rx(struct net_device *dev, int budget)
9691edd2 1255{
1e56a4b4 1256 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2 1257 int entry = lp->cur_rx & lp->rx_mod_mask;
3904c324
DF		 1258 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1259 int npackets = 0;
9691edd2
DF		 1260
1261 /* If we own the next entry, it's a new packet. Send it up. */
bea3348e 1262 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
3904c324
DF		 1263 pcnet32_rx_entry(dev, lp, rxp, entry);
1264 npackets += 1;
9691edd2 1265 /*
3904c324
DF		 1266 * The docs say that the buffer length isn't touched, but Andrew
1267 * Boyd of QNX reports that some revs of the 79C965 clear it.
9691edd2 1268 */
232c5640 1269 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
3904c324 1270 wmb(); /* Make sure owner changes after others are visible */
3e33545b 1271 rxp->status = cpu_to_le16(0x8000);
9691edd2 1272 entry = (++lp->cur_rx) & lp->rx_mod_mask;
3904c324 1273 rxp = &lp->rx_ring[entry];
9691edd2
DF		 1274 }
1275
7de745e5 1276 return npackets;
9691edd2
DF		 1277}
1278
7de745e5 1279static int pcnet32_tx(struct net_device *dev)
9691edd2 1280{
1e56a4b4 1281 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2
DF		 1282 unsigned int dirty_tx = lp->dirty_tx;
1283 int delta;
1284 int must_restart = 0;
1285
1286 while (dirty_tx != lp->cur_tx) {
1287 int entry = dirty_tx & lp->tx_mod_mask;
1288 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1289
1290 if (status < 0)
1291 break; /* It still hasn't been Txed */
1292
1293 lp->tx_ring[entry].base = 0;
1294
1295 if (status & 0x4000) {
3904c324 1296 /* There was a major error, log it. */
9691edd2 1297 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
4f1e5ba0 1298 dev->stats.tx_errors++;
9691edd2
DF		 1299 if (netif_msg_tx_err(lp))
1300 printk(KERN_ERR
1301 "%s: Tx error status=%04x err_status=%08x\n",
1302 dev->name, status,
1303 err_status);
1304 if (err_status & 0x04000000)
4f1e5ba0 1305 dev->stats.tx_aborted_errors++;
9691edd2 1306 if (err_status & 0x08000000)
4f1e5ba0 1307 dev->stats.tx_carrier_errors++;
9691edd2 1308 if (err_status & 0x10000000)
4f1e5ba0 1309 dev->stats.tx_window_errors++;
9691edd2
DF		 1310#ifndef DO_DXSUFLO
1311 if (err_status & 0x40000000) {
4f1e5ba0 1312 dev->stats.tx_fifo_errors++;
9691edd2
DF		 1313 /* Ackk! On FIFO errors the Tx unit is turned off! */
1314 /* Remove this verbosity later! */
1315 if (netif_msg_tx_err(lp))
1316 printk(KERN_ERR
7de745e5
DF		 1317 "%s: Tx FIFO error!\n",
1318 dev->name);
9691edd2
DF		 1319 must_restart = 1;
1320 }
1321#else
1322 if (err_status & 0x40000000) {
4f1e5ba0 1323 dev->stats.tx_fifo_errors++;
9691edd2
DF		 1324 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1325 /* Ackk! On FIFO errors the Tx unit is turned off! */
1326 /* Remove this verbosity later! */
3904c324 1327 if (netif_msg_tx_err(lp))
9691edd2 1328 printk(KERN_ERR
7de745e5
DF		 1329 "%s: Tx FIFO error!\n",
1330 dev->name);
9691edd2
DF		 1331 must_restart = 1;
1332 }
1333 }
1334#endif
1335 } else {
1336 if (status & 0x1800)
4f1e5ba0
DF		 1337 dev->stats.collisions++;
1338 dev->stats.tx_packets++;
9691edd2
DF		 1339 }
1340
1341 /* We must free the original skb */
1342 if (lp->tx_skbuff[entry]) {
1343 pci_unmap_single(lp->pci_dev,
1344 lp->tx_dma_addr[entry],
1345 lp->tx_skbuff[entry]->
1346 len, PCI_DMA_TODEVICE);
3904c324 1347 dev_kfree_skb_any(lp->tx_skbuff[entry]);
9691edd2
DF		 1348 lp->tx_skbuff[entry] = NULL;
1349 lp->tx_dma_addr[entry] = 0;
1350 }
1351 dirty_tx++;
1352 }
1353
3904c324 1354 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
9691edd2
DF		 1355 if (delta > lp->tx_ring_size) {
1356 if (netif_msg_drv(lp))
1357 printk(KERN_ERR
1358 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1359 dev->name, dirty_tx, lp->cur_tx,
1360 lp->tx_full);
1361 dirty_tx += lp->tx_ring_size;
1362 delta -= lp->tx_ring_size;
1363 }
1364
1365 if (lp->tx_full &&
1366 netif_queue_stopped(dev) &&
1367 delta < lp->tx_ring_size - 2) {
1368 /* The ring is no longer full, clear tbusy. */
1369 lp->tx_full = 0;
1370 netif_wake_queue(dev);
1371 }
1372 lp->dirty_tx = dirty_tx;
1373
1374 return must_restart;
1375}
1376
bea3348e 1377static int pcnet32_poll(struct napi_struct *napi, int budget)
7de745e5 1378{
bea3348e
SH		 1379 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1380 struct net_device *dev = lp->dev;
7de745e5
DF		 1381 unsigned long ioaddr = dev->base_addr;
1382 unsigned long flags;
bea3348e 1383 int work_done;
7de745e5
DF		 1384 u16 val;
1385
bea3348e 1386 work_done = pcnet32_rx(dev, budget);
7de745e5
DF		 1387
1388 spin_lock_irqsave(&lp->lock, flags);
1389 if (pcnet32_tx(dev)) {
1390 /* reset the chip to clear the error condition, then restart */
1391 lp->a.reset(ioaddr);
1392 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1393 pcnet32_restart(dev, CSR0_START);
1394 netif_wake_queue(dev);
1395 }
1396 spin_unlock_irqrestore(&lp->lock, flags);
1397
bea3348e
SH		 1398 if (work_done < budget) {
1399 spin_lock_irqsave(&lp->lock, flags);
7de745e5 1400
bea3348e 1401 __netif_rx_complete(dev, napi);
7de745e5 1402
bea3348e
SH		 1403 /* clear interrupt masks */
1404 val = lp->a.read_csr(ioaddr, CSR3);
1405 val &= 0x00ff;
1406 lp->a.write_csr(ioaddr, CSR3, val);
7de745e5 1407
bea3348e
SH		 1408 /* Set interrupt enable. */
1409 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
1410 mmiowb();
1411 spin_unlock_irqrestore(&lp->lock, flags);
1412 }
1413 return work_done;
7de745e5 1414}
7de745e5 1415
ac62ef04
DF		 1416#define PCNET32_REGS_PER_PHY 32
1417#define PCNET32_MAX_PHYS 32
1da177e4
LT		 1418static int pcnet32_get_regs_len(struct net_device *dev)
1419{
1e56a4b4 1420 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 1421 int j = lp->phycount * PCNET32_REGS_PER_PHY;
ac62ef04 1422
4a5e8e29 1423 return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1da177e4
LT		 1424}
1425
1426static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 1427 void *ptr)
1da177e4 1428{
4a5e8e29
JG		 1429 int i, csr0;
1430 u16 *buff = ptr;
1e56a4b4 1431 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1432 struct pcnet32_access *a = &lp->a;
1433 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 1434 unsigned long flags;
1435
1436 spin_lock_irqsave(&lp->lock, flags);
1437
df27f4a6
DF		 1438 csr0 = a->read_csr(ioaddr, CSR0);
1439 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1440 pcnet32_suspend(dev, &flags, 1);
1da177e4 1441
4a5e8e29
JG		 1442 /* read address PROM */
1443 for (i = 0; i < 16; i += 2)
1444 *buff++ = inw(ioaddr + i);
1445
1446 /* read control and status registers */
1447 for (i = 0; i < 90; i++) {
1448 *buff++ = a->read_csr(ioaddr, i);
1449 }
1450
1451 *buff++ = a->read_csr(ioaddr, 112);
1452 *buff++ = a->read_csr(ioaddr, 114);
1da177e4 1453
4a5e8e29
JG		 1454 /* read bus configuration registers */
1455 for (i = 0; i < 30; i++) {
1456 *buff++ = a->read_bcr(ioaddr, i);
1457 }
1458 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1459 for (i = 31; i < 36; i++) {
1460 *buff++ = a->read_bcr(ioaddr, i);
1461 }
1462
1463 /* read mii phy registers */
1464 if (lp->mii) {
1465 int j;
1466 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1467 if (lp->phymask & (1 << j)) {
1468 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1469 lp->a.write_bcr(ioaddr, 33,
1470 (j << 5) | i);
1471 *buff++ = lp->a.read_bcr(ioaddr, 34);
1472 }
1473 }
1474 }
1475 }
1476
df27f4a6
DF		 1477 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1478 int csr5;
1479
4a5e8e29 1480 /* clear SUSPEND (SPND) - CSR5 bit 0 */
df27f4a6
DF		 1481 csr5 = a->read_csr(ioaddr, CSR5);
1482 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
4a5e8e29
JG		 1483 }
1484
1485 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 1486}
1487
7282d491 1488static const struct ethtool_ops pcnet32_ethtool_ops = {
4a5e8e29
JG		 1489 .get_settings = pcnet32_get_settings,
1490 .set_settings = pcnet32_set_settings,
1491 .get_drvinfo = pcnet32_get_drvinfo,
1492 .get_msglevel = pcnet32_get_msglevel,
1493 .set_msglevel = pcnet32_set_msglevel,
1494 .nway_reset = pcnet32_nway_reset,
1495 .get_link = pcnet32_get_link,
1496 .get_ringparam = pcnet32_get_ringparam,
1497 .set_ringparam = pcnet32_set_ringparam,
4a5e8e29 1498 .get_strings = pcnet32_get_strings,
4a5e8e29
JG		 1499 .self_test = pcnet32_ethtool_test,
1500 .phys_id = pcnet32_phys_id,
1501 .get_regs_len = pcnet32_get_regs_len,
1502 .get_regs = pcnet32_get_regs,
b9f2c044 1503 .get_sset_count = pcnet32_get_sset_count,
1da177e4
LT		 1504};
1505
1506/* only probes for non-PCI devices, the rest are handled by
1507 * pci_register_driver via pcnet32_probe_pci */
1508
dcaf9769 1509static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1da177e4 1510{
4a5e8e29
JG		 1511 unsigned int *port, ioaddr;
1512
1513 /* search for PCnet32 VLB cards at known addresses */
1514 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1515 if (request_region
1516 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1517 /* check if there is really a pcnet chip on that ioaddr */
1518 if ((inb(ioaddr + 14) == 0x57)
1519 && (inb(ioaddr + 15) == 0x57)) {
1520 pcnet32_probe1(ioaddr, 0, NULL);
1521 } else {
1522 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1523 }
1524 }
1525 }
1da177e4
LT		 1526}
1527
1da177e4
LT		 1528static int __devinit
1529pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1530{
4a5e8e29
JG		 1531 unsigned long ioaddr;
1532 int err;
1533
1534 err = pci_enable_device(pdev);
1535 if (err < 0) {
1536 if (pcnet32_debug & NETIF_MSG_PROBE)
1537 printk(KERN_ERR PFX
1538 "failed to enable device -- err=%d\n", err);
1539 return err;
1540 }
1541 pci_set_master(pdev);
1542
1543 ioaddr = pci_resource_start(pdev, 0);
1544 if (!ioaddr) {
1545 if (pcnet32_debug & NETIF_MSG_PROBE)
1546 printk(KERN_ERR PFX
1547 "card has no PCI IO resources, aborting\n");
1548 return -ENODEV;
1549 }
1da177e4 1550
4a5e8e29
JG		 1551 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1552 if (pcnet32_debug & NETIF_MSG_PROBE)
1553 printk(KERN_ERR PFX
1554 "architecture does not support 32bit PCI busmaster DMA\n");
1555 return -ENODEV;
1556 }
1557 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1558 NULL) {
1559 if (pcnet32_debug & NETIF_MSG_PROBE)
1560 printk(KERN_ERR PFX
1561 "io address range already allocated\n");
1562 return -EBUSY;
1563 }
1da177e4 1564
4a5e8e29
JG		 1565 err = pcnet32_probe1(ioaddr, 1, pdev);
1566 if (err < 0) {
1567 pci_disable_device(pdev);
1568 }
1569 return err;
1da177e4
LT		 1570}
1571
1da177e4
LT		 1572/* pcnet32_probe1
1573 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1574 * pdev will be NULL when called from pcnet32_probe_vlbus.
1575 */
1576static int __devinit
1577pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1578{
4a5e8e29 1579 struct pcnet32_private *lp;
4a5e8e29
JG		 1580 int i, media;
1581 int fdx, mii, fset, dxsuflo;
1582 int chip_version;
1583 char *chipname;
1584 struct net_device *dev;
1585 struct pcnet32_access *a = NULL;
1586 u8 promaddr[6];
1587 int ret = -ENODEV;
1588
1589 /* reset the chip */
1590 pcnet32_wio_reset(ioaddr);
1591
1592 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1593 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1594 a = &pcnet32_wio;
1595 } else {
1596 pcnet32_dwio_reset(ioaddr);
1597 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1598 && pcnet32_dwio_check(ioaddr)) {
1599 a = &pcnet32_dwio;
1600 } else
1601 goto err_release_region;
1602 }
1603
1604 chip_version =
1605 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1606 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1607 printk(KERN_INFO " PCnet chip version is %#x.\n",
1608 chip_version);
1609 if ((chip_version & 0xfff) != 0x003) {
1610 if (pcnet32_debug & NETIF_MSG_PROBE)
1611 printk(KERN_INFO PFX "Unsupported chip version.\n");
1612 goto err_release_region;
1613 }
1614
1615 /* initialize variables */
1616 fdx = mii = fset = dxsuflo = 0;
1617 chip_version = (chip_version >> 12) & 0xffff;
1618
1619 switch (chip_version) {
1620 case 0x2420:
1621 chipname = "PCnet/PCI 79C970"; /* PCI */
1622 break;
1623 case 0x2430:
1624 if (shared)
1625 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1626 else
1627 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1628 break;
1629 case 0x2621:
1630 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1631 fdx = 1;
1632 break;
1633 case 0x2623:
1634 chipname = "PCnet/FAST 79C971"; /* PCI */
1635 fdx = 1;
1636 mii = 1;
1637 fset = 1;
1638 break;
1639 case 0x2624:
1640 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1641 fdx = 1;
1642 mii = 1;
1643 fset = 1;
1644 break;
1645 case 0x2625:
1646 chipname = "PCnet/FAST III 79C973"; /* PCI */
1647 fdx = 1;
1648 mii = 1;
1649 break;
1650 case 0x2626:
1651 chipname = "PCnet/Home 79C978"; /* PCI */
1652 fdx = 1;
1653 /*
1654 * This is based on specs published at www.amd.com. This section
1655 * assumes that a card with a 79C978 wants to go into standard
1656 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1657 * and the module option homepna=1 can select this instead.
1658 */
1659 media = a->read_bcr(ioaddr, 49);
1660 media &= ~3; /* default to 10Mb ethernet */
1661 if (cards_found < MAX_UNITS && homepna[cards_found])
1662 media |= 1; /* switch to home wiring mode */
1663 if (pcnet32_debug & NETIF_MSG_PROBE)
1664 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1665 (media & 1) ? "1" : "10");
1666 a->write_bcr(ioaddr, 49, media);
1667 break;
1668 case 0x2627:
1669 chipname = "PCnet/FAST III 79C975"; /* PCI */
1670 fdx = 1;
1671 mii = 1;
1672 break;
1673 case 0x2628:
1674 chipname = "PCnet/PRO 79C976";
1675 fdx = 1;
1676 mii = 1;
1677 break;
1678 default:
1679 if (pcnet32_debug & NETIF_MSG_PROBE)
1680 printk(KERN_INFO PFX
1681 "PCnet version %#x, no PCnet32 chip.\n",
1682 chip_version);
1683 goto err_release_region;
1684 }
1685
1da177e4 1686 /*
4a5e8e29
JG		 1687 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1688 * starting until the packet is loaded. Strike one for reliability, lose
1689 * one for latency - although on PCI this isnt a big loss. Older chips
1690 * have FIFO's smaller than a packet, so you can't do this.
1691 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1da177e4 1692 */
4a5e8e29
JG		 1693
1694 if (fset) {
1695 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1696 a->write_csr(ioaddr, 80,
1697 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1698 dxsuflo = 1;
1699 }
1700
6ecb7667 1701 dev = alloc_etherdev(sizeof(*lp));
4a5e8e29
JG		 1702 if (!dev) {
1703 if (pcnet32_debug & NETIF_MSG_PROBE)
1704 printk(KERN_ERR PFX "Memory allocation failed.\n");
1705 ret = -ENOMEM;
1706 goto err_release_region;
1707 }
1708 SET_NETDEV_DEV(dev, &pdev->dev);
1709
1da177e4 1710 if (pcnet32_debug & NETIF_MSG_PROBE)
4a5e8e29
JG		 1711 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1712
1713 /* In most chips, after a chip reset, the ethernet address is read from the
1714 * station address PROM at the base address and programmed into the
1715 * "Physical Address Registers" CSR12-14.
1716 * As a precautionary measure, we read the PROM values and complain if
bc0e1fc9
LV		 1717 * they disagree with the CSRs. If they miscompare, and the PROM addr
1718 * is valid, then the PROM addr is used.
4a5e8e29
JG		 1719 */
1720 for (i = 0; i < 3; i++) {
1721 unsigned int val;
1722 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1723 /* There may be endianness issues here. */
1724 dev->dev_addr[2 * i] = val & 0x0ff;
1725 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1726 }
1727
1728 /* read PROM address and compare with CSR address */
1da177e4 1729 for (i = 0; i < 6; i++)
4a5e8e29
JG		 1730 promaddr[i] = inb(ioaddr + i);
1731
1732 if (memcmp(promaddr, dev->dev_addr, 6)
1733 || !is_valid_ether_addr(dev->dev_addr)) {
1734 if (is_valid_ether_addr(promaddr)) {
1735 if (pcnet32_debug & NETIF_MSG_PROBE) {
1736 printk(" warning: CSR address invalid,\n");
1737 printk(KERN_INFO
1738 " using instead PROM address of");
1739 }
1740 memcpy(dev->dev_addr, promaddr, 6);
1741 }
1742 }
1743 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1744
1745 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1746 if (!is_valid_ether_addr(dev->perm_addr))
1747 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1748
1749 if (pcnet32_debug & NETIF_MSG_PROBE) {
e174961c 1750 printk(" %pM", dev->dev_addr);
4a5e8e29
JG		 1751
1752 /* Version 0x2623 and 0x2624 */
1753 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1754 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1755 printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
1756 switch (i >> 10) {
1757 case 0:
1758 printk(" 20 bytes,");
1759 break;
1760 case 1:
1761 printk(" 64 bytes,");
1762 break;
1763 case 2:
1764 printk(" 128 bytes,");
1765 break;
1766 case 3:
1767 printk("~220 bytes,");
1768 break;
1769 }
1770 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1771 printk(" BCR18(%x):", i & 0xffff);
1772 if (i & (1 << 5))
1773 printk("BurstWrEn ");
1774 if (i & (1 << 6))
1775 printk("BurstRdEn ");
1776 if (i & (1 << 7))
1777 printk("DWordIO ");
1778 if (i & (1 << 11))
1779 printk("NoUFlow ");
1780 i = a->read_bcr(ioaddr, 25);
1781 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
1782 i = a->read_bcr(ioaddr, 26);
1783 printk(" SRAM_BND=0x%04x,", i << 8);
1784 i = a->read_bcr(ioaddr, 27);
1785 if (i & (1 << 14))
1786 printk("LowLatRx");
1787 }
1788 }
1789
1790 dev->base_addr = ioaddr;
1e56a4b4 1791 lp = netdev_priv(dev);
4a5e8e29 1792 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
6ecb7667
DF		 1793 if ((lp->init_block =
1794 pci_alloc_consistent(pdev, sizeof(*lp->init_block), &lp->init_dma_addr)) == NULL) {
4a5e8e29
JG		 1795 if (pcnet32_debug & NETIF_MSG_PROBE)
1796 printk(KERN_ERR PFX
1797 "Consistent memory allocation failed.\n");
1798 ret = -ENOMEM;
1799 goto err_free_netdev;
1800 }
4a5e8e29
JG		 1801 lp->pci_dev = pdev;
1802
bea3348e
SH		 1803 lp->dev = dev;
1804
4a5e8e29
JG		 1805 spin_lock_init(&lp->lock);
1806
4a5e8e29 1807 SET_NETDEV_DEV(dev, &pdev->dev);
4a5e8e29
JG		 1808 lp->name = chipname;
1809 lp->shared_irq = shared;
1810 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1811 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1812 lp->tx_mod_mask = lp->tx_ring_size - 1;
1813 lp->rx_mod_mask = lp->rx_ring_size - 1;
1814 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1815 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1816 lp->mii_if.full_duplex = fdx;
1817 lp->mii_if.phy_id_mask = 0x1f;
1818 lp->mii_if.reg_num_mask = 0x1f;
1819 lp->dxsuflo = dxsuflo;
1820 lp->mii = mii;
8d916266 1821 lp->chip_version = chip_version;
4a5e8e29
JG		 1822 lp->msg_enable = pcnet32_debug;
1823 if ((cards_found >= MAX_UNITS)
1824 || (options[cards_found] > sizeof(options_mapping)))
1825 lp->options = PCNET32_PORT_ASEL;
1826 else
1827 lp->options = options_mapping[options[cards_found]];
1828 lp->mii_if.dev = dev;
1829 lp->mii_if.mdio_read = mdio_read;
1830 lp->mii_if.mdio_write = mdio_write;
1831
feff348f
DF		 1832 /* napi.weight is used in both the napi and non-napi cases */
1833 lp->napi.weight = lp->rx_ring_size / 2;
1834
bea3348e 1835 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
bea3348e 1836
4a5e8e29
JG		 1837 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1838 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1839 lp->options |= PCNET32_PORT_FD;
1840
1841 if (!a) {
1842 if (pcnet32_debug & NETIF_MSG_PROBE)
1843 printk(KERN_ERR PFX "No access methods\n");
1844 ret = -ENODEV;
1845 goto err_free_consistent;
1846 }
1847 lp->a = *a;
1848
1849 /* prior to register_netdev, dev->name is not yet correct */
1850 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1851 ret = -ENOMEM;
1852 goto err_free_ring;
1853 }
1854 /* detect special T1/E1 WAN card by checking for MAC address */
1855 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1da177e4 1856 && dev->dev_addr[2] == 0x75)
4a5e8e29 1857 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1da177e4 1858
3e33545b 1859 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */
6ecb7667 1860 lp->init_block->tlen_rlen =
3e33545b 1861 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
4a5e8e29 1862 for (i = 0; i < 6; i++)
6ecb7667
DF		 1863 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1864 lp->init_block->filter[0] = 0x00000000;
1865 lp->init_block->filter[1] = 0x00000000;
3e33545b
AV		 1866 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1867 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
4a5e8e29
JG		 1868
1869 /* switch pcnet32 to 32bit mode */
1870 a->write_bcr(ioaddr, 20, 2);
1871
6ecb7667
DF		 1872 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1873 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29
JG		 1874
1875 if (pdev) { /* use the IRQ provided by PCI */
1876 dev->irq = pdev->irq;
1877 if (pcnet32_debug & NETIF_MSG_PROBE)
1878 printk(" assigned IRQ %d.\n", dev->irq);
1879 } else {
1880 unsigned long irq_mask = probe_irq_on();
1881
1882 /*
1883 * To auto-IRQ we enable the initialization-done and DMA error
1884 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1885 * boards will work.
1886 */
1887 /* Trigger an initialization just for the interrupt. */
b368a3fb 1888 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
4a5e8e29
JG		 1889 mdelay(1);
1890
1891 dev->irq = probe_irq_off(irq_mask);
1892 if (!dev->irq) {
1893 if (pcnet32_debug & NETIF_MSG_PROBE)
1894 printk(", failed to detect IRQ line.\n");
1895 ret = -ENODEV;
1896 goto err_free_ring;
1897 }
1898 if (pcnet32_debug & NETIF_MSG_PROBE)
1899 printk(", probed IRQ %d.\n", dev->irq);
1900 }
1da177e4 1901
4a5e8e29
JG		 1902 /* Set the mii phy_id so that we can query the link state */
1903 if (lp->mii) {
1904 /* lp->phycount and lp->phymask are set to 0 by memset above */
1905
1906 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1907 /* scan for PHYs */
1908 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1909 unsigned short id1, id2;
1910
1911 id1 = mdio_read(dev, i, MII_PHYSID1);
1912 if (id1 == 0xffff)
1913 continue;
1914 id2 = mdio_read(dev, i, MII_PHYSID2);
1915 if (id2 == 0xffff)
1916 continue;
1917 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1918 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1919 lp->phycount++;
1920 lp->phymask |= (1 << i);
1921 lp->mii_if.phy_id = i;
1922 if (pcnet32_debug & NETIF_MSG_PROBE)
1923 printk(KERN_INFO PFX
1924 "Found PHY %04x:%04x at address %d.\n",
1925 id1, id2, i);
1926 }
1927 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1928 if (lp->phycount > 1) {
1929 lp->options |= PCNET32_PORT_MII;
1930 }
1da177e4 1931 }
4a5e8e29
JG		 1932
1933 init_timer(&lp->watchdog_timer);
1934 lp->watchdog_timer.data = (unsigned long)dev;
1935 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1936
1937 /* The PCNET32-specific entries in the device structure. */
1938 dev->open = &pcnet32_open;
1939 dev->hard_start_xmit = &pcnet32_start_xmit;
1940 dev->stop = &pcnet32_close;
1941 dev->get_stats = &pcnet32_get_stats;
1942 dev->set_multicast_list = &pcnet32_set_multicast_list;
1943 dev->do_ioctl = &pcnet32_ioctl;
1944 dev->ethtool_ops = &pcnet32_ethtool_ops;
1945 dev->tx_timeout = pcnet32_tx_timeout;
1946 dev->watchdog_timeo = (5 * HZ);
1da177e4
LT		 1947
1948#ifdef CONFIG_NET_POLL_CONTROLLER
4a5e8e29 1949 dev->poll_controller = pcnet32_poll_controller;
1da177e4
LT		 1950#endif
1951
4a5e8e29
JG		 1952 /* Fill in the generic fields of the device structure. */
1953 if (register_netdev(dev))
1954 goto err_free_ring;
1955
1956 if (pdev) {
1957 pci_set_drvdata(pdev, dev);
1958 } else {
1959 lp->next = pcnet32_dev;
1960 pcnet32_dev = dev;
1961 }
1962
1963 if (pcnet32_debug & NETIF_MSG_PROBE)
1964 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1965 cards_found++;
1966
1967 /* enable LED writes */
1968 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1da177e4 1969
4a5e8e29
JG		 1970 return 0;
1971
1972 err_free_ring:
1973 pcnet32_free_ring(dev);
1974 err_free_consistent:
7d2e3cb7 1975 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 1976 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 1977 err_free_netdev:
1978 free_netdev(dev);
1979 err_release_region:
1980 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1981 return ret;
1982}
1da177e4 1983
a88c844c 1984/* if any allocation fails, caller must also call pcnet32_free_ring */
b166cfba 1985static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
eabf0415 1986{
1e56a4b4 1987 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 1988
4a5e8e29
JG		 1989 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1990 sizeof(struct pcnet32_tx_head) *
1991 lp->tx_ring_size,
1992 &lp->tx_ring_dma_addr);
1993 if (lp->tx_ring == NULL) {
12fa30f3 1994 if (netif_msg_drv(lp))
4a5e8e29
JG		 1995 printk("\n" KERN_ERR PFX
1996 "%s: Consistent memory allocation failed.\n",
1997 name);
1998 return -ENOMEM;
1999 }
eabf0415 2000
4a5e8e29
JG		 2001 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
2002 sizeof(struct pcnet32_rx_head) *
2003 lp->rx_ring_size,
2004 &lp->rx_ring_dma_addr);
2005 if (lp->rx_ring == NULL) {
12fa30f3 2006 if (netif_msg_drv(lp))
4a5e8e29
JG		 2007 printk("\n" KERN_ERR PFX
2008 "%s: Consistent memory allocation failed.\n",
2009 name);
2010 return -ENOMEM;
2011 }
eabf0415 2012
12fa30f3 2013 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 2014 GFP_ATOMIC);
2015 if (!lp->tx_dma_addr) {
12fa30f3 2016 if (netif_msg_drv(lp))
4a5e8e29
JG		 2017 printk("\n" KERN_ERR PFX
2018 "%s: Memory allocation failed.\n", name);
2019 return -ENOMEM;
2020 }
4a5e8e29 2021
12fa30f3 2022 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 2023 GFP_ATOMIC);
2024 if (!lp->rx_dma_addr) {
12fa30f3 2025 if (netif_msg_drv(lp))
4a5e8e29
JG		 2026 printk("\n" KERN_ERR PFX
2027 "%s: Memory allocation failed.\n", name);
2028 return -ENOMEM;
2029 }
4a5e8e29 2030
12fa30f3 2031 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 2032 GFP_ATOMIC);
2033 if (!lp->tx_skbuff) {
12fa30f3 2034 if (netif_msg_drv(lp))
4a5e8e29
JG		 2035 printk("\n" KERN_ERR PFX
2036 "%s: Memory allocation failed.\n", name);
2037 return -ENOMEM;
2038 }
4a5e8e29 2039
12fa30f3 2040 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 2041 GFP_ATOMIC);
2042 if (!lp->rx_skbuff) {
12fa30f3 2043 if (netif_msg_drv(lp))
4a5e8e29
JG		 2044 printk("\n" KERN_ERR PFX
2045 "%s: Memory allocation failed.\n", name);
2046 return -ENOMEM;
2047 }
4a5e8e29
JG		 2048
2049 return 0;
2050}
eabf0415
HWL		 2051
2052static void pcnet32_free_ring(struct net_device *dev)
2053{
1e56a4b4 2054 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 2055
4a5e8e29
JG		 2056 kfree(lp->tx_skbuff);
2057 lp->tx_skbuff = NULL;
eabf0415 2058
4a5e8e29
JG		 2059 kfree(lp->rx_skbuff);
2060 lp->rx_skbuff = NULL;
eabf0415 2061
4a5e8e29
JG		 2062 kfree(lp->tx_dma_addr);
2063 lp->tx_dma_addr = NULL;
eabf0415 2064
4a5e8e29
JG		 2065 kfree(lp->rx_dma_addr);
2066 lp->rx_dma_addr = NULL;
eabf0415 2067
4a5e8e29
JG		 2068 if (lp->tx_ring) {
2069 pci_free_consistent(lp->pci_dev,
2070 sizeof(struct pcnet32_tx_head) *
2071 lp->tx_ring_size, lp->tx_ring,
2072 lp->tx_ring_dma_addr);
2073 lp->tx_ring = NULL;
2074 }
eabf0415 2075
4a5e8e29
JG		 2076 if (lp->rx_ring) {
2077 pci_free_consistent(lp->pci_dev,
2078 sizeof(struct pcnet32_rx_head) *
2079 lp->rx_ring_size, lp->rx_ring,
2080 lp->rx_ring_dma_addr);
2081 lp->rx_ring = NULL;
2082 }
eabf0415
HWL		 2083}
2084
4a5e8e29 2085static int pcnet32_open(struct net_device *dev)
1da177e4 2086{
1e56a4b4 2087 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2088 unsigned long ioaddr = dev->base_addr;
2089 u16 val;
2090 int i;
2091 int rc;
2092 unsigned long flags;
2093
2094 if (request_irq(dev->irq, &pcnet32_interrupt,
1fb9df5d 2095 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
4a5e8e29
JG		 2096 (void *)dev)) {
2097 return -EAGAIN;
2098 }
2099
2100 spin_lock_irqsave(&lp->lock, flags);
2101 /* Check for a valid station address */
2102 if (!is_valid_ether_addr(dev->dev_addr)) {
2103 rc = -EINVAL;
2104 goto err_free_irq;
2105 }
2106
2107 /* Reset the PCNET32 */
2108 lp->a.reset(ioaddr);
2109
2110 /* switch pcnet32 to 32bit mode */
2111 lp->a.write_bcr(ioaddr, 20, 2);
2112
2113 if (netif_msg_ifup(lp))
2114 printk(KERN_DEBUG
2115 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2116 dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
2117 (u32) (lp->rx_ring_dma_addr),
6ecb7667 2118 (u32) (lp->init_dma_addr));
4a5e8e29
JG		 2119
2120 /* set/reset autoselect bit */
2121 val = lp->a.read_bcr(ioaddr, 2) & ~2;
2122 if (lp->options & PCNET32_PORT_ASEL)
1da177e4 2123 val |= 2;
4a5e8e29
JG		 2124 lp->a.write_bcr(ioaddr, 2, val);
2125
2126 /* handle full duplex setting */
2127 if (lp->mii_if.full_duplex) {
2128 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2129 if (lp->options & PCNET32_PORT_FD) {
2130 val |= 1;
2131 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2132 val |= 2;
2133 } else if (lp->options & PCNET32_PORT_ASEL) {
2134 /* workaround of xSeries250, turn on for 79C975 only */
8d916266 2135 if (lp->chip_version == 0x2627)
4a5e8e29
JG		 2136 val |= 3;
2137 }
2138 lp->a.write_bcr(ioaddr, 9, val);
2139 }
2140
2141 /* set/reset GPSI bit in test register */
2142 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2143 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2144 val |= 0x10;
2145 lp->a.write_csr(ioaddr, 124, val);
2146
2147 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2148 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2964bbd7
DF		 2149 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2150 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
ac62ef04 2151 if (lp->options & PCNET32_PORT_ASEL) {
4a5e8e29
JG		 2152 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2153 if (netif_msg_link(lp))
2154 printk(KERN_DEBUG
2155 "%s: Setting 100Mb-Full Duplex.\n",
2156 dev->name);
2157 }
2158 }
2159 if (lp->phycount < 2) {
2160 /*
2161 * 24 Jun 2004 according AMD, in order to change the PHY,
2162 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2163 * duplex, and/or enable auto negotiation, and clear DANAS
2164 */
2165 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2166 lp->a.write_bcr(ioaddr, 32,
2167 lp->a.read_bcr(ioaddr, 32) | 0x0080);
2168 /* disable Auto Negotiation, set 10Mpbs, HD */
2169 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2170 if (lp->options & PCNET32_PORT_FD)
2171 val |= 0x10;
2172 if (lp->options & PCNET32_PORT_100)
2173 val |= 0x08;
2174 lp->a.write_bcr(ioaddr, 32, val);
2175 } else {
2176 if (lp->options & PCNET32_PORT_ASEL) {
2177 lp->a.write_bcr(ioaddr, 32,
2178 lp->a.read_bcr(ioaddr,
2179 32) | 0x0080);
2180 /* enable auto negotiate, setup, disable fd */
2181 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2182 val |= 0x20;
2183 lp->a.write_bcr(ioaddr, 32, val);
2184 }
2185 }
2186 } else {
2187 int first_phy = -1;
2188 u16 bmcr;
2189 u32 bcr9;
2190 struct ethtool_cmd ecmd;
2191
2192 /*
2193 * There is really no good other way to handle multiple PHYs
2194 * other than turning off all automatics
2195 */
2196 val = lp->a.read_bcr(ioaddr, 2);
2197 lp->a.write_bcr(ioaddr, 2, val & ~2);
2198 val = lp->a.read_bcr(ioaddr, 32);
2199 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2200
2201 if (!(lp->options & PCNET32_PORT_ASEL)) {
2202 /* setup ecmd */
2203 ecmd.port = PORT_MII;
2204 ecmd.transceiver = XCVR_INTERNAL;
2205 ecmd.autoneg = AUTONEG_DISABLE;
2206 ecmd.speed =
2207 lp->
2208 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2209 bcr9 = lp->a.read_bcr(ioaddr, 9);
2210
2211 if (lp->options & PCNET32_PORT_FD) {
2212 ecmd.duplex = DUPLEX_FULL;
2213 bcr9 |= (1 << 0);
2214 } else {
2215 ecmd.duplex = DUPLEX_HALF;
2216 bcr9 |= ~(1 << 0);
2217 }
2218 lp->a.write_bcr(ioaddr, 9, bcr9);
ac62ef04 2219 }
4a5e8e29
JG		 2220
2221 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2222 if (lp->phymask & (1 << i)) {
2223 /* isolate all but the first PHY */
2224 bmcr = mdio_read(dev, i, MII_BMCR);
2225 if (first_phy == -1) {
2226 first_phy = i;
2227 mdio_write(dev, i, MII_BMCR,
2228 bmcr & ~BMCR_ISOLATE);
2229 } else {
2230 mdio_write(dev, i, MII_BMCR,
2231 bmcr | BMCR_ISOLATE);
2232 }
2233 /* use mii_ethtool_sset to setup PHY */
2234 lp->mii_if.phy_id = i;
2235 ecmd.phy_address = i;
2236 if (lp->options & PCNET32_PORT_ASEL) {
2237 mii_ethtool_gset(&lp->mii_if, &ecmd);
2238 ecmd.autoneg = AUTONEG_ENABLE;
2239 }
2240 mii_ethtool_sset(&lp->mii_if, &ecmd);
2241 }
2242 }
2243 lp->mii_if.phy_id = first_phy;
2244 if (netif_msg_link(lp))
2245 printk(KERN_INFO "%s: Using PHY number %d.\n",
2246 dev->name, first_phy);
2247 }
1da177e4
LT		 2248
2249#ifdef DO_DXSUFLO
4a5e8e29 2250 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
b368a3fb 2251 val = lp->a.read_csr(ioaddr, CSR3);
4a5e8e29 2252 val |= 0x40;
b368a3fb 2253 lp->a.write_csr(ioaddr, CSR3, val);
4a5e8e29 2254 }
1da177e4
LT		 2255#endif
2256
6ecb7667 2257 lp->init_block->mode =
3e33545b 2258 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
4a5e8e29
JG		 2259 pcnet32_load_multicast(dev);
2260
2261 if (pcnet32_init_ring(dev)) {
2262 rc = -ENOMEM;
2263 goto err_free_ring;
2264 }
2265
bea3348e 2266 napi_enable(&lp->napi);
bea3348e 2267
4a5e8e29 2268 /* Re-initialize the PCNET32, and start it when done. */
6ecb7667
DF		 2269 lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2270 lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29 2271
b368a3fb
DF		 2272 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2273 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2274
2275 netif_start_queue(dev);
2276
8d916266
DF		 2277 if (lp->chip_version >= PCNET32_79C970A) {
2278 /* Print the link status and start the watchdog */
2279 pcnet32_check_media(dev, 1);
2280 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2281 }
4a5e8e29
JG		 2282
2283 i = 0;
2284 while (i++ < 100)
b368a3fb 2285 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29
JG		 2286 break;
2287 /*
2288 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2289 * reports that doing so triggers a bug in the '974.
2290 */
b368a3fb 2291 lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
4a5e8e29
JG		 2292
2293 if (netif_msg_ifup(lp))
2294 printk(KERN_DEBUG
2295 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2296 dev->name, i,
6ecb7667 2297 (u32) (lp->init_dma_addr),
b368a3fb 2298 lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2299
2300 spin_unlock_irqrestore(&lp->lock, flags);
2301
2302 return 0; /* Always succeed */
2303
2304 err_free_ring:
2305 /* free any allocated skbuffs */
ac5bfe40 2306 pcnet32_purge_rx_ring(dev);
4a5e8e29 2307
4a5e8e29
JG		 2308 /*
2309 * Switch back to 16bit mode to avoid problems with dumb
2310 * DOS packet driver after a warm reboot
2311 */
2312 lp->a.write_bcr(ioaddr, 20, 4);
2313
2314 err_free_irq:
2315 spin_unlock_irqrestore(&lp->lock, flags);
2316 free_irq(dev->irq, dev);
2317 return rc;
1da177e4
LT		 2318}
2319
2320/*
2321 * The LANCE has been halted for one reason or another (busmaster memory
2322 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2323 * etc.). Modern LANCE variants always reload their ring-buffer
2324 * configuration when restarted, so we must reinitialize our ring
2325 * context before restarting. As part of this reinitialization,
2326 * find all packets still on the Tx ring and pretend that they had been
2327 * sent (in effect, drop the packets on the floor) - the higher-level
2328 * protocols will time out and retransmit. It'd be better to shuffle
2329 * these skbs to a temp list and then actually re-Tx them after
2330 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2331 */
2332
4a5e8e29 2333static void pcnet32_purge_tx_ring(struct net_device *dev)
1da177e4 2334{
1e56a4b4 2335 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2336 int i;
1da177e4 2337
4a5e8e29
JG		 2338 for (i = 0; i < lp->tx_ring_size; i++) {
2339 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2340 wmb(); /* Make sure adapter sees owner change */
2341 if (lp->tx_skbuff[i]) {
2342 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2343 lp->tx_skbuff[i]->len,
2344 PCI_DMA_TODEVICE);
2345 dev_kfree_skb_any(lp->tx_skbuff[i]);
2346 }
2347 lp->tx_skbuff[i] = NULL;
2348 lp->tx_dma_addr[i] = 0;
2349 }
2350}
1da177e4
LT		 2351
2352/* Initialize the PCNET32 Rx and Tx rings. */
4a5e8e29 2353static int pcnet32_init_ring(struct net_device *dev)
1da177e4 2354{
1e56a4b4 2355 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2356 int i;
2357
2358 lp->tx_full = 0;
2359 lp->cur_rx = lp->cur_tx = 0;
2360 lp->dirty_rx = lp->dirty_tx = 0;
2361
2362 for (i = 0; i < lp->rx_ring_size; i++) {
2363 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2364 if (rx_skbuff == NULL) {
2365 if (!
2366 (rx_skbuff = lp->rx_skbuff[i] =
232c5640 2367 dev_alloc_skb(PKT_BUF_SKB))) {
4a5e8e29 2368 /* there is not much, we can do at this point */
b368a3fb 2369 if (netif_msg_drv(lp))
4a5e8e29
JG		 2370 printk(KERN_ERR
2371 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2372 dev->name);
2373 return -1;
2374 }
232c5640 2375 skb_reserve(rx_skbuff, NET_IP_ALIGN);
4a5e8e29
JG		 2376 }
2377
2378 rmb();
2379 if (lp->rx_dma_addr[i] == 0)
2380 lp->rx_dma_addr[i] =
2381 pci_map_single(lp->pci_dev, rx_skbuff->data,
232c5640 2382 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
3e33545b 2383 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
232c5640 2384 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
4a5e8e29 2385 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 2386 lp->rx_ring[i].status = cpu_to_le16(0x8000);
4a5e8e29
JG		 2387 }
2388 /* The Tx buffer address is filled in as needed, but we do need to clear
2389 * the upper ownership bit. */
2390 for (i = 0; i < lp->tx_ring_size; i++) {
2391 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2392 wmb(); /* Make sure adapter sees owner change */
2393 lp->tx_ring[i].base = 0;
2394 lp->tx_dma_addr[i] = 0;
2395 }
2396
6ecb7667 2397 lp->init_block->tlen_rlen =
3e33545b 2398 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
4a5e8e29 2399 for (i = 0; i < 6; i++)
6ecb7667 2400 lp->init_block->phys_addr[i] = dev->dev_addr[i];
3e33545b
AV		 2401 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2402 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
4a5e8e29
JG		 2403 wmb(); /* Make sure all changes are visible */
2404 return 0;
1da177e4
LT		 2405}
2406
2407/* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2408 * then flush the pending transmit operations, re-initialize the ring,
2409 * and tell the chip to initialize.
2410 */
4a5e8e29 2411static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1da177e4 2412{
1e56a4b4 2413 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2414 unsigned long ioaddr = dev->base_addr;
2415 int i;
1da177e4 2416
4a5e8e29
JG		 2417 /* wait for stop */
2418 for (i = 0; i < 100; i++)
b368a3fb 2419 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
4a5e8e29 2420 break;
1da177e4 2421
4a5e8e29
JG		 2422 if (i >= 100 && netif_msg_drv(lp))
2423 printk(KERN_ERR
2424 "%s: pcnet32_restart timed out waiting for stop.\n",
2425 dev->name);
1da177e4 2426
4a5e8e29
JG		 2427 pcnet32_purge_tx_ring(dev);
2428 if (pcnet32_init_ring(dev))
2429 return;
1da177e4 2430
4a5e8e29 2431 /* ReInit Ring */
b368a3fb 2432 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2433 i = 0;
2434 while (i++ < 1000)
b368a3fb 2435 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29 2436 break;
1da177e4 2437
b368a3fb 2438 lp->a.write_csr(ioaddr, CSR0, csr0_bits);
1da177e4
LT		 2439}
2440
4a5e8e29 2441static void pcnet32_tx_timeout(struct net_device *dev)
1da177e4 2442{
1e56a4b4 2443 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2444 unsigned long ioaddr = dev->base_addr, flags;
2445
2446 spin_lock_irqsave(&lp->lock, flags);
2447 /* Transmitter timeout, serious problems. */
2448 if (pcnet32_debug & NETIF_MSG_DRV)
2449 printk(KERN_ERR
2450 "%s: transmit timed out, status %4.4x, resetting.\n",
b368a3fb
DF		 2451 dev->name, lp->a.read_csr(ioaddr, CSR0));
2452 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
4f1e5ba0 2453 dev->stats.tx_errors++;
4a5e8e29
JG		 2454 if (netif_msg_tx_err(lp)) {
2455 int i;
2456 printk(KERN_DEBUG
2457 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2458 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2459 lp->cur_rx);
2460 for (i = 0; i < lp->rx_ring_size; i++)
2461 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2462 le32_to_cpu(lp->rx_ring[i].base),
2463 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2464 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2465 le16_to_cpu(lp->rx_ring[i].status));
2466 for (i = 0; i < lp->tx_ring_size; i++)
2467 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2468 le32_to_cpu(lp->tx_ring[i].base),
2469 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2470 le32_to_cpu(lp->tx_ring[i].misc),
2471 le16_to_cpu(lp->tx_ring[i].status));
2472 printk("\n");
2473 }
b368a3fb 2474 pcnet32_restart(dev, CSR0_NORMAL);
1da177e4 2475
4a5e8e29
JG		 2476 dev->trans_start = jiffies;
2477 netif_wake_queue(dev);
1da177e4 2478
4a5e8e29
JG		 2479 spin_unlock_irqrestore(&lp->lock, flags);
2480}
2481
2482static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 2483{
1e56a4b4 2484 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2485 unsigned long ioaddr = dev->base_addr;
2486 u16 status;
2487 int entry;
2488 unsigned long flags;
1da177e4 2489
4a5e8e29 2490 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2491
4a5e8e29
JG		 2492 if (netif_msg_tx_queued(lp)) {
2493 printk(KERN_DEBUG
2494 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
b368a3fb 2495 dev->name, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29 2496 }
1da177e4 2497
4a5e8e29
JG		 2498 /* Default status -- will not enable Successful-TxDone
2499 * interrupt when that option is available to us.
2500 */
2501 status = 0x8300;
1da177e4 2502
4a5e8e29 2503 /* Fill in a Tx ring entry */
1da177e4 2504
4a5e8e29
JG		 2505 /* Mask to ring buffer boundary. */
2506 entry = lp->cur_tx & lp->tx_mod_mask;
1da177e4 2507
4a5e8e29
JG		 2508 /* Caution: the write order is important here, set the status
2509 * with the "ownership" bits last. */
1da177e4 2510
3e33545b 2511 lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
1da177e4 2512
4a5e8e29 2513 lp->tx_ring[entry].misc = 0x00000000;
1da177e4 2514
4a5e8e29
JG		 2515 lp->tx_skbuff[entry] = skb;
2516 lp->tx_dma_addr[entry] =
2517 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
3e33545b 2518 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
4a5e8e29 2519 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 2520 lp->tx_ring[entry].status = cpu_to_le16(status);
1da177e4 2521
4a5e8e29 2522 lp->cur_tx++;
4f1e5ba0 2523 dev->stats.tx_bytes += skb->len;
1da177e4 2524
4a5e8e29 2525 /* Trigger an immediate send poll. */
b368a3fb 2526 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
1da177e4 2527
4a5e8e29 2528 dev->trans_start = jiffies;
1da177e4 2529
4a5e8e29
JG		 2530 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2531 lp->tx_full = 1;
2532 netif_stop_queue(dev);
2533 }
2534 spin_unlock_irqrestore(&lp->lock, flags);
2535 return 0;
1da177e4
LT		 2536}
2537
2538/* The PCNET32 interrupt handler. */
2539static irqreturn_t
7d12e780 2540pcnet32_interrupt(int irq, void *dev_id)
1da177e4 2541{
4a5e8e29
JG		 2542 struct net_device *dev = dev_id;
2543 struct pcnet32_private *lp;
2544 unsigned long ioaddr;
5c99346a 2545 u16 csr0;
4a5e8e29 2546 int boguscnt = max_interrupt_work;
4a5e8e29 2547
4a5e8e29 2548 ioaddr = dev->base_addr;
1e56a4b4 2549 lp = netdev_priv(dev);
1da177e4 2550
4a5e8e29
JG		 2551 spin_lock(&lp->lock);
2552
3904c324
DF		 2553 csr0 = lp->a.read_csr(ioaddr, CSR0);
2554 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
4a5e8e29
JG		 2555 if (csr0 == 0xffff) {
2556 break; /* PCMCIA remove happened */
2557 }
2558 /* Acknowledge all of the current interrupt sources ASAP. */
3904c324 2559 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
4a5e8e29 2560
4a5e8e29
JG		 2561 if (netif_msg_intr(lp))
2562 printk(KERN_DEBUG
2563 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
3904c324 2564 dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29 2565
4a5e8e29
JG		 2566 /* Log misc errors. */
2567 if (csr0 & 0x4000)
4f1e5ba0 2568 dev->stats.tx_errors++; /* Tx babble. */
4a5e8e29
JG		 2569 if (csr0 & 0x1000) {
2570 /*
3904c324
DF		 2571 * This happens when our receive ring is full. This
2572 * shouldn't be a problem as we will see normal rx
2573 * interrupts for the frames in the receive ring. But
2574 * there are some PCI chipsets (I can reproduce this
2575 * on SP3G with Intel saturn chipset) which have
2576 * sometimes problems and will fill up the receive
2577 * ring with error descriptors. In this situation we
2578 * don't get a rx interrupt, but a missed frame
7de745e5 2579 * interrupt sooner or later.
4a5e8e29 2580 */
4f1e5ba0 2581 dev->stats.rx_errors++; /* Missed a Rx frame. */
4a5e8e29
JG		 2582 }
2583 if (csr0 & 0x0800) {
2584 if (netif_msg_drv(lp))
2585 printk(KERN_ERR
2586 "%s: Bus master arbitration failure, status %4.4x.\n",
2587 dev->name, csr0);
2588 /* unlike for the lance, there is no restart needed */
1da177e4 2589 }
bea3348e 2590 if (netif_rx_schedule_prep(dev, &lp->napi)) {
7de745e5
DF		 2591 u16 val;
2592 /* set interrupt masks */
2593 val = lp->a.read_csr(ioaddr, CSR3);
2594 val |= 0x5f00;
2595 lp->a.write_csr(ioaddr, CSR3, val);
2596 mmiowb();
bea3348e 2597 __netif_rx_schedule(dev, &lp->napi);
7de745e5
DF		 2598 break;
2599 }
3904c324 2600 csr0 = lp->a.read_csr(ioaddr, CSR0);
4a5e8e29
JG		 2601 }
2602
4a5e8e29
JG		 2603 if (netif_msg_intr(lp))
2604 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
b368a3fb 2605 dev->name, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2606
2607 spin_unlock(&lp->lock);
2608
2609 return IRQ_HANDLED;
1da177e4
LT		 2610}
2611
4a5e8e29 2612static int pcnet32_close(struct net_device *dev)
1da177e4 2613{
4a5e8e29 2614 unsigned long ioaddr = dev->base_addr;
1e56a4b4 2615 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2616 unsigned long flags;
1da177e4 2617
4a5e8e29 2618 del_timer_sync(&lp->watchdog_timer);
1da177e4 2619
4a5e8e29 2620 netif_stop_queue(dev);
bea3348e 2621 napi_disable(&lp->napi);
1da177e4 2622
4a5e8e29 2623 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2624
4f1e5ba0 2625 dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
1da177e4 2626
4a5e8e29
JG		 2627 if (netif_msg_ifdown(lp))
2628 printk(KERN_DEBUG
2629 "%s: Shutting down ethercard, status was %2.2x.\n",
b368a3fb 2630 dev->name, lp->a.read_csr(ioaddr, CSR0));
1da177e4 2631
4a5e8e29 2632 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
b368a3fb 2633 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
1da177e4 2634
4a5e8e29
JG		 2635 /*
2636 * Switch back to 16bit mode to avoid problems with dumb
2637 * DOS packet driver after a warm reboot
2638 */
2639 lp->a.write_bcr(ioaddr, 20, 4);
1da177e4 2640
4a5e8e29 2641 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2642
4a5e8e29 2643 free_irq(dev->irq, dev);
1da177e4 2644
4a5e8e29 2645 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2646
ac5bfe40
DF		 2647 pcnet32_purge_rx_ring(dev);
2648 pcnet32_purge_tx_ring(dev);
1da177e4 2649
4a5e8e29 2650 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2651
4a5e8e29 2652 return 0;
1da177e4
LT		 2653}
2654
4a5e8e29 2655static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
1da177e4 2656{
1e56a4b4 2657 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2658 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2659 unsigned long flags;
2660
2661 spin_lock_irqsave(&lp->lock, flags);
4f1e5ba0 2662 dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
4a5e8e29
JG		 2663 spin_unlock_irqrestore(&lp->lock, flags);
2664
4f1e5ba0 2665 return &dev->stats;
1da177e4
LT		 2666}
2667
2668/* taken from the sunlance driver, which it took from the depca driver */
4a5e8e29 2669static void pcnet32_load_multicast(struct net_device *dev)
1da177e4 2670{
1e56a4b4 2671 struct pcnet32_private *lp = netdev_priv(dev);
6ecb7667 2672 volatile struct pcnet32_init_block *ib = lp->init_block;
3e33545b 2673 volatile __le16 *mcast_table = (__le16 *)ib->filter;
4a5e8e29 2674 struct dev_mc_list *dmi = dev->mc_list;
df27f4a6 2675 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2676 char *addrs;
2677 int i;
2678 u32 crc;
2679
2680 /* set all multicast bits */
2681 if (dev->flags & IFF_ALLMULTI) {
3e33545b
AV		 2682 ib->filter[0] = cpu_to_le32(~0U);
2683 ib->filter[1] = cpu_to_le32(~0U);
df27f4a6
DF		 2684 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2685 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2686 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2687 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
4a5e8e29
JG		 2688 return;
2689 }
2690 /* clear the multicast filter */
2691 ib->filter[0] = 0;
2692 ib->filter[1] = 0;
2693
2694 /* Add addresses */
2695 for (i = 0; i < dev->mc_count; i++) {
2696 addrs = dmi->dmi_addr;
2697 dmi = dmi->next;
2698
2699 /* multicast address? */
2700 if (!(*addrs & 1))
2701 continue;
2702
2703 crc = ether_crc_le(6, addrs);
2704 crc = crc >> 26;
3e33545b 2705 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
4a5e8e29 2706 }
df27f4a6
DF		 2707 for (i = 0; i < 4; i++)
2708 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2709 le16_to_cpu(mcast_table[i]));
1da177e4 2710 return;
1da177e4
LT		 2711}
2712
1da177e4
LT		 2713/*
2714 * Set or clear the multicast filter for this adaptor.
2715 */
2716static void pcnet32_set_multicast_list(struct net_device *dev)
2717{
4a5e8e29 2718 unsigned long ioaddr = dev->base_addr, flags;
1e56a4b4 2719 struct pcnet32_private *lp = netdev_priv(dev);
df27f4a6 2720 int csr15, suspended;
4a5e8e29
JG		 2721
2722 spin_lock_irqsave(&lp->lock, flags);
df27f4a6
DF		 2723 suspended = pcnet32_suspend(dev, &flags, 0);
2724 csr15 = lp->a.read_csr(ioaddr, CSR15);
4a5e8e29
JG		 2725 if (dev->flags & IFF_PROMISC) {
2726 /* Log any net taps. */
2727 if (netif_msg_hw(lp))
2728 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2729 dev->name);
6ecb7667 2730 lp->init_block->mode =
3e33545b 2731 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
4a5e8e29 2732 7);
df27f4a6 2733 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
4a5e8e29 2734 } else {
6ecb7667 2735 lp->init_block->mode =
3e33545b 2736 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
df27f4a6 2737 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
4a5e8e29
JG		 2738 pcnet32_load_multicast(dev);
2739 }
2740
df27f4a6
DF		 2741 if (suspended) {
2742 int csr5;
2743 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2744 csr5 = lp->a.read_csr(ioaddr, CSR5);
2745 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
b368a3fb 2746 } else {
df27f4a6
DF		 2747 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2748 pcnet32_restart(dev, CSR0_NORMAL);
2749 netif_wake_queue(dev);
2750 }
4a5e8e29
JG		 2751
2752 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 2753}
2754
2755/* This routine assumes that the lp->lock is held */
2756static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2757{
1e56a4b4 2758 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2759 unsigned long ioaddr = dev->base_addr;
2760 u16 val_out;
1da177e4 2761
4a5e8e29
JG		 2762 if (!lp->mii)
2763 return 0;
1da177e4 2764
4a5e8e29
JG		 2765 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2766 val_out = lp->a.read_bcr(ioaddr, 34);
1da177e4 2767
4a5e8e29 2768 return val_out;
1da177e4
LT		 2769}
2770
2771/* This routine assumes that the lp->lock is held */
2772static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2773{
1e56a4b4 2774 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2775 unsigned long ioaddr = dev->base_addr;
1da177e4 2776
4a5e8e29
JG		 2777 if (!lp->mii)
2778 return;
1da177e4 2779
4a5e8e29
JG		 2780 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2781 lp->a.write_bcr(ioaddr, 34, val);
1da177e4
LT		 2782}
2783
2784static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2785{
1e56a4b4 2786 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2787 int rc;
2788 unsigned long flags;
1da177e4 2789
4a5e8e29
JG		 2790 /* SIOC[GS]MIIxxx ioctls */
2791 if (lp->mii) {
2792 spin_lock_irqsave(&lp->lock, flags);
2793 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2794 spin_unlock_irqrestore(&lp->lock, flags);
2795 } else {
2796 rc = -EOPNOTSUPP;
2797 }
1da177e4 2798
4a5e8e29 2799 return rc;
1da177e4
LT		 2800}
2801
ac62ef04
DF		 2802static int pcnet32_check_otherphy(struct net_device *dev)
2803{
1e56a4b4 2804 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2805 struct mii_if_info mii = lp->mii_if;
2806 u16 bmcr;
2807 int i;
ac62ef04 2808
4a5e8e29
JG		 2809 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2810 if (i == lp->mii_if.phy_id)
2811 continue; /* skip active phy */
2812 if (lp->phymask & (1 << i)) {
2813 mii.phy_id = i;
2814 if (mii_link_ok(&mii)) {
2815 /* found PHY with active link */
2816 if (netif_msg_link(lp))
2817 printk(KERN_INFO
2818 "%s: Using PHY number %d.\n",
2819 dev->name, i);
2820
2821 /* isolate inactive phy */
2822 bmcr =
2823 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2824 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2825 bmcr | BMCR_ISOLATE);
2826
2827 /* de-isolate new phy */
2828 bmcr = mdio_read(dev, i, MII_BMCR);
2829 mdio_write(dev, i, MII_BMCR,
2830 bmcr & ~BMCR_ISOLATE);
2831
2832 /* set new phy address */
2833 lp->mii_if.phy_id = i;
2834 return 1;
2835 }
2836 }
ac62ef04 2837 }
4a5e8e29 2838 return 0;
ac62ef04
DF		 2839}
2840
2841/*
2842 * Show the status of the media. Similar to mii_check_media however it
2843 * correctly shows the link speed for all (tested) pcnet32 variants.
2844 * Devices with no mii just report link state without speed.
2845 *
2846 * Caller is assumed to hold and release the lp->lock.
2847 */
2848
2849static void pcnet32_check_media(struct net_device *dev, int verbose)
2850{
1e56a4b4 2851 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2852 int curr_link;
2853 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2854 u32 bcr9;
2855
ac62ef04 2856 if (lp->mii) {
4a5e8e29 2857 curr_link = mii_link_ok(&lp->mii_if);
ac62ef04 2858 } else {
4a5e8e29
JG		 2859 ulong ioaddr = dev->base_addr; /* card base I/O address */
2860 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2861 }
2862 if (!curr_link) {
2863 if (prev_link || verbose) {
2864 netif_carrier_off(dev);
2865 if (netif_msg_link(lp))
2866 printk(KERN_INFO "%s: link down\n", dev->name);
2867 }
2868 if (lp->phycount > 1) {
2869 curr_link = pcnet32_check_otherphy(dev);
2870 prev_link = 0;
2871 }
2872 } else if (verbose || !prev_link) {
2873 netif_carrier_on(dev);
2874 if (lp->mii) {
2875 if (netif_msg_link(lp)) {
2876 struct ethtool_cmd ecmd;
2877 mii_ethtool_gset(&lp->mii_if, &ecmd);
2878 printk(KERN_INFO
2879 "%s: link up, %sMbps, %s-duplex\n",
2880 dev->name,
2881 (ecmd.speed == SPEED_100) ? "100" : "10",
2882 (ecmd.duplex ==
2883 DUPLEX_FULL) ? "full" : "half");
2884 }
2885 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2886 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2887 if (lp->mii_if.full_duplex)
2888 bcr9 |= (1 << 0);
2889 else
2890 bcr9 &= ~(1 << 0);
2891 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2892 }
2893 } else {
2894 if (netif_msg_link(lp))
2895 printk(KERN_INFO "%s: link up\n", dev->name);
2896 }
ac62ef04 2897 }
ac62ef04
DF		 2898}
2899
2900/*
2901 * Check for loss of link and link establishment.
2902 * Can not use mii_check_media because it does nothing if mode is forced.
2903 */
2904
1da177e4
LT		 2905static void pcnet32_watchdog(struct net_device *dev)
2906{
1e56a4b4 2907 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2908 unsigned long flags;
1da177e4 2909
4a5e8e29
JG		 2910 /* Print the link status if it has changed */
2911 spin_lock_irqsave(&lp->lock, flags);
2912 pcnet32_check_media(dev, 0);
2913 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2914
4a5e8e29 2915 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1da177e4
LT		 2916}
2917
917270c6
DF		 2918static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2919{
2920 struct net_device *dev = pci_get_drvdata(pdev);
2921
2922 if (netif_running(dev)) {
2923 netif_device_detach(dev);
2924 pcnet32_close(dev);
2925 }
2926 pci_save_state(pdev);
2927 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2928 return 0;
2929}
2930
2931static int pcnet32_pm_resume(struct pci_dev *pdev)
2932{
2933 struct net_device *dev = pci_get_drvdata(pdev);
2934
2935 pci_set_power_state(pdev, PCI_D0);
2936 pci_restore_state(pdev);
2937
2938 if (netif_running(dev)) {
2939 pcnet32_open(dev);
2940 netif_device_attach(dev);
2941 }
2942 return 0;
2943}
2944
1da177e4
LT		 2945static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2946{
4a5e8e29
JG		 2947 struct net_device *dev = pci_get_drvdata(pdev);
2948
2949 if (dev) {
1e56a4b4 2950 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2951
2952 unregister_netdev(dev);
2953 pcnet32_free_ring(dev);
2954 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
7d2e3cb7 2955 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 2956 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 2957 free_netdev(dev);
2958 pci_disable_device(pdev);
2959 pci_set_drvdata(pdev, NULL);
2960 }
1da177e4
LT		 2961}
2962
2963static struct pci_driver pcnet32_driver = {
4a5e8e29
JG		 2964 .name = DRV_NAME,
2965 .probe = pcnet32_probe_pci,
2966 .remove = __devexit_p(pcnet32_remove_one),
2967 .id_table = pcnet32_pci_tbl,
917270c6
DF		 2968 .suspend = pcnet32_pm_suspend,
2969 .resume = pcnet32_pm_resume,
1da177e4
LT		 2970};
2971
2972/* An additional parameter that may be passed in... */
2973static int debug = -1;
2974static int tx_start_pt = -1;
2975static int pcnet32_have_pci;
2976
2977module_param(debug, int, 0);
2978MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2979module_param(max_interrupt_work, int, 0);
4a5e8e29
JG		 2980MODULE_PARM_DESC(max_interrupt_work,
2981 DRV_NAME " maximum events handled per interrupt");
1da177e4 2982module_param(rx_copybreak, int, 0);
4a5e8e29
JG		 2983MODULE_PARM_DESC(rx_copybreak,
2984 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 2985module_param(tx_start_pt, int, 0);
2986MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2987module_param(pcnet32vlb, int, 0);
2988MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2989module_param_array(options, int, NULL, 0);
2990MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2991module_param_array(full_duplex, int, NULL, 0);
2992MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2993/* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2994module_param_array(homepna, int, NULL, 0);
4a5e8e29
JG		 2995MODULE_PARM_DESC(homepna,
2996 DRV_NAME
2997 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
1da177e4
LT		 2998
2999MODULE_AUTHOR("Thomas Bogendoerfer");
3000MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3001MODULE_LICENSE("GPL");
3002
3003#define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3004
3005static int __init pcnet32_init_module(void)
3006{
4a5e8e29 3007 printk(KERN_INFO "%s", version);
1da177e4 3008
4a5e8e29 3009 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
1da177e4 3010
4a5e8e29
JG		 3011 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3012 tx_start = tx_start_pt;
1da177e4 3013
4a5e8e29 3014 /* find the PCI devices */
29917620 3015 if (!pci_register_driver(&pcnet32_driver))
4a5e8e29 3016 pcnet32_have_pci = 1;
1da177e4 3017
4a5e8e29
JG		 3018 /* should we find any remaining VLbus devices ? */
3019 if (pcnet32vlb)
dcaf9769 3020 pcnet32_probe_vlbus(pcnet32_portlist);
1da177e4 3021
4a5e8e29
JG		 3022 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3023 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
1da177e4 3024
4a5e8e29 3025 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
1da177e4
LT		 3026}
3027
3028static void __exit pcnet32_cleanup_module(void)
3029{
4a5e8e29
JG		 3030 struct net_device *next_dev;
3031
3032 while (pcnet32_dev) {
1e56a4b4 3033 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
4a5e8e29
JG		 3034 next_dev = lp->next;
3035 unregister_netdev(pcnet32_dev);
3036 pcnet32_free_ring(pcnet32_dev);
3037 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
7d2e3cb7 3038 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 3039 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 3040 free_netdev(pcnet32_dev);
3041 pcnet32_dev = next_dev;
3042 }
1da177e4 3043
4a5e8e29
JG		 3044 if (pcnet32_have_pci)
3045 pci_unregister_driver(&pcnet32_driver);
1da177e4
LT		 3046}
3047
3048module_init(pcnet32_init_module);
3049module_exit(pcnet32_cleanup_module);
3050
3051/*
3052 * Local variables:
3053 * c-indent-level: 4
3054 * tab-width: 8
3055 * End:
3056 */
Clone of davem's net-next-2.6 tree