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Merge branch 'ebt_config_compat_v4' of git://git.breakpoint.cc/fw/nf-next-2.6
[net-next-2.6.git] / drivers / net / pcmcia / nmclan_cs.c
CommitLineData
1da177e4
LT		 1/* ----------------------------------------------------------------------------
2Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
4
5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
6 Access Controller for Ethernet (MACE). It is essentially the Am2150
7 PCMCIA Ethernet card contained in the Am2150 Demo Kit.
8
9Written by Roger C. Pao <rpao@paonet.org>
10 Copyright 1995 Roger C. Pao
11 Linux 2.5 cleanups Copyright Red Hat 2003
12
13 This software may be used and distributed according to the terms of
14 the GNU General Public License.
15
16Ported to Linux 1.3.* network driver environment by
17 Matti Aarnio <mea@utu.fi>
18
19References
20
21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
22 Am79C940 (MACE) Data Sheet, 1994
23 Am79C90 (C-LANCE) Data Sheet, 1994
24 Linux PCMCIA Programmer's Guide v1.17
25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
26
27 Eric Mears, New Media Corporation
28 Tom Pollard, New Media Corporation
29 Dean Siasoyco, New Media Corporation
30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
31 Donald Becker <becker@scyld.com>
32 David Hinds <dahinds@users.sourceforge.net>
33
34 The Linux client driver is based on the 3c589_cs.c client driver by
35 David Hinds.
36
37 The Linux network driver outline is based on the 3c589_cs.c driver,
38 the 8390.c driver, and the example skeleton.c kernel code, which are
39 by Donald Becker.
40
41 The Am2150 network driver hardware interface code is based on the
42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
43
44 Special thanks for testing and help in debugging this driver goes
45 to Ken Lesniak.
46
47-------------------------------------------------------------------------------
48Driver Notes and Issues
49-------------------------------------------------------------------------------
50
511. Developed on a Dell 320SLi
52 PCMCIA Card Services 2.6.2
53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
54
552. rc.pcmcia may require loading pcmcia_core with io_speed=300:
56 'insmod pcmcia_core.o io_speed=300'.
57 This will avoid problems with fast systems which causes rx_framecnt
58 to return random values.
59
603. If hot extraction does not work for you, use 'ifconfig eth0 down'
61 before extraction.
62
634. There is a bad slow-down problem in this driver.
64
655. Future: Multicast processing. In the meantime, do _not_ compile your
66 kernel with multicast ip enabled.
67
68-------------------------------------------------------------------------------
69History
70-------------------------------------------------------------------------------
71Log: nmclan_cs.c,v
113aa838 72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk>
1da177e4
LT		 73 * Fixed hang on card eject as we probe it
74 * Cleaned up to use new style locking.
75 *
76 * Revision 0.16 1995/07/01 06:42:17 rpao
77 * Bug fix: nmclan_reset() called CardServices incorrectly.
78 *
79 * Revision 0.15 1995/05/24 08:09:47 rpao
80 * Re-implement MULTI_TX dev->tbusy handling.
81 *
82 * Revision 0.14 1995/05/23 03:19:30 rpao
83 * Added, in nmclan_config(), "tuple.Attributes = 0;".
84 * Modified MACE ID check to ignore chip revision level.
85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
86 *
87 * Revision 0.13 1995/05/18 05:56:34 rpao
88 * Statistics changes.
89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup.
91 *
92 * Revision 0.12 1995/05/14 00:12:23 rpao
93 * Statistics overhaul.
94 *
95
9695/05/13 rpao V0.10a
97 Bug fix: MACE statistics counters used wrong I/O ports.
98 Bug fix: mace_interrupt() needed to allow statistics to be
99 processed without RX or TX interrupts pending.
10095/05/11 rpao V0.10
101 Multiple transmit request processing.
102 Modified statistics to use MACE counters where possible.
10395/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
104 *Released
10595/05/10 rpao V0.08
106 Bug fix: Make all non-exported functions private by using
107 static keyword.
108 Bug fix: Test IntrCnt _before_ reading MACE_IR.
10995/05/10 rpao V0.07 Statistics.
11095/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
111
112---------------------------------------------------------------------------- */
113
114#define DRV_NAME "nmclan_cs"
115#define DRV_VERSION "0.16"
116
117
118/* ----------------------------------------------------------------------------
119Conditional Compilation Options
120---------------------------------------------------------------------------- */
121
122#define MULTI_TX 0
123#define RESET_ON_TIMEOUT 1
124#define TX_INTERRUPTABLE 1
125#define RESET_XILINX 0
126
127/* ----------------------------------------------------------------------------
128Include Files
129---------------------------------------------------------------------------- */
130
131#include <linux/module.h>
132#include <linux/kernel.h>
133#include <linux/init.h>
134#include <linux/ptrace.h>
135#include <linux/slab.h>
136#include <linux/string.h>
137#include <linux/timer.h>
138#include <linux/interrupt.h>
139#include <linux/in.h>
140#include <linux/delay.h>
141#include <linux/ethtool.h>
142#include <linux/netdevice.h>
143#include <linux/etherdevice.h>
144#include <linux/skbuff.h>
145#include <linux/if_arp.h>
146#include <linux/ioport.h>
147#include <linux/bitops.h>
148
1da177e4
LT		 149#include <pcmcia/cs_types.h>
150#include <pcmcia/cs.h>
151#include <pcmcia/cisreg.h>
152#include <pcmcia/cistpl.h>
153#include <pcmcia/ds.h>
154
155#include <asm/uaccess.h>
156#include <asm/io.h>
157#include <asm/system.h>
158
159/* ----------------------------------------------------------------------------
160Defines
161---------------------------------------------------------------------------- */
162
163#define ETHER_ADDR_LEN ETH_ALEN
164 /* 6 bytes in an Ethernet Address */
165#define MACE_LADRF_LEN 8
166 /* 8 bytes in Logical Address Filter */
167
168/* Loop Control Defines */
169#define MACE_MAX_IR_ITERATIONS 10
170#define MACE_MAX_RX_ITERATIONS 12
171 /*
172 TBD: Dean brought this up, and I assumed the hardware would
173 handle it:
174
175 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
176 non-zero when the isr exits. We may not get another interrupt
177 to process the remaining packets for some time.
178 */
179
180/*
181The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
182which manages the interface between the MACE and the PCMCIA bus. It
183also includes buffer management for the 32K x 8 SRAM to control up to
184four transmit and 12 receive frames at a time.
185*/
186#define AM2150_MAX_TX_FRAMES 4
187#define AM2150_MAX_RX_FRAMES 12
188
189/* Am2150 Ethernet Card I/O Mapping */
190#define AM2150_RCV 0x00
191#define AM2150_XMT 0x04
192#define AM2150_XMT_SKIP 0x09
193#define AM2150_RCV_NEXT 0x0A
194#define AM2150_RCV_FRAME_COUNT 0x0B
195#define AM2150_MACE_BANK 0x0C
196#define AM2150_MACE_BASE 0x10
197
198/* MACE Registers */
199#define MACE_RCVFIFO 0
200#define MACE_XMTFIFO 1
201#define MACE_XMTFC 2
202#define MACE_XMTFS 3
203#define MACE_XMTRC 4
204#define MACE_RCVFC 5
205#define MACE_RCVFS 6
206#define MACE_FIFOFC 7
207#define MACE_IR 8
208#define MACE_IMR 9
209#define MACE_PR 10
210#define MACE_BIUCC 11
211#define MACE_FIFOCC 12
212#define MACE_MACCC 13
213#define MACE_PLSCC 14
214#define MACE_PHYCC 15
215#define MACE_CHIPIDL 16
216#define MACE_CHIPIDH 17
217#define MACE_IAC 18
218/* Reserved */
219#define MACE_LADRF 20
220#define MACE_PADR 21
221/* Reserved */
222/* Reserved */
223#define MACE_MPC 24
224/* Reserved */
225#define MACE_RNTPC 26
226#define MACE_RCVCC 27
227/* Reserved */
228#define MACE_UTR 29
229#define MACE_RTR1 30
230#define MACE_RTR2 31
231
232/* MACE Bit Masks */
233#define MACE_XMTRC_EXDEF 0x80
234#define MACE_XMTRC_XMTRC 0x0F
235
236#define MACE_XMTFS_XMTSV 0x80
237#define MACE_XMTFS_UFLO 0x40
238#define MACE_XMTFS_LCOL 0x20
239#define MACE_XMTFS_MORE 0x10
240#define MACE_XMTFS_ONE 0x08
241#define MACE_XMTFS_DEFER 0x04
242#define MACE_XMTFS_LCAR 0x02
243#define MACE_XMTFS_RTRY 0x01
244
245#define MACE_RCVFS_RCVSTS 0xF000
246#define MACE_RCVFS_OFLO 0x8000
247#define MACE_RCVFS_CLSN 0x4000
248#define MACE_RCVFS_FRAM 0x2000
249#define MACE_RCVFS_FCS 0x1000
250
251#define MACE_FIFOFC_RCVFC 0xF0
252#define MACE_FIFOFC_XMTFC 0x0F
253
254#define MACE_IR_JAB 0x80
255#define MACE_IR_BABL 0x40
256#define MACE_IR_CERR 0x20
257#define MACE_IR_RCVCCO 0x10
258#define MACE_IR_RNTPCO 0x08
259#define MACE_IR_MPCO 0x04
260#define MACE_IR_RCVINT 0x02
261#define MACE_IR_XMTINT 0x01
262
263#define MACE_MACCC_PROM 0x80
264#define MACE_MACCC_DXMT2PD 0x40
265#define MACE_MACCC_EMBA 0x20
266#define MACE_MACCC_RESERVED 0x10
267#define MACE_MACCC_DRCVPA 0x08
268#define MACE_MACCC_DRCVBC 0x04
269#define MACE_MACCC_ENXMT 0x02
270#define MACE_MACCC_ENRCV 0x01
271
272#define MACE_PHYCC_LNKFL 0x80
273#define MACE_PHYCC_DLNKTST 0x40
274#define MACE_PHYCC_REVPOL 0x20
275#define MACE_PHYCC_DAPC 0x10
276#define MACE_PHYCC_LRT 0x08
277#define MACE_PHYCC_ASEL 0x04
278#define MACE_PHYCC_RWAKE 0x02
279#define MACE_PHYCC_AWAKE 0x01
280
281#define MACE_IAC_ADDRCHG 0x80
282#define MACE_IAC_PHYADDR 0x04
283#define MACE_IAC_LOGADDR 0x02
284
285#define MACE_UTR_RTRE 0x80
286#define MACE_UTR_RTRD 0x40
287#define MACE_UTR_RPA 0x20
288#define MACE_UTR_FCOLL 0x10
289#define MACE_UTR_RCVFCSE 0x08
290#define MACE_UTR_LOOP_INCL_MENDEC 0x06
291#define MACE_UTR_LOOP_NO_MENDEC 0x04
292#define MACE_UTR_LOOP_EXTERNAL 0x02
293#define MACE_UTR_LOOP_NONE 0x00
294#define MACE_UTR_RESERVED 0x01
295
296/* Switch MACE register bank (only 0 and 1 are valid) */
297#define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
298
299#define MACE_IMR_DEFAULT \
300 (0xFF - \
301 ( \
302 MACE_IR_CERR | \
303 MACE_IR_RCVCCO | \
304 MACE_IR_RNTPCO | \
305 MACE_IR_MPCO | \
306 MACE_IR_RCVINT | \
307 MACE_IR_XMTINT \
308 ) \
309 )
310#undef MACE_IMR_DEFAULT
311#define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
312
313#define TX_TIMEOUT ((400*HZ)/1000)
314
315/* ----------------------------------------------------------------------------
316Type Definitions
317---------------------------------------------------------------------------- */
318
319typedef struct _mace_statistics {
320 /* MACE_XMTFS */
321 int xmtsv;
322 int uflo;
323 int lcol;
324 int more;
325 int one;
326 int defer;
327 int lcar;
328 int rtry;
329
330 /* MACE_XMTRC */
331 int exdef;
332 int xmtrc;
333
334 /* RFS1--Receive Status (RCVSTS) */
335 int oflo;
336 int clsn;
337 int fram;
338 int fcs;
339
340 /* RFS2--Runt Packet Count (RNTPC) */
341 int rfs_rntpc;
342
343 /* RFS3--Receive Collision Count (RCVCC) */
344 int rfs_rcvcc;
345
346 /* MACE_IR */
347 int jab;
348 int babl;
349 int cerr;
350 int rcvcco;
351 int rntpco;
352 int mpco;
353
354 /* MACE_MPC */
355 int mpc;
356
357 /* MACE_RNTPC */
358 int rntpc;
359
360 /* MACE_RCVCC */
361 int rcvcc;
362} mace_statistics;
363
364typedef struct _mace_private {
fd238232 365 struct pcmcia_device *p_dev;
1da177e4
LT		 366 dev_node_t node;
367 struct net_device_stats linux_stats; /* Linux statistics counters */
368 mace_statistics mace_stats; /* MACE chip statistics counters */
369
370 /* restore_multicast_list() state variables */
371 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
372 int multicast_num_addrs;
373
374 char tx_free_frames; /* Number of free transmit frame buffers */
375 char tx_irq_disabled; /* MACE TX interrupt disabled */
376
377 spinlock_t bank_lock; /* Must be held if you step off bank 0 */
378} mace_private;
379
380/* ----------------------------------------------------------------------------
381Private Global Variables
382---------------------------------------------------------------------------- */
383
f71e1309 384static const char *if_names[]={
1da177e4
LT		 385 "Auto", "10baseT", "BNC",
386};
387
388/* ----------------------------------------------------------------------------
389Parameters
390 These are the parameters that can be set during loading with
391 'insmod'.
392---------------------------------------------------------------------------- */
393
394MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
395MODULE_LICENSE("GPL");
396
397#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
398
399/* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
400INT_MODULE_PARM(if_port, 0);
401
1da177e4
LT		 402
403/* ----------------------------------------------------------------------------
404Function Prototypes
405---------------------------------------------------------------------------- */
406
15b99ac1 407static int nmclan_config(struct pcmcia_device *link);
fba395ee 408static void nmclan_release(struct pcmcia_device *link);
1da177e4
LT		 409
410static void nmclan_reset(struct net_device *dev);
411static int mace_config(struct net_device *dev, struct ifmap *map);
412static int mace_open(struct net_device *dev);
413static int mace_close(struct net_device *dev);
dbf02fae
SH		 414static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
415 struct net_device *dev);
1da177e4 416static void mace_tx_timeout(struct net_device *dev);
7d12e780 417static irqreturn_t mace_interrupt(int irq, void *dev_id);
1da177e4
LT		 418static struct net_device_stats *mace_get_stats(struct net_device *dev);
419static int mace_rx(struct net_device *dev, unsigned char RxCnt);
420static void restore_multicast_list(struct net_device *dev);
421static void set_multicast_list(struct net_device *dev);
7282d491 422static const struct ethtool_ops netdev_ethtool_ops;
1da177e4
LT		 423
424
cc3b4866 425static void nmclan_detach(struct pcmcia_device *p_dev);
1da177e4 426
28b1801d
SH		 427static const struct net_device_ops mace_netdev_ops = {
428 .ndo_open = mace_open,
429 .ndo_stop = mace_close,
430 .ndo_start_xmit = mace_start_xmit,
431 .ndo_tx_timeout = mace_tx_timeout,
432 .ndo_set_config = mace_config,
433 .ndo_get_stats = mace_get_stats,
434 .ndo_set_multicast_list = set_multicast_list,
435 .ndo_change_mtu = eth_change_mtu,
436 .ndo_set_mac_address = eth_mac_addr,
437 .ndo_validate_addr = eth_validate_addr,
438};
439
1da177e4
LT		 440/* ----------------------------------------------------------------------------
441nmclan_attach
442 Creates an "instance" of the driver, allocating local data
443 structures for one device. The device is registered with Card
444 Services.
445---------------------------------------------------------------------------- */
446
15b99ac1 447static int nmclan_probe(struct pcmcia_device *link)
1da177e4
LT		 448{
449 mace_private *lp;
1da177e4 450 struct net_device *dev;
1da177e4 451
dd0fab5b 452 dev_dbg(&link->dev, "nmclan_attach()\n");
1da177e4
LT		 453
454 /* Create new ethernet device */
455 dev = alloc_etherdev(sizeof(mace_private));
456 if (!dev)
f8cfa618 457 return -ENOMEM;
1da177e4 458 lp = netdev_priv(dev);
fba395ee 459 lp->p_dev = link;
1da177e4
LT		 460 link->priv = dev;
461
462 spin_lock_init(&lp->bank_lock);
463 link->io.NumPorts1 = 32;
464 link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
465 link->io.IOAddrLines = 5;
5fa9167a 466 link->irq.Attributes = IRQ_TYPE_EXCLUSIVE;
dddcb445 467 link->irq.Handler = mace_interrupt;
1da177e4 468 link->conf.Attributes = CONF_ENABLE_IRQ;
1da177e4
LT		 469 link->conf.IntType = INT_MEMORY_AND_IO;
470 link->conf.ConfigIndex = 1;
471 link->conf.Present = PRESENT_OPTION;
472
473 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
474
28b1801d 475 dev->netdev_ops = &mace_netdev_ops;
1da177e4 476 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
1da177e4 477 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 478
15b99ac1 479 return nmclan_config(link);
1da177e4
LT		 480} /* nmclan_attach */
481
482/* ----------------------------------------------------------------------------
483nmclan_detach
484 This deletes a driver "instance". The device is de-registered
485 with Card Services. If it has been released, all local data
486 structures are freed. Otherwise, the structures will be freed
487 when the device is released.
488---------------------------------------------------------------------------- */
489
fba395ee 490static void nmclan_detach(struct pcmcia_device *link)
1da177e4
LT		 491{
492 struct net_device *dev = link->priv;
1da177e4 493
dd0fab5b 494 dev_dbg(&link->dev, "nmclan_detach\n");
1da177e4 495
fd238232 496 if (link->dev_node)
1da177e4
LT		 497 unregister_netdev(dev);
498
e2d40963 499 nmclan_release(link);
1da177e4 500
1da177e4
LT		 501 free_netdev(dev);
502} /* nmclan_detach */
503
504/* ----------------------------------------------------------------------------
505mace_read
506 Reads a MACE register. This is bank independent; however, the
507 caller must ensure that this call is not interruptable. We are
508 assuming that during normal operation, the MACE is always in
509 bank 0.
510---------------------------------------------------------------------------- */
906da809 511static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
1da177e4
LT		 512{
513 int data = 0xFF;
514 unsigned long flags;
515
516 switch (reg >> 4) {
517 case 0: /* register 0-15 */
518 data = inb(ioaddr + AM2150_MACE_BASE + reg);
519 break;
520 case 1: /* register 16-31 */
521 spin_lock_irqsave(&lp->bank_lock, flags);
522 MACEBANK(1);
523 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
524 MACEBANK(0);
525 spin_unlock_irqrestore(&lp->bank_lock, flags);
526 break;
527 }
528 return (data & 0xFF);
529} /* mace_read */
530
531/* ----------------------------------------------------------------------------
532mace_write
533 Writes to a MACE register. This is bank independent; however,
534 the caller must ensure that this call is not interruptable. We
535 are assuming that during normal operation, the MACE is always in
536 bank 0.
537---------------------------------------------------------------------------- */
906da809
OJ		 538static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
539 int data)
1da177e4
LT		 540{
541 unsigned long flags;
542
543 switch (reg >> 4) {
544 case 0: /* register 0-15 */
545 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
546 break;
547 case 1: /* register 16-31 */
548 spin_lock_irqsave(&lp->bank_lock, flags);
549 MACEBANK(1);
550 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
551 MACEBANK(0);
552 spin_unlock_irqrestore(&lp->bank_lock, flags);
553 break;
554 }
555} /* mace_write */
556
557/* ----------------------------------------------------------------------------
558mace_init
559 Resets the MACE chip.
560---------------------------------------------------------------------------- */
906da809 561static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr)
1da177e4
LT		 562{
563 int i;
564 int ct = 0;
565
566 /* MACE Software reset */
567 mace_write(lp, ioaddr, MACE_BIUCC, 1);
568 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
569 /* Wait for reset bit to be cleared automatically after <= 200ns */;
570 if(++ct > 500)
571 {
572 printk(KERN_ERR "mace: reset failed, card removed ?\n");
573 return -1;
574 }
575 udelay(1);
576 }
577 mace_write(lp, ioaddr, MACE_BIUCC, 0);
578
579 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
580 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
581
582 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
583 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
584
585 /*
586 * Bit 2-1 PORTSEL[1-0] Port Select.
587 * 00 AUI/10Base-2
588 * 01 10Base-T
589 * 10 DAI Port (reserved in Am2150)
590 * 11 GPSI
591 * For this card, only the first two are valid.
592 * So, PLSCC should be set to
593 * 0x00 for 10Base-2
594 * 0x02 for 10Base-T
595 * Or just set ASEL in PHYCC below!
596 */
597 switch (if_port) {
598 case 1:
599 mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
600 break;
601 case 2:
602 mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
603 break;
604 default:
605 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
606 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
607 and the MACE device will automatically select the operating media
608 interface port. */
609 break;
610 }
611
612 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
613 /* Poll ADDRCHG bit */
614 ct = 0;
615 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
616 {
617 if(++ ct > 500)
618 {
619 printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n");
620 return -1;
621 }
622 }
623 /* Set PADR register */
624 for (i = 0; i < ETHER_ADDR_LEN; i++)
625 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
626
627 /* MAC Configuration Control Register should be written last */
628 /* Let set_multicast_list set this. */
629 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
630 mace_write(lp, ioaddr, MACE_MACCC, 0x00);
631 return 0;
632} /* mace_init */
633
634/* ----------------------------------------------------------------------------
635nmclan_config
636 This routine is scheduled to run after a CARD_INSERTION event
637 is received, to configure the PCMCIA socket, and to make the
638 ethernet device available to the system.
639---------------------------------------------------------------------------- */
640
15b99ac1 641static int nmclan_config(struct pcmcia_device *link)
1da177e4 642{
1da177e4
LT		 643 struct net_device *dev = link->priv;
644 mace_private *lp = netdev_priv(dev);
dddfbd82
DB		 645 u8 *buf;
646 size_t len;
dd0fab5b 647 int i, ret;
906da809 648 unsigned int ioaddr;
1da177e4 649
dd0fab5b
DB		 650 dev_dbg(&link->dev, "nmclan_config\n");
651
652 ret = pcmcia_request_io(link, &link->io);
653 if (ret)
654 goto failed;
655 ret = pcmcia_request_irq(link, &link->irq);
656 if (ret)
657 goto failed;
658 ret = pcmcia_request_configuration(link, &link->conf);
659 if (ret)
660 goto failed;
1da177e4 661
1da177e4
LT		 662 dev->irq = link->irq.AssignedIRQ;
663 dev->base_addr = link->io.BasePort1;
664
665 ioaddr = dev->base_addr;
666
667 /* Read the ethernet address from the CIS. */
dddfbd82
DB		 668 len = pcmcia_get_tuple(link, 0x80, &buf);
669 if (!buf || len < ETHER_ADDR_LEN) {
670 kfree(buf);
671 goto failed;
672 }
673 memcpy(dev->dev_addr, buf, ETHER_ADDR_LEN);
674 kfree(buf);
1da177e4
LT		 675
676 /* Verify configuration by reading the MACE ID. */
677 {
678 char sig[2];
679
680 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
681 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
682 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
dd0fab5b 683 dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n",
1da177e4
LT		 684 sig[0], sig[1]);
685 } else {
686 printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"
687 " be 0x40 0x?9\n", sig[0], sig[1]);
15b99ac1 688 return -ENODEV;
1da177e4
LT		 689 }
690 }
691
692 if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
693 goto failed;
694
695 /* The if_port symbol can be set when the module is loaded */
696 if (if_port <= 2)
697 dev->if_port = if_port;
698 else
699 printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");
700
fd238232 701 link->dev_node = &lp->node;
dd2e5a15 702 SET_NETDEV_DEV(dev, &link->dev);
1da177e4
LT		 703
704 i = register_netdev(dev);
705 if (i != 0) {
706 printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");
fd238232 707 link->dev_node = NULL;
1da177e4
LT		 708 goto failed;
709 }
710
711 strcpy(lp->node.dev_name, dev->name);
712
0795af57 713 printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port,"
e174961c 714 " hw_addr %pM\n",
0795af57 715 dev->name, dev->base_addr, dev->irq, if_names[dev->if_port],
e174961c 716 dev->dev_addr);
15b99ac1 717 return 0;
1da177e4 718
1da177e4 719failed:
15b99ac1
DB		 720 nmclan_release(link);
721 return -ENODEV;
1da177e4
LT		 722} /* nmclan_config */
723
724/* ----------------------------------------------------------------------------
725nmclan_release
726 After a card is removed, nmclan_release() will unregister the
727 net device, and release the PCMCIA configuration. If the device
728 is still open, this will be postponed until it is closed.
729---------------------------------------------------------------------------- */
fba395ee 730static void nmclan_release(struct pcmcia_device *link)
1da177e4 731{
dd0fab5b 732 dev_dbg(&link->dev, "nmclan_release\n");
fba395ee 733 pcmcia_disable_device(link);
1da177e4
LT		 734}
735
fba395ee 736static int nmclan_suspend(struct pcmcia_device *link)
98e4c28b 737{
98e4c28b
DB		 738 struct net_device *dev = link->priv;
739
e2d40963 740 if (link->open)
8661bb5b 741 netif_device_detach(dev);
98e4c28b
DB		 742
743 return 0;
744}
745
fba395ee 746static int nmclan_resume(struct pcmcia_device *link)
98e4c28b 747{
98e4c28b
DB		 748 struct net_device *dev = link->priv;
749
e2d40963 750 if (link->open) {
8661bb5b
DB		 751 nmclan_reset(dev);
752 netif_device_attach(dev);
98e4c28b
DB		 753 }
754
755 return 0;
756}
757
1da177e4
LT		 758
759/* ----------------------------------------------------------------------------
760nmclan_reset
761 Reset and restore all of the Xilinx and MACE registers.
762---------------------------------------------------------------------------- */
763static void nmclan_reset(struct net_device *dev)
764{
765 mace_private *lp = netdev_priv(dev);
766
767#if RESET_XILINX
fba395ee 768 struct pcmcia_device *link = &lp->link;
1da177e4
LT		 769 conf_reg_t reg;
770 u_long OrigCorValue;
771
772 /* Save original COR value */
773 reg.Function = 0;
774 reg.Action = CS_READ;
775 reg.Offset = CISREG_COR;
776 reg.Value = 0;
fba395ee 777 pcmcia_access_configuration_register(link, &reg);
1da177e4
LT		 778 OrigCorValue = reg.Value;
779
780 /* Reset Xilinx */
781 reg.Action = CS_WRITE;
782 reg.Offset = CISREG_COR;
dd0fab5b 783 dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",
1da177e4
LT		 784 OrigCorValue);
785 reg.Value = COR_SOFT_RESET;
fba395ee 786 pcmcia_access_configuration_register(link, &reg);
1da177e4
LT		 787 /* Need to wait for 20 ms for PCMCIA to finish reset. */
788
789 /* Restore original COR configuration index */
790 reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);
fba395ee 791 pcmcia_access_configuration_register(link, &reg);
1da177e4
LT		 792 /* Xilinx is now completely reset along with the MACE chip. */
793 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
794
795#endif /* #if RESET_XILINX */
796
797 /* Xilinx is now completely reset along with the MACE chip. */
798 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
799
800 /* Reinitialize the MACE chip for operation. */
801 mace_init(lp, dev->base_addr, dev->dev_addr);
802 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
803
804 /* Restore the multicast list and enable TX and RX. */
805 restore_multicast_list(dev);
806} /* nmclan_reset */
807
808/* ----------------------------------------------------------------------------
809mace_config
810 [Someone tell me what this is supposed to do? Is if_port a defined
811 standard? If so, there should be defines to indicate 1=10Base-T,
812 2=10Base-2, etc. including limited automatic detection.]
813---------------------------------------------------------------------------- */
814static int mace_config(struct net_device *dev, struct ifmap *map)
815{
816 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
817 if (map->port <= 2) {
818 dev->if_port = map->port;
819 printk(KERN_INFO "%s: switched to %s port\n", dev->name,
820 if_names[dev->if_port]);
821 } else
822 return -EINVAL;
823 }
824 return 0;
825} /* mace_config */
826
827/* ----------------------------------------------------------------------------
828mace_open
829 Open device driver.
830---------------------------------------------------------------------------- */
831static int mace_open(struct net_device *dev)
832{
906da809 833 unsigned int ioaddr = dev->base_addr;
1da177e4 834 mace_private *lp = netdev_priv(dev);
fba395ee 835 struct pcmcia_device *link = lp->p_dev;
1da177e4 836
9940ec36 837 if (!pcmcia_dev_present(link))
1da177e4
LT		 838 return -ENODEV;
839
840 link->open++;
841
842 MACEBANK(0);
843
844 netif_start_queue(dev);
845 nmclan_reset(dev);
846
847 return 0; /* Always succeed */
848} /* mace_open */
849
850/* ----------------------------------------------------------------------------
851mace_close
852 Closes device driver.
853---------------------------------------------------------------------------- */
854static int mace_close(struct net_device *dev)
855{
906da809 856 unsigned int ioaddr = dev->base_addr;
1da177e4 857 mace_private *lp = netdev_priv(dev);
fba395ee 858 struct pcmcia_device *link = lp->p_dev;
1da177e4 859
dd0fab5b 860 dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name);
1da177e4
LT		 861
862 /* Mask off all interrupts from the MACE chip. */
863 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
864
865 link->open--;
866 netif_stop_queue(dev);
867
868 return 0;
869} /* mace_close */
870
871static void netdev_get_drvinfo(struct net_device *dev,
872 struct ethtool_drvinfo *info)
873{
874 strcpy(info->driver, DRV_NAME);
875 strcpy(info->version, DRV_VERSION);
876 sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
877}
878
7282d491 879static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4 880 .get_drvinfo = netdev_get_drvinfo,
1da177e4
LT		 881};
882
883/* ----------------------------------------------------------------------------
884mace_start_xmit
885 This routine begins the packet transmit function. When completed,
886 it will generate a transmit interrupt.
887
888 According to /usr/src/linux/net/inet/dev.c, if _start_xmit
889 returns 0, the "packet is now solely the responsibility of the
890 driver." If _start_xmit returns non-zero, the "transmission
891 failed, put skb back into a list."
892---------------------------------------------------------------------------- */
893
894static void mace_tx_timeout(struct net_device *dev)
895{
896 mace_private *lp = netdev_priv(dev);
fba395ee 897 struct pcmcia_device *link = lp->p_dev;
1da177e4
LT		 898
899 printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
900#if RESET_ON_TIMEOUT
901 printk("resetting card\n");
994917f8 902 pcmcia_reset_card(link->socket);
1da177e4
LT		 903#else /* #if RESET_ON_TIMEOUT */
904 printk("NOT resetting card\n");
905#endif /* #if RESET_ON_TIMEOUT */
906 dev->trans_start = jiffies;
907 netif_wake_queue(dev);
908}
909
dbf02fae
SH		 910static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
911 struct net_device *dev)
1da177e4
LT		 912{
913 mace_private *lp = netdev_priv(dev);
906da809 914 unsigned int ioaddr = dev->base_addr;
1da177e4
LT		 915
916 netif_stop_queue(dev);
917
dd0fab5b 918 pr_debug("%s: mace_start_xmit(length = %ld) called.\n",
1da177e4
LT		 919 dev->name, (long)skb->len);
920
921#if (!TX_INTERRUPTABLE)
922 /* Disable MACE TX interrupts. */
923 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
924 ioaddr + AM2150_MACE_BASE + MACE_IMR);
925 lp->tx_irq_disabled=1;
926#endif /* #if (!TX_INTERRUPTABLE) */
927
928 {
929 /* This block must not be interrupted by another transmit request!
930 mace_tx_timeout will take care of timer-based retransmissions from
931 the upper layers. The interrupt handler is guaranteed never to
932 service a transmit interrupt while we are in here.
933 */
934
935 lp->linux_stats.tx_bytes += skb->len;
936 lp->tx_free_frames--;
937
938 /* WARNING: Write the _exact_ number of bytes written in the header! */
939 /* Put out the word header [must be an outw()] . . . */
940 outw(skb->len, ioaddr + AM2150_XMT);
941 /* . . . and the packet [may be any combination of outw() and outb()] */
942 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
943 if (skb->len & 1) {
944 /* Odd byte transfer */
945 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
946 }
947
948 dev->trans_start = jiffies;
949
950#if MULTI_TX
951 if (lp->tx_free_frames > 0)
952 netif_start_queue(dev);
953#endif /* #if MULTI_TX */
954 }
955
956#if (!TX_INTERRUPTABLE)
957 /* Re-enable MACE TX interrupts. */
958 lp->tx_irq_disabled=0;
959 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
960#endif /* #if (!TX_INTERRUPTABLE) */
961
962 dev_kfree_skb(skb);
963
6ed10654 964 return NETDEV_TX_OK;
1da177e4
LT		 965} /* mace_start_xmit */
966
967/* ----------------------------------------------------------------------------
968mace_interrupt
969 The interrupt handler.
970---------------------------------------------------------------------------- */
7d12e780 971static irqreturn_t mace_interrupt(int irq, void *dev_id)
1da177e4
LT		 972{
973 struct net_device *dev = (struct net_device *) dev_id;
974 mace_private *lp = netdev_priv(dev);
906da809 975 unsigned int ioaddr;
1da177e4
LT		 976 int status;
977 int IntrCnt = MACE_MAX_IR_ITERATIONS;
978
979 if (dev == NULL) {
dd0fab5b 980 pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n",
1da177e4
LT		 981 irq);
982 return IRQ_NONE;
983 }
984
c196d80f
MG		 985 ioaddr = dev->base_addr;
986
1da177e4
LT		 987 if (lp->tx_irq_disabled) {
988 printk(
989 (lp->tx_irq_disabled?
990 KERN_NOTICE "%s: Interrupt with tx_irq_disabled "
991 "[isr=%02X, imr=%02X]\n":
992 KERN_NOTICE "%s: Re-entering the interrupt handler "
993 "[isr=%02X, imr=%02X]\n"),
994 dev->name,
995 inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
996 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)
997 );
998 /* WARNING: MACE_IR has been read! */
999 return IRQ_NONE;
1000 }
1001
1002 if (!netif_device_present(dev)) {
dd0fab5b 1003 pr_debug("%s: interrupt from dead card\n", dev->name);
1da177e4
LT		 1004 return IRQ_NONE;
1005 }
1006
1007 do {
1008 /* WARNING: MACE_IR is a READ/CLEAR port! */
1009 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
1010
dd0fab5b 1011 pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
1da177e4
LT		 1012
1013 if (status & MACE_IR_RCVINT) {
1014 mace_rx(dev, MACE_MAX_RX_ITERATIONS);
1015 }
1016
1017 if (status & MACE_IR_XMTINT) {
1018 unsigned char fifofc;
1019 unsigned char xmtrc;
1020 unsigned char xmtfs;
1021
1022 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
1023 if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
1024 lp->linux_stats.tx_errors++;
1025 outb(0xFF, ioaddr + AM2150_XMT_SKIP);
1026 }
1027
1028 /* Transmit Retry Count (XMTRC, reg 4) */
1029 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
1030 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
1031 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
1032
1033 if (
1034 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
1035 MACE_XMTFS_XMTSV /* Transmit Status Valid */
1036 ) {
1037 lp->mace_stats.xmtsv++;
1038
1039 if (xmtfs & ~MACE_XMTFS_XMTSV) {
1040 if (xmtfs & MACE_XMTFS_UFLO) {
1041 /* Underflow. Indicates that the Transmit FIFO emptied before
1042 the end of frame was reached. */
1043 lp->mace_stats.uflo++;
1044 }
1045 if (xmtfs & MACE_XMTFS_LCOL) {
1046 /* Late Collision */
1047 lp->mace_stats.lcol++;
1048 }
1049 if (xmtfs & MACE_XMTFS_MORE) {
1050 /* MORE than one retry was needed */
1051 lp->mace_stats.more++;
1052 }
1053 if (xmtfs & MACE_XMTFS_ONE) {
1054 /* Exactly ONE retry occurred */
1055 lp->mace_stats.one++;
1056 }
1057 if (xmtfs & MACE_XMTFS_DEFER) {
1058 /* Transmission was defered */
1059 lp->mace_stats.defer++;
1060 }
1061 if (xmtfs & MACE_XMTFS_LCAR) {
1062 /* Loss of carrier */
1063 lp->mace_stats.lcar++;
1064 }
1065 if (xmtfs & MACE_XMTFS_RTRY) {
1066 /* Retry error: transmit aborted after 16 attempts */
1067 lp->mace_stats.rtry++;
1068 }
1069 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1070
1071 } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1072
1073 lp->linux_stats.tx_packets++;
1074 lp->tx_free_frames++;
1075 netif_wake_queue(dev);
1076 } /* if (status & MACE_IR_XMTINT) */
1077
1078 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1079 if (status & MACE_IR_JAB) {
1080 /* Jabber Error. Excessive transmit duration (20-150ms). */
1081 lp->mace_stats.jab++;
1082 }
1083 if (status & MACE_IR_BABL) {
1084 /* Babble Error. >1518 bytes transmitted. */
1085 lp->mace_stats.babl++;
1086 }
1087 if (status & MACE_IR_CERR) {
1088 /* Collision Error. CERR indicates the absence of the
1089 Signal Quality Error Test message after a packet
1090 transmission. */
1091 lp->mace_stats.cerr++;
1092 }
1093 if (status & MACE_IR_RCVCCO) {
1094 /* Receive Collision Count Overflow; */
1095 lp->mace_stats.rcvcco++;
1096 }
1097 if (status & MACE_IR_RNTPCO) {
1098 /* Runt Packet Count Overflow */
1099 lp->mace_stats.rntpco++;
1100 }
1101 if (status & MACE_IR_MPCO) {
1102 /* Missed Packet Count Overflow */
1103 lp->mace_stats.mpco++;
1104 }
1105 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1106
1107 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1108
1109 return IRQ_HANDLED;
1110} /* mace_interrupt */
1111
1112/* ----------------------------------------------------------------------------
1113mace_rx
1114 Receives packets.
1115---------------------------------------------------------------------------- */
1116static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1117{
1118 mace_private *lp = netdev_priv(dev);
906da809 1119 unsigned int ioaddr = dev->base_addr;
1da177e4
LT		 1120 unsigned char rx_framecnt;
1121 unsigned short rx_status;
1122
1123 while (
1124 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1125 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1126 (RxCnt--)
1127 ) {
1128 rx_status = inw(ioaddr + AM2150_RCV);
1129
dd0fab5b 1130 pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status"
1da177e4
LT		 1131 " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1132
1133 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1134 lp->linux_stats.rx_errors++;
1135 if (rx_status & MACE_RCVFS_OFLO) {
1136 lp->mace_stats.oflo++;
1137 }
1138 if (rx_status & MACE_RCVFS_CLSN) {
1139 lp->mace_stats.clsn++;
1140 }
1141 if (rx_status & MACE_RCVFS_FRAM) {
1142 lp->mace_stats.fram++;
1143 }
1144 if (rx_status & MACE_RCVFS_FCS) {
1145 lp->mace_stats.fcs++;
1146 }
1147 } else {
1148 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1149 /* Auto Strip is off, always subtract 4 */
1150 struct sk_buff *skb;
1151
1152 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1153 /* runt packet count */
1154 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1155 /* rcv collision count */
1156
dd0fab5b 1157 pr_debug(" receiving packet size 0x%X rx_status"
1da177e4
LT		 1158 " 0x%X.\n", pkt_len, rx_status);
1159
1160 skb = dev_alloc_skb(pkt_len+2);
1161
1162 if (skb != NULL) {
1da177e4
LT		 1163 skb_reserve(skb, 2);
1164 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1165 if (pkt_len & 1)
27a884dc 1166 *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1da177e4
LT		 1167 skb->protocol = eth_type_trans(skb, dev);
1168
1169 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1170
1da177e4 1171 lp->linux_stats.rx_packets++;
6f258910 1172 lp->linux_stats.rx_bytes += pkt_len;
1da177e4
LT		 1173 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1174 continue;
1175 } else {
dd0fab5b 1176 pr_debug("%s: couldn't allocate a sk_buff of size"
1da177e4
LT		 1177 " %d.\n", dev->name, pkt_len);
1178 lp->linux_stats.rx_dropped++;
1179 }
1180 }
1181 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1182 } /* while */
1183
1184 return 0;
1185} /* mace_rx */
1186
1187/* ----------------------------------------------------------------------------
1188pr_linux_stats
1189---------------------------------------------------------------------------- */
1190static void pr_linux_stats(struct net_device_stats *pstats)
1191{
dd0fab5b
DB		 1192 pr_debug("pr_linux_stats\n");
1193 pr_debug(" rx_packets=%-7ld tx_packets=%ld\n",
1da177e4 1194 (long)pstats->rx_packets, (long)pstats->tx_packets);
dd0fab5b 1195 pr_debug(" rx_errors=%-7ld tx_errors=%ld\n",
1da177e4 1196 (long)pstats->rx_errors, (long)pstats->tx_errors);
dd0fab5b 1197 pr_debug(" rx_dropped=%-7ld tx_dropped=%ld\n",
1da177e4 1198 (long)pstats->rx_dropped, (long)pstats->tx_dropped);
dd0fab5b 1199 pr_debug(" multicast=%-7ld collisions=%ld\n",
1da177e4
LT		 1200 (long)pstats->multicast, (long)pstats->collisions);
1201
dd0fab5b 1202 pr_debug(" rx_length_errors=%-7ld rx_over_errors=%ld\n",
1da177e4 1203 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
dd0fab5b 1204 pr_debug(" rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1da177e4 1205 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
dd0fab5b 1206 pr_debug(" rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1da177e4
LT		 1207 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1208
dd0fab5b 1209 pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1da177e4 1210 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
dd0fab5b 1211 pr_debug(" tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1da177e4 1212 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
dd0fab5b 1213 pr_debug(" tx_window_errors=%ld\n",
1da177e4
LT		 1214 (long)pstats->tx_window_errors);
1215} /* pr_linux_stats */
1216
1217/* ----------------------------------------------------------------------------
1218pr_mace_stats
1219---------------------------------------------------------------------------- */
1220static void pr_mace_stats(mace_statistics *pstats)
1221{
dd0fab5b 1222 pr_debug("pr_mace_stats\n");
1da177e4 1223
dd0fab5b 1224 pr_debug(" xmtsv=%-7d uflo=%d\n",
1da177e4 1225 pstats->xmtsv, pstats->uflo);
dd0fab5b 1226 pr_debug(" lcol=%-7d more=%d\n",
1da177e4 1227 pstats->lcol, pstats->more);
dd0fab5b 1228 pr_debug(" one=%-7d defer=%d\n",
1da177e4 1229 pstats->one, pstats->defer);
dd0fab5b 1230 pr_debug(" lcar=%-7d rtry=%d\n",
1da177e4
LT		 1231 pstats->lcar, pstats->rtry);
1232
1233 /* MACE_XMTRC */
dd0fab5b 1234 pr_debug(" exdef=%-7d xmtrc=%d\n",
1da177e4
LT		 1235 pstats->exdef, pstats->xmtrc);
1236
1237 /* RFS1--Receive Status (RCVSTS) */
dd0fab5b 1238 pr_debug(" oflo=%-7d clsn=%d\n",
1da177e4 1239 pstats->oflo, pstats->clsn);
dd0fab5b 1240 pr_debug(" fram=%-7d fcs=%d\n",
1da177e4
LT		 1241 pstats->fram, pstats->fcs);
1242
1243 /* RFS2--Runt Packet Count (RNTPC) */
1244 /* RFS3--Receive Collision Count (RCVCC) */
dd0fab5b 1245 pr_debug(" rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1da177e4
LT		 1246 pstats->rfs_rntpc, pstats->rfs_rcvcc);
1247
1248 /* MACE_IR */
dd0fab5b 1249 pr_debug(" jab=%-7d babl=%d\n",
1da177e4 1250 pstats->jab, pstats->babl);
dd0fab5b 1251 pr_debug(" cerr=%-7d rcvcco=%d\n",
1da177e4 1252 pstats->cerr, pstats->rcvcco);
dd0fab5b 1253 pr_debug(" rntpco=%-7d mpco=%d\n",
1da177e4
LT		 1254 pstats->rntpco, pstats->mpco);
1255
1256 /* MACE_MPC */
dd0fab5b 1257 pr_debug(" mpc=%d\n", pstats->mpc);
1da177e4
LT		 1258
1259 /* MACE_RNTPC */
dd0fab5b 1260 pr_debug(" rntpc=%d\n", pstats->rntpc);
1da177e4
LT		 1261
1262 /* MACE_RCVCC */
dd0fab5b 1263 pr_debug(" rcvcc=%d\n", pstats->rcvcc);
1da177e4
LT		 1264
1265} /* pr_mace_stats */
1266
1267/* ----------------------------------------------------------------------------
1268update_stats
1269 Update statistics. We change to register window 1, so this
1270 should be run single-threaded if the device is active. This is
1271 expected to be a rare operation, and it's simpler for the rest
1272 of the driver to assume that window 0 is always valid rather
1273 than use a special window-state variable.
1274
1275 oflo & uflo should _never_ occur since it would mean the Xilinx
1276 was not able to transfer data between the MACE FIFO and the
1277 card's SRAM fast enough. If this happens, something is
1278 seriously wrong with the hardware.
1279---------------------------------------------------------------------------- */
906da809 1280static void update_stats(unsigned int ioaddr, struct net_device *dev)
1da177e4
LT		 1281{
1282 mace_private *lp = netdev_priv(dev);
1283
1284 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1285 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1286 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1287 /* At this point, mace_stats is fully updated for this call.
1288 We may now update the linux_stats. */
1289
1290 /* The MACE has no equivalent for linux_stats field which are commented
1291 out. */
1292
1293 /* lp->linux_stats.multicast; */
1294 lp->linux_stats.collisions =
1295 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1296 /* Collision: The MACE may retry sending a packet 15 times
1297 before giving up. The retry count is in XMTRC.
1298 Does each retry constitute a collision?
1299 If so, why doesn't the RCVCC record these collisions? */
1300
1301 /* detailed rx_errors: */
1302 lp->linux_stats.rx_length_errors =
1303 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1304 /* lp->linux_stats.rx_over_errors */
1305 lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1306 lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1307 lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1308 lp->linux_stats.rx_missed_errors =
1309 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1310
1311 /* detailed tx_errors */
1312 lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1313 lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1314 /* LCAR usually results from bad cabling. */
1315 lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1316 lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1317 /* lp->linux_stats.tx_window_errors; */
1318
1319 return;
1320} /* update_stats */
1321
1322/* ----------------------------------------------------------------------------
1323mace_get_stats
1324 Gathers ethernet statistics from the MACE chip.
1325---------------------------------------------------------------------------- */
1326static struct net_device_stats *mace_get_stats(struct net_device *dev)
1327{
1328 mace_private *lp = netdev_priv(dev);
1329
1330 update_stats(dev->base_addr, dev);
1331
dd0fab5b 1332 pr_debug("%s: updating the statistics.\n", dev->name);
1da177e4
LT		 1333 pr_linux_stats(&lp->linux_stats);
1334 pr_mace_stats(&lp->mace_stats);
1335
1336 return &lp->linux_stats;
1337} /* net_device_stats */
1338
1339/* ----------------------------------------------------------------------------
1340updateCRC
1341 Modified from Am79C90 data sheet.
1342---------------------------------------------------------------------------- */
1343
1344#ifdef BROKEN_MULTICAST
1345
1346static void updateCRC(int *CRC, int bit)
1347{
1348 int poly[]={
1349 1,1,1,0, 1,1,0,1,
1350 1,0,1,1, 1,0,0,0,
1351 1,0,0,0, 0,0,1,1,
1352 0,0,1,0, 0,0,0,0
1353 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the
1354 CRC generator polynomial. */
1355
1356 int j;
1357
1358 /* shift CRC and control bit (CRC[32]) */
1359 for (j = 32; j > 0; j--)
1360 CRC[j] = CRC[j-1];
1361 CRC[0] = 0;
1362
1363 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1364 if (bit ^ CRC[32])
1365 for (j = 0; j < 32; j++)
1366 CRC[j] ^= poly[j];
1367} /* updateCRC */
1368
1369/* ----------------------------------------------------------------------------
1370BuildLAF
1371 Build logical address filter.
1372 Modified from Am79C90 data sheet.
1373
1374Input
1375 ladrf: logical address filter (contents initialized to 0)
1376 adr: ethernet address
1377---------------------------------------------------------------------------- */
1378static void BuildLAF(int *ladrf, int *adr)
1379{
1380 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1381
1382 int i, byte; /* temporary array indices */
1383 int hashcode; /* the output object */
1384
1385 CRC[32]=0;
1386
1387 for (byte = 0; byte < 6; byte++)
1388 for (i = 0; i < 8; i++)
1389 updateCRC(CRC, (adr[byte] >> i) & 1);
1390
1391 hashcode = 0;
1392 for (i = 0; i < 6; i++)
1393 hashcode = (hashcode << 1) + CRC[i];
1394
1395 byte = hashcode >> 3;
1396 ladrf[byte] |= (1 << (hashcode & 7));
1397
1398#ifdef PCMCIA_DEBUG
dd0fab5b 1399 if (0)
ad361c98
JP		 1400 printk(KERN_DEBUG " adr =%pM\n", adr);
1401 printk(KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63] =", hashcode);
1402 for (i = 0; i < 8; i++)
1403 printk(KERN_CONT " %02X", ladrf[i]);
1404 printk(KERN_CONT "\n");
1da177e4
LT		 1405#endif
1406} /* BuildLAF */
1407
1408/* ----------------------------------------------------------------------------
1409restore_multicast_list
1410 Restores the multicast filter for MACE chip to the last
1411 set_multicast_list() call.
1412
1413Input
1414 multicast_num_addrs
1415 multicast_ladrf[]
1416---------------------------------------------------------------------------- */
1417static void restore_multicast_list(struct net_device *dev)
1418{
1419 mace_private *lp = netdev_priv(dev);
1420 int num_addrs = lp->multicast_num_addrs;
1421 int *ladrf = lp->multicast_ladrf;
906da809 1422 unsigned int ioaddr = dev->base_addr;
1da177e4
LT		 1423 int i;
1424
dd0fab5b 1425 pr_debug("%s: restoring Rx mode to %d addresses.\n",
1da177e4
LT		 1426 dev->name, num_addrs);
1427
1428 if (num_addrs > 0) {
1429
dd0fab5b 1430 pr_debug("Attempt to restore multicast list detected.\n");
1da177e4
LT		 1431
1432 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1433 /* Poll ADDRCHG bit */
1434 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1435 ;
1436 /* Set LADRF register */
1437 for (i = 0; i < MACE_LADRF_LEN; i++)
1438 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1439
1440 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1441 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1442
1443 } else if (num_addrs < 0) {
1444
1445 /* Promiscuous mode: receive all packets */
1446 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1447 mace_write(lp, ioaddr, MACE_MACCC,
1448 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1449 );
1450
1451 } else {
1452
1453 /* Normal mode */
1454 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1455 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1456
1457 }
1458} /* restore_multicast_list */
1459
1460/* ----------------------------------------------------------------------------
1461set_multicast_list
1462 Set or clear the multicast filter for this adaptor.
1463
1464Input
1465 num_addrs == -1 Promiscuous mode, receive all packets
1466 num_addrs == 0 Normal mode, clear multicast list
1467 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1468 best-effort filtering.
1469Output
1470 multicast_num_addrs
1471 multicast_ladrf[]
1472---------------------------------------------------------------------------- */
1473
1474static void set_multicast_list(struct net_device *dev)
1475{
1476 mace_private *lp = netdev_priv(dev);
1477 int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
1478 int i;
1479 struct dev_mc_list *dmi = dev->mc_list;
1480
1481#ifdef PCMCIA_DEBUG
dd0fab5b 1482 {
1da177e4 1483 static int old;
4cd24eaf
JP		 1484 if (netdev_mc_count(dev) != old) {
1485 old = netdev_mc_count(dev);
dd0fab5b 1486 pr_debug("%s: setting Rx mode to %d addresses.\n",
1da177e4
LT		 1487 dev->name, old);
1488 }
1489 }
1490#endif
1491
1492 /* Set multicast_num_addrs. */
4cd24eaf 1493 lp->multicast_num_addrs = netdev_mc_count(dev);
1da177e4
LT		 1494
1495 /* Set multicast_ladrf. */
1496 if (num_addrs > 0) {
1497 /* Calculate multicast logical address filter */
1498 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
4cd24eaf 1499 for (i = 0; i < netdev_mc_count(dev); i++) {
1da177e4
LT		 1500 memcpy(adr, dmi->dmi_addr, ETHER_ADDR_LEN);
1501 dmi = dmi->next;
1502 BuildLAF(lp->multicast_ladrf, adr);
1503 }
1504 }
1505
1506 restore_multicast_list(dev);
1507
1508} /* set_multicast_list */
1509
1510#endif /* BROKEN_MULTICAST */
1511
1512static void restore_multicast_list(struct net_device *dev)
1513{
906da809 1514 unsigned int ioaddr = dev->base_addr;
1da177e4
LT		 1515 mace_private *lp = netdev_priv(dev);
1516
dd0fab5b 1517 pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name,
1da177e4
LT		 1518 lp->multicast_num_addrs);
1519
1520 if (dev->flags & IFF_PROMISC) {
1521 /* Promiscuous mode: receive all packets */
1522 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1523 mace_write(lp, ioaddr, MACE_MACCC,
1524 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1525 );
1526 } else {
1527 /* Normal mode */
1528 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1529 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1530 }
1531} /* restore_multicast_list */
1532
1533static void set_multicast_list(struct net_device *dev)
1534{
1535 mace_private *lp = netdev_priv(dev);
1536
1537#ifdef PCMCIA_DEBUG
dd0fab5b 1538 {
1da177e4 1539 static int old;
4cd24eaf
JP		 1540 if (netdev_mc_count(dev) != old) {
1541 old = netdev_mc_count(dev);
dd0fab5b 1542 pr_debug("%s: setting Rx mode to %d addresses.\n",
1da177e4
LT		 1543 dev->name, old);
1544 }
1545 }
1546#endif
1547
4cd24eaf 1548 lp->multicast_num_addrs = netdev_mc_count(dev);
1da177e4
LT		 1549 restore_multicast_list(dev);
1550
1551} /* set_multicast_list */
1552
a58e26cb
DB		 1553static struct pcmcia_device_id nmclan_ids[] = {
1554 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
d277ad0e 1555 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
a58e26cb
DB		 1556 PCMCIA_DEVICE_NULL,
1557};
1558MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1559
1da177e4
LT		 1560static struct pcmcia_driver nmclan_cs_driver = {
1561 .owner = THIS_MODULE,
1562 .drv = {
1563 .name = "nmclan_cs",
1564 },
15b99ac1 1565 .probe = nmclan_probe,
cc3b4866 1566 .remove = nmclan_detach,
a58e26cb 1567 .id_table = nmclan_ids,
98e4c28b
DB		 1568 .suspend = nmclan_suspend,
1569 .resume = nmclan_resume,
1da177e4
LT		 1570};
1571
1572static int __init init_nmclan_cs(void)
1573{
1574 return pcmcia_register_driver(&nmclan_cs_driver);
1575}
1576
1577static void __exit exit_nmclan_cs(void)
1578{
1579 pcmcia_unregister_driver(&nmclan_cs_driver);
1da177e4
LT		 1580}
1581
1582module_init(init_nmclan_cs);
1583module_exit(exit_nmclan_cs);
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