]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/pci-skeleton.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
[net-next-2.6.git] / drivers / net / pci-skeleton.c
CommitLineData
1da177e4
LT		 1/*
2
3 drivers/net/pci-skeleton.c
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6
7 Original code came from 8139too.c, which in turns was based
8 originally on Donald Becker's rtl8139.c driver, versions 1.11
9 and older. This driver was originally based on rtl8139.c
10 version 1.07. Header of rtl8139.c version 1.11:
11
12 -----<snip>-----
13
14 Written 1997-2000 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41
42-----------------------------------------------------------------------------
43
44 Theory of Operation
45
46I. Board Compatibility
47
48This device driver is designed for the RealTek RTL8139 series, the RealTek
49Fast Ethernet controllers for PCI and CardBus. This chip is used on many
50low-end boards, sometimes with its markings changed.
51
52
53II. Board-specific settings
54
55PCI bus devices are configured by the system at boot time, so no jumpers
56need to be set on the board. The system BIOS will assign the
57PCI INTA signal to a (preferably otherwise unused) system IRQ line.
58
59III. Driver operation
60
61IIIa. Rx Ring buffers
62
63The receive unit uses a single linear ring buffer rather than the more
64common (and more efficient) descriptor-based architecture. Incoming frames
65are sequentially stored into the Rx region, and the host copies them into
66skbuffs.
67
68Comment: While it is theoretically possible to process many frames in place,
69any delay in Rx processing would cause us to drop frames. More importantly,
70the Linux protocol stack is not designed to operate in this manner.
71
72IIIb. Tx operation
73
74The RTL8139 uses a fixed set of four Tx descriptors in register space.
75In a stunningly bad design choice, Tx frames must be 32 bit aligned. Linux
76aligns the IP header on word boundaries, and 14 byte ethernet header means
77that almost all frames will need to be copied to an alignment buffer.
78
79IVb. References
80
81http://www.realtek.com.tw/cn/cn.html
82http://www.scyld.com/expert/NWay.html
83
84IVc. Errata
85
86*/
87
1da177e4
LT		 88#include <linux/module.h>
89#include <linux/kernel.h>
90#include <linux/pci.h>
91#include <linux/init.h>
92#include <linux/ioport.h>
93#include <linux/netdevice.h>
94#include <linux/etherdevice.h>
95#include <linux/delay.h>
96#include <linux/ethtool.h>
97#include <linux/mii.h>
98#include <linux/crc32.h>
99#include <asm/io.h>
100
d5b20697 101#define NETDRV_VERSION "1.0.1"
1da177e4
LT		 102#define MODNAME "netdrv"
103#define NETDRV_DRIVER_LOAD_MSG "MyVendor Fast Ethernet driver " NETDRV_VERSION " loaded"
104#define PFX MODNAME ": "
105
106static char version[] __devinitdata =
107KERN_INFO NETDRV_DRIVER_LOAD_MSG "\n"
108KERN_INFO " Support available from http://foo.com/bar/baz.html\n";
109
110/* define to 1 to enable PIO instead of MMIO */
111#undef USE_IO_OPS
112
113/* define to 1 to enable copious debugging info */
114#undef NETDRV_DEBUG
115
116/* define to 1 to disable lightweight runtime debugging checks */
117#undef NETDRV_NDEBUG
118
119
120#ifdef NETDRV_DEBUG
121/* note: prints function name for you */
122# define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
123#else
124# define DPRINTK(fmt, args...)
125#endif
126
127#ifdef NETDRV_NDEBUG
128# define assert(expr) do {} while (0)
129#else
130# define assert(expr) \
131 if(!(expr)) { \
132 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
133 #expr,__FILE__,__FUNCTION__,__LINE__); \
134 }
135#endif
136
137
138/* A few user-configurable values. */
139/* media options */
140static int media[] = {-1, -1, -1, -1, -1, -1, -1, -1};
141
142/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
143static int max_interrupt_work = 20;
144
145/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
146 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
147static int multicast_filter_limit = 32;
148
149/* Size of the in-memory receive ring. */
150#define RX_BUF_LEN_IDX 2 /* 0==8K, 1==16K, 2==32K, 3==64K */
151#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
152#define RX_BUF_PAD 16
153#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
154#define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
155
156/* Number of Tx descriptor registers. */
157#define NUM_TX_DESC 4
158
159/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
160#define MAX_ETH_FRAME_SIZE 1536
161
162/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
163#define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
164#define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
165
166/* PCI Tuning Parameters
167 Threshold is bytes transferred to chip before transmission starts. */
168#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
169
170/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
171#define RX_FIFO_THRESH 6 /* Rx buffer level before first PCI xfer. */
172#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
173#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
174
175
176/* Operational parameters that usually are not changed. */
177/* Time in jiffies before concluding the transmitter is hung. */
178#define TX_TIMEOUT (6*HZ)
179
180
181enum {
182 HAS_CHIP_XCVR = 0x020000,
183 HAS_LNK_CHNG = 0x040000,
184};
185
186#define NETDRV_MIN_IO_SIZE 0x80
187#define RTL8139B_IO_SIZE 256
188
189#define NETDRV_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
190
191typedef enum {
192 RTL8139 = 0,
193 NETDRV_CB,
194 SMC1211TX,
195 /*MPX5030,*/
196 DELTA8139,
197 ADDTRON8139,
198} board_t;
199
200
201/* indexed by board_t, above */
202static struct {
203 const char *name;
204} board_info[] __devinitdata = {
205 { "RealTek RTL8139 Fast Ethernet" },
206 { "RealTek RTL8139B PCI/CardBus" },
207 { "SMC1211TX EZCard 10/100 (RealTek RTL8139)" },
208/* { MPX5030, "Accton MPX5030 (RealTek RTL8139)" },*/
209 { "Delta Electronics 8139 10/100BaseTX" },
210 { "Addtron Technolgy 8139 10/100BaseTX" },
211};
212
213
214static struct pci_device_id netdrv_pci_tbl[] = {
215 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
216 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, NETDRV_CB },
217 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
218/* {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
219 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
220 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
221 {0,}
222};
223MODULE_DEVICE_TABLE (pci, netdrv_pci_tbl);
224
225
226/* The rest of these values should never change. */
227
228/* Symbolic offsets to registers. */
229enum NETDRV_registers {
230 MAC0 = 0, /* Ethernet hardware address. */
231 MAR0 = 8, /* Multicast filter. */
232 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
233 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
234 RxBuf = 0x30,
235 RxEarlyCnt = 0x34,
236 RxEarlyStatus = 0x36,
237 ChipCmd = 0x37,
238 RxBufPtr = 0x38,
239 RxBufAddr = 0x3A,
240 IntrMask = 0x3C,
241 IntrStatus = 0x3E,
242 TxConfig = 0x40,
243 ChipVersion = 0x43,
244 RxConfig = 0x44,
245 Timer = 0x48, /* A general-purpose counter. */
246 RxMissed = 0x4C, /* 24 bits valid, write clears. */
247 Cfg9346 = 0x50,
248 Config0 = 0x51,
249 Config1 = 0x52,
250 FlashReg = 0x54,
251 MediaStatus = 0x58,
252 Config3 = 0x59,
253 Config4 = 0x5A, /* absent on RTL-8139A */
254 HltClk = 0x5B,
255 MultiIntr = 0x5C,
256 TxSummary = 0x60,
257 BasicModeCtrl = 0x62,
258 BasicModeStatus = 0x64,
259 NWayAdvert = 0x66,
260 NWayLPAR = 0x68,
261 NWayExpansion = 0x6A,
262 /* Undocumented registers, but required for proper operation. */
263 FIFOTMS = 0x70, /* FIFO Control and test. */
264 CSCR = 0x74, /* Chip Status and Configuration Register. */
265 PARA78 = 0x78,
266 PARA7c = 0x7c, /* Magic transceiver parameter register. */
267 Config5 = 0xD8, /* absent on RTL-8139A */
268};
269
270enum ClearBitMasks {
271 MultiIntrClear = 0xF000,
272 ChipCmdClear = 0xE2,
273 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
274};
275
276enum ChipCmdBits {
277 CmdReset = 0x10,
278 CmdRxEnb = 0x08,
279 CmdTxEnb = 0x04,
280 RxBufEmpty = 0x01,
281};
282
283/* Interrupt register bits, using my own meaningful names. */
284enum IntrStatusBits {
285 PCIErr = 0x8000,
286 PCSTimeout = 0x4000,
287 RxFIFOOver = 0x40,
288 RxUnderrun = 0x20,
289 RxOverflow = 0x10,
290 TxErr = 0x08,
291 TxOK = 0x04,
292 RxErr = 0x02,
293 RxOK = 0x01,
294};
295enum TxStatusBits {
296 TxHostOwns = 0x2000,
297 TxUnderrun = 0x4000,
298 TxStatOK = 0x8000,
299 TxOutOfWindow = 0x20000000,
300 TxAborted = 0x40000000,
301 TxCarrierLost = 0x80000000,
302};
303enum RxStatusBits {
304 RxMulticast = 0x8000,
305 RxPhysical = 0x4000,
306 RxBroadcast = 0x2000,
307 RxBadSymbol = 0x0020,
308 RxRunt = 0x0010,
309 RxTooLong = 0x0008,
310 RxCRCErr = 0x0004,
311 RxBadAlign = 0x0002,
312 RxStatusOK = 0x0001,
313};
314
315/* Bits in RxConfig. */
316enum rx_mode_bits {
317 AcceptErr = 0x20,
318 AcceptRunt = 0x10,
319 AcceptBroadcast = 0x08,
320 AcceptMulticast = 0x04,
321 AcceptMyPhys = 0x02,
322 AcceptAllPhys = 0x01,
323};
324
325/* Bits in TxConfig. */
326enum tx_config_bits {
327 TxIFG1 = (1 << 25), /* Interframe Gap Time */
328 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
329 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
330 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
331 TxClearAbt = (1 << 0), /* Clear abort (WO) */
332 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
333
334 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
335};
336
337/* Bits in Config1 */
338enum Config1Bits {
339 Cfg1_PM_Enable = 0x01,
340 Cfg1_VPD_Enable = 0x02,
341 Cfg1_PIO = 0x04,
342 Cfg1_MMIO = 0x08,
343 Cfg1_LWAKE = 0x10,
344 Cfg1_Driver_Load = 0x20,
345 Cfg1_LED0 = 0x40,
346 Cfg1_LED1 = 0x80,
347};
348
349enum RxConfigBits {
350 /* Early Rx threshold, none or X/16 */
351 RxCfgEarlyRxNone = 0,
352 RxCfgEarlyRxShift = 24,
353
354 /* rx fifo threshold */
355 RxCfgFIFOShift = 13,
356 RxCfgFIFONone = (7 << RxCfgFIFOShift),
357
358 /* Max DMA burst */
359 RxCfgDMAShift = 8,
360 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
361
362 /* rx ring buffer length */
363 RxCfgRcv8K = 0,
364 RxCfgRcv16K = (1 << 11),
365 RxCfgRcv32K = (1 << 12),
366 RxCfgRcv64K = (1 << 11) | (1 << 12),
367
368 /* Disable packet wrap at end of Rx buffer */
369 RxNoWrap = (1 << 7),
370};
371
372
373/* Twister tuning parameters from RealTek.
374 Completely undocumented, but required to tune bad links. */
375enum CSCRBits {
376 CSCR_LinkOKBit = 0x0400,
377 CSCR_LinkChangeBit = 0x0800,
378 CSCR_LinkStatusBits = 0x0f000,
379 CSCR_LinkDownOffCmd = 0x003c0,
380 CSCR_LinkDownCmd = 0x0f3c0,
381};
382
383
384enum Cfg9346Bits {
385 Cfg9346_Lock = 0x00,
386 Cfg9346_Unlock = 0xC0,
387};
388
389
390#define PARA78_default 0x78fa8388
391#define PARA7c_default 0xcb38de43 /* param[0][3] */
392#define PARA7c_xxx 0xcb38de43
393static const unsigned long param[4][4] = {
394 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
395 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
396 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
397 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
398};
399
400struct ring_info {
401 struct sk_buff *skb;
402 dma_addr_t mapping;
403};
404
405
406typedef enum {
407 CH_8139 = 0,
408 CH_8139_K,
409 CH_8139A,
410 CH_8139B,
411 CH_8130,
412 CH_8139C,
413} chip_t;
414
415
416/* directly indexed by chip_t, above */
3c6bee1d 417static const struct {
1da177e4
LT		 418 const char *name;
419 u8 version; /* from RTL8139C docs */
420 u32 RxConfigMask; /* should clear the bits supported by this chip */
421} rtl_chip_info[] = {
422 { "RTL-8139",
423 0x40,
424 0xf0fe0040, /* XXX copied from RTL8139A, verify */
425 },
426
427 { "RTL-8139 rev K",
428 0x60,
429 0xf0fe0040,
430 },
431
432 { "RTL-8139A",
433 0x70,
434 0xf0fe0040,
435 },
436
437 { "RTL-8139B",
438 0x78,
439 0xf0fc0040
440 },
441
442 { "RTL-8130",
443 0x7C,
444 0xf0fe0040, /* XXX copied from RTL8139A, verify */
445 },
446
447 { "RTL-8139C",
448 0x74,
449 0xf0fc0040, /* XXX copied from RTL8139B, verify */
450 },
451
452};
453
454
455struct netdrv_private {
456 board_t board;
457 void *mmio_addr;
458 int drv_flags;
459 struct pci_dev *pci_dev;
460 struct net_device_stats stats;
461 struct timer_list timer; /* Media selection timer. */
462 unsigned char *rx_ring;
463 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
464 unsigned int tx_flag;
465 atomic_t cur_tx;
466 atomic_t dirty_tx;
467 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
468 struct ring_info tx_info[NUM_TX_DESC];
469 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
470 unsigned char *tx_bufs; /* Tx bounce buffer region. */
471 dma_addr_t rx_ring_dma;
472 dma_addr_t tx_bufs_dma;
473 char phys[4]; /* MII device addresses. */
474 char twistie, twist_row, twist_col; /* Twister tune state. */
475 unsigned int full_duplex:1; /* Full-duplex operation requested. */
476 unsigned int duplex_lock:1;
477 unsigned int default_port:4; /* Last dev->if_port value. */
478 unsigned int media2:4; /* Secondary monitored media port. */
479 unsigned int medialock:1; /* Don't sense media type. */
480 unsigned int mediasense:1; /* Media sensing in progress. */
481 spinlock_t lock;
482 chip_t chipset;
483};
484
485MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
486MODULE_DESCRIPTION ("Skeleton for a PCI Fast Ethernet driver");
487MODULE_LICENSE("GPL");
2f761478
VF		 488module_param(multicast_filter_limit, int, 0);
489module_param(max_interrupt_work, int, 0);
490module_param_array(media, int, NULL, 0);
1da177e4
LT		 491MODULE_PARM_DESC (multicast_filter_limit, "pci-skeleton maximum number of filtered multicast addresses");
492MODULE_PARM_DESC (max_interrupt_work, "pci-skeleton maximum events handled per interrupt");
493MODULE_PARM_DESC (media, "pci-skeleton: Bits 0-3: media type, bit 17: full duplex");
494
495static int read_eeprom (void *ioaddr, int location, int addr_len);
496static int netdrv_open (struct net_device *dev);
497static int mdio_read (struct net_device *dev, int phy_id, int location);
498static void mdio_write (struct net_device *dev, int phy_id, int location,
499 int val);
500static void netdrv_timer (unsigned long data);
501static void netdrv_tx_timeout (struct net_device *dev);
502static void netdrv_init_ring (struct net_device *dev);
503static int netdrv_start_xmit (struct sk_buff *skb,
504 struct net_device *dev);
7d12e780 505static irqreturn_t netdrv_interrupt (int irq, void *dev_instance);
1da177e4
LT		 506static int netdrv_close (struct net_device *dev);
507static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
508static struct net_device_stats *netdrv_get_stats (struct net_device *dev);
509static void netdrv_set_rx_mode (struct net_device *dev);
510static void netdrv_hw_start (struct net_device *dev);
511
512
513#ifdef USE_IO_OPS
514
515#define NETDRV_R8(reg) inb (((unsigned long)ioaddr) + (reg))
516#define NETDRV_R16(reg) inw (((unsigned long)ioaddr) + (reg))
517#define NETDRV_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
518#define NETDRV_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
519#define NETDRV_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
520#define NETDRV_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
521#define NETDRV_W8_F NETDRV_W8
522#define NETDRV_W16_F NETDRV_W16
523#define NETDRV_W32_F NETDRV_W32
524#undef readb
525#undef readw
526#undef readl
527#undef writeb
528#undef writew
529#undef writel
530#define readb(addr) inb((unsigned long)(addr))
531#define readw(addr) inw((unsigned long)(addr))
532#define readl(addr) inl((unsigned long)(addr))
533#define writeb(val,addr) outb((val),(unsigned long)(addr))
534#define writew(val,addr) outw((val),(unsigned long)(addr))
535#define writel(val,addr) outl((val),(unsigned long)(addr))
536
537#else
538
539/* write MMIO register, with flush */
540/* Flush avoids rtl8139 bug w/ posted MMIO writes */
541#define NETDRV_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
542#define NETDRV_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
543#define NETDRV_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
544
545
546#if MMIO_FLUSH_AUDIT_COMPLETE
547
548/* write MMIO register */
549#define NETDRV_W8(reg, val8) writeb ((val8), ioaddr + (reg))
550#define NETDRV_W16(reg, val16) writew ((val16), ioaddr + (reg))
551#define NETDRV_W32(reg, val32) writel ((val32), ioaddr + (reg))
552
553#else
554
555/* write MMIO register, then flush */
556#define NETDRV_W8 NETDRV_W8_F
557#define NETDRV_W16 NETDRV_W16_F
558#define NETDRV_W32 NETDRV_W32_F
559
560#endif /* MMIO_FLUSH_AUDIT_COMPLETE */
561
562/* read MMIO register */
563#define NETDRV_R8(reg) readb (ioaddr + (reg))
564#define NETDRV_R16(reg) readw (ioaddr + (reg))
565#define NETDRV_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
566
567#endif /* USE_IO_OPS */
568
569
570static const u16 netdrv_intr_mask =
571 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
572 TxErr | TxOK | RxErr | RxOK;
573
574static const unsigned int netdrv_rx_config =
575 RxCfgEarlyRxNone | RxCfgRcv32K | RxNoWrap |
576 (RX_FIFO_THRESH << RxCfgFIFOShift) |
577 (RX_DMA_BURST << RxCfgDMAShift);
578
579
580static int __devinit netdrv_init_board (struct pci_dev *pdev,
581 struct net_device **dev_out,
582 void **ioaddr_out)
583{
584 void *ioaddr = NULL;
585 struct net_device *dev;
586 struct netdrv_private *tp;
587 int rc, i;
588 u32 pio_start, pio_end, pio_flags, pio_len;
589 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
590 u32 tmp;
591
592 DPRINTK ("ENTER\n");
593
594 assert (pdev != NULL);
595 assert (ioaddr_out != NULL);
596
597 *ioaddr_out = NULL;
598 *dev_out = NULL;
599
600 /* dev zeroed in alloc_etherdev */
601 dev = alloc_etherdev (sizeof (*tp));
602 if (dev == NULL) {
9b91cf9d 603 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1da177e4
LT		 604 DPRINTK ("EXIT, returning -ENOMEM\n");
605 return -ENOMEM;
606 }
607 SET_MODULE_OWNER(dev);
608 SET_NETDEV_DEV(dev, &pdev->dev);
609 tp = dev->priv;
610
611 /* enable device (incl. PCI PM wakeup), and bus-mastering */
612 rc = pci_enable_device (pdev);
613 if (rc)
614 goto err_out;
615
616 pio_start = pci_resource_start (pdev, 0);
617 pio_end = pci_resource_end (pdev, 0);
618 pio_flags = pci_resource_flags (pdev, 0);
619 pio_len = pci_resource_len (pdev, 0);
620
621 mmio_start = pci_resource_start (pdev, 1);
622 mmio_end = pci_resource_end (pdev, 1);
623 mmio_flags = pci_resource_flags (pdev, 1);
624 mmio_len = pci_resource_len (pdev, 1);
625
626 /* set this immediately, we need to know before
627 * we talk to the chip directly */
628 DPRINTK("PIO region size == 0x%02X\n", pio_len);
629 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
630
631 /* make sure PCI base addr 0 is PIO */
632 if (!(pio_flags & IORESOURCE_IO)) {
9b91cf9d 633 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
1da177e4
LT		 634 rc = -ENODEV;
635 goto err_out;
636 }
637
638 /* make sure PCI base addr 1 is MMIO */
639 if (!(mmio_flags & IORESOURCE_MEM)) {
9b91cf9d 640 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
1da177e4
LT		 641 rc = -ENODEV;
642 goto err_out;
643 }
644
645 /* check for weird/broken PCI region reporting */
646 if ((pio_len < NETDRV_MIN_IO_SIZE) ||
647 (mmio_len < NETDRV_MIN_IO_SIZE)) {
9b91cf9d 648 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
1da177e4
LT		 649 rc = -ENODEV;
650 goto err_out;
651 }
652
2e8a538d 653 rc = pci_request_regions (pdev, MODNAME);
1da177e4
LT		 654 if (rc)
655 goto err_out;
656
657 pci_set_master (pdev);
658
659#ifdef USE_IO_OPS
660 ioaddr = (void *) pio_start;
661#else
662 /* ioremap MMIO region */
663 ioaddr = ioremap (mmio_start, mmio_len);
664 if (ioaddr == NULL) {
9b91cf9d 665 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4
LT		 666 rc = -EIO;
667 goto err_out_free_res;
668 }
669#endif /* USE_IO_OPS */
670
671 /* Soft reset the chip. */
672 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
673
674 /* Check that the chip has finished the reset. */
675 for (i = 1000; i > 0; i--)
676 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
677 break;
678 else
679 udelay (10);
680
681 /* Bring the chip out of low-power mode. */
682 /* <insert device-specific code here> */
683
684#ifndef USE_IO_OPS
685 /* sanity checks -- ensure PIO and MMIO registers agree */
686 assert (inb (pio_start+Config0) == readb (ioaddr+Config0));
687 assert (inb (pio_start+Config1) == readb (ioaddr+Config1));
688 assert (inb (pio_start+TxConfig) == readb (ioaddr+TxConfig));
689 assert (inb (pio_start+RxConfig) == readb (ioaddr+RxConfig));
690#endif /* !USE_IO_OPS */
691
692 /* identify chip attached to board */
693 tmp = NETDRV_R8 (ChipVersion);
694 for (i = ARRAY_SIZE (rtl_chip_info) - 1; i >= 0; i--)
695 if (tmp == rtl_chip_info[i].version) {
696 tp->chipset = i;
697 goto match;
698 }
699
700 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
2e8a538d
JG		 701 dev_printk (KERN_DEBUG, &pdev->dev,
702 "unknown chip version, assuming RTL-8139\n");
703 dev_printk (KERN_DEBUG, &pdev->dev, "TxConfig = 0x%lx\n",
704 NETDRV_R32 (TxConfig));
1da177e4
LT		 705 tp->chipset = 0;
706
707match:
708 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
709 tmp,
710 tp->chipset,
711 rtl_chip_info[tp->chipset].name);
712
713 i = register_netdev (dev);
714 if (i)
715 goto err_out_unmap;
716
717 DPRINTK ("EXIT, returning 0\n");
718 *ioaddr_out = ioaddr;
719 *dev_out = dev;
720 return 0;
721
722err_out_unmap:
723#ifndef USE_IO_OPS
724 iounmap(ioaddr);
725err_out_free_res:
726#endif
727 pci_release_regions (pdev);
728err_out:
729 free_netdev (dev);
730 DPRINTK ("EXIT, returning %d\n", rc);
731 return rc;
732}
733
734
735static int __devinit netdrv_init_one (struct pci_dev *pdev,
736 const struct pci_device_id *ent)
737{
738 struct net_device *dev = NULL;
739 struct netdrv_private *tp;
740 int i, addr_len, option;
741 void *ioaddr = NULL;
742 static int board_idx = -1;
743
744/* when built into the kernel, we only print version if device is found */
745#ifndef MODULE
746 static int printed_version;
747 if (!printed_version++)
748 printk(version);
749#endif
750
751 DPRINTK ("ENTER\n");
752
753 assert (pdev != NULL);
754 assert (ent != NULL);
755
756 board_idx++;
757
758 i = netdrv_init_board (pdev, &dev, &ioaddr);
759 if (i < 0) {
760 DPRINTK ("EXIT, returning %d\n", i);
761 return i;
762 }
763
764 tp = dev->priv;
765
766 assert (ioaddr != NULL);
767 assert (dev != NULL);
768 assert (tp != NULL);
769
770 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
771 for (i = 0; i < 3; i++)
772 ((u16 *) (dev->dev_addr))[i] =
773 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
774
775 /* The Rtl8139-specific entries in the device structure. */
776 dev->open = netdrv_open;
777 dev->hard_start_xmit = netdrv_start_xmit;
778 dev->stop = netdrv_close;
779 dev->get_stats = netdrv_get_stats;
780 dev->set_multicast_list = netdrv_set_rx_mode;
781 dev->do_ioctl = netdrv_ioctl;
782 dev->tx_timeout = netdrv_tx_timeout;
783 dev->watchdog_timeo = TX_TIMEOUT;
784
785 dev->irq = pdev->irq;
786 dev->base_addr = (unsigned long) ioaddr;
787
788 /* dev->priv/tp zeroed and aligned in alloc_etherdev */
789 tp = dev->priv;
790
791 /* note: tp->chipset set in netdrv_init_board */
792 tp->drv_flags = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
793 PCI_COMMAND_MASTER | NETDRV_CAPS;
794 tp->pci_dev = pdev;
795 tp->board = ent->driver_data;
796 tp->mmio_addr = ioaddr;
797 spin_lock_init(&tp->lock);
798
799 pci_set_drvdata(pdev, dev);
800
801 tp->phys[0] = 32;
802
803 printk (KERN_INFO "%s: %s at 0x%lx, "
804 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
805 "IRQ %d\n",
806 dev->name,
807 board_info[ent->driver_data].name,
808 dev->base_addr,
809 dev->dev_addr[0], dev->dev_addr[1],
810 dev->dev_addr[2], dev->dev_addr[3],
811 dev->dev_addr[4], dev->dev_addr[5],
812 dev->irq);
813
814 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
815 dev->name, rtl_chip_info[tp->chipset].name);
816
817 /* Put the chip into low-power mode. */
818 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
819
820 /* The lower four bits are the media type. */
821 option = (board_idx > 7) ? 0 : media[board_idx];
822 if (option > 0) {
823 tp->full_duplex = (option & 0x200) ? 1 : 0;
824 tp->default_port = option & 15;
825 if (tp->default_port)
826 tp->medialock = 1;
827 }
828
829 if (tp->full_duplex) {
830 printk (KERN_INFO
831 "%s: Media type forced to Full Duplex.\n",
832 dev->name);
833 mdio_write (dev, tp->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
834 tp->duplex_lock = 1;
835 }
836
837 DPRINTK ("EXIT - returning 0\n");
838 return 0;
839}
840
841
842static void __devexit netdrv_remove_one (struct pci_dev *pdev)
843{
844 struct net_device *dev = pci_get_drvdata (pdev);
845 struct netdrv_private *np;
846
847 DPRINTK ("ENTER\n");
848
849 assert (dev != NULL);
850
851 np = dev->priv;
852 assert (np != NULL);
853
854 unregister_netdev (dev);
855
856#ifndef USE_IO_OPS
857 iounmap (np->mmio_addr);
858#endif /* !USE_IO_OPS */
859
860 pci_release_regions (pdev);
861
862 free_netdev (dev);
863
864 pci_set_drvdata (pdev, NULL);
865
866 pci_disable_device (pdev);
867
868 DPRINTK ("EXIT\n");
869}
870
871
872/* Serial EEPROM section. */
873
874/* EEPROM_Ctrl bits. */
875#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
876#define EE_CS 0x08 /* EEPROM chip select. */
877#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
878#define EE_WRITE_0 0x00
879#define EE_WRITE_1 0x02
880#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
881#define EE_ENB (0x80 | EE_CS)
882
883/* Delay between EEPROM clock transitions.
884 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
885 */
886
887#define eeprom_delay() readl(ee_addr)
888
889/* The EEPROM commands include the alway-set leading bit. */
890#define EE_WRITE_CMD (5)
891#define EE_READ_CMD (6)
892#define EE_ERASE_CMD (7)
893
894static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
895{
896 int i;
897 unsigned retval = 0;
898 void *ee_addr = ioaddr + Cfg9346;
899 int read_cmd = location | (EE_READ_CMD << addr_len);
900
901 DPRINTK ("ENTER\n");
902
903 writeb (EE_ENB & ~EE_CS, ee_addr);
904 writeb (EE_ENB, ee_addr);
905 eeprom_delay ();
906
907 /* Shift the read command bits out. */
908 for (i = 4 + addr_len; i >= 0; i--) {
909 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
910 writeb (EE_ENB | dataval, ee_addr);
911 eeprom_delay ();
912 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
913 eeprom_delay ();
914 }
915 writeb (EE_ENB, ee_addr);
916 eeprom_delay ();
917
918 for (i = 16; i > 0; i--) {
919 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
920 eeprom_delay ();
921 retval =
922 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
923 0);
924 writeb (EE_ENB, ee_addr);
925 eeprom_delay ();
926 }
927
928 /* Terminate the EEPROM access. */
929 writeb (~EE_CS, ee_addr);
930 eeprom_delay ();
931
932 DPRINTK ("EXIT - returning %d\n", retval);
933 return retval;
934}
935
936/* MII serial management: mostly bogus for now. */
937/* Read and write the MII management registers using software-generated
938 serial MDIO protocol.
939 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
940 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
941 "overclocking" issues. */
942#define MDIO_DIR 0x80
943#define MDIO_DATA_OUT 0x04
944#define MDIO_DATA_IN 0x02
945#define MDIO_CLK 0x01
946#define MDIO_WRITE0 (MDIO_DIR)
947#define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
948
949#define mdio_delay() readb(mdio_addr)
950
951
952static char mii_2_8139_map[8] = {
953 BasicModeCtrl,
954 BasicModeStatus,
955 0,
956 0,
957 NWayAdvert,
958 NWayLPAR,
959 NWayExpansion,
960 0
961};
962
963
964/* Syncronize the MII management interface by shifting 32 one bits out. */
965static void mdio_sync (void *mdio_addr)
966{
967 int i;
968
969 DPRINTK ("ENTER\n");
970
971 for (i = 32; i >= 0; i--) {
972 writeb (MDIO_WRITE1, mdio_addr);
973 mdio_delay ();
974 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
975 mdio_delay ();
976 }
977
978 DPRINTK ("EXIT\n");
979}
980
981
982static int mdio_read (struct net_device *dev, int phy_id, int location)
983{
984 struct netdrv_private *tp = dev->priv;
985 void *mdio_addr = tp->mmio_addr + Config4;
986 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
987 int retval = 0;
988 int i;
989
990 DPRINTK ("ENTER\n");
991
992 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
993 DPRINTK ("EXIT after directly using 8139 internal regs\n");
994 return location < 8 && mii_2_8139_map[location] ?
995 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
996 }
997 mdio_sync (mdio_addr);
998 /* Shift the read command bits out. */
999 for (i = 15; i >= 0; i--) {
1000 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1001
1002 writeb (MDIO_DIR | dataval, mdio_addr);
1003 mdio_delay ();
1004 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1005 mdio_delay ();
1006 }
1007
1008 /* Read the two transition, 16 data, and wire-idle bits. */
1009 for (i = 19; i > 0; i--) {
1010 writeb (0, mdio_addr);
1011 mdio_delay ();
1012 retval =
1013 (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1
1014 : 0);
1015 writeb (MDIO_CLK, mdio_addr);
1016 mdio_delay ();
1017 }
1018
1019 DPRINTK ("EXIT, returning %d\n", (retval >> 1) & 0xffff);
1020 return (retval >> 1) & 0xffff;
1021}
1022
1023
1024static void mdio_write (struct net_device *dev, int phy_id, int location,
1025 int value)
1026{
1027 struct netdrv_private *tp = dev->priv;
1028 void *mdio_addr = tp->mmio_addr + Config4;
1029 int mii_cmd =
1030 (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1031 int i;
1032
1033 DPRINTK ("ENTER\n");
1034
1035 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1036 if (location < 8 && mii_2_8139_map[location]) {
1037 writew (value,
1038 tp->mmio_addr + mii_2_8139_map[location]);
1039 readw (tp->mmio_addr + mii_2_8139_map[location]);
1040 }
1041 DPRINTK ("EXIT after directly using 8139 internal regs\n");
1042 return;
1043 }
1044 mdio_sync (mdio_addr);
1045
1046 /* Shift the command bits out. */
1047 for (i = 31; i >= 0; i--) {
1048 int dataval =
1049 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1050 writeb (dataval, mdio_addr);
1051 mdio_delay ();
1052 writeb (dataval | MDIO_CLK, mdio_addr);
1053 mdio_delay ();
1054 }
1055
1056 /* Clear out extra bits. */
1057 for (i = 2; i > 0; i--) {
1058 writeb (0, mdio_addr);
1059 mdio_delay ();
1060 writeb (MDIO_CLK, mdio_addr);
1061 mdio_delay ();
1062 }
1063
1064 DPRINTK ("EXIT\n");
1065}
1066
1067
1068static int netdrv_open (struct net_device *dev)
1069{
1070 struct netdrv_private *tp = dev->priv;
1071 int retval;
1072#ifdef NETDRV_DEBUG
1073 void *ioaddr = tp->mmio_addr;
1074#endif
1075
1076 DPRINTK ("ENTER\n");
1077
1fb9df5d 1078 retval = request_irq (dev->irq, netdrv_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1079 if (retval) {
1080 DPRINTK ("EXIT, returning %d\n", retval);
1081 return retval;
1082 }
1083
1084 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1085 &tp->tx_bufs_dma);
1086 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1087 &tp->rx_ring_dma);
1088 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1089 free_irq(dev->irq, dev);
1090
1091 if (tp->tx_bufs)
1092 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1093 tp->tx_bufs, tp->tx_bufs_dma);
1094 if (tp->rx_ring)
1095 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1096 tp->rx_ring, tp->rx_ring_dma);
1097
1098 DPRINTK ("EXIT, returning -ENOMEM\n");
1099 return -ENOMEM;
1100
1101 }
1102
1103 tp->full_duplex = tp->duplex_lock;
1104 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1105
1106 netdrv_init_ring (dev);
1107 netdrv_hw_start (dev);
1108
1109 DPRINTK ("%s: netdrv_open() ioaddr %#lx IRQ %d"
1110 " GP Pins %2.2x %s-duplex.\n",
1111 dev->name, pci_resource_start (tp->pci_dev, 1),
1112 dev->irq, NETDRV_R8 (MediaStatus),
1113 tp->full_duplex ? "full" : "half");
1114
1115 /* Set the timer to switch to check for link beat and perhaps switch
1116 to an alternate media type. */
1117 init_timer (&tp->timer);
1118 tp->timer.expires = jiffies + 3 * HZ;
1119 tp->timer.data = (unsigned long) dev;
1120 tp->timer.function = &netdrv_timer;
1121 add_timer (&tp->timer);
1122
1123 DPRINTK ("EXIT, returning 0\n");
1124 return 0;
1125}
1126
1127
1128/* Start the hardware at open or resume. */
1129static void netdrv_hw_start (struct net_device *dev)
1130{
1131 struct netdrv_private *tp = dev->priv;
1132 void *ioaddr = tp->mmio_addr;
1133 u32 i;
1134
1135 DPRINTK ("ENTER\n");
1136
1137 /* Soft reset the chip. */
1138 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
1139 udelay (100);
1140
1141 /* Check that the chip has finished the reset. */
1142 for (i = 1000; i > 0; i--)
1143 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
1144 break;
1145
1146 /* Restore our idea of the MAC address. */
1147 NETDRV_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1148 NETDRV_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1149
1150 /* Must enable Tx/Rx before setting transfer thresholds! */
1151 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1152 CmdRxEnb | CmdTxEnb);
1153
1154 i = netdrv_rx_config |
1155 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1156 NETDRV_W32_F (RxConfig, i);
1157
1158 /* Check this value: the documentation for IFG contradicts ifself. */
1159 NETDRV_W32 (TxConfig, (TX_DMA_BURST << TxDMAShift));
1160
1161 /* unlock Config[01234] and BMCR register writes */
1162 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
1163 udelay (10);
1164
1165 tp->cur_rx = 0;
1166
1167 /* Lock Config[01234] and BMCR register writes */
1168 NETDRV_W8_F (Cfg9346, Cfg9346_Lock);
1169 udelay (10);
1170
1171 /* init Rx ring buffer DMA address */
1172 NETDRV_W32_F (RxBuf, tp->rx_ring_dma);
1173
1174 /* init Tx buffer DMA addresses */
1175 for (i = 0; i < NUM_TX_DESC; i++)
1176 NETDRV_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1177
1178 NETDRV_W32_F (RxMissed, 0);
1179
1180 netdrv_set_rx_mode (dev);
1181
1182 /* no early-rx interrupts */
1183 NETDRV_W16 (MultiIntr, NETDRV_R16 (MultiIntr) & MultiIntrClear);
1184
1185 /* make sure RxTx has started */
1186 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1187 CmdRxEnb | CmdTxEnb);
1188
1189 /* Enable all known interrupts by setting the interrupt mask. */
1190 NETDRV_W16_F (IntrMask, netdrv_intr_mask);
1191
1192 netif_start_queue (dev);
1193
1194 DPRINTK ("EXIT\n");
1195}
1196
1197
1198/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1199static void netdrv_init_ring (struct net_device *dev)
1200{
1201 struct netdrv_private *tp = dev->priv;
1202 int i;
1203
1204 DPRINTK ("ENTER\n");
1205
1206 tp->cur_rx = 0;
1207 atomic_set (&tp->cur_tx, 0);
1208 atomic_set (&tp->dirty_tx, 0);
1209
1210 for (i = 0; i < NUM_TX_DESC; i++) {
1211 tp->tx_info[i].skb = NULL;
1212 tp->tx_info[i].mapping = 0;
1213 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1214 }
1215
1216 DPRINTK ("EXIT\n");
1217}
1218
1219
1220static void netdrv_timer (unsigned long data)
1221{
1222 struct net_device *dev = (struct net_device *) data;
1223 struct netdrv_private *tp = dev->priv;
1224 void *ioaddr = tp->mmio_addr;
1225 int next_tick = 60 * HZ;
1226 int mii_lpa;
1227
1228 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1229
1230 if (!tp->duplex_lock && mii_lpa != 0xffff) {
1231 int duplex = (mii_lpa & LPA_100FULL)
1232 || (mii_lpa & 0x01C0) == 0x0040;
1233 if (tp->full_duplex != duplex) {
1234 tp->full_duplex = duplex;
1235 printk (KERN_INFO
1236 "%s: Setting %s-duplex based on MII #%d link"
1237 " partner ability of %4.4x.\n", dev->name,
1238 tp->full_duplex ? "full" : "half",
1239 tp->phys[0], mii_lpa);
1240 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1241 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1242 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1243 }
1244 }
1245
1246 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1247 dev->name, NETDRV_R16 (NWayLPAR));
1248 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x"
1249 " RxStatus %4.4x.\n", dev->name,
1250 NETDRV_R16 (IntrMask),
1251 NETDRV_R16 (IntrStatus),
1252 NETDRV_R32 (RxEarlyStatus));
1253 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1254 dev->name, NETDRV_R8 (Config0),
1255 NETDRV_R8 (Config1));
1256
1257 tp->timer.expires = jiffies + next_tick;
1258 add_timer (&tp->timer);
1259}
1260
1261
1262static void netdrv_tx_clear (struct netdrv_private *tp)
1263{
1264 int i;
1265
1266 atomic_set (&tp->cur_tx, 0);
1267 atomic_set (&tp->dirty_tx, 0);
1268
1269 /* Dump the unsent Tx packets. */
1270 for (i = 0; i < NUM_TX_DESC; i++) {
1271 struct ring_info *rp = &tp->tx_info[i];
1272 if (rp->mapping != 0) {
1273 pci_unmap_single (tp->pci_dev, rp->mapping,
1274 rp->skb->len, PCI_DMA_TODEVICE);
1275 rp->mapping = 0;
1276 }
1277 if (rp->skb) {
1278 dev_kfree_skb (rp->skb);
1279 rp->skb = NULL;
1280 tp->stats.tx_dropped++;
1281 }
1282 }
1283}
1284
1285
1286static void netdrv_tx_timeout (struct net_device *dev)
1287{
1288 struct netdrv_private *tp = dev->priv;
1289 void *ioaddr = tp->mmio_addr;
1290 int i;
1291 u8 tmp8;
1292 unsigned long flags;
1293
1294 DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
1295 "media %2.2x.\n", dev->name,
1296 NETDRV_R8 (ChipCmd),
1297 NETDRV_R16 (IntrStatus),
1298 NETDRV_R8 (MediaStatus));
1299
1300 /* disable Tx ASAP, if not already */
1301 tmp8 = NETDRV_R8 (ChipCmd);
1302 if (tmp8 & CmdTxEnb)
1303 NETDRV_W8 (ChipCmd, tmp8 & ~CmdTxEnb);
1304
1305 /* Disable interrupts by clearing the interrupt mask. */
1306 NETDRV_W16 (IntrMask, 0x0000);
1307
1308 /* Emit info to figure out what went wrong. */
1309 printk (KERN_DEBUG "%s: Tx queue start entry %d dirty entry %d.\n",
1310 dev->name, atomic_read (&tp->cur_tx),
1311 atomic_read (&tp->dirty_tx));
1312 for (i = 0; i < NUM_TX_DESC; i++)
1313 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1314 dev->name, i, NETDRV_R32 (TxStatus0 + (i * 4)),
1315 i == atomic_read (&tp->dirty_tx) % NUM_TX_DESC ?
1316 " (queue head)" : "");
1317
1318 /* Stop a shared interrupt from scavenging while we are. */
1319 spin_lock_irqsave (&tp->lock, flags);
6aa20a22 1320
1da177e4
LT		 1321 netdrv_tx_clear (tp);
1322
1323 spin_unlock_irqrestore (&tp->lock, flags);
1324
1325 /* ...and finally, reset everything */
1326 netdrv_hw_start (dev);
1327
1328 netif_wake_queue (dev);
1329}
1330
1331
1332
1333static int netdrv_start_xmit (struct sk_buff *skb, struct net_device *dev)
1334{
1335 struct netdrv_private *tp = dev->priv;
1336 void *ioaddr = tp->mmio_addr;
1337 int entry;
1338
1339 /* Calculate the next Tx descriptor entry. */
1340 entry = atomic_read (&tp->cur_tx) % NUM_TX_DESC;
1341
1342 assert (tp->tx_info[entry].skb == NULL);
1343 assert (tp->tx_info[entry].mapping == 0);
1344
1345 tp->tx_info[entry].skb = skb;
1346 /* tp->tx_info[entry].mapping = 0; */
1347 memcpy (tp->tx_buf[entry], skb->data, skb->len);
1348
1349 /* Note: the chip doesn't have auto-pad! */
1350 NETDRV_W32 (TxStatus0 + (entry * sizeof(u32)),
1351 tp->tx_flag | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1352
1353 dev->trans_start = jiffies;
1354 atomic_inc (&tp->cur_tx);
1355 if ((atomic_read (&tp->cur_tx) - atomic_read (&tp->dirty_tx)) >= NUM_TX_DESC)
1356 netif_stop_queue (dev);
1357
1358 DPRINTK ("%s: Queued Tx packet at %p size %u to slot %d.\n",
1359 dev->name, skb->data, skb->len, entry);
1360
1361 return 0;
1362}
1363
1364
1365static void netdrv_tx_interrupt (struct net_device *dev,
1366 struct netdrv_private *tp,
1367 void *ioaddr)
1368{
1369 int cur_tx, dirty_tx, tx_left;
1370
1371 assert (dev != NULL);
1372 assert (tp != NULL);
1373 assert (ioaddr != NULL);
1374
1375 dirty_tx = atomic_read (&tp->dirty_tx);
1376
1377 cur_tx = atomic_read (&tp->cur_tx);
1378 tx_left = cur_tx - dirty_tx;
1379 while (tx_left > 0) {
1380 int entry = dirty_tx % NUM_TX_DESC;
1381 int txstatus;
1382
1383 txstatus = NETDRV_R32 (TxStatus0 + (entry * sizeof (u32)));
1384
1385 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1386 break; /* It still hasn't been Txed */
1387
1388 /* Note: TxCarrierLost is always asserted at 100mbps. */
1389 if (txstatus & (TxOutOfWindow | TxAborted)) {
1390 /* There was an major error, log it. */
1391 DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
1392 dev->name, txstatus);
1393 tp->stats.tx_errors++;
1394 if (txstatus & TxAborted) {
1395 tp->stats.tx_aborted_errors++;
1396 NETDRV_W32 (TxConfig, TxClearAbt | (TX_DMA_BURST << TxDMAShift));
1397 }
1398 if (txstatus & TxCarrierLost)
1399 tp->stats.tx_carrier_errors++;
1400 if (txstatus & TxOutOfWindow)
1401 tp->stats.tx_window_errors++;
1402 } else {
1403 if (txstatus & TxUnderrun) {
1404 /* Add 64 to the Tx FIFO threshold. */
1405 if (tp->tx_flag < 0x00300000)
1406 tp->tx_flag += 0x00020000;
1407 tp->stats.tx_fifo_errors++;
1408 }
1409 tp->stats.collisions += (txstatus >> 24) & 15;
1410 tp->stats.tx_bytes += txstatus & 0x7ff;
1411 tp->stats.tx_packets++;
1412 }
1413
1414 /* Free the original skb. */
1415 if (tp->tx_info[entry].mapping != 0) {
1416 pci_unmap_single(tp->pci_dev,
1417 tp->tx_info[entry].mapping,
1418 tp->tx_info[entry].skb->len,
1419 PCI_DMA_TODEVICE);
1420 tp->tx_info[entry].mapping = 0;
1421 }
1422 dev_kfree_skb_irq (tp->tx_info[entry].skb);
1423 tp->tx_info[entry].skb = NULL;
1424 dirty_tx++;
1425 if (dirty_tx < 0) { /* handle signed int overflow */
1426 atomic_sub (cur_tx, &tp->cur_tx); /* XXX racy? */
1427 dirty_tx = cur_tx - tx_left + 1;
1428 }
1429 if (netif_queue_stopped (dev))
1430 netif_wake_queue (dev);
1431
1432 cur_tx = atomic_read (&tp->cur_tx);
1433 tx_left = cur_tx - dirty_tx;
1434
1435 }
1436
1437#ifndef NETDRV_NDEBUG
1438 if (atomic_read (&tp->cur_tx) - dirty_tx > NUM_TX_DESC) {
1439 printk (KERN_ERR
1440 "%s: Out-of-sync dirty pointer, %d vs. %d.\n",
1441 dev->name, dirty_tx, atomic_read (&tp->cur_tx));
1442 dirty_tx += NUM_TX_DESC;
1443 }
1444#endif /* NETDRV_NDEBUG */
1445
1446 atomic_set (&tp->dirty_tx, dirty_tx);
1447}
1448
1449
1450/* TODO: clean this up! Rx reset need not be this intensive */
1451static void netdrv_rx_err (u32 rx_status, struct net_device *dev,
1452 struct netdrv_private *tp, void *ioaddr)
1453{
1454 u8 tmp8;
1455 int tmp_work = 1000;
1456
1457 DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
1458 dev->name, rx_status);
1459 if (rx_status & RxTooLong) {
1460 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1461 dev->name, rx_status);
1462 /* A.C.: The chip hangs here. */
1463 }
1464 tp->stats.rx_errors++;
1465 if (rx_status & (RxBadSymbol | RxBadAlign))
1466 tp->stats.rx_frame_errors++;
1467 if (rx_status & (RxRunt | RxTooLong))
1468 tp->stats.rx_length_errors++;
1469 if (rx_status & RxCRCErr)
1470 tp->stats.rx_crc_errors++;
1471 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1472 tp->cur_rx = 0;
1473
1474 /* disable receive */
1475 tmp8 = NETDRV_R8 (ChipCmd) & ChipCmdClear;
1476 NETDRV_W8_F (ChipCmd, tmp8 | CmdTxEnb);
1477
1478 /* A.C.: Reset the multicast list. */
1479 netdrv_set_rx_mode (dev);
1480
1481 /* XXX potentially temporary hack to
1482 * restart hung receiver */
1483 while (--tmp_work > 0) {
1484 tmp8 = NETDRV_R8 (ChipCmd);
1485 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1486 break;
1487 NETDRV_W8_F (ChipCmd,
1488 (tmp8 & ChipCmdClear) | CmdRxEnb | CmdTxEnb);
1489 }
1490
1491 /* G.S.: Re-enable receiver */
1492 /* XXX temporary hack to work around receiver hang */
1493 netdrv_set_rx_mode (dev);
1494
1495 if (tmp_work <= 0)
1496 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1497}
1498
1499
1500/* The data sheet doesn't describe the Rx ring at all, so I'm guessing at the
1501 field alignments and semantics. */
1502static void netdrv_rx_interrupt (struct net_device *dev,
1503 struct netdrv_private *tp, void *ioaddr)
1504{
1505 unsigned char *rx_ring;
1506 u16 cur_rx;
1507
1508 assert (dev != NULL);
1509 assert (tp != NULL);
1510 assert (ioaddr != NULL);
1511
1512 rx_ring = tp->rx_ring;
1513 cur_rx = tp->cur_rx;
1514
1515 DPRINTK ("%s: In netdrv_rx(), current %4.4x BufAddr %4.4x,"
1516 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1517 NETDRV_R16 (RxBufAddr),
1518 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1519
1520 while ((NETDRV_R8 (ChipCmd) & RxBufEmpty) == 0) {
1521 int ring_offset = cur_rx % RX_BUF_LEN;
1522 u32 rx_status;
1523 unsigned int rx_size;
1524 unsigned int pkt_size;
1525 struct sk_buff *skb;
1526
1527 /* read size+status of next frame from DMA ring buffer */
1528 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1529 rx_size = rx_status >> 16;
1530 pkt_size = rx_size - 4;
1531
1532 DPRINTK ("%s: netdrv_rx() status %4.4x, size %4.4x,"
1533 " cur %4.4x.\n", dev->name, rx_status,
1534 rx_size, cur_rx);
1535#if NETDRV_DEBUG > 2
1536 {
1537 int i;
1538 DPRINTK ("%s: Frame contents ", dev->name);
1539 for (i = 0; i < 70; i++)
1540 printk (" %2.2x",
1541 rx_ring[ring_offset + i]);
1542 printk (".\n");
1543 }
1544#endif
1545
1546 /* If Rx err or invalid rx_size/rx_status received
1547 * (which happens if we get lost in the ring),
1548 * Rx process gets reset, so we abort any further
1549 * Rx processing.
1550 */
1551 if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1552 (!(rx_status & RxStatusOK))) {
1553 netdrv_rx_err (rx_status, dev, tp, ioaddr);
1554 return;
1555 }
1556
1557 /* Malloc up new buffer, compatible with net-2e. */
1558 /* Omit the four octet CRC from the length. */
1559
1560 /* TODO: consider allocating skb's outside of
1561 * interrupt context, both to speed interrupt processing,
1562 * and also to reduce the chances of having to
1563 * drop packets here under memory pressure.
1564 */
1565
1566 skb = dev_alloc_skb (pkt_size + 2);
1567 if (skb) {
1568 skb->dev = dev;
1569 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
1570
1571 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
1572 skb_put (skb, pkt_size);
1573
1574 skb->protocol = eth_type_trans (skb, dev);
1575 netif_rx (skb);
1576 dev->last_rx = jiffies;
1577 tp->stats.rx_bytes += pkt_size;
1578 tp->stats.rx_packets++;
1579 } else {
1580 printk (KERN_WARNING
1581 "%s: Memory squeeze, dropping packet.\n",
1582 dev->name);
1583 tp->stats.rx_dropped++;
1584 }
1585
1586 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1587 NETDRV_W16_F (RxBufPtr, cur_rx - 16);
1588 }
1589
1590 DPRINTK ("%s: Done netdrv_rx(), current %4.4x BufAddr %4.4x,"
1591 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1592 NETDRV_R16 (RxBufAddr),
1593 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1594
1595 tp->cur_rx = cur_rx;
1596}
1597
1598
1599static void netdrv_weird_interrupt (struct net_device *dev,
1600 struct netdrv_private *tp,
1601 void *ioaddr,
1602 int status, int link_changed)
1603{
1604 printk (KERN_DEBUG "%s: Abnormal interrupt, status %8.8x.\n",
1605 dev->name, status);
1606
1607 assert (dev != NULL);
1608 assert (tp != NULL);
1609 assert (ioaddr != NULL);
1610
1611 /* Update the error count. */
1612 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1613 NETDRV_W32 (RxMissed, 0);
1614
1615 if ((status & RxUnderrun) && link_changed &&
1616 (tp->drv_flags & HAS_LNK_CHNG)) {
1617 /* Really link-change on new chips. */
1618 int lpar = NETDRV_R16 (NWayLPAR);
1619 int duplex = (lpar & 0x0100) || (lpar & 0x01C0) == 0x0040
1620 || tp->duplex_lock;
1621 if (tp->full_duplex != duplex) {
1622 tp->full_duplex = duplex;
1623 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1624 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1625 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1626 }
1627 status &= ~RxUnderrun;
1628 }
1629
1630 /* XXX along with netdrv_rx_err, are we double-counting errors? */
1631 if (status &
1632 (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
1633 tp->stats.rx_errors++;
1634
1635 if (status & (PCSTimeout))
1636 tp->stats.rx_length_errors++;
1637 if (status & (RxUnderrun | RxFIFOOver))
1638 tp->stats.rx_fifo_errors++;
1639 if (status & RxOverflow) {
1640 tp->stats.rx_over_errors++;
1641 tp->cur_rx = NETDRV_R16 (RxBufAddr) % RX_BUF_LEN;
1642 NETDRV_W16_F (RxBufPtr, tp->cur_rx - 16);
1643 }
1644 if (status & PCIErr) {
1645 u16 pci_cmd_status;
1646 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
1647
1648 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
1649 dev->name, pci_cmd_status);
1650 }
1651}
1652
1653
1654/* The interrupt handler does all of the Rx thread work and cleans up
1655 after the Tx thread. */
7d12e780 1656static irqreturn_t netdrv_interrupt (int irq, void *dev_instance)
1da177e4
LT		 1657{
1658 struct net_device *dev = (struct net_device *) dev_instance;
1659 struct netdrv_private *tp = dev->priv;
1660 int boguscnt = max_interrupt_work;
1661 void *ioaddr = tp->mmio_addr;
1662 int status = 0, link_changed = 0; /* avoid bogus "uninit" warning */
1663 int handled = 0;
1664
1665 spin_lock (&tp->lock);
1666
1667 do {
1668 status = NETDRV_R16 (IntrStatus);
1669
1670 /* h/w no longer present (hotplug?) or major error, bail */
1671 if (status == 0xFFFF)
1672 break;
1673
1674 handled = 1;
1675 /* Acknowledge all of the current interrupt sources ASAP */
1676 NETDRV_W16_F (IntrStatus, status);
1677
1678 DPRINTK ("%s: interrupt status=%#4.4x new intstat=%#4.4x.\n",
1679 dev->name, status,
1680 NETDRV_R16 (IntrStatus));
1681
1682 if ((status &
1683 (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1684 RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
1685 break;
1686
1687 /* Check uncommon events with one test. */
1688 if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1689 RxFIFOOver | TxErr | RxErr))
1690 netdrv_weird_interrupt (dev, tp, ioaddr,
1691 status, link_changed);
1692
1693 if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver)) /* Rx interrupt */
1694 netdrv_rx_interrupt (dev, tp, ioaddr);
1695
1696 if (status & (TxOK | TxErr))
1697 netdrv_tx_interrupt (dev, tp, ioaddr);
1698
1699 boguscnt--;
1700 } while (boguscnt > 0);
1701
1702 if (boguscnt <= 0) {
1703 printk (KERN_WARNING
1704 "%s: Too much work at interrupt, "
1705 "IntrStatus=0x%4.4x.\n", dev->name,
1706 status);
1707
1708 /* Clear all interrupt sources. */
1709 NETDRV_W16 (IntrStatus, 0xffff);
1710 }
1711
1712 spin_unlock (&tp->lock);
1713
1714 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
1715 dev->name, NETDRV_R16 (IntrStatus));
1716 return IRQ_RETVAL(handled);
1717}
1718
1719
1720static int netdrv_close (struct net_device *dev)
1721{
1722 struct netdrv_private *tp = dev->priv;
1723 void *ioaddr = tp->mmio_addr;
1724 unsigned long flags;
1725
1726 DPRINTK ("ENTER\n");
1727
1728 netif_stop_queue (dev);
1729
1730 DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
1731 dev->name, NETDRV_R16 (IntrStatus));
1732
1733 del_timer_sync (&tp->timer);
1734
1735 spin_lock_irqsave (&tp->lock, flags);
1736
1737 /* Stop the chip's Tx and Rx DMA processes. */
1738 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1739
1740 /* Disable interrupts by clearing the interrupt mask. */
1741 NETDRV_W16 (IntrMask, 0x0000);
1742
1743 /* Update the error counts. */
1744 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1745 NETDRV_W32 (RxMissed, 0);
1746
1747 spin_unlock_irqrestore (&tp->lock, flags);
1748
1749 synchronize_irq ();
1750 free_irq (dev->irq, dev);
1751
1752 netdrv_tx_clear (tp);
1753
1754 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1755 tp->rx_ring, tp->rx_ring_dma);
1756 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1757 tp->tx_bufs, tp->tx_bufs_dma);
1758 tp->rx_ring = NULL;
1759 tp->tx_bufs = NULL;
1760
1761 /* Green! Put the chip in low-power mode. */
1762 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1763 NETDRV_W8 (Config1, 0x03);
1764 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1765
1766 DPRINTK ("EXIT\n");
1767 return 0;
1768}
1769
1770
1771static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1772{
1773 struct netdrv_private *tp = dev->priv;
1774 struct mii_ioctl_data *data = if_mii(rq);
1775 unsigned long flags;
1776 int rc = 0;
1777
1778 DPRINTK ("ENTER\n");
1779
1780 switch (cmd) {
1781 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1782 data->phy_id = tp->phys[0] & 0x3f;
1783 /* Fall Through */
1784
1785 case SIOCGMIIREG: /* Read MII PHY register. */
1786 spin_lock_irqsave (&tp->lock, flags);
1787 data->val_out = mdio_read (dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1788 spin_unlock_irqrestore (&tp->lock, flags);
1789 break;
1790
1791 case SIOCSMIIREG: /* Write MII PHY register. */
1792 if (!capable (CAP_NET_ADMIN)) {
1793 rc = -EPERM;
1794 break;
1795 }
1796
1797 spin_lock_irqsave (&tp->lock, flags);
1798 mdio_write (dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1799 spin_unlock_irqrestore (&tp->lock, flags);
1800 break;
1801
1802 default:
1803 rc = -EOPNOTSUPP;
1804 break;
1805 }
1806
1807 DPRINTK ("EXIT, returning %d\n", rc);
1808 return rc;
1809}
1810
1811
1812static struct net_device_stats *netdrv_get_stats (struct net_device *dev)
1813{
1814 struct netdrv_private *tp = dev->priv;
1815 void *ioaddr = tp->mmio_addr;
1816
1817 DPRINTK ("ENTER\n");
1818
1819 assert (tp != NULL);
1820
1821 if (netif_running(dev)) {
1822 unsigned long flags;
1823
1824 spin_lock_irqsave (&tp->lock, flags);
1825
1826 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1827 NETDRV_W32 (RxMissed, 0);
1828
1829 spin_unlock_irqrestore (&tp->lock, flags);
1830 }
1831
1832 DPRINTK ("EXIT\n");
1833 return &tp->stats;
1834}
1835
1836/* Set or clear the multicast filter for this adaptor.
1837 This routine is not state sensitive and need not be SMP locked. */
1838
1839static void netdrv_set_rx_mode (struct net_device *dev)
1840{
1841 struct netdrv_private *tp = dev->priv;
1842 void *ioaddr = tp->mmio_addr;
1843 u32 mc_filter[2]; /* Multicast hash filter */
1844 int i, rx_mode;
1845 u32 tmp;
1846
1847 DPRINTK ("ENTER\n");
1848
1849 DPRINTK ("%s: netdrv_set_rx_mode(%4.4x) done -- Rx config %8.8x.\n",
1850 dev->name, dev->flags, NETDRV_R32 (RxConfig));
1851
1852 /* Note: do not reorder, GCC is clever about common statements. */
1853 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 1854 rx_mode =
1855 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1856 AcceptAllPhys;
1857 mc_filter[1] = mc_filter[0] = 0xffffffff;
1858 } else if ((dev->mc_count > multicast_filter_limit)
1859 || (dev->flags & IFF_ALLMULTI)) {
1860 /* Too many to filter perfectly -- accept all multicasts. */
1861 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1862 mc_filter[1] = mc_filter[0] = 0xffffffff;
1863 } else {
1864 struct dev_mc_list *mclist;
1865 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1866 mc_filter[1] = mc_filter[0] = 0;
1867 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1868 i++, mclist = mclist->next) {
1869 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1870
1871 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1872 }
1873 }
1874
1875 /* if called from irq handler, lock already acquired */
1876 if (!in_irq ())
1877 spin_lock_irq (&tp->lock);
1878
1879 /* We can safely update without stopping the chip. */
1880 tmp = netdrv_rx_config | rx_mode |
1881 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1882 NETDRV_W32_F (RxConfig, tmp);
1883 NETDRV_W32_F (MAR0 + 0, mc_filter[0]);
1884 NETDRV_W32_F (MAR0 + 4, mc_filter[1]);
1885
1886 if (!in_irq ())
1887 spin_unlock_irq (&tp->lock);
1888
1889 DPRINTK ("EXIT\n");
1890}
1891
1892
1893#ifdef CONFIG_PM
1894
05adc3b7 1895static int netdrv_suspend (struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 1896{
1897 struct net_device *dev = pci_get_drvdata (pdev);
1898 struct netdrv_private *tp = dev->priv;
1899 void *ioaddr = tp->mmio_addr;
1900 unsigned long flags;
1901
1902 if (!netif_running(dev))
1903 return 0;
1904 netif_device_detach (dev);
1905
1906 spin_lock_irqsave (&tp->lock, flags);
1907
1908 /* Disable interrupts, stop Tx and Rx. */
1909 NETDRV_W16 (IntrMask, 0x0000);
1910 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1911
1912 /* Update the error counts. */
1913 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1914 NETDRV_W32 (RxMissed, 0);
1915
1916 spin_unlock_irqrestore (&tp->lock, flags);
1917
1918 pci_save_state (pdev);
1919 pci_set_power_state (pdev, PCI_D3hot);
1920
1921 return 0;
1922}
1923
1924
1925static int netdrv_resume (struct pci_dev *pdev)
1926{
1927 struct net_device *dev = pci_get_drvdata (pdev);
1928 struct netdrv_private *tp = dev->priv;
1929
1930 if (!netif_running(dev))
1931 return 0;
1932 pci_set_power_state (pdev, PCI_D0);
1933 pci_restore_state (pdev);
1934 netif_device_attach (dev);
1935 netdrv_hw_start (dev);
1936
1937 return 0;
1938}
1939
1940#endif /* CONFIG_PM */
1941
1942
1943static struct pci_driver netdrv_pci_driver = {
1944 .name = MODNAME,
1945 .id_table = netdrv_pci_tbl,
1946 .probe = netdrv_init_one,
1947 .remove = __devexit_p(netdrv_remove_one),
1948#ifdef CONFIG_PM
1949 .suspend = netdrv_suspend,
1950 .resume = netdrv_resume,
1951#endif /* CONFIG_PM */
1952};
1953
1954
1955static int __init netdrv_init_module (void)
1956{
1957/* when a module, this is printed whether or not devices are found in probe */
1958#ifdef MODULE
1959 printk(version);
1960#endif
29917620 1961 return pci_register_driver(&netdrv_pci_driver);
1da177e4
LT		 1962}
1963
1964
1965static void __exit netdrv_cleanup_module (void)
1966{
1967 pci_unregister_driver (&netdrv_pci_driver);
1968}
1969
1970
1971module_init(netdrv_init_module);
1972module_exit(netdrv_cleanup_module);
Clone of davem's net-next-2.6 tree