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drivers/net: avoid some skb->ip_summed initializations
[net-next-2.6.git] / drivers / net / niu.c
CommitLineData
a3138df9
DM		 1/* niu.c: Neptune ethernet driver.
2 *
be0c007a 3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
a3138df9
DM		 4 */
5
f10a1f2e
JP		 6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
a3138df9
DM		 8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/dma-mapping.h>
12#include <linux/netdevice.h>
13#include <linux/ethtool.h>
14#include <linux/etherdevice.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/bitops.h>
18#include <linux/mii.h>
19#include <linux/if_ether.h>
20#include <linux/if_vlan.h>
21#include <linux/ip.h>
22#include <linux/in.h>
23#include <linux/ipv6.h>
24#include <linux/log2.h>
25#include <linux/jiffies.h>
26#include <linux/crc32.h>
ccffad25 27#include <linux/list.h>
5a0e3ad6 28#include <linux/slab.h>
a3138df9
DM		 29
30#include <linux/io.h>
a3138df9 31#include <linux/of_device.h>
a3138df9
DM		 32
33#include "niu.h"
34
35#define DRV_MODULE_NAME "niu"
3cfa856d
DM		 36#define DRV_MODULE_VERSION "1.1"
37#define DRV_MODULE_RELDATE "Apr 22, 2010"
a3138df9
DM		 38
39static char version[] __devinitdata =
40 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
41
42MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43MODULE_DESCRIPTION("NIU ethernet driver");
44MODULE_LICENSE("GPL");
45MODULE_VERSION(DRV_MODULE_VERSION);
46
a3138df9
DM		 47#ifndef readq
48static u64 readq(void __iomem *reg)
49{
e23a59e1 50 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
a3138df9
DM		 51}
52
53static void writeq(u64 val, void __iomem *reg)
54{
55 writel(val & 0xffffffff, reg);
56 writel(val >> 32, reg + 0x4UL);
57}
58#endif
59
a3aa1884 60static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
a3138df9
DM		 61 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
62 {}
63};
64
65MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
66
67#define NIU_TX_TIMEOUT (5 * HZ)
68
69#define nr64(reg) readq(np->regs + (reg))
70#define nw64(reg, val) writeq((val), np->regs + (reg))
71
72#define nr64_mac(reg) readq(np->mac_regs + (reg))
73#define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
74
75#define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
76#define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
77
78#define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
79#define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
80
81#define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
82#define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
83
84#define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
85
86static int niu_debug;
87static int debug = -1;
88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "NIU debug level");
90
a3138df9
DM		 91#define niu_lock_parent(np, flags) \
92 spin_lock_irqsave(&np->parent->lock, flags)
93#define niu_unlock_parent(np, flags) \
94 spin_unlock_irqrestore(&np->parent->lock, flags)
95
5fbd7e24
MW		 96static int serdes_init_10g_serdes(struct niu *np);
97
a3138df9
DM		 98static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
99 u64 bits, int limit, int delay)
100{
101 while (--limit >= 0) {
102 u64 val = nr64_mac(reg);
103
104 if (!(val & bits))
105 break;
106 udelay(delay);
107 }
108 if (limit < 0)
109 return -ENODEV;
110 return 0;
111}
112
113static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
114 u64 bits, int limit, int delay,
115 const char *reg_name)
116{
117 int err;
118
119 nw64_mac(reg, bits);
120 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
121 if (err)
f10a1f2e
JP		 122 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
123 (unsigned long long)bits, reg_name,
124 (unsigned long long)nr64_mac(reg));
a3138df9
DM		 125 return err;
126}
127
128#define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
129({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
130 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
131})
132
133static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
134 u64 bits, int limit, int delay)
135{
136 while (--limit >= 0) {
137 u64 val = nr64_ipp(reg);
138
139 if (!(val & bits))
140 break;
141 udelay(delay);
142 }
143 if (limit < 0)
144 return -ENODEV;
145 return 0;
146}
147
148static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
149 u64 bits, int limit, int delay,
150 const char *reg_name)
151{
152 int err;
153 u64 val;
154
155 val = nr64_ipp(reg);
156 val |= bits;
157 nw64_ipp(reg, val);
158
159 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
160 if (err)
f10a1f2e
JP		 161 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
162 (unsigned long long)bits, reg_name,
163 (unsigned long long)nr64_ipp(reg));
a3138df9
DM		 164 return err;
165}
166
167#define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
168({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
169 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
170})
171
172static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
173 u64 bits, int limit, int delay)
174{
175 while (--limit >= 0) {
176 u64 val = nr64(reg);
177
178 if (!(val & bits))
179 break;
180 udelay(delay);
181 }
182 if (limit < 0)
183 return -ENODEV;
184 return 0;
185}
186
187#define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
188({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
189 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
190})
191
192static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
193 u64 bits, int limit, int delay,
194 const char *reg_name)
195{
196 int err;
197
198 nw64(reg, bits);
199 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
200 if (err)
f10a1f2e
JP		 201 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
202 (unsigned long long)bits, reg_name,
203 (unsigned long long)nr64(reg));
a3138df9
DM		 204 return err;
205}
206
207#define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
208({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
209 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
210})
211
212static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
213{
214 u64 val = (u64) lp->timer;
215
216 if (on)
217 val |= LDG_IMGMT_ARM;
218
219 nw64(LDG_IMGMT(lp->ldg_num), val);
220}
221
222static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
223{
224 unsigned long mask_reg, bits;
225 u64 val;
226
227 if (ldn < 0 || ldn > LDN_MAX)
228 return -EINVAL;
229
230 if (ldn < 64) {
231 mask_reg = LD_IM0(ldn);
232 bits = LD_IM0_MASK;
233 } else {
234 mask_reg = LD_IM1(ldn - 64);
235 bits = LD_IM1_MASK;
236 }
237
238 val = nr64(mask_reg);
239 if (on)
240 val &= ~bits;
241 else
242 val |= bits;
243 nw64(mask_reg, val);
244
245 return 0;
246}
247
248static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
249{
250 struct niu_parent *parent = np->parent;
251 int i;
252
253 for (i = 0; i <= LDN_MAX; i++) {
254 int err;
255
256 if (parent->ldg_map[i] != lp->ldg_num)
257 continue;
258
259 err = niu_ldn_irq_enable(np, i, on);
260 if (err)
261 return err;
262 }
263 return 0;
264}
265
266static int niu_enable_interrupts(struct niu *np, int on)
267{
268 int i;
269
270 for (i = 0; i < np->num_ldg; i++) {
271 struct niu_ldg *lp = &np->ldg[i];
272 int err;
273
274 err = niu_enable_ldn_in_ldg(np, lp, on);
275 if (err)
276 return err;
277 }
278 for (i = 0; i < np->num_ldg; i++)
279 niu_ldg_rearm(np, &np->ldg[i], on);
280
281 return 0;
282}
283
284static u32 phy_encode(u32 type, int port)
285{
286 return (type << (port * 2));
287}
288
289static u32 phy_decode(u32 val, int port)
290{
291 return (val >> (port * 2)) & PORT_TYPE_MASK;
292}
293
294static int mdio_wait(struct niu *np)
295{
296 int limit = 1000;
297 u64 val;
298
299 while (--limit > 0) {
300 val = nr64(MIF_FRAME_OUTPUT);
301 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
302 return val & MIF_FRAME_OUTPUT_DATA;
303
304 udelay(10);
305 }
306
307 return -ENODEV;
308}
309
310static int mdio_read(struct niu *np, int port, int dev, int reg)
311{
312 int err;
313
314 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
315 err = mdio_wait(np);
316 if (err < 0)
317 return err;
318
319 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
320 return mdio_wait(np);
321}
322
323static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
324{
325 int err;
326
327 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
328 err = mdio_wait(np);
329 if (err < 0)
330 return err;
331
332 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
333 err = mdio_wait(np);
334 if (err < 0)
335 return err;
336
337 return 0;
338}
339
340static int mii_read(struct niu *np, int port, int reg)
341{
342 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
343 return mdio_wait(np);
344}
345
346static int mii_write(struct niu *np, int port, int reg, int data)
347{
348 int err;
349
350 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
351 err = mdio_wait(np);
352 if (err < 0)
353 return err;
354
355 return 0;
356}
357
358static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
359{
360 int err;
361
362 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
363 ESR2_TI_PLL_TX_CFG_L(channel),
364 val & 0xffff);
365 if (!err)
366 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
367 ESR2_TI_PLL_TX_CFG_H(channel),
368 val >> 16);
369 return err;
370}
371
372static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
373{
374 int err;
375
376 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
377 ESR2_TI_PLL_RX_CFG_L(channel),
378 val & 0xffff);
379 if (!err)
380 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
381 ESR2_TI_PLL_RX_CFG_H(channel),
382 val >> 16);
383 return err;
384}
385
386/* Mode is always 10G fiber. */
e3e081e1 387static int serdes_init_niu_10g_fiber(struct niu *np)
a3138df9
DM		 388{
389 struct niu_link_config *lp = &np->link_config;
390 u32 tx_cfg, rx_cfg;
391 unsigned long i;
392
393 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
394 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
395 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
396 PLL_RX_CFG_EQ_LP_ADAPTIVE);
397
398 if (lp->loopback_mode == LOOPBACK_PHY) {
399 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
400
401 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
402 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
403
404 tx_cfg |= PLL_TX_CFG_ENTEST;
405 rx_cfg |= PLL_RX_CFG_ENTEST;
406 }
407
408 /* Initialize all 4 lanes of the SERDES. */
409 for (i = 0; i < 4; i++) {
410 int err = esr2_set_tx_cfg(np, i, tx_cfg);
411 if (err)
412 return err;
413 }
414
415 for (i = 0; i < 4; i++) {
416 int err = esr2_set_rx_cfg(np, i, rx_cfg);
417 if (err)
418 return err;
419 }
420
421 return 0;
422}
423
e3e081e1
SB		 424static int serdes_init_niu_1g_serdes(struct niu *np)
425{
426 struct niu_link_config *lp = &np->link_config;
427 u16 pll_cfg, pll_sts;
428 int max_retry = 100;
51e0f058 429 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 430 u32 tx_cfg, rx_cfg;
431 unsigned long i;
432 int err;
433
434 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
435 PLL_TX_CFG_RATE_HALF);
436 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
437 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
438 PLL_RX_CFG_RATE_HALF);
439
440 if (np->port == 0)
441 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
442
443 if (lp->loopback_mode == LOOPBACK_PHY) {
444 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
445
446 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
447 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
448
449 tx_cfg |= PLL_TX_CFG_ENTEST;
450 rx_cfg |= PLL_RX_CFG_ENTEST;
451 }
452
453 /* Initialize PLL for 1G */
454 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
455
456 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
457 ESR2_TI_PLL_CFG_L, pll_cfg);
458 if (err) {
f10a1f2e
JP		 459 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
460 np->port, __func__);
e3e081e1
SB		 461 return err;
462 }
463
464 pll_sts = PLL_CFG_ENPLL;
465
466 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
467 ESR2_TI_PLL_STS_L, pll_sts);
468 if (err) {
f10a1f2e
JP		 469 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
470 np->port, __func__);
e3e081e1
SB		 471 return err;
472 }
473
474 udelay(200);
475
476 /* Initialize all 4 lanes of the SERDES. */
477 for (i = 0; i < 4; i++) {
478 err = esr2_set_tx_cfg(np, i, tx_cfg);
479 if (err)
480 return err;
481 }
482
483 for (i = 0; i < 4; i++) {
484 err = esr2_set_rx_cfg(np, i, rx_cfg);
485 if (err)
486 return err;
487 }
488
489 switch (np->port) {
490 case 0:
491 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
492 mask = val;
493 break;
494
495 case 1:
496 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
497 mask = val;
498 break;
499
500 default:
501 return -EINVAL;
502 }
503
504 while (max_retry--) {
505 sig = nr64(ESR_INT_SIGNALS);
506 if ((sig & mask) == val)
507 break;
508
509 mdelay(500);
510 }
511
512 if ((sig & mask) != val) {
f10a1f2e
JP		 513 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
514 np->port, (int)(sig & mask), (int)val);
e3e081e1
SB		 515 return -ENODEV;
516 }
517
518 return 0;
519}
520
521static int serdes_init_niu_10g_serdes(struct niu *np)
522{
523 struct niu_link_config *lp = &np->link_config;
524 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
525 int max_retry = 100;
51e0f058 526 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 527 unsigned long i;
528 int err;
529
530 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
531 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
532 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
533 PLL_RX_CFG_EQ_LP_ADAPTIVE);
534
535 if (lp->loopback_mode == LOOPBACK_PHY) {
536 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
537
538 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
539 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
540
541 tx_cfg |= PLL_TX_CFG_ENTEST;
542 rx_cfg |= PLL_RX_CFG_ENTEST;
543 }
544
545 /* Initialize PLL for 10G */
546 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
547
548 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
549 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
550 if (err) {
f10a1f2e
JP		 551 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
552 np->port, __func__);
e3e081e1
SB		 553 return err;
554 }
555
556 pll_sts = PLL_CFG_ENPLL;
557
558 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
559 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
560 if (err) {
f10a1f2e
JP		 561 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
562 np->port, __func__);
e3e081e1
SB		 563 return err;
564 }
565
566 udelay(200);
567
568 /* Initialize all 4 lanes of the SERDES. */
569 for (i = 0; i < 4; i++) {
570 err = esr2_set_tx_cfg(np, i, tx_cfg);
571 if (err)
572 return err;
573 }
574
575 for (i = 0; i < 4; i++) {
576 err = esr2_set_rx_cfg(np, i, rx_cfg);
577 if (err)
578 return err;
579 }
580
581 /* check if serdes is ready */
582
583 switch (np->port) {
584 case 0:
585 mask = ESR_INT_SIGNALS_P0_BITS;
586 val = (ESR_INT_SRDY0_P0 |
587 ESR_INT_DET0_P0 |
588 ESR_INT_XSRDY_P0 |
589 ESR_INT_XDP_P0_CH3 |
590 ESR_INT_XDP_P0_CH2 |
591 ESR_INT_XDP_P0_CH1 |
592 ESR_INT_XDP_P0_CH0);
593 break;
594
595 case 1:
596 mask = ESR_INT_SIGNALS_P1_BITS;
597 val = (ESR_INT_SRDY0_P1 |
598 ESR_INT_DET0_P1 |
599 ESR_INT_XSRDY_P1 |
600 ESR_INT_XDP_P1_CH3 |
601 ESR_INT_XDP_P1_CH2 |
602 ESR_INT_XDP_P1_CH1 |
603 ESR_INT_XDP_P1_CH0);
604 break;
605
606 default:
607 return -EINVAL;
608 }
609
610 while (max_retry--) {
611 sig = nr64(ESR_INT_SIGNALS);
612 if ((sig & mask) == val)
613 break;
614
615 mdelay(500);
616 }
617
618 if ((sig & mask) != val) {
f10a1f2e
JP		 619 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
620 np->port, (int)(sig & mask), (int)val);
e3e081e1
SB		 621
622 /* 10G failed, try initializing at 1G */
623 err = serdes_init_niu_1g_serdes(np);
624 if (!err) {
625 np->flags &= ~NIU_FLAGS_10G;
626 np->mac_xcvr = MAC_XCVR_PCS;
627 } else {
f10a1f2e
JP		 628 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
629 np->port);
e3e081e1
SB		 630 return -ENODEV;
631 }
632 }
633 return 0;
634}
635
a3138df9
DM		 636static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
637{
638 int err;
639
640 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
641 if (err >= 0) {
642 *val = (err & 0xffff);
643 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
644 ESR_RXTX_CTRL_H(chan));
645 if (err >= 0)
646 *val |= ((err & 0xffff) << 16);
647 err = 0;
648 }
649 return err;
650}
651
652static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
653{
654 int err;
655
656 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
657 ESR_GLUE_CTRL0_L(chan));
658 if (err >= 0) {
659 *val = (err & 0xffff);
660 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
661 ESR_GLUE_CTRL0_H(chan));
662 if (err >= 0) {
663 *val |= ((err & 0xffff) << 16);
664 err = 0;
665 }
666 }
667 return err;
668}
669
670static int esr_read_reset(struct niu *np, u32 *val)
671{
672 int err;
673
674 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
675 ESR_RXTX_RESET_CTRL_L);
676 if (err >= 0) {
677 *val = (err & 0xffff);
678 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
679 ESR_RXTX_RESET_CTRL_H);
680 if (err >= 0) {
681 *val |= ((err & 0xffff) << 16);
682 err = 0;
683 }
684 }
685 return err;
686}
687
688static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
689{
690 int err;
691
692 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
693 ESR_RXTX_CTRL_L(chan), val & 0xffff);
694 if (!err)
695 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
696 ESR_RXTX_CTRL_H(chan), (val >> 16));
697 return err;
698}
699
700static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
701{
702 int err;
703
704 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
705 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
706 if (!err)
707 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
708 ESR_GLUE_CTRL0_H(chan), (val >> 16));
709 return err;
710}
711
712static int esr_reset(struct niu *np)
713{
f166400b 714 u32 uninitialized_var(reset);
a3138df9
DM		 715 int err;
716
717 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
718 ESR_RXTX_RESET_CTRL_L, 0x0000);
719 if (err)
720 return err;
721 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
722 ESR_RXTX_RESET_CTRL_H, 0xffff);
723 if (err)
724 return err;
725 udelay(200);
726
727 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
728 ESR_RXTX_RESET_CTRL_L, 0xffff);
729 if (err)
730 return err;
731 udelay(200);
732
733 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
734 ESR_RXTX_RESET_CTRL_H, 0x0000);
735 if (err)
736 return err;
737 udelay(200);
738
739 err = esr_read_reset(np, &reset);
740 if (err)
741 return err;
742 if (reset != 0) {
f10a1f2e
JP		 743 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
744 np->port, reset);
a3138df9
DM		 745 return -ENODEV;
746 }
747
748 return 0;
749}
750
751static int serdes_init_10g(struct niu *np)
752{
753 struct niu_link_config *lp = &np->link_config;
754 unsigned long ctrl_reg, test_cfg_reg, i;
755 u64 ctrl_val, test_cfg_val, sig, mask, val;
756 int err;
757
758 switch (np->port) {
759 case 0:
760 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
761 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
762 break;
763 case 1:
764 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
765 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
766 break;
767
768 default:
769 return -EINVAL;
770 }
771 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
772 ENET_SERDES_CTRL_SDET_1 |
773 ENET_SERDES_CTRL_SDET_2 |
774 ENET_SERDES_CTRL_SDET_3 |
775 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
776 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
777 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
778 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
779 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
780 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
781 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
783 test_cfg_val = 0;
784
785 if (lp->loopback_mode == LOOPBACK_PHY) {
786 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
787 ENET_SERDES_TEST_MD_0_SHIFT) |
788 (ENET_TEST_MD_PAD_LOOPBACK <<
789 ENET_SERDES_TEST_MD_1_SHIFT) |
790 (ENET_TEST_MD_PAD_LOOPBACK <<
791 ENET_SERDES_TEST_MD_2_SHIFT) |
792 (ENET_TEST_MD_PAD_LOOPBACK <<
793 ENET_SERDES_TEST_MD_3_SHIFT));
794 }
795
796 nw64(ctrl_reg, ctrl_val);
797 nw64(test_cfg_reg, test_cfg_val);
798
799 /* Initialize all 4 lanes of the SERDES. */
800 for (i = 0; i < 4; i++) {
801 u32 rxtx_ctrl, glue0;
802
803 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
804 if (err)
805 return err;
806 err = esr_read_glue0(np, i, &glue0);
807 if (err)
808 return err;
809
810 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
811 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
812 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
813
814 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
815 ESR_GLUE_CTRL0_THCNT |
816 ESR_GLUE_CTRL0_BLTIME);
817 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
818 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
819 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
820 (BLTIME_300_CYCLES <<
821 ESR_GLUE_CTRL0_BLTIME_SHIFT));
822
823 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
824 if (err)
825 return err;
826 err = esr_write_glue0(np, i, glue0);
827 if (err)
828 return err;
829 }
830
831 err = esr_reset(np);
832 if (err)
833 return err;
834
835 sig = nr64(ESR_INT_SIGNALS);
836 switch (np->port) {
837 case 0:
838 mask = ESR_INT_SIGNALS_P0_BITS;
839 val = (ESR_INT_SRDY0_P0 |
840 ESR_INT_DET0_P0 |
841 ESR_INT_XSRDY_P0 |
842 ESR_INT_XDP_P0_CH3 |
843 ESR_INT_XDP_P0_CH2 |
844 ESR_INT_XDP_P0_CH1 |
845 ESR_INT_XDP_P0_CH0);
846 break;
847
848 case 1:
849 mask = ESR_INT_SIGNALS_P1_BITS;
850 val = (ESR_INT_SRDY0_P1 |
851 ESR_INT_DET0_P1 |
852 ESR_INT_XSRDY_P1 |
853 ESR_INT_XDP_P1_CH3 |
854 ESR_INT_XDP_P1_CH2 |
855 ESR_INT_XDP_P1_CH1 |
856 ESR_INT_XDP_P1_CH0);
857 break;
858
859 default:
860 return -EINVAL;
861 }
862
863 if ((sig & mask) != val) {
a5d6ab56
MW		 864 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
865 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
866 return 0;
867 }
f10a1f2e
JP		 868 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
869 np->port, (int)(sig & mask), (int)val);
a3138df9
DM		 870 return -ENODEV;
871 }
a5d6ab56
MW		 872 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
873 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
a3138df9
DM		 874 return 0;
875}
876
877static int serdes_init_1g(struct niu *np)
878{
879 u64 val;
880
881 val = nr64(ENET_SERDES_1_PLL_CFG);
882 val &= ~ENET_SERDES_PLL_FBDIV2;
883 switch (np->port) {
884 case 0:
885 val |= ENET_SERDES_PLL_HRATE0;
886 break;
887 case 1:
888 val |= ENET_SERDES_PLL_HRATE1;
889 break;
890 case 2:
891 val |= ENET_SERDES_PLL_HRATE2;
892 break;
893 case 3:
894 val |= ENET_SERDES_PLL_HRATE3;
895 break;
896 default:
897 return -EINVAL;
898 }
899 nw64(ENET_SERDES_1_PLL_CFG, val);
900
901 return 0;
902}
903
5fbd7e24
MW		 904static int serdes_init_1g_serdes(struct niu *np)
905{
906 struct niu_link_config *lp = &np->link_config;
907 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
908 u64 ctrl_val, test_cfg_val, sig, mask, val;
909 int err;
910 u64 reset_val, val_rd;
911
912 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
913 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
914 ENET_SERDES_PLL_FBDIV0;
915 switch (np->port) {
916 case 0:
917 reset_val = ENET_SERDES_RESET_0;
918 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
919 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
920 pll_cfg = ENET_SERDES_0_PLL_CFG;
921 break;
922 case 1:
923 reset_val = ENET_SERDES_RESET_1;
924 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
925 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
926 pll_cfg = ENET_SERDES_1_PLL_CFG;
927 break;
928
929 default:
930 return -EINVAL;
931 }
932 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
933 ENET_SERDES_CTRL_SDET_1 |
934 ENET_SERDES_CTRL_SDET_2 |
935 ENET_SERDES_CTRL_SDET_3 |
936 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
937 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
938 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
939 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
940 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
941 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
942 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
944 test_cfg_val = 0;
945
946 if (lp->loopback_mode == LOOPBACK_PHY) {
947 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
948 ENET_SERDES_TEST_MD_0_SHIFT) |
949 (ENET_TEST_MD_PAD_LOOPBACK <<
950 ENET_SERDES_TEST_MD_1_SHIFT) |
951 (ENET_TEST_MD_PAD_LOOPBACK <<
952 ENET_SERDES_TEST_MD_2_SHIFT) |
953 (ENET_TEST_MD_PAD_LOOPBACK <<
954 ENET_SERDES_TEST_MD_3_SHIFT));
955 }
956
957 nw64(ENET_SERDES_RESET, reset_val);
958 mdelay(20);
959 val_rd = nr64(ENET_SERDES_RESET);
960 val_rd &= ~reset_val;
961 nw64(pll_cfg, val);
962 nw64(ctrl_reg, ctrl_val);
963 nw64(test_cfg_reg, test_cfg_val);
964 nw64(ENET_SERDES_RESET, val_rd);
965 mdelay(2000);
966
967 /* Initialize all 4 lanes of the SERDES. */
968 for (i = 0; i < 4; i++) {
969 u32 rxtx_ctrl, glue0;
970
971 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
972 if (err)
973 return err;
974 err = esr_read_glue0(np, i, &glue0);
975 if (err)
976 return err;
977
978 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
979 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
980 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
981
982 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
983 ESR_GLUE_CTRL0_THCNT |
984 ESR_GLUE_CTRL0_BLTIME);
985 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
986 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
987 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
988 (BLTIME_300_CYCLES <<
989 ESR_GLUE_CTRL0_BLTIME_SHIFT));
990
991 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
992 if (err)
993 return err;
994 err = esr_write_glue0(np, i, glue0);
995 if (err)
996 return err;
997 }
998
999
1000 sig = nr64(ESR_INT_SIGNALS);
1001 switch (np->port) {
1002 case 0:
1003 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1004 mask = val;
1005 break;
1006
1007 case 1:
1008 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1009 mask = val;
1010 break;
1011
1012 default:
1013 return -EINVAL;
1014 }
1015
1016 if ((sig & mask) != val) {
f10a1f2e
JP		 1017 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1018 np->port, (int)(sig & mask), (int)val);
5fbd7e24
MW		 1019 return -ENODEV;
1020 }
1021
1022 return 0;
1023}
1024
1025static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1026{
1027 struct niu_link_config *lp = &np->link_config;
1028 int link_up;
1029 u64 val;
1030 u16 current_speed;
1031 unsigned long flags;
1032 u8 current_duplex;
1033
1034 link_up = 0;
1035 current_speed = SPEED_INVALID;
1036 current_duplex = DUPLEX_INVALID;
1037
1038 spin_lock_irqsave(&np->lock, flags);
1039
1040 val = nr64_pcs(PCS_MII_STAT);
1041
1042 if (val & PCS_MII_STAT_LINK_STATUS) {
1043 link_up = 1;
1044 current_speed = SPEED_1000;
1045 current_duplex = DUPLEX_FULL;
1046 }
1047
1048 lp->active_speed = current_speed;
1049 lp->active_duplex = current_duplex;
1050 spin_unlock_irqrestore(&np->lock, flags);
1051
1052 *link_up_p = link_up;
1053 return 0;
1054}
1055
5fbd7e24
MW		 1056static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1057{
1058 unsigned long flags;
1059 struct niu_link_config *lp = &np->link_config;
1060 int link_up = 0;
1061 int link_ok = 1;
1062 u64 val, val2;
1063 u16 current_speed;
1064 u8 current_duplex;
1065
1066 if (!(np->flags & NIU_FLAGS_10G))
1067 return link_status_1g_serdes(np, link_up_p);
1068
1069 current_speed = SPEED_INVALID;
1070 current_duplex = DUPLEX_INVALID;
1071 spin_lock_irqsave(&np->lock, flags);
1072
1073 val = nr64_xpcs(XPCS_STATUS(0));
1074 val2 = nr64_mac(XMAC_INTER2);
1075 if (val2 & 0x01000000)
1076 link_ok = 0;
1077
1078 if ((val & 0x1000ULL) && link_ok) {
1079 link_up = 1;
1080 current_speed = SPEED_10000;
1081 current_duplex = DUPLEX_FULL;
1082 }
1083 lp->active_speed = current_speed;
1084 lp->active_duplex = current_duplex;
1085 spin_unlock_irqrestore(&np->lock, flags);
1086 *link_up_p = link_up;
1087 return 0;
1088}
1089
38bb045d
CB		 1090static int link_status_mii(struct niu *np, int *link_up_p)
1091{
1092 struct niu_link_config *lp = &np->link_config;
1093 int err;
1094 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1095 int supported, advertising, active_speed, active_duplex;
1096
1097 err = mii_read(np, np->phy_addr, MII_BMCR);
1098 if (unlikely(err < 0))
1099 return err;
1100 bmcr = err;
1101
1102 err = mii_read(np, np->phy_addr, MII_BMSR);
1103 if (unlikely(err < 0))
1104 return err;
1105 bmsr = err;
1106
1107 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1108 if (unlikely(err < 0))
1109 return err;
1110 advert = err;
1111
1112 err = mii_read(np, np->phy_addr, MII_LPA);
1113 if (unlikely(err < 0))
1114 return err;
1115 lpa = err;
1116
1117 if (likely(bmsr & BMSR_ESTATEN)) {
1118 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1119 if (unlikely(err < 0))
1120 return err;
1121 estatus = err;
1122
1123 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1124 if (unlikely(err < 0))
1125 return err;
1126 ctrl1000 = err;
1127
1128 err = mii_read(np, np->phy_addr, MII_STAT1000);
1129 if (unlikely(err < 0))
1130 return err;
1131 stat1000 = err;
1132 } else
1133 estatus = ctrl1000 = stat1000 = 0;
1134
1135 supported = 0;
1136 if (bmsr & BMSR_ANEGCAPABLE)
1137 supported |= SUPPORTED_Autoneg;
1138 if (bmsr & BMSR_10HALF)
1139 supported |= SUPPORTED_10baseT_Half;
1140 if (bmsr & BMSR_10FULL)
1141 supported |= SUPPORTED_10baseT_Full;
1142 if (bmsr & BMSR_100HALF)
1143 supported |= SUPPORTED_100baseT_Half;
1144 if (bmsr & BMSR_100FULL)
1145 supported |= SUPPORTED_100baseT_Full;
1146 if (estatus & ESTATUS_1000_THALF)
1147 supported |= SUPPORTED_1000baseT_Half;
1148 if (estatus & ESTATUS_1000_TFULL)
1149 supported |= SUPPORTED_1000baseT_Full;
1150 lp->supported = supported;
1151
1152 advertising = 0;
1153 if (advert & ADVERTISE_10HALF)
1154 advertising |= ADVERTISED_10baseT_Half;
1155 if (advert & ADVERTISE_10FULL)
1156 advertising |= ADVERTISED_10baseT_Full;
1157 if (advert & ADVERTISE_100HALF)
1158 advertising |= ADVERTISED_100baseT_Half;
1159 if (advert & ADVERTISE_100FULL)
1160 advertising |= ADVERTISED_100baseT_Full;
1161 if (ctrl1000 & ADVERTISE_1000HALF)
1162 advertising |= ADVERTISED_1000baseT_Half;
1163 if (ctrl1000 & ADVERTISE_1000FULL)
1164 advertising |= ADVERTISED_1000baseT_Full;
1165
1166 if (bmcr & BMCR_ANENABLE) {
1167 int neg, neg1000;
1168
1169 lp->active_autoneg = 1;
1170 advertising |= ADVERTISED_Autoneg;
1171
1172 neg = advert & lpa;
1173 neg1000 = (ctrl1000 << 2) & stat1000;
1174
1175 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1176 active_speed = SPEED_1000;
1177 else if (neg & LPA_100)
1178 active_speed = SPEED_100;
1179 else if (neg & (LPA_10HALF | LPA_10FULL))
1180 active_speed = SPEED_10;
1181 else
1182 active_speed = SPEED_INVALID;
1183
1184 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1185 active_duplex = DUPLEX_FULL;
1186 else if (active_speed != SPEED_INVALID)
1187 active_duplex = DUPLEX_HALF;
1188 else
1189 active_duplex = DUPLEX_INVALID;
1190 } else {
1191 lp->active_autoneg = 0;
1192
1193 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1194 active_speed = SPEED_1000;
1195 else if (bmcr & BMCR_SPEED100)
1196 active_speed = SPEED_100;
1197 else
1198 active_speed = SPEED_10;
1199
1200 if (bmcr & BMCR_FULLDPLX)
1201 active_duplex = DUPLEX_FULL;
1202 else
1203 active_duplex = DUPLEX_HALF;
1204 }
1205
1206 lp->active_advertising = advertising;
1207 lp->active_speed = active_speed;
1208 lp->active_duplex = active_duplex;
1209 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1210
1211 return 0;
1212}
1213
5fbd7e24
MW		 1214static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1215{
1216 struct niu_link_config *lp = &np->link_config;
1217 u16 current_speed, bmsr;
1218 unsigned long flags;
1219 u8 current_duplex;
1220 int err, link_up;
1221
1222 link_up = 0;
1223 current_speed = SPEED_INVALID;
1224 current_duplex = DUPLEX_INVALID;
1225
1226 spin_lock_irqsave(&np->lock, flags);
1227
1228 err = -EINVAL;
1229
1230 err = mii_read(np, np->phy_addr, MII_BMSR);
1231 if (err < 0)
1232 goto out;
1233
1234 bmsr = err;
1235 if (bmsr & BMSR_LSTATUS) {
1236 u16 adv, lpa, common, estat;
1237
1238 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1239 if (err < 0)
1240 goto out;
1241 adv = err;
1242
1243 err = mii_read(np, np->phy_addr, MII_LPA);
1244 if (err < 0)
1245 goto out;
1246 lpa = err;
1247
1248 common = adv & lpa;
1249
1250 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1251 if (err < 0)
1252 goto out;
1253 estat = err;
1254 link_up = 1;
1255 current_speed = SPEED_1000;
1256 current_duplex = DUPLEX_FULL;
1257
1258 }
1259 lp->active_speed = current_speed;
1260 lp->active_duplex = current_duplex;
1261 err = 0;
1262
1263out:
1264 spin_unlock_irqrestore(&np->lock, flags);
1265
1266 *link_up_p = link_up;
1267 return err;
1268}
1269
38bb045d
CB		 1270static int link_status_1g(struct niu *np, int *link_up_p)
1271{
1272 struct niu_link_config *lp = &np->link_config;
1273 unsigned long flags;
1274 int err;
1275
1276 spin_lock_irqsave(&np->lock, flags);
1277
1278 err = link_status_mii(np, link_up_p);
1279 lp->supported |= SUPPORTED_TP;
1280 lp->active_advertising |= ADVERTISED_TP;
1281
1282 spin_unlock_irqrestore(&np->lock, flags);
1283 return err;
1284}
1285
a3138df9
DM		 1286static int bcm8704_reset(struct niu *np)
1287{
1288 int err, limit;
1289
1290 err = mdio_read(np, np->phy_addr,
1291 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
9c5cd670 1292 if (err < 0 || err == 0xffff)
a3138df9
DM		 1293 return err;
1294 err |= BMCR_RESET;
1295 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1296 MII_BMCR, err);
1297 if (err)
1298 return err;
1299
1300 limit = 1000;
1301 while (--limit >= 0) {
1302 err = mdio_read(np, np->phy_addr,
1303 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1304 if (err < 0)
1305 return err;
1306 if (!(err & BMCR_RESET))
1307 break;
1308 }
1309 if (limit < 0) {
f10a1f2e
JP		 1310 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1311 np->port, (err & 0xffff));
a3138df9
DM		 1312 return -ENODEV;
1313 }
1314 return 0;
1315}
1316
1317/* When written, certain PHY registers need to be read back twice
1318 * in order for the bits to settle properly.
1319 */
1320static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1321{
1322 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1323 if (err < 0)
1324 return err;
1325 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1326 if (err < 0)
1327 return err;
1328 return 0;
1329}
1330
a5d6ab56
MW		 1331static int bcm8706_init_user_dev3(struct niu *np)
1332{
1333 int err;
1334
1335
1336 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1337 BCM8704_USER_OPT_DIGITAL_CTRL);
1338 if (err < 0)
1339 return err;
1340 err &= ~USER_ODIG_CTRL_GPIOS;
1341 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1342 err |= USER_ODIG_CTRL_RESV2;
1343 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1344 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1345 if (err)
1346 return err;
1347
1348 mdelay(1000);
1349
1350 return 0;
1351}
1352
a3138df9
DM		 1353static int bcm8704_init_user_dev3(struct niu *np)
1354{
1355 int err;
1356
1357 err = mdio_write(np, np->phy_addr,
1358 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1359 (USER_CONTROL_OPTXRST_LVL |
1360 USER_CONTROL_OPBIASFLT_LVL |
1361 USER_CONTROL_OBTMPFLT_LVL |
1362 USER_CONTROL_OPPRFLT_LVL |
1363 USER_CONTROL_OPTXFLT_LVL |
1364 USER_CONTROL_OPRXLOS_LVL |
1365 USER_CONTROL_OPRXFLT_LVL |
1366 USER_CONTROL_OPTXON_LVL |
1367 (0x3f << USER_CONTROL_RES1_SHIFT)));
1368 if (err)
1369 return err;
1370
1371 err = mdio_write(np, np->phy_addr,
1372 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1373 (USER_PMD_TX_CTL_XFP_CLKEN |
1374 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1375 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1376 USER_PMD_TX_CTL_TSCK_LPWREN));
1377 if (err)
1378 return err;
1379
1380 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1381 if (err)
1382 return err;
1383 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1384 if (err)
1385 return err;
1386
1387 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1388 BCM8704_USER_OPT_DIGITAL_CTRL);
1389 if (err < 0)
1390 return err;
1391 err &= ~USER_ODIG_CTRL_GPIOS;
1392 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1393 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1394 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1395 if (err)
1396 return err;
1397
1398 mdelay(1000);
1399
1400 return 0;
1401}
1402
b0de8e40
ML		 1403static int mrvl88x2011_act_led(struct niu *np, int val)
1404{
1405 int err;
1406
1407 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1408 MRVL88X2011_LED_8_TO_11_CTL);
1409 if (err < 0)
1410 return err;
1411
1412 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1413 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1414
1415 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1416 MRVL88X2011_LED_8_TO_11_CTL, err);
1417}
1418
1419static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1420{
1421 int err;
1422
1423 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1424 MRVL88X2011_LED_BLINK_CTL);
1425 if (err >= 0) {
1426 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1427 err |= (rate << 4);
1428
1429 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1430 MRVL88X2011_LED_BLINK_CTL, err);
1431 }
1432
1433 return err;
1434}
1435
1436static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1437{
1438 int err;
1439
1440 /* Set LED functions */
1441 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1442 if (err)
1443 return err;
1444
1445 /* led activity */
1446 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1447 if (err)
1448 return err;
1449
1450 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1451 MRVL88X2011_GENERAL_CTL);
1452 if (err < 0)
1453 return err;
1454
1455 err |= MRVL88X2011_ENA_XFPREFCLK;
1456
1457 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1458 MRVL88X2011_GENERAL_CTL, err);
1459 if (err < 0)
1460 return err;
1461
1462 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1463 MRVL88X2011_PMA_PMD_CTL_1);
1464 if (err < 0)
1465 return err;
1466
1467 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1468 err |= MRVL88X2011_LOOPBACK;
1469 else
1470 err &= ~MRVL88X2011_LOOPBACK;
1471
1472 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1473 MRVL88X2011_PMA_PMD_CTL_1, err);
1474 if (err < 0)
1475 return err;
1476
1477 /* Enable PMD */
1478 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1479 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1480}
1481
a5d6ab56
MW		 1482
1483static int xcvr_diag_bcm870x(struct niu *np)
a3138df9 1484{
a3138df9 1485 u16 analog_stat0, tx_alarm_status;
a5d6ab56 1486 int err = 0;
a3138df9
DM		 1487
1488#if 1
1489 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1490 MII_STAT1000);
1491 if (err < 0)
1492 return err;
f10a1f2e 1493 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
a3138df9
DM		 1494
1495 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1496 if (err < 0)
1497 return err;
f10a1f2e 1498 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
a3138df9
DM		 1499
1500 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1501 MII_NWAYTEST);
1502 if (err < 0)
1503 return err;
f10a1f2e 1504 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
a3138df9
DM		 1505#endif
1506
1507 /* XXX dig this out it might not be so useful XXX */
1508 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1509 BCM8704_USER_ANALOG_STATUS0);
1510 if (err < 0)
1511 return err;
1512 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1513 BCM8704_USER_ANALOG_STATUS0);
1514 if (err < 0)
1515 return err;
1516 analog_stat0 = err;
1517
1518 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1519 BCM8704_USER_TX_ALARM_STATUS);
1520 if (err < 0)
1521 return err;
1522 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1523 BCM8704_USER_TX_ALARM_STATUS);
1524 if (err < 0)
1525 return err;
1526 tx_alarm_status = err;
1527
1528 if (analog_stat0 != 0x03fc) {
1529 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
f10a1f2e
JP		 1530 pr_info("Port %u cable not connected or bad cable\n",
1531 np->port);
a3138df9 1532 } else if (analog_stat0 == 0x639c) {
f10a1f2e
JP		 1533 pr_info("Port %u optical module is bad or missing\n",
1534 np->port);
a3138df9
DM		 1535 }
1536 }
1537
1538 return 0;
1539}
1540
a5d6ab56
MW		 1541static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1542{
1543 struct niu_link_config *lp = &np->link_config;
1544 int err;
1545
1546 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1547 MII_BMCR);
1548 if (err < 0)
1549 return err;
1550
1551 err &= ~BMCR_LOOPBACK;
1552
1553 if (lp->loopback_mode == LOOPBACK_MAC)
1554 err |= BMCR_LOOPBACK;
1555
1556 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1557 MII_BMCR, err);
1558 if (err)
1559 return err;
1560
1561 return 0;
1562}
1563
1564static int xcvr_init_10g_bcm8706(struct niu *np)
1565{
1566 int err = 0;
1567 u64 val;
1568
1569 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1570 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1571 return err;
1572
1573 val = nr64_mac(XMAC_CONFIG);
1574 val &= ~XMAC_CONFIG_LED_POLARITY;
1575 val |= XMAC_CONFIG_FORCE_LED_ON;
1576 nw64_mac(XMAC_CONFIG, val);
1577
1578 val = nr64(MIF_CONFIG);
1579 val |= MIF_CONFIG_INDIRECT_MODE;
1580 nw64(MIF_CONFIG, val);
1581
1582 err = bcm8704_reset(np);
1583 if (err)
1584 return err;
1585
1586 err = xcvr_10g_set_lb_bcm870x(np);
1587 if (err)
1588 return err;
1589
1590 err = bcm8706_init_user_dev3(np);
1591 if (err)
1592 return err;
1593
1594 err = xcvr_diag_bcm870x(np);
1595 if (err)
1596 return err;
1597
1598 return 0;
1599}
1600
1601static int xcvr_init_10g_bcm8704(struct niu *np)
1602{
1603 int err;
1604
1605 err = bcm8704_reset(np);
1606 if (err)
1607 return err;
1608
1609 err = bcm8704_init_user_dev3(np);
1610 if (err)
1611 return err;
1612
1613 err = xcvr_10g_set_lb_bcm870x(np);
1614 if (err)
1615 return err;
1616
1617 err = xcvr_diag_bcm870x(np);
1618 if (err)
1619 return err;
1620
1621 return 0;
1622}
1623
b0de8e40
ML		 1624static int xcvr_init_10g(struct niu *np)
1625{
1626 int phy_id, err;
1627 u64 val;
1628
1629 val = nr64_mac(XMAC_CONFIG);
1630 val &= ~XMAC_CONFIG_LED_POLARITY;
1631 val |= XMAC_CONFIG_FORCE_LED_ON;
1632 nw64_mac(XMAC_CONFIG, val);
1633
1634 /* XXX shared resource, lock parent XXX */
1635 val = nr64(MIF_CONFIG);
1636 val |= MIF_CONFIG_INDIRECT_MODE;
1637 nw64(MIF_CONFIG, val);
1638
1639 phy_id = phy_decode(np->parent->port_phy, np->port);
1640 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1641
1642 /* handle different phy types */
1643 switch (phy_id & NIU_PHY_ID_MASK) {
1644 case NIU_PHY_ID_MRVL88X2011:
1645 err = xcvr_init_10g_mrvl88x2011(np);
1646 break;
1647
1648 default: /* bcom 8704 */
1649 err = xcvr_init_10g_bcm8704(np);
1650 break;
1651 }
1652
1653 return 0;
1654}
1655
a3138df9
DM		 1656static int mii_reset(struct niu *np)
1657{
1658 int limit, err;
1659
1660 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1661 if (err)
1662 return err;
1663
1664 limit = 1000;
1665 while (--limit >= 0) {
1666 udelay(500);
1667 err = mii_read(np, np->phy_addr, MII_BMCR);
1668 if (err < 0)
1669 return err;
1670 if (!(err & BMCR_RESET))
1671 break;
1672 }
1673 if (limit < 0) {
f10a1f2e
JP		 1674 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1675 np->port, err);
a3138df9
DM		 1676 return -ENODEV;
1677 }
1678
1679 return 0;
1680}
1681
5fbd7e24
MW		 1682static int xcvr_init_1g_rgmii(struct niu *np)
1683{
1684 int err;
1685 u64 val;
1686 u16 bmcr, bmsr, estat;
1687
1688 val = nr64(MIF_CONFIG);
1689 val &= ~MIF_CONFIG_INDIRECT_MODE;
1690 nw64(MIF_CONFIG, val);
1691
1692 err = mii_reset(np);
1693 if (err)
1694 return err;
1695
1696 err = mii_read(np, np->phy_addr, MII_BMSR);
1697 if (err < 0)
1698 return err;
1699 bmsr = err;
1700
1701 estat = 0;
1702 if (bmsr & BMSR_ESTATEN) {
1703 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1704 if (err < 0)
1705 return err;
1706 estat = err;
1707 }
1708
1709 bmcr = 0;
1710 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1711 if (err)
1712 return err;
1713
1714 if (bmsr & BMSR_ESTATEN) {
1715 u16 ctrl1000 = 0;
1716
1717 if (estat & ESTATUS_1000_TFULL)
1718 ctrl1000 |= ADVERTISE_1000FULL;
1719 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1720 if (err)
1721 return err;
1722 }
1723
1724 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1725
1726 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1727 if (err)
1728 return err;
1729
1730 err = mii_read(np, np->phy_addr, MII_BMCR);
1731 if (err < 0)
1732 return err;
1733 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1734
1735 err = mii_read(np, np->phy_addr, MII_BMSR);
1736 if (err < 0)
1737 return err;
1738
1739 return 0;
1740}
1741
a3138df9
DM		 1742static int mii_init_common(struct niu *np)
1743{
1744 struct niu_link_config *lp = &np->link_config;
1745 u16 bmcr, bmsr, adv, estat;
1746 int err;
1747
1748 err = mii_reset(np);
1749 if (err)
1750 return err;
1751
1752 err = mii_read(np, np->phy_addr, MII_BMSR);
1753 if (err < 0)
1754 return err;
1755 bmsr = err;
1756
1757 estat = 0;
1758 if (bmsr & BMSR_ESTATEN) {
1759 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1760 if (err < 0)
1761 return err;
1762 estat = err;
1763 }
1764
1765 bmcr = 0;
1766 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1767 if (err)
1768 return err;
1769
1770 if (lp->loopback_mode == LOOPBACK_MAC) {
1771 bmcr |= BMCR_LOOPBACK;
1772 if (lp->active_speed == SPEED_1000)
1773 bmcr |= BMCR_SPEED1000;
1774 if (lp->active_duplex == DUPLEX_FULL)
1775 bmcr |= BMCR_FULLDPLX;
1776 }
1777
1778 if (lp->loopback_mode == LOOPBACK_PHY) {
1779 u16 aux;
1780
1781 aux = (BCM5464R_AUX_CTL_EXT_LB |
1782 BCM5464R_AUX_CTL_WRITE_1);
1783 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1784 if (err)
1785 return err;
1786 }
1787
38bb045d
CB		 1788 if (lp->autoneg) {
1789 u16 ctrl1000;
1790
1791 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1792 if ((bmsr & BMSR_10HALF) &&
1793 (lp->advertising & ADVERTISED_10baseT_Half))
1794 adv |= ADVERTISE_10HALF;
1795 if ((bmsr & BMSR_10FULL) &&
1796 (lp->advertising & ADVERTISED_10baseT_Full))
1797 adv |= ADVERTISE_10FULL;
1798 if ((bmsr & BMSR_100HALF) &&
1799 (lp->advertising & ADVERTISED_100baseT_Half))
1800 adv |= ADVERTISE_100HALF;
1801 if ((bmsr & BMSR_100FULL) &&
1802 (lp->advertising & ADVERTISED_100baseT_Full))
1803 adv |= ADVERTISE_100FULL;
1804 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
a3138df9
DM		 1805 if (err)
1806 return err;
38bb045d
CB		 1807
1808 if (likely(bmsr & BMSR_ESTATEN)) {
1809 ctrl1000 = 0;
1810 if ((estat & ESTATUS_1000_THALF) &&
1811 (lp->advertising & ADVERTISED_1000baseT_Half))
1812 ctrl1000 |= ADVERTISE_1000HALF;
1813 if ((estat & ESTATUS_1000_TFULL) &&
1814 (lp->advertising & ADVERTISED_1000baseT_Full))
1815 ctrl1000 |= ADVERTISE_1000FULL;
1816 err = mii_write(np, np->phy_addr,
1817 MII_CTRL1000, ctrl1000);
1818 if (err)
1819 return err;
1820 }
1821
1822 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1823 } else {
1824 /* !lp->autoneg */
1825 int fulldpx;
1826
1827 if (lp->duplex == DUPLEX_FULL) {
1828 bmcr |= BMCR_FULLDPLX;
1829 fulldpx = 1;
1830 } else if (lp->duplex == DUPLEX_HALF)
1831 fulldpx = 0;
1832 else
1833 return -EINVAL;
1834
1835 if (lp->speed == SPEED_1000) {
1836 /* if X-full requested while not supported, or
1837 X-half requested while not supported... */
1838 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1839 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1840 return -EINVAL;
1841 bmcr |= BMCR_SPEED1000;
1842 } else if (lp->speed == SPEED_100) {
1843 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1844 (!fulldpx && !(bmsr & BMSR_100HALF)))
1845 return -EINVAL;
1846 bmcr |= BMCR_SPEED100;
1847 } else if (lp->speed == SPEED_10) {
1848 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1849 (!fulldpx && !(bmsr & BMSR_10HALF)))
1850 return -EINVAL;
1851 } else
1852 return -EINVAL;
a3138df9 1853 }
a3138df9
DM		 1854
1855 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1856 if (err)
1857 return err;
1858
38bb045d 1859#if 0
a3138df9
DM		 1860 err = mii_read(np, np->phy_addr, MII_BMCR);
1861 if (err < 0)
1862 return err;
38bb045d
CB		 1863 bmcr = err;
1864
a3138df9
DM		 1865 err = mii_read(np, np->phy_addr, MII_BMSR);
1866 if (err < 0)
1867 return err;
38bb045d
CB		 1868 bmsr = err;
1869
f10a1f2e 1870 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
a3138df9
DM		 1871 np->port, bmcr, bmsr);
1872#endif
1873
1874 return 0;
1875}
1876
1877static int xcvr_init_1g(struct niu *np)
1878{
1879 u64 val;
1880
1881 /* XXX shared resource, lock parent XXX */
1882 val = nr64(MIF_CONFIG);
1883 val &= ~MIF_CONFIG_INDIRECT_MODE;
1884 nw64(MIF_CONFIG, val);
1885
1886 return mii_init_common(np);
1887}
1888
1889static int niu_xcvr_init(struct niu *np)
1890{
1891 const struct niu_phy_ops *ops = np->phy_ops;
1892 int err;
1893
1894 err = 0;
1895 if (ops->xcvr_init)
1896 err = ops->xcvr_init(np);
1897
1898 return err;
1899}
1900
1901static int niu_serdes_init(struct niu *np)
1902{
1903 const struct niu_phy_ops *ops = np->phy_ops;
1904 int err;
1905
1906 err = 0;
1907 if (ops->serdes_init)
1908 err = ops->serdes_init(np);
1909
1910 return err;
1911}
1912
1913static void niu_init_xif(struct niu *);
0c3b091b 1914static void niu_handle_led(struct niu *, int status);
a3138df9
DM		 1915
1916static int niu_link_status_common(struct niu *np, int link_up)
1917{
1918 struct niu_link_config *lp = &np->link_config;
1919 struct net_device *dev = np->dev;
1920 unsigned long flags;
1921
1922 if (!netif_carrier_ok(dev) && link_up) {
f10a1f2e
JP		 1923 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1924 lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1925 lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1926 lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1927 "10Mbit/sec",
1928 lp->active_duplex == DUPLEX_FULL ? "full" : "half");
a3138df9
DM		 1929
1930 spin_lock_irqsave(&np->lock, flags);
1931 niu_init_xif(np);
0c3b091b 1932 niu_handle_led(np, 1);
a3138df9
DM		 1933 spin_unlock_irqrestore(&np->lock, flags);
1934
1935 netif_carrier_on(dev);
1936 } else if (netif_carrier_ok(dev) && !link_up) {
f10a1f2e 1937 netif_warn(np, link, dev, "Link is down\n");
0c3b091b
ML		 1938 spin_lock_irqsave(&np->lock, flags);
1939 niu_handle_led(np, 0);
1940 spin_unlock_irqrestore(&np->lock, flags);
a3138df9
DM		 1941 netif_carrier_off(dev);
1942 }
1943
1944 return 0;
1945}
1946
b0de8e40 1947static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
a3138df9 1948{
b0de8e40 1949 int err, link_up, pma_status, pcs_status;
a3138df9
DM		 1950
1951 link_up = 0;
1952
b0de8e40
ML		 1953 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1954 MRVL88X2011_10G_PMD_STATUS_2);
1955 if (err < 0)
1956 goto out;
a3138df9 1957
b0de8e40
ML		 1958 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1959 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1960 MRVL88X2011_PMA_PMD_STATUS_1);
1961 if (err < 0)
1962 goto out;
1963
1964 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1965
1966 /* Check PMC Register : 3.0001.2 == 1: read twice */
1967 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1968 MRVL88X2011_PMA_PMD_STATUS_1);
1969 if (err < 0)
1970 goto out;
1971
1972 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1973 MRVL88X2011_PMA_PMD_STATUS_1);
1974 if (err < 0)
1975 goto out;
1976
1977 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1978
1979 /* Check XGXS Register : 4.0018.[0-3,12] */
1980 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1981 MRVL88X2011_10G_XGXS_LANE_STAT);
1982 if (err < 0)
a3138df9
DM		 1983 goto out;
1984
b0de8e40
ML		 1985 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1986 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1987 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1988 0x800))
1989 link_up = (pma_status && pcs_status) ? 1 : 0;
1990
1991 np->link_config.active_speed = SPEED_10000;
1992 np->link_config.active_duplex = DUPLEX_FULL;
1993 err = 0;
1994out:
1995 mrvl88x2011_act_led(np, (link_up ?
1996 MRVL88X2011_LED_CTL_PCS_ACT :
1997 MRVL88X2011_LED_CTL_OFF));
1998
1999 *link_up_p = link_up;
2000 return err;
2001}
2002
a5d6ab56
MW		 2003static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2004{
2005 int err, link_up;
2006 link_up = 0;
2007
2008 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2009 BCM8704_PMD_RCV_SIGDET);
9c5cd670 2010 if (err < 0 || err == 0xffff)
a5d6ab56
MW		 2011 goto out;
2012 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2013 err = 0;
2014 goto out;
2015 }
2016
2017 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2018 BCM8704_PCS_10G_R_STATUS);
2019 if (err < 0)
2020 goto out;
2021
2022 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2023 err = 0;
2024 goto out;
2025 }
2026
2027 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2028 BCM8704_PHYXS_XGXS_LANE_STAT);
2029 if (err < 0)
2030 goto out;
2031 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2032 PHYXS_XGXS_LANE_STAT_MAGIC |
2033 PHYXS_XGXS_LANE_STAT_PATTEST |
2034 PHYXS_XGXS_LANE_STAT_LANE3 |
2035 PHYXS_XGXS_LANE_STAT_LANE2 |
2036 PHYXS_XGXS_LANE_STAT_LANE1 |
2037 PHYXS_XGXS_LANE_STAT_LANE0)) {
2038 err = 0;
2039 np->link_config.active_speed = SPEED_INVALID;
2040 np->link_config.active_duplex = DUPLEX_INVALID;
2041 goto out;
2042 }
2043
2044 link_up = 1;
2045 np->link_config.active_speed = SPEED_10000;
2046 np->link_config.active_duplex = DUPLEX_FULL;
2047 err = 0;
2048
2049out:
2050 *link_up_p = link_up;
a5d6ab56
MW		 2051 return err;
2052}
2053
b0de8e40
ML		 2054static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2055{
2056 int err, link_up;
2057
2058 link_up = 0;
2059
a3138df9
DM		 2060 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2061 BCM8704_PMD_RCV_SIGDET);
2062 if (err < 0)
2063 goto out;
2064 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2065 err = 0;
2066 goto out;
2067 }
2068
2069 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2070 BCM8704_PCS_10G_R_STATUS);
2071 if (err < 0)
2072 goto out;
2073 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2074 err = 0;
2075 goto out;
2076 }
2077
2078 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2079 BCM8704_PHYXS_XGXS_LANE_STAT);
2080 if (err < 0)
2081 goto out;
2082
2083 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2084 PHYXS_XGXS_LANE_STAT_MAGIC |
2085 PHYXS_XGXS_LANE_STAT_LANE3 |
2086 PHYXS_XGXS_LANE_STAT_LANE2 |
2087 PHYXS_XGXS_LANE_STAT_LANE1 |
2088 PHYXS_XGXS_LANE_STAT_LANE0)) {
2089 err = 0;
2090 goto out;
2091 }
2092
2093 link_up = 1;
2094 np->link_config.active_speed = SPEED_10000;
2095 np->link_config.active_duplex = DUPLEX_FULL;
2096 err = 0;
2097
2098out:
b0de8e40
ML		 2099 *link_up_p = link_up;
2100 return err;
2101}
2102
2103static int link_status_10g(struct niu *np, int *link_up_p)
2104{
2105 unsigned long flags;
2106 int err = -EINVAL;
2107
2108 spin_lock_irqsave(&np->lock, flags);
2109
2110 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2111 int phy_id;
2112
2113 phy_id = phy_decode(np->parent->port_phy, np->port);
2114 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2115
2116 /* handle different phy types */
2117 switch (phy_id & NIU_PHY_ID_MASK) {
2118 case NIU_PHY_ID_MRVL88X2011:
2119 err = link_status_10g_mrvl(np, link_up_p);
2120 break;
2121
2122 default: /* bcom 8704 */
2123 err = link_status_10g_bcom(np, link_up_p);
2124 break;
2125 }
2126 }
2127
a3138df9
DM		 2128 spin_unlock_irqrestore(&np->lock, flags);
2129
a3138df9
DM		 2130 return err;
2131}
2132
a5d6ab56
MW		 2133static int niu_10g_phy_present(struct niu *np)
2134{
2135 u64 sig, mask, val;
2136
2137 sig = nr64(ESR_INT_SIGNALS);
2138 switch (np->port) {
2139 case 0:
2140 mask = ESR_INT_SIGNALS_P0_BITS;
2141 val = (ESR_INT_SRDY0_P0 |
2142 ESR_INT_DET0_P0 |
2143 ESR_INT_XSRDY_P0 |
2144 ESR_INT_XDP_P0_CH3 |
2145 ESR_INT_XDP_P0_CH2 |
2146 ESR_INT_XDP_P0_CH1 |
2147 ESR_INT_XDP_P0_CH0);
2148 break;
2149
2150 case 1:
2151 mask = ESR_INT_SIGNALS_P1_BITS;
2152 val = (ESR_INT_SRDY0_P1 |
2153 ESR_INT_DET0_P1 |
2154 ESR_INT_XSRDY_P1 |
2155 ESR_INT_XDP_P1_CH3 |
2156 ESR_INT_XDP_P1_CH2 |
2157 ESR_INT_XDP_P1_CH1 |
2158 ESR_INT_XDP_P1_CH0);
2159 break;
2160
2161 default:
2162 return 0;
2163 }
2164
2165 if ((sig & mask) != val)
2166 return 0;
2167 return 1;
2168}
2169
2170static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2171{
2172 unsigned long flags;
2173 int err = 0;
2174 int phy_present;
2175 int phy_present_prev;
2176
2177 spin_lock_irqsave(&np->lock, flags);
2178
2179 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2180 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2181 1 : 0;
2182 phy_present = niu_10g_phy_present(np);
2183 if (phy_present != phy_present_prev) {
2184 /* state change */
2185 if (phy_present) {
9c5cd670 2186 /* A NEM was just plugged in */
a5d6ab56
MW		 2187 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2188 if (np->phy_ops->xcvr_init)
2189 err = np->phy_ops->xcvr_init(np);
2190 if (err) {
9c5cd670
TC		 2191 err = mdio_read(np, np->phy_addr,
2192 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2193 if (err == 0xffff) {
2194 /* No mdio, back-to-back XAUI */
2195 goto out;
2196 }
a5d6ab56
MW		 2197 /* debounce */
2198 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2199 }
2200 } else {
2201 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2202 *link_up_p = 0;
f10a1f2e
JP		 2203 netif_warn(np, link, np->dev,
2204 "Hotplug PHY Removed\n");
a5d6ab56
MW		 2205 }
2206 }
9c5cd670
TC		 2207out:
2208 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
a5d6ab56 2209 err = link_status_10g_bcm8706(np, link_up_p);
9c5cd670
TC		 2210 if (err == 0xffff) {
2211 /* No mdio, back-to-back XAUI: it is C10NEM */
2212 *link_up_p = 1;
2213 np->link_config.active_speed = SPEED_10000;
2214 np->link_config.active_duplex = DUPLEX_FULL;
2215 }
2216 }
a5d6ab56
MW		 2217 }
2218
2219 spin_unlock_irqrestore(&np->lock, flags);
2220
9c5cd670 2221 return 0;
a5d6ab56
MW		 2222}
2223
a3138df9
DM		 2224static int niu_link_status(struct niu *np, int *link_up_p)
2225{
2226 const struct niu_phy_ops *ops = np->phy_ops;
2227 int err;
2228
2229 err = 0;
2230 if (ops->link_status)
2231 err = ops->link_status(np, link_up_p);
2232
2233 return err;
2234}
2235
2236static void niu_timer(unsigned long __opaque)
2237{
2238 struct niu *np = (struct niu *) __opaque;
2239 unsigned long off;
2240 int err, link_up;
2241
2242 err = niu_link_status(np, &link_up);
2243 if (!err)
2244 niu_link_status_common(np, link_up);
2245
2246 if (netif_carrier_ok(np->dev))
2247 off = 5 * HZ;
2248 else
2249 off = 1 * HZ;
2250 np->timer.expires = jiffies + off;
2251
2252 add_timer(&np->timer);
2253}
2254
5fbd7e24
MW		 2255static const struct niu_phy_ops phy_ops_10g_serdes = {
2256 .serdes_init = serdes_init_10g_serdes,
2257 .link_status = link_status_10g_serdes,
2258};
2259
e3e081e1
SB		 2260static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2261 .serdes_init = serdes_init_niu_10g_serdes,
2262 .link_status = link_status_10g_serdes,
2263};
2264
2265static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2266 .serdes_init = serdes_init_niu_1g_serdes,
2267 .link_status = link_status_1g_serdes,
2268};
2269
5fbd7e24
MW		 2270static const struct niu_phy_ops phy_ops_1g_rgmii = {
2271 .xcvr_init = xcvr_init_1g_rgmii,
2272 .link_status = link_status_1g_rgmii,
2273};
2274
a3138df9 2275static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
e3e081e1 2276 .serdes_init = serdes_init_niu_10g_fiber,
a3138df9
DM		 2277 .xcvr_init = xcvr_init_10g,
2278 .link_status = link_status_10g,
2279};
2280
2281static const struct niu_phy_ops phy_ops_10g_fiber = {
2282 .serdes_init = serdes_init_10g,
2283 .xcvr_init = xcvr_init_10g,
2284 .link_status = link_status_10g,
2285};
2286
a5d6ab56
MW		 2287static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2288 .serdes_init = serdes_init_10g,
2289 .xcvr_init = xcvr_init_10g_bcm8706,
2290 .link_status = link_status_10g_hotplug,
2291};
2292
9c5cd670
TC		 2293static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2294 .serdes_init = serdes_init_niu_10g_fiber,
2295 .xcvr_init = xcvr_init_10g_bcm8706,
2296 .link_status = link_status_10g_hotplug,
2297};
2298
a3138df9
DM		 2299static const struct niu_phy_ops phy_ops_10g_copper = {
2300 .serdes_init = serdes_init_10g,
2301 .link_status = link_status_10g, /* XXX */
2302};
2303
2304static const struct niu_phy_ops phy_ops_1g_fiber = {
2305 .serdes_init = serdes_init_1g,
2306 .xcvr_init = xcvr_init_1g,
2307 .link_status = link_status_1g,
2308};
2309
2310static const struct niu_phy_ops phy_ops_1g_copper = {
2311 .xcvr_init = xcvr_init_1g,
2312 .link_status = link_status_1g,
2313};
2314
2315struct niu_phy_template {
2316 const struct niu_phy_ops *ops;
2317 u32 phy_addr_base;
2318};
2319
e3e081e1 2320static const struct niu_phy_template phy_template_niu_10g_fiber = {
a3138df9
DM		 2321 .ops = &phy_ops_10g_fiber_niu,
2322 .phy_addr_base = 16,
2323};
2324
e3e081e1
SB		 2325static const struct niu_phy_template phy_template_niu_10g_serdes = {
2326 .ops = &phy_ops_10g_serdes_niu,
2327 .phy_addr_base = 0,
2328};
2329
2330static const struct niu_phy_template phy_template_niu_1g_serdes = {
2331 .ops = &phy_ops_1g_serdes_niu,
2332 .phy_addr_base = 0,
2333};
2334
a3138df9
DM		 2335static const struct niu_phy_template phy_template_10g_fiber = {
2336 .ops = &phy_ops_10g_fiber,
2337 .phy_addr_base = 8,
2338};
2339
a5d6ab56
MW		 2340static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2341 .ops = &phy_ops_10g_fiber_hotplug,
2342 .phy_addr_base = 8,
2343};
2344
9c5cd670
TC		 2345static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2346 .ops = &phy_ops_niu_10g_hotplug,
2347 .phy_addr_base = 8,
2348};
2349
a3138df9
DM		 2350static const struct niu_phy_template phy_template_10g_copper = {
2351 .ops = &phy_ops_10g_copper,
2352 .phy_addr_base = 10,
2353};
2354
2355static const struct niu_phy_template phy_template_1g_fiber = {
2356 .ops = &phy_ops_1g_fiber,
2357 .phy_addr_base = 0,
2358};
2359
2360static const struct niu_phy_template phy_template_1g_copper = {
2361 .ops = &phy_ops_1g_copper,
2362 .phy_addr_base = 0,
2363};
2364
5fbd7e24
MW		 2365static const struct niu_phy_template phy_template_1g_rgmii = {
2366 .ops = &phy_ops_1g_rgmii,
2367 .phy_addr_base = 0,
2368};
2369
2370static const struct niu_phy_template phy_template_10g_serdes = {
2371 .ops = &phy_ops_10g_serdes,
2372 .phy_addr_base = 0,
2373};
2374
2375static int niu_atca_port_num[4] = {
2376 0, 0, 11, 10
2377};
2378
2379static int serdes_init_10g_serdes(struct niu *np)
2380{
2381 struct niu_link_config *lp = &np->link_config;
2382 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2383 u64 ctrl_val, test_cfg_val, sig, mask, val;
5fbd7e24
MW		 2384 u64 reset_val;
2385
2386 switch (np->port) {
2387 case 0:
2388 reset_val = ENET_SERDES_RESET_0;
2389 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2390 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2391 pll_cfg = ENET_SERDES_0_PLL_CFG;
2392 break;
2393 case 1:
2394 reset_val = ENET_SERDES_RESET_1;
2395 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2396 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2397 pll_cfg = ENET_SERDES_1_PLL_CFG;
2398 break;
2399
2400 default:
2401 return -EINVAL;
2402 }
2403 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2404 ENET_SERDES_CTRL_SDET_1 |
2405 ENET_SERDES_CTRL_SDET_2 |
2406 ENET_SERDES_CTRL_SDET_3 |
2407 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2408 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2409 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2410 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2411 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2412 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2413 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2414 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2415 test_cfg_val = 0;
2416
2417 if (lp->loopback_mode == LOOPBACK_PHY) {
2418 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2419 ENET_SERDES_TEST_MD_0_SHIFT) |
2420 (ENET_TEST_MD_PAD_LOOPBACK <<
2421 ENET_SERDES_TEST_MD_1_SHIFT) |
2422 (ENET_TEST_MD_PAD_LOOPBACK <<
2423 ENET_SERDES_TEST_MD_2_SHIFT) |
2424 (ENET_TEST_MD_PAD_LOOPBACK <<
2425 ENET_SERDES_TEST_MD_3_SHIFT));
2426 }
2427
2428 esr_reset(np);
2429 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2430 nw64(ctrl_reg, ctrl_val);
2431 nw64(test_cfg_reg, test_cfg_val);
2432
2433 /* Initialize all 4 lanes of the SERDES. */
2434 for (i = 0; i < 4; i++) {
2435 u32 rxtx_ctrl, glue0;
7c34eb89 2436 int err;
5fbd7e24
MW		 2437
2438 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2439 if (err)
2440 return err;
2441 err = esr_read_glue0(np, i, &glue0);
2442 if (err)
2443 return err;
2444
2445 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2446 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2447 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2448
2449 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2450 ESR_GLUE_CTRL0_THCNT |
2451 ESR_GLUE_CTRL0_BLTIME);
2452 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2453 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2454 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2455 (BLTIME_300_CYCLES <<
2456 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2457
2458 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2459 if (err)
2460 return err;
2461 err = esr_write_glue0(np, i, glue0);
2462 if (err)
2463 return err;
2464 }
2465
2466
2467 sig = nr64(ESR_INT_SIGNALS);
2468 switch (np->port) {
2469 case 0:
2470 mask = ESR_INT_SIGNALS_P0_BITS;
2471 val = (ESR_INT_SRDY0_P0 |
2472 ESR_INT_DET0_P0 |
2473 ESR_INT_XSRDY_P0 |
2474 ESR_INT_XDP_P0_CH3 |
2475 ESR_INT_XDP_P0_CH2 |
2476 ESR_INT_XDP_P0_CH1 |
2477 ESR_INT_XDP_P0_CH0);
2478 break;
2479
2480 case 1:
2481 mask = ESR_INT_SIGNALS_P1_BITS;
2482 val = (ESR_INT_SRDY0_P1 |
2483 ESR_INT_DET0_P1 |
2484 ESR_INT_XSRDY_P1 |
2485 ESR_INT_XDP_P1_CH3 |
2486 ESR_INT_XDP_P1_CH2 |
2487 ESR_INT_XDP_P1_CH1 |
2488 ESR_INT_XDP_P1_CH0);
2489 break;
2490
2491 default:
2492 return -EINVAL;
2493 }
2494
2495 if ((sig & mask) != val) {
2496 int err;
2497 err = serdes_init_1g_serdes(np);
2498 if (!err) {
2499 np->flags &= ~NIU_FLAGS_10G;
2500 np->mac_xcvr = MAC_XCVR_PCS;
2501 } else {
f10a1f2e
JP		 2502 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2503 np->port);
5fbd7e24
MW		 2504 return -ENODEV;
2505 }
2506 }
2507
2508 return 0;
2509}
2510
a3138df9
DM		 2511static int niu_determine_phy_disposition(struct niu *np)
2512{
2513 struct niu_parent *parent = np->parent;
2514 u8 plat_type = parent->plat_type;
2515 const struct niu_phy_template *tp;
2516 u32 phy_addr_off = 0;
2517
2518 if (plat_type == PLAT_TYPE_NIU) {
e3e081e1
SB		 2519 switch (np->flags &
2520 (NIU_FLAGS_10G |
2521 NIU_FLAGS_FIBER |
2522 NIU_FLAGS_XCVR_SERDES)) {
2523 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2524 /* 10G Serdes */
2525 tp = &phy_template_niu_10g_serdes;
2526 break;
2527 case NIU_FLAGS_XCVR_SERDES:
2528 /* 1G Serdes */
2529 tp = &phy_template_niu_1g_serdes;
2530 break;
2531 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2532 /* 10G Fiber */
2533 default:
9c5cd670
TC		 2534 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2535 tp = &phy_template_niu_10g_hotplug;
2536 if (np->port == 0)
2537 phy_addr_off = 8;
2538 if (np->port == 1)
2539 phy_addr_off = 12;
2540 } else {
2541 tp = &phy_template_niu_10g_fiber;
2542 phy_addr_off += np->port;
2543 }
e3e081e1
SB		 2544 break;
2545 }
a3138df9 2546 } else {
5fbd7e24
MW		 2547 switch (np->flags &
2548 (NIU_FLAGS_10G |
2549 NIU_FLAGS_FIBER |
2550 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 2551 case 0:
2552 /* 1G copper */
2553 tp = &phy_template_1g_copper;
2554 if (plat_type == PLAT_TYPE_VF_P0)
2555 phy_addr_off = 10;
2556 else if (plat_type == PLAT_TYPE_VF_P1)
2557 phy_addr_off = 26;
2558
2559 phy_addr_off += (np->port ^ 0x3);
2560 break;
2561
2562 case NIU_FLAGS_10G:
2563 /* 10G copper */
e0d8496a 2564 tp = &phy_template_10g_copper;
a3138df9
DM		 2565 break;
2566
2567 case NIU_FLAGS_FIBER:
2568 /* 1G fiber */
2569 tp = &phy_template_1g_fiber;
2570 break;
2571
2572 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2573 /* 10G fiber */
2574 tp = &phy_template_10g_fiber;
2575 if (plat_type == PLAT_TYPE_VF_P0 ||
2576 plat_type == PLAT_TYPE_VF_P1)
2577 phy_addr_off = 8;
2578 phy_addr_off += np->port;
a5d6ab56
MW		 2579 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2580 tp = &phy_template_10g_fiber_hotplug;
2581 if (np->port == 0)
2582 phy_addr_off = 8;
2583 if (np->port == 1)
2584 phy_addr_off = 12;
2585 }
a3138df9
DM		 2586 break;
2587
5fbd7e24
MW		 2588 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2589 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2590 case NIU_FLAGS_XCVR_SERDES:
2591 switch(np->port) {
2592 case 0:
2593 case 1:
2594 tp = &phy_template_10g_serdes;
2595 break;
2596 case 2:
2597 case 3:
2598 tp = &phy_template_1g_rgmii;
2599 break;
2600 default:
2601 return -EINVAL;
2602 break;
2603 }
2604 phy_addr_off = niu_atca_port_num[np->port];
2605 break;
2606
a3138df9
DM		 2607 default:
2608 return -EINVAL;
2609 }
2610 }
2611
2612 np->phy_ops = tp->ops;
2613 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2614
2615 return 0;
2616}
2617
2618static int niu_init_link(struct niu *np)
2619{
2620 struct niu_parent *parent = np->parent;
2621 int err, ignore;
2622
2623 if (parent->plat_type == PLAT_TYPE_NIU) {
2624 err = niu_xcvr_init(np);
2625 if (err)
2626 return err;
2627 msleep(200);
2628 }
2629 err = niu_serdes_init(np);
9c5cd670 2630 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
a3138df9
DM		 2631 return err;
2632 msleep(200);
2633 err = niu_xcvr_init(np);
9c5cd670 2634 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
a3138df9
DM		 2635 niu_link_status(np, &ignore);
2636 return 0;
2637}
2638
2639static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2640{
2641 u16 reg0 = addr[4] << 8 | addr[5];
2642 u16 reg1 = addr[2] << 8 | addr[3];
2643 u16 reg2 = addr[0] << 8 | addr[1];
2644
2645 if (np->flags & NIU_FLAGS_XMAC) {
2646 nw64_mac(XMAC_ADDR0, reg0);
2647 nw64_mac(XMAC_ADDR1, reg1);
2648 nw64_mac(XMAC_ADDR2, reg2);
2649 } else {
2650 nw64_mac(BMAC_ADDR0, reg0);
2651 nw64_mac(BMAC_ADDR1, reg1);
2652 nw64_mac(BMAC_ADDR2, reg2);
2653 }
2654}
2655
2656static int niu_num_alt_addr(struct niu *np)
2657{
2658 if (np->flags & NIU_FLAGS_XMAC)
2659 return XMAC_NUM_ALT_ADDR;
2660 else
2661 return BMAC_NUM_ALT_ADDR;
2662}
2663
2664static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2665{
2666 u16 reg0 = addr[4] << 8 | addr[5];
2667 u16 reg1 = addr[2] << 8 | addr[3];
2668 u16 reg2 = addr[0] << 8 | addr[1];
2669
2670 if (index >= niu_num_alt_addr(np))
2671 return -EINVAL;
2672
2673 if (np->flags & NIU_FLAGS_XMAC) {
2674 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2675 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2676 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2677 } else {
2678 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2679 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2680 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2681 }
2682
2683 return 0;
2684}
2685
2686static int niu_enable_alt_mac(struct niu *np, int index, int on)
2687{
2688 unsigned long reg;
2689 u64 val, mask;
2690
2691 if (index >= niu_num_alt_addr(np))
2692 return -EINVAL;
2693
fa907895 2694 if (np->flags & NIU_FLAGS_XMAC) {
a3138df9 2695 reg = XMAC_ADDR_CMPEN;
fa907895
MW		 2696 mask = 1 << index;
2697 } else {
a3138df9 2698 reg = BMAC_ADDR_CMPEN;
fa907895
MW		 2699 mask = 1 << (index + 1);
2700 }
a3138df9
DM		 2701
2702 val = nr64_mac(reg);
2703 if (on)
2704 val |= mask;
2705 else
2706 val &= ~mask;
2707 nw64_mac(reg, val);
2708
2709 return 0;
2710}
2711
2712static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2713 int num, int mac_pref)
2714{
2715 u64 val = nr64_mac(reg);
2716 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2717 val |= num;
2718 if (mac_pref)
2719 val |= HOST_INFO_MPR;
2720 nw64_mac(reg, val);
2721}
2722
2723static int __set_rdc_table_num(struct niu *np,
2724 int xmac_index, int bmac_index,
2725 int rdc_table_num, int mac_pref)
2726{
2727 unsigned long reg;
2728
2729 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2730 return -EINVAL;
2731 if (np->flags & NIU_FLAGS_XMAC)
2732 reg = XMAC_HOST_INFO(xmac_index);
2733 else
2734 reg = BMAC_HOST_INFO(bmac_index);
2735 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2736 return 0;
2737}
2738
2739static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2740 int mac_pref)
2741{
2742 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2743}
2744
2745static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2746 int mac_pref)
2747{
2748 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2749}
2750
2751static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2752 int table_num, int mac_pref)
2753{
2754 if (idx >= niu_num_alt_addr(np))
2755 return -EINVAL;
2756 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2757}
2758
2759static u64 vlan_entry_set_parity(u64 reg_val)
2760{
2761 u64 port01_mask;
2762 u64 port23_mask;
2763
2764 port01_mask = 0x00ff;
2765 port23_mask = 0xff00;
2766
2767 if (hweight64(reg_val & port01_mask) & 1)
2768 reg_val |= ENET_VLAN_TBL_PARITY0;
2769 else
2770 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2771
2772 if (hweight64(reg_val & port23_mask) & 1)
2773 reg_val |= ENET_VLAN_TBL_PARITY1;
2774 else
2775 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2776
2777 return reg_val;
2778}
2779
2780static void vlan_tbl_write(struct niu *np, unsigned long index,
2781 int port, int vpr, int rdc_table)
2782{
2783 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2784
2785 reg_val &= ~((ENET_VLAN_TBL_VPR |
2786 ENET_VLAN_TBL_VLANRDCTBLN) <<
2787 ENET_VLAN_TBL_SHIFT(port));
2788 if (vpr)
2789 reg_val |= (ENET_VLAN_TBL_VPR <<
2790 ENET_VLAN_TBL_SHIFT(port));
2791 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2792
2793 reg_val = vlan_entry_set_parity(reg_val);
2794
2795 nw64(ENET_VLAN_TBL(index), reg_val);
2796}
2797
2798static void vlan_tbl_clear(struct niu *np)
2799{
2800 int i;
2801
2802 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2803 nw64(ENET_VLAN_TBL(i), 0);
2804}
2805
2806static int tcam_wait_bit(struct niu *np, u64 bit)
2807{
2808 int limit = 1000;
2809
2810 while (--limit > 0) {
2811 if (nr64(TCAM_CTL) & bit)
2812 break;
2813 udelay(1);
2814 }
d2a928e4 2815 if (limit <= 0)
a3138df9
DM		 2816 return -ENODEV;
2817
2818 return 0;
2819}
2820
2821static int tcam_flush(struct niu *np, int index)
2822{
2823 nw64(TCAM_KEY_0, 0x00);
2824 nw64(TCAM_KEY_MASK_0, 0xff);
2825 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2826
2827 return tcam_wait_bit(np, TCAM_CTL_STAT);
2828}
2829
2830#if 0
2831static int tcam_read(struct niu *np, int index,
2832 u64 *key, u64 *mask)
2833{
2834 int err;
2835
2836 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2837 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2838 if (!err) {
2839 key[0] = nr64(TCAM_KEY_0);
2840 key[1] = nr64(TCAM_KEY_1);
2841 key[2] = nr64(TCAM_KEY_2);
2842 key[3] = nr64(TCAM_KEY_3);
2843 mask[0] = nr64(TCAM_KEY_MASK_0);
2844 mask[1] = nr64(TCAM_KEY_MASK_1);
2845 mask[2] = nr64(TCAM_KEY_MASK_2);
2846 mask[3] = nr64(TCAM_KEY_MASK_3);
2847 }
2848 return err;
2849}
2850#endif
2851
2852static int tcam_write(struct niu *np, int index,
2853 u64 *key, u64 *mask)
2854{
2855 nw64(TCAM_KEY_0, key[0]);
2856 nw64(TCAM_KEY_1, key[1]);
2857 nw64(TCAM_KEY_2, key[2]);
2858 nw64(TCAM_KEY_3, key[3]);
2859 nw64(TCAM_KEY_MASK_0, mask[0]);
2860 nw64(TCAM_KEY_MASK_1, mask[1]);
2861 nw64(TCAM_KEY_MASK_2, mask[2]);
2862 nw64(TCAM_KEY_MASK_3, mask[3]);
2863 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2864
2865 return tcam_wait_bit(np, TCAM_CTL_STAT);
2866}
2867
2868#if 0
2869static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2870{
2871 int err;
2872
2873 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2874 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2875 if (!err)
2876 *data = nr64(TCAM_KEY_1);
2877
2878 return err;
2879}
2880#endif
2881
2882static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2883{
2884 nw64(TCAM_KEY_1, assoc_data);
2885 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2886
2887 return tcam_wait_bit(np, TCAM_CTL_STAT);
2888}
2889
2890static void tcam_enable(struct niu *np, int on)
2891{
2892 u64 val = nr64(FFLP_CFG_1);
2893
2894 if (on)
2895 val &= ~FFLP_CFG_1_TCAM_DIS;
2896 else
2897 val |= FFLP_CFG_1_TCAM_DIS;
2898 nw64(FFLP_CFG_1, val);
2899}
2900
2901static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2902{
2903 u64 val = nr64(FFLP_CFG_1);
2904
2905 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2906 FFLP_CFG_1_CAMLAT |
2907 FFLP_CFG_1_CAMRATIO);
2908 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2909 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2910 nw64(FFLP_CFG_1, val);
2911
2912 val = nr64(FFLP_CFG_1);
2913 val |= FFLP_CFG_1_FFLPINITDONE;
2914 nw64(FFLP_CFG_1, val);
2915}
2916
2917static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2918 int on)
2919{
2920 unsigned long reg;
2921 u64 val;
2922
2923 if (class < CLASS_CODE_ETHERTYPE1 ||
2924 class > CLASS_CODE_ETHERTYPE2)
2925 return -EINVAL;
2926
2927 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2928 val = nr64(reg);
2929 if (on)
2930 val |= L2_CLS_VLD;
2931 else
2932 val &= ~L2_CLS_VLD;
2933 nw64(reg, val);
2934
2935 return 0;
2936}
2937
2938#if 0
2939static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2940 u64 ether_type)
2941{
2942 unsigned long reg;
2943 u64 val;
2944
2945 if (class < CLASS_CODE_ETHERTYPE1 ||
2946 class > CLASS_CODE_ETHERTYPE2 ||
2947 (ether_type & ~(u64)0xffff) != 0)
2948 return -EINVAL;
2949
2950 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2951 val = nr64(reg);
2952 val &= ~L2_CLS_ETYPE;
2953 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2954 nw64(reg, val);
2955
2956 return 0;
2957}
2958#endif
2959
2960static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2961 int on)
2962{
2963 unsigned long reg;
2964 u64 val;
2965
2966 if (class < CLASS_CODE_USER_PROG1 ||
2967 class > CLASS_CODE_USER_PROG4)
2968 return -EINVAL;
2969
2970 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2971 val = nr64(reg);
2972 if (on)
2973 val |= L3_CLS_VALID;
2974 else
2975 val &= ~L3_CLS_VALID;
2976 nw64(reg, val);
2977
2978 return 0;
2979}
2980
a3138df9
DM		 2981static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2982 int ipv6, u64 protocol_id,
2983 u64 tos_mask, u64 tos_val)
2984{
2985 unsigned long reg;
2986 u64 val;
2987
2988 if (class < CLASS_CODE_USER_PROG1 ||
2989 class > CLASS_CODE_USER_PROG4 ||
2990 (protocol_id & ~(u64)0xff) != 0 ||
2991 (tos_mask & ~(u64)0xff) != 0 ||
2992 (tos_val & ~(u64)0xff) != 0)
2993 return -EINVAL;
2994
2995 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2996 val = nr64(reg);
2997 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2998 L3_CLS_TOSMASK | L3_CLS_TOS);
2999 if (ipv6)
3000 val |= L3_CLS_IPVER;
3001 val |= (protocol_id << L3_CLS_PID_SHIFT);
3002 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3003 val |= (tos_val << L3_CLS_TOS_SHIFT);
3004 nw64(reg, val);
3005
3006 return 0;
3007}
a3138df9
DM		 3008
3009static int tcam_early_init(struct niu *np)
3010{
3011 unsigned long i;
3012 int err;
3013
3014 tcam_enable(np, 0);
3015 tcam_set_lat_and_ratio(np,
3016 DEFAULT_TCAM_LATENCY,
3017 DEFAULT_TCAM_ACCESS_RATIO);
3018 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3019 err = tcam_user_eth_class_enable(np, i, 0);
3020 if (err)
3021 return err;
3022 }
3023 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3024 err = tcam_user_ip_class_enable(np, i, 0);
3025 if (err)
3026 return err;
3027 }
3028
3029 return 0;
3030}
3031
3032static int tcam_flush_all(struct niu *np)
3033{
3034 unsigned long i;
3035
3036 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3037 int err = tcam_flush(np, i);
3038 if (err)
3039 return err;
3040 }
3041 return 0;
3042}
3043
3044static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3045{
3046 return ((u64)index | (num_entries == 1 ?
3047 HASH_TBL_ADDR_AUTOINC : 0));
3048}
3049
3050#if 0
3051static int hash_read(struct niu *np, unsigned long partition,
3052 unsigned long index, unsigned long num_entries,
3053 u64 *data)
3054{
3055 u64 val = hash_addr_regval(index, num_entries);
3056 unsigned long i;
3057
3058 if (partition >= FCRAM_NUM_PARTITIONS ||
3059 index + num_entries > FCRAM_SIZE)
3060 return -EINVAL;
3061
3062 nw64(HASH_TBL_ADDR(partition), val);
3063 for (i = 0; i < num_entries; i++)
3064 data[i] = nr64(HASH_TBL_DATA(partition));
3065
3066 return 0;
3067}
3068#endif
3069
3070static int hash_write(struct niu *np, unsigned long partition,
3071 unsigned long index, unsigned long num_entries,
3072 u64 *data)
3073{
3074 u64 val = hash_addr_regval(index, num_entries);
3075 unsigned long i;
3076
3077 if (partition >= FCRAM_NUM_PARTITIONS ||
3078 index + (num_entries * 8) > FCRAM_SIZE)
3079 return -EINVAL;
3080
3081 nw64(HASH_TBL_ADDR(partition), val);
3082 for (i = 0; i < num_entries; i++)
3083 nw64(HASH_TBL_DATA(partition), data[i]);
3084
3085 return 0;
3086}
3087
3088static void fflp_reset(struct niu *np)
3089{
3090 u64 val;
3091
3092 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3093 udelay(10);
3094 nw64(FFLP_CFG_1, 0);
3095
3096 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3097 nw64(FFLP_CFG_1, val);
3098}
3099
3100static void fflp_set_timings(struct niu *np)
3101{
3102 u64 val = nr64(FFLP_CFG_1);
3103
3104 val &= ~FFLP_CFG_1_FFLPINITDONE;
3105 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3106 nw64(FFLP_CFG_1, val);
3107
3108 val = nr64(FFLP_CFG_1);
3109 val |= FFLP_CFG_1_FFLPINITDONE;
3110 nw64(FFLP_CFG_1, val);
3111
3112 val = nr64(FCRAM_REF_TMR);
3113 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3114 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3115 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3116 nw64(FCRAM_REF_TMR, val);
3117}
3118
3119static int fflp_set_partition(struct niu *np, u64 partition,
3120 u64 mask, u64 base, int enable)
3121{
3122 unsigned long reg;
3123 u64 val;
3124
3125 if (partition >= FCRAM_NUM_PARTITIONS ||
3126 (mask & ~(u64)0x1f) != 0 ||
3127 (base & ~(u64)0x1f) != 0)
3128 return -EINVAL;
3129
3130 reg = FLW_PRT_SEL(partition);
3131
3132 val = nr64(reg);
3133 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3134 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3135 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3136 if (enable)
3137 val |= FLW_PRT_SEL_EXT;
3138 nw64(reg, val);
3139
3140 return 0;
3141}
3142
3143static int fflp_disable_all_partitions(struct niu *np)
3144{
3145 unsigned long i;
3146
3147 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3148 int err = fflp_set_partition(np, 0, 0, 0, 0);
3149 if (err)
3150 return err;
3151 }
3152 return 0;
3153}
3154
3155static void fflp_llcsnap_enable(struct niu *np, int on)
3156{
3157 u64 val = nr64(FFLP_CFG_1);
3158
3159 if (on)
3160 val |= FFLP_CFG_1_LLCSNAP;
3161 else
3162 val &= ~FFLP_CFG_1_LLCSNAP;
3163 nw64(FFLP_CFG_1, val);
3164}
3165
3166static void fflp_errors_enable(struct niu *np, int on)
3167{
3168 u64 val = nr64(FFLP_CFG_1);
3169
3170 if (on)
3171 val &= ~FFLP_CFG_1_ERRORDIS;
3172 else
3173 val |= FFLP_CFG_1_ERRORDIS;
3174 nw64(FFLP_CFG_1, val);
3175}
3176
3177static int fflp_hash_clear(struct niu *np)
3178{
3179 struct fcram_hash_ipv4 ent;
3180 unsigned long i;
3181
3182 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3183 memset(&ent, 0, sizeof(ent));
3184 ent.header = HASH_HEADER_EXT;
3185
3186 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3187 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3188 if (err)
3189 return err;
3190 }
3191 return 0;
3192}
3193
3194static int fflp_early_init(struct niu *np)
3195{
3196 struct niu_parent *parent;
3197 unsigned long flags;
3198 int err;
3199
3200 niu_lock_parent(np, flags);
3201
3202 parent = np->parent;
3203 err = 0;
3204 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
a3138df9
DM		 3205 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3206 fflp_reset(np);
3207 fflp_set_timings(np);
3208 err = fflp_disable_all_partitions(np);
3209 if (err) {
f10a1f2e
JP		 3210 netif_printk(np, probe, KERN_DEBUG, np->dev,
3211 "fflp_disable_all_partitions failed, err=%d\n",
3212 err);
a3138df9
DM		 3213 goto out;
3214 }
3215 }
3216
3217 err = tcam_early_init(np);
3218 if (err) {
f10a1f2e
JP		 3219 netif_printk(np, probe, KERN_DEBUG, np->dev,
3220 "tcam_early_init failed, err=%d\n", err);
a3138df9
DM		 3221 goto out;
3222 }
3223 fflp_llcsnap_enable(np, 1);
3224 fflp_errors_enable(np, 0);
3225 nw64(H1POLY, 0);
3226 nw64(H2POLY, 0);
3227
3228 err = tcam_flush_all(np);
3229 if (err) {
f10a1f2e
JP		 3230 netif_printk(np, probe, KERN_DEBUG, np->dev,
3231 "tcam_flush_all failed, err=%d\n", err);
a3138df9
DM		 3232 goto out;
3233 }
3234 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3235 err = fflp_hash_clear(np);
3236 if (err) {
f10a1f2e
JP		 3237 netif_printk(np, probe, KERN_DEBUG, np->dev,
3238 "fflp_hash_clear failed, err=%d\n",
3239 err);
a3138df9
DM		 3240 goto out;
3241 }
3242 }
3243
3244 vlan_tbl_clear(np);
3245
a3138df9
DM		 3246 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3247 }
3248out:
3249 niu_unlock_parent(np, flags);
3250 return err;
3251}
3252
3253static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3254{
3255 if (class_code < CLASS_CODE_USER_PROG1 ||
3256 class_code > CLASS_CODE_SCTP_IPV6)
3257 return -EINVAL;
3258
3259 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3260 return 0;
3261}
3262
3263static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3264{
3265 if (class_code < CLASS_CODE_USER_PROG1 ||
3266 class_code > CLASS_CODE_SCTP_IPV6)
3267 return -EINVAL;
3268
3269 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3270 return 0;
3271}
3272
2d96cf8c
SB		 3273/* Entries for the ports are interleaved in the TCAM */
3274static u16 tcam_get_index(struct niu *np, u16 idx)
3275{
3276 /* One entry reserved for IP fragment rule */
3277 if (idx >= (np->clas.tcam_sz - 1))
3278 idx = 0;
3279 return (np->clas.tcam_top + ((idx+1) * np->parent->num_ports));
3280}
3281
3282static u16 tcam_get_size(struct niu *np)
3283{
3284 /* One entry reserved for IP fragment rule */
3285 return np->clas.tcam_sz - 1;
3286}
3287
3288static u16 tcam_get_valid_entry_cnt(struct niu *np)
3289{
3290 /* One entry reserved for IP fragment rule */
3291 return np->clas.tcam_valid_entries - 1;
3292}
3293
a3138df9
DM		 3294static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3295 u32 offset, u32 size)
3296{
3297 int i = skb_shinfo(skb)->nr_frags;
3298 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3299
3300 frag->page = page;
3301 frag->page_offset = offset;
3302 frag->size = size;
3303
3304 skb->len += size;
3305 skb->data_len += size;
3306 skb->truesize += size;
3307
3308 skb_shinfo(skb)->nr_frags = i + 1;
3309}
3310
3311static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3312{
3313 a >>= PAGE_SHIFT;
3314 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3315
3316 return (a & (MAX_RBR_RING_SIZE - 1));
3317}
3318
3319static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3320 struct page ***link)
3321{
3322 unsigned int h = niu_hash_rxaddr(rp, addr);
3323 struct page *p, **pp;
3324
3325 addr &= PAGE_MASK;
3326 pp = &rp->rxhash[h];
3327 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3328 if (p->index == addr) {
3329 *link = pp;
a0387169 3330 goto found;
a3138df9
DM		 3331 }
3332 }
a0387169 3333 BUG();
a3138df9 3334
a0387169 3335found:
a3138df9
DM		 3336 return p;
3337}
3338
3339static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3340{
3341 unsigned int h = niu_hash_rxaddr(rp, base);
3342
3343 page->index = base;
3344 page->mapping = (struct address_space *) rp->rxhash[h];
3345 rp->rxhash[h] = page;
3346}
3347
3348static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3349 gfp_t mask, int start_index)
3350{
3351 struct page *page;
3352 u64 addr;
3353 int i;
3354
3355 page = alloc_page(mask);
3356 if (!page)
3357 return -ENOMEM;
3358
3359 addr = np->ops->map_page(np->device, page, 0,
3360 PAGE_SIZE, DMA_FROM_DEVICE);
3361
3362 niu_hash_page(rp, page, addr);
3363 if (rp->rbr_blocks_per_page > 1)
3364 atomic_add(rp->rbr_blocks_per_page - 1,
3365 &compound_head(page)->_count);
3366
3367 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3368 __le32 *rbr = &rp->rbr[start_index + i];
3369
3370 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3371 addr += rp->rbr_block_size;
3372 }
3373
3374 return 0;
3375}
3376
3377static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3378{
3379 int index = rp->rbr_index;
3380
3381 rp->rbr_pending++;
3382 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3383 int err = niu_rbr_add_page(np, rp, mask, index);
3384
3385 if (unlikely(err)) {
3386 rp->rbr_pending--;
3387 return;
3388 }
3389
3390 rp->rbr_index += rp->rbr_blocks_per_page;
3391 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3392 if (rp->rbr_index == rp->rbr_table_size)
3393 rp->rbr_index = 0;
3394
3395 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3396 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3397 rp->rbr_pending = 0;
3398 }
3399 }
3400}
3401
3402static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3403{
3404 unsigned int index = rp->rcr_index;
3405 int num_rcr = 0;
3406
3407 rp->rx_dropped++;
3408 while (1) {
3409 struct page *page, **link;
3410 u64 addr, val;
3411 u32 rcr_size;
3412
3413 num_rcr++;
3414
3415 val = le64_to_cpup(&rp->rcr[index]);
3416 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3417 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3418 page = niu_find_rxpage(rp, addr, &link);
3419
3420 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3421 RCR_ENTRY_PKTBUFSZ_SHIFT];
3422 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3423 *link = (struct page *) page->mapping;
3424 np->ops->unmap_page(np->device, page->index,
3425 PAGE_SIZE, DMA_FROM_DEVICE);
3426 page->index = 0;
3427 page->mapping = NULL;
3428 __free_page(page);
3429 rp->rbr_refill_pending++;
3430 }
3431
3432 index = NEXT_RCR(rp, index);
3433 if (!(val & RCR_ENTRY_MULTI))
3434 break;
3435
3436 }
3437 rp->rcr_index = index;
3438
3439 return num_rcr;
3440}
3441
4099e012
DM		 3442static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3443 struct rx_ring_info *rp)
a3138df9
DM		 3444{
3445 unsigned int index = rp->rcr_index;
3cfa856d 3446 struct rx_pkt_hdr1 *rh;
a3138df9
DM		 3447 struct sk_buff *skb;
3448 int len, num_rcr;
3449
3450 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3451 if (unlikely(!skb))
3452 return niu_rx_pkt_ignore(np, rp);
3453
3454 num_rcr = 0;
3455 while (1) {
3456 struct page *page, **link;
3457 u32 rcr_size, append_size;
3458 u64 addr, val, off;
3459
3460 num_rcr++;
3461
3462 val = le64_to_cpup(&rp->rcr[index]);
3463
3464 len = (val & RCR_ENTRY_L2_LEN) >>
3465 RCR_ENTRY_L2_LEN_SHIFT;
3466 len -= ETH_FCS_LEN;
3467
3468 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3469 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3470 page = niu_find_rxpage(rp, addr, &link);
3471
3472 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3473 RCR_ENTRY_PKTBUFSZ_SHIFT];
3474
3475 off = addr & ~PAGE_MASK;
3476 append_size = rcr_size;
3477 if (num_rcr == 1) {
3478 int ptype;
3479
a3138df9
DM		 3480 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3481 if ((ptype == RCR_PKT_TYPE_TCP ||
3482 ptype == RCR_PKT_TYPE_UDP) &&
3483 !(val & (RCR_ENTRY_NOPORT |
3484 RCR_ENTRY_ERROR)))
3485 skb->ip_summed = CHECKSUM_UNNECESSARY;
3486 else
bc8acf2c 3487 skb_checksum_none_assert(skb);
3cfa856d 3488 } else if (!(val & RCR_ENTRY_MULTI))
a3138df9
DM		 3489 append_size = len - skb->len;
3490
3491 niu_rx_skb_append(skb, page, off, append_size);
3492 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3493 *link = (struct page *) page->mapping;
3494 np->ops->unmap_page(np->device, page->index,
3495 PAGE_SIZE, DMA_FROM_DEVICE);
3496 page->index = 0;
3497 page->mapping = NULL;
3498 rp->rbr_refill_pending++;
3499 } else
3500 get_page(page);
3501
3502 index = NEXT_RCR(rp, index);
3503 if (!(val & RCR_ENTRY_MULTI))
3504 break;
3505
3506 }
3507 rp->rcr_index = index;
3508
3cfa856d
DM		 3509 len += sizeof(*rh);
3510 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3511 __pskb_pull_tail(skb, len);
3512
3513 rh = (struct rx_pkt_hdr1 *) skb->data;
3514 if (np->dev->features & NETIF_F_RXHASH)
3515 skb->rxhash = ((u32)rh->hashval2_0 << 24 |
3516 (u32)rh->hashval2_1 << 16 |
3517 (u32)rh->hashval1_1 << 8 |
3518 (u32)rh->hashval1_2 << 0);
3519 skb_pull(skb, sizeof(*rh));
a3138df9
DM		 3520
3521 rp->rx_packets++;
3522 rp->rx_bytes += skb->len;
3523
3524 skb->protocol = eth_type_trans(skb, np->dev);
0c8dfc83 3525 skb_record_rx_queue(skb, rp->rx_channel);
4099e012 3526 napi_gro_receive(napi, skb);
a3138df9
DM		 3527
3528 return num_rcr;
3529}
3530
3531static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3532{
3533 int blocks_per_page = rp->rbr_blocks_per_page;
3534 int err, index = rp->rbr_index;
3535
3536 err = 0;
3537 while (index < (rp->rbr_table_size - blocks_per_page)) {
3538 err = niu_rbr_add_page(np, rp, mask, index);
3539 if (err)
3540 break;
3541
3542 index += blocks_per_page;
3543 }
3544
3545 rp->rbr_index = index;
3546 return err;
3547}
3548
3549static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3550{
3551 int i;
3552
3553 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3554 struct page *page;
3555
3556 page = rp->rxhash[i];
3557 while (page) {
3558 struct page *next = (struct page *) page->mapping;
3559 u64 base = page->index;
3560
3561 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3562 DMA_FROM_DEVICE);
3563 page->index = 0;
3564 page->mapping = NULL;
3565
3566 __free_page(page);
3567
3568 page = next;
3569 }
3570 }
3571
3572 for (i = 0; i < rp->rbr_table_size; i++)
3573 rp->rbr[i] = cpu_to_le32(0);
3574 rp->rbr_index = 0;
3575}
3576
3577static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3578{
3579 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3580 struct sk_buff *skb = tb->skb;
3581 struct tx_pkt_hdr *tp;
3582 u64 tx_flags;
3583 int i, len;
3584
3585 tp = (struct tx_pkt_hdr *) skb->data;
3586 tx_flags = le64_to_cpup(&tp->flags);
3587
3588 rp->tx_packets++;
3589 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3590 ((tx_flags & TXHDR_PAD) / 2));
3591
3592 len = skb_headlen(skb);
3593 np->ops->unmap_single(np->device, tb->mapping,
3594 len, DMA_TO_DEVICE);
3595
3596 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3597 rp->mark_pending--;
3598
3599 tb->skb = NULL;
3600 do {
3601 idx = NEXT_TX(rp, idx);
3602 len -= MAX_TX_DESC_LEN;
3603 } while (len > 0);
3604
3605 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3606 tb = &rp->tx_buffs[idx];
3607 BUG_ON(tb->skb != NULL);
3608 np->ops->unmap_page(np->device, tb->mapping,
3609 skb_shinfo(skb)->frags[i].size,
3610 DMA_TO_DEVICE);
3611 idx = NEXT_TX(rp, idx);
3612 }
3613
3614 dev_kfree_skb(skb);
3615
3616 return idx;
3617}
3618
3619#define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3620
3621static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3622{
b4c21639 3623 struct netdev_queue *txq;
a3138df9 3624 u16 pkt_cnt, tmp;
b4c21639 3625 int cons, index;
a3138df9
DM		 3626 u64 cs;
3627
b4c21639
DM		 3628 index = (rp - np->tx_rings);
3629 txq = netdev_get_tx_queue(np->dev, index);
3630
a3138df9
DM		 3631 cs = rp->tx_cs;
3632 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3633 goto out;
3634
3635 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3636 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3637 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3638
3639 rp->last_pkt_cnt = tmp;
3640
3641 cons = rp->cons;
3642
f10a1f2e
JP		 3643 netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3644 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
a3138df9
DM		 3645
3646 while (pkt_cnt--)
3647 cons = release_tx_packet(np, rp, cons);
3648
3649 rp->cons = cons;
3650 smp_mb();
3651
3652out:
b4c21639 3653 if (unlikely(netif_tx_queue_stopped(txq) &&
a3138df9 3654 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
b4c21639
DM		 3655 __netif_tx_lock(txq, smp_processor_id());
3656 if (netif_tx_queue_stopped(txq) &&
a3138df9 3657 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
b4c21639
DM		 3658 netif_tx_wake_queue(txq);
3659 __netif_tx_unlock(txq);
a3138df9
DM		 3660 }
3661}
3662
b8a606b8
JDB		 3663static inline void niu_sync_rx_discard_stats(struct niu *np,
3664 struct rx_ring_info *rp,
3665 const int limit)
3666{
3667 /* This elaborate scheme is needed for reading the RX discard
3668 * counters, as they are only 16-bit and can overflow quickly,
3669 * and because the overflow indication bit is not usable as
3670 * the counter value does not wrap, but remains at max value
3671 * 0xFFFF.
3672 *
3673 * In theory and in practice counters can be lost in between
3674 * reading nr64() and clearing the counter nw64(). For this
3675 * reason, the number of counter clearings nw64() is
3676 * limited/reduced though the limit parameter.
3677 */
3678 int rx_channel = rp->rx_channel;
3679 u32 misc, wred;
3680
3681 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3682 * following discard events: IPP (Input Port Process),
3683 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3684 * Block Ring) prefetch buffer is empty.
3685 */
3686 misc = nr64(RXMISC(rx_channel));
3687 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3688 nw64(RXMISC(rx_channel), 0);
3689 rp->rx_errors += misc & RXMISC_COUNT;
3690
3691 if (unlikely(misc & RXMISC_OFLOW))
f10a1f2e
JP		 3692 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3693 rx_channel);
d231776f 3694
f10a1f2e
JP		 3695 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3696 "rx-%d: MISC drop=%u over=%u\n",
3697 rx_channel, misc, misc-limit);
b8a606b8
JDB		 3698 }
3699
3700 /* WRED (Weighted Random Early Discard) by hardware */
3701 wred = nr64(RED_DIS_CNT(rx_channel));
3702 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3703 nw64(RED_DIS_CNT(rx_channel), 0);
3704 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3705
3706 if (unlikely(wred & RED_DIS_CNT_OFLOW))
f10a1f2e 3707 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
d231776f 3708
f10a1f2e
JP		 3709 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3710 "rx-%d: WRED drop=%u over=%u\n",
3711 rx_channel, wred, wred-limit);
b8a606b8
JDB		 3712 }
3713}
3714
4099e012
DM		 3715static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3716 struct rx_ring_info *rp, int budget)
a3138df9
DM		 3717{
3718 int qlen, rcr_done = 0, work_done = 0;
3719 struct rxdma_mailbox *mbox = rp->mbox;
3720 u64 stat;
3721
3722#if 1
3723 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3724 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3725#else
3726 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3727 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3728#endif
3729 mbox->rx_dma_ctl_stat = 0;
3730 mbox->rcrstat_a = 0;
3731
f10a1f2e
JP		 3732 netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3733 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3734 __func__, rp->rx_channel, (unsigned long long)stat, qlen);
a3138df9
DM		 3735
3736 rcr_done = work_done = 0;
3737 qlen = min(qlen, budget);
3738 while (work_done < qlen) {
4099e012 3739 rcr_done += niu_process_rx_pkt(napi, np, rp);
a3138df9
DM		 3740 work_done++;
3741 }
3742
3743 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3744 unsigned int i;
3745
3746 for (i = 0; i < rp->rbr_refill_pending; i++)
3747 niu_rbr_refill(np, rp, GFP_ATOMIC);
3748 rp->rbr_refill_pending = 0;
3749 }
3750
3751 stat = (RX_DMA_CTL_STAT_MEX |
3752 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3753 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3754
3755 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3756
e98def1f
JDB		 3757 /* Only sync discards stats when qlen indicate potential for drops */
3758 if (qlen > 10)
3759 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
b8a606b8 3760
a3138df9
DM		 3761 return work_done;
3762}
3763
3764static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3765{
3766 u64 v0 = lp->v0;
3767 u32 tx_vec = (v0 >> 32);
3768 u32 rx_vec = (v0 & 0xffffffff);
3769 int i, work_done = 0;
3770
f10a1f2e
JP		 3771 netif_printk(np, intr, KERN_DEBUG, np->dev,
3772 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
a3138df9
DM		 3773
3774 for (i = 0; i < np->num_tx_rings; i++) {
3775 struct tx_ring_info *rp = &np->tx_rings[i];
3776 if (tx_vec & (1 << rp->tx_channel))
3777 niu_tx_work(np, rp);
3778 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3779 }
3780
3781 for (i = 0; i < np->num_rx_rings; i++) {
3782 struct rx_ring_info *rp = &np->rx_rings[i];
3783
3784 if (rx_vec & (1 << rp->rx_channel)) {
3785 int this_work_done;
3786
4099e012 3787 this_work_done = niu_rx_work(&lp->napi, np, rp,
a3138df9
DM		 3788 budget);
3789
3790 budget -= this_work_done;
3791 work_done += this_work_done;
3792 }
3793 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3794 }
3795
3796 return work_done;
3797}
3798
3799static int niu_poll(struct napi_struct *napi, int budget)
3800{
3801 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3802 struct niu *np = lp->np;
3803 int work_done;
3804
3805 work_done = niu_poll_core(np, lp, budget);
3806
3807 if (work_done < budget) {
288379f0 3808 napi_complete(napi);
a3138df9
DM		 3809 niu_ldg_rearm(np, lp, 1);
3810 }
3811 return work_done;
3812}
3813
3814static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3815 u64 stat)
3816{
f10a1f2e 3817 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
a3138df9
DM		 3818
3819 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
f10a1f2e 3820 pr_cont("RBR_TMOUT ");
a3138df9 3821 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
f10a1f2e 3822 pr_cont("RSP_CNT ");
a3138df9 3823 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
f10a1f2e 3824 pr_cont("BYTE_EN_BUS ");
a3138df9 3825 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
f10a1f2e 3826 pr_cont("RSP_DAT ");
a3138df9 3827 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
f10a1f2e 3828 pr_cont("RCR_ACK ");
a3138df9 3829 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
f10a1f2e 3830 pr_cont("RCR_SHA_PAR ");
a3138df9 3831 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
f10a1f2e 3832 pr_cont("RBR_PRE_PAR ");
a3138df9 3833 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
f10a1f2e 3834 pr_cont("CONFIG ");
a3138df9 3835 if (stat & RX_DMA_CTL_STAT_RCRINCON)
f10a1f2e 3836 pr_cont("RCRINCON ");
a3138df9 3837 if (stat & RX_DMA_CTL_STAT_RCRFULL)
f10a1f2e 3838 pr_cont("RCRFULL ");
a3138df9 3839 if (stat & RX_DMA_CTL_STAT_RBRFULL)
f10a1f2e 3840 pr_cont("RBRFULL ");
a3138df9 3841 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
f10a1f2e 3842 pr_cont("RBRLOGPAGE ");
a3138df9 3843 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
f10a1f2e 3844 pr_cont("CFIGLOGPAGE ");
a3138df9 3845 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
f10a1f2e 3846 pr_cont("DC_FIDO ");
a3138df9 3847
f10a1f2e 3848 pr_cont(")\n");
a3138df9
DM		 3849}
3850
3851static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3852{
3853 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3854 int err = 0;
3855
a3138df9
DM		 3856
3857 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3858 RX_DMA_CTL_STAT_PORT_FATAL))
3859 err = -EINVAL;
3860
406f353c 3861 if (err) {
f10a1f2e
JP		 3862 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3863 rp->rx_channel,
3864 (unsigned long long) stat);
406f353c
MW		 3865
3866 niu_log_rxchan_errors(np, rp, stat);
3867 }
3868
a3138df9
DM		 3869 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3870 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3871
3872 return err;
3873}
3874
3875static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3876 u64 cs)
3877{
f10a1f2e 3878 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
a3138df9
DM		 3879
3880 if (cs & TX_CS_MBOX_ERR)
f10a1f2e 3881 pr_cont("MBOX ");
a3138df9 3882 if (cs & TX_CS_PKT_SIZE_ERR)
f10a1f2e 3883 pr_cont("PKT_SIZE ");
a3138df9 3884 if (cs & TX_CS_TX_RING_OFLOW)
f10a1f2e 3885 pr_cont("TX_RING_OFLOW ");
a3138df9 3886 if (cs & TX_CS_PREF_BUF_PAR_ERR)
f10a1f2e 3887 pr_cont("PREF_BUF_PAR ");
a3138df9 3888 if (cs & TX_CS_NACK_PREF)
f10a1f2e 3889 pr_cont("NACK_PREF ");
a3138df9 3890 if (cs & TX_CS_NACK_PKT_RD)
f10a1f2e 3891 pr_cont("NACK_PKT_RD ");
a3138df9 3892 if (cs & TX_CS_CONF_PART_ERR)
f10a1f2e 3893 pr_cont("CONF_PART ");
a3138df9 3894 if (cs & TX_CS_PKT_PRT_ERR)
f10a1f2e 3895 pr_cont("PKT_PTR ");
a3138df9 3896
f10a1f2e 3897 pr_cont(")\n");
a3138df9
DM		 3898}
3899
3900static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3901{
3902 u64 cs, logh, logl;
3903
3904 cs = nr64(TX_CS(rp->tx_channel));
3905 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3906 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3907
f10a1f2e
JP		 3908 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3909 rp->tx_channel,
3910 (unsigned long long)cs,
3911 (unsigned long long)logh,
3912 (unsigned long long)logl);
a3138df9
DM		 3913
3914 niu_log_txchan_errors(np, rp, cs);
3915
3916 return -ENODEV;
3917}
3918
3919static int niu_mif_interrupt(struct niu *np)
3920{
3921 u64 mif_status = nr64(MIF_STATUS);
3922 int phy_mdint = 0;
3923
3924 if (np->flags & NIU_FLAGS_XMAC) {
3925 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3926
3927 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3928 phy_mdint = 1;
3929 }
3930
f10a1f2e
JP		 3931 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3932 (unsigned long long)mif_status, phy_mdint);
a3138df9
DM		 3933
3934 return -ENODEV;
3935}
3936
3937static void niu_xmac_interrupt(struct niu *np)
3938{
3939 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3940 u64 val;
3941
3942 val = nr64_mac(XTXMAC_STATUS);
3943 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3944 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3945 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3946 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3947 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3948 mp->tx_fifo_errors++;
3949 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3950 mp->tx_overflow_errors++;
3951 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3952 mp->tx_max_pkt_size_errors++;
3953 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3954 mp->tx_underflow_errors++;
3955
3956 val = nr64_mac(XRXMAC_STATUS);
3957 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3958 mp->rx_local_faults++;
3959 if (val & XRXMAC_STATUS_RFLT_DET)
3960 mp->rx_remote_faults++;
3961 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3962 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3963 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3964 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3965 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3966 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3967 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3968 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3969 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3970 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3971 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3972 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3973 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3974 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3975 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3976 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3977 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3978 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3979 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3980 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3981 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3982 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3983 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3984 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3985 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3986 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
176edd52 3987 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
a3138df9
DM		 3988 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3989 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3990 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3991 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3992 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3993 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3994 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3995 if (val & XRXMAC_STATUS_RXUFLOW)
3996 mp->rx_underflows++;
3997 if (val & XRXMAC_STATUS_RXOFLOW)
3998 mp->rx_overflows++;
3999
4000 val = nr64_mac(XMAC_FC_STAT);
4001 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
4002 mp->pause_off_state++;
4003 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
4004 mp->pause_on_state++;
4005 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4006 mp->pause_received++;
4007}
4008
4009static void niu_bmac_interrupt(struct niu *np)
4010{
4011 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4012 u64 val;
4013
4014 val = nr64_mac(BTXMAC_STATUS);
4015 if (val & BTXMAC_STATUS_UNDERRUN)
4016 mp->tx_underflow_errors++;
4017 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4018 mp->tx_max_pkt_size_errors++;
4019 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4020 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4021 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4022 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4023
4024 val = nr64_mac(BRXMAC_STATUS);
4025 if (val & BRXMAC_STATUS_OVERFLOW)
4026 mp->rx_overflows++;
4027 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4028 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4029 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4030 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4031 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4032 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4033 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4034 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4035
4036 val = nr64_mac(BMAC_CTRL_STATUS);
4037 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4038 mp->pause_off_state++;
4039 if (val & BMAC_CTRL_STATUS_PAUSE)
4040 mp->pause_on_state++;
4041 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4042 mp->pause_received++;
4043}
4044
4045static int niu_mac_interrupt(struct niu *np)
4046{
4047 if (np->flags & NIU_FLAGS_XMAC)
4048 niu_xmac_interrupt(np);
4049 else
4050 niu_bmac_interrupt(np);
4051
4052 return 0;
4053}
4054
4055static void niu_log_device_error(struct niu *np, u64 stat)
4056{
f10a1f2e 4057 netdev_err(np->dev, "Core device errors ( ");
a3138df9
DM		 4058
4059 if (stat & SYS_ERR_MASK_META2)
f10a1f2e 4060 pr_cont("META2 ");
a3138df9 4061 if (stat & SYS_ERR_MASK_META1)
f10a1f2e 4062 pr_cont("META1 ");
a3138df9 4063 if (stat & SYS_ERR_MASK_PEU)
f10a1f2e 4064 pr_cont("PEU ");
a3138df9 4065 if (stat & SYS_ERR_MASK_TXC)
f10a1f2e 4066 pr_cont("TXC ");
a3138df9 4067 if (stat & SYS_ERR_MASK_RDMC)
f10a1f2e 4068 pr_cont("RDMC ");
a3138df9 4069 if (stat & SYS_ERR_MASK_TDMC)
f10a1f2e 4070 pr_cont("TDMC ");
a3138df9 4071 if (stat & SYS_ERR_MASK_ZCP)
f10a1f2e 4072 pr_cont("ZCP ");
a3138df9 4073 if (stat & SYS_ERR_MASK_FFLP)
f10a1f2e 4074 pr_cont("FFLP ");
a3138df9 4075 if (stat & SYS_ERR_MASK_IPP)
f10a1f2e 4076 pr_cont("IPP ");
a3138df9 4077 if (stat & SYS_ERR_MASK_MAC)
f10a1f2e 4078 pr_cont("MAC ");
a3138df9 4079 if (stat & SYS_ERR_MASK_SMX)
f10a1f2e 4080 pr_cont("SMX ");
a3138df9 4081
f10a1f2e 4082 pr_cont(")\n");
a3138df9
DM		 4083}
4084
4085static int niu_device_error(struct niu *np)
4086{
4087 u64 stat = nr64(SYS_ERR_STAT);
4088
f10a1f2e
JP		 4089 netdev_err(np->dev, "Core device error, stat[%llx]\n",
4090 (unsigned long long)stat);
a3138df9
DM		 4091
4092 niu_log_device_error(np, stat);
4093
4094 return -ENODEV;
4095}
4096
406f353c
MW		 4097static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4098 u64 v0, u64 v1, u64 v2)
a3138df9 4099{
406f353c 4100
a3138df9
DM		 4101 int i, err = 0;
4102
406f353c
MW		 4103 lp->v0 = v0;
4104 lp->v1 = v1;
4105 lp->v2 = v2;
4106
a3138df9
DM		 4107 if (v1 & 0x00000000ffffffffULL) {
4108 u32 rx_vec = (v1 & 0xffffffff);
4109
4110 for (i = 0; i < np->num_rx_rings; i++) {
4111 struct rx_ring_info *rp = &np->rx_rings[i];
4112
4113 if (rx_vec & (1 << rp->rx_channel)) {
4114 int r = niu_rx_error(np, rp);
406f353c 4115 if (r) {
a3138df9 4116 err = r;
406f353c
MW		 4117 } else {
4118 if (!v0)
4119 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4120 RX_DMA_CTL_STAT_MEX);
4121 }
a3138df9
DM		 4122 }
4123 }
4124 }
4125 if (v1 & 0x7fffffff00000000ULL) {
4126 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4127
4128 for (i = 0; i < np->num_tx_rings; i++) {
4129 struct tx_ring_info *rp = &np->tx_rings[i];
4130
4131 if (tx_vec & (1 << rp->tx_channel)) {
4132 int r = niu_tx_error(np, rp);
4133 if (r)
4134 err = r;
4135 }
4136 }
4137 }
4138 if ((v0 | v1) & 0x8000000000000000ULL) {
4139 int r = niu_mif_interrupt(np);
4140 if (r)
4141 err = r;
4142 }
4143 if (v2) {
4144 if (v2 & 0x01ef) {
4145 int r = niu_mac_interrupt(np);
4146 if (r)
4147 err = r;
4148 }
4149 if (v2 & 0x0210) {
4150 int r = niu_device_error(np);
4151 if (r)
4152 err = r;
4153 }
4154 }
4155
4156 if (err)
4157 niu_enable_interrupts(np, 0);
4158
406f353c 4159 return err;
a3138df9
DM		 4160}
4161
4162static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4163 int ldn)
4164{
4165 struct rxdma_mailbox *mbox = rp->mbox;
4166 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4167
4168 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4169 RX_DMA_CTL_STAT_RCRTO);
4170 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4171
f10a1f2e
JP		 4172 netif_printk(np, intr, KERN_DEBUG, np->dev,
4173 "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
a3138df9
DM		 4174}
4175
4176static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4177 int ldn)
4178{
4179 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4180
f10a1f2e
JP		 4181 netif_printk(np, intr, KERN_DEBUG, np->dev,
4182 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
a3138df9
DM		 4183}
4184
4185static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4186{
4187 struct niu_parent *parent = np->parent;
4188 u32 rx_vec, tx_vec;
4189 int i;
4190
4191 tx_vec = (v0 >> 32);
4192 rx_vec = (v0 & 0xffffffff);
4193
4194 for (i = 0; i < np->num_rx_rings; i++) {
4195 struct rx_ring_info *rp = &np->rx_rings[i];
4196 int ldn = LDN_RXDMA(rp->rx_channel);
4197
4198 if (parent->ldg_map[ldn] != ldg)
4199 continue;
4200
4201 nw64(LD_IM0(ldn), LD_IM0_MASK);
4202 if (rx_vec & (1 << rp->rx_channel))
4203 niu_rxchan_intr(np, rp, ldn);
4204 }
4205
4206 for (i = 0; i < np->num_tx_rings; i++) {
4207 struct tx_ring_info *rp = &np->tx_rings[i];
4208 int ldn = LDN_TXDMA(rp->tx_channel);
4209
4210 if (parent->ldg_map[ldn] != ldg)
4211 continue;
4212
4213 nw64(LD_IM0(ldn), LD_IM0_MASK);
4214 if (tx_vec & (1 << rp->tx_channel))
4215 niu_txchan_intr(np, rp, ldn);
4216 }
4217}
4218
4219static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4220 u64 v0, u64 v1, u64 v2)
4221{
288379f0 4222 if (likely(napi_schedule_prep(&lp->napi))) {
a3138df9
DM		 4223 lp->v0 = v0;
4224 lp->v1 = v1;
4225 lp->v2 = v2;
4226 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
288379f0 4227 __napi_schedule(&lp->napi);
a3138df9
DM		 4228 }
4229}
4230
4231static irqreturn_t niu_interrupt(int irq, void *dev_id)
4232{
4233 struct niu_ldg *lp = dev_id;
4234 struct niu *np = lp->np;
4235 int ldg = lp->ldg_num;
4236 unsigned long flags;
4237 u64 v0, v1, v2;
4238
4239 if (netif_msg_intr(np))
f10a1f2e
JP		 4240 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4241 __func__, lp, ldg);
a3138df9
DM		 4242
4243 spin_lock_irqsave(&np->lock, flags);
4244
4245 v0 = nr64(LDSV0(ldg));
4246 v1 = nr64(LDSV1(ldg));
4247 v2 = nr64(LDSV2(ldg));
4248
4249 if (netif_msg_intr(np))
02b1bae5 4250 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
a3138df9
DM		 4251 (unsigned long long) v0,
4252 (unsigned long long) v1,
4253 (unsigned long long) v2);
4254
4255 if (unlikely(!v0 && !v1 && !v2)) {
4256 spin_unlock_irqrestore(&np->lock, flags);
4257 return IRQ_NONE;
4258 }
4259
4260 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
406f353c 4261 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
a3138df9
DM		 4262 if (err)
4263 goto out;
4264 }
4265 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4266 niu_schedule_napi(np, lp, v0, v1, v2);
4267 else
4268 niu_ldg_rearm(np, lp, 1);
4269out:
4270 spin_unlock_irqrestore(&np->lock, flags);
4271
4272 return IRQ_HANDLED;
4273}
4274
4275static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4276{
4277 if (rp->mbox) {
4278 np->ops->free_coherent(np->device,
4279 sizeof(struct rxdma_mailbox),
4280 rp->mbox, rp->mbox_dma);
4281 rp->mbox = NULL;
4282 }
4283 if (rp->rcr) {
4284 np->ops->free_coherent(np->device,
4285 MAX_RCR_RING_SIZE * sizeof(__le64),
4286 rp->rcr, rp->rcr_dma);
4287 rp->rcr = NULL;
4288 rp->rcr_table_size = 0;
4289 rp->rcr_index = 0;
4290 }
4291 if (rp->rbr) {
4292 niu_rbr_free(np, rp);
4293
4294 np->ops->free_coherent(np->device,
4295 MAX_RBR_RING_SIZE * sizeof(__le32),
4296 rp->rbr, rp->rbr_dma);
4297 rp->rbr = NULL;
4298 rp->rbr_table_size = 0;
4299 rp->rbr_index = 0;
4300 }
4301 kfree(rp->rxhash);
4302 rp->rxhash = NULL;
4303}
4304
4305static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4306{
4307 if (rp->mbox) {
4308 np->ops->free_coherent(np->device,
4309 sizeof(struct txdma_mailbox),
4310 rp->mbox, rp->mbox_dma);
4311 rp->mbox = NULL;
4312 }
4313 if (rp->descr) {
4314 int i;
4315
4316 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4317 if (rp->tx_buffs[i].skb)
4318 (void) release_tx_packet(np, rp, i);
4319 }
4320
4321 np->ops->free_coherent(np->device,
4322 MAX_TX_RING_SIZE * sizeof(__le64),
4323 rp->descr, rp->descr_dma);
4324 rp->descr = NULL;
4325 rp->pending = 0;
4326 rp->prod = 0;
4327 rp->cons = 0;
4328 rp->wrap_bit = 0;
4329 }
4330}
4331
4332static void niu_free_channels(struct niu *np)
4333{
4334 int i;
4335
4336 if (np->rx_rings) {
4337 for (i = 0; i < np->num_rx_rings; i++) {
4338 struct rx_ring_info *rp = &np->rx_rings[i];
4339
4340 niu_free_rx_ring_info(np, rp);
4341 }
4342 kfree(np->rx_rings);
4343 np->rx_rings = NULL;
4344 np->num_rx_rings = 0;
4345 }
4346
4347 if (np->tx_rings) {
4348 for (i = 0; i < np->num_tx_rings; i++) {
4349 struct tx_ring_info *rp = &np->tx_rings[i];
4350
4351 niu_free_tx_ring_info(np, rp);
4352 }
4353 kfree(np->tx_rings);
4354 np->tx_rings = NULL;
4355 np->num_tx_rings = 0;
4356 }
4357}
4358
4359static int niu_alloc_rx_ring_info(struct niu *np,
4360 struct rx_ring_info *rp)
4361{
4362 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4363
4364 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4365 GFP_KERNEL);
4366 if (!rp->rxhash)
4367 return -ENOMEM;
4368
4369 rp->mbox = np->ops->alloc_coherent(np->device,
4370 sizeof(struct rxdma_mailbox),
4371 &rp->mbox_dma, GFP_KERNEL);
4372 if (!rp->mbox)
4373 return -ENOMEM;
4374 if ((unsigned long)rp->mbox & (64UL - 1)) {
f10a1f2e
JP		 4375 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4376 rp->mbox);
a3138df9
DM		 4377 return -EINVAL;
4378 }
4379
4380 rp->rcr = np->ops->alloc_coherent(np->device,
4381 MAX_RCR_RING_SIZE * sizeof(__le64),
4382 &rp->rcr_dma, GFP_KERNEL);
4383 if (!rp->rcr)
4384 return -ENOMEM;
4385 if ((unsigned long)rp->rcr & (64UL - 1)) {
f10a1f2e
JP		 4386 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4387 rp->rcr);
a3138df9
DM		 4388 return -EINVAL;
4389 }
4390 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4391 rp->rcr_index = 0;
4392
4393 rp->rbr = np->ops->alloc_coherent(np->device,
4394 MAX_RBR_RING_SIZE * sizeof(__le32),
4395 &rp->rbr_dma, GFP_KERNEL);
4396 if (!rp->rbr)
4397 return -ENOMEM;
4398 if ((unsigned long)rp->rbr & (64UL - 1)) {
f10a1f2e
JP		 4399 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4400 rp->rbr);
a3138df9
DM		 4401 return -EINVAL;
4402 }
4403 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4404 rp->rbr_index = 0;
4405 rp->rbr_pending = 0;
4406
4407 return 0;
4408}
4409
4410static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4411{
4412 int mtu = np->dev->mtu;
4413
4414 /* These values are recommended by the HW designers for fair
4415 * utilization of DRR amongst the rings.
4416 */
4417 rp->max_burst = mtu + 32;
4418 if (rp->max_burst > 4096)
4419 rp->max_burst = 4096;
4420}
4421
4422static int niu_alloc_tx_ring_info(struct niu *np,
4423 struct tx_ring_info *rp)
4424{
4425 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4426
4427 rp->mbox = np->ops->alloc_coherent(np->device,
4428 sizeof(struct txdma_mailbox),
4429 &rp->mbox_dma, GFP_KERNEL);
4430 if (!rp->mbox)
4431 return -ENOMEM;
4432 if ((unsigned long)rp->mbox & (64UL - 1)) {
f10a1f2e
JP		 4433 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4434 rp->mbox);
a3138df9
DM		 4435 return -EINVAL;
4436 }
4437
4438 rp->descr = np->ops->alloc_coherent(np->device,
4439 MAX_TX_RING_SIZE * sizeof(__le64),
4440 &rp->descr_dma, GFP_KERNEL);
4441 if (!rp->descr)
4442 return -ENOMEM;
4443 if ((unsigned long)rp->descr & (64UL - 1)) {
f10a1f2e
JP		 4444 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4445 rp->descr);
a3138df9
DM		 4446 return -EINVAL;
4447 }
4448
4449 rp->pending = MAX_TX_RING_SIZE;
4450 rp->prod = 0;
4451 rp->cons = 0;
4452 rp->wrap_bit = 0;
4453
4454 /* XXX make these configurable... XXX */
4455 rp->mark_freq = rp->pending / 4;
4456
4457 niu_set_max_burst(np, rp);
4458
4459 return 0;
4460}
4461
4462static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4463{
81429973 4464 u16 bss;
a3138df9 4465
81429973 4466 bss = min(PAGE_SHIFT, 15);
a3138df9 4467
81429973
OJ		 4468 rp->rbr_block_size = 1 << bss;
4469 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
a3138df9
DM		 4470
4471 rp->rbr_sizes[0] = 256;
4472 rp->rbr_sizes[1] = 1024;
4473 if (np->dev->mtu > ETH_DATA_LEN) {
4474 switch (PAGE_SIZE) {
4475 case 4 * 1024:
4476 rp->rbr_sizes[2] = 4096;
4477 break;
4478
4479 default:
4480 rp->rbr_sizes[2] = 8192;
4481 break;
4482 }
4483 } else {
4484 rp->rbr_sizes[2] = 2048;
4485 }
4486 rp->rbr_sizes[3] = rp->rbr_block_size;
4487}
4488
4489static int niu_alloc_channels(struct niu *np)
4490{
4491 struct niu_parent *parent = np->parent;
4492 int first_rx_channel, first_tx_channel;
4493 int i, port, err;
4494
4495 port = np->port;
4496 first_rx_channel = first_tx_channel = 0;
4497 for (i = 0; i < port; i++) {
4498 first_rx_channel += parent->rxchan_per_port[i];
4499 first_tx_channel += parent->txchan_per_port[i];
4500 }
4501
4502 np->num_rx_rings = parent->rxchan_per_port[port];
4503 np->num_tx_rings = parent->txchan_per_port[port];
4504
b4c21639
DM		 4505 np->dev->real_num_tx_queues = np->num_tx_rings;
4506
baeb2ffa 4507 np->rx_rings = kcalloc(np->num_rx_rings, sizeof(struct rx_ring_info),
a3138df9
DM		 4508 GFP_KERNEL);
4509 err = -ENOMEM;
4510 if (!np->rx_rings)
4511 goto out_err;
4512
4513 for (i = 0; i < np->num_rx_rings; i++) {
4514 struct rx_ring_info *rp = &np->rx_rings[i];
4515
4516 rp->np = np;
4517 rp->rx_channel = first_rx_channel + i;
4518
4519 err = niu_alloc_rx_ring_info(np, rp);
4520 if (err)
4521 goto out_err;
4522
4523 niu_size_rbr(np, rp);
4524
4525 /* XXX better defaults, configurable, etc... XXX */
4526 rp->nonsyn_window = 64;
4527 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4528 rp->syn_window = 64;
4529 rp->syn_threshold = rp->rcr_table_size - 64;
4530 rp->rcr_pkt_threshold = 16;
4531 rp->rcr_timeout = 8;
4532 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4533 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4534 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4535
4536 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4537 if (err)
4538 return err;
4539 }
4540
baeb2ffa 4541 np->tx_rings = kcalloc(np->num_tx_rings, sizeof(struct tx_ring_info),
a3138df9
DM		 4542 GFP_KERNEL);
4543 err = -ENOMEM;
4544 if (!np->tx_rings)
4545 goto out_err;
4546
4547 for (i = 0; i < np->num_tx_rings; i++) {
4548 struct tx_ring_info *rp = &np->tx_rings[i];
4549
4550 rp->np = np;
4551 rp->tx_channel = first_tx_channel + i;
4552
4553 err = niu_alloc_tx_ring_info(np, rp);
4554 if (err)
4555 goto out_err;
4556 }
4557
4558 return 0;
4559
4560out_err:
4561 niu_free_channels(np);
4562 return err;
4563}
4564
4565static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4566{
4567 int limit = 1000;
4568
4569 while (--limit > 0) {
4570 u64 val = nr64(TX_CS(channel));
4571 if (val & TX_CS_SNG_STATE)
4572 return 0;
4573 }
4574 return -ENODEV;
4575}
4576
4577static int niu_tx_channel_stop(struct niu *np, int channel)
4578{
4579 u64 val = nr64(TX_CS(channel));
4580
4581 val |= TX_CS_STOP_N_GO;
4582 nw64(TX_CS(channel), val);
4583
4584 return niu_tx_cs_sng_poll(np, channel);
4585}
4586
4587static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4588{
4589 int limit = 1000;
4590
4591 while (--limit > 0) {
4592 u64 val = nr64(TX_CS(channel));
4593 if (!(val & TX_CS_RST))
4594 return 0;
4595 }
4596 return -ENODEV;
4597}
4598
4599static int niu_tx_channel_reset(struct niu *np, int channel)
4600{
4601 u64 val = nr64(TX_CS(channel));
4602 int err;
4603
4604 val |= TX_CS_RST;
4605 nw64(TX_CS(channel), val);
4606
4607 err = niu_tx_cs_reset_poll(np, channel);
4608 if (!err)
4609 nw64(TX_RING_KICK(channel), 0);
4610
4611 return err;
4612}
4613
4614static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4615{
4616 u64 val;
4617
4618 nw64(TX_LOG_MASK1(channel), 0);
4619 nw64(TX_LOG_VAL1(channel), 0);
4620 nw64(TX_LOG_MASK2(channel), 0);
4621 nw64(TX_LOG_VAL2(channel), 0);
4622 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4623 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4624 nw64(TX_LOG_PAGE_HDL(channel), 0);
4625
4626 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4627 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4628 nw64(TX_LOG_PAGE_VLD(channel), val);
4629
4630 /* XXX TXDMA 32bit mode? XXX */
4631
4632 return 0;
4633}
4634
4635static void niu_txc_enable_port(struct niu *np, int on)
4636{
4637 unsigned long flags;
4638 u64 val, mask;
4639
4640 niu_lock_parent(np, flags);
4641 val = nr64(TXC_CONTROL);
4642 mask = (u64)1 << np->port;
4643 if (on) {
4644 val |= TXC_CONTROL_ENABLE | mask;
4645 } else {
4646 val &= ~mask;
4647 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4648 val &= ~TXC_CONTROL_ENABLE;
4649 }
4650 nw64(TXC_CONTROL, val);
4651 niu_unlock_parent(np, flags);
4652}
4653
4654static void niu_txc_set_imask(struct niu *np, u64 imask)
4655{
4656 unsigned long flags;
4657 u64 val;
4658
4659 niu_lock_parent(np, flags);
4660 val = nr64(TXC_INT_MASK);
4661 val &= ~TXC_INT_MASK_VAL(np->port);
4662 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4663 niu_unlock_parent(np, flags);
4664}
4665
4666static void niu_txc_port_dma_enable(struct niu *np, int on)
4667{
4668 u64 val = 0;
4669
4670 if (on) {
4671 int i;
4672
4673 for (i = 0; i < np->num_tx_rings; i++)
4674 val |= (1 << np->tx_rings[i].tx_channel);
4675 }
4676 nw64(TXC_PORT_DMA(np->port), val);
4677}
4678
4679static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4680{
4681 int err, channel = rp->tx_channel;
4682 u64 val, ring_len;
4683
4684 err = niu_tx_channel_stop(np, channel);
4685 if (err)
4686 return err;
4687
4688 err = niu_tx_channel_reset(np, channel);
4689 if (err)
4690 return err;
4691
4692 err = niu_tx_channel_lpage_init(np, channel);
4693 if (err)
4694 return err;
4695
4696 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4697 nw64(TX_ENT_MSK(channel), 0);
4698
4699 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4700 TX_RNG_CFIG_STADDR)) {
f10a1f2e
JP		 4701 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4702 channel, (unsigned long long)rp->descr_dma);
a3138df9
DM		 4703 return -EINVAL;
4704 }
4705
4706 /* The length field in TX_RNG_CFIG is measured in 64-byte
4707 * blocks. rp->pending is the number of TX descriptors in
4708 * our ring, 8 bytes each, thus we divide by 8 bytes more
4709 * to get the proper value the chip wants.
4710 */
4711 ring_len = (rp->pending / 8);
4712
4713 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4714 rp->descr_dma);
4715 nw64(TX_RNG_CFIG(channel), val);
4716
4717 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4718 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
f10a1f2e
JP		 4719 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4720 channel, (unsigned long long)rp->mbox_dma);
a3138df9
DM		 4721 return -EINVAL;
4722 }
4723 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4724 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4725
4726 nw64(TX_CS(channel), 0);
4727
4728 rp->last_pkt_cnt = 0;
4729
4730 return 0;
4731}
4732
4733static void niu_init_rdc_groups(struct niu *np)
4734{
4735 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4736 int i, first_table_num = tp->first_table_num;
4737
4738 for (i = 0; i < tp->num_tables; i++) {
4739 struct rdc_table *tbl = &tp->tables[i];
4740 int this_table = first_table_num + i;
4741 int slot;
4742
4743 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4744 nw64(RDC_TBL(this_table, slot),
4745 tbl->rxdma_channel[slot]);
4746 }
4747
4748 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4749}
4750
4751static void niu_init_drr_weight(struct niu *np)
4752{
4753 int type = phy_decode(np->parent->port_phy, np->port);
4754 u64 val;
4755
4756 switch (type) {
4757 case PORT_TYPE_10G:
4758 val = PT_DRR_WEIGHT_DEFAULT_10G;
4759 break;
4760
4761 case PORT_TYPE_1G:
4762 default:
4763 val = PT_DRR_WEIGHT_DEFAULT_1G;
4764 break;
4765 }
4766 nw64(PT_DRR_WT(np->port), val);
4767}
4768
4769static int niu_init_hostinfo(struct niu *np)
4770{
4771 struct niu_parent *parent = np->parent;
4772 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4773 int i, err, num_alt = niu_num_alt_addr(np);
4774 int first_rdc_table = tp->first_table_num;
4775
4776 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4777 if (err)
4778 return err;
4779
4780 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4781 if (err)
4782 return err;
4783
4784 for (i = 0; i < num_alt; i++) {
4785 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4786 if (err)
4787 return err;
4788 }
4789
4790 return 0;
4791}
4792
4793static int niu_rx_channel_reset(struct niu *np, int channel)
4794{
4795 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4796 RXDMA_CFIG1_RST, 1000, 10,
4797 "RXDMA_CFIG1");
4798}
4799
4800static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4801{
4802 u64 val;
4803
4804 nw64(RX_LOG_MASK1(channel), 0);
4805 nw64(RX_LOG_VAL1(channel), 0);
4806 nw64(RX_LOG_MASK2(channel), 0);
4807 nw64(RX_LOG_VAL2(channel), 0);
4808 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4809 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4810 nw64(RX_LOG_PAGE_HDL(channel), 0);
4811
4812 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4813 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4814 nw64(RX_LOG_PAGE_VLD(channel), val);
4815
4816 return 0;
4817}
4818
4819static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4820{
4821 u64 val;
4822
4823 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4824 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4825 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4826 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4827 nw64(RDC_RED_PARA(rp->rx_channel), val);
4828}
4829
4830static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4831{
4832 u64 val = 0;
4833
efb6c736 4834 *ret = 0;
a3138df9
DM		 4835 switch (rp->rbr_block_size) {
4836 case 4 * 1024:
4837 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4838 break;
4839 case 8 * 1024:
4840 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4841 break;
4842 case 16 * 1024:
4843 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4844 break;
4845 case 32 * 1024:
4846 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4847 break;
4848 default:
4849 return -EINVAL;
4850 }
4851 val |= RBR_CFIG_B_VLD2;
4852 switch (rp->rbr_sizes[2]) {
4853 case 2 * 1024:
4854 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4855 break;
4856 case 4 * 1024:
4857 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4858 break;
4859 case 8 * 1024:
4860 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4861 break;
4862 case 16 * 1024:
4863 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4864 break;
4865
4866 default:
4867 return -EINVAL;
4868 }
4869 val |= RBR_CFIG_B_VLD1;
4870 switch (rp->rbr_sizes[1]) {
4871 case 1 * 1024:
4872 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4873 break;
4874 case 2 * 1024:
4875 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4876 break;
4877 case 4 * 1024:
4878 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4879 break;
4880 case 8 * 1024:
4881 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4882 break;
4883
4884 default:
4885 return -EINVAL;
4886 }
4887 val |= RBR_CFIG_B_VLD0;
4888 switch (rp->rbr_sizes[0]) {
4889 case 256:
4890 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4891 break;
4892 case 512:
4893 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4894 break;
4895 case 1 * 1024:
4896 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4897 break;
4898 case 2 * 1024:
4899 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4900 break;
4901
4902 default:
4903 return -EINVAL;
4904 }
4905
4906 *ret = val;
4907 return 0;
4908}
4909
4910static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4911{
4912 u64 val = nr64(RXDMA_CFIG1(channel));
4913 int limit;
4914
4915 if (on)
4916 val |= RXDMA_CFIG1_EN;
4917 else
4918 val &= ~RXDMA_CFIG1_EN;
4919 nw64(RXDMA_CFIG1(channel), val);
4920
4921 limit = 1000;
4922 while (--limit > 0) {
4923 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4924 break;
4925 udelay(10);
4926 }
4927 if (limit <= 0)
4928 return -ENODEV;
4929 return 0;
4930}
4931
4932static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4933{
4934 int err, channel = rp->rx_channel;
4935 u64 val;
4936
4937 err = niu_rx_channel_reset(np, channel);
4938 if (err)
4939 return err;
4940
4941 err = niu_rx_channel_lpage_init(np, channel);
4942 if (err)
4943 return err;
4944
4945 niu_rx_channel_wred_init(np, rp);
4946
4947 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4948 nw64(RX_DMA_CTL_STAT(channel),
4949 (RX_DMA_CTL_STAT_MEX |
4950 RX_DMA_CTL_STAT_RCRTHRES |
4951 RX_DMA_CTL_STAT_RCRTO |
4952 RX_DMA_CTL_STAT_RBR_EMPTY));
4953 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
3cfa856d
DM		 4954 nw64(RXDMA_CFIG2(channel),
4955 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4956 RXDMA_CFIG2_FULL_HDR));
a3138df9
DM		 4957 nw64(RBR_CFIG_A(channel),
4958 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4959 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4960 err = niu_compute_rbr_cfig_b(rp, &val);
4961 if (err)
4962 return err;
4963 nw64(RBR_CFIG_B(channel), val);
4964 nw64(RCRCFIG_A(channel),
4965 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4966 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4967 nw64(RCRCFIG_B(channel),
4968 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4969 RCRCFIG_B_ENTOUT |
4970 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4971
4972 err = niu_enable_rx_channel(np, channel, 1);
4973 if (err)
4974 return err;
4975
4976 nw64(RBR_KICK(channel), rp->rbr_index);
4977
4978 val = nr64(RX_DMA_CTL_STAT(channel));
4979 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4980 nw64(RX_DMA_CTL_STAT(channel), val);
4981
4982 return 0;
4983}
4984
4985static int niu_init_rx_channels(struct niu *np)
4986{
4987 unsigned long flags;
4988 u64 seed = jiffies_64;
4989 int err, i;
4990
4991 niu_lock_parent(np, flags);
4992 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4993 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4994 niu_unlock_parent(np, flags);
4995
4996 /* XXX RXDMA 32bit mode? XXX */
4997
4998 niu_init_rdc_groups(np);
4999 niu_init_drr_weight(np);
5000
5001 err = niu_init_hostinfo(np);
5002 if (err)
5003 return err;
5004
5005 for (i = 0; i < np->num_rx_rings; i++) {
5006 struct rx_ring_info *rp = &np->rx_rings[i];
5007
5008 err = niu_init_one_rx_channel(np, rp);
5009 if (err)
5010 return err;
5011 }
5012
5013 return 0;
5014}
5015
5016static int niu_set_ip_frag_rule(struct niu *np)
5017{
5018 struct niu_parent *parent = np->parent;
5019 struct niu_classifier *cp = &np->clas;
5020 struct niu_tcam_entry *tp;
5021 int index, err;
5022
2d96cf8c 5023 index = cp->tcam_top;
a3138df9
DM		 5024 tp = &parent->tcam[index];
5025
5026 /* Note that the noport bit is the same in both ipv4 and
5027 * ipv6 format TCAM entries.
5028 */
5029 memset(tp, 0, sizeof(*tp));
5030 tp->key[1] = TCAM_V4KEY1_NOPORT;
5031 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5032 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5033 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5034 err = tcam_write(np, index, tp->key, tp->key_mask);
5035 if (err)
5036 return err;
5037 err = tcam_assoc_write(np, index, tp->assoc_data);
5038 if (err)
5039 return err;
2d96cf8c
SB		 5040 tp->valid = 1;
5041 cp->tcam_valid_entries++;
a3138df9
DM		 5042
5043 return 0;
5044}
5045
5046static int niu_init_classifier_hw(struct niu *np)
5047{
5048 struct niu_parent *parent = np->parent;
5049 struct niu_classifier *cp = &np->clas;
5050 int i, err;
5051
5052 nw64(H1POLY, cp->h1_init);
5053 nw64(H2POLY, cp->h2_init);
5054
5055 err = niu_init_hostinfo(np);
5056 if (err)
5057 return err;
5058
5059 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5060 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5061
5062 vlan_tbl_write(np, i, np->port,
5063 vp->vlan_pref, vp->rdc_num);
5064 }
5065
5066 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5067 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5068
5069 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5070 ap->rdc_num, ap->mac_pref);
5071 if (err)
5072 return err;
5073 }
5074
5075 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5076 int index = i - CLASS_CODE_USER_PROG1;
5077
5078 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5079 if (err)
5080 return err;
5081 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5082 if (err)
5083 return err;
5084 }
5085
5086 err = niu_set_ip_frag_rule(np);
5087 if (err)
5088 return err;
5089
5090 tcam_enable(np, 1);
5091
5092 return 0;
5093}
5094
5095static int niu_zcp_write(struct niu *np, int index, u64 *data)
5096{
5097 nw64(ZCP_RAM_DATA0, data[0]);
5098 nw64(ZCP_RAM_DATA1, data[1]);
5099 nw64(ZCP_RAM_DATA2, data[2]);
5100 nw64(ZCP_RAM_DATA3, data[3]);
5101 nw64(ZCP_RAM_DATA4, data[4]);
5102 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5103 nw64(ZCP_RAM_ACC,
5104 (ZCP_RAM_ACC_WRITE |
5105 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5106 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5107
5108 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5109 1000, 100);
5110}
5111
5112static int niu_zcp_read(struct niu *np, int index, u64 *data)
5113{
5114 int err;
5115
5116 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5117 1000, 100);
5118 if (err) {
f10a1f2e
JP		 5119 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5120 (unsigned long long)nr64(ZCP_RAM_ACC));
a3138df9
DM		 5121 return err;
5122 }
5123
5124 nw64(ZCP_RAM_ACC,
5125 (ZCP_RAM_ACC_READ |
5126 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5127 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5128
5129 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5130 1000, 100);
5131 if (err) {
f10a1f2e
JP		 5132 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5133 (unsigned long long)nr64(ZCP_RAM_ACC));
a3138df9
DM		 5134 return err;
5135 }
5136
5137 data[0] = nr64(ZCP_RAM_DATA0);
5138 data[1] = nr64(ZCP_RAM_DATA1);
5139 data[2] = nr64(ZCP_RAM_DATA2);
5140 data[3] = nr64(ZCP_RAM_DATA3);
5141 data[4] = nr64(ZCP_RAM_DATA4);
5142
5143 return 0;
5144}
5145
5146static void niu_zcp_cfifo_reset(struct niu *np)
5147{
5148 u64 val = nr64(RESET_CFIFO);
5149
5150 val |= RESET_CFIFO_RST(np->port);
5151 nw64(RESET_CFIFO, val);
5152 udelay(10);
5153
5154 val &= ~RESET_CFIFO_RST(np->port);
5155 nw64(RESET_CFIFO, val);
5156}
5157
5158static int niu_init_zcp(struct niu *np)
5159{
5160 u64 data[5], rbuf[5];
5161 int i, max, err;
5162
5163 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5164 if (np->port == 0 || np->port == 1)
5165 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5166 else
5167 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5168 } else
5169 max = NIU_CFIFO_ENTRIES;
5170
5171 data[0] = 0;
5172 data[1] = 0;
5173 data[2] = 0;
5174 data[3] = 0;
5175 data[4] = 0;
5176
5177 for (i = 0; i < max; i++) {
5178 err = niu_zcp_write(np, i, data);
5179 if (err)
5180 return err;
5181 err = niu_zcp_read(np, i, rbuf);
5182 if (err)
5183 return err;
5184 }
5185
5186 niu_zcp_cfifo_reset(np);
5187 nw64(CFIFO_ECC(np->port), 0);
5188 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5189 (void) nr64(ZCP_INT_STAT);
5190 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5191
5192 return 0;
5193}
5194
5195static void niu_ipp_write(struct niu *np, int index, u64 *data)
5196{
5197 u64 val = nr64_ipp(IPP_CFIG);
5198
5199 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5200 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5201 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5202 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5203 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5204 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5205 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5206 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5207}
5208
5209static void niu_ipp_read(struct niu *np, int index, u64 *data)
5210{
5211 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5212 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5213 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5214 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5215 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5216 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5217}
5218
5219static int niu_ipp_reset(struct niu *np)
5220{
5221 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5222 1000, 100, "IPP_CFIG");
5223}
5224
5225static int niu_init_ipp(struct niu *np)
5226{
5227 u64 data[5], rbuf[5], val;
5228 int i, max, err;
5229
5230 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5231 if (np->port == 0 || np->port == 1)
5232 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5233 else
5234 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5235 } else
5236 max = NIU_DFIFO_ENTRIES;
5237
5238 data[0] = 0;
5239 data[1] = 0;
5240 data[2] = 0;
5241 data[3] = 0;
5242 data[4] = 0;
5243
5244 for (i = 0; i < max; i++) {
5245 niu_ipp_write(np, i, data);
5246 niu_ipp_read(np, i, rbuf);
5247 }
5248
5249 (void) nr64_ipp(IPP_INT_STAT);
5250 (void) nr64_ipp(IPP_INT_STAT);
5251
5252 err = niu_ipp_reset(np);
5253 if (err)
5254 return err;
5255
5256 (void) nr64_ipp(IPP_PKT_DIS);
5257 (void) nr64_ipp(IPP_BAD_CS_CNT);
5258 (void) nr64_ipp(IPP_ECC);
5259
5260 (void) nr64_ipp(IPP_INT_STAT);
5261
5262 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5263
5264 val = nr64_ipp(IPP_CFIG);
5265 val &= ~IPP_CFIG_IP_MAX_PKT;
5266 val |= (IPP_CFIG_IPP_ENABLE |
5267 IPP_CFIG_DFIFO_ECC_EN |
5268 IPP_CFIG_DROP_BAD_CRC |
5269 IPP_CFIG_CKSUM_EN |
5270 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5271 nw64_ipp(IPP_CFIG, val);
5272
5273 return 0;
5274}
5275
0c3b091b 5276static void niu_handle_led(struct niu *np, int status)
a3138df9 5277{
a3138df9 5278 u64 val;
a3138df9
DM		 5279 val = nr64_mac(XMAC_CONFIG);
5280
5281 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5282 (np->flags & NIU_FLAGS_FIBER) != 0) {
0c3b091b 5283 if (status) {
a3138df9
DM		 5284 val |= XMAC_CONFIG_LED_POLARITY;
5285 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5286 } else {
5287 val |= XMAC_CONFIG_FORCE_LED_ON;
5288 val &= ~XMAC_CONFIG_LED_POLARITY;
5289 }
5290 }
5291
0c3b091b
ML		 5292 nw64_mac(XMAC_CONFIG, val);
5293}
5294
5295static void niu_init_xif_xmac(struct niu *np)
5296{
5297 struct niu_link_config *lp = &np->link_config;
5298 u64 val;
5299
5fbd7e24
MW		 5300 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5301 val = nr64(MIF_CONFIG);
5302 val |= MIF_CONFIG_ATCA_GE;
5303 nw64(MIF_CONFIG, val);
5304 }
5305
0c3b091b 5306 val = nr64_mac(XMAC_CONFIG);
a3138df9
DM		 5307 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5308
5309 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5310
5311 if (lp->loopback_mode == LOOPBACK_MAC) {
5312 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5313 val |= XMAC_CONFIG_LOOPBACK;
5314 } else {
5315 val &= ~XMAC_CONFIG_LOOPBACK;
5316 }
5317
5318 if (np->flags & NIU_FLAGS_10G) {
5319 val &= ~XMAC_CONFIG_LFS_DISABLE;
5320 } else {
5321 val |= XMAC_CONFIG_LFS_DISABLE;
5fbd7e24
MW		 5322 if (!(np->flags & NIU_FLAGS_FIBER) &&
5323 !(np->flags & NIU_FLAGS_XCVR_SERDES))
a3138df9
DM		 5324 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5325 else
5326 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5327 }
5328
5329 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5330
5331 if (lp->active_speed == SPEED_100)
5332 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5333 else
5334 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5335
5336 nw64_mac(XMAC_CONFIG, val);
5337
5338 val = nr64_mac(XMAC_CONFIG);
5339 val &= ~XMAC_CONFIG_MODE_MASK;
5340 if (np->flags & NIU_FLAGS_10G) {
5341 val |= XMAC_CONFIG_MODE_XGMII;
5342 } else {
38bb045d 5343 if (lp->active_speed == SPEED_1000)
a3138df9 5344 val |= XMAC_CONFIG_MODE_GMII;
38bb045d
CB		 5345 else
5346 val |= XMAC_CONFIG_MODE_MII;
a3138df9
DM		 5347 }
5348
5349 nw64_mac(XMAC_CONFIG, val);
5350}
5351
5352static void niu_init_xif_bmac(struct niu *np)
5353{
5354 struct niu_link_config *lp = &np->link_config;
5355 u64 val;
5356
5357 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5358
5359 if (lp->loopback_mode == LOOPBACK_MAC)
5360 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5361 else
5362 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5363
5364 if (lp->active_speed == SPEED_1000)
5365 val |= BMAC_XIF_CONFIG_GMII_MODE;
5366 else
5367 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5368
5369 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5370 BMAC_XIF_CONFIG_LED_POLARITY);
5371
5372 if (!(np->flags & NIU_FLAGS_10G) &&
5373 !(np->flags & NIU_FLAGS_FIBER) &&
5374 lp->active_speed == SPEED_100)
5375 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5376 else
5377 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5378
5379 nw64_mac(BMAC_XIF_CONFIG, val);
5380}
5381
5382static void niu_init_xif(struct niu *np)
5383{
5384 if (np->flags & NIU_FLAGS_XMAC)
5385 niu_init_xif_xmac(np);
5386 else
5387 niu_init_xif_bmac(np);
5388}
5389
5390static void niu_pcs_mii_reset(struct niu *np)
5391{
5fbd7e24 5392 int limit = 1000;
a3138df9
DM		 5393 u64 val = nr64_pcs(PCS_MII_CTL);
5394 val |= PCS_MII_CTL_RST;
5395 nw64_pcs(PCS_MII_CTL, val);
5fbd7e24
MW		 5396 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5397 udelay(100);
5398 val = nr64_pcs(PCS_MII_CTL);
5399 }
a3138df9
DM		 5400}
5401
5402static void niu_xpcs_reset(struct niu *np)
5403{
5fbd7e24 5404 int limit = 1000;
a3138df9
DM		 5405 u64 val = nr64_xpcs(XPCS_CONTROL1);
5406 val |= XPCS_CONTROL1_RESET;
5407 nw64_xpcs(XPCS_CONTROL1, val);
5fbd7e24
MW		 5408 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5409 udelay(100);
5410 val = nr64_xpcs(XPCS_CONTROL1);
5411 }
a3138df9
DM		 5412}
5413
5414static int niu_init_pcs(struct niu *np)
5415{
5416 struct niu_link_config *lp = &np->link_config;
5417 u64 val;
5418
5fbd7e24
MW		 5419 switch (np->flags & (NIU_FLAGS_10G |
5420 NIU_FLAGS_FIBER |
5421 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 5422 case NIU_FLAGS_FIBER:
5423 /* 1G fiber */
5424 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5425 nw64_pcs(PCS_DPATH_MODE, 0);
5426 niu_pcs_mii_reset(np);
5427 break;
5428
5429 case NIU_FLAGS_10G:
5430 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5fbd7e24
MW		 5431 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5432 /* 10G SERDES */
a3138df9
DM		 5433 if (!(np->flags & NIU_FLAGS_XMAC))
5434 return -EINVAL;
5435
5436 /* 10G copper or fiber */
5437 val = nr64_mac(XMAC_CONFIG);
5438 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5439 nw64_mac(XMAC_CONFIG, val);
5440
5441 niu_xpcs_reset(np);
5442
5443 val = nr64_xpcs(XPCS_CONTROL1);
5444 if (lp->loopback_mode == LOOPBACK_PHY)
5445 val |= XPCS_CONTROL1_LOOPBACK;
5446 else
5447 val &= ~XPCS_CONTROL1_LOOPBACK;
5448 nw64_xpcs(XPCS_CONTROL1, val);
5449
5450 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5451 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5452 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5453 break;
5454
5fbd7e24
MW		 5455
5456 case NIU_FLAGS_XCVR_SERDES:
5457 /* 1G SERDES */
5458 niu_pcs_mii_reset(np);
5459 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5460 nw64_pcs(PCS_DPATH_MODE, 0);
5461 break;
5462
a3138df9
DM		 5463 case 0:
5464 /* 1G copper */
5fbd7e24
MW		 5465 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5466 /* 1G RGMII FIBER */
a3138df9
DM		 5467 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5468 niu_pcs_mii_reset(np);
5469 break;
5470
5471 default:
5472 return -EINVAL;
5473 }
5474
5475 return 0;
5476}
5477
5478static int niu_reset_tx_xmac(struct niu *np)
5479{
5480 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5481 (XTXMAC_SW_RST_REG_RS |
5482 XTXMAC_SW_RST_SOFT_RST),
5483 1000, 100, "XTXMAC_SW_RST");
5484}
5485
5486static int niu_reset_tx_bmac(struct niu *np)
5487{
5488 int limit;
5489
5490 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5491 limit = 1000;
5492 while (--limit >= 0) {
5493 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5494 break;
5495 udelay(100);
5496 }
5497 if (limit < 0) {
f10a1f2e 5498 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5499 np->port,
5500 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5501 return -ENODEV;
5502 }
5503
5504 return 0;
5505}
5506
5507static int niu_reset_tx_mac(struct niu *np)
5508{
5509 if (np->flags & NIU_FLAGS_XMAC)
5510 return niu_reset_tx_xmac(np);
5511 else
5512 return niu_reset_tx_bmac(np);
5513}
5514
5515static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5516{
5517 u64 val;
5518
5519 val = nr64_mac(XMAC_MIN);
5520 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5521 XMAC_MIN_RX_MIN_PKT_SIZE);
5522 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5523 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5524 nw64_mac(XMAC_MIN, val);
5525
5526 nw64_mac(XMAC_MAX, max);
5527
5528 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5529
5530 val = nr64_mac(XMAC_IPG);
5531 if (np->flags & NIU_FLAGS_10G) {
5532 val &= ~XMAC_IPG_IPG_XGMII;
5533 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5534 } else {
5535 val &= ~XMAC_IPG_IPG_MII_GMII;
5536 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5537 }
5538 nw64_mac(XMAC_IPG, val);
5539
5540 val = nr64_mac(XMAC_CONFIG);
5541 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5542 XMAC_CONFIG_STRETCH_MODE |
5543 XMAC_CONFIG_VAR_MIN_IPG_EN |
5544 XMAC_CONFIG_TX_ENABLE);
5545 nw64_mac(XMAC_CONFIG, val);
5546
5547 nw64_mac(TXMAC_FRM_CNT, 0);
5548 nw64_mac(TXMAC_BYTE_CNT, 0);
5549}
5550
5551static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5552{
5553 u64 val;
5554
5555 nw64_mac(BMAC_MIN_FRAME, min);
5556 nw64_mac(BMAC_MAX_FRAME, max);
5557
5558 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5559 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5560 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5561
5562 val = nr64_mac(BTXMAC_CONFIG);
5563 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5564 BTXMAC_CONFIG_ENABLE);
5565 nw64_mac(BTXMAC_CONFIG, val);
5566}
5567
5568static void niu_init_tx_mac(struct niu *np)
5569{
5570 u64 min, max;
5571
5572 min = 64;
5573 if (np->dev->mtu > ETH_DATA_LEN)
5574 max = 9216;
5575 else
5576 max = 1522;
5577
5578 /* The XMAC_MIN register only accepts values for TX min which
5579 * have the low 3 bits cleared.
5580 */
8c87df45 5581 BUG_ON(min & 0x7);
a3138df9
DM		 5582
5583 if (np->flags & NIU_FLAGS_XMAC)
5584 niu_init_tx_xmac(np, min, max);
5585 else
5586 niu_init_tx_bmac(np, min, max);
5587}
5588
5589static int niu_reset_rx_xmac(struct niu *np)
5590{
5591 int limit;
5592
5593 nw64_mac(XRXMAC_SW_RST,
5594 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5595 limit = 1000;
5596 while (--limit >= 0) {
5597 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5598 XRXMAC_SW_RST_SOFT_RST)))
f10a1f2e 5599 break;
a3138df9
DM		 5600 udelay(100);
5601 }
5602 if (limit < 0) {
f10a1f2e 5603 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5604 np->port,
5605 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5606 return -ENODEV;
5607 }
5608
5609 return 0;
5610}
5611
5612static int niu_reset_rx_bmac(struct niu *np)
5613{
5614 int limit;
5615
5616 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5617 limit = 1000;
5618 while (--limit >= 0) {
5619 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5620 break;
5621 udelay(100);
5622 }
5623 if (limit < 0) {
f10a1f2e 5624 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5625 np->port,
5626 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5627 return -ENODEV;
5628 }
5629
5630 return 0;
5631}
5632
5633static int niu_reset_rx_mac(struct niu *np)
5634{
5635 if (np->flags & NIU_FLAGS_XMAC)
5636 return niu_reset_rx_xmac(np);
5637 else
5638 return niu_reset_rx_bmac(np);
5639}
5640
5641static void niu_init_rx_xmac(struct niu *np)
5642{
5643 struct niu_parent *parent = np->parent;
5644 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5645 int first_rdc_table = tp->first_table_num;
5646 unsigned long i;
5647 u64 val;
5648
5649 nw64_mac(XMAC_ADD_FILT0, 0);
5650 nw64_mac(XMAC_ADD_FILT1, 0);
5651 nw64_mac(XMAC_ADD_FILT2, 0);
5652 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5653 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5654 for (i = 0; i < MAC_NUM_HASH; i++)
5655 nw64_mac(XMAC_HASH_TBL(i), 0);
5656 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5657 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5658 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5659
5660 val = nr64_mac(XMAC_CONFIG);
5661 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5662 XMAC_CONFIG_PROMISCUOUS |
5663 XMAC_CONFIG_PROMISC_GROUP |
5664 XMAC_CONFIG_ERR_CHK_DIS |
5665 XMAC_CONFIG_RX_CRC_CHK_DIS |
5666 XMAC_CONFIG_RESERVED_MULTICAST |
5667 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5668 XMAC_CONFIG_ADDR_FILTER_EN |
5669 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5670 XMAC_CONFIG_STRIP_CRC |
5671 XMAC_CONFIG_PASS_FLOW_CTRL |
5672 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5673 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5674 nw64_mac(XMAC_CONFIG, val);
5675
5676 nw64_mac(RXMAC_BT_CNT, 0);
5677 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5678 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5679 nw64_mac(RXMAC_FRAG_CNT, 0);
5680 nw64_mac(RXMAC_HIST_CNT1, 0);
5681 nw64_mac(RXMAC_HIST_CNT2, 0);
5682 nw64_mac(RXMAC_HIST_CNT3, 0);
5683 nw64_mac(RXMAC_HIST_CNT4, 0);
5684 nw64_mac(RXMAC_HIST_CNT5, 0);
5685 nw64_mac(RXMAC_HIST_CNT6, 0);
5686 nw64_mac(RXMAC_HIST_CNT7, 0);
5687 nw64_mac(RXMAC_MPSZER_CNT, 0);
5688 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5689 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5690 nw64_mac(LINK_FAULT_CNT, 0);
5691}
5692
5693static void niu_init_rx_bmac(struct niu *np)
5694{
5695 struct niu_parent *parent = np->parent;
5696 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5697 int first_rdc_table = tp->first_table_num;
5698 unsigned long i;
5699 u64 val;
5700
5701 nw64_mac(BMAC_ADD_FILT0, 0);
5702 nw64_mac(BMAC_ADD_FILT1, 0);
5703 nw64_mac(BMAC_ADD_FILT2, 0);
5704 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5705 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5706 for (i = 0; i < MAC_NUM_HASH; i++)
5707 nw64_mac(BMAC_HASH_TBL(i), 0);
5708 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5709 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5710 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5711
5712 val = nr64_mac(BRXMAC_CONFIG);
5713 val &= ~(BRXMAC_CONFIG_ENABLE |
5714 BRXMAC_CONFIG_STRIP_PAD |
5715 BRXMAC_CONFIG_STRIP_FCS |
5716 BRXMAC_CONFIG_PROMISC |
5717 BRXMAC_CONFIG_PROMISC_GRP |
5718 BRXMAC_CONFIG_ADDR_FILT_EN |
5719 BRXMAC_CONFIG_DISCARD_DIS);
5720 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5721 nw64_mac(BRXMAC_CONFIG, val);
5722
5723 val = nr64_mac(BMAC_ADDR_CMPEN);
5724 val |= BMAC_ADDR_CMPEN_EN0;
5725 nw64_mac(BMAC_ADDR_CMPEN, val);
5726}
5727
5728static void niu_init_rx_mac(struct niu *np)
5729{
5730 niu_set_primary_mac(np, np->dev->dev_addr);
5731
5732 if (np->flags & NIU_FLAGS_XMAC)
5733 niu_init_rx_xmac(np);
5734 else
5735 niu_init_rx_bmac(np);
5736}
5737
5738static void niu_enable_tx_xmac(struct niu *np, int on)
5739{
5740 u64 val = nr64_mac(XMAC_CONFIG);
5741
5742 if (on)
5743 val |= XMAC_CONFIG_TX_ENABLE;
5744 else
5745 val &= ~XMAC_CONFIG_TX_ENABLE;
5746 nw64_mac(XMAC_CONFIG, val);
5747}
5748
5749static void niu_enable_tx_bmac(struct niu *np, int on)
5750{
5751 u64 val = nr64_mac(BTXMAC_CONFIG);
5752
5753 if (on)
5754 val |= BTXMAC_CONFIG_ENABLE;
5755 else
5756 val &= ~BTXMAC_CONFIG_ENABLE;
5757 nw64_mac(BTXMAC_CONFIG, val);
5758}
5759
5760static void niu_enable_tx_mac(struct niu *np, int on)
5761{
5762 if (np->flags & NIU_FLAGS_XMAC)
5763 niu_enable_tx_xmac(np, on);
5764 else
5765 niu_enable_tx_bmac(np, on);
5766}
5767
5768static void niu_enable_rx_xmac(struct niu *np, int on)
5769{
5770 u64 val = nr64_mac(XMAC_CONFIG);
5771
5772 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5773 XMAC_CONFIG_PROMISCUOUS);
5774
5775 if (np->flags & NIU_FLAGS_MCAST)
5776 val |= XMAC_CONFIG_HASH_FILTER_EN;
5777 if (np->flags & NIU_FLAGS_PROMISC)
5778 val |= XMAC_CONFIG_PROMISCUOUS;
5779
5780 if (on)
5781 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5782 else
5783 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5784 nw64_mac(XMAC_CONFIG, val);
5785}
5786
5787static void niu_enable_rx_bmac(struct niu *np, int on)
5788{
5789 u64 val = nr64_mac(BRXMAC_CONFIG);
5790
5791 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5792 BRXMAC_CONFIG_PROMISC);
5793
5794 if (np->flags & NIU_FLAGS_MCAST)
5795 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5796 if (np->flags & NIU_FLAGS_PROMISC)
5797 val |= BRXMAC_CONFIG_PROMISC;
5798
5799 if (on)
5800 val |= BRXMAC_CONFIG_ENABLE;
5801 else
5802 val &= ~BRXMAC_CONFIG_ENABLE;
5803 nw64_mac(BRXMAC_CONFIG, val);
5804}
5805
5806static void niu_enable_rx_mac(struct niu *np, int on)
5807{
5808 if (np->flags & NIU_FLAGS_XMAC)
5809 niu_enable_rx_xmac(np, on);
5810 else
5811 niu_enable_rx_bmac(np, on);
5812}
5813
5814static int niu_init_mac(struct niu *np)
5815{
5816 int err;
5817
5818 niu_init_xif(np);
5819 err = niu_init_pcs(np);
5820 if (err)
5821 return err;
5822
5823 err = niu_reset_tx_mac(np);
5824 if (err)
5825 return err;
5826 niu_init_tx_mac(np);
5827 err = niu_reset_rx_mac(np);
5828 if (err)
5829 return err;
5830 niu_init_rx_mac(np);
5831
5832 /* This looks hookey but the RX MAC reset we just did will
5833 * undo some of the state we setup in niu_init_tx_mac() so we
5834 * have to call it again. In particular, the RX MAC reset will
5835 * set the XMAC_MAX register back to it's default value.
5836 */
5837 niu_init_tx_mac(np);
5838 niu_enable_tx_mac(np, 1);
5839
5840 niu_enable_rx_mac(np, 1);
5841
5842 return 0;
5843}
5844
5845static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5846{
5847 (void) niu_tx_channel_stop(np, rp->tx_channel);
5848}
5849
5850static void niu_stop_tx_channels(struct niu *np)
5851{
5852 int i;
5853
5854 for (i = 0; i < np->num_tx_rings; i++) {
5855 struct tx_ring_info *rp = &np->tx_rings[i];
5856
5857 niu_stop_one_tx_channel(np, rp);
5858 }
5859}
5860
5861static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5862{
5863 (void) niu_tx_channel_reset(np, rp->tx_channel);
5864}
5865
5866static void niu_reset_tx_channels(struct niu *np)
5867{
5868 int i;
5869
5870 for (i = 0; i < np->num_tx_rings; i++) {
5871 struct tx_ring_info *rp = &np->tx_rings[i];
5872
5873 niu_reset_one_tx_channel(np, rp);
5874 }
5875}
5876
5877static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5878{
5879 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5880}
5881
5882static void niu_stop_rx_channels(struct niu *np)
5883{
5884 int i;
5885
5886 for (i = 0; i < np->num_rx_rings; i++) {
5887 struct rx_ring_info *rp = &np->rx_rings[i];
5888
5889 niu_stop_one_rx_channel(np, rp);
5890 }
5891}
5892
5893static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5894{
5895 int channel = rp->rx_channel;
5896
5897 (void) niu_rx_channel_reset(np, channel);
5898 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5899 nw64(RX_DMA_CTL_STAT(channel), 0);
5900 (void) niu_enable_rx_channel(np, channel, 0);
5901}
5902
5903static void niu_reset_rx_channels(struct niu *np)
5904{
5905 int i;
5906
5907 for (i = 0; i < np->num_rx_rings; i++) {
5908 struct rx_ring_info *rp = &np->rx_rings[i];
5909
5910 niu_reset_one_rx_channel(np, rp);
5911 }
5912}
5913
5914static void niu_disable_ipp(struct niu *np)
5915{
5916 u64 rd, wr, val;
5917 int limit;
5918
5919 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5920 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5921 limit = 100;
5922 while (--limit >= 0 && (rd != wr)) {
5923 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5924 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5925 }
5926 if (limit < 0 &&
5927 (rd != 0 && wr != 1)) {
f10a1f2e
JP		 5928 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5929 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5930 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
a3138df9
DM		 5931 }
5932
5933 val = nr64_ipp(IPP_CFIG);
5934 val &= ~(IPP_CFIG_IPP_ENABLE |
5935 IPP_CFIG_DFIFO_ECC_EN |
5936 IPP_CFIG_DROP_BAD_CRC |
5937 IPP_CFIG_CKSUM_EN);
5938 nw64_ipp(IPP_CFIG, val);
5939
5940 (void) niu_ipp_reset(np);
5941}
5942
5943static int niu_init_hw(struct niu *np)
5944{
5945 int i, err;
5946
f10a1f2e 5947 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
a3138df9
DM		 5948 niu_txc_enable_port(np, 1);
5949 niu_txc_port_dma_enable(np, 1);
5950 niu_txc_set_imask(np, 0);
5951
f10a1f2e 5952 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
a3138df9
DM		 5953 for (i = 0; i < np->num_tx_rings; i++) {
5954 struct tx_ring_info *rp = &np->tx_rings[i];
5955
5956 err = niu_init_one_tx_channel(np, rp);
5957 if (err)
5958 return err;
5959 }
5960
f10a1f2e 5961 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
a3138df9
DM		 5962 err = niu_init_rx_channels(np);
5963 if (err)
5964 goto out_uninit_tx_channels;
5965
f10a1f2e 5966 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
a3138df9
DM		 5967 err = niu_init_classifier_hw(np);
5968 if (err)
5969 goto out_uninit_rx_channels;
5970
f10a1f2e 5971 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
a3138df9
DM		 5972 err = niu_init_zcp(np);
5973 if (err)
5974 goto out_uninit_rx_channels;
5975
f10a1f2e 5976 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
a3138df9
DM		 5977 err = niu_init_ipp(np);
5978 if (err)
5979 goto out_uninit_rx_channels;
5980
f10a1f2e 5981 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
a3138df9
DM		 5982 err = niu_init_mac(np);
5983 if (err)
5984 goto out_uninit_ipp;
5985
5986 return 0;
5987
5988out_uninit_ipp:
f10a1f2e 5989 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
a3138df9
DM		 5990 niu_disable_ipp(np);
5991
5992out_uninit_rx_channels:
f10a1f2e 5993 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
a3138df9
DM		 5994 niu_stop_rx_channels(np);
5995 niu_reset_rx_channels(np);
5996
5997out_uninit_tx_channels:
f10a1f2e 5998 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
a3138df9
DM		 5999 niu_stop_tx_channels(np);
6000 niu_reset_tx_channels(np);
6001
6002 return err;
6003}
6004
6005static void niu_stop_hw(struct niu *np)
6006{
f10a1f2e 6007 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
a3138df9
DM		 6008 niu_enable_interrupts(np, 0);
6009
f10a1f2e 6010 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
a3138df9
DM		 6011 niu_enable_rx_mac(np, 0);
6012
f10a1f2e 6013 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
a3138df9
DM		 6014 niu_disable_ipp(np);
6015
f10a1f2e 6016 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
a3138df9
DM		 6017 niu_stop_tx_channels(np);
6018
f10a1f2e 6019 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
a3138df9
DM		 6020 niu_stop_rx_channels(np);
6021
f10a1f2e 6022 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
a3138df9
DM		 6023 niu_reset_tx_channels(np);
6024
f10a1f2e 6025 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
a3138df9
DM		 6026 niu_reset_rx_channels(np);
6027}
6028
70340d72
RO		 6029static void niu_set_irq_name(struct niu *np)
6030{
6031 int port = np->port;
6032 int i, j = 1;
6033
6034 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6035
6036 if (port == 0) {
6037 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6038 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6039 j = 3;
6040 }
6041
6042 for (i = 0; i < np->num_ldg - j; i++) {
6043 if (i < np->num_rx_rings)
6044 sprintf(np->irq_name[i+j], "%s-rx-%d",
6045 np->dev->name, i);
6046 else if (i < np->num_tx_rings + np->num_rx_rings)
6047 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6048 i - np->num_rx_rings);
6049 }
6050}
6051
a3138df9
DM		 6052static int niu_request_irq(struct niu *np)
6053{
6054 int i, j, err;
6055
70340d72
RO		 6056 niu_set_irq_name(np);
6057
a3138df9
DM		 6058 err = 0;
6059 for (i = 0; i < np->num_ldg; i++) {
6060 struct niu_ldg *lp = &np->ldg[i];
6061
6062 err = request_irq(lp->irq, niu_interrupt,
6063 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
70340d72 6064 np->irq_name[i], lp);
a3138df9
DM		 6065 if (err)
6066 goto out_free_irqs;
6067
6068 }
6069
6070 return 0;
6071
6072out_free_irqs:
6073 for (j = 0; j < i; j++) {
6074 struct niu_ldg *lp = &np->ldg[j];
6075
6076 free_irq(lp->irq, lp);
6077 }
6078 return err;
6079}
6080
6081static void niu_free_irq(struct niu *np)
6082{
6083 int i;
6084
6085 for (i = 0; i < np->num_ldg; i++) {
6086 struct niu_ldg *lp = &np->ldg[i];
6087
6088 free_irq(lp->irq, lp);
6089 }
6090}
6091
6092static void niu_enable_napi(struct niu *np)
6093{
6094 int i;
6095
6096 for (i = 0; i < np->num_ldg; i++)
6097 napi_enable(&np->ldg[i].napi);
6098}
6099
6100static void niu_disable_napi(struct niu *np)
6101{
6102 int i;
6103
6104 for (i = 0; i < np->num_ldg; i++)
6105 napi_disable(&np->ldg[i].napi);
6106}
6107
6108static int niu_open(struct net_device *dev)
6109{
6110 struct niu *np = netdev_priv(dev);
6111 int err;
6112
6113 netif_carrier_off(dev);
6114
6115 err = niu_alloc_channels(np);
6116 if (err)
6117 goto out_err;
6118
6119 err = niu_enable_interrupts(np, 0);
6120 if (err)
6121 goto out_free_channels;
6122
6123 err = niu_request_irq(np);
6124 if (err)
6125 goto out_free_channels;
6126
6127 niu_enable_napi(np);
6128
6129 spin_lock_irq(&np->lock);
6130
6131 err = niu_init_hw(np);
6132 if (!err) {
6133 init_timer(&np->timer);
6134 np->timer.expires = jiffies + HZ;
6135 np->timer.data = (unsigned long) np;
6136 np->timer.function = niu_timer;
6137
6138 err = niu_enable_interrupts(np, 1);
6139 if (err)
6140 niu_stop_hw(np);
6141 }
6142
6143 spin_unlock_irq(&np->lock);
6144
6145 if (err) {
6146 niu_disable_napi(np);
6147 goto out_free_irq;
6148 }
6149
b4c21639 6150 netif_tx_start_all_queues(dev);
a3138df9
DM		 6151
6152 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6153 netif_carrier_on(dev);
6154
6155 add_timer(&np->timer);
6156
6157 return 0;
6158
6159out_free_irq:
6160 niu_free_irq(np);
6161
6162out_free_channels:
6163 niu_free_channels(np);
6164
6165out_err:
6166 return err;
6167}
6168
6169static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6170{
6171 cancel_work_sync(&np->reset_task);
6172
6173 niu_disable_napi(np);
b4c21639 6174 netif_tx_stop_all_queues(dev);
a3138df9
DM		 6175
6176 del_timer_sync(&np->timer);
6177
6178 spin_lock_irq(&np->lock);
6179
6180 niu_stop_hw(np);
6181
6182 spin_unlock_irq(&np->lock);
6183}
6184
6185static int niu_close(struct net_device *dev)
6186{
6187 struct niu *np = netdev_priv(dev);
6188
6189 niu_full_shutdown(np, dev);
6190
6191 niu_free_irq(np);
6192
6193 niu_free_channels(np);
6194
0c3b091b
ML		 6195 niu_handle_led(np, 0);
6196
a3138df9
DM		 6197 return 0;
6198}
6199
6200static void niu_sync_xmac_stats(struct niu *np)
6201{
6202 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6203
6204 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6205 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6206
6207 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6208 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6209 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6210 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6211 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6212 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6213 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6214 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6215 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6216 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6217 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6218 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6219 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6220 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6221 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6222 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6223}
6224
6225static void niu_sync_bmac_stats(struct niu *np)
6226{
6227 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6228
6229 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6230 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6231
6232 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6233 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6234 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6235 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6236}
6237
6238static void niu_sync_mac_stats(struct niu *np)
6239{
6240 if (np->flags & NIU_FLAGS_XMAC)
6241 niu_sync_xmac_stats(np);
6242 else
6243 niu_sync_bmac_stats(np);
6244}
6245
6246static void niu_get_rx_stats(struct niu *np)
6247{
6248 unsigned long pkts, dropped, errors, bytes;
6249 int i;
6250
6251 pkts = dropped = errors = bytes = 0;
6252 for (i = 0; i < np->num_rx_rings; i++) {
6253 struct rx_ring_info *rp = &np->rx_rings[i];
6254
b8a606b8
JDB		 6255 niu_sync_rx_discard_stats(np, rp, 0);
6256
a3138df9
DM		 6257 pkts += rp->rx_packets;
6258 bytes += rp->rx_bytes;
6259 dropped += rp->rx_dropped;
6260 errors += rp->rx_errors;
6261 }
9fd42876
IJ		 6262 np->dev->stats.rx_packets = pkts;
6263 np->dev->stats.rx_bytes = bytes;
6264 np->dev->stats.rx_dropped = dropped;
6265 np->dev->stats.rx_errors = errors;
a3138df9
DM		 6266}
6267
6268static void niu_get_tx_stats(struct niu *np)
6269{
6270 unsigned long pkts, errors, bytes;
6271 int i;
6272
6273 pkts = errors = bytes = 0;
6274 for (i = 0; i < np->num_tx_rings; i++) {
6275 struct tx_ring_info *rp = &np->tx_rings[i];
6276
6277 pkts += rp->tx_packets;
6278 bytes += rp->tx_bytes;
6279 errors += rp->tx_errors;
6280 }
9fd42876
IJ		 6281 np->dev->stats.tx_packets = pkts;
6282 np->dev->stats.tx_bytes = bytes;
6283 np->dev->stats.tx_errors = errors;
a3138df9
DM		 6284}
6285
6286static struct net_device_stats *niu_get_stats(struct net_device *dev)
6287{
6288 struct niu *np = netdev_priv(dev);
6289
6290 niu_get_rx_stats(np);
6291 niu_get_tx_stats(np);
6292
9fd42876 6293 return &dev->stats;
a3138df9
DM		 6294}
6295
6296static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6297{
6298 int i;
6299
6300 for (i = 0; i < 16; i++)
6301 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6302}
6303
6304static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6305{
6306 int i;
6307
6308 for (i = 0; i < 16; i++)
6309 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6310}
6311
6312static void niu_load_hash(struct niu *np, u16 *hash)
6313{
6314 if (np->flags & NIU_FLAGS_XMAC)
6315 niu_load_hash_xmac(np, hash);
6316 else
6317 niu_load_hash_bmac(np, hash);
6318}
6319
6320static void niu_set_rx_mode(struct net_device *dev)
6321{
6322 struct niu *np = netdev_priv(dev);
6323 int i, alt_cnt, err;
ccffad25 6324 struct netdev_hw_addr *ha;
a3138df9
DM		 6325 unsigned long flags;
6326 u16 hash[16] = { 0, };
6327
6328 spin_lock_irqsave(&np->lock, flags);
6329 niu_enable_rx_mac(np, 0);
6330
6331 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6332 if (dev->flags & IFF_PROMISC)
6333 np->flags |= NIU_FLAGS_PROMISC;
4cd24eaf 6334 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
a3138df9
DM		 6335 np->flags |= NIU_FLAGS_MCAST;
6336
32e7bfc4 6337 alt_cnt = netdev_uc_count(dev);
a3138df9
DM		 6338 if (alt_cnt > niu_num_alt_addr(np)) {
6339 alt_cnt = 0;
6340 np->flags |= NIU_FLAGS_PROMISC;
6341 }
6342
6343 if (alt_cnt) {
6344 int index = 0;
6345
32e7bfc4 6346 netdev_for_each_uc_addr(ha, dev) {
ccffad25 6347 err = niu_set_alt_mac(np, index, ha->addr);
a3138df9 6348 if (err)
f10a1f2e
JP		 6349 netdev_warn(dev, "Error %d adding alt mac %d\n",
6350 err, index);
a3138df9
DM		 6351 err = niu_enable_alt_mac(np, index, 1);
6352 if (err)
f10a1f2e
JP		 6353 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6354 err, index);
a3138df9
DM		 6355
6356 index++;
6357 }
6358 } else {
3b5bcede
MW		 6359 int alt_start;
6360 if (np->flags & NIU_FLAGS_XMAC)
6361 alt_start = 0;
6362 else
6363 alt_start = 1;
6364 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
a3138df9
DM		 6365 err = niu_enable_alt_mac(np, i, 0);
6366 if (err)
f10a1f2e
JP		 6367 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6368 err, i);
a3138df9
DM		 6369 }
6370 }
6371 if (dev->flags & IFF_ALLMULTI) {
6372 for (i = 0; i < 16; i++)
6373 hash[i] = 0xffff;
4cd24eaf 6374 } else if (!netdev_mc_empty(dev)) {
22bedad3
JP		 6375 netdev_for_each_mc_addr(ha, dev) {
6376 u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
a3138df9
DM		 6377
6378 crc >>= 24;
6379 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6380 }
6381 }
6382
6383 if (np->flags & NIU_FLAGS_MCAST)
6384 niu_load_hash(np, hash);
6385
6386 niu_enable_rx_mac(np, 1);
6387 spin_unlock_irqrestore(&np->lock, flags);
6388}
6389
6390static int niu_set_mac_addr(struct net_device *dev, void *p)
6391{
6392 struct niu *np = netdev_priv(dev);
6393 struct sockaddr *addr = p;
6394 unsigned long flags;
6395
6396 if (!is_valid_ether_addr(addr->sa_data))
6397 return -EINVAL;
6398
6399 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6400
6401 if (!netif_running(dev))
6402 return 0;
6403
6404 spin_lock_irqsave(&np->lock, flags);
6405 niu_enable_rx_mac(np, 0);
6406 niu_set_primary_mac(np, dev->dev_addr);
6407 niu_enable_rx_mac(np, 1);
6408 spin_unlock_irqrestore(&np->lock, flags);
6409
6410 return 0;
6411}
6412
6413static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6414{
6415 return -EOPNOTSUPP;
6416}
6417
6418static void niu_netif_stop(struct niu *np)
6419{
6420 np->dev->trans_start = jiffies; /* prevent tx timeout */
6421
6422 niu_disable_napi(np);
6423
6424 netif_tx_disable(np->dev);
6425}
6426
6427static void niu_netif_start(struct niu *np)
6428{
6429 /* NOTE: unconditional netif_wake_queue is only appropriate
6430 * so long as all callers are assured to have free tx slots
6431 * (such as after niu_init_hw).
6432 */
b4c21639 6433 netif_tx_wake_all_queues(np->dev);
a3138df9
DM		 6434
6435 niu_enable_napi(np);
6436
6437 niu_enable_interrupts(np, 1);
6438}
6439
cff502a3
SB		 6440static void niu_reset_buffers(struct niu *np)
6441{
6442 int i, j, k, err;
6443
6444 if (np->rx_rings) {
6445 for (i = 0; i < np->num_rx_rings; i++) {
6446 struct rx_ring_info *rp = &np->rx_rings[i];
6447
6448 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6449 struct page *page;
6450
6451 page = rp->rxhash[j];
6452 while (page) {
6453 struct page *next =
6454 (struct page *) page->mapping;
6455 u64 base = page->index;
6456 base = base >> RBR_DESCR_ADDR_SHIFT;
6457 rp->rbr[k++] = cpu_to_le32(base);
6458 page = next;
6459 }
6460 }
6461 for (; k < MAX_RBR_RING_SIZE; k++) {
6462 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6463 if (unlikely(err))
6464 break;
6465 }
6466
6467 rp->rbr_index = rp->rbr_table_size - 1;
6468 rp->rcr_index = 0;
6469 rp->rbr_pending = 0;
6470 rp->rbr_refill_pending = 0;
6471 }
6472 }
6473 if (np->tx_rings) {
6474 for (i = 0; i < np->num_tx_rings; i++) {
6475 struct tx_ring_info *rp = &np->tx_rings[i];
6476
6477 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6478 if (rp->tx_buffs[j].skb)
6479 (void) release_tx_packet(np, rp, j);
6480 }
6481
6482 rp->pending = MAX_TX_RING_SIZE;
6483 rp->prod = 0;
6484 rp->cons = 0;
6485 rp->wrap_bit = 0;
6486 }
6487 }
6488}
6489
a3138df9
DM		 6490static void niu_reset_task(struct work_struct *work)
6491{
6492 struct niu *np = container_of(work, struct niu, reset_task);
6493 unsigned long flags;
6494 int err;
6495
6496 spin_lock_irqsave(&np->lock, flags);
6497 if (!netif_running(np->dev)) {
6498 spin_unlock_irqrestore(&np->lock, flags);
6499 return;
6500 }
6501
6502 spin_unlock_irqrestore(&np->lock, flags);
6503
6504 del_timer_sync(&np->timer);
6505
6506 niu_netif_stop(np);
6507
6508 spin_lock_irqsave(&np->lock, flags);
6509
6510 niu_stop_hw(np);
6511
cff502a3
SB		 6512 spin_unlock_irqrestore(&np->lock, flags);
6513
6514 niu_reset_buffers(np);
6515
6516 spin_lock_irqsave(&np->lock, flags);
6517
a3138df9
DM		 6518 err = niu_init_hw(np);
6519 if (!err) {
6520 np->timer.expires = jiffies + HZ;
6521 add_timer(&np->timer);
6522 niu_netif_start(np);
6523 }
6524
6525 spin_unlock_irqrestore(&np->lock, flags);
6526}
6527
6528static void niu_tx_timeout(struct net_device *dev)
6529{
6530 struct niu *np = netdev_priv(dev);
6531
f10a1f2e 6532 dev_err(np->device, "%s: Transmit timed out, resetting\n",
a3138df9
DM		 6533 dev->name);
6534
6535 schedule_work(&np->reset_task);
6536}
6537
6538static void niu_set_txd(struct tx_ring_info *rp, int index,
6539 u64 mapping, u64 len, u64 mark,
6540 u64 n_frags)
6541{
6542 __le64 *desc = &rp->descr[index];
6543
6544 *desc = cpu_to_le64(mark |
6545 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6546 (len << TX_DESC_TR_LEN_SHIFT) |
6547 (mapping & TX_DESC_SAD));
6548}
6549
6550static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6551 u64 pad_bytes, u64 len)
6552{
6553 u16 eth_proto, eth_proto_inner;
6554 u64 csum_bits, l3off, ihl, ret;
6555 u8 ip_proto;
6556 int ipv6;
6557
6558 eth_proto = be16_to_cpu(ehdr->h_proto);
6559 eth_proto_inner = eth_proto;
6560 if (eth_proto == ETH_P_8021Q) {
6561 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6562 __be16 val = vp->h_vlan_encapsulated_proto;
6563
6564 eth_proto_inner = be16_to_cpu(val);
6565 }
6566
6567 ipv6 = ihl = 0;
6568 switch (skb->protocol) {
09640e63 6569 case cpu_to_be16(ETH_P_IP):
a3138df9
DM		 6570 ip_proto = ip_hdr(skb)->protocol;
6571 ihl = ip_hdr(skb)->ihl;
6572 break;
09640e63 6573 case cpu_to_be16(ETH_P_IPV6):
a3138df9
DM		 6574 ip_proto = ipv6_hdr(skb)->nexthdr;
6575 ihl = (40 >> 2);
6576 ipv6 = 1;
6577 break;
6578 default:
6579 ip_proto = ihl = 0;
6580 break;
6581 }
6582
6583 csum_bits = TXHDR_CSUM_NONE;
6584 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6585 u64 start, stuff;
6586
6587 csum_bits = (ip_proto == IPPROTO_TCP ?
6588 TXHDR_CSUM_TCP :
6589 (ip_proto == IPPROTO_UDP ?
6590 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6591
6592 start = skb_transport_offset(skb) -
6593 (pad_bytes + sizeof(struct tx_pkt_hdr));
6594 stuff = start + skb->csum_offset;
6595
6596 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6597 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6598 }
6599
6600 l3off = skb_network_offset(skb) -
6601 (pad_bytes + sizeof(struct tx_pkt_hdr));
6602
6603 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6604 (len << TXHDR_LEN_SHIFT) |
6605 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6606 (ihl << TXHDR_IHL_SHIFT) |
6607 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6608 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6609 (ipv6 ? TXHDR_IP_VER : 0) |
6610 csum_bits);
6611
6612 return ret;
6613}
6614
61357325
SH		 6615static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6616 struct net_device *dev)
a3138df9
DM		 6617{
6618 struct niu *np = netdev_priv(dev);
6619 unsigned long align, headroom;
b4c21639 6620 struct netdev_queue *txq;
a3138df9
DM		 6621 struct tx_ring_info *rp;
6622 struct tx_pkt_hdr *tp;
6623 unsigned int len, nfg;
6624 struct ethhdr *ehdr;
6625 int prod, i, tlen;
6626 u64 mapping, mrk;
6627
b4c21639
DM		 6628 i = skb_get_queue_mapping(skb);
6629 rp = &np->tx_rings[i];
6630 txq = netdev_get_tx_queue(dev, i);
a3138df9
DM		 6631
6632 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
b4c21639 6633 netif_tx_stop_queue(txq);
f10a1f2e 6634 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
a3138df9
DM		 6635 rp->tx_errors++;
6636 return NETDEV_TX_BUSY;
6637 }
6638
6639 if (skb->len < ETH_ZLEN) {
6640 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6641
6642 if (skb_pad(skb, pad_bytes))
6643 goto out;
6644 skb_put(skb, pad_bytes);
6645 }
6646
6647 len = sizeof(struct tx_pkt_hdr) + 15;
6648 if (skb_headroom(skb) < len) {
6649 struct sk_buff *skb_new;
6650
6651 skb_new = skb_realloc_headroom(skb, len);
6652 if (!skb_new) {
6653 rp->tx_errors++;
6654 goto out_drop;
6655 }
6656 kfree_skb(skb);
6657 skb = skb_new;
3ebebccf
DM		 6658 } else
6659 skb_orphan(skb);
a3138df9
DM		 6660
6661 align = ((unsigned long) skb->data & (16 - 1));
6662 headroom = align + sizeof(struct tx_pkt_hdr);
6663
6664 ehdr = (struct ethhdr *) skb->data;
6665 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6666
6667 len = skb->len - sizeof(struct tx_pkt_hdr);
6668 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6669 tp->resv = 0;
6670
6671 len = skb_headlen(skb);
6672 mapping = np->ops->map_single(np->device, skb->data,
6673 len, DMA_TO_DEVICE);
6674
6675 prod = rp->prod;
6676
6677 rp->tx_buffs[prod].skb = skb;
6678 rp->tx_buffs[prod].mapping = mapping;
6679
6680 mrk = TX_DESC_SOP;
6681 if (++rp->mark_counter == rp->mark_freq) {
6682 rp->mark_counter = 0;
6683 mrk |= TX_DESC_MARK;
6684 rp->mark_pending++;
6685 }
6686
6687 tlen = len;
6688 nfg = skb_shinfo(skb)->nr_frags;
6689 while (tlen > 0) {
6690 tlen -= MAX_TX_DESC_LEN;
6691 nfg++;
6692 }
6693
6694 while (len > 0) {
6695 unsigned int this_len = len;
6696
6697 if (this_len > MAX_TX_DESC_LEN)
6698 this_len = MAX_TX_DESC_LEN;
6699
6700 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6701 mrk = nfg = 0;
6702
6703 prod = NEXT_TX(rp, prod);
6704 mapping += this_len;
6705 len -= this_len;
6706 }
6707
6708 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6709 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6710
6711 len = frag->size;
6712 mapping = np->ops->map_page(np->device, frag->page,
6713 frag->page_offset, len,
6714 DMA_TO_DEVICE);
6715
6716 rp->tx_buffs[prod].skb = NULL;
6717 rp->tx_buffs[prod].mapping = mapping;
6718
6719 niu_set_txd(rp, prod, mapping, len, 0, 0);
6720
6721 prod = NEXT_TX(rp, prod);
6722 }
6723
6724 if (prod < rp->prod)
6725 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6726 rp->prod = prod;
6727
6728 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6729
6730 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
b4c21639 6731 netif_tx_stop_queue(txq);
a3138df9 6732 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
b4c21639 6733 netif_tx_wake_queue(txq);
a3138df9
DM		 6734 }
6735
a3138df9
DM		 6736out:
6737 return NETDEV_TX_OK;
6738
6739out_drop:
6740 rp->tx_errors++;
6741 kfree_skb(skb);
6742 goto out;
6743}
6744
6745static int niu_change_mtu(struct net_device *dev, int new_mtu)
6746{
6747 struct niu *np = netdev_priv(dev);
6748 int err, orig_jumbo, new_jumbo;
6749
6750 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6751 return -EINVAL;
6752
6753 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6754 new_jumbo = (new_mtu > ETH_DATA_LEN);
6755
6756 dev->mtu = new_mtu;
6757
6758 if (!netif_running(dev) ||
6759 (orig_jumbo == new_jumbo))
6760 return 0;
6761
6762 niu_full_shutdown(np, dev);
6763
6764 niu_free_channels(np);
6765
6766 niu_enable_napi(np);
6767
6768 err = niu_alloc_channels(np);
6769 if (err)
6770 return err;
6771
6772 spin_lock_irq(&np->lock);
6773
6774 err = niu_init_hw(np);
6775 if (!err) {
6776 init_timer(&np->timer);
6777 np->timer.expires = jiffies + HZ;
6778 np->timer.data = (unsigned long) np;
6779 np->timer.function = niu_timer;
6780
6781 err = niu_enable_interrupts(np, 1);
6782 if (err)
6783 niu_stop_hw(np);
6784 }
6785
6786 spin_unlock_irq(&np->lock);
6787
6788 if (!err) {
b4c21639 6789 netif_tx_start_all_queues(dev);
a3138df9
DM		 6790 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6791 netif_carrier_on(dev);
6792
6793 add_timer(&np->timer);
6794 }
6795
6796 return err;
6797}
6798
6799static void niu_get_drvinfo(struct net_device *dev,
6800 struct ethtool_drvinfo *info)
6801{
6802 struct niu *np = netdev_priv(dev);
6803 struct niu_vpd *vpd = &np->vpd;
6804
6805 strcpy(info->driver, DRV_MODULE_NAME);
6806 strcpy(info->version, DRV_MODULE_VERSION);
6807 sprintf(info->fw_version, "%d.%d",
6808 vpd->fcode_major, vpd->fcode_minor);
6809 if (np->parent->plat_type != PLAT_TYPE_NIU)
6810 strcpy(info->bus_info, pci_name(np->pdev));
6811}
6812
6813static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6814{
6815 struct niu *np = netdev_priv(dev);
6816 struct niu_link_config *lp;
6817
6818 lp = &np->link_config;
6819
6820 memset(cmd, 0, sizeof(*cmd));
6821 cmd->phy_address = np->phy_addr;
6822 cmd->supported = lp->supported;
38bb045d
CB		 6823 cmd->advertising = lp->active_advertising;
6824 cmd->autoneg = lp->active_autoneg;
a3138df9
DM		 6825 cmd->speed = lp->active_speed;
6826 cmd->duplex = lp->active_duplex;
38bb045d
CB		 6827 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6828 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6829 XCVR_EXTERNAL : XCVR_INTERNAL;
a3138df9
DM		 6830
6831 return 0;
6832}
6833
6834static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6835{
38bb045d
CB		 6836 struct niu *np = netdev_priv(dev);
6837 struct niu_link_config *lp = &np->link_config;
6838
6839 lp->advertising = cmd->advertising;
6840 lp->speed = cmd->speed;
6841 lp->duplex = cmd->duplex;
6842 lp->autoneg = cmd->autoneg;
6843 return niu_init_link(np);
a3138df9
DM		 6844}
6845
6846static u32 niu_get_msglevel(struct net_device *dev)
6847{
6848 struct niu *np = netdev_priv(dev);
6849 return np->msg_enable;
6850}
6851
6852static void niu_set_msglevel(struct net_device *dev, u32 value)
6853{
6854 struct niu *np = netdev_priv(dev);
6855 np->msg_enable = value;
6856}
6857
38bb045d
CB		 6858static int niu_nway_reset(struct net_device *dev)
6859{
6860 struct niu *np = netdev_priv(dev);
6861
6862 if (np->link_config.autoneg)
6863 return niu_init_link(np);
6864
6865 return 0;
6866}
6867
a3138df9
DM		 6868static int niu_get_eeprom_len(struct net_device *dev)
6869{
6870 struct niu *np = netdev_priv(dev);
6871
6872 return np->eeprom_len;
6873}
6874
6875static int niu_get_eeprom(struct net_device *dev,
6876 struct ethtool_eeprom *eeprom, u8 *data)
6877{
6878 struct niu *np = netdev_priv(dev);
6879 u32 offset, len, val;
6880
6881 offset = eeprom->offset;
6882 len = eeprom->len;
6883
6884 if (offset + len < offset)
6885 return -EINVAL;
6886 if (offset >= np->eeprom_len)
6887 return -EINVAL;
6888 if (offset + len > np->eeprom_len)
6889 len = eeprom->len = np->eeprom_len - offset;
6890
6891 if (offset & 3) {
6892 u32 b_offset, b_count;
6893
6894 b_offset = offset & 3;
6895 b_count = 4 - b_offset;
6896 if (b_count > len)
6897 b_count = len;
6898
6899 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6900 memcpy(data, ((char *)&val) + b_offset, b_count);
6901 data += b_count;
6902 len -= b_count;
6903 offset += b_count;
6904 }
6905 while (len >= 4) {
6906 val = nr64(ESPC_NCR(offset / 4));
6907 memcpy(data, &val, 4);
6908 data += 4;
6909 len -= 4;
6910 offset += 4;
6911 }
6912 if (len) {
6913 val = nr64(ESPC_NCR(offset / 4));
6914 memcpy(data, &val, len);
6915 }
6916 return 0;
6917}
6918
2d96cf8c
SB		 6919static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6920{
6921 switch (flow_type) {
6922 case TCP_V4_FLOW:
6923 case TCP_V6_FLOW:
6924 *pid = IPPROTO_TCP;
6925 break;
6926 case UDP_V4_FLOW:
6927 case UDP_V6_FLOW:
6928 *pid = IPPROTO_UDP;
6929 break;
6930 case SCTP_V4_FLOW:
6931 case SCTP_V6_FLOW:
6932 *pid = IPPROTO_SCTP;
6933 break;
6934 case AH_V4_FLOW:
6935 case AH_V6_FLOW:
6936 *pid = IPPROTO_AH;
6937 break;
6938 case ESP_V4_FLOW:
6939 case ESP_V6_FLOW:
6940 *pid = IPPROTO_ESP;
6941 break;
6942 default:
6943 *pid = 0;
6944 break;
6945 }
6946}
6947
6948static int niu_class_to_ethflow(u64 class, int *flow_type)
6949{
6950 switch (class) {
6951 case CLASS_CODE_TCP_IPV4:
6952 *flow_type = TCP_V4_FLOW;
6953 break;
6954 case CLASS_CODE_UDP_IPV4:
6955 *flow_type = UDP_V4_FLOW;
6956 break;
6957 case CLASS_CODE_AH_ESP_IPV4:
6958 *flow_type = AH_V4_FLOW;
6959 break;
6960 case CLASS_CODE_SCTP_IPV4:
6961 *flow_type = SCTP_V4_FLOW;
6962 break;
6963 case CLASS_CODE_TCP_IPV6:
6964 *flow_type = TCP_V6_FLOW;
6965 break;
6966 case CLASS_CODE_UDP_IPV6:
6967 *flow_type = UDP_V6_FLOW;
6968 break;
6969 case CLASS_CODE_AH_ESP_IPV6:
6970 *flow_type = AH_V6_FLOW;
6971 break;
6972 case CLASS_CODE_SCTP_IPV6:
6973 *flow_type = SCTP_V6_FLOW;
6974 break;
6975 case CLASS_CODE_USER_PROG1:
6976 case CLASS_CODE_USER_PROG2:
6977 case CLASS_CODE_USER_PROG3:
6978 case CLASS_CODE_USER_PROG4:
6979 *flow_type = IP_USER_FLOW;
6980 break;
6981 default:
6982 return 0;
6983 }
6984
6985 return 1;
6986}
6987
b4653e99
SB		 6988static int niu_ethflow_to_class(int flow_type, u64 *class)
6989{
6990 switch (flow_type) {
6991 case TCP_V4_FLOW:
6992 *class = CLASS_CODE_TCP_IPV4;
6993 break;
6994 case UDP_V4_FLOW:
6995 *class = CLASS_CODE_UDP_IPV4;
6996 break;
2d96cf8c
SB		 6997 case AH_V4_FLOW:
6998 case ESP_V4_FLOW:
b4653e99
SB		 6999 *class = CLASS_CODE_AH_ESP_IPV4;
7000 break;
7001 case SCTP_V4_FLOW:
7002 *class = CLASS_CODE_SCTP_IPV4;
7003 break;
7004 case TCP_V6_FLOW:
7005 *class = CLASS_CODE_TCP_IPV6;
7006 break;
7007 case UDP_V6_FLOW:
7008 *class = CLASS_CODE_UDP_IPV6;
7009 break;
2d96cf8c
SB		 7010 case AH_V6_FLOW:
7011 case ESP_V6_FLOW:
b4653e99
SB		 7012 *class = CLASS_CODE_AH_ESP_IPV6;
7013 break;
7014 case SCTP_V6_FLOW:
7015 *class = CLASS_CODE_SCTP_IPV6;
7016 break;
7017 default:
38c080ff 7018 return 0;
b4653e99
SB		 7019 }
7020
7021 return 1;
7022}
7023
7024static u64 niu_flowkey_to_ethflow(u64 flow_key)
7025{
7026 u64 ethflow = 0;
7027
b4653e99
SB		 7028 if (flow_key & FLOW_KEY_L2DA)
7029 ethflow |= RXH_L2DA;
7030 if (flow_key & FLOW_KEY_VLAN)
7031 ethflow |= RXH_VLAN;
7032 if (flow_key & FLOW_KEY_IPSA)
7033 ethflow |= RXH_IP_SRC;
7034 if (flow_key & FLOW_KEY_IPDA)
7035 ethflow |= RXH_IP_DST;
7036 if (flow_key & FLOW_KEY_PROTO)
7037 ethflow |= RXH_L3_PROTO;
7038 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7039 ethflow |= RXH_L4_B_0_1;
7040 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7041 ethflow |= RXH_L4_B_2_3;
7042
7043 return ethflow;
7044
7045}
7046
7047static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7048{
7049 u64 key = 0;
7050
b4653e99
SB		 7051 if (ethflow & RXH_L2DA)
7052 key |= FLOW_KEY_L2DA;
7053 if (ethflow & RXH_VLAN)
7054 key |= FLOW_KEY_VLAN;
7055 if (ethflow & RXH_IP_SRC)
7056 key |= FLOW_KEY_IPSA;
7057 if (ethflow & RXH_IP_DST)
7058 key |= FLOW_KEY_IPDA;
7059 if (ethflow & RXH_L3_PROTO)
7060 key |= FLOW_KEY_PROTO;
7061 if (ethflow & RXH_L4_B_0_1)
7062 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7063 if (ethflow & RXH_L4_B_2_3)
7064 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7065
7066 *flow_key = key;
7067
7068 return 1;
7069
7070}
7071
2d96cf8c 7072static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
b4653e99 7073{
b4653e99
SB		 7074 u64 class;
7075
2d96cf8c 7076 nfc->data = 0;
b4653e99 7077
2d96cf8c 7078 if (!niu_ethflow_to_class(nfc->flow_type, &class))
b4653e99
SB		 7079 return -EINVAL;
7080
7081 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7082 TCAM_KEY_DISC)
2d96cf8c 7083 nfc->data = RXH_DISCARD;
b4653e99 7084 else
2d96cf8c 7085 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
b4653e99
SB		 7086 CLASS_CODE_USER_PROG1]);
7087 return 0;
7088}
7089
2d96cf8c
SB		 7090static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7091 struct ethtool_rx_flow_spec *fsp)
7092{
7093
7094 fsp->h_u.tcp_ip4_spec.ip4src = (tp->key[3] & TCAM_V4KEY3_SADDR) >>
7095 TCAM_V4KEY3_SADDR_SHIFT;
7096 fsp->h_u.tcp_ip4_spec.ip4dst = (tp->key[3] & TCAM_V4KEY3_DADDR) >>
7097 TCAM_V4KEY3_DADDR_SHIFT;
7098 fsp->m_u.tcp_ip4_spec.ip4src = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >>
7099 TCAM_V4KEY3_SADDR_SHIFT;
7100 fsp->m_u.tcp_ip4_spec.ip4dst = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >>
7101 TCAM_V4KEY3_DADDR_SHIFT;
7102
7103 fsp->h_u.tcp_ip4_spec.ip4src =
7104 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4src);
7105 fsp->m_u.tcp_ip4_spec.ip4src =
7106 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4src);
7107 fsp->h_u.tcp_ip4_spec.ip4dst =
7108 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4dst);
7109 fsp->m_u.tcp_ip4_spec.ip4dst =
7110 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4dst);
7111
7112 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7113 TCAM_V4KEY2_TOS_SHIFT;
7114 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7115 TCAM_V4KEY2_TOS_SHIFT;
7116
7117 switch (fsp->flow_type) {
7118 case TCP_V4_FLOW:
7119 case UDP_V4_FLOW:
7120 case SCTP_V4_FLOW:
7121 fsp->h_u.tcp_ip4_spec.psrc =
7122 ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7123 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7124 fsp->h_u.tcp_ip4_spec.pdst =
7125 ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7126 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7127 fsp->m_u.tcp_ip4_spec.psrc =
7128 ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7129 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7130 fsp->m_u.tcp_ip4_spec.pdst =
7131 ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7132 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7133
7134 fsp->h_u.tcp_ip4_spec.psrc =
7135 cpu_to_be16(fsp->h_u.tcp_ip4_spec.psrc);
7136 fsp->h_u.tcp_ip4_spec.pdst =
7137 cpu_to_be16(fsp->h_u.tcp_ip4_spec.pdst);
7138 fsp->m_u.tcp_ip4_spec.psrc =
7139 cpu_to_be16(fsp->m_u.tcp_ip4_spec.psrc);
7140 fsp->m_u.tcp_ip4_spec.pdst =
7141 cpu_to_be16(fsp->m_u.tcp_ip4_spec.pdst);
7142 break;
7143 case AH_V4_FLOW:
7144 case ESP_V4_FLOW:
7145 fsp->h_u.ah_ip4_spec.spi =
7146 (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7147 TCAM_V4KEY2_PORT_SPI_SHIFT;
7148 fsp->m_u.ah_ip4_spec.spi =
7149 (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7150 TCAM_V4KEY2_PORT_SPI_SHIFT;
7151
7152 fsp->h_u.ah_ip4_spec.spi =
7153 cpu_to_be32(fsp->h_u.ah_ip4_spec.spi);
7154 fsp->m_u.ah_ip4_spec.spi =
7155 cpu_to_be32(fsp->m_u.ah_ip4_spec.spi);
7156 break;
7157 case IP_USER_FLOW:
7158 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7159 (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7160 TCAM_V4KEY2_PORT_SPI_SHIFT;
7161 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7162 (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7163 TCAM_V4KEY2_PORT_SPI_SHIFT;
7164
7165 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7166 cpu_to_be32(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7167 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7168 cpu_to_be32(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7169
7170 fsp->h_u.usr_ip4_spec.proto =
7171 (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7172 TCAM_V4KEY2_PROTO_SHIFT;
7173 fsp->m_u.usr_ip4_spec.proto =
7174 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7175 TCAM_V4KEY2_PROTO_SHIFT;
7176
7177 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7178 break;
7179 default:
7180 break;
7181 }
7182}
7183
7184static int niu_get_ethtool_tcam_entry(struct niu *np,
7185 struct ethtool_rxnfc *nfc)
7186{
7187 struct niu_parent *parent = np->parent;
7188 struct niu_tcam_entry *tp;
7189 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7190 u16 idx;
7191 u64 class;
7192 int ret = 0;
7193
7194 idx = tcam_get_index(np, (u16)nfc->fs.location);
7195
7196 tp = &parent->tcam[idx];
7197 if (!tp->valid) {
f10a1f2e
JP		 7198 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7199 parent->index, (u16)nfc->fs.location, idx);
2d96cf8c
SB		 7200 return -EINVAL;
7201 }
7202
7203 /* fill the flow spec entry */
7204 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7205 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7206 ret = niu_class_to_ethflow(class, &fsp->flow_type);
7207
7208 if (ret < 0) {
f10a1f2e
JP		 7209 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7210 parent->index);
2d96cf8c
SB		 7211 ret = -EINVAL;
7212 goto out;
7213 }
7214
7215 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7216 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7217 TCAM_V4KEY2_PROTO_SHIFT;
7218 if (proto == IPPROTO_ESP) {
7219 if (fsp->flow_type == AH_V4_FLOW)
7220 fsp->flow_type = ESP_V4_FLOW;
7221 else
7222 fsp->flow_type = ESP_V6_FLOW;
7223 }
7224 }
7225
7226 switch (fsp->flow_type) {
7227 case TCP_V4_FLOW:
7228 case UDP_V4_FLOW:
7229 case SCTP_V4_FLOW:
7230 case AH_V4_FLOW:
7231 case ESP_V4_FLOW:
7232 niu_get_ip4fs_from_tcam_key(tp, fsp);
7233 break;
7234 case TCP_V6_FLOW:
7235 case UDP_V6_FLOW:
7236 case SCTP_V6_FLOW:
7237 case AH_V6_FLOW:
7238 case ESP_V6_FLOW:
7239 /* Not yet implemented */
7240 ret = -EINVAL;
7241 break;
7242 case IP_USER_FLOW:
7243 niu_get_ip4fs_from_tcam_key(tp, fsp);
7244 break;
7245 default:
7246 ret = -EINVAL;
7247 break;
7248 }
7249
7250 if (ret < 0)
7251 goto out;
7252
7253 if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7254 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7255 else
7256 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7257 TCAM_ASSOCDATA_OFFSET_SHIFT;
7258
7259 /* put the tcam size here */
7260 nfc->data = tcam_get_size(np);
7261out:
7262 return ret;
7263}
7264
7265static int niu_get_ethtool_tcam_all(struct niu *np,
7266 struct ethtool_rxnfc *nfc,
7267 u32 *rule_locs)
7268{
7269 struct niu_parent *parent = np->parent;
7270 struct niu_tcam_entry *tp;
7271 int i, idx, cnt;
7272 u16 n_entries;
7273 unsigned long flags;
7274
7275
7276 /* put the tcam size here */
7277 nfc->data = tcam_get_size(np);
7278
7279 niu_lock_parent(np, flags);
7280 n_entries = nfc->rule_cnt;
7281 for (cnt = 0, i = 0; i < nfc->data; i++) {
7282 idx = tcam_get_index(np, i);
7283 tp = &parent->tcam[idx];
7284 if (!tp->valid)
7285 continue;
7286 rule_locs[cnt] = i;
7287 cnt++;
7288 }
7289 niu_unlock_parent(np, flags);
7290
7291 if (n_entries != cnt) {
7292 /* print warning, this should not happen */
f10a1f2e
JP		 7293 netdev_info(np->dev, "niu%d: In %s(): n_entries[%d] != cnt[%d]!!!\n",
7294 np->parent->index, __func__, n_entries, cnt);
2d96cf8c
SB		 7295 }
7296
7297 return 0;
7298}
7299
7300static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7301 void *rule_locs)
b4653e99
SB		 7302{
7303 struct niu *np = netdev_priv(dev);
2d96cf8c
SB		 7304 int ret = 0;
7305
7306 switch (cmd->cmd) {
7307 case ETHTOOL_GRXFH:
7308 ret = niu_get_hash_opts(np, cmd);
7309 break;
7310 case ETHTOOL_GRXRINGS:
7311 cmd->data = np->num_rx_rings;
7312 break;
7313 case ETHTOOL_GRXCLSRLCNT:
7314 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7315 break;
7316 case ETHTOOL_GRXCLSRULE:
7317 ret = niu_get_ethtool_tcam_entry(np, cmd);
7318 break;
7319 case ETHTOOL_GRXCLSRLALL:
7320 ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs);
7321 break;
7322 default:
7323 ret = -EINVAL;
7324 break;
7325 }
7326
7327 return ret;
7328}
7329
7330static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7331{
b4653e99
SB		 7332 u64 class;
7333 u64 flow_key = 0;
7334 unsigned long flags;
7335
2d96cf8c 7336 if (!niu_ethflow_to_class(nfc->flow_type, &class))
b4653e99
SB		 7337 return -EINVAL;
7338
7339 if (class < CLASS_CODE_USER_PROG1 ||
7340 class > CLASS_CODE_SCTP_IPV6)
7341 return -EINVAL;
7342
2d96cf8c 7343 if (nfc->data & RXH_DISCARD) {
b4653e99
SB		 7344 niu_lock_parent(np, flags);
7345 flow_key = np->parent->tcam_key[class -
7346 CLASS_CODE_USER_PROG1];
7347 flow_key |= TCAM_KEY_DISC;
7348 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7349 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7350 niu_unlock_parent(np, flags);
7351 return 0;
7352 } else {
7353 /* Discard was set before, but is not set now */
7354 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7355 TCAM_KEY_DISC) {
7356 niu_lock_parent(np, flags);
7357 flow_key = np->parent->tcam_key[class -
7358 CLASS_CODE_USER_PROG1];
7359 flow_key &= ~TCAM_KEY_DISC;
7360 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7361 flow_key);
7362 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7363 flow_key;
7364 niu_unlock_parent(np, flags);
7365 }
7366 }
7367
2d96cf8c 7368 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
b4653e99
SB		 7369 return -EINVAL;
7370
7371 niu_lock_parent(np, flags);
7372 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7373 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7374 niu_unlock_parent(np, flags);
7375
7376 return 0;
7377}
7378
2d96cf8c
SB		 7379static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7380 struct niu_tcam_entry *tp,
7381 int l2_rdc_tab, u64 class)
7382{
7383 u8 pid = 0;
7384 u32 sip, dip, sipm, dipm, spi, spim;
7385 u16 sport, dport, spm, dpm;
7386
7387 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7388 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7389 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7390 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7391
7392 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7393 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7394 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7395 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7396
7397 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7398 tp->key[3] |= dip;
7399
7400 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7401 tp->key_mask[3] |= dipm;
7402
7403 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7404 TCAM_V4KEY2_TOS_SHIFT);
7405 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7406 TCAM_V4KEY2_TOS_SHIFT);
7407 switch (fsp->flow_type) {
7408 case TCP_V4_FLOW:
7409 case UDP_V4_FLOW:
7410 case SCTP_V4_FLOW:
7411 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7412 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7413 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7414 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7415
7416 tp->key[2] |= (((u64)sport << 16) | dport);
7417 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7418 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7419 break;
7420 case AH_V4_FLOW:
7421 case ESP_V4_FLOW:
7422 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7423 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7424
7425 tp->key[2] |= spi;
7426 tp->key_mask[2] |= spim;
7427 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7428 break;
7429 case IP_USER_FLOW:
7430 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7431 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7432
7433 tp->key[2] |= spi;
7434 tp->key_mask[2] |= spim;
7435 pid = fsp->h_u.usr_ip4_spec.proto;
7436 break;
7437 default:
7438 break;
7439 }
7440
7441 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7442 if (pid) {
7443 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7444 }
7445}
7446
7447static int niu_add_ethtool_tcam_entry(struct niu *np,
7448 struct ethtool_rxnfc *nfc)
7449{
7450 struct niu_parent *parent = np->parent;
7451 struct niu_tcam_entry *tp;
7452 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7453 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7454 int l2_rdc_table = rdc_table->first_table_num;
7455 u16 idx;
7456 u64 class;
7457 unsigned long flags;
7458 int err, ret;
7459
7460 ret = 0;
7461
7462 idx = nfc->fs.location;
7463 if (idx >= tcam_get_size(np))
7464 return -EINVAL;
7465
7466 if (fsp->flow_type == IP_USER_FLOW) {
7467 int i;
7468 int add_usr_cls = 0;
7469 int ipv6 = 0;
7470 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7471 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7472
7473 niu_lock_parent(np, flags);
7474
7475 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7476 if (parent->l3_cls[i]) {
7477 if (uspec->proto == parent->l3_cls_pid[i]) {
7478 class = parent->l3_cls[i];
7479 parent->l3_cls_refcnt[i]++;
7480 add_usr_cls = 1;
7481 break;
7482 }
7483 } else {
7484 /* Program new user IP class */
7485 switch (i) {
7486 case 0:
7487 class = CLASS_CODE_USER_PROG1;
7488 break;
7489 case 1:
7490 class = CLASS_CODE_USER_PROG2;
7491 break;
7492 case 2:
7493 class = CLASS_CODE_USER_PROG3;
7494 break;
7495 case 3:
7496 class = CLASS_CODE_USER_PROG4;
7497 break;
7498 default:
7499 break;
7500 }
7501 if (uspec->ip_ver == ETH_RX_NFC_IP6)
7502 ipv6 = 1;
7503 ret = tcam_user_ip_class_set(np, class, ipv6,
7504 uspec->proto,
7505 uspec->tos,
7506 umask->tos);
7507 if (ret)
7508 goto out;
7509
7510 ret = tcam_user_ip_class_enable(np, class, 1);
7511 if (ret)
7512 goto out;
7513 parent->l3_cls[i] = class;
7514 parent->l3_cls_pid[i] = uspec->proto;
7515 parent->l3_cls_refcnt[i]++;
7516 add_usr_cls = 1;
7517 break;
7518 }
7519 }
7520 if (!add_usr_cls) {
f10a1f2e
JP		 7521 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7522 parent->index, __func__, uspec->proto);
2d96cf8c
SB		 7523 ret = -EINVAL;
7524 goto out;
7525 }
7526 niu_unlock_parent(np, flags);
7527 } else {
7528 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7529 return -EINVAL;
7530 }
7531 }
7532
7533 niu_lock_parent(np, flags);
7534
7535 idx = tcam_get_index(np, idx);
7536 tp = &parent->tcam[idx];
7537
7538 memset(tp, 0, sizeof(*tp));
7539
7540 /* fill in the tcam key and mask */
7541 switch (fsp->flow_type) {
7542 case TCP_V4_FLOW:
7543 case UDP_V4_FLOW:
7544 case SCTP_V4_FLOW:
7545 case AH_V4_FLOW:
7546 case ESP_V4_FLOW:
7547 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7548 break;
7549 case TCP_V6_FLOW:
7550 case UDP_V6_FLOW:
7551 case SCTP_V6_FLOW:
7552 case AH_V6_FLOW:
7553 case ESP_V6_FLOW:
7554 /* Not yet implemented */
f10a1f2e
JP		 7555 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7556 parent->index, __func__, fsp->flow_type);
2d96cf8c
SB		 7557 ret = -EINVAL;
7558 goto out;
7559 case IP_USER_FLOW:
7560 if (fsp->h_u.usr_ip4_spec.ip_ver == ETH_RX_NFC_IP4) {
7561 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table,
7562 class);
7563 } else {
7564 /* Not yet implemented */
f10a1f2e
JP		 7565 netdev_info(np->dev, "niu%d: In %s(): usr flow for IPv6 not implemented\n",
7566 parent->index, __func__);
2d96cf8c
SB		 7567 ret = -EINVAL;
7568 goto out;
7569 }
7570 break;
7571 default:
f10a1f2e
JP		 7572 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7573 parent->index, __func__, fsp->flow_type);
2d96cf8c
SB		 7574 ret = -EINVAL;
7575 goto out;
7576 }
7577
7578 /* fill in the assoc data */
7579 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7580 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7581 } else {
7582 if (fsp->ring_cookie >= np->num_rx_rings) {
f10a1f2e
JP		 7583 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7584 parent->index, __func__,
7585 (long long)fsp->ring_cookie);
2d96cf8c
SB		 7586 ret = -EINVAL;
7587 goto out;
7588 }
7589 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7590 (fsp->ring_cookie <<
7591 TCAM_ASSOCDATA_OFFSET_SHIFT));
7592 }
7593
7594 err = tcam_write(np, idx, tp->key, tp->key_mask);
7595 if (err) {
7596 ret = -EINVAL;
7597 goto out;
7598 }
7599 err = tcam_assoc_write(np, idx, tp->assoc_data);
7600 if (err) {
7601 ret = -EINVAL;
7602 goto out;
7603 }
7604
7605 /* validate the entry */
7606 tp->valid = 1;
7607 np->clas.tcam_valid_entries++;
7608out:
7609 niu_unlock_parent(np, flags);
7610
7611 return ret;
7612}
7613
7614static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7615{
7616 struct niu_parent *parent = np->parent;
7617 struct niu_tcam_entry *tp;
7618 u16 idx;
7619 unsigned long flags;
7620 u64 class;
7621 int ret = 0;
7622
7623 if (loc >= tcam_get_size(np))
7624 return -EINVAL;
7625
7626 niu_lock_parent(np, flags);
7627
7628 idx = tcam_get_index(np, loc);
7629 tp = &parent->tcam[idx];
7630
7631 /* if the entry is of a user defined class, then update*/
7632 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7633 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7634
7635 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7636 int i;
7637 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7638 if (parent->l3_cls[i] == class) {
7639 parent->l3_cls_refcnt[i]--;
7640 if (!parent->l3_cls_refcnt[i]) {
7641 /* disable class */
7642 ret = tcam_user_ip_class_enable(np,
7643 class,
7644 0);
7645 if (ret)
7646 goto out;
7647 parent->l3_cls[i] = 0;
7648 parent->l3_cls_pid[i] = 0;
7649 }
7650 break;
7651 }
7652 }
7653 if (i == NIU_L3_PROG_CLS) {
f10a1f2e
JP		 7654 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7655 parent->index, __func__,
7656 (unsigned long long)class);
2d96cf8c
SB		 7657 ret = -EINVAL;
7658 goto out;
7659 }
7660 }
7661
7662 ret = tcam_flush(np, idx);
7663 if (ret)
7664 goto out;
7665
7666 /* invalidate the entry */
7667 tp->valid = 0;
7668 np->clas.tcam_valid_entries--;
7669out:
7670 niu_unlock_parent(np, flags);
7671
7672 return ret;
7673}
7674
7675static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7676{
7677 struct niu *np = netdev_priv(dev);
7678 int ret = 0;
7679
7680 switch (cmd->cmd) {
7681 case ETHTOOL_SRXFH:
7682 ret = niu_set_hash_opts(np, cmd);
7683 break;
7684 case ETHTOOL_SRXCLSRLINS:
7685 ret = niu_add_ethtool_tcam_entry(np, cmd);
7686 break;
7687 case ETHTOOL_SRXCLSRLDEL:
7688 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7689 break;
7690 default:
7691 ret = -EINVAL;
7692 break;
7693 }
7694
7695 return ret;
7696}
7697
a3138df9
DM		 7698static const struct {
7699 const char string[ETH_GSTRING_LEN];
7700} niu_xmac_stat_keys[] = {
7701 { "tx_frames" },
7702 { "tx_bytes" },
7703 { "tx_fifo_errors" },
7704 { "tx_overflow_errors" },
7705 { "tx_max_pkt_size_errors" },
7706 { "tx_underflow_errors" },
7707 { "rx_local_faults" },
7708 { "rx_remote_faults" },
7709 { "rx_link_faults" },
7710 { "rx_align_errors" },
7711 { "rx_frags" },
7712 { "rx_mcasts" },
7713 { "rx_bcasts" },
7714 { "rx_hist_cnt1" },
7715 { "rx_hist_cnt2" },
7716 { "rx_hist_cnt3" },
7717 { "rx_hist_cnt4" },
7718 { "rx_hist_cnt5" },
7719 { "rx_hist_cnt6" },
7720 { "rx_hist_cnt7" },
7721 { "rx_octets" },
7722 { "rx_code_violations" },
7723 { "rx_len_errors" },
7724 { "rx_crc_errors" },
7725 { "rx_underflows" },
7726 { "rx_overflows" },
7727 { "pause_off_state" },
7728 { "pause_on_state" },
7729 { "pause_received" },
7730};
7731
7732#define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7733
7734static const struct {
7735 const char string[ETH_GSTRING_LEN];
7736} niu_bmac_stat_keys[] = {
7737 { "tx_underflow_errors" },
7738 { "tx_max_pkt_size_errors" },
7739 { "tx_bytes" },
7740 { "tx_frames" },
7741 { "rx_overflows" },
7742 { "rx_frames" },
7743 { "rx_align_errors" },
7744 { "rx_crc_errors" },
7745 { "rx_len_errors" },
7746 { "pause_off_state" },
7747 { "pause_on_state" },
7748 { "pause_received" },
7749};
7750
7751#define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7752
7753static const struct {
7754 const char string[ETH_GSTRING_LEN];
7755} niu_rxchan_stat_keys[] = {
7756 { "rx_channel" },
7757 { "rx_packets" },
7758 { "rx_bytes" },
7759 { "rx_dropped" },
7760 { "rx_errors" },
7761};
7762
7763#define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7764
7765static const struct {
7766 const char string[ETH_GSTRING_LEN];
7767} niu_txchan_stat_keys[] = {
7768 { "tx_channel" },
7769 { "tx_packets" },
7770 { "tx_bytes" },
7771 { "tx_errors" },
7772};
7773
7774#define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7775
7776static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7777{
7778 struct niu *np = netdev_priv(dev);
7779 int i;
7780
7781 if (stringset != ETH_SS_STATS)
7782 return;
7783
7784 if (np->flags & NIU_FLAGS_XMAC) {
7785 memcpy(data, niu_xmac_stat_keys,
7786 sizeof(niu_xmac_stat_keys));
7787 data += sizeof(niu_xmac_stat_keys);
7788 } else {
7789 memcpy(data, niu_bmac_stat_keys,
7790 sizeof(niu_bmac_stat_keys));
7791 data += sizeof(niu_bmac_stat_keys);
7792 }
7793 for (i = 0; i < np->num_rx_rings; i++) {
7794 memcpy(data, niu_rxchan_stat_keys,
7795 sizeof(niu_rxchan_stat_keys));
7796 data += sizeof(niu_rxchan_stat_keys);
7797 }
7798 for (i = 0; i < np->num_tx_rings; i++) {
7799 memcpy(data, niu_txchan_stat_keys,
7800 sizeof(niu_txchan_stat_keys));
7801 data += sizeof(niu_txchan_stat_keys);
7802 }
7803}
7804
15f0a394 7805static int niu_get_sset_count(struct net_device *dev, int stringset)
a3138df9
DM		 7806{
7807 struct niu *np = netdev_priv(dev);
7808
15f0a394
BH		 7809 if (stringset != ETH_SS_STATS)
7810 return -EINVAL;
7811
a3138df9
DM		 7812 return ((np->flags & NIU_FLAGS_XMAC ?
7813 NUM_XMAC_STAT_KEYS :
7814 NUM_BMAC_STAT_KEYS) +
7815 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7816 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
7817}
7818
7819static void niu_get_ethtool_stats(struct net_device *dev,
7820 struct ethtool_stats *stats, u64 *data)
7821{
7822 struct niu *np = netdev_priv(dev);
7823 int i;
7824
7825 niu_sync_mac_stats(np);
7826 if (np->flags & NIU_FLAGS_XMAC) {
7827 memcpy(data, &np->mac_stats.xmac,
7828 sizeof(struct niu_xmac_stats));
7829 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7830 } else {
7831 memcpy(data, &np->mac_stats.bmac,
7832 sizeof(struct niu_bmac_stats));
7833 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7834 }
7835 for (i = 0; i < np->num_rx_rings; i++) {
7836 struct rx_ring_info *rp = &np->rx_rings[i];
7837
b8a606b8
JDB		 7838 niu_sync_rx_discard_stats(np, rp, 0);
7839
a3138df9
DM		 7840 data[0] = rp->rx_channel;
7841 data[1] = rp->rx_packets;
7842 data[2] = rp->rx_bytes;
7843 data[3] = rp->rx_dropped;
7844 data[4] = rp->rx_errors;
7845 data += 5;
7846 }
7847 for (i = 0; i < np->num_tx_rings; i++) {
7848 struct tx_ring_info *rp = &np->tx_rings[i];
7849
7850 data[0] = rp->tx_channel;
7851 data[1] = rp->tx_packets;
7852 data[2] = rp->tx_bytes;
7853 data[3] = rp->tx_errors;
7854 data += 4;
7855 }
7856}
7857
7858static u64 niu_led_state_save(struct niu *np)
7859{
7860 if (np->flags & NIU_FLAGS_XMAC)
7861 return nr64_mac(XMAC_CONFIG);
7862 else
7863 return nr64_mac(BMAC_XIF_CONFIG);
7864}
7865
7866static void niu_led_state_restore(struct niu *np, u64 val)
7867{
7868 if (np->flags & NIU_FLAGS_XMAC)
7869 nw64_mac(XMAC_CONFIG, val);
7870 else
7871 nw64_mac(BMAC_XIF_CONFIG, val);
7872}
7873
7874static void niu_force_led(struct niu *np, int on)
7875{
7876 u64 val, reg, bit;
7877
7878 if (np->flags & NIU_FLAGS_XMAC) {
7879 reg = XMAC_CONFIG;
7880 bit = XMAC_CONFIG_FORCE_LED_ON;
7881 } else {
7882 reg = BMAC_XIF_CONFIG;
7883 bit = BMAC_XIF_CONFIG_LINK_LED;
7884 }
7885
7886 val = nr64_mac(reg);
7887 if (on)
7888 val |= bit;
7889 else
7890 val &= ~bit;
7891 nw64_mac(reg, val);
7892}
7893
7894static int niu_phys_id(struct net_device *dev, u32 data)
7895{
7896 struct niu *np = netdev_priv(dev);
7897 u64 orig_led_state;
7898 int i;
7899
7900 if (!netif_running(dev))
7901 return -EAGAIN;
7902
7903 if (data == 0)
7904 data = 2;
7905
7906 orig_led_state = niu_led_state_save(np);
7907 for (i = 0; i < (data * 2); i++) {
7908 int on = ((i % 2) == 0);
7909
7910 niu_force_led(np, on);
7911
7912 if (msleep_interruptible(500))
7913 break;
7914 }
7915 niu_led_state_restore(np, orig_led_state);
7916
7917 return 0;
7918}
7919
3cfa856d
DM		 7920static int niu_set_flags(struct net_device *dev, u32 data)
7921{
1437ce39 7922 return ethtool_op_set_flags(dev, data, ETH_FLAG_RXHASH);
3cfa856d
DM		 7923}
7924
a3138df9
DM		 7925static const struct ethtool_ops niu_ethtool_ops = {
7926 .get_drvinfo = niu_get_drvinfo,
7927 .get_link = ethtool_op_get_link,
7928 .get_msglevel = niu_get_msglevel,
7929 .set_msglevel = niu_set_msglevel,
38bb045d 7930 .nway_reset = niu_nway_reset,
a3138df9
DM		 7931 .get_eeprom_len = niu_get_eeprom_len,
7932 .get_eeprom = niu_get_eeprom,
7933 .get_settings = niu_get_settings,
7934 .set_settings = niu_set_settings,
7935 .get_strings = niu_get_strings,
15f0a394 7936 .get_sset_count = niu_get_sset_count,
a3138df9
DM		 7937 .get_ethtool_stats = niu_get_ethtool_stats,
7938 .phys_id = niu_phys_id,
2d96cf8c
SB		 7939 .get_rxnfc = niu_get_nfc,
7940 .set_rxnfc = niu_set_nfc,
3cfa856d
DM		 7941 .set_flags = niu_set_flags,
7942 .get_flags = ethtool_op_get_flags,
a3138df9
DM		 7943};
7944
7945static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7946 int ldg, int ldn)
7947{
7948 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7949 return -EINVAL;
7950 if (ldn < 0 || ldn > LDN_MAX)
7951 return -EINVAL;
7952
7953 parent->ldg_map[ldn] = ldg;
7954
7955 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7956 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7957 * the firmware, and we're not supposed to change them.
7958 * Validate the mapping, because if it's wrong we probably
7959 * won't get any interrupts and that's painful to debug.
7960 */
7961 if (nr64(LDG_NUM(ldn)) != ldg) {
f10a1f2e 7962 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
a3138df9
DM		 7963 np->port, ldn, ldg,
7964 (unsigned long long) nr64(LDG_NUM(ldn)));
7965 return -EINVAL;
7966 }
7967 } else
7968 nw64(LDG_NUM(ldn), ldg);
7969
7970 return 0;
7971}
7972
7973static int niu_set_ldg_timer_res(struct niu *np, int res)
7974{
7975 if (res < 0 || res > LDG_TIMER_RES_VAL)
7976 return -EINVAL;
7977
7978
7979 nw64(LDG_TIMER_RES, res);
7980
7981 return 0;
7982}
7983
7984static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7985{
7986 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7987 (func < 0 || func > 3) ||
7988 (vector < 0 || vector > 0x1f))
7989 return -EINVAL;
7990
7991 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7992
7993 return 0;
7994}
7995
7996static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7997{
7998 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7999 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
8000 int limit;
8001
8002 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
8003 return -EINVAL;
8004
8005 frame = frame_base;
8006 nw64(ESPC_PIO_STAT, frame);
8007 limit = 64;
8008 do {
8009 udelay(5);
8010 frame = nr64(ESPC_PIO_STAT);
8011 if (frame & ESPC_PIO_STAT_READ_END)
8012 break;
8013 } while (limit--);
8014 if (!(frame & ESPC_PIO_STAT_READ_END)) {
f10a1f2e 8015 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
a3138df9
DM		 8016 (unsigned long long) frame);
8017 return -ENODEV;
8018 }
8019
8020 frame = frame_base;
8021 nw64(ESPC_PIO_STAT, frame);
8022 limit = 64;
8023 do {
8024 udelay(5);
8025 frame = nr64(ESPC_PIO_STAT);
8026 if (frame & ESPC_PIO_STAT_READ_END)
8027 break;
8028 } while (limit--);
8029 if (!(frame & ESPC_PIO_STAT_READ_END)) {
f10a1f2e 8030 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
a3138df9
DM		 8031 (unsigned long long) frame);
8032 return -ENODEV;
8033 }
8034
8035 frame = nr64(ESPC_PIO_STAT);
8036 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8037}
8038
8039static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8040{
8041 int err = niu_pci_eeprom_read(np, off);
8042 u16 val;
8043
8044 if (err < 0)
8045 return err;
8046 val = (err << 8);
8047 err = niu_pci_eeprom_read(np, off + 1);
8048 if (err < 0)
8049 return err;
8050 val |= (err & 0xff);
8051
8052 return val;
8053}
8054
8055static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8056{
8057 int err = niu_pci_eeprom_read(np, off);
8058 u16 val;
8059
8060 if (err < 0)
8061 return err;
8062
8063 val = (err & 0xff);
8064 err = niu_pci_eeprom_read(np, off + 1);
8065 if (err < 0)
8066 return err;
8067
8068 val |= (err & 0xff) << 8;
8069
8070 return val;
8071}
8072
8073static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8074 u32 off,
8075 char *namebuf,
8076 int namebuf_len)
8077{
8078 int i;
8079
8080 for (i = 0; i < namebuf_len; i++) {
8081 int err = niu_pci_eeprom_read(np, off + i);
8082 if (err < 0)
8083 return err;
8084 *namebuf++ = err;
8085 if (!err)
8086 break;
8087 }
8088 if (i >= namebuf_len)
8089 return -EINVAL;
8090
8091 return i + 1;
8092}
8093
8094static void __devinit niu_vpd_parse_version(struct niu *np)
8095{
8096 struct niu_vpd *vpd = &np->vpd;
8097 int len = strlen(vpd->version) + 1;
8098 const char *s = vpd->version;
8099 int i;
8100
8101 for (i = 0; i < len - 5; i++) {
9ea2bdab 8102 if (!strncmp(s + i, "FCode ", 6))
a3138df9
DM		 8103 break;
8104 }
8105 if (i >= len - 5)
8106 return;
8107
8108 s += i + 5;
8109 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8110
f10a1f2e
JP		 8111 netif_printk(np, probe, KERN_DEBUG, np->dev,
8112 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8113 vpd->fcode_major, vpd->fcode_minor);
a3138df9
DM		 8114 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8115 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8116 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8117 np->flags |= NIU_FLAGS_VPD_VALID;
8118}
8119
8120/* ESPC_PIO_EN_ENABLE must be set */
8121static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8122 u32 start, u32 end)
8123{
8124 unsigned int found_mask = 0;
8125#define FOUND_MASK_MODEL 0x00000001
8126#define FOUND_MASK_BMODEL 0x00000002
8127#define FOUND_MASK_VERS 0x00000004
8128#define FOUND_MASK_MAC 0x00000008
8129#define FOUND_MASK_NMAC 0x00000010
8130#define FOUND_MASK_PHY 0x00000020
8131#define FOUND_MASK_ALL 0x0000003f
8132
f10a1f2e
JP		 8133 netif_printk(np, probe, KERN_DEBUG, np->dev,
8134 "VPD_SCAN: start[%x] end[%x]\n", start, end);
a3138df9
DM		 8135 while (start < end) {
8136 int len, err, instance, type, prop_len;
8137 char namebuf[64];
8138 u8 *prop_buf;
8139 int max_len;
8140
8141 if (found_mask == FOUND_MASK_ALL) {
8142 niu_vpd_parse_version(np);
8143 return 1;
8144 }
8145
8146 err = niu_pci_eeprom_read(np, start + 2);
8147 if (err < 0)
8148 return err;
8149 len = err;
8150 start += 3;
8151
8152 instance = niu_pci_eeprom_read(np, start);
8153 type = niu_pci_eeprom_read(np, start + 3);
8154 prop_len = niu_pci_eeprom_read(np, start + 4);
8155 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8156 if (err < 0)
8157 return err;
8158
8159 prop_buf = NULL;
8160 max_len = 0;
8161 if (!strcmp(namebuf, "model")) {
8162 prop_buf = np->vpd.model;
8163 max_len = NIU_VPD_MODEL_MAX;
8164 found_mask |= FOUND_MASK_MODEL;
8165 } else if (!strcmp(namebuf, "board-model")) {
8166 prop_buf = np->vpd.board_model;
8167 max_len = NIU_VPD_BD_MODEL_MAX;
8168 found_mask |= FOUND_MASK_BMODEL;
8169 } else if (!strcmp(namebuf, "version")) {
8170 prop_buf = np->vpd.version;
8171 max_len = NIU_VPD_VERSION_MAX;
8172 found_mask |= FOUND_MASK_VERS;
8173 } else if (!strcmp(namebuf, "local-mac-address")) {
8174 prop_buf = np->vpd.local_mac;
8175 max_len = ETH_ALEN;
8176 found_mask |= FOUND_MASK_MAC;
8177 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8178 prop_buf = &np->vpd.mac_num;
8179 max_len = 1;
8180 found_mask |= FOUND_MASK_NMAC;
8181 } else if (!strcmp(namebuf, "phy-type")) {
8182 prop_buf = np->vpd.phy_type;
8183 max_len = NIU_VPD_PHY_TYPE_MAX;
8184 found_mask |= FOUND_MASK_PHY;
8185 }
8186
8187 if (max_len && prop_len > max_len) {
f10a1f2e 8188 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
a3138df9
DM		 8189 return -EINVAL;
8190 }
8191
8192 if (prop_buf) {
8193 u32 off = start + 5 + err;
8194 int i;
8195
f10a1f2e
JP		 8196 netif_printk(np, probe, KERN_DEBUG, np->dev,
8197 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8198 namebuf, prop_len);
a3138df9
DM		 8199 for (i = 0; i < prop_len; i++)
8200 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8201 }
8202
8203 start += len;
8204 }
8205
8206 return 0;
8207}
8208
8209/* ESPC_PIO_EN_ENABLE must be set */
8210static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8211{
8212 u32 offset;
8213 int err;
8214
8215 err = niu_pci_eeprom_read16_swp(np, start + 1);
8216 if (err < 0)
8217 return;
8218
8219 offset = err + 3;
8220
8221 while (start + offset < ESPC_EEPROM_SIZE) {
8222 u32 here = start + offset;
8223 u32 end;
8224
8225 err = niu_pci_eeprom_read(np, here);
8226 if (err != 0x90)
8227 return;
8228
8229 err = niu_pci_eeprom_read16_swp(np, here + 1);
8230 if (err < 0)
8231 return;
8232
8233 here = start + offset + 3;
8234 end = start + offset + err;
8235
8236 offset += err;
8237
8238 err = niu_pci_vpd_scan_props(np, here, end);
8239 if (err < 0 || err == 1)
8240 return;
8241 }
8242}
8243
8244/* ESPC_PIO_EN_ENABLE must be set */
8245static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8246{
8247 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8248 int err;
8249
8250 while (start < end) {
8251 ret = start;
8252
8253 /* ROM header signature? */
8254 err = niu_pci_eeprom_read16(np, start + 0);
8255 if (err != 0x55aa)
8256 return 0;
8257
8258 /* Apply offset to PCI data structure. */
8259 err = niu_pci_eeprom_read16(np, start + 23);
8260 if (err < 0)
8261 return 0;
8262 start += err;
8263
8264 /* Check for "PCIR" signature. */
8265 err = niu_pci_eeprom_read16(np, start + 0);
8266 if (err != 0x5043)
8267 return 0;
8268 err = niu_pci_eeprom_read16(np, start + 2);
8269 if (err != 0x4952)
8270 return 0;
8271
8272 /* Check for OBP image type. */
8273 err = niu_pci_eeprom_read(np, start + 20);
8274 if (err < 0)
8275 return 0;
8276 if (err != 0x01) {
8277 err = niu_pci_eeprom_read(np, ret + 2);
8278 if (err < 0)
8279 return 0;
8280
8281 start = ret + (err * 512);
8282 continue;
8283 }
8284
8285 err = niu_pci_eeprom_read16_swp(np, start + 8);
8286 if (err < 0)
8287 return err;
8288 ret += err;
8289
8290 err = niu_pci_eeprom_read(np, ret + 0);
8291 if (err != 0x82)
8292 return 0;
8293
8294 return ret;
8295 }
8296
8297 return 0;
8298}
8299
8300static int __devinit niu_phy_type_prop_decode(struct niu *np,
8301 const char *phy_prop)
8302{
8303 if (!strcmp(phy_prop, "mif")) {
8304 /* 1G copper, MII */
8305 np->flags &= ~(NIU_FLAGS_FIBER |
8306 NIU_FLAGS_10G);
8307 np->mac_xcvr = MAC_XCVR_MII;
8308 } else if (!strcmp(phy_prop, "xgf")) {
8309 /* 10G fiber, XPCS */
8310 np->flags |= (NIU_FLAGS_10G |
8311 NIU_FLAGS_FIBER);
8312 np->mac_xcvr = MAC_XCVR_XPCS;
8313 } else if (!strcmp(phy_prop, "pcs")) {
8314 /* 1G fiber, PCS */
8315 np->flags &= ~NIU_FLAGS_10G;
8316 np->flags |= NIU_FLAGS_FIBER;
8317 np->mac_xcvr = MAC_XCVR_PCS;
8318 } else if (!strcmp(phy_prop, "xgc")) {
8319 /* 10G copper, XPCS */
8320 np->flags |= NIU_FLAGS_10G;
8321 np->flags &= ~NIU_FLAGS_FIBER;
8322 np->mac_xcvr = MAC_XCVR_XPCS;
e3e081e1
SB		 8323 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8324 /* 10G Serdes or 1G Serdes, default to 10G */
8325 np->flags |= NIU_FLAGS_10G;
8326 np->flags &= ~NIU_FLAGS_FIBER;
8327 np->flags |= NIU_FLAGS_XCVR_SERDES;
8328 np->mac_xcvr = MAC_XCVR_XPCS;
a3138df9
DM		 8329 } else {
8330 return -EINVAL;
8331 }
8332 return 0;
8333}
8334
7f7c4072
MW		 8335static int niu_pci_vpd_get_nports(struct niu *np)
8336{
8337 int ports = 0;
8338
f9af8574
MW		 8339 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8340 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8341 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8342 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8343 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
7f7c4072 8344 ports = 4;
f9af8574
MW		 8345 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8346 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8347 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8348 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
7f7c4072
MW		 8349 ports = 2;
8350 }
8351
8352 return ports;
8353}
8354
a3138df9
DM		 8355static void __devinit niu_pci_vpd_validate(struct niu *np)
8356{
8357 struct net_device *dev = np->dev;
8358 struct niu_vpd *vpd = &np->vpd;
8359 u8 val8;
8360
8361 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
f10a1f2e 8362 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
a3138df9
DM		 8363
8364 np->flags &= ~NIU_FLAGS_VPD_VALID;
8365 return;
8366 }
8367
f9af8574
MW		 8368 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8369 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8370 np->flags |= NIU_FLAGS_10G;
8371 np->flags &= ~NIU_FLAGS_FIBER;
8372 np->flags |= NIU_FLAGS_XCVR_SERDES;
8373 np->mac_xcvr = MAC_XCVR_PCS;
8374 if (np->port > 1) {
8375 np->flags |= NIU_FLAGS_FIBER;
8376 np->flags &= ~NIU_FLAGS_10G;
8377 }
8378 if (np->flags & NIU_FLAGS_10G)
f10a1f2e 8379 np->mac_xcvr = MAC_XCVR_XPCS;
f9af8574 8380 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8381 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8382 NIU_FLAGS_HOTPLUG_PHY);
5fbd7e24 8383 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
f10a1f2e 8384 dev_err(np->device, "Illegal phy string [%s]\n",
a3138df9 8385 np->vpd.phy_type);
f10a1f2e 8386 dev_err(np->device, "Falling back to SPROM\n");
a3138df9
DM		 8387 np->flags &= ~NIU_FLAGS_VPD_VALID;
8388 return;
8389 }
8390
8391 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8392
8393 val8 = dev->perm_addr[5];
8394 dev->perm_addr[5] += np->port;
8395 if (dev->perm_addr[5] < val8)
8396 dev->perm_addr[4]++;
8397
8398 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8399}
8400
8401static int __devinit niu_pci_probe_sprom(struct niu *np)
8402{
8403 struct net_device *dev = np->dev;
8404 int len, i;
8405 u64 val, sum;
8406 u8 val8;
8407
8408 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8409 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8410 len = val / 4;
8411
8412 np->eeprom_len = len;
8413
f10a1f2e
JP		 8414 netif_printk(np, probe, KERN_DEBUG, np->dev,
8415 "SPROM: Image size %llu\n", (unsigned long long)val);
a3138df9
DM		 8416
8417 sum = 0;
8418 for (i = 0; i < len; i++) {
8419 val = nr64(ESPC_NCR(i));
8420 sum += (val >> 0) & 0xff;
8421 sum += (val >> 8) & 0xff;
8422 sum += (val >> 16) & 0xff;
8423 sum += (val >> 24) & 0xff;
8424 }
f10a1f2e
JP		 8425 netif_printk(np, probe, KERN_DEBUG, np->dev,
8426 "SPROM: Checksum %x\n", (int)(sum & 0xff));
a3138df9 8427 if ((sum & 0xff) != 0xab) {
f10a1f2e 8428 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
a3138df9
DM		 8429 return -EINVAL;
8430 }
8431
8432 val = nr64(ESPC_PHY_TYPE);
8433 switch (np->port) {
8434 case 0:
a9d41192 8435 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
a3138df9
DM		 8436 ESPC_PHY_TYPE_PORT0_SHIFT;
8437 break;
8438 case 1:
a9d41192 8439 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
a3138df9
DM		 8440 ESPC_PHY_TYPE_PORT1_SHIFT;
8441 break;
8442 case 2:
a9d41192 8443 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
a3138df9
DM		 8444 ESPC_PHY_TYPE_PORT2_SHIFT;
8445 break;
8446 case 3:
a9d41192 8447 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
a3138df9
DM		 8448 ESPC_PHY_TYPE_PORT3_SHIFT;
8449 break;
8450 default:
f10a1f2e 8451 dev_err(np->device, "Bogus port number %u\n",
a3138df9
DM		 8452 np->port);
8453 return -EINVAL;
8454 }
f10a1f2e
JP		 8455 netif_printk(np, probe, KERN_DEBUG, np->dev,
8456 "SPROM: PHY type %x\n", val8);
a3138df9 8457
a9d41192 8458 switch (val8) {
a3138df9
DM		 8459 case ESPC_PHY_TYPE_1G_COPPER:
8460 /* 1G copper, MII */
8461 np->flags &= ~(NIU_FLAGS_FIBER |
8462 NIU_FLAGS_10G);
8463 np->mac_xcvr = MAC_XCVR_MII;
8464 break;
8465
8466 case ESPC_PHY_TYPE_1G_FIBER:
8467 /* 1G fiber, PCS */
8468 np->flags &= ~NIU_FLAGS_10G;
8469 np->flags |= NIU_FLAGS_FIBER;
8470 np->mac_xcvr = MAC_XCVR_PCS;
8471 break;
8472
8473 case ESPC_PHY_TYPE_10G_COPPER:
8474 /* 10G copper, XPCS */
8475 np->flags |= NIU_FLAGS_10G;
8476 np->flags &= ~NIU_FLAGS_FIBER;
8477 np->mac_xcvr = MAC_XCVR_XPCS;
8478 break;
8479
8480 case ESPC_PHY_TYPE_10G_FIBER:
8481 /* 10G fiber, XPCS */
8482 np->flags |= (NIU_FLAGS_10G |
8483 NIU_FLAGS_FIBER);
8484 np->mac_xcvr = MAC_XCVR_XPCS;
8485 break;
8486
8487 default:
f10a1f2e 8488 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
a3138df9
DM		 8489 return -EINVAL;
8490 }
8491
8492 val = nr64(ESPC_MAC_ADDR0);
f10a1f2e
JP		 8493 netif_printk(np, probe, KERN_DEBUG, np->dev,
8494 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
a3138df9
DM		 8495 dev->perm_addr[0] = (val >> 0) & 0xff;
8496 dev->perm_addr[1] = (val >> 8) & 0xff;
8497 dev->perm_addr[2] = (val >> 16) & 0xff;
8498 dev->perm_addr[3] = (val >> 24) & 0xff;
8499
8500 val = nr64(ESPC_MAC_ADDR1);
f10a1f2e
JP		 8501 netif_printk(np, probe, KERN_DEBUG, np->dev,
8502 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
a3138df9
DM		 8503 dev->perm_addr[4] = (val >> 0) & 0xff;
8504 dev->perm_addr[5] = (val >> 8) & 0xff;
8505
8506 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
f10a1f2e
JP		 8507 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8508 dev->perm_addr);
a3138df9
DM		 8509 return -EINVAL;
8510 }
8511
8512 val8 = dev->perm_addr[5];
8513 dev->perm_addr[5] += np->port;
8514 if (dev->perm_addr[5] < val8)
8515 dev->perm_addr[4]++;
8516
8517 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8518
8519 val = nr64(ESPC_MOD_STR_LEN);
f10a1f2e
JP		 8520 netif_printk(np, probe, KERN_DEBUG, np->dev,
8521 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
e6a5fdf5 8522 if (val >= 8 * 4)
a3138df9
DM		 8523 return -EINVAL;
8524
8525 for (i = 0; i < val; i += 4) {
8526 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8527
8528 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
8529 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
8530 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8531 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8532 }
8533 np->vpd.model[val] = '\0';
8534
8535 val = nr64(ESPC_BD_MOD_STR_LEN);
f10a1f2e
JP		 8536 netif_printk(np, probe, KERN_DEBUG, np->dev,
8537 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
e6a5fdf5 8538 if (val >= 4 * 4)
a3138df9
DM		 8539 return -EINVAL;
8540
8541 for (i = 0; i < val; i += 4) {
8542 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8543
8544 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
8545 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
8546 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8547 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8548 }
8549 np->vpd.board_model[val] = '\0';
8550
8551 np->vpd.mac_num =
8552 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
f10a1f2e
JP		 8553 netif_printk(np, probe, KERN_DEBUG, np->dev,
8554 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
a3138df9
DM		 8555
8556 return 0;
8557}
8558
8559static int __devinit niu_get_and_validate_port(struct niu *np)
8560{
8561 struct niu_parent *parent = np->parent;
8562
8563 if (np->port <= 1)
8564 np->flags |= NIU_FLAGS_XMAC;
8565
8566 if (!parent->num_ports) {
8567 if (parent->plat_type == PLAT_TYPE_NIU) {
8568 parent->num_ports = 2;
8569 } else {
7f7c4072
MW		 8570 parent->num_ports = niu_pci_vpd_get_nports(np);
8571 if (!parent->num_ports) {
8572 /* Fall back to SPROM as last resort.
8573 * This will fail on most cards.
8574 */
8575 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8576 ESPC_NUM_PORTS_MACS_VAL;
8577
be0c007a
DM		 8578 /* All of the current probing methods fail on
8579 * Maramba on-board parts.
8580 */
7f7c4072 8581 if (!parent->num_ports)
be0c007a 8582 parent->num_ports = 4;
7f7c4072 8583 }
a3138df9
DM		 8584 }
8585 }
8586
a3138df9
DM		 8587 if (np->port >= parent->num_ports)
8588 return -ENODEV;
8589
8590 return 0;
8591}
8592
8593static int __devinit phy_record(struct niu_parent *parent,
8594 struct phy_probe_info *p,
8595 int dev_id_1, int dev_id_2, u8 phy_port,
8596 int type)
8597{
8598 u32 id = (dev_id_1 << 16) | dev_id_2;
8599 u8 idx;
8600
8601 if (dev_id_1 < 0 || dev_id_2 < 0)
8602 return 0;
8603 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
b0de8e40 8604 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
a5d6ab56
MW		 8605 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
8606 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
a3138df9
DM		 8607 return 0;
8608 } else {
8609 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8610 return 0;
8611 }
8612
8613 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8614 parent->index, id,
f10a1f2e
JP		 8615 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8616 type == PHY_TYPE_PCS ? "PCS" : "MII",
a3138df9
DM		 8617 phy_port);
8618
8619 if (p->cur[type] >= NIU_MAX_PORTS) {
f10a1f2e 8620 pr_err("Too many PHY ports\n");
a3138df9
DM		 8621 return -EINVAL;
8622 }
8623 idx = p->cur[type];
8624 p->phy_id[type][idx] = id;
8625 p->phy_port[type][idx] = phy_port;
8626 p->cur[type] = idx + 1;
8627 return 0;
8628}
8629
8630static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8631{
8632 int i;
8633
8634 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8635 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8636 return 1;
8637 }
8638 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8639 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8640 return 1;
8641 }
8642
8643 return 0;
8644}
8645
8646static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8647{
8648 int port, cnt;
8649
8650 cnt = 0;
8651 *lowest = 32;
8652 for (port = 8; port < 32; port++) {
8653 if (port_has_10g(p, port)) {
8654 if (!cnt)
8655 *lowest = port;
8656 cnt++;
8657 }
8658 }
8659
8660 return cnt;
8661}
8662
8663static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8664{
8665 *lowest = 32;
8666 if (p->cur[PHY_TYPE_MII])
8667 *lowest = p->phy_port[PHY_TYPE_MII][0];
8668
8669 return p->cur[PHY_TYPE_MII];
8670}
8671
8672static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8673{
8674 int num_ports = parent->num_ports;
8675 int i;
8676
8677 for (i = 0; i < num_ports; i++) {
8678 parent->rxchan_per_port[i] = (16 / num_ports);
8679 parent->txchan_per_port[i] = (16 / num_ports);
8680
f10a1f2e 8681 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
a3138df9
DM		 8682 parent->index, i,
8683 parent->rxchan_per_port[i],
8684 parent->txchan_per_port[i]);
8685 }
8686}
8687
8688static void __devinit niu_divide_channels(struct niu_parent *parent,
8689 int num_10g, int num_1g)
8690{
8691 int num_ports = parent->num_ports;
8692 int rx_chans_per_10g, rx_chans_per_1g;
8693 int tx_chans_per_10g, tx_chans_per_1g;
8694 int i, tot_rx, tot_tx;
8695
8696 if (!num_10g || !num_1g) {
8697 rx_chans_per_10g = rx_chans_per_1g =
8698 (NIU_NUM_RXCHAN / num_ports);
8699 tx_chans_per_10g = tx_chans_per_1g =
8700 (NIU_NUM_TXCHAN / num_ports);
8701 } else {
8702 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8703 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8704 (rx_chans_per_1g * num_1g)) /
8705 num_10g;
8706
8707 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8708 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8709 (tx_chans_per_1g * num_1g)) /
8710 num_10g;
8711 }
8712
8713 tot_rx = tot_tx = 0;
8714 for (i = 0; i < num_ports; i++) {
8715 int type = phy_decode(parent->port_phy, i);
8716
8717 if (type == PORT_TYPE_10G) {
8718 parent->rxchan_per_port[i] = rx_chans_per_10g;
8719 parent->txchan_per_port[i] = tx_chans_per_10g;
8720 } else {
8721 parent->rxchan_per_port[i] = rx_chans_per_1g;
8722 parent->txchan_per_port[i] = tx_chans_per_1g;
8723 }
f10a1f2e 8724 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
a3138df9
DM		 8725 parent->index, i,
8726 parent->rxchan_per_port[i],
8727 parent->txchan_per_port[i]);
8728 tot_rx += parent->rxchan_per_port[i];
8729 tot_tx += parent->txchan_per_port[i];
8730 }
8731
8732 if (tot_rx > NIU_NUM_RXCHAN) {
f10a1f2e 8733 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
a3138df9
DM		 8734 parent->index, tot_rx);
8735 for (i = 0; i < num_ports; i++)
8736 parent->rxchan_per_port[i] = 1;
8737 }
8738 if (tot_tx > NIU_NUM_TXCHAN) {
f10a1f2e 8739 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
a3138df9
DM		 8740 parent->index, tot_tx);
8741 for (i = 0; i < num_ports; i++)
8742 parent->txchan_per_port[i] = 1;
8743 }
8744 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
f10a1f2e
JP		 8745 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8746 parent->index, tot_rx, tot_tx);
a3138df9
DM		 8747 }
8748}
8749
8750static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8751 int num_10g, int num_1g)
8752{
8753 int i, num_ports = parent->num_ports;
8754 int rdc_group, rdc_groups_per_port;
8755 int rdc_channel_base;
8756
8757 rdc_group = 0;
8758 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8759
8760 rdc_channel_base = 0;
8761
8762 for (i = 0; i < num_ports; i++) {
8763 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8764 int grp, num_channels = parent->rxchan_per_port[i];
8765 int this_channel_offset;
8766
8767 tp->first_table_num = rdc_group;
8768 tp->num_tables = rdc_groups_per_port;
8769 this_channel_offset = 0;
8770 for (grp = 0; grp < tp->num_tables; grp++) {
8771 struct rdc_table *rt = &tp->tables[grp];
8772 int slot;
8773
f10a1f2e 8774 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
a3138df9
DM		 8775 parent->index, i, tp->first_table_num + grp);
8776 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8777 rt->rxdma_channel[slot] =
8778 rdc_channel_base + this_channel_offset;
8779
f10a1f2e 8780 pr_cont("%d ", rt->rxdma_channel[slot]);
a3138df9
DM		 8781
8782 if (++this_channel_offset == num_channels)
8783 this_channel_offset = 0;
8784 }
f10a1f2e 8785 pr_cont("]\n");
a3138df9
DM		 8786 }
8787
8788 parent->rdc_default[i] = rdc_channel_base;
8789
8790 rdc_channel_base += num_channels;
8791 rdc_group += rdc_groups_per_port;
8792 }
8793}
8794
8795static int __devinit fill_phy_probe_info(struct niu *np,
8796 struct niu_parent *parent,
8797 struct phy_probe_info *info)
8798{
8799 unsigned long flags;
8800 int port, err;
8801
8802 memset(info, 0, sizeof(*info));
8803
8804 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8805 niu_lock_parent(np, flags);
8806 err = 0;
8807 for (port = 8; port < 32; port++) {
8808 int dev_id_1, dev_id_2;
8809
8810 dev_id_1 = mdio_read(np, port,
8811 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8812 dev_id_2 = mdio_read(np, port,
8813 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8814 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8815 PHY_TYPE_PMA_PMD);
8816 if (err)
8817 break;
8818 dev_id_1 = mdio_read(np, port,
8819 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8820 dev_id_2 = mdio_read(np, port,
8821 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8822 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8823 PHY_TYPE_PCS);
8824 if (err)
8825 break;
8826 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8827 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8828 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8829 PHY_TYPE_MII);
8830 if (err)
8831 break;
8832 }
8833 niu_unlock_parent(np, flags);
8834
8835 return err;
8836}
8837
8838static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8839{
8840 struct phy_probe_info *info = &parent->phy_probe_info;
8841 int lowest_10g, lowest_1g;
8842 int num_10g, num_1g;
8843 u32 val;
8844 int err;
8845
e3e081e1
SB		 8846 num_10g = num_1g = 0;
8847
f9af8574
MW		 8848 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8849 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8850 num_10g = 0;
8851 num_1g = 2;
8852 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8853 parent->num_ports = 4;
8854 val = (phy_encode(PORT_TYPE_1G, 0) |
8855 phy_encode(PORT_TYPE_1G, 1) |
a3138df9
DM		 8856 phy_encode(PORT_TYPE_1G, 2) |
8857 phy_encode(PORT_TYPE_1G, 3));
f9af8574 8858 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8859 num_10g = 2;
8860 num_1g = 0;
8861 parent->num_ports = 2;
8862 val = (phy_encode(PORT_TYPE_10G, 0) |
8863 phy_encode(PORT_TYPE_10G, 1));
e3e081e1
SB		 8864 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8865 (parent->plat_type == PLAT_TYPE_NIU)) {
8866 /* this is the Monza case */
8867 if (np->flags & NIU_FLAGS_10G) {
8868 val = (phy_encode(PORT_TYPE_10G, 0) |
8869 phy_encode(PORT_TYPE_10G, 1));
8870 } else {
8871 val = (phy_encode(PORT_TYPE_1G, 0) |
8872 phy_encode(PORT_TYPE_1G, 1));
8873 }
5fbd7e24
MW		 8874 } else {
8875 err = fill_phy_probe_info(np, parent, info);
8876 if (err)
8877 return err;
a3138df9 8878
5fbd7e24
MW		 8879 num_10g = count_10g_ports(info, &lowest_10g);
8880 num_1g = count_1g_ports(info, &lowest_1g);
a3138df9 8881
5fbd7e24
MW		 8882 switch ((num_10g << 4) | num_1g) {
8883 case 0x24:
8884 if (lowest_1g == 10)
8885 parent->plat_type = PLAT_TYPE_VF_P0;
8886 else if (lowest_1g == 26)
8887 parent->plat_type = PLAT_TYPE_VF_P1;
8888 else
8889 goto unknown_vg_1g_port;
a3138df9 8890
5fbd7e24
MW		 8891 /* fallthru */
8892 case 0x22:
a3138df9 8893 val = (phy_encode(PORT_TYPE_10G, 0) |
a3138df9
DM		 8894 phy_encode(PORT_TYPE_10G, 1) |
8895 phy_encode(PORT_TYPE_1G, 2) |
8896 phy_encode(PORT_TYPE_1G, 3));
5fbd7e24 8897 break;
a3138df9 8898
5fbd7e24
MW		 8899 case 0x20:
8900 val = (phy_encode(PORT_TYPE_10G, 0) |
8901 phy_encode(PORT_TYPE_10G, 1));
8902 break;
a3138df9 8903
5fbd7e24
MW		 8904 case 0x10:
8905 val = phy_encode(PORT_TYPE_10G, np->port);
8906 break;
a3138df9 8907
5fbd7e24
MW		 8908 case 0x14:
8909 if (lowest_1g == 10)
8910 parent->plat_type = PLAT_TYPE_VF_P0;
8911 else if (lowest_1g == 26)
8912 parent->plat_type = PLAT_TYPE_VF_P1;
8913 else
8914 goto unknown_vg_1g_port;
8915
8916 /* fallthru */
8917 case 0x13:
8918 if ((lowest_10g & 0x7) == 0)
8919 val = (phy_encode(PORT_TYPE_10G, 0) |
8920 phy_encode(PORT_TYPE_1G, 1) |
8921 phy_encode(PORT_TYPE_1G, 2) |
8922 phy_encode(PORT_TYPE_1G, 3));
8923 else
8924 val = (phy_encode(PORT_TYPE_1G, 0) |
8925 phy_encode(PORT_TYPE_10G, 1) |
8926 phy_encode(PORT_TYPE_1G, 2) |
8927 phy_encode(PORT_TYPE_1G, 3));
8928 break;
8929
8930 case 0x04:
8931 if (lowest_1g == 10)
8932 parent->plat_type = PLAT_TYPE_VF_P0;
8933 else if (lowest_1g == 26)
8934 parent->plat_type = PLAT_TYPE_VF_P1;
8935 else
8936 goto unknown_vg_1g_port;
8937
8938 val = (phy_encode(PORT_TYPE_1G, 0) |
8939 phy_encode(PORT_TYPE_1G, 1) |
8940 phy_encode(PORT_TYPE_1G, 2) |
8941 phy_encode(PORT_TYPE_1G, 3));
8942 break;
8943
8944 default:
f10a1f2e 8945 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
5fbd7e24
MW		 8946 num_10g, num_1g);
8947 return -EINVAL;
8948 }
a3138df9
DM		 8949 }
8950
8951 parent->port_phy = val;
8952
8953 if (parent->plat_type == PLAT_TYPE_NIU)
8954 niu_n2_divide_channels(parent);
8955 else
8956 niu_divide_channels(parent, num_10g, num_1g);
8957
8958 niu_divide_rdc_groups(parent, num_10g, num_1g);
8959
8960 return 0;
8961
8962unknown_vg_1g_port:
f10a1f2e 8963 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
a3138df9
DM		 8964 return -EINVAL;
8965}
8966
8967static int __devinit niu_probe_ports(struct niu *np)
8968{
8969 struct niu_parent *parent = np->parent;
8970 int err, i;
8971
a3138df9
DM		 8972 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8973 err = walk_phys(np, parent);
8974 if (err)
8975 return err;
8976
8977 niu_set_ldg_timer_res(np, 2);
8978 for (i = 0; i <= LDN_MAX; i++)
8979 niu_ldn_irq_enable(np, i, 0);
8980 }
8981
8982 if (parent->port_phy == PORT_PHY_INVALID)
8983 return -EINVAL;
8984
8985 return 0;
8986}
8987
8988static int __devinit niu_classifier_swstate_init(struct niu *np)
8989{
8990 struct niu_classifier *cp = &np->clas;
8991
2d96cf8c
SB		 8992 cp->tcam_top = (u16) np->port;
8993 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
a3138df9
DM		 8994 cp->h1_init = 0xffffffff;
8995 cp->h2_init = 0xffff;
8996
8997 return fflp_early_init(np);
8998}
8999
9000static void __devinit niu_link_config_init(struct niu *np)
9001{
9002 struct niu_link_config *lp = &np->link_config;
9003
9004 lp->advertising = (ADVERTISED_10baseT_Half |
9005 ADVERTISED_10baseT_Full |
9006 ADVERTISED_100baseT_Half |
9007 ADVERTISED_100baseT_Full |
9008 ADVERTISED_1000baseT_Half |
9009 ADVERTISED_1000baseT_Full |
9010 ADVERTISED_10000baseT_Full |
9011 ADVERTISED_Autoneg);
9012 lp->speed = lp->active_speed = SPEED_INVALID;
38bb045d
CB		 9013 lp->duplex = DUPLEX_FULL;
9014 lp->active_duplex = DUPLEX_INVALID;
9015 lp->autoneg = 1;
a3138df9
DM		 9016#if 0
9017 lp->loopback_mode = LOOPBACK_MAC;
9018 lp->active_speed = SPEED_10000;
9019 lp->active_duplex = DUPLEX_FULL;
9020#else
9021 lp->loopback_mode = LOOPBACK_DISABLED;
9022#endif
9023}
9024
9025static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
9026{
9027 switch (np->port) {
9028 case 0:
9029 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9030 np->ipp_off = 0x00000;
9031 np->pcs_off = 0x04000;
9032 np->xpcs_off = 0x02000;
9033 break;
9034
9035 case 1:
9036 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9037 np->ipp_off = 0x08000;
9038 np->pcs_off = 0x0a000;
9039 np->xpcs_off = 0x08000;
9040 break;
9041
9042 case 2:
9043 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9044 np->ipp_off = 0x04000;
9045 np->pcs_off = 0x0e000;
9046 np->xpcs_off = ~0UL;
9047 break;
9048
9049 case 3:
9050 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9051 np->ipp_off = 0x0c000;
9052 np->pcs_off = 0x12000;
9053 np->xpcs_off = ~0UL;
9054 break;
9055
9056 default:
f10a1f2e 9057 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
a3138df9
DM		 9058 return -EINVAL;
9059 }
9060
9061 return 0;
9062}
9063
9064static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9065{
9066 struct msix_entry msi_vec[NIU_NUM_LDG];
9067 struct niu_parent *parent = np->parent;
9068 struct pci_dev *pdev = np->pdev;
9069 int i, num_irqs, err;
9070 u8 first_ldg;
9071
9072 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9073 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9074 ldg_num_map[i] = first_ldg + i;
9075
9076 num_irqs = (parent->rxchan_per_port[np->port] +
9077 parent->txchan_per_port[np->port] +
9078 (np->port == 0 ? 3 : 1));
9079 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9080
9081retry:
9082 for (i = 0; i < num_irqs; i++) {
9083 msi_vec[i].vector = 0;
9084 msi_vec[i].entry = i;
9085 }
9086
9087 err = pci_enable_msix(pdev, msi_vec, num_irqs);
9088 if (err < 0) {
9089 np->flags &= ~NIU_FLAGS_MSIX;
9090 return;
9091 }
9092 if (err > 0) {
9093 num_irqs = err;
9094 goto retry;
9095 }
9096
9097 np->flags |= NIU_FLAGS_MSIX;
9098 for (i = 0; i < num_irqs; i++)
9099 np->ldg[i].irq = msi_vec[i].vector;
9100 np->num_ldg = num_irqs;
9101}
9102
9103static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9104{
9105#ifdef CONFIG_SPARC64
2dc11581 9106 struct platform_device *op = np->op;
a3138df9
DM		 9107 const u32 *int_prop;
9108 int i;
9109
61c7a080 9110 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL);
a3138df9
DM		 9111 if (!int_prop)
9112 return -ENODEV;
9113
1636f8ac 9114 for (i = 0; i < op->archdata.num_irqs; i++) {
a3138df9 9115 ldg_num_map[i] = int_prop[i];
1636f8ac 9116 np->ldg[i].irq = op->archdata.irqs[i];
a3138df9
DM		 9117 }
9118
1636f8ac 9119 np->num_ldg = op->archdata.num_irqs;
a3138df9
DM		 9120
9121 return 0;
9122#else
9123 return -EINVAL;
9124#endif
9125}
9126
9127static int __devinit niu_ldg_init(struct niu *np)
9128{
9129 struct niu_parent *parent = np->parent;
9130 u8 ldg_num_map[NIU_NUM_LDG];
9131 int first_chan, num_chan;
9132 int i, err, ldg_rotor;
9133 u8 port;
9134
9135 np->num_ldg = 1;
9136 np->ldg[0].irq = np->dev->irq;
9137 if (parent->plat_type == PLAT_TYPE_NIU) {
9138 err = niu_n2_irq_init(np, ldg_num_map);
9139 if (err)
9140 return err;
9141 } else
9142 niu_try_msix(np, ldg_num_map);
9143
9144 port = np->port;
9145 for (i = 0; i < np->num_ldg; i++) {
9146 struct niu_ldg *lp = &np->ldg[i];
9147
9148 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9149
9150 lp->np = np;
9151 lp->ldg_num = ldg_num_map[i];
9152 lp->timer = 2; /* XXX */
9153
9154 /* On N2 NIU the firmware has setup the SID mappings so they go
9155 * to the correct values that will route the LDG to the proper
9156 * interrupt in the NCU interrupt table.
9157 */
9158 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9159 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9160 if (err)
9161 return err;
9162 }
9163 }
9164
9165 /* We adopt the LDG assignment ordering used by the N2 NIU
9166 * 'interrupt' properties because that simplifies a lot of
9167 * things. This ordering is:
9168 *
9169 * MAC
9170 * MIF (if port zero)
9171 * SYSERR (if port zero)
9172 * RX channels
9173 * TX channels
9174 */
9175
9176 ldg_rotor = 0;
9177
9178 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9179 LDN_MAC(port));
9180 if (err)
9181 return err;
9182
9183 ldg_rotor++;
9184 if (ldg_rotor == np->num_ldg)
9185 ldg_rotor = 0;
9186
9187 if (port == 0) {
9188 err = niu_ldg_assign_ldn(np, parent,
9189 ldg_num_map[ldg_rotor],
9190 LDN_MIF);
9191 if (err)
9192 return err;
9193
9194 ldg_rotor++;
9195 if (ldg_rotor == np->num_ldg)
9196 ldg_rotor = 0;
9197
9198 err = niu_ldg_assign_ldn(np, parent,
9199 ldg_num_map[ldg_rotor],
9200 LDN_DEVICE_ERROR);
9201 if (err)
9202 return err;
9203
9204 ldg_rotor++;
9205 if (ldg_rotor == np->num_ldg)
9206 ldg_rotor = 0;
9207
9208 }
9209
9210 first_chan = 0;
9211 for (i = 0; i < port; i++)
9212 first_chan += parent->rxchan_per_port[port];
9213 num_chan = parent->rxchan_per_port[port];
9214
9215 for (i = first_chan; i < (first_chan + num_chan); i++) {
9216 err = niu_ldg_assign_ldn(np, parent,
9217 ldg_num_map[ldg_rotor],
9218 LDN_RXDMA(i));
9219 if (err)
9220 return err;
9221 ldg_rotor++;
9222 if (ldg_rotor == np->num_ldg)
9223 ldg_rotor = 0;
9224 }
9225
9226 first_chan = 0;
9227 for (i = 0; i < port; i++)
9228 first_chan += parent->txchan_per_port[port];
9229 num_chan = parent->txchan_per_port[port];
9230 for (i = first_chan; i < (first_chan + num_chan); i++) {
9231 err = niu_ldg_assign_ldn(np, parent,
9232 ldg_num_map[ldg_rotor],
9233 LDN_TXDMA(i));
9234 if (err)
9235 return err;
9236 ldg_rotor++;
9237 if (ldg_rotor == np->num_ldg)
9238 ldg_rotor = 0;
9239 }
9240
9241 return 0;
9242}
9243
9244static void __devexit niu_ldg_free(struct niu *np)
9245{
9246 if (np->flags & NIU_FLAGS_MSIX)
9247 pci_disable_msix(np->pdev);
9248}
9249
9250static int __devinit niu_get_of_props(struct niu *np)
9251{
9252#ifdef CONFIG_SPARC64
9253 struct net_device *dev = np->dev;
9254 struct device_node *dp;
9255 const char *phy_type;
9256 const u8 *mac_addr;
f9af8574 9257 const char *model;
a3138df9
DM		 9258 int prop_len;
9259
9260 if (np->parent->plat_type == PLAT_TYPE_NIU)
61c7a080 9261 dp = np->op->dev.of_node;
a3138df9
DM		 9262 else
9263 dp = pci_device_to_OF_node(np->pdev);
9264
9265 phy_type = of_get_property(dp, "phy-type", &prop_len);
9266 if (!phy_type) {
f10a1f2e
JP		 9267 netdev_err(dev, "%s: OF node lacks phy-type property\n",
9268 dp->full_name);
a3138df9
DM		 9269 return -EINVAL;
9270 }
9271
9272 if (!strcmp(phy_type, "none"))
9273 return -ENODEV;
9274
9275 strcpy(np->vpd.phy_type, phy_type);
9276
9277 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
f10a1f2e
JP		 9278 netdev_err(dev, "%s: Illegal phy string [%s]\n",
9279 dp->full_name, np->vpd.phy_type);
a3138df9
DM		 9280 return -EINVAL;
9281 }
9282
9283 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9284 if (!mac_addr) {
f10a1f2e
JP		 9285 netdev_err(dev, "%s: OF node lacks local-mac-address property\n",
9286 dp->full_name);
a3138df9
DM		 9287 return -EINVAL;
9288 }
9289 if (prop_len != dev->addr_len) {
f10a1f2e
JP		 9290 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n",
9291 dp->full_name, prop_len);
a3138df9
DM		 9292 }
9293 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9294 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
f10a1f2e
JP		 9295 netdev_err(dev, "%s: OF MAC address is invalid\n",
9296 dp->full_name);
9297 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->perm_addr);
a3138df9
DM		 9298 return -EINVAL;
9299 }
9300
9301 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
f9af8574
MW		 9302
9303 model = of_get_property(dp, "model", &prop_len);
9304
9305 if (model)
9306 strcpy(np->vpd.model, model);
a3138df9 9307
9c5cd670
TC		 9308 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9309 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9310 NIU_FLAGS_HOTPLUG_PHY);
9311 }
9312
a3138df9
DM		 9313 return 0;
9314#else
9315 return -EINVAL;
9316#endif
9317}
9318
9319static int __devinit niu_get_invariants(struct niu *np)
9320{
9321 int err, have_props;
9322 u32 offset;
9323
9324 err = niu_get_of_props(np);
9325 if (err == -ENODEV)
9326 return err;
9327
9328 have_props = !err;
9329
a3138df9
DM		 9330 err = niu_init_mac_ipp_pcs_base(np);
9331 if (err)
9332 return err;
9333
7f7c4072
MW		 9334 if (have_props) {
9335 err = niu_get_and_validate_port(np);
9336 if (err)
9337 return err;
9338
9339 } else {
a3138df9
DM		 9340 if (np->parent->plat_type == PLAT_TYPE_NIU)
9341 return -EINVAL;
9342
9343 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9344 offset = niu_pci_vpd_offset(np);
f10a1f2e
JP		 9345 netif_printk(np, probe, KERN_DEBUG, np->dev,
9346 "%s() VPD offset [%08x]\n", __func__, offset);
a3138df9
DM		 9347 if (offset)
9348 niu_pci_vpd_fetch(np, offset);
9349 nw64(ESPC_PIO_EN, 0);
9350
7f7c4072 9351 if (np->flags & NIU_FLAGS_VPD_VALID) {
a3138df9 9352 niu_pci_vpd_validate(np);
7f7c4072
MW		 9353 err = niu_get_and_validate_port(np);
9354 if (err)
9355 return err;
9356 }
a3138df9
DM		 9357
9358 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
7f7c4072
MW		 9359 err = niu_get_and_validate_port(np);
9360 if (err)
9361 return err;
a3138df9
DM		 9362 err = niu_pci_probe_sprom(np);
9363 if (err)
9364 return err;
9365 }
9366 }
9367
9368 err = niu_probe_ports(np);
9369 if (err)
9370 return err;
9371
9372 niu_ldg_init(np);
9373
9374 niu_classifier_swstate_init(np);
9375 niu_link_config_init(np);
9376
9377 err = niu_determine_phy_disposition(np);
9378 if (!err)
9379 err = niu_init_link(np);
9380
9381 return err;
9382}
9383
9384static LIST_HEAD(niu_parent_list);
9385static DEFINE_MUTEX(niu_parent_lock);
9386static int niu_parent_index;
9387
9388static ssize_t show_port_phy(struct device *dev,
9389 struct device_attribute *attr, char *buf)
9390{
9391 struct platform_device *plat_dev = to_platform_device(dev);
9392 struct niu_parent *p = plat_dev->dev.platform_data;
9393 u32 port_phy = p->port_phy;
9394 char *orig_buf = buf;
9395 int i;
9396
9397 if (port_phy == PORT_PHY_UNKNOWN ||
9398 port_phy == PORT_PHY_INVALID)
9399 return 0;
9400
9401 for (i = 0; i < p->num_ports; i++) {
9402 const char *type_str;
9403 int type;
9404
9405 type = phy_decode(port_phy, i);
9406 if (type == PORT_TYPE_10G)
9407 type_str = "10G";
9408 else
9409 type_str = "1G";
9410 buf += sprintf(buf,
9411 (i == 0) ? "%s" : " %s",
9412 type_str);
9413 }
9414 buf += sprintf(buf, "\n");
9415 return buf - orig_buf;
9416}
9417
9418static ssize_t show_plat_type(struct device *dev,
9419 struct device_attribute *attr, char *buf)
9420{
9421 struct platform_device *plat_dev = to_platform_device(dev);
9422 struct niu_parent *p = plat_dev->dev.platform_data;
9423 const char *type_str;
9424
9425 switch (p->plat_type) {
9426 case PLAT_TYPE_ATLAS:
9427 type_str = "atlas";
9428 break;
9429 case PLAT_TYPE_NIU:
9430 type_str = "niu";
9431 break;
9432 case PLAT_TYPE_VF_P0:
9433 type_str = "vf_p0";
9434 break;
9435 case PLAT_TYPE_VF_P1:
9436 type_str = "vf_p1";
9437 break;
9438 default:
9439 type_str = "unknown";
9440 break;
9441 }
9442
9443 return sprintf(buf, "%s\n", type_str);
9444}
9445
9446static ssize_t __show_chan_per_port(struct device *dev,
9447 struct device_attribute *attr, char *buf,
9448 int rx)
9449{
9450 struct platform_device *plat_dev = to_platform_device(dev);
9451 struct niu_parent *p = plat_dev->dev.platform_data;
9452 char *orig_buf = buf;
9453 u8 *arr;
9454 int i;
9455
9456 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9457
9458 for (i = 0; i < p->num_ports; i++) {
9459 buf += sprintf(buf,
9460 (i == 0) ? "%d" : " %d",
9461 arr[i]);
9462 }
9463 buf += sprintf(buf, "\n");
9464
9465 return buf - orig_buf;
9466}
9467
9468static ssize_t show_rxchan_per_port(struct device *dev,
9469 struct device_attribute *attr, char *buf)
9470{
9471 return __show_chan_per_port(dev, attr, buf, 1);
9472}
9473
9474static ssize_t show_txchan_per_port(struct device *dev,
9475 struct device_attribute *attr, char *buf)
9476{
9477 return __show_chan_per_port(dev, attr, buf, 1);
9478}
9479
9480static ssize_t show_num_ports(struct device *dev,
9481 struct device_attribute *attr, char *buf)
9482{
9483 struct platform_device *plat_dev = to_platform_device(dev);
9484 struct niu_parent *p = plat_dev->dev.platform_data;
9485
9486 return sprintf(buf, "%d\n", p->num_ports);
9487}
9488
9489static struct device_attribute niu_parent_attributes[] = {
9490 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9491 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9492 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9493 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9494 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9495 {}
9496};
9497
9498static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9499 union niu_parent_id *id,
9500 u8 ptype)
9501{
9502 struct platform_device *plat_dev;
9503 struct niu_parent *p;
9504 int i;
9505
a3138df9
DM		 9506 plat_dev = platform_device_register_simple("niu", niu_parent_index,
9507 NULL, 0);
58f3e0a8 9508 if (IS_ERR(plat_dev))
a3138df9
DM		 9509 return NULL;
9510
9511 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9512 int err = device_create_file(&plat_dev->dev,
9513 &niu_parent_attributes[i]);
9514 if (err)
9515 goto fail_unregister;
9516 }
9517
9518 p = kzalloc(sizeof(*p), GFP_KERNEL);
9519 if (!p)
9520 goto fail_unregister;
9521
9522 p->index = niu_parent_index++;
9523
9524 plat_dev->dev.platform_data = p;
9525 p->plat_dev = plat_dev;
9526
9527 memcpy(&p->id, id, sizeof(*id));
9528 p->plat_type = ptype;
9529 INIT_LIST_HEAD(&p->list);
9530 atomic_set(&p->refcnt, 0);
9531 list_add(&p->list, &niu_parent_list);
9532 spin_lock_init(&p->lock);
9533
9534 p->rxdma_clock_divider = 7500;
9535
9536 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9537 if (p->plat_type == PLAT_TYPE_NIU)
9538 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9539
9540 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9541 int index = i - CLASS_CODE_USER_PROG1;
9542
9543 p->tcam_key[index] = TCAM_KEY_TSEL;
9544 p->flow_key[index] = (FLOW_KEY_IPSA |
9545 FLOW_KEY_IPDA |
9546 FLOW_KEY_PROTO |
9547 (FLOW_KEY_L4_BYTE12 <<
9548 FLOW_KEY_L4_0_SHIFT) |
9549 (FLOW_KEY_L4_BYTE12 <<
9550 FLOW_KEY_L4_1_SHIFT));
9551 }
9552
9553 for (i = 0; i < LDN_MAX + 1; i++)
9554 p->ldg_map[i] = LDG_INVALID;
9555
9556 return p;
9557
9558fail_unregister:
9559 platform_device_unregister(plat_dev);
9560 return NULL;
9561}
9562
9563static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9564 union niu_parent_id *id,
9565 u8 ptype)
9566{
9567 struct niu_parent *p, *tmp;
9568 int port = np->port;
9569
a3138df9
DM		 9570 mutex_lock(&niu_parent_lock);
9571 p = NULL;
9572 list_for_each_entry(tmp, &niu_parent_list, list) {
9573 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9574 p = tmp;
9575 break;
9576 }
9577 }
9578 if (!p)
9579 p = niu_new_parent(np, id, ptype);
9580
9581 if (p) {
9582 char port_name[6];
9583 int err;
9584
9585 sprintf(port_name, "port%d", port);
9586 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9587 &np->device->kobj,
9588 port_name);
9589 if (!err) {
9590 p->ports[port] = np;
9591 atomic_inc(&p->refcnt);
9592 }
9593 }
9594 mutex_unlock(&niu_parent_lock);
9595
9596 return p;
9597}
9598
9599static void niu_put_parent(struct niu *np)
9600{
9601 struct niu_parent *p = np->parent;
9602 u8 port = np->port;
9603 char port_name[6];
9604
9605 BUG_ON(!p || p->ports[port] != np);
9606
f10a1f2e
JP		 9607 netif_printk(np, probe, KERN_DEBUG, np->dev,
9608 "%s() port[%u]\n", __func__, port);
a3138df9
DM		 9609
9610 sprintf(port_name, "port%d", port);
9611
9612 mutex_lock(&niu_parent_lock);
9613
9614 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9615
9616 p->ports[port] = NULL;
9617 np->parent = NULL;
9618
9619 if (atomic_dec_and_test(&p->refcnt)) {
9620 list_del(&p->list);
9621 platform_device_unregister(p->plat_dev);
9622 }
9623
9624 mutex_unlock(&niu_parent_lock);
9625}
9626
9627static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9628 u64 *handle, gfp_t flag)
9629{
9630 dma_addr_t dh;
9631 void *ret;
9632
9633 ret = dma_alloc_coherent(dev, size, &dh, flag);
9634 if (ret)
9635 *handle = dh;
9636 return ret;
9637}
9638
9639static void niu_pci_free_coherent(struct device *dev, size_t size,
9640 void *cpu_addr, u64 handle)
9641{
9642 dma_free_coherent(dev, size, cpu_addr, handle);
9643}
9644
9645static u64 niu_pci_map_page(struct device *dev, struct page *page,
9646 unsigned long offset, size_t size,
9647 enum dma_data_direction direction)
9648{
9649 return dma_map_page(dev, page, offset, size, direction);
9650}
9651
9652static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9653 size_t size, enum dma_data_direction direction)
9654{
a08b32df 9655 dma_unmap_page(dev, dma_address, size, direction);
a3138df9
DM		 9656}
9657
9658static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9659 size_t size,
9660 enum dma_data_direction direction)
9661{
9662 return dma_map_single(dev, cpu_addr, size, direction);
9663}
9664
9665static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9666 size_t size,
9667 enum dma_data_direction direction)
9668{
9669 dma_unmap_single(dev, dma_address, size, direction);
9670}
9671
9672static const struct niu_ops niu_pci_ops = {
9673 .alloc_coherent = niu_pci_alloc_coherent,
9674 .free_coherent = niu_pci_free_coherent,
9675 .map_page = niu_pci_map_page,
9676 .unmap_page = niu_pci_unmap_page,
9677 .map_single = niu_pci_map_single,
9678 .unmap_single = niu_pci_unmap_single,
9679};
9680
9681static void __devinit niu_driver_version(void)
9682{
9683 static int niu_version_printed;
9684
9685 if (niu_version_printed++ == 0)
9686 pr_info("%s", version);
9687}
9688
9689static struct net_device * __devinit niu_alloc_and_init(
9690 struct device *gen_dev, struct pci_dev *pdev,
2dc11581 9691 struct platform_device *op, const struct niu_ops *ops,
a3138df9
DM		 9692 u8 port)
9693{
b4c21639 9694 struct net_device *dev;
a3138df9
DM		 9695 struct niu *np;
9696
b4c21639 9697 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
a3138df9 9698 if (!dev) {
f10a1f2e 9699 dev_err(gen_dev, "Etherdev alloc failed, aborting\n");
a3138df9
DM		 9700 return NULL;
9701 }
9702
9703 SET_NETDEV_DEV(dev, gen_dev);
9704
9705 np = netdev_priv(dev);
9706 np->dev = dev;
9707 np->pdev = pdev;
9708 np->op = op;
9709 np->device = gen_dev;
9710 np->ops = ops;
9711
9712 np->msg_enable = niu_debug;
9713
9714 spin_lock_init(&np->lock);
9715 INIT_WORK(&np->reset_task, niu_reset_task);
9716
9717 np->port = port;
9718
9719 return dev;
9720}
9721
2c9171d4
SH		 9722static const struct net_device_ops niu_netdev_ops = {
9723 .ndo_open = niu_open,
9724 .ndo_stop = niu_close,
00829823 9725 .ndo_start_xmit = niu_start_xmit,
2c9171d4
SH		 9726 .ndo_get_stats = niu_get_stats,
9727 .ndo_set_multicast_list = niu_set_rx_mode,
9728 .ndo_validate_addr = eth_validate_addr,
9729 .ndo_set_mac_address = niu_set_mac_addr,
9730 .ndo_do_ioctl = niu_ioctl,
9731 .ndo_tx_timeout = niu_tx_timeout,
9732 .ndo_change_mtu = niu_change_mtu,
9733};
9734
a3138df9
DM		 9735static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9736{
2c9171d4 9737 dev->netdev_ops = &niu_netdev_ops;
a3138df9
DM		 9738 dev->ethtool_ops = &niu_ethtool_ops;
9739 dev->watchdog_timeo = NIU_TX_TIMEOUT;
a3138df9
DM		 9740}
9741
9742static void __devinit niu_device_announce(struct niu *np)
9743{
9744 struct net_device *dev = np->dev;
a3138df9 9745
e174961c 9746 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
a3138df9 9747
5fbd7e24
MW		 9748 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9749 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9750 dev->name,
9751 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9752 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9753 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9754 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9755 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9756 np->vpd.phy_type);
9757 } else {
9758 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9759 dev->name,
9760 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9761 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
e3e081e1
SB		 9762 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9763 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9764 "COPPER")),
5fbd7e24
MW		 9765 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9766 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9767 np->vpd.phy_type);
9768 }
a3138df9
DM		 9769}
9770
3cfa856d
DM		 9771static void __devinit niu_set_basic_features(struct net_device *dev)
9772{
9773 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM |
9774 NETIF_F_GRO | NETIF_F_RXHASH);
9775}
9776
a3138df9
DM		 9777static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9778 const struct pci_device_id *ent)
9779{
a3138df9
DM		 9780 union niu_parent_id parent_id;
9781 struct net_device *dev;
9782 struct niu *np;
9783 int err, pos;
9784 u64 dma_mask;
9785 u16 val16;
9786
9787 niu_driver_version();
9788
9789 err = pci_enable_device(pdev);
9790 if (err) {
f10a1f2e 9791 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
a3138df9
DM		 9792 return err;
9793 }
9794
9795 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9796 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
f10a1f2e 9797 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
a3138df9
DM		 9798 err = -ENODEV;
9799 goto err_out_disable_pdev;
9800 }
9801
9802 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9803 if (err) {
f10a1f2e 9804 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
a3138df9
DM		 9805 goto err_out_disable_pdev;
9806 }
9807
9808 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9809 if (pos <= 0) {
f10a1f2e 9810 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
a3138df9
DM		 9811 goto err_out_free_res;
9812 }
9813
9814 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9815 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9816 if (!dev) {
9817 err = -ENOMEM;
9818 goto err_out_free_res;
9819 }
9820 np = netdev_priv(dev);
9821
9822 memset(&parent_id, 0, sizeof(parent_id));
9823 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9824 parent_id.pci.bus = pdev->bus->number;
9825 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9826
9827 np->parent = niu_get_parent(np, &parent_id,
9828 PLAT_TYPE_ATLAS);
9829 if (!np->parent) {
9830 err = -ENOMEM;
9831 goto err_out_free_dev;
9832 }
9833
9834 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9835 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9836 val16 |= (PCI_EXP_DEVCTL_CERE |
9837 PCI_EXP_DEVCTL_NFERE |
9838 PCI_EXP_DEVCTL_FERE |
9839 PCI_EXP_DEVCTL_URRE |
9840 PCI_EXP_DEVCTL_RELAX_EN);
9841 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9842
8cbd9623 9843 dma_mask = DMA_BIT_MASK(44);
a3138df9
DM		 9844 err = pci_set_dma_mask(pdev, dma_mask);
9845 if (!err) {
9846 dev->features |= NETIF_F_HIGHDMA;
9847 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9848 if (err) {
f10a1f2e 9849 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
a3138df9
DM		 9850 goto err_out_release_parent;
9851 }
9852 }
284901a9
YH		 9853 if (err || dma_mask == DMA_BIT_MASK(32)) {
9854 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
a3138df9 9855 if (err) {
f10a1f2e 9856 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
a3138df9
DM		 9857 goto err_out_release_parent;
9858 }
9859 }
9860
3cfa856d 9861 niu_set_basic_features(dev);
a3138df9 9862
19ecb6ba 9863 np->regs = pci_ioremap_bar(pdev, 0);
a3138df9 9864 if (!np->regs) {
f10a1f2e 9865 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
a3138df9
DM		 9866 err = -ENOMEM;
9867 goto err_out_release_parent;
9868 }
9869
9870 pci_set_master(pdev);
9871 pci_save_state(pdev);
9872
9873 dev->irq = pdev->irq;
9874
9875 niu_assign_netdev_ops(dev);
9876
9877 err = niu_get_invariants(np);
9878 if (err) {
9879 if (err != -ENODEV)
f10a1f2e 9880 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
a3138df9
DM		 9881 goto err_out_iounmap;
9882 }
9883
9884 err = register_netdev(dev);
9885 if (err) {
f10a1f2e 9886 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
a3138df9
DM		 9887 goto err_out_iounmap;
9888 }
9889
9890 pci_set_drvdata(pdev, dev);
9891
9892 niu_device_announce(np);
9893
9894 return 0;
9895
9896err_out_iounmap:
9897 if (np->regs) {
9898 iounmap(np->regs);
9899 np->regs = NULL;
9900 }
9901
9902err_out_release_parent:
9903 niu_put_parent(np);
9904
9905err_out_free_dev:
9906 free_netdev(dev);
9907
9908err_out_free_res:
9909 pci_release_regions(pdev);
9910
9911err_out_disable_pdev:
9912 pci_disable_device(pdev);
9913 pci_set_drvdata(pdev, NULL);
9914
9915 return err;
9916}
9917
9918static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9919{
9920 struct net_device *dev = pci_get_drvdata(pdev);
9921
9922 if (dev) {
9923 struct niu *np = netdev_priv(dev);
9924
9925 unregister_netdev(dev);
9926 if (np->regs) {
9927 iounmap(np->regs);
9928 np->regs = NULL;
9929 }
9930
9931 niu_ldg_free(np);
9932
9933 niu_put_parent(np);
9934
9935 free_netdev(dev);
9936 pci_release_regions(pdev);
9937 pci_disable_device(pdev);
9938 pci_set_drvdata(pdev, NULL);
9939 }
9940}
9941
9942static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9943{
9944 struct net_device *dev = pci_get_drvdata(pdev);
9945 struct niu *np = netdev_priv(dev);
9946 unsigned long flags;
9947
9948 if (!netif_running(dev))
9949 return 0;
9950
9951 flush_scheduled_work();
9952 niu_netif_stop(np);
9953
9954 del_timer_sync(&np->timer);
9955
9956 spin_lock_irqsave(&np->lock, flags);
9957 niu_enable_interrupts(np, 0);
9958 spin_unlock_irqrestore(&np->lock, flags);
9959
9960 netif_device_detach(dev);
9961
9962 spin_lock_irqsave(&np->lock, flags);
9963 niu_stop_hw(np);
9964 spin_unlock_irqrestore(&np->lock, flags);
9965
9966 pci_save_state(pdev);
9967
9968 return 0;
9969}
9970
9971static int niu_resume(struct pci_dev *pdev)
9972{
9973 struct net_device *dev = pci_get_drvdata(pdev);
9974 struct niu *np = netdev_priv(dev);
9975 unsigned long flags;
9976 int err;
9977
9978 if (!netif_running(dev))
9979 return 0;
9980
9981 pci_restore_state(pdev);
9982
9983 netif_device_attach(dev);
9984
9985 spin_lock_irqsave(&np->lock, flags);
9986
9987 err = niu_init_hw(np);
9988 if (!err) {
9989 np->timer.expires = jiffies + HZ;
9990 add_timer(&np->timer);
9991 niu_netif_start(np);
9992 }
9993
9994 spin_unlock_irqrestore(&np->lock, flags);
9995
9996 return err;
9997}
9998
9999static struct pci_driver niu_pci_driver = {
10000 .name = DRV_MODULE_NAME,
10001 .id_table = niu_pci_tbl,
10002 .probe = niu_pci_init_one,
10003 .remove = __devexit_p(niu_pci_remove_one),
10004 .suspend = niu_suspend,
10005 .resume = niu_resume,
10006};
10007
10008#ifdef CONFIG_SPARC64
10009static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
10010 u64 *dma_addr, gfp_t flag)
10011{
10012 unsigned long order = get_order(size);
10013 unsigned long page = __get_free_pages(flag, order);
10014
10015 if (page == 0UL)
10016 return NULL;
10017 memset((char *)page, 0, PAGE_SIZE << order);
10018 *dma_addr = __pa(page);
10019
10020 return (void *) page;
10021}
10022
10023static void niu_phys_free_coherent(struct device *dev, size_t size,
10024 void *cpu_addr, u64 handle)
10025{
10026 unsigned long order = get_order(size);
10027
10028 free_pages((unsigned long) cpu_addr, order);
10029}
10030
10031static u64 niu_phys_map_page(struct device *dev, struct page *page,
10032 unsigned long offset, size_t size,
10033 enum dma_data_direction direction)
10034{
10035 return page_to_phys(page) + offset;
10036}
10037
10038static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10039 size_t size, enum dma_data_direction direction)
10040{
10041 /* Nothing to do. */
10042}
10043
10044static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10045 size_t size,
10046 enum dma_data_direction direction)
10047{
10048 return __pa(cpu_addr);
10049}
10050
10051static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10052 size_t size,
10053 enum dma_data_direction direction)
10054{
10055 /* Nothing to do. */
10056}
10057
10058static const struct niu_ops niu_phys_ops = {
10059 .alloc_coherent = niu_phys_alloc_coherent,
10060 .free_coherent = niu_phys_free_coherent,
10061 .map_page = niu_phys_map_page,
10062 .unmap_page = niu_phys_unmap_page,
10063 .map_single = niu_phys_map_single,
10064 .unmap_single = niu_phys_unmap_single,
10065};
10066
2dc11581 10067static int __devinit niu_of_probe(struct platform_device *op,
a3138df9
DM		 10068 const struct of_device_id *match)
10069{
10070 union niu_parent_id parent_id;
10071 struct net_device *dev;
10072 struct niu *np;
10073 const u32 *reg;
10074 int err;
10075
10076 niu_driver_version();
10077
61c7a080 10078 reg = of_get_property(op->dev.of_node, "reg", NULL);
a3138df9 10079 if (!reg) {
f10a1f2e 10080 dev_err(&op->dev, "%s: No 'reg' property, aborting\n",
61c7a080 10081 op->dev.of_node->full_name);
a3138df9
DM		 10082 return -ENODEV;
10083 }
10084
10085 dev = niu_alloc_and_init(&op->dev, NULL, op,
10086 &niu_phys_ops, reg[0] & 0x1);
10087 if (!dev) {
10088 err = -ENOMEM;
10089 goto err_out;
10090 }
10091 np = netdev_priv(dev);
10092
10093 memset(&parent_id, 0, sizeof(parent_id));
61c7a080 10094 parent_id.of = of_get_parent(op->dev.of_node);
a3138df9
DM		 10095
10096 np->parent = niu_get_parent(np, &parent_id,
10097 PLAT_TYPE_NIU);
10098 if (!np->parent) {
10099 err = -ENOMEM;
10100 goto err_out_free_dev;
10101 }
10102
3cfa856d 10103 niu_set_basic_features(dev);
a3138df9
DM		 10104
10105 np->regs = of_ioremap(&op->resource[1], 0,
6f0e0135 10106 resource_size(&op->resource[1]),
a3138df9
DM		 10107 "niu regs");
10108 if (!np->regs) {
f10a1f2e 10109 dev_err(&op->dev, "Cannot map device registers, aborting\n");
a3138df9
DM		 10110 err = -ENOMEM;
10111 goto err_out_release_parent;
10112 }
10113
10114 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
6f0e0135 10115 resource_size(&op->resource[2]),
a3138df9
DM		 10116 "niu vregs-1");
10117 if (!np->vir_regs_1) {
f10a1f2e 10118 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
a3138df9
DM		 10119 err = -ENOMEM;
10120 goto err_out_iounmap;
10121 }
10122
10123 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
6f0e0135 10124 resource_size(&op->resource[3]),
a3138df9
DM		 10125 "niu vregs-2");
10126 if (!np->vir_regs_2) {
f10a1f2e 10127 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
a3138df9
DM		 10128 err = -ENOMEM;
10129 goto err_out_iounmap;
10130 }
10131
10132 niu_assign_netdev_ops(dev);
10133
10134 err = niu_get_invariants(np);
10135 if (err) {
10136 if (err != -ENODEV)
f10a1f2e 10137 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
a3138df9
DM		 10138 goto err_out_iounmap;
10139 }
10140
10141 err = register_netdev(dev);
10142 if (err) {
f10a1f2e 10143 dev_err(&op->dev, "Cannot register net device, aborting\n");
a3138df9
DM		 10144 goto err_out_iounmap;
10145 }
10146
10147 dev_set_drvdata(&op->dev, dev);
10148
10149 niu_device_announce(np);
10150
10151 return 0;
10152
10153err_out_iounmap:
10154 if (np->vir_regs_1) {
10155 of_iounmap(&op->resource[2], np->vir_regs_1,
6f0e0135 10156 resource_size(&op->resource[2]));
a3138df9
DM		 10157 np->vir_regs_1 = NULL;
10158 }
10159
10160 if (np->vir_regs_2) {
10161 of_iounmap(&op->resource[3], np->vir_regs_2,
6f0e0135 10162 resource_size(&op->resource[3]));
a3138df9
DM		 10163 np->vir_regs_2 = NULL;
10164 }
10165
10166 if (np->regs) {
10167 of_iounmap(&op->resource[1], np->regs,
6f0e0135 10168 resource_size(&op->resource[1]));
a3138df9
DM		 10169 np->regs = NULL;
10170 }
10171
10172err_out_release_parent:
10173 niu_put_parent(np);
10174
10175err_out_free_dev:
10176 free_netdev(dev);
10177
10178err_out:
10179 return err;
10180}
10181
2dc11581 10182static int __devexit niu_of_remove(struct platform_device *op)
a3138df9
DM		 10183{
10184 struct net_device *dev = dev_get_drvdata(&op->dev);
10185
10186 if (dev) {
10187 struct niu *np = netdev_priv(dev);
10188
10189 unregister_netdev(dev);
10190
10191 if (np->vir_regs_1) {
10192 of_iounmap(&op->resource[2], np->vir_regs_1,
6f0e0135 10193 resource_size(&op->resource[2]));
a3138df9
DM		 10194 np->vir_regs_1 = NULL;
10195 }
10196
10197 if (np->vir_regs_2) {
10198 of_iounmap(&op->resource[3], np->vir_regs_2,
6f0e0135 10199 resource_size(&op->resource[3]));
a3138df9
DM		 10200 np->vir_regs_2 = NULL;
10201 }
10202
10203 if (np->regs) {
10204 of_iounmap(&op->resource[1], np->regs,
6f0e0135 10205 resource_size(&op->resource[1]));
a3138df9
DM		 10206 np->regs = NULL;
10207 }
10208
10209 niu_ldg_free(np);
10210
10211 niu_put_parent(np);
10212
10213 free_netdev(dev);
10214 dev_set_drvdata(&op->dev, NULL);
10215 }
10216 return 0;
10217}
10218
fd098316 10219static const struct of_device_id niu_match[] = {
a3138df9
DM		 10220 {
10221 .name = "network",
10222 .compatible = "SUNW,niusl",
10223 },
10224 {},
10225};
10226MODULE_DEVICE_TABLE(of, niu_match);
10227
10228static struct of_platform_driver niu_of_driver = {
4018294b
GL		 10229 .driver = {
10230 .name = "niu",
10231 .owner = THIS_MODULE,
10232 .of_match_table = niu_match,
10233 },
a3138df9
DM		 10234 .probe = niu_of_probe,
10235 .remove = __devexit_p(niu_of_remove),
10236};
10237
10238#endif /* CONFIG_SPARC64 */
10239
10240static int __init niu_init(void)
10241{
10242 int err = 0;
10243
81429973 10244 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
a3138df9
DM		 10245
10246 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10247
10248#ifdef CONFIG_SPARC64
1ab1d63a 10249 err = of_register_platform_driver(&niu_of_driver);
a3138df9
DM		 10250#endif
10251
10252 if (!err) {
10253 err = pci_register_driver(&niu_pci_driver);
10254#ifdef CONFIG_SPARC64
10255 if (err)
1ab1d63a 10256 of_unregister_platform_driver(&niu_of_driver);
a3138df9
DM		 10257#endif
10258 }
10259
10260 return err;
10261}
10262
10263static void __exit niu_exit(void)
10264{
10265 pci_unregister_driver(&niu_pci_driver);
10266#ifdef CONFIG_SPARC64
1ab1d63a 10267 of_unregister_platform_driver(&niu_of_driver);
a3138df9
DM		 10268#endif
10269}
10270
10271module_init(niu_init);
10272module_exit(niu_exit);
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