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dma-mapping: replace all DMA_39BIT_MASK macro with DMA_BIT_MASK(39)
[net-next-2.6.git] / drivers / net / niu.c
CommitLineData
a3138df9
DM		 1/* niu.c: Neptune ethernet driver.
2 *
be0c007a 3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
a3138df9
DM		 4 */
5
6#include <linux/module.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/dma-mapping.h>
10#include <linux/netdevice.h>
11#include <linux/ethtool.h>
12#include <linux/etherdevice.h>
13#include <linux/platform_device.h>
14#include <linux/delay.h>
15#include <linux/bitops.h>
16#include <linux/mii.h>
17#include <linux/if_ether.h>
18#include <linux/if_vlan.h>
19#include <linux/ip.h>
20#include <linux/in.h>
21#include <linux/ipv6.h>
22#include <linux/log2.h>
23#include <linux/jiffies.h>
24#include <linux/crc32.h>
25
26#include <linux/io.h>
27
28#ifdef CONFIG_SPARC64
29#include <linux/of_device.h>
30#endif
31
32#include "niu.h"
33
34#define DRV_MODULE_NAME "niu"
35#define PFX DRV_MODULE_NAME ": "
d8c3e23d
DM		 36#define DRV_MODULE_VERSION "1.0"
37#define DRV_MODULE_RELDATE "Nov 14, 2008"
a3138df9
DM		 38
39static char version[] __devinitdata =
40 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
41
42MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43MODULE_DESCRIPTION("NIU ethernet driver");
44MODULE_LICENSE("GPL");
45MODULE_VERSION(DRV_MODULE_VERSION);
46
47#ifndef DMA_44BIT_MASK
48#define DMA_44BIT_MASK 0x00000fffffffffffULL
49#endif
50
51#ifndef readq
52static u64 readq(void __iomem *reg)
53{
e23a59e1 54 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
a3138df9
DM		 55}
56
57static void writeq(u64 val, void __iomem *reg)
58{
59 writel(val & 0xffffffff, reg);
60 writel(val >> 32, reg + 0x4UL);
61}
62#endif
63
64static struct pci_device_id niu_pci_tbl[] = {
65 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
66 {}
67};
68
69MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
70
71#define NIU_TX_TIMEOUT (5 * HZ)
72
73#define nr64(reg) readq(np->regs + (reg))
74#define nw64(reg, val) writeq((val), np->regs + (reg))
75
76#define nr64_mac(reg) readq(np->mac_regs + (reg))
77#define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
78
79#define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
80#define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
81
82#define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
83#define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
84
85#define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
86#define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
87
88#define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
89
90static int niu_debug;
91static int debug = -1;
92module_param(debug, int, 0);
93MODULE_PARM_DESC(debug, "NIU debug level");
94
95#define niudbg(TYPE, f, a...) \
96do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
97 printk(KERN_DEBUG PFX f, ## a); \
98} while (0)
99
100#define niuinfo(TYPE, f, a...) \
101do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
102 printk(KERN_INFO PFX f, ## a); \
103} while (0)
104
105#define niuwarn(TYPE, f, a...) \
106do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
107 printk(KERN_WARNING PFX f, ## a); \
108} while (0)
109
110#define niu_lock_parent(np, flags) \
111 spin_lock_irqsave(&np->parent->lock, flags)
112#define niu_unlock_parent(np, flags) \
113 spin_unlock_irqrestore(&np->parent->lock, flags)
114
5fbd7e24
MW		 115static int serdes_init_10g_serdes(struct niu *np);
116
a3138df9
DM		 117static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
118 u64 bits, int limit, int delay)
119{
120 while (--limit >= 0) {
121 u64 val = nr64_mac(reg);
122
123 if (!(val & bits))
124 break;
125 udelay(delay);
126 }
127 if (limit < 0)
128 return -ENODEV;
129 return 0;
130}
131
132static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
133 u64 bits, int limit, int delay,
134 const char *reg_name)
135{
136 int err;
137
138 nw64_mac(reg, bits);
139 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
140 if (err)
141 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
142 "would not clear, val[%llx]\n",
143 np->dev->name, (unsigned long long) bits, reg_name,
144 (unsigned long long) nr64_mac(reg));
145 return err;
146}
147
148#define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
149({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
150 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
151})
152
153static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
154 u64 bits, int limit, int delay)
155{
156 while (--limit >= 0) {
157 u64 val = nr64_ipp(reg);
158
159 if (!(val & bits))
160 break;
161 udelay(delay);
162 }
163 if (limit < 0)
164 return -ENODEV;
165 return 0;
166}
167
168static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
169 u64 bits, int limit, int delay,
170 const char *reg_name)
171{
172 int err;
173 u64 val;
174
175 val = nr64_ipp(reg);
176 val |= bits;
177 nw64_ipp(reg, val);
178
179 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
180 if (err)
181 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
182 "would not clear, val[%llx]\n",
183 np->dev->name, (unsigned long long) bits, reg_name,
184 (unsigned long long) nr64_ipp(reg));
185 return err;
186}
187
188#define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
189({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
190 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
191})
192
193static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
194 u64 bits, int limit, int delay)
195{
196 while (--limit >= 0) {
197 u64 val = nr64(reg);
198
199 if (!(val & bits))
200 break;
201 udelay(delay);
202 }
203 if (limit < 0)
204 return -ENODEV;
205 return 0;
206}
207
208#define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
209({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
210 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
211})
212
213static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
214 u64 bits, int limit, int delay,
215 const char *reg_name)
216{
217 int err;
218
219 nw64(reg, bits);
220 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
221 if (err)
222 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
223 "would not clear, val[%llx]\n",
224 np->dev->name, (unsigned long long) bits, reg_name,
225 (unsigned long long) nr64(reg));
226 return err;
227}
228
229#define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
230({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
231 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
232})
233
234static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
235{
236 u64 val = (u64) lp->timer;
237
238 if (on)
239 val |= LDG_IMGMT_ARM;
240
241 nw64(LDG_IMGMT(lp->ldg_num), val);
242}
243
244static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
245{
246 unsigned long mask_reg, bits;
247 u64 val;
248
249 if (ldn < 0 || ldn > LDN_MAX)
250 return -EINVAL;
251
252 if (ldn < 64) {
253 mask_reg = LD_IM0(ldn);
254 bits = LD_IM0_MASK;
255 } else {
256 mask_reg = LD_IM1(ldn - 64);
257 bits = LD_IM1_MASK;
258 }
259
260 val = nr64(mask_reg);
261 if (on)
262 val &= ~bits;
263 else
264 val |= bits;
265 nw64(mask_reg, val);
266
267 return 0;
268}
269
270static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
271{
272 struct niu_parent *parent = np->parent;
273 int i;
274
275 for (i = 0; i <= LDN_MAX; i++) {
276 int err;
277
278 if (parent->ldg_map[i] != lp->ldg_num)
279 continue;
280
281 err = niu_ldn_irq_enable(np, i, on);
282 if (err)
283 return err;
284 }
285 return 0;
286}
287
288static int niu_enable_interrupts(struct niu *np, int on)
289{
290 int i;
291
292 for (i = 0; i < np->num_ldg; i++) {
293 struct niu_ldg *lp = &np->ldg[i];
294 int err;
295
296 err = niu_enable_ldn_in_ldg(np, lp, on);
297 if (err)
298 return err;
299 }
300 for (i = 0; i < np->num_ldg; i++)
301 niu_ldg_rearm(np, &np->ldg[i], on);
302
303 return 0;
304}
305
306static u32 phy_encode(u32 type, int port)
307{
308 return (type << (port * 2));
309}
310
311static u32 phy_decode(u32 val, int port)
312{
313 return (val >> (port * 2)) & PORT_TYPE_MASK;
314}
315
316static int mdio_wait(struct niu *np)
317{
318 int limit = 1000;
319 u64 val;
320
321 while (--limit > 0) {
322 val = nr64(MIF_FRAME_OUTPUT);
323 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
324 return val & MIF_FRAME_OUTPUT_DATA;
325
326 udelay(10);
327 }
328
329 return -ENODEV;
330}
331
332static int mdio_read(struct niu *np, int port, int dev, int reg)
333{
334 int err;
335
336 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
337 err = mdio_wait(np);
338 if (err < 0)
339 return err;
340
341 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
342 return mdio_wait(np);
343}
344
345static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
346{
347 int err;
348
349 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
350 err = mdio_wait(np);
351 if (err < 0)
352 return err;
353
354 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
355 err = mdio_wait(np);
356 if (err < 0)
357 return err;
358
359 return 0;
360}
361
362static int mii_read(struct niu *np, int port, int reg)
363{
364 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
365 return mdio_wait(np);
366}
367
368static int mii_write(struct niu *np, int port, int reg, int data)
369{
370 int err;
371
372 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
373 err = mdio_wait(np);
374 if (err < 0)
375 return err;
376
377 return 0;
378}
379
380static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
381{
382 int err;
383
384 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
385 ESR2_TI_PLL_TX_CFG_L(channel),
386 val & 0xffff);
387 if (!err)
388 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
389 ESR2_TI_PLL_TX_CFG_H(channel),
390 val >> 16);
391 return err;
392}
393
394static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
395{
396 int err;
397
398 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
399 ESR2_TI_PLL_RX_CFG_L(channel),
400 val & 0xffff);
401 if (!err)
402 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
403 ESR2_TI_PLL_RX_CFG_H(channel),
404 val >> 16);
405 return err;
406}
407
408/* Mode is always 10G fiber. */
e3e081e1 409static int serdes_init_niu_10g_fiber(struct niu *np)
a3138df9
DM		 410{
411 struct niu_link_config *lp = &np->link_config;
412 u32 tx_cfg, rx_cfg;
413 unsigned long i;
414
415 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
416 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
417 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
418 PLL_RX_CFG_EQ_LP_ADAPTIVE);
419
420 if (lp->loopback_mode == LOOPBACK_PHY) {
421 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
422
423 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
424 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
425
426 tx_cfg |= PLL_TX_CFG_ENTEST;
427 rx_cfg |= PLL_RX_CFG_ENTEST;
428 }
429
430 /* Initialize all 4 lanes of the SERDES. */
431 for (i = 0; i < 4; i++) {
432 int err = esr2_set_tx_cfg(np, i, tx_cfg);
433 if (err)
434 return err;
435 }
436
437 for (i = 0; i < 4; i++) {
438 int err = esr2_set_rx_cfg(np, i, rx_cfg);
439 if (err)
440 return err;
441 }
442
443 return 0;
444}
445
e3e081e1
SB		 446static int serdes_init_niu_1g_serdes(struct niu *np)
447{
448 struct niu_link_config *lp = &np->link_config;
449 u16 pll_cfg, pll_sts;
450 int max_retry = 100;
51e0f058 451 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 452 u32 tx_cfg, rx_cfg;
453 unsigned long i;
454 int err;
455
456 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
457 PLL_TX_CFG_RATE_HALF);
458 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
459 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
460 PLL_RX_CFG_RATE_HALF);
461
462 if (np->port == 0)
463 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
464
465 if (lp->loopback_mode == LOOPBACK_PHY) {
466 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
467
468 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
469 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
470
471 tx_cfg |= PLL_TX_CFG_ENTEST;
472 rx_cfg |= PLL_RX_CFG_ENTEST;
473 }
474
475 /* Initialize PLL for 1G */
476 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
477
478 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
479 ESR2_TI_PLL_CFG_L, pll_cfg);
480 if (err) {
481 dev_err(np->device, PFX "NIU Port %d "
482 "serdes_init_niu_1g_serdes: "
483 "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
484 return err;
485 }
486
487 pll_sts = PLL_CFG_ENPLL;
488
489 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
490 ESR2_TI_PLL_STS_L, pll_sts);
491 if (err) {
492 dev_err(np->device, PFX "NIU Port %d "
493 "serdes_init_niu_1g_serdes: "
494 "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
495 return err;
496 }
497
498 udelay(200);
499
500 /* Initialize all 4 lanes of the SERDES. */
501 for (i = 0; i < 4; i++) {
502 err = esr2_set_tx_cfg(np, i, tx_cfg);
503 if (err)
504 return err;
505 }
506
507 for (i = 0; i < 4; i++) {
508 err = esr2_set_rx_cfg(np, i, rx_cfg);
509 if (err)
510 return err;
511 }
512
513 switch (np->port) {
514 case 0:
515 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
516 mask = val;
517 break;
518
519 case 1:
520 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
521 mask = val;
522 break;
523
524 default:
525 return -EINVAL;
526 }
527
528 while (max_retry--) {
529 sig = nr64(ESR_INT_SIGNALS);
530 if ((sig & mask) == val)
531 break;
532
533 mdelay(500);
534 }
535
536 if ((sig & mask) != val) {
537 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
538 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
539 return -ENODEV;
540 }
541
542 return 0;
543}
544
545static int serdes_init_niu_10g_serdes(struct niu *np)
546{
547 struct niu_link_config *lp = &np->link_config;
548 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
549 int max_retry = 100;
51e0f058 550 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 551 unsigned long i;
552 int err;
553
554 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
555 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
556 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
557 PLL_RX_CFG_EQ_LP_ADAPTIVE);
558
559 if (lp->loopback_mode == LOOPBACK_PHY) {
560 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
561
562 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
563 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
564
565 tx_cfg |= PLL_TX_CFG_ENTEST;
566 rx_cfg |= PLL_RX_CFG_ENTEST;
567 }
568
569 /* Initialize PLL for 10G */
570 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
571
572 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
573 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
574 if (err) {
575 dev_err(np->device, PFX "NIU Port %d "
576 "serdes_init_niu_10g_serdes: "
577 "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
578 return err;
579 }
580
581 pll_sts = PLL_CFG_ENPLL;
582
583 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
584 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
585 if (err) {
586 dev_err(np->device, PFX "NIU Port %d "
587 "serdes_init_niu_10g_serdes: "
588 "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
589 return err;
590 }
591
592 udelay(200);
593
594 /* Initialize all 4 lanes of the SERDES. */
595 for (i = 0; i < 4; i++) {
596 err = esr2_set_tx_cfg(np, i, tx_cfg);
597 if (err)
598 return err;
599 }
600
601 for (i = 0; i < 4; i++) {
602 err = esr2_set_rx_cfg(np, i, rx_cfg);
603 if (err)
604 return err;
605 }
606
607 /* check if serdes is ready */
608
609 switch (np->port) {
610 case 0:
611 mask = ESR_INT_SIGNALS_P0_BITS;
612 val = (ESR_INT_SRDY0_P0 |
613 ESR_INT_DET0_P0 |
614 ESR_INT_XSRDY_P0 |
615 ESR_INT_XDP_P0_CH3 |
616 ESR_INT_XDP_P0_CH2 |
617 ESR_INT_XDP_P0_CH1 |
618 ESR_INT_XDP_P0_CH0);
619 break;
620
621 case 1:
622 mask = ESR_INT_SIGNALS_P1_BITS;
623 val = (ESR_INT_SRDY0_P1 |
624 ESR_INT_DET0_P1 |
625 ESR_INT_XSRDY_P1 |
626 ESR_INT_XDP_P1_CH3 |
627 ESR_INT_XDP_P1_CH2 |
628 ESR_INT_XDP_P1_CH1 |
629 ESR_INT_XDP_P1_CH0);
630 break;
631
632 default:
633 return -EINVAL;
634 }
635
636 while (max_retry--) {
637 sig = nr64(ESR_INT_SIGNALS);
638 if ((sig & mask) == val)
639 break;
640
641 mdelay(500);
642 }
643
644 if ((sig & mask) != val) {
645 pr_info(PFX "NIU Port %u signal bits [%08x] are not "
646 "[%08x] for 10G...trying 1G\n",
647 np->port, (int) (sig & mask), (int) val);
648
649 /* 10G failed, try initializing at 1G */
650 err = serdes_init_niu_1g_serdes(np);
651 if (!err) {
652 np->flags &= ~NIU_FLAGS_10G;
653 np->mac_xcvr = MAC_XCVR_PCS;
654 } else {
655 dev_err(np->device, PFX "Port %u 10G/1G SERDES "
656 "Link Failed \n", np->port);
657 return -ENODEV;
658 }
659 }
660 return 0;
661}
662
a3138df9
DM		 663static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
664{
665 int err;
666
667 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
668 if (err >= 0) {
669 *val = (err & 0xffff);
670 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
671 ESR_RXTX_CTRL_H(chan));
672 if (err >= 0)
673 *val |= ((err & 0xffff) << 16);
674 err = 0;
675 }
676 return err;
677}
678
679static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
680{
681 int err;
682
683 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
684 ESR_GLUE_CTRL0_L(chan));
685 if (err >= 0) {
686 *val = (err & 0xffff);
687 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
688 ESR_GLUE_CTRL0_H(chan));
689 if (err >= 0) {
690 *val |= ((err & 0xffff) << 16);
691 err = 0;
692 }
693 }
694 return err;
695}
696
697static int esr_read_reset(struct niu *np, u32 *val)
698{
699 int err;
700
701 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
702 ESR_RXTX_RESET_CTRL_L);
703 if (err >= 0) {
704 *val = (err & 0xffff);
705 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
706 ESR_RXTX_RESET_CTRL_H);
707 if (err >= 0) {
708 *val |= ((err & 0xffff) << 16);
709 err = 0;
710 }
711 }
712 return err;
713}
714
715static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
716{
717 int err;
718
719 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
720 ESR_RXTX_CTRL_L(chan), val & 0xffff);
721 if (!err)
722 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
723 ESR_RXTX_CTRL_H(chan), (val >> 16));
724 return err;
725}
726
727static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
728{
729 int err;
730
731 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
732 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
733 if (!err)
734 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
735 ESR_GLUE_CTRL0_H(chan), (val >> 16));
736 return err;
737}
738
739static int esr_reset(struct niu *np)
740{
f166400b 741 u32 uninitialized_var(reset);
a3138df9
DM		 742 int err;
743
744 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
745 ESR_RXTX_RESET_CTRL_L, 0x0000);
746 if (err)
747 return err;
748 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
749 ESR_RXTX_RESET_CTRL_H, 0xffff);
750 if (err)
751 return err;
752 udelay(200);
753
754 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
755 ESR_RXTX_RESET_CTRL_L, 0xffff);
756 if (err)
757 return err;
758 udelay(200);
759
760 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
761 ESR_RXTX_RESET_CTRL_H, 0x0000);
762 if (err)
763 return err;
764 udelay(200);
765
766 err = esr_read_reset(np, &reset);
767 if (err)
768 return err;
769 if (reset != 0) {
770 dev_err(np->device, PFX "Port %u ESR_RESET "
771 "did not clear [%08x]\n",
772 np->port, reset);
773 return -ENODEV;
774 }
775
776 return 0;
777}
778
779static int serdes_init_10g(struct niu *np)
780{
781 struct niu_link_config *lp = &np->link_config;
782 unsigned long ctrl_reg, test_cfg_reg, i;
783 u64 ctrl_val, test_cfg_val, sig, mask, val;
784 int err;
785
786 switch (np->port) {
787 case 0:
788 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
789 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
790 break;
791 case 1:
792 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
793 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
794 break;
795
796 default:
797 return -EINVAL;
798 }
799 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
800 ENET_SERDES_CTRL_SDET_1 |
801 ENET_SERDES_CTRL_SDET_2 |
802 ENET_SERDES_CTRL_SDET_3 |
803 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
804 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
805 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
806 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
807 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
808 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
809 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
810 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
811 test_cfg_val = 0;
812
813 if (lp->loopback_mode == LOOPBACK_PHY) {
814 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
815 ENET_SERDES_TEST_MD_0_SHIFT) |
816 (ENET_TEST_MD_PAD_LOOPBACK <<
817 ENET_SERDES_TEST_MD_1_SHIFT) |
818 (ENET_TEST_MD_PAD_LOOPBACK <<
819 ENET_SERDES_TEST_MD_2_SHIFT) |
820 (ENET_TEST_MD_PAD_LOOPBACK <<
821 ENET_SERDES_TEST_MD_3_SHIFT));
822 }
823
824 nw64(ctrl_reg, ctrl_val);
825 nw64(test_cfg_reg, test_cfg_val);
826
827 /* Initialize all 4 lanes of the SERDES. */
828 for (i = 0; i < 4; i++) {
829 u32 rxtx_ctrl, glue0;
830
831 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
832 if (err)
833 return err;
834 err = esr_read_glue0(np, i, &glue0);
835 if (err)
836 return err;
837
838 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
839 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
840 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
841
842 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
843 ESR_GLUE_CTRL0_THCNT |
844 ESR_GLUE_CTRL0_BLTIME);
845 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
846 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
847 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
848 (BLTIME_300_CYCLES <<
849 ESR_GLUE_CTRL0_BLTIME_SHIFT));
850
851 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
852 if (err)
853 return err;
854 err = esr_write_glue0(np, i, glue0);
855 if (err)
856 return err;
857 }
858
859 err = esr_reset(np);
860 if (err)
861 return err;
862
863 sig = nr64(ESR_INT_SIGNALS);
864 switch (np->port) {
865 case 0:
866 mask = ESR_INT_SIGNALS_P0_BITS;
867 val = (ESR_INT_SRDY0_P0 |
868 ESR_INT_DET0_P0 |
869 ESR_INT_XSRDY_P0 |
870 ESR_INT_XDP_P0_CH3 |
871 ESR_INT_XDP_P0_CH2 |
872 ESR_INT_XDP_P0_CH1 |
873 ESR_INT_XDP_P0_CH0);
874 break;
875
876 case 1:
877 mask = ESR_INT_SIGNALS_P1_BITS;
878 val = (ESR_INT_SRDY0_P1 |
879 ESR_INT_DET0_P1 |
880 ESR_INT_XSRDY_P1 |
881 ESR_INT_XDP_P1_CH3 |
882 ESR_INT_XDP_P1_CH2 |
883 ESR_INT_XDP_P1_CH1 |
884 ESR_INT_XDP_P1_CH0);
885 break;
886
887 default:
888 return -EINVAL;
889 }
890
891 if ((sig & mask) != val) {
a5d6ab56
MW		 892 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
893 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
894 return 0;
895 }
a3138df9
DM		 896 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
897 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
898 return -ENODEV;
899 }
a5d6ab56
MW		 900 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
901 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
a3138df9
DM		 902 return 0;
903}
904
905static int serdes_init_1g(struct niu *np)
906{
907 u64 val;
908
909 val = nr64(ENET_SERDES_1_PLL_CFG);
910 val &= ~ENET_SERDES_PLL_FBDIV2;
911 switch (np->port) {
912 case 0:
913 val |= ENET_SERDES_PLL_HRATE0;
914 break;
915 case 1:
916 val |= ENET_SERDES_PLL_HRATE1;
917 break;
918 case 2:
919 val |= ENET_SERDES_PLL_HRATE2;
920 break;
921 case 3:
922 val |= ENET_SERDES_PLL_HRATE3;
923 break;
924 default:
925 return -EINVAL;
926 }
927 nw64(ENET_SERDES_1_PLL_CFG, val);
928
929 return 0;
930}
931
5fbd7e24
MW		 932static int serdes_init_1g_serdes(struct niu *np)
933{
934 struct niu_link_config *lp = &np->link_config;
935 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
936 u64 ctrl_val, test_cfg_val, sig, mask, val;
937 int err;
938 u64 reset_val, val_rd;
939
940 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
941 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
942 ENET_SERDES_PLL_FBDIV0;
943 switch (np->port) {
944 case 0:
945 reset_val = ENET_SERDES_RESET_0;
946 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
947 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
948 pll_cfg = ENET_SERDES_0_PLL_CFG;
949 break;
950 case 1:
951 reset_val = ENET_SERDES_RESET_1;
952 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
953 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
954 pll_cfg = ENET_SERDES_1_PLL_CFG;
955 break;
956
957 default:
958 return -EINVAL;
959 }
960 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
961 ENET_SERDES_CTRL_SDET_1 |
962 ENET_SERDES_CTRL_SDET_2 |
963 ENET_SERDES_CTRL_SDET_3 |
964 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
965 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
966 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
967 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
968 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
969 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
970 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
971 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
972 test_cfg_val = 0;
973
974 if (lp->loopback_mode == LOOPBACK_PHY) {
975 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
976 ENET_SERDES_TEST_MD_0_SHIFT) |
977 (ENET_TEST_MD_PAD_LOOPBACK <<
978 ENET_SERDES_TEST_MD_1_SHIFT) |
979 (ENET_TEST_MD_PAD_LOOPBACK <<
980 ENET_SERDES_TEST_MD_2_SHIFT) |
981 (ENET_TEST_MD_PAD_LOOPBACK <<
982 ENET_SERDES_TEST_MD_3_SHIFT));
983 }
984
985 nw64(ENET_SERDES_RESET, reset_val);
986 mdelay(20);
987 val_rd = nr64(ENET_SERDES_RESET);
988 val_rd &= ~reset_val;
989 nw64(pll_cfg, val);
990 nw64(ctrl_reg, ctrl_val);
991 nw64(test_cfg_reg, test_cfg_val);
992 nw64(ENET_SERDES_RESET, val_rd);
993 mdelay(2000);
994
995 /* Initialize all 4 lanes of the SERDES. */
996 for (i = 0; i < 4; i++) {
997 u32 rxtx_ctrl, glue0;
998
999 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
1000 if (err)
1001 return err;
1002 err = esr_read_glue0(np, i, &glue0);
1003 if (err)
1004 return err;
1005
1006 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
1007 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
1008 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
1009
1010 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
1011 ESR_GLUE_CTRL0_THCNT |
1012 ESR_GLUE_CTRL0_BLTIME);
1013 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
1014 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
1015 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
1016 (BLTIME_300_CYCLES <<
1017 ESR_GLUE_CTRL0_BLTIME_SHIFT));
1018
1019 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
1020 if (err)
1021 return err;
1022 err = esr_write_glue0(np, i, glue0);
1023 if (err)
1024 return err;
1025 }
1026
1027
1028 sig = nr64(ESR_INT_SIGNALS);
1029 switch (np->port) {
1030 case 0:
1031 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1032 mask = val;
1033 break;
1034
1035 case 1:
1036 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1037 mask = val;
1038 break;
1039
1040 default:
1041 return -EINVAL;
1042 }
1043
1044 if ((sig & mask) != val) {
1045 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
1046 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
1047 return -ENODEV;
1048 }
1049
1050 return 0;
1051}
1052
1053static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1054{
1055 struct niu_link_config *lp = &np->link_config;
1056 int link_up;
1057 u64 val;
1058 u16 current_speed;
1059 unsigned long flags;
1060 u8 current_duplex;
1061
1062 link_up = 0;
1063 current_speed = SPEED_INVALID;
1064 current_duplex = DUPLEX_INVALID;
1065
1066 spin_lock_irqsave(&np->lock, flags);
1067
1068 val = nr64_pcs(PCS_MII_STAT);
1069
1070 if (val & PCS_MII_STAT_LINK_STATUS) {
1071 link_up = 1;
1072 current_speed = SPEED_1000;
1073 current_duplex = DUPLEX_FULL;
1074 }
1075
1076 lp->active_speed = current_speed;
1077 lp->active_duplex = current_duplex;
1078 spin_unlock_irqrestore(&np->lock, flags);
1079
1080 *link_up_p = link_up;
1081 return 0;
1082}
1083
5fbd7e24
MW		 1084static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1085{
1086 unsigned long flags;
1087 struct niu_link_config *lp = &np->link_config;
1088 int link_up = 0;
1089 int link_ok = 1;
1090 u64 val, val2;
1091 u16 current_speed;
1092 u8 current_duplex;
1093
1094 if (!(np->flags & NIU_FLAGS_10G))
1095 return link_status_1g_serdes(np, link_up_p);
1096
1097 current_speed = SPEED_INVALID;
1098 current_duplex = DUPLEX_INVALID;
1099 spin_lock_irqsave(&np->lock, flags);
1100
1101 val = nr64_xpcs(XPCS_STATUS(0));
1102 val2 = nr64_mac(XMAC_INTER2);
1103 if (val2 & 0x01000000)
1104 link_ok = 0;
1105
1106 if ((val & 0x1000ULL) && link_ok) {
1107 link_up = 1;
1108 current_speed = SPEED_10000;
1109 current_duplex = DUPLEX_FULL;
1110 }
1111 lp->active_speed = current_speed;
1112 lp->active_duplex = current_duplex;
1113 spin_unlock_irqrestore(&np->lock, flags);
1114 *link_up_p = link_up;
1115 return 0;
1116}
1117
38bb045d
CB		 1118static int link_status_mii(struct niu *np, int *link_up_p)
1119{
1120 struct niu_link_config *lp = &np->link_config;
1121 int err;
1122 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1123 int supported, advertising, active_speed, active_duplex;
1124
1125 err = mii_read(np, np->phy_addr, MII_BMCR);
1126 if (unlikely(err < 0))
1127 return err;
1128 bmcr = err;
1129
1130 err = mii_read(np, np->phy_addr, MII_BMSR);
1131 if (unlikely(err < 0))
1132 return err;
1133 bmsr = err;
1134
1135 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1136 if (unlikely(err < 0))
1137 return err;
1138 advert = err;
1139
1140 err = mii_read(np, np->phy_addr, MII_LPA);
1141 if (unlikely(err < 0))
1142 return err;
1143 lpa = err;
1144
1145 if (likely(bmsr & BMSR_ESTATEN)) {
1146 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1147 if (unlikely(err < 0))
1148 return err;
1149 estatus = err;
1150
1151 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1152 if (unlikely(err < 0))
1153 return err;
1154 ctrl1000 = err;
1155
1156 err = mii_read(np, np->phy_addr, MII_STAT1000);
1157 if (unlikely(err < 0))
1158 return err;
1159 stat1000 = err;
1160 } else
1161 estatus = ctrl1000 = stat1000 = 0;
1162
1163 supported = 0;
1164 if (bmsr & BMSR_ANEGCAPABLE)
1165 supported |= SUPPORTED_Autoneg;
1166 if (bmsr & BMSR_10HALF)
1167 supported |= SUPPORTED_10baseT_Half;
1168 if (bmsr & BMSR_10FULL)
1169 supported |= SUPPORTED_10baseT_Full;
1170 if (bmsr & BMSR_100HALF)
1171 supported |= SUPPORTED_100baseT_Half;
1172 if (bmsr & BMSR_100FULL)
1173 supported |= SUPPORTED_100baseT_Full;
1174 if (estatus & ESTATUS_1000_THALF)
1175 supported |= SUPPORTED_1000baseT_Half;
1176 if (estatus & ESTATUS_1000_TFULL)
1177 supported |= SUPPORTED_1000baseT_Full;
1178 lp->supported = supported;
1179
1180 advertising = 0;
1181 if (advert & ADVERTISE_10HALF)
1182 advertising |= ADVERTISED_10baseT_Half;
1183 if (advert & ADVERTISE_10FULL)
1184 advertising |= ADVERTISED_10baseT_Full;
1185 if (advert & ADVERTISE_100HALF)
1186 advertising |= ADVERTISED_100baseT_Half;
1187 if (advert & ADVERTISE_100FULL)
1188 advertising |= ADVERTISED_100baseT_Full;
1189 if (ctrl1000 & ADVERTISE_1000HALF)
1190 advertising |= ADVERTISED_1000baseT_Half;
1191 if (ctrl1000 & ADVERTISE_1000FULL)
1192 advertising |= ADVERTISED_1000baseT_Full;
1193
1194 if (bmcr & BMCR_ANENABLE) {
1195 int neg, neg1000;
1196
1197 lp->active_autoneg = 1;
1198 advertising |= ADVERTISED_Autoneg;
1199
1200 neg = advert & lpa;
1201 neg1000 = (ctrl1000 << 2) & stat1000;
1202
1203 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1204 active_speed = SPEED_1000;
1205 else if (neg & LPA_100)
1206 active_speed = SPEED_100;
1207 else if (neg & (LPA_10HALF | LPA_10FULL))
1208 active_speed = SPEED_10;
1209 else
1210 active_speed = SPEED_INVALID;
1211
1212 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1213 active_duplex = DUPLEX_FULL;
1214 else if (active_speed != SPEED_INVALID)
1215 active_duplex = DUPLEX_HALF;
1216 else
1217 active_duplex = DUPLEX_INVALID;
1218 } else {
1219 lp->active_autoneg = 0;
1220
1221 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1222 active_speed = SPEED_1000;
1223 else if (bmcr & BMCR_SPEED100)
1224 active_speed = SPEED_100;
1225 else
1226 active_speed = SPEED_10;
1227
1228 if (bmcr & BMCR_FULLDPLX)
1229 active_duplex = DUPLEX_FULL;
1230 else
1231 active_duplex = DUPLEX_HALF;
1232 }
1233
1234 lp->active_advertising = advertising;
1235 lp->active_speed = active_speed;
1236 lp->active_duplex = active_duplex;
1237 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1238
1239 return 0;
1240}
1241
5fbd7e24
MW		 1242static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1243{
1244 struct niu_link_config *lp = &np->link_config;
1245 u16 current_speed, bmsr;
1246 unsigned long flags;
1247 u8 current_duplex;
1248 int err, link_up;
1249
1250 link_up = 0;
1251 current_speed = SPEED_INVALID;
1252 current_duplex = DUPLEX_INVALID;
1253
1254 spin_lock_irqsave(&np->lock, flags);
1255
1256 err = -EINVAL;
1257
1258 err = mii_read(np, np->phy_addr, MII_BMSR);
1259 if (err < 0)
1260 goto out;
1261
1262 bmsr = err;
1263 if (bmsr & BMSR_LSTATUS) {
1264 u16 adv, lpa, common, estat;
1265
1266 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1267 if (err < 0)
1268 goto out;
1269 adv = err;
1270
1271 err = mii_read(np, np->phy_addr, MII_LPA);
1272 if (err < 0)
1273 goto out;
1274 lpa = err;
1275
1276 common = adv & lpa;
1277
1278 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1279 if (err < 0)
1280 goto out;
1281 estat = err;
1282 link_up = 1;
1283 current_speed = SPEED_1000;
1284 current_duplex = DUPLEX_FULL;
1285
1286 }
1287 lp->active_speed = current_speed;
1288 lp->active_duplex = current_duplex;
1289 err = 0;
1290
1291out:
1292 spin_unlock_irqrestore(&np->lock, flags);
1293
1294 *link_up_p = link_up;
1295 return err;
1296}
1297
38bb045d
CB		 1298static int link_status_1g(struct niu *np, int *link_up_p)
1299{
1300 struct niu_link_config *lp = &np->link_config;
1301 unsigned long flags;
1302 int err;
1303
1304 spin_lock_irqsave(&np->lock, flags);
1305
1306 err = link_status_mii(np, link_up_p);
1307 lp->supported |= SUPPORTED_TP;
1308 lp->active_advertising |= ADVERTISED_TP;
1309
1310 spin_unlock_irqrestore(&np->lock, flags);
1311 return err;
1312}
1313
a3138df9
DM		 1314static int bcm8704_reset(struct niu *np)
1315{
1316 int err, limit;
1317
1318 err = mdio_read(np, np->phy_addr,
1319 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1320 if (err < 0)
1321 return err;
1322 err |= BMCR_RESET;
1323 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1324 MII_BMCR, err);
1325 if (err)
1326 return err;
1327
1328 limit = 1000;
1329 while (--limit >= 0) {
1330 err = mdio_read(np, np->phy_addr,
1331 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1332 if (err < 0)
1333 return err;
1334 if (!(err & BMCR_RESET))
1335 break;
1336 }
1337 if (limit < 0) {
1338 dev_err(np->device, PFX "Port %u PHY will not reset "
1339 "(bmcr=%04x)\n", np->port, (err & 0xffff));
1340 return -ENODEV;
1341 }
1342 return 0;
1343}
1344
1345/* When written, certain PHY registers need to be read back twice
1346 * in order for the bits to settle properly.
1347 */
1348static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1349{
1350 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1351 if (err < 0)
1352 return err;
1353 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1354 if (err < 0)
1355 return err;
1356 return 0;
1357}
1358
a5d6ab56
MW		 1359static int bcm8706_init_user_dev3(struct niu *np)
1360{
1361 int err;
1362
1363
1364 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1365 BCM8704_USER_OPT_DIGITAL_CTRL);
1366 if (err < 0)
1367 return err;
1368 err &= ~USER_ODIG_CTRL_GPIOS;
1369 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1370 err |= USER_ODIG_CTRL_RESV2;
1371 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1372 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1373 if (err)
1374 return err;
1375
1376 mdelay(1000);
1377
1378 return 0;
1379}
1380
a3138df9
DM		 1381static int bcm8704_init_user_dev3(struct niu *np)
1382{
1383 int err;
1384
1385 err = mdio_write(np, np->phy_addr,
1386 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1387 (USER_CONTROL_OPTXRST_LVL |
1388 USER_CONTROL_OPBIASFLT_LVL |
1389 USER_CONTROL_OBTMPFLT_LVL |
1390 USER_CONTROL_OPPRFLT_LVL |
1391 USER_CONTROL_OPTXFLT_LVL |
1392 USER_CONTROL_OPRXLOS_LVL |
1393 USER_CONTROL_OPRXFLT_LVL |
1394 USER_CONTROL_OPTXON_LVL |
1395 (0x3f << USER_CONTROL_RES1_SHIFT)));
1396 if (err)
1397 return err;
1398
1399 err = mdio_write(np, np->phy_addr,
1400 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1401 (USER_PMD_TX_CTL_XFP_CLKEN |
1402 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1403 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1404 USER_PMD_TX_CTL_TSCK_LPWREN));
1405 if (err)
1406 return err;
1407
1408 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1409 if (err)
1410 return err;
1411 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1412 if (err)
1413 return err;
1414
1415 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1416 BCM8704_USER_OPT_DIGITAL_CTRL);
1417 if (err < 0)
1418 return err;
1419 err &= ~USER_ODIG_CTRL_GPIOS;
1420 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1421 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1422 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1423 if (err)
1424 return err;
1425
1426 mdelay(1000);
1427
1428 return 0;
1429}
1430
b0de8e40
ML		 1431static int mrvl88x2011_act_led(struct niu *np, int val)
1432{
1433 int err;
1434
1435 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1436 MRVL88X2011_LED_8_TO_11_CTL);
1437 if (err < 0)
1438 return err;
1439
1440 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1441 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1442
1443 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1444 MRVL88X2011_LED_8_TO_11_CTL, err);
1445}
1446
1447static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1448{
1449 int err;
1450
1451 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1452 MRVL88X2011_LED_BLINK_CTL);
1453 if (err >= 0) {
1454 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1455 err |= (rate << 4);
1456
1457 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1458 MRVL88X2011_LED_BLINK_CTL, err);
1459 }
1460
1461 return err;
1462}
1463
1464static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1465{
1466 int err;
1467
1468 /* Set LED functions */
1469 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1470 if (err)
1471 return err;
1472
1473 /* led activity */
1474 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1475 if (err)
1476 return err;
1477
1478 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1479 MRVL88X2011_GENERAL_CTL);
1480 if (err < 0)
1481 return err;
1482
1483 err |= MRVL88X2011_ENA_XFPREFCLK;
1484
1485 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1486 MRVL88X2011_GENERAL_CTL, err);
1487 if (err < 0)
1488 return err;
1489
1490 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1491 MRVL88X2011_PMA_PMD_CTL_1);
1492 if (err < 0)
1493 return err;
1494
1495 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1496 err |= MRVL88X2011_LOOPBACK;
1497 else
1498 err &= ~MRVL88X2011_LOOPBACK;
1499
1500 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1501 MRVL88X2011_PMA_PMD_CTL_1, err);
1502 if (err < 0)
1503 return err;
1504
1505 /* Enable PMD */
1506 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1507 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1508}
1509
a5d6ab56
MW		 1510
1511static int xcvr_diag_bcm870x(struct niu *np)
a3138df9 1512{
a3138df9 1513 u16 analog_stat0, tx_alarm_status;
a5d6ab56 1514 int err = 0;
a3138df9
DM		 1515
1516#if 1
1517 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1518 MII_STAT1000);
1519 if (err < 0)
1520 return err;
1521 pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1522 np->port, err);
1523
1524 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1525 if (err < 0)
1526 return err;
1527 pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
1528 np->port, err);
1529
1530 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1531 MII_NWAYTEST);
1532 if (err < 0)
1533 return err;
1534 pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1535 np->port, err);
1536#endif
1537
1538 /* XXX dig this out it might not be so useful XXX */
1539 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1540 BCM8704_USER_ANALOG_STATUS0);
1541 if (err < 0)
1542 return err;
1543 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1544 BCM8704_USER_ANALOG_STATUS0);
1545 if (err < 0)
1546 return err;
1547 analog_stat0 = err;
1548
1549 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1550 BCM8704_USER_TX_ALARM_STATUS);
1551 if (err < 0)
1552 return err;
1553 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1554 BCM8704_USER_TX_ALARM_STATUS);
1555 if (err < 0)
1556 return err;
1557 tx_alarm_status = err;
1558
1559 if (analog_stat0 != 0x03fc) {
1560 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1561 pr_info(PFX "Port %u cable not connected "
1562 "or bad cable.\n", np->port);
1563 } else if (analog_stat0 == 0x639c) {
1564 pr_info(PFX "Port %u optical module is bad "
1565 "or missing.\n", np->port);
1566 }
1567 }
1568
1569 return 0;
1570}
1571
a5d6ab56
MW		 1572static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1573{
1574 struct niu_link_config *lp = &np->link_config;
1575 int err;
1576
1577 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1578 MII_BMCR);
1579 if (err < 0)
1580 return err;
1581
1582 err &= ~BMCR_LOOPBACK;
1583
1584 if (lp->loopback_mode == LOOPBACK_MAC)
1585 err |= BMCR_LOOPBACK;
1586
1587 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1588 MII_BMCR, err);
1589 if (err)
1590 return err;
1591
1592 return 0;
1593}
1594
1595static int xcvr_init_10g_bcm8706(struct niu *np)
1596{
1597 int err = 0;
1598 u64 val;
1599
1600 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1601 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1602 return err;
1603
1604 val = nr64_mac(XMAC_CONFIG);
1605 val &= ~XMAC_CONFIG_LED_POLARITY;
1606 val |= XMAC_CONFIG_FORCE_LED_ON;
1607 nw64_mac(XMAC_CONFIG, val);
1608
1609 val = nr64(MIF_CONFIG);
1610 val |= MIF_CONFIG_INDIRECT_MODE;
1611 nw64(MIF_CONFIG, val);
1612
1613 err = bcm8704_reset(np);
1614 if (err)
1615 return err;
1616
1617 err = xcvr_10g_set_lb_bcm870x(np);
1618 if (err)
1619 return err;
1620
1621 err = bcm8706_init_user_dev3(np);
1622 if (err)
1623 return err;
1624
1625 err = xcvr_diag_bcm870x(np);
1626 if (err)
1627 return err;
1628
1629 return 0;
1630}
1631
1632static int xcvr_init_10g_bcm8704(struct niu *np)
1633{
1634 int err;
1635
1636 err = bcm8704_reset(np);
1637 if (err)
1638 return err;
1639
1640 err = bcm8704_init_user_dev3(np);
1641 if (err)
1642 return err;
1643
1644 err = xcvr_10g_set_lb_bcm870x(np);
1645 if (err)
1646 return err;
1647
1648 err = xcvr_diag_bcm870x(np);
1649 if (err)
1650 return err;
1651
1652 return 0;
1653}
1654
b0de8e40
ML		 1655static int xcvr_init_10g(struct niu *np)
1656{
1657 int phy_id, err;
1658 u64 val;
1659
1660 val = nr64_mac(XMAC_CONFIG);
1661 val &= ~XMAC_CONFIG_LED_POLARITY;
1662 val |= XMAC_CONFIG_FORCE_LED_ON;
1663 nw64_mac(XMAC_CONFIG, val);
1664
1665 /* XXX shared resource, lock parent XXX */
1666 val = nr64(MIF_CONFIG);
1667 val |= MIF_CONFIG_INDIRECT_MODE;
1668 nw64(MIF_CONFIG, val);
1669
1670 phy_id = phy_decode(np->parent->port_phy, np->port);
1671 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1672
1673 /* handle different phy types */
1674 switch (phy_id & NIU_PHY_ID_MASK) {
1675 case NIU_PHY_ID_MRVL88X2011:
1676 err = xcvr_init_10g_mrvl88x2011(np);
1677 break;
1678
1679 default: /* bcom 8704 */
1680 err = xcvr_init_10g_bcm8704(np);
1681 break;
1682 }
1683
1684 return 0;
1685}
1686
a3138df9
DM		 1687static int mii_reset(struct niu *np)
1688{
1689 int limit, err;
1690
1691 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1692 if (err)
1693 return err;
1694
1695 limit = 1000;
1696 while (--limit >= 0) {
1697 udelay(500);
1698 err = mii_read(np, np->phy_addr, MII_BMCR);
1699 if (err < 0)
1700 return err;
1701 if (!(err & BMCR_RESET))
1702 break;
1703 }
1704 if (limit < 0) {
1705 dev_err(np->device, PFX "Port %u MII would not reset, "
1706 "bmcr[%04x]\n", np->port, err);
1707 return -ENODEV;
1708 }
1709
1710 return 0;
1711}
1712
5fbd7e24
MW		 1713static int xcvr_init_1g_rgmii(struct niu *np)
1714{
1715 int err;
1716 u64 val;
1717 u16 bmcr, bmsr, estat;
1718
1719 val = nr64(MIF_CONFIG);
1720 val &= ~MIF_CONFIG_INDIRECT_MODE;
1721 nw64(MIF_CONFIG, val);
1722
1723 err = mii_reset(np);
1724 if (err)
1725 return err;
1726
1727 err = mii_read(np, np->phy_addr, MII_BMSR);
1728 if (err < 0)
1729 return err;
1730 bmsr = err;
1731
1732 estat = 0;
1733 if (bmsr & BMSR_ESTATEN) {
1734 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1735 if (err < 0)
1736 return err;
1737 estat = err;
1738 }
1739
1740 bmcr = 0;
1741 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1742 if (err)
1743 return err;
1744
1745 if (bmsr & BMSR_ESTATEN) {
1746 u16 ctrl1000 = 0;
1747
1748 if (estat & ESTATUS_1000_TFULL)
1749 ctrl1000 |= ADVERTISE_1000FULL;
1750 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1751 if (err)
1752 return err;
1753 }
1754
1755 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1756
1757 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1758 if (err)
1759 return err;
1760
1761 err = mii_read(np, np->phy_addr, MII_BMCR);
1762 if (err < 0)
1763 return err;
1764 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1765
1766 err = mii_read(np, np->phy_addr, MII_BMSR);
1767 if (err < 0)
1768 return err;
1769
1770 return 0;
1771}
1772
a3138df9
DM		 1773static int mii_init_common(struct niu *np)
1774{
1775 struct niu_link_config *lp = &np->link_config;
1776 u16 bmcr, bmsr, adv, estat;
1777 int err;
1778
1779 err = mii_reset(np);
1780 if (err)
1781 return err;
1782
1783 err = mii_read(np, np->phy_addr, MII_BMSR);
1784 if (err < 0)
1785 return err;
1786 bmsr = err;
1787
1788 estat = 0;
1789 if (bmsr & BMSR_ESTATEN) {
1790 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1791 if (err < 0)
1792 return err;
1793 estat = err;
1794 }
1795
1796 bmcr = 0;
1797 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1798 if (err)
1799 return err;
1800
1801 if (lp->loopback_mode == LOOPBACK_MAC) {
1802 bmcr |= BMCR_LOOPBACK;
1803 if (lp->active_speed == SPEED_1000)
1804 bmcr |= BMCR_SPEED1000;
1805 if (lp->active_duplex == DUPLEX_FULL)
1806 bmcr |= BMCR_FULLDPLX;
1807 }
1808
1809 if (lp->loopback_mode == LOOPBACK_PHY) {
1810 u16 aux;
1811
1812 aux = (BCM5464R_AUX_CTL_EXT_LB |
1813 BCM5464R_AUX_CTL_WRITE_1);
1814 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1815 if (err)
1816 return err;
1817 }
1818
38bb045d
CB		 1819 if (lp->autoneg) {
1820 u16 ctrl1000;
1821
1822 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1823 if ((bmsr & BMSR_10HALF) &&
1824 (lp->advertising & ADVERTISED_10baseT_Half))
1825 adv |= ADVERTISE_10HALF;
1826 if ((bmsr & BMSR_10FULL) &&
1827 (lp->advertising & ADVERTISED_10baseT_Full))
1828 adv |= ADVERTISE_10FULL;
1829 if ((bmsr & BMSR_100HALF) &&
1830 (lp->advertising & ADVERTISED_100baseT_Half))
1831 adv |= ADVERTISE_100HALF;
1832 if ((bmsr & BMSR_100FULL) &&
1833 (lp->advertising & ADVERTISED_100baseT_Full))
1834 adv |= ADVERTISE_100FULL;
1835 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
a3138df9
DM		 1836 if (err)
1837 return err;
38bb045d
CB		 1838
1839 if (likely(bmsr & BMSR_ESTATEN)) {
1840 ctrl1000 = 0;
1841 if ((estat & ESTATUS_1000_THALF) &&
1842 (lp->advertising & ADVERTISED_1000baseT_Half))
1843 ctrl1000 |= ADVERTISE_1000HALF;
1844 if ((estat & ESTATUS_1000_TFULL) &&
1845 (lp->advertising & ADVERTISED_1000baseT_Full))
1846 ctrl1000 |= ADVERTISE_1000FULL;
1847 err = mii_write(np, np->phy_addr,
1848 MII_CTRL1000, ctrl1000);
1849 if (err)
1850 return err;
1851 }
1852
1853 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1854 } else {
1855 /* !lp->autoneg */
1856 int fulldpx;
1857
1858 if (lp->duplex == DUPLEX_FULL) {
1859 bmcr |= BMCR_FULLDPLX;
1860 fulldpx = 1;
1861 } else if (lp->duplex == DUPLEX_HALF)
1862 fulldpx = 0;
1863 else
1864 return -EINVAL;
1865
1866 if (lp->speed == SPEED_1000) {
1867 /* if X-full requested while not supported, or
1868 X-half requested while not supported... */
1869 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1870 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1871 return -EINVAL;
1872 bmcr |= BMCR_SPEED1000;
1873 } else if (lp->speed == SPEED_100) {
1874 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1875 (!fulldpx && !(bmsr & BMSR_100HALF)))
1876 return -EINVAL;
1877 bmcr |= BMCR_SPEED100;
1878 } else if (lp->speed == SPEED_10) {
1879 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1880 (!fulldpx && !(bmsr & BMSR_10HALF)))
1881 return -EINVAL;
1882 } else
1883 return -EINVAL;
a3138df9 1884 }
a3138df9
DM		 1885
1886 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1887 if (err)
1888 return err;
1889
38bb045d 1890#if 0
a3138df9
DM		 1891 err = mii_read(np, np->phy_addr, MII_BMCR);
1892 if (err < 0)
1893 return err;
38bb045d
CB		 1894 bmcr = err;
1895
a3138df9
DM		 1896 err = mii_read(np, np->phy_addr, MII_BMSR);
1897 if (err < 0)
1898 return err;
38bb045d
CB		 1899 bmsr = err;
1900
a3138df9
DM		 1901 pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1902 np->port, bmcr, bmsr);
1903#endif
1904
1905 return 0;
1906}
1907
1908static int xcvr_init_1g(struct niu *np)
1909{
1910 u64 val;
1911
1912 /* XXX shared resource, lock parent XXX */
1913 val = nr64(MIF_CONFIG);
1914 val &= ~MIF_CONFIG_INDIRECT_MODE;
1915 nw64(MIF_CONFIG, val);
1916
1917 return mii_init_common(np);
1918}
1919
1920static int niu_xcvr_init(struct niu *np)
1921{
1922 const struct niu_phy_ops *ops = np->phy_ops;
1923 int err;
1924
1925 err = 0;
1926 if (ops->xcvr_init)
1927 err = ops->xcvr_init(np);
1928
1929 return err;
1930}
1931
1932static int niu_serdes_init(struct niu *np)
1933{
1934 const struct niu_phy_ops *ops = np->phy_ops;
1935 int err;
1936
1937 err = 0;
1938 if (ops->serdes_init)
1939 err = ops->serdes_init(np);
1940
1941 return err;
1942}
1943
1944static void niu_init_xif(struct niu *);
0c3b091b 1945static void niu_handle_led(struct niu *, int status);
a3138df9
DM		 1946
1947static int niu_link_status_common(struct niu *np, int link_up)
1948{
1949 struct niu_link_config *lp = &np->link_config;
1950 struct net_device *dev = np->dev;
1951 unsigned long flags;
1952
1953 if (!netif_carrier_ok(dev) && link_up) {
1954 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1955 dev->name,
1956 (lp->active_speed == SPEED_10000 ?
1957 "10Gb/sec" :
1958 (lp->active_speed == SPEED_1000 ?
1959 "1Gb/sec" :
1960 (lp->active_speed == SPEED_100 ?
1961 "100Mbit/sec" : "10Mbit/sec"))),
1962 (lp->active_duplex == DUPLEX_FULL ?
1963 "full" : "half"));
1964
1965 spin_lock_irqsave(&np->lock, flags);
1966 niu_init_xif(np);
0c3b091b 1967 niu_handle_led(np, 1);
a3138df9
DM		 1968 spin_unlock_irqrestore(&np->lock, flags);
1969
1970 netif_carrier_on(dev);
1971 } else if (netif_carrier_ok(dev) && !link_up) {
1972 niuwarn(LINK, "%s: Link is down\n", dev->name);
0c3b091b
ML		 1973 spin_lock_irqsave(&np->lock, flags);
1974 niu_handle_led(np, 0);
1975 spin_unlock_irqrestore(&np->lock, flags);
a3138df9
DM		 1976 netif_carrier_off(dev);
1977 }
1978
1979 return 0;
1980}
1981
b0de8e40 1982static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
a3138df9 1983{
b0de8e40 1984 int err, link_up, pma_status, pcs_status;
a3138df9
DM		 1985
1986 link_up = 0;
1987
b0de8e40
ML		 1988 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1989 MRVL88X2011_10G_PMD_STATUS_2);
1990 if (err < 0)
1991 goto out;
a3138df9 1992
b0de8e40
ML		 1993 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1994 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1995 MRVL88X2011_PMA_PMD_STATUS_1);
1996 if (err < 0)
1997 goto out;
1998
1999 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
2000
2001 /* Check PMC Register : 3.0001.2 == 1: read twice */
2002 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
2003 MRVL88X2011_PMA_PMD_STATUS_1);
2004 if (err < 0)
2005 goto out;
2006
2007 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
2008 MRVL88X2011_PMA_PMD_STATUS_1);
2009 if (err < 0)
2010 goto out;
2011
2012 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
2013
2014 /* Check XGXS Register : 4.0018.[0-3,12] */
2015 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
2016 MRVL88X2011_10G_XGXS_LANE_STAT);
2017 if (err < 0)
a3138df9
DM		 2018 goto out;
2019
b0de8e40
ML		 2020 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
2021 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
2022 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
2023 0x800))
2024 link_up = (pma_status && pcs_status) ? 1 : 0;
2025
2026 np->link_config.active_speed = SPEED_10000;
2027 np->link_config.active_duplex = DUPLEX_FULL;
2028 err = 0;
2029out:
2030 mrvl88x2011_act_led(np, (link_up ?
2031 MRVL88X2011_LED_CTL_PCS_ACT :
2032 MRVL88X2011_LED_CTL_OFF));
2033
2034 *link_up_p = link_up;
2035 return err;
2036}
2037
a5d6ab56
MW		 2038static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2039{
2040 int err, link_up;
2041 link_up = 0;
2042
2043 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2044 BCM8704_PMD_RCV_SIGDET);
2045 if (err < 0)
2046 goto out;
2047 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2048 err = 0;
2049 goto out;
2050 }
2051
2052 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2053 BCM8704_PCS_10G_R_STATUS);
2054 if (err < 0)
2055 goto out;
2056
2057 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2058 err = 0;
2059 goto out;
2060 }
2061
2062 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2063 BCM8704_PHYXS_XGXS_LANE_STAT);
2064 if (err < 0)
2065 goto out;
2066 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2067 PHYXS_XGXS_LANE_STAT_MAGIC |
2068 PHYXS_XGXS_LANE_STAT_PATTEST |
2069 PHYXS_XGXS_LANE_STAT_LANE3 |
2070 PHYXS_XGXS_LANE_STAT_LANE2 |
2071 PHYXS_XGXS_LANE_STAT_LANE1 |
2072 PHYXS_XGXS_LANE_STAT_LANE0)) {
2073 err = 0;
2074 np->link_config.active_speed = SPEED_INVALID;
2075 np->link_config.active_duplex = DUPLEX_INVALID;
2076 goto out;
2077 }
2078
2079 link_up = 1;
2080 np->link_config.active_speed = SPEED_10000;
2081 np->link_config.active_duplex = DUPLEX_FULL;
2082 err = 0;
2083
2084out:
2085 *link_up_p = link_up;
2086 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
2087 err = 0;
2088 return err;
2089}
2090
b0de8e40
ML		 2091static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2092{
2093 int err, link_up;
2094
2095 link_up = 0;
2096
a3138df9
DM		 2097 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2098 BCM8704_PMD_RCV_SIGDET);
2099 if (err < 0)
2100 goto out;
2101 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2102 err = 0;
2103 goto out;
2104 }
2105
2106 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2107 BCM8704_PCS_10G_R_STATUS);
2108 if (err < 0)
2109 goto out;
2110 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2111 err = 0;
2112 goto out;
2113 }
2114
2115 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2116 BCM8704_PHYXS_XGXS_LANE_STAT);
2117 if (err < 0)
2118 goto out;
2119
2120 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2121 PHYXS_XGXS_LANE_STAT_MAGIC |
2122 PHYXS_XGXS_LANE_STAT_LANE3 |
2123 PHYXS_XGXS_LANE_STAT_LANE2 |
2124 PHYXS_XGXS_LANE_STAT_LANE1 |
2125 PHYXS_XGXS_LANE_STAT_LANE0)) {
2126 err = 0;
2127 goto out;
2128 }
2129
2130 link_up = 1;
2131 np->link_config.active_speed = SPEED_10000;
2132 np->link_config.active_duplex = DUPLEX_FULL;
2133 err = 0;
2134
2135out:
b0de8e40
ML		 2136 *link_up_p = link_up;
2137 return err;
2138}
2139
2140static int link_status_10g(struct niu *np, int *link_up_p)
2141{
2142 unsigned long flags;
2143 int err = -EINVAL;
2144
2145 spin_lock_irqsave(&np->lock, flags);
2146
2147 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2148 int phy_id;
2149
2150 phy_id = phy_decode(np->parent->port_phy, np->port);
2151 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2152
2153 /* handle different phy types */
2154 switch (phy_id & NIU_PHY_ID_MASK) {
2155 case NIU_PHY_ID_MRVL88X2011:
2156 err = link_status_10g_mrvl(np, link_up_p);
2157 break;
2158
2159 default: /* bcom 8704 */
2160 err = link_status_10g_bcom(np, link_up_p);
2161 break;
2162 }
2163 }
2164
a3138df9
DM		 2165 spin_unlock_irqrestore(&np->lock, flags);
2166
a3138df9
DM		 2167 return err;
2168}
2169
a5d6ab56
MW		 2170static int niu_10g_phy_present(struct niu *np)
2171{
2172 u64 sig, mask, val;
2173
2174 sig = nr64(ESR_INT_SIGNALS);
2175 switch (np->port) {
2176 case 0:
2177 mask = ESR_INT_SIGNALS_P0_BITS;
2178 val = (ESR_INT_SRDY0_P0 |
2179 ESR_INT_DET0_P0 |
2180 ESR_INT_XSRDY_P0 |
2181 ESR_INT_XDP_P0_CH3 |
2182 ESR_INT_XDP_P0_CH2 |
2183 ESR_INT_XDP_P0_CH1 |
2184 ESR_INT_XDP_P0_CH0);
2185 break;
2186
2187 case 1:
2188 mask = ESR_INT_SIGNALS_P1_BITS;
2189 val = (ESR_INT_SRDY0_P1 |
2190 ESR_INT_DET0_P1 |
2191 ESR_INT_XSRDY_P1 |
2192 ESR_INT_XDP_P1_CH3 |
2193 ESR_INT_XDP_P1_CH2 |
2194 ESR_INT_XDP_P1_CH1 |
2195 ESR_INT_XDP_P1_CH0);
2196 break;
2197
2198 default:
2199 return 0;
2200 }
2201
2202 if ((sig & mask) != val)
2203 return 0;
2204 return 1;
2205}
2206
2207static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2208{
2209 unsigned long flags;
2210 int err = 0;
2211 int phy_present;
2212 int phy_present_prev;
2213
2214 spin_lock_irqsave(&np->lock, flags);
2215
2216 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2217 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2218 1 : 0;
2219 phy_present = niu_10g_phy_present(np);
2220 if (phy_present != phy_present_prev) {
2221 /* state change */
2222 if (phy_present) {
2223 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2224 if (np->phy_ops->xcvr_init)
2225 err = np->phy_ops->xcvr_init(np);
2226 if (err) {
2227 /* debounce */
2228 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2229 }
2230 } else {
2231 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2232 *link_up_p = 0;
2233 niuwarn(LINK, "%s: Hotplug PHY Removed\n",
2234 np->dev->name);
2235 }
2236 }
2237 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT)
2238 err = link_status_10g_bcm8706(np, link_up_p);
2239 }
2240
2241 spin_unlock_irqrestore(&np->lock, flags);
2242
2243 return err;
2244}
2245
a3138df9
DM		 2246static int niu_link_status(struct niu *np, int *link_up_p)
2247{
2248 const struct niu_phy_ops *ops = np->phy_ops;
2249 int err;
2250
2251 err = 0;
2252 if (ops->link_status)
2253 err = ops->link_status(np, link_up_p);
2254
2255 return err;
2256}
2257
2258static void niu_timer(unsigned long __opaque)
2259{
2260 struct niu *np = (struct niu *) __opaque;
2261 unsigned long off;
2262 int err, link_up;
2263
2264 err = niu_link_status(np, &link_up);
2265 if (!err)
2266 niu_link_status_common(np, link_up);
2267
2268 if (netif_carrier_ok(np->dev))
2269 off = 5 * HZ;
2270 else
2271 off = 1 * HZ;
2272 np->timer.expires = jiffies + off;
2273
2274 add_timer(&np->timer);
2275}
2276
5fbd7e24
MW		 2277static const struct niu_phy_ops phy_ops_10g_serdes = {
2278 .serdes_init = serdes_init_10g_serdes,
2279 .link_status = link_status_10g_serdes,
2280};
2281
e3e081e1
SB		 2282static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2283 .serdes_init = serdes_init_niu_10g_serdes,
2284 .link_status = link_status_10g_serdes,
2285};
2286
2287static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2288 .serdes_init = serdes_init_niu_1g_serdes,
2289 .link_status = link_status_1g_serdes,
2290};
2291
5fbd7e24
MW		 2292static const struct niu_phy_ops phy_ops_1g_rgmii = {
2293 .xcvr_init = xcvr_init_1g_rgmii,
2294 .link_status = link_status_1g_rgmii,
2295};
2296
a3138df9 2297static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
e3e081e1 2298 .serdes_init = serdes_init_niu_10g_fiber,
a3138df9
DM		 2299 .xcvr_init = xcvr_init_10g,
2300 .link_status = link_status_10g,
2301};
2302
2303static const struct niu_phy_ops phy_ops_10g_fiber = {
2304 .serdes_init = serdes_init_10g,
2305 .xcvr_init = xcvr_init_10g,
2306 .link_status = link_status_10g,
2307};
2308
a5d6ab56
MW		 2309static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2310 .serdes_init = serdes_init_10g,
2311 .xcvr_init = xcvr_init_10g_bcm8706,
2312 .link_status = link_status_10g_hotplug,
2313};
2314
a3138df9
DM		 2315static const struct niu_phy_ops phy_ops_10g_copper = {
2316 .serdes_init = serdes_init_10g,
2317 .link_status = link_status_10g, /* XXX */
2318};
2319
2320static const struct niu_phy_ops phy_ops_1g_fiber = {
2321 .serdes_init = serdes_init_1g,
2322 .xcvr_init = xcvr_init_1g,
2323 .link_status = link_status_1g,
2324};
2325
2326static const struct niu_phy_ops phy_ops_1g_copper = {
2327 .xcvr_init = xcvr_init_1g,
2328 .link_status = link_status_1g,
2329};
2330
2331struct niu_phy_template {
2332 const struct niu_phy_ops *ops;
2333 u32 phy_addr_base;
2334};
2335
e3e081e1 2336static const struct niu_phy_template phy_template_niu_10g_fiber = {
a3138df9
DM		 2337 .ops = &phy_ops_10g_fiber_niu,
2338 .phy_addr_base = 16,
2339};
2340
e3e081e1
SB		 2341static const struct niu_phy_template phy_template_niu_10g_serdes = {
2342 .ops = &phy_ops_10g_serdes_niu,
2343 .phy_addr_base = 0,
2344};
2345
2346static const struct niu_phy_template phy_template_niu_1g_serdes = {
2347 .ops = &phy_ops_1g_serdes_niu,
2348 .phy_addr_base = 0,
2349};
2350
a3138df9
DM		 2351static const struct niu_phy_template phy_template_10g_fiber = {
2352 .ops = &phy_ops_10g_fiber,
2353 .phy_addr_base = 8,
2354};
2355
a5d6ab56
MW		 2356static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2357 .ops = &phy_ops_10g_fiber_hotplug,
2358 .phy_addr_base = 8,
2359};
2360
a3138df9
DM		 2361static const struct niu_phy_template phy_template_10g_copper = {
2362 .ops = &phy_ops_10g_copper,
2363 .phy_addr_base = 10,
2364};
2365
2366static const struct niu_phy_template phy_template_1g_fiber = {
2367 .ops = &phy_ops_1g_fiber,
2368 .phy_addr_base = 0,
2369};
2370
2371static const struct niu_phy_template phy_template_1g_copper = {
2372 .ops = &phy_ops_1g_copper,
2373 .phy_addr_base = 0,
2374};
2375
5fbd7e24
MW		 2376static const struct niu_phy_template phy_template_1g_rgmii = {
2377 .ops = &phy_ops_1g_rgmii,
2378 .phy_addr_base = 0,
2379};
2380
2381static const struct niu_phy_template phy_template_10g_serdes = {
2382 .ops = &phy_ops_10g_serdes,
2383 .phy_addr_base = 0,
2384};
2385
2386static int niu_atca_port_num[4] = {
2387 0, 0, 11, 10
2388};
2389
2390static int serdes_init_10g_serdes(struct niu *np)
2391{
2392 struct niu_link_config *lp = &np->link_config;
2393 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2394 u64 ctrl_val, test_cfg_val, sig, mask, val;
5fbd7e24
MW		 2395 u64 reset_val;
2396
2397 switch (np->port) {
2398 case 0:
2399 reset_val = ENET_SERDES_RESET_0;
2400 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2401 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2402 pll_cfg = ENET_SERDES_0_PLL_CFG;
2403 break;
2404 case 1:
2405 reset_val = ENET_SERDES_RESET_1;
2406 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2407 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2408 pll_cfg = ENET_SERDES_1_PLL_CFG;
2409 break;
2410
2411 default:
2412 return -EINVAL;
2413 }
2414 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2415 ENET_SERDES_CTRL_SDET_1 |
2416 ENET_SERDES_CTRL_SDET_2 |
2417 ENET_SERDES_CTRL_SDET_3 |
2418 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2419 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2420 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2421 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2422 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2423 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2424 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2425 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2426 test_cfg_val = 0;
2427
2428 if (lp->loopback_mode == LOOPBACK_PHY) {
2429 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2430 ENET_SERDES_TEST_MD_0_SHIFT) |
2431 (ENET_TEST_MD_PAD_LOOPBACK <<
2432 ENET_SERDES_TEST_MD_1_SHIFT) |
2433 (ENET_TEST_MD_PAD_LOOPBACK <<
2434 ENET_SERDES_TEST_MD_2_SHIFT) |
2435 (ENET_TEST_MD_PAD_LOOPBACK <<
2436 ENET_SERDES_TEST_MD_3_SHIFT));
2437 }
2438
2439 esr_reset(np);
2440 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2441 nw64(ctrl_reg, ctrl_val);
2442 nw64(test_cfg_reg, test_cfg_val);
2443
2444 /* Initialize all 4 lanes of the SERDES. */
2445 for (i = 0; i < 4; i++) {
2446 u32 rxtx_ctrl, glue0;
7c34eb89 2447 int err;
5fbd7e24
MW		 2448
2449 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2450 if (err)
2451 return err;
2452 err = esr_read_glue0(np, i, &glue0);
2453 if (err)
2454 return err;
2455
2456 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2457 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2458 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2459
2460 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2461 ESR_GLUE_CTRL0_THCNT |
2462 ESR_GLUE_CTRL0_BLTIME);
2463 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2464 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2465 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2466 (BLTIME_300_CYCLES <<
2467 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2468
2469 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2470 if (err)
2471 return err;
2472 err = esr_write_glue0(np, i, glue0);
2473 if (err)
2474 return err;
2475 }
2476
2477
2478 sig = nr64(ESR_INT_SIGNALS);
2479 switch (np->port) {
2480 case 0:
2481 mask = ESR_INT_SIGNALS_P0_BITS;
2482 val = (ESR_INT_SRDY0_P0 |
2483 ESR_INT_DET0_P0 |
2484 ESR_INT_XSRDY_P0 |
2485 ESR_INT_XDP_P0_CH3 |
2486 ESR_INT_XDP_P0_CH2 |
2487 ESR_INT_XDP_P0_CH1 |
2488 ESR_INT_XDP_P0_CH0);
2489 break;
2490
2491 case 1:
2492 mask = ESR_INT_SIGNALS_P1_BITS;
2493 val = (ESR_INT_SRDY0_P1 |
2494 ESR_INT_DET0_P1 |
2495 ESR_INT_XSRDY_P1 |
2496 ESR_INT_XDP_P1_CH3 |
2497 ESR_INT_XDP_P1_CH2 |
2498 ESR_INT_XDP_P1_CH1 |
2499 ESR_INT_XDP_P1_CH0);
2500 break;
2501
2502 default:
2503 return -EINVAL;
2504 }
2505
2506 if ((sig & mask) != val) {
2507 int err;
2508 err = serdes_init_1g_serdes(np);
2509 if (!err) {
2510 np->flags &= ~NIU_FLAGS_10G;
2511 np->mac_xcvr = MAC_XCVR_PCS;
2512 } else {
2513 dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n",
2514 np->port);
2515 return -ENODEV;
2516 }
2517 }
2518
2519 return 0;
2520}
2521
a3138df9
DM		 2522static int niu_determine_phy_disposition(struct niu *np)
2523{
2524 struct niu_parent *parent = np->parent;
2525 u8 plat_type = parent->plat_type;
2526 const struct niu_phy_template *tp;
2527 u32 phy_addr_off = 0;
2528
2529 if (plat_type == PLAT_TYPE_NIU) {
e3e081e1
SB		 2530 switch (np->flags &
2531 (NIU_FLAGS_10G |
2532 NIU_FLAGS_FIBER |
2533 NIU_FLAGS_XCVR_SERDES)) {
2534 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2535 /* 10G Serdes */
2536 tp = &phy_template_niu_10g_serdes;
2537 break;
2538 case NIU_FLAGS_XCVR_SERDES:
2539 /* 1G Serdes */
2540 tp = &phy_template_niu_1g_serdes;
2541 break;
2542 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2543 /* 10G Fiber */
2544 default:
2545 tp = &phy_template_niu_10g_fiber;
2546 phy_addr_off += np->port;
2547 break;
2548 }
a3138df9 2549 } else {
5fbd7e24
MW		 2550 switch (np->flags &
2551 (NIU_FLAGS_10G |
2552 NIU_FLAGS_FIBER |
2553 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 2554 case 0:
2555 /* 1G copper */
2556 tp = &phy_template_1g_copper;
2557 if (plat_type == PLAT_TYPE_VF_P0)
2558 phy_addr_off = 10;
2559 else if (plat_type == PLAT_TYPE_VF_P1)
2560 phy_addr_off = 26;
2561
2562 phy_addr_off += (np->port ^ 0x3);
2563 break;
2564
2565 case NIU_FLAGS_10G:
2566 /* 10G copper */
e0d8496a 2567 tp = &phy_template_10g_copper;
a3138df9
DM		 2568 break;
2569
2570 case NIU_FLAGS_FIBER:
2571 /* 1G fiber */
2572 tp = &phy_template_1g_fiber;
2573 break;
2574
2575 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2576 /* 10G fiber */
2577 tp = &phy_template_10g_fiber;
2578 if (plat_type == PLAT_TYPE_VF_P0 ||
2579 plat_type == PLAT_TYPE_VF_P1)
2580 phy_addr_off = 8;
2581 phy_addr_off += np->port;
a5d6ab56
MW		 2582 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2583 tp = &phy_template_10g_fiber_hotplug;
2584 if (np->port == 0)
2585 phy_addr_off = 8;
2586 if (np->port == 1)
2587 phy_addr_off = 12;
2588 }
a3138df9
DM		 2589 break;
2590
5fbd7e24
MW		 2591 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2592 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2593 case NIU_FLAGS_XCVR_SERDES:
2594 switch(np->port) {
2595 case 0:
2596 case 1:
2597 tp = &phy_template_10g_serdes;
2598 break;
2599 case 2:
2600 case 3:
2601 tp = &phy_template_1g_rgmii;
2602 break;
2603 default:
2604 return -EINVAL;
2605 break;
2606 }
2607 phy_addr_off = niu_atca_port_num[np->port];
2608 break;
2609
a3138df9
DM		 2610 default:
2611 return -EINVAL;
2612 }
2613 }
2614
2615 np->phy_ops = tp->ops;
2616 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2617
2618 return 0;
2619}
2620
2621static int niu_init_link(struct niu *np)
2622{
2623 struct niu_parent *parent = np->parent;
2624 int err, ignore;
2625
2626 if (parent->plat_type == PLAT_TYPE_NIU) {
2627 err = niu_xcvr_init(np);
2628 if (err)
2629 return err;
2630 msleep(200);
2631 }
2632 err = niu_serdes_init(np);
2633 if (err)
2634 return err;
2635 msleep(200);
2636 err = niu_xcvr_init(np);
2637 if (!err)
2638 niu_link_status(np, &ignore);
2639 return 0;
2640}
2641
2642static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2643{
2644 u16 reg0 = addr[4] << 8 | addr[5];
2645 u16 reg1 = addr[2] << 8 | addr[3];
2646 u16 reg2 = addr[0] << 8 | addr[1];
2647
2648 if (np->flags & NIU_FLAGS_XMAC) {
2649 nw64_mac(XMAC_ADDR0, reg0);
2650 nw64_mac(XMAC_ADDR1, reg1);
2651 nw64_mac(XMAC_ADDR2, reg2);
2652 } else {
2653 nw64_mac(BMAC_ADDR0, reg0);
2654 nw64_mac(BMAC_ADDR1, reg1);
2655 nw64_mac(BMAC_ADDR2, reg2);
2656 }
2657}
2658
2659static int niu_num_alt_addr(struct niu *np)
2660{
2661 if (np->flags & NIU_FLAGS_XMAC)
2662 return XMAC_NUM_ALT_ADDR;
2663 else
2664 return BMAC_NUM_ALT_ADDR;
2665}
2666
2667static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2668{
2669 u16 reg0 = addr[4] << 8 | addr[5];
2670 u16 reg1 = addr[2] << 8 | addr[3];
2671 u16 reg2 = addr[0] << 8 | addr[1];
2672
2673 if (index >= niu_num_alt_addr(np))
2674 return -EINVAL;
2675
2676 if (np->flags & NIU_FLAGS_XMAC) {
2677 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2678 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2679 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2680 } else {
2681 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2682 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2683 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2684 }
2685
2686 return 0;
2687}
2688
2689static int niu_enable_alt_mac(struct niu *np, int index, int on)
2690{
2691 unsigned long reg;
2692 u64 val, mask;
2693
2694 if (index >= niu_num_alt_addr(np))
2695 return -EINVAL;
2696
fa907895 2697 if (np->flags & NIU_FLAGS_XMAC) {
a3138df9 2698 reg = XMAC_ADDR_CMPEN;
fa907895
MW		 2699 mask = 1 << index;
2700 } else {
a3138df9 2701 reg = BMAC_ADDR_CMPEN;
fa907895
MW		 2702 mask = 1 << (index + 1);
2703 }
a3138df9
DM		 2704
2705 val = nr64_mac(reg);
2706 if (on)
2707 val |= mask;
2708 else
2709 val &= ~mask;
2710 nw64_mac(reg, val);
2711
2712 return 0;
2713}
2714
2715static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2716 int num, int mac_pref)
2717{
2718 u64 val = nr64_mac(reg);
2719 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2720 val |= num;
2721 if (mac_pref)
2722 val |= HOST_INFO_MPR;
2723 nw64_mac(reg, val);
2724}
2725
2726static int __set_rdc_table_num(struct niu *np,
2727 int xmac_index, int bmac_index,
2728 int rdc_table_num, int mac_pref)
2729{
2730 unsigned long reg;
2731
2732 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2733 return -EINVAL;
2734 if (np->flags & NIU_FLAGS_XMAC)
2735 reg = XMAC_HOST_INFO(xmac_index);
2736 else
2737 reg = BMAC_HOST_INFO(bmac_index);
2738 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2739 return 0;
2740}
2741
2742static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2743 int mac_pref)
2744{
2745 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2746}
2747
2748static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2749 int mac_pref)
2750{
2751 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2752}
2753
2754static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2755 int table_num, int mac_pref)
2756{
2757 if (idx >= niu_num_alt_addr(np))
2758 return -EINVAL;
2759 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2760}
2761
2762static u64 vlan_entry_set_parity(u64 reg_val)
2763{
2764 u64 port01_mask;
2765 u64 port23_mask;
2766
2767 port01_mask = 0x00ff;
2768 port23_mask = 0xff00;
2769
2770 if (hweight64(reg_val & port01_mask) & 1)
2771 reg_val |= ENET_VLAN_TBL_PARITY0;
2772 else
2773 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2774
2775 if (hweight64(reg_val & port23_mask) & 1)
2776 reg_val |= ENET_VLAN_TBL_PARITY1;
2777 else
2778 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2779
2780 return reg_val;
2781}
2782
2783static void vlan_tbl_write(struct niu *np, unsigned long index,
2784 int port, int vpr, int rdc_table)
2785{
2786 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2787
2788 reg_val &= ~((ENET_VLAN_TBL_VPR |
2789 ENET_VLAN_TBL_VLANRDCTBLN) <<
2790 ENET_VLAN_TBL_SHIFT(port));
2791 if (vpr)
2792 reg_val |= (ENET_VLAN_TBL_VPR <<
2793 ENET_VLAN_TBL_SHIFT(port));
2794 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2795
2796 reg_val = vlan_entry_set_parity(reg_val);
2797
2798 nw64(ENET_VLAN_TBL(index), reg_val);
2799}
2800
2801static void vlan_tbl_clear(struct niu *np)
2802{
2803 int i;
2804
2805 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2806 nw64(ENET_VLAN_TBL(i), 0);
2807}
2808
2809static int tcam_wait_bit(struct niu *np, u64 bit)
2810{
2811 int limit = 1000;
2812
2813 while (--limit > 0) {
2814 if (nr64(TCAM_CTL) & bit)
2815 break;
2816 udelay(1);
2817 }
2818 if (limit < 0)
2819 return -ENODEV;
2820
2821 return 0;
2822}
2823
2824static int tcam_flush(struct niu *np, int index)
2825{
2826 nw64(TCAM_KEY_0, 0x00);
2827 nw64(TCAM_KEY_MASK_0, 0xff);
2828 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2829
2830 return tcam_wait_bit(np, TCAM_CTL_STAT);
2831}
2832
2833#if 0
2834static int tcam_read(struct niu *np, int index,
2835 u64 *key, u64 *mask)
2836{
2837 int err;
2838
2839 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2840 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2841 if (!err) {
2842 key[0] = nr64(TCAM_KEY_0);
2843 key[1] = nr64(TCAM_KEY_1);
2844 key[2] = nr64(TCAM_KEY_2);
2845 key[3] = nr64(TCAM_KEY_3);
2846 mask[0] = nr64(TCAM_KEY_MASK_0);
2847 mask[1] = nr64(TCAM_KEY_MASK_1);
2848 mask[2] = nr64(TCAM_KEY_MASK_2);
2849 mask[3] = nr64(TCAM_KEY_MASK_3);
2850 }
2851 return err;
2852}
2853#endif
2854
2855static int tcam_write(struct niu *np, int index,
2856 u64 *key, u64 *mask)
2857{
2858 nw64(TCAM_KEY_0, key[0]);
2859 nw64(TCAM_KEY_1, key[1]);
2860 nw64(TCAM_KEY_2, key[2]);
2861 nw64(TCAM_KEY_3, key[3]);
2862 nw64(TCAM_KEY_MASK_0, mask[0]);
2863 nw64(TCAM_KEY_MASK_1, mask[1]);
2864 nw64(TCAM_KEY_MASK_2, mask[2]);
2865 nw64(TCAM_KEY_MASK_3, mask[3]);
2866 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2867
2868 return tcam_wait_bit(np, TCAM_CTL_STAT);
2869}
2870
2871#if 0
2872static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2873{
2874 int err;
2875
2876 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2877 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2878 if (!err)
2879 *data = nr64(TCAM_KEY_1);
2880
2881 return err;
2882}
2883#endif
2884
2885static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2886{
2887 nw64(TCAM_KEY_1, assoc_data);
2888 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2889
2890 return tcam_wait_bit(np, TCAM_CTL_STAT);
2891}
2892
2893static void tcam_enable(struct niu *np, int on)
2894{
2895 u64 val = nr64(FFLP_CFG_1);
2896
2897 if (on)
2898 val &= ~FFLP_CFG_1_TCAM_DIS;
2899 else
2900 val |= FFLP_CFG_1_TCAM_DIS;
2901 nw64(FFLP_CFG_1, val);
2902}
2903
2904static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2905{
2906 u64 val = nr64(FFLP_CFG_1);
2907
2908 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2909 FFLP_CFG_1_CAMLAT |
2910 FFLP_CFG_1_CAMRATIO);
2911 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2912 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2913 nw64(FFLP_CFG_1, val);
2914
2915 val = nr64(FFLP_CFG_1);
2916 val |= FFLP_CFG_1_FFLPINITDONE;
2917 nw64(FFLP_CFG_1, val);
2918}
2919
2920static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2921 int on)
2922{
2923 unsigned long reg;
2924 u64 val;
2925
2926 if (class < CLASS_CODE_ETHERTYPE1 ||
2927 class > CLASS_CODE_ETHERTYPE2)
2928 return -EINVAL;
2929
2930 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2931 val = nr64(reg);
2932 if (on)
2933 val |= L2_CLS_VLD;
2934 else
2935 val &= ~L2_CLS_VLD;
2936 nw64(reg, val);
2937
2938 return 0;
2939}
2940
2941#if 0
2942static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2943 u64 ether_type)
2944{
2945 unsigned long reg;
2946 u64 val;
2947
2948 if (class < CLASS_CODE_ETHERTYPE1 ||
2949 class > CLASS_CODE_ETHERTYPE2 ||
2950 (ether_type & ~(u64)0xffff) != 0)
2951 return -EINVAL;
2952
2953 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2954 val = nr64(reg);
2955 val &= ~L2_CLS_ETYPE;
2956 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2957 nw64(reg, val);
2958
2959 return 0;
2960}
2961#endif
2962
2963static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2964 int on)
2965{
2966 unsigned long reg;
2967 u64 val;
2968
2969 if (class < CLASS_CODE_USER_PROG1 ||
2970 class > CLASS_CODE_USER_PROG4)
2971 return -EINVAL;
2972
2973 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2974 val = nr64(reg);
2975 if (on)
2976 val |= L3_CLS_VALID;
2977 else
2978 val &= ~L3_CLS_VALID;
2979 nw64(reg, val);
2980
2981 return 0;
2982}
2983
a3138df9
DM		 2984static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2985 int ipv6, u64 protocol_id,
2986 u64 tos_mask, u64 tos_val)
2987{
2988 unsigned long reg;
2989 u64 val;
2990
2991 if (class < CLASS_CODE_USER_PROG1 ||
2992 class > CLASS_CODE_USER_PROG4 ||
2993 (protocol_id & ~(u64)0xff) != 0 ||
2994 (tos_mask & ~(u64)0xff) != 0 ||
2995 (tos_val & ~(u64)0xff) != 0)
2996 return -EINVAL;
2997
2998 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2999 val = nr64(reg);
3000 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
3001 L3_CLS_TOSMASK | L3_CLS_TOS);
3002 if (ipv6)
3003 val |= L3_CLS_IPVER;
3004 val |= (protocol_id << L3_CLS_PID_SHIFT);
3005 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3006 val |= (tos_val << L3_CLS_TOS_SHIFT);
3007 nw64(reg, val);
3008
3009 return 0;
3010}
a3138df9
DM		 3011
3012static int tcam_early_init(struct niu *np)
3013{
3014 unsigned long i;
3015 int err;
3016
3017 tcam_enable(np, 0);
3018 tcam_set_lat_and_ratio(np,
3019 DEFAULT_TCAM_LATENCY,
3020 DEFAULT_TCAM_ACCESS_RATIO);
3021 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3022 err = tcam_user_eth_class_enable(np, i, 0);
3023 if (err)
3024 return err;
3025 }
3026 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3027 err = tcam_user_ip_class_enable(np, i, 0);
3028 if (err)
3029 return err;
3030 }
3031
3032 return 0;
3033}
3034
3035static int tcam_flush_all(struct niu *np)
3036{
3037 unsigned long i;
3038
3039 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3040 int err = tcam_flush(np, i);
3041 if (err)
3042 return err;
3043 }
3044 return 0;
3045}
3046
3047static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3048{
3049 return ((u64)index | (num_entries == 1 ?
3050 HASH_TBL_ADDR_AUTOINC : 0));
3051}
3052
3053#if 0
3054static int hash_read(struct niu *np, unsigned long partition,
3055 unsigned long index, unsigned long num_entries,
3056 u64 *data)
3057{
3058 u64 val = hash_addr_regval(index, num_entries);
3059 unsigned long i;
3060
3061 if (partition >= FCRAM_NUM_PARTITIONS ||
3062 index + num_entries > FCRAM_SIZE)
3063 return -EINVAL;
3064
3065 nw64(HASH_TBL_ADDR(partition), val);
3066 for (i = 0; i < num_entries; i++)
3067 data[i] = nr64(HASH_TBL_DATA(partition));
3068
3069 return 0;
3070}
3071#endif
3072
3073static int hash_write(struct niu *np, unsigned long partition,
3074 unsigned long index, unsigned long num_entries,
3075 u64 *data)
3076{
3077 u64 val = hash_addr_regval(index, num_entries);
3078 unsigned long i;
3079
3080 if (partition >= FCRAM_NUM_PARTITIONS ||
3081 index + (num_entries * 8) > FCRAM_SIZE)
3082 return -EINVAL;
3083
3084 nw64(HASH_TBL_ADDR(partition), val);
3085 for (i = 0; i < num_entries; i++)
3086 nw64(HASH_TBL_DATA(partition), data[i]);
3087
3088 return 0;
3089}
3090
3091static void fflp_reset(struct niu *np)
3092{
3093 u64 val;
3094
3095 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3096 udelay(10);
3097 nw64(FFLP_CFG_1, 0);
3098
3099 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3100 nw64(FFLP_CFG_1, val);
3101}
3102
3103static void fflp_set_timings(struct niu *np)
3104{
3105 u64 val = nr64(FFLP_CFG_1);
3106
3107 val &= ~FFLP_CFG_1_FFLPINITDONE;
3108 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3109 nw64(FFLP_CFG_1, val);
3110
3111 val = nr64(FFLP_CFG_1);
3112 val |= FFLP_CFG_1_FFLPINITDONE;
3113 nw64(FFLP_CFG_1, val);
3114
3115 val = nr64(FCRAM_REF_TMR);
3116 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3117 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3118 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3119 nw64(FCRAM_REF_TMR, val);
3120}
3121
3122static int fflp_set_partition(struct niu *np, u64 partition,
3123 u64 mask, u64 base, int enable)
3124{
3125 unsigned long reg;
3126 u64 val;
3127
3128 if (partition >= FCRAM_NUM_PARTITIONS ||
3129 (mask & ~(u64)0x1f) != 0 ||
3130 (base & ~(u64)0x1f) != 0)
3131 return -EINVAL;
3132
3133 reg = FLW_PRT_SEL(partition);
3134
3135 val = nr64(reg);
3136 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3137 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3138 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3139 if (enable)
3140 val |= FLW_PRT_SEL_EXT;
3141 nw64(reg, val);
3142
3143 return 0;
3144}
3145
3146static int fflp_disable_all_partitions(struct niu *np)
3147{
3148 unsigned long i;
3149
3150 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3151 int err = fflp_set_partition(np, 0, 0, 0, 0);
3152 if (err)
3153 return err;
3154 }
3155 return 0;
3156}
3157
3158static void fflp_llcsnap_enable(struct niu *np, int on)
3159{
3160 u64 val = nr64(FFLP_CFG_1);
3161
3162 if (on)
3163 val |= FFLP_CFG_1_LLCSNAP;
3164 else
3165 val &= ~FFLP_CFG_1_LLCSNAP;
3166 nw64(FFLP_CFG_1, val);
3167}
3168
3169static void fflp_errors_enable(struct niu *np, int on)
3170{
3171 u64 val = nr64(FFLP_CFG_1);
3172
3173 if (on)
3174 val &= ~FFLP_CFG_1_ERRORDIS;
3175 else
3176 val |= FFLP_CFG_1_ERRORDIS;
3177 nw64(FFLP_CFG_1, val);
3178}
3179
3180static int fflp_hash_clear(struct niu *np)
3181{
3182 struct fcram_hash_ipv4 ent;
3183 unsigned long i;
3184
3185 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3186 memset(&ent, 0, sizeof(ent));
3187 ent.header = HASH_HEADER_EXT;
3188
3189 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3190 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3191 if (err)
3192 return err;
3193 }
3194 return 0;
3195}
3196
3197static int fflp_early_init(struct niu *np)
3198{
3199 struct niu_parent *parent;
3200 unsigned long flags;
3201 int err;
3202
3203 niu_lock_parent(np, flags);
3204
3205 parent = np->parent;
3206 err = 0;
3207 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3208 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
3209 np->port);
3210 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3211 fflp_reset(np);
3212 fflp_set_timings(np);
3213 err = fflp_disable_all_partitions(np);
3214 if (err) {
3215 niudbg(PROBE, "fflp_disable_all_partitions "
3216 "failed, err=%d\n", err);
3217 goto out;
3218 }
3219 }
3220
3221 err = tcam_early_init(np);
3222 if (err) {
3223 niudbg(PROBE, "tcam_early_init failed, err=%d\n",
3224 err);
3225 goto out;
3226 }
3227 fflp_llcsnap_enable(np, 1);
3228 fflp_errors_enable(np, 0);
3229 nw64(H1POLY, 0);
3230 nw64(H2POLY, 0);
3231
3232 err = tcam_flush_all(np);
3233 if (err) {
3234 niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
3235 err);
3236 goto out;
3237 }
3238 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3239 err = fflp_hash_clear(np);
3240 if (err) {
3241 niudbg(PROBE, "fflp_hash_clear failed, "
3242 "err=%d\n", err);
3243 goto out;
3244 }
3245 }
3246
3247 vlan_tbl_clear(np);
3248
3249 niudbg(PROBE, "fflp_early_init: Success\n");
3250 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3251 }
3252out:
3253 niu_unlock_parent(np, flags);
3254 return err;
3255}
3256
3257static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3258{
3259 if (class_code < CLASS_CODE_USER_PROG1 ||
3260 class_code > CLASS_CODE_SCTP_IPV6)
3261 return -EINVAL;
3262
3263 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3264 return 0;
3265}
3266
3267static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3268{
3269 if (class_code < CLASS_CODE_USER_PROG1 ||
3270 class_code > CLASS_CODE_SCTP_IPV6)
3271 return -EINVAL;
3272
3273 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3274 return 0;
3275}
3276
2d96cf8c
SB		 3277/* Entries for the ports are interleaved in the TCAM */
3278static u16 tcam_get_index(struct niu *np, u16 idx)
3279{
3280 /* One entry reserved for IP fragment rule */
3281 if (idx >= (np->clas.tcam_sz - 1))
3282 idx = 0;
3283 return (np->clas.tcam_top + ((idx+1) * np->parent->num_ports));
3284}
3285
3286static u16 tcam_get_size(struct niu *np)
3287{
3288 /* One entry reserved for IP fragment rule */
3289 return np->clas.tcam_sz - 1;
3290}
3291
3292static u16 tcam_get_valid_entry_cnt(struct niu *np)
3293{
3294 /* One entry reserved for IP fragment rule */
3295 return np->clas.tcam_valid_entries - 1;
3296}
3297
a3138df9
DM		 3298static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3299 u32 offset, u32 size)
3300{
3301 int i = skb_shinfo(skb)->nr_frags;
3302 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3303
3304 frag->page = page;
3305 frag->page_offset = offset;
3306 frag->size = size;
3307
3308 skb->len += size;
3309 skb->data_len += size;
3310 skb->truesize += size;
3311
3312 skb_shinfo(skb)->nr_frags = i + 1;
3313}
3314
3315static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3316{
3317 a >>= PAGE_SHIFT;
3318 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3319
3320 return (a & (MAX_RBR_RING_SIZE - 1));
3321}
3322
3323static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3324 struct page ***link)
3325{
3326 unsigned int h = niu_hash_rxaddr(rp, addr);
3327 struct page *p, **pp;
3328
3329 addr &= PAGE_MASK;
3330 pp = &rp->rxhash[h];
3331 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3332 if (p->index == addr) {
3333 *link = pp;
3334 break;
3335 }
3336 }
3337
3338 return p;
3339}
3340
3341static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3342{
3343 unsigned int h = niu_hash_rxaddr(rp, base);
3344
3345 page->index = base;
3346 page->mapping = (struct address_space *) rp->rxhash[h];
3347 rp->rxhash[h] = page;
3348}
3349
3350static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3351 gfp_t mask, int start_index)
3352{
3353 struct page *page;
3354 u64 addr;
3355 int i;
3356
3357 page = alloc_page(mask);
3358 if (!page)
3359 return -ENOMEM;
3360
3361 addr = np->ops->map_page(np->device, page, 0,
3362 PAGE_SIZE, DMA_FROM_DEVICE);
3363
3364 niu_hash_page(rp, page, addr);
3365 if (rp->rbr_blocks_per_page > 1)
3366 atomic_add(rp->rbr_blocks_per_page - 1,
3367 &compound_head(page)->_count);
3368
3369 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3370 __le32 *rbr = &rp->rbr[start_index + i];
3371
3372 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3373 addr += rp->rbr_block_size;
3374 }
3375
3376 return 0;
3377}
3378
3379static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3380{
3381 int index = rp->rbr_index;
3382
3383 rp->rbr_pending++;
3384 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3385 int err = niu_rbr_add_page(np, rp, mask, index);
3386
3387 if (unlikely(err)) {
3388 rp->rbr_pending--;
3389 return;
3390 }
3391
3392 rp->rbr_index += rp->rbr_blocks_per_page;
3393 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3394 if (rp->rbr_index == rp->rbr_table_size)
3395 rp->rbr_index = 0;
3396
3397 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3398 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3399 rp->rbr_pending = 0;
3400 }
3401 }
3402}
3403
3404static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3405{
3406 unsigned int index = rp->rcr_index;
3407 int num_rcr = 0;
3408
3409 rp->rx_dropped++;
3410 while (1) {
3411 struct page *page, **link;
3412 u64 addr, val;
3413 u32 rcr_size;
3414
3415 num_rcr++;
3416
3417 val = le64_to_cpup(&rp->rcr[index]);
3418 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3419 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3420 page = niu_find_rxpage(rp, addr, &link);
3421
3422 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3423 RCR_ENTRY_PKTBUFSZ_SHIFT];
3424 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3425 *link = (struct page *) page->mapping;
3426 np->ops->unmap_page(np->device, page->index,
3427 PAGE_SIZE, DMA_FROM_DEVICE);
3428 page->index = 0;
3429 page->mapping = NULL;
3430 __free_page(page);
3431 rp->rbr_refill_pending++;
3432 }
3433
3434 index = NEXT_RCR(rp, index);
3435 if (!(val & RCR_ENTRY_MULTI))
3436 break;
3437
3438 }
3439 rp->rcr_index = index;
3440
3441 return num_rcr;
3442}
3443
4099e012
DM		 3444static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3445 struct rx_ring_info *rp)
a3138df9
DM		 3446{
3447 unsigned int index = rp->rcr_index;
3448 struct sk_buff *skb;
3449 int len, num_rcr;
3450
3451 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3452 if (unlikely(!skb))
3453 return niu_rx_pkt_ignore(np, rp);
3454
3455 num_rcr = 0;
3456 while (1) {
3457 struct page *page, **link;
3458 u32 rcr_size, append_size;
3459 u64 addr, val, off;
3460
3461 num_rcr++;
3462
3463 val = le64_to_cpup(&rp->rcr[index]);
3464
3465 len = (val & RCR_ENTRY_L2_LEN) >>
3466 RCR_ENTRY_L2_LEN_SHIFT;
3467 len -= ETH_FCS_LEN;
3468
3469 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3470 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3471 page = niu_find_rxpage(rp, addr, &link);
3472
3473 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3474 RCR_ENTRY_PKTBUFSZ_SHIFT];
3475
3476 off = addr & ~PAGE_MASK;
3477 append_size = rcr_size;
3478 if (num_rcr == 1) {
3479 int ptype;
3480
3481 off += 2;
3482 append_size -= 2;
3483
3484 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3485 if ((ptype == RCR_PKT_TYPE_TCP ||
3486 ptype == RCR_PKT_TYPE_UDP) &&
3487 !(val & (RCR_ENTRY_NOPORT |
3488 RCR_ENTRY_ERROR)))
3489 skb->ip_summed = CHECKSUM_UNNECESSARY;
3490 else
3491 skb->ip_summed = CHECKSUM_NONE;
3492 }
3493 if (!(val & RCR_ENTRY_MULTI))
3494 append_size = len - skb->len;
3495
3496 niu_rx_skb_append(skb, page, off, append_size);
3497 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3498 *link = (struct page *) page->mapping;
3499 np->ops->unmap_page(np->device, page->index,
3500 PAGE_SIZE, DMA_FROM_DEVICE);
3501 page->index = 0;
3502 page->mapping = NULL;
3503 rp->rbr_refill_pending++;
3504 } else
3505 get_page(page);
3506
3507 index = NEXT_RCR(rp, index);
3508 if (!(val & RCR_ENTRY_MULTI))
3509 break;
3510
3511 }
3512 rp->rcr_index = index;
3513
3514 skb_reserve(skb, NET_IP_ALIGN);
3515 __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
3516
3517 rp->rx_packets++;
3518 rp->rx_bytes += skb->len;
3519
3520 skb->protocol = eth_type_trans(skb, np->dev);
0c8dfc83 3521 skb_record_rx_queue(skb, rp->rx_channel);
4099e012 3522 napi_gro_receive(napi, skb);
a3138df9
DM		 3523
3524 return num_rcr;
3525}
3526
3527static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3528{
3529 int blocks_per_page = rp->rbr_blocks_per_page;
3530 int err, index = rp->rbr_index;
3531
3532 err = 0;
3533 while (index < (rp->rbr_table_size - blocks_per_page)) {
3534 err = niu_rbr_add_page(np, rp, mask, index);
3535 if (err)
3536 break;
3537
3538 index += blocks_per_page;
3539 }
3540
3541 rp->rbr_index = index;
3542 return err;
3543}
3544
3545static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3546{
3547 int i;
3548
3549 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3550 struct page *page;
3551
3552 page = rp->rxhash[i];
3553 while (page) {
3554 struct page *next = (struct page *) page->mapping;
3555 u64 base = page->index;
3556
3557 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3558 DMA_FROM_DEVICE);
3559 page->index = 0;
3560 page->mapping = NULL;
3561
3562 __free_page(page);
3563
3564 page = next;
3565 }
3566 }
3567
3568 for (i = 0; i < rp->rbr_table_size; i++)
3569 rp->rbr[i] = cpu_to_le32(0);
3570 rp->rbr_index = 0;
3571}
3572
3573static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3574{
3575 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3576 struct sk_buff *skb = tb->skb;
3577 struct tx_pkt_hdr *tp;
3578 u64 tx_flags;
3579 int i, len;
3580
3581 tp = (struct tx_pkt_hdr *) skb->data;
3582 tx_flags = le64_to_cpup(&tp->flags);
3583
3584 rp->tx_packets++;
3585 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3586 ((tx_flags & TXHDR_PAD) / 2));
3587
3588 len = skb_headlen(skb);
3589 np->ops->unmap_single(np->device, tb->mapping,
3590 len, DMA_TO_DEVICE);
3591
3592 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3593 rp->mark_pending--;
3594
3595 tb->skb = NULL;
3596 do {
3597 idx = NEXT_TX(rp, idx);
3598 len -= MAX_TX_DESC_LEN;
3599 } while (len > 0);
3600
3601 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3602 tb = &rp->tx_buffs[idx];
3603 BUG_ON(tb->skb != NULL);
3604 np->ops->unmap_page(np->device, tb->mapping,
3605 skb_shinfo(skb)->frags[i].size,
3606 DMA_TO_DEVICE);
3607 idx = NEXT_TX(rp, idx);
3608 }
3609
3610 dev_kfree_skb(skb);
3611
3612 return idx;
3613}
3614
3615#define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3616
3617static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3618{
b4c21639 3619 struct netdev_queue *txq;
a3138df9 3620 u16 pkt_cnt, tmp;
b4c21639 3621 int cons, index;
a3138df9
DM		 3622 u64 cs;
3623
b4c21639
DM		 3624 index = (rp - np->tx_rings);
3625 txq = netdev_get_tx_queue(np->dev, index);
3626
a3138df9
DM		 3627 cs = rp->tx_cs;
3628 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3629 goto out;
3630
3631 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3632 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3633 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3634
3635 rp->last_pkt_cnt = tmp;
3636
3637 cons = rp->cons;
3638
3639 niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3640 np->dev->name, pkt_cnt, cons);
3641
3642 while (pkt_cnt--)
3643 cons = release_tx_packet(np, rp, cons);
3644
3645 rp->cons = cons;
3646 smp_mb();
3647
3648out:
b4c21639 3649 if (unlikely(netif_tx_queue_stopped(txq) &&
a3138df9 3650 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
b4c21639
DM		 3651 __netif_tx_lock(txq, smp_processor_id());
3652 if (netif_tx_queue_stopped(txq) &&
a3138df9 3653 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
b4c21639
DM		 3654 netif_tx_wake_queue(txq);
3655 __netif_tx_unlock(txq);
a3138df9
DM		 3656 }
3657}
3658
b8a606b8
JDB		 3659static inline void niu_sync_rx_discard_stats(struct niu *np,
3660 struct rx_ring_info *rp,
3661 const int limit)
3662{
3663 /* This elaborate scheme is needed for reading the RX discard
3664 * counters, as they are only 16-bit and can overflow quickly,
3665 * and because the overflow indication bit is not usable as
3666 * the counter value does not wrap, but remains at max value
3667 * 0xFFFF.
3668 *
3669 * In theory and in practice counters can be lost in between
3670 * reading nr64() and clearing the counter nw64(). For this
3671 * reason, the number of counter clearings nw64() is
3672 * limited/reduced though the limit parameter.
3673 */
3674 int rx_channel = rp->rx_channel;
3675 u32 misc, wred;
3676
3677 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3678 * following discard events: IPP (Input Port Process),
3679 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3680 * Block Ring) prefetch buffer is empty.
3681 */
3682 misc = nr64(RXMISC(rx_channel));
3683 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3684 nw64(RXMISC(rx_channel), 0);
3685 rp->rx_errors += misc & RXMISC_COUNT;
3686
3687 if (unlikely(misc & RXMISC_OFLOW))
3688 dev_err(np->device, "rx-%d: Counter overflow "
3689 "RXMISC discard\n", rx_channel);
d231776f
JDB		 3690
3691 niudbg(RX_ERR, "%s-rx-%d: MISC drop=%u over=%u\n",
3692 np->dev->name, rx_channel, misc, misc-limit);
b8a606b8
JDB		 3693 }
3694
3695 /* WRED (Weighted Random Early Discard) by hardware */
3696 wred = nr64(RED_DIS_CNT(rx_channel));
3697 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3698 nw64(RED_DIS_CNT(rx_channel), 0);
3699 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3700
3701 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3702 dev_err(np->device, "rx-%d: Counter overflow "
3703 "WRED discard\n", rx_channel);
d231776f
JDB		 3704
3705 niudbg(RX_ERR, "%s-rx-%d: WRED drop=%u over=%u\n",
3706 np->dev->name, rx_channel, wred, wred-limit);
b8a606b8
JDB		 3707 }
3708}
3709
4099e012
DM		 3710static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3711 struct rx_ring_info *rp, int budget)
a3138df9
DM		 3712{
3713 int qlen, rcr_done = 0, work_done = 0;
3714 struct rxdma_mailbox *mbox = rp->mbox;
3715 u64 stat;
3716
3717#if 1
3718 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3719 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3720#else
3721 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3722 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3723#endif
3724 mbox->rx_dma_ctl_stat = 0;
3725 mbox->rcrstat_a = 0;
3726
3727 niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3728 np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
3729
3730 rcr_done = work_done = 0;
3731 qlen = min(qlen, budget);
3732 while (work_done < qlen) {
4099e012 3733 rcr_done += niu_process_rx_pkt(napi, np, rp);
a3138df9
DM		 3734 work_done++;
3735 }
3736
3737 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3738 unsigned int i;
3739
3740 for (i = 0; i < rp->rbr_refill_pending; i++)
3741 niu_rbr_refill(np, rp, GFP_ATOMIC);
3742 rp->rbr_refill_pending = 0;
3743 }
3744
3745 stat = (RX_DMA_CTL_STAT_MEX |
3746 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3747 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3748
3749 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3750
e98def1f
JDB		 3751 /* Only sync discards stats when qlen indicate potential for drops */
3752 if (qlen > 10)
3753 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
b8a606b8 3754
a3138df9
DM		 3755 return work_done;
3756}
3757
3758static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3759{
3760 u64 v0 = lp->v0;
3761 u32 tx_vec = (v0 >> 32);
3762 u32 rx_vec = (v0 & 0xffffffff);
3763 int i, work_done = 0;
3764
3765 niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
3766 np->dev->name, (unsigned long long) v0);
3767
3768 for (i = 0; i < np->num_tx_rings; i++) {
3769 struct tx_ring_info *rp = &np->tx_rings[i];
3770 if (tx_vec & (1 << rp->tx_channel))
3771 niu_tx_work(np, rp);
3772 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3773 }
3774
3775 for (i = 0; i < np->num_rx_rings; i++) {
3776 struct rx_ring_info *rp = &np->rx_rings[i];
3777
3778 if (rx_vec & (1 << rp->rx_channel)) {
3779 int this_work_done;
3780
4099e012 3781 this_work_done = niu_rx_work(&lp->napi, np, rp,
a3138df9
DM		 3782 budget);
3783
3784 budget -= this_work_done;
3785 work_done += this_work_done;
3786 }
3787 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3788 }
3789
3790 return work_done;
3791}
3792
3793static int niu_poll(struct napi_struct *napi, int budget)
3794{
3795 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3796 struct niu *np = lp->np;
3797 int work_done;
3798
3799 work_done = niu_poll_core(np, lp, budget);
3800
3801 if (work_done < budget) {
288379f0 3802 napi_complete(napi);
a3138df9
DM		 3803 niu_ldg_rearm(np, lp, 1);
3804 }
3805 return work_done;
3806}
3807
3808static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3809 u64 stat)
3810{
3811 dev_err(np->device, PFX "%s: RX channel %u errors ( ",
3812 np->dev->name, rp->rx_channel);
3813
3814 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3815 printk("RBR_TMOUT ");
3816 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3817 printk("RSP_CNT ");
3818 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3819 printk("BYTE_EN_BUS ");
3820 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3821 printk("RSP_DAT ");
3822 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3823 printk("RCR_ACK ");
3824 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3825 printk("RCR_SHA_PAR ");
3826 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3827 printk("RBR_PRE_PAR ");
3828 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3829 printk("CONFIG ");
3830 if (stat & RX_DMA_CTL_STAT_RCRINCON)
3831 printk("RCRINCON ");
3832 if (stat & RX_DMA_CTL_STAT_RCRFULL)
3833 printk("RCRFULL ");
3834 if (stat & RX_DMA_CTL_STAT_RBRFULL)
3835 printk("RBRFULL ");
3836 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3837 printk("RBRLOGPAGE ");
3838 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3839 printk("CFIGLOGPAGE ");
3840 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3841 printk("DC_FIDO ");
3842
3843 printk(")\n");
3844}
3845
3846static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3847{
3848 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3849 int err = 0;
3850
a3138df9
DM		 3851
3852 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3853 RX_DMA_CTL_STAT_PORT_FATAL))
3854 err = -EINVAL;
3855
406f353c
MW		 3856 if (err) {
3857 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
3858 np->dev->name, rp->rx_channel,
3859 (unsigned long long) stat);
3860
3861 niu_log_rxchan_errors(np, rp, stat);
3862 }
3863
a3138df9
DM		 3864 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3865 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3866
3867 return err;
3868}
3869
3870static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3871 u64 cs)
3872{
3873 dev_err(np->device, PFX "%s: TX channel %u errors ( ",
3874 np->dev->name, rp->tx_channel);
3875
3876 if (cs & TX_CS_MBOX_ERR)
3877 printk("MBOX ");
3878 if (cs & TX_CS_PKT_SIZE_ERR)
3879 printk("PKT_SIZE ");
3880 if (cs & TX_CS_TX_RING_OFLOW)
3881 printk("TX_RING_OFLOW ");
3882 if (cs & TX_CS_PREF_BUF_PAR_ERR)
3883 printk("PREF_BUF_PAR ");
3884 if (cs & TX_CS_NACK_PREF)
3885 printk("NACK_PREF ");
3886 if (cs & TX_CS_NACK_PKT_RD)
3887 printk("NACK_PKT_RD ");
3888 if (cs & TX_CS_CONF_PART_ERR)
3889 printk("CONF_PART ");
3890 if (cs & TX_CS_PKT_PRT_ERR)
3891 printk("PKT_PTR ");
3892
3893 printk(")\n");
3894}
3895
3896static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3897{
3898 u64 cs, logh, logl;
3899
3900 cs = nr64(TX_CS(rp->tx_channel));
3901 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3902 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3903
3904 dev_err(np->device, PFX "%s: TX channel %u error, "
3905 "cs[%llx] logh[%llx] logl[%llx]\n",
3906 np->dev->name, rp->tx_channel,
3907 (unsigned long long) cs,
3908 (unsigned long long) logh,
3909 (unsigned long long) logl);
3910
3911 niu_log_txchan_errors(np, rp, cs);
3912
3913 return -ENODEV;
3914}
3915
3916static int niu_mif_interrupt(struct niu *np)
3917{
3918 u64 mif_status = nr64(MIF_STATUS);
3919 int phy_mdint = 0;
3920
3921 if (np->flags & NIU_FLAGS_XMAC) {
3922 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3923
3924 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3925 phy_mdint = 1;
3926 }
3927
3928 dev_err(np->device, PFX "%s: MIF interrupt, "
3929 "stat[%llx] phy_mdint(%d)\n",
3930 np->dev->name, (unsigned long long) mif_status, phy_mdint);
3931
3932 return -ENODEV;
3933}
3934
3935static void niu_xmac_interrupt(struct niu *np)
3936{
3937 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3938 u64 val;
3939
3940 val = nr64_mac(XTXMAC_STATUS);
3941 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3942 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3943 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3944 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3945 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3946 mp->tx_fifo_errors++;
3947 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3948 mp->tx_overflow_errors++;
3949 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3950 mp->tx_max_pkt_size_errors++;
3951 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3952 mp->tx_underflow_errors++;
3953
3954 val = nr64_mac(XRXMAC_STATUS);
3955 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3956 mp->rx_local_faults++;
3957 if (val & XRXMAC_STATUS_RFLT_DET)
3958 mp->rx_remote_faults++;
3959 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3960 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3961 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3962 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3963 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3964 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3965 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3966 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3967 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3968 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3969 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3970 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3971 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3972 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3973 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3974 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3975 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3976 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3977 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3978 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3979 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3980 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3981 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3982 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3983 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3984 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3985 if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
3986 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3987 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3988 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3989 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3990 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3991 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3992 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3993 if (val & XRXMAC_STATUS_RXUFLOW)
3994 mp->rx_underflows++;
3995 if (val & XRXMAC_STATUS_RXOFLOW)
3996 mp->rx_overflows++;
3997
3998 val = nr64_mac(XMAC_FC_STAT);
3999 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
4000 mp->pause_off_state++;
4001 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
4002 mp->pause_on_state++;
4003 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4004 mp->pause_received++;
4005}
4006
4007static void niu_bmac_interrupt(struct niu *np)
4008{
4009 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4010 u64 val;
4011
4012 val = nr64_mac(BTXMAC_STATUS);
4013 if (val & BTXMAC_STATUS_UNDERRUN)
4014 mp->tx_underflow_errors++;
4015 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4016 mp->tx_max_pkt_size_errors++;
4017 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4018 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4019 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4020 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4021
4022 val = nr64_mac(BRXMAC_STATUS);
4023 if (val & BRXMAC_STATUS_OVERFLOW)
4024 mp->rx_overflows++;
4025 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4026 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4027 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4028 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4029 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4030 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4031 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4032 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4033
4034 val = nr64_mac(BMAC_CTRL_STATUS);
4035 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4036 mp->pause_off_state++;
4037 if (val & BMAC_CTRL_STATUS_PAUSE)
4038 mp->pause_on_state++;
4039 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4040 mp->pause_received++;
4041}
4042
4043static int niu_mac_interrupt(struct niu *np)
4044{
4045 if (np->flags & NIU_FLAGS_XMAC)
4046 niu_xmac_interrupt(np);
4047 else
4048 niu_bmac_interrupt(np);
4049
4050 return 0;
4051}
4052
4053static void niu_log_device_error(struct niu *np, u64 stat)
4054{
4055 dev_err(np->device, PFX "%s: Core device errors ( ",
4056 np->dev->name);
4057
4058 if (stat & SYS_ERR_MASK_META2)
4059 printk("META2 ");
4060 if (stat & SYS_ERR_MASK_META1)
4061 printk("META1 ");
4062 if (stat & SYS_ERR_MASK_PEU)
4063 printk("PEU ");
4064 if (stat & SYS_ERR_MASK_TXC)
4065 printk("TXC ");
4066 if (stat & SYS_ERR_MASK_RDMC)
4067 printk("RDMC ");
4068 if (stat & SYS_ERR_MASK_TDMC)
4069 printk("TDMC ");
4070 if (stat & SYS_ERR_MASK_ZCP)
4071 printk("ZCP ");
4072 if (stat & SYS_ERR_MASK_FFLP)
4073 printk("FFLP ");
4074 if (stat & SYS_ERR_MASK_IPP)
4075 printk("IPP ");
4076 if (stat & SYS_ERR_MASK_MAC)
4077 printk("MAC ");
4078 if (stat & SYS_ERR_MASK_SMX)
4079 printk("SMX ");
4080
4081 printk(")\n");
4082}
4083
4084static int niu_device_error(struct niu *np)
4085{
4086 u64 stat = nr64(SYS_ERR_STAT);
4087
4088 dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
4089 np->dev->name, (unsigned long long) stat);
4090
4091 niu_log_device_error(np, stat);
4092
4093 return -ENODEV;
4094}
4095
406f353c
MW		 4096static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4097 u64 v0, u64 v1, u64 v2)
a3138df9 4098{
406f353c 4099
a3138df9
DM		 4100 int i, err = 0;
4101
406f353c
MW		 4102 lp->v0 = v0;
4103 lp->v1 = v1;
4104 lp->v2 = v2;
4105
a3138df9
DM		 4106 if (v1 & 0x00000000ffffffffULL) {
4107 u32 rx_vec = (v1 & 0xffffffff);
4108
4109 for (i = 0; i < np->num_rx_rings; i++) {
4110 struct rx_ring_info *rp = &np->rx_rings[i];
4111
4112 if (rx_vec & (1 << rp->rx_channel)) {
4113 int r = niu_rx_error(np, rp);
406f353c 4114 if (r) {
a3138df9 4115 err = r;
406f353c
MW		 4116 } else {
4117 if (!v0)
4118 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4119 RX_DMA_CTL_STAT_MEX);
4120 }
a3138df9
DM		 4121 }
4122 }
4123 }
4124 if (v1 & 0x7fffffff00000000ULL) {
4125 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4126
4127 for (i = 0; i < np->num_tx_rings; i++) {
4128 struct tx_ring_info *rp = &np->tx_rings[i];
4129
4130 if (tx_vec & (1 << rp->tx_channel)) {
4131 int r = niu_tx_error(np, rp);
4132 if (r)
4133 err = r;
4134 }
4135 }
4136 }
4137 if ((v0 | v1) & 0x8000000000000000ULL) {
4138 int r = niu_mif_interrupt(np);
4139 if (r)
4140 err = r;
4141 }
4142 if (v2) {
4143 if (v2 & 0x01ef) {
4144 int r = niu_mac_interrupt(np);
4145 if (r)
4146 err = r;
4147 }
4148 if (v2 & 0x0210) {
4149 int r = niu_device_error(np);
4150 if (r)
4151 err = r;
4152 }
4153 }
4154
4155 if (err)
4156 niu_enable_interrupts(np, 0);
4157
406f353c 4158 return err;
a3138df9
DM		 4159}
4160
4161static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4162 int ldn)
4163{
4164 struct rxdma_mailbox *mbox = rp->mbox;
4165 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4166
4167 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4168 RX_DMA_CTL_STAT_RCRTO);
4169 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4170
4171 niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
4172 np->dev->name, (unsigned long long) stat);
4173}
4174
4175static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4176 int ldn)
4177{
4178 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4179
4180 niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
4181 np->dev->name, (unsigned long long) rp->tx_cs);
4182}
4183
4184static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4185{
4186 struct niu_parent *parent = np->parent;
4187 u32 rx_vec, tx_vec;
4188 int i;
4189
4190 tx_vec = (v0 >> 32);
4191 rx_vec = (v0 & 0xffffffff);
4192
4193 for (i = 0; i < np->num_rx_rings; i++) {
4194 struct rx_ring_info *rp = &np->rx_rings[i];
4195 int ldn = LDN_RXDMA(rp->rx_channel);
4196
4197 if (parent->ldg_map[ldn] != ldg)
4198 continue;
4199
4200 nw64(LD_IM0(ldn), LD_IM0_MASK);
4201 if (rx_vec & (1 << rp->rx_channel))
4202 niu_rxchan_intr(np, rp, ldn);
4203 }
4204
4205 for (i = 0; i < np->num_tx_rings; i++) {
4206 struct tx_ring_info *rp = &np->tx_rings[i];
4207 int ldn = LDN_TXDMA(rp->tx_channel);
4208
4209 if (parent->ldg_map[ldn] != ldg)
4210 continue;
4211
4212 nw64(LD_IM0(ldn), LD_IM0_MASK);
4213 if (tx_vec & (1 << rp->tx_channel))
4214 niu_txchan_intr(np, rp, ldn);
4215 }
4216}
4217
4218static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4219 u64 v0, u64 v1, u64 v2)
4220{
288379f0 4221 if (likely(napi_schedule_prep(&lp->napi))) {
a3138df9
DM		 4222 lp->v0 = v0;
4223 lp->v1 = v1;
4224 lp->v2 = v2;
4225 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
288379f0 4226 __napi_schedule(&lp->napi);
a3138df9
DM		 4227 }
4228}
4229
4230static irqreturn_t niu_interrupt(int irq, void *dev_id)
4231{
4232 struct niu_ldg *lp = dev_id;
4233 struct niu *np = lp->np;
4234 int ldg = lp->ldg_num;
4235 unsigned long flags;
4236 u64 v0, v1, v2;
4237
4238 if (netif_msg_intr(np))
4239 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
4240 lp, ldg);
4241
4242 spin_lock_irqsave(&np->lock, flags);
4243
4244 v0 = nr64(LDSV0(ldg));
4245 v1 = nr64(LDSV1(ldg));
4246 v2 = nr64(LDSV2(ldg));
4247
4248 if (netif_msg_intr(np))
4249 printk("v0[%llx] v1[%llx] v2[%llx]\n",
4250 (unsigned long long) v0,
4251 (unsigned long long) v1,
4252 (unsigned long long) v2);
4253
4254 if (unlikely(!v0 && !v1 && !v2)) {
4255 spin_unlock_irqrestore(&np->lock, flags);
4256 return IRQ_NONE;
4257 }
4258
4259 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
406f353c 4260 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
a3138df9
DM		 4261 if (err)
4262 goto out;
4263 }
4264 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4265 niu_schedule_napi(np, lp, v0, v1, v2);
4266 else
4267 niu_ldg_rearm(np, lp, 1);
4268out:
4269 spin_unlock_irqrestore(&np->lock, flags);
4270
4271 return IRQ_HANDLED;
4272}
4273
4274static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4275{
4276 if (rp->mbox) {
4277 np->ops->free_coherent(np->device,
4278 sizeof(struct rxdma_mailbox),
4279 rp->mbox, rp->mbox_dma);
4280 rp->mbox = NULL;
4281 }
4282 if (rp->rcr) {
4283 np->ops->free_coherent(np->device,
4284 MAX_RCR_RING_SIZE * sizeof(__le64),
4285 rp->rcr, rp->rcr_dma);
4286 rp->rcr = NULL;
4287 rp->rcr_table_size = 0;
4288 rp->rcr_index = 0;
4289 }
4290 if (rp->rbr) {
4291 niu_rbr_free(np, rp);
4292
4293 np->ops->free_coherent(np->device,
4294 MAX_RBR_RING_SIZE * sizeof(__le32),
4295 rp->rbr, rp->rbr_dma);
4296 rp->rbr = NULL;
4297 rp->rbr_table_size = 0;
4298 rp->rbr_index = 0;
4299 }
4300 kfree(rp->rxhash);
4301 rp->rxhash = NULL;
4302}
4303
4304static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4305{
4306 if (rp->mbox) {
4307 np->ops->free_coherent(np->device,
4308 sizeof(struct txdma_mailbox),
4309 rp->mbox, rp->mbox_dma);
4310 rp->mbox = NULL;
4311 }
4312 if (rp->descr) {
4313 int i;
4314
4315 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4316 if (rp->tx_buffs[i].skb)
4317 (void) release_tx_packet(np, rp, i);
4318 }
4319
4320 np->ops->free_coherent(np->device,
4321 MAX_TX_RING_SIZE * sizeof(__le64),
4322 rp->descr, rp->descr_dma);
4323 rp->descr = NULL;
4324 rp->pending = 0;
4325 rp->prod = 0;
4326 rp->cons = 0;
4327 rp->wrap_bit = 0;
4328 }
4329}
4330
4331static void niu_free_channels(struct niu *np)
4332{
4333 int i;
4334
4335 if (np->rx_rings) {
4336 for (i = 0; i < np->num_rx_rings; i++) {
4337 struct rx_ring_info *rp = &np->rx_rings[i];
4338
4339 niu_free_rx_ring_info(np, rp);
4340 }
4341 kfree(np->rx_rings);
4342 np->rx_rings = NULL;
4343 np->num_rx_rings = 0;
4344 }
4345
4346 if (np->tx_rings) {
4347 for (i = 0; i < np->num_tx_rings; i++) {
4348 struct tx_ring_info *rp = &np->tx_rings[i];
4349
4350 niu_free_tx_ring_info(np, rp);
4351 }
4352 kfree(np->tx_rings);
4353 np->tx_rings = NULL;
4354 np->num_tx_rings = 0;
4355 }
4356}
4357
4358static int niu_alloc_rx_ring_info(struct niu *np,
4359 struct rx_ring_info *rp)
4360{
4361 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4362
4363 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4364 GFP_KERNEL);
4365 if (!rp->rxhash)
4366 return -ENOMEM;
4367
4368 rp->mbox = np->ops->alloc_coherent(np->device,
4369 sizeof(struct rxdma_mailbox),
4370 &rp->mbox_dma, GFP_KERNEL);
4371 if (!rp->mbox)
4372 return -ENOMEM;
4373 if ((unsigned long)rp->mbox & (64UL - 1)) {
4374 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4375 "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
4376 return -EINVAL;
4377 }
4378
4379 rp->rcr = np->ops->alloc_coherent(np->device,
4380 MAX_RCR_RING_SIZE * sizeof(__le64),
4381 &rp->rcr_dma, GFP_KERNEL);
4382 if (!rp->rcr)
4383 return -ENOMEM;
4384 if ((unsigned long)rp->rcr & (64UL - 1)) {
4385 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4386 "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
4387 return -EINVAL;
4388 }
4389 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4390 rp->rcr_index = 0;
4391
4392 rp->rbr = np->ops->alloc_coherent(np->device,
4393 MAX_RBR_RING_SIZE * sizeof(__le32),
4394 &rp->rbr_dma, GFP_KERNEL);
4395 if (!rp->rbr)
4396 return -ENOMEM;
4397 if ((unsigned long)rp->rbr & (64UL - 1)) {
4398 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4399 "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
4400 return -EINVAL;
4401 }
4402 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4403 rp->rbr_index = 0;
4404 rp->rbr_pending = 0;
4405
4406 return 0;
4407}
4408
4409static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4410{
4411 int mtu = np->dev->mtu;
4412
4413 /* These values are recommended by the HW designers for fair
4414 * utilization of DRR amongst the rings.
4415 */
4416 rp->max_burst = mtu + 32;
4417 if (rp->max_burst > 4096)
4418 rp->max_burst = 4096;
4419}
4420
4421static int niu_alloc_tx_ring_info(struct niu *np,
4422 struct tx_ring_info *rp)
4423{
4424 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4425
4426 rp->mbox = np->ops->alloc_coherent(np->device,
4427 sizeof(struct txdma_mailbox),
4428 &rp->mbox_dma, GFP_KERNEL);
4429 if (!rp->mbox)
4430 return -ENOMEM;
4431 if ((unsigned long)rp->mbox & (64UL - 1)) {
4432 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4433 "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
4434 return -EINVAL;
4435 }
4436
4437 rp->descr = np->ops->alloc_coherent(np->device,
4438 MAX_TX_RING_SIZE * sizeof(__le64),
4439 &rp->descr_dma, GFP_KERNEL);
4440 if (!rp->descr)
4441 return -ENOMEM;
4442 if ((unsigned long)rp->descr & (64UL - 1)) {
4443 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4444 "TXDMA descr table %p\n", np->dev->name, rp->descr);
4445 return -EINVAL;
4446 }
4447
4448 rp->pending = MAX_TX_RING_SIZE;
4449 rp->prod = 0;
4450 rp->cons = 0;
4451 rp->wrap_bit = 0;
4452
4453 /* XXX make these configurable... XXX */
4454 rp->mark_freq = rp->pending / 4;
4455
4456 niu_set_max_burst(np, rp);
4457
4458 return 0;
4459}
4460
4461static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4462{
81429973 4463 u16 bss;
a3138df9 4464
81429973 4465 bss = min(PAGE_SHIFT, 15);
a3138df9 4466
81429973
OJ		 4467 rp->rbr_block_size = 1 << bss;
4468 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
a3138df9
DM		 4469
4470 rp->rbr_sizes[0] = 256;
4471 rp->rbr_sizes[1] = 1024;
4472 if (np->dev->mtu > ETH_DATA_LEN) {
4473 switch (PAGE_SIZE) {
4474 case 4 * 1024:
4475 rp->rbr_sizes[2] = 4096;
4476 break;
4477
4478 default:
4479 rp->rbr_sizes[2] = 8192;
4480 break;
4481 }
4482 } else {
4483 rp->rbr_sizes[2] = 2048;
4484 }
4485 rp->rbr_sizes[3] = rp->rbr_block_size;
4486}
4487
4488static int niu_alloc_channels(struct niu *np)
4489{
4490 struct niu_parent *parent = np->parent;
4491 int first_rx_channel, first_tx_channel;
4492 int i, port, err;
4493
4494 port = np->port;
4495 first_rx_channel = first_tx_channel = 0;
4496 for (i = 0; i < port; i++) {
4497 first_rx_channel += parent->rxchan_per_port[i];
4498 first_tx_channel += parent->txchan_per_port[i];
4499 }
4500
4501 np->num_rx_rings = parent->rxchan_per_port[port];
4502 np->num_tx_rings = parent->txchan_per_port[port];
4503
b4c21639
DM		 4504 np->dev->real_num_tx_queues = np->num_tx_rings;
4505
a3138df9
DM		 4506 np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4507 GFP_KERNEL);
4508 err = -ENOMEM;
4509 if (!np->rx_rings)
4510 goto out_err;
4511
4512 for (i = 0; i < np->num_rx_rings; i++) {
4513 struct rx_ring_info *rp = &np->rx_rings[i];
4514
4515 rp->np = np;
4516 rp->rx_channel = first_rx_channel + i;
4517
4518 err = niu_alloc_rx_ring_info(np, rp);
4519 if (err)
4520 goto out_err;
4521
4522 niu_size_rbr(np, rp);
4523
4524 /* XXX better defaults, configurable, etc... XXX */
4525 rp->nonsyn_window = 64;
4526 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4527 rp->syn_window = 64;
4528 rp->syn_threshold = rp->rcr_table_size - 64;
4529 rp->rcr_pkt_threshold = 16;
4530 rp->rcr_timeout = 8;
4531 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4532 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4533 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4534
4535 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4536 if (err)
4537 return err;
4538 }
4539
4540 np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4541 GFP_KERNEL);
4542 err = -ENOMEM;
4543 if (!np->tx_rings)
4544 goto out_err;
4545
4546 for (i = 0; i < np->num_tx_rings; i++) {
4547 struct tx_ring_info *rp = &np->tx_rings[i];
4548
4549 rp->np = np;
4550 rp->tx_channel = first_tx_channel + i;
4551
4552 err = niu_alloc_tx_ring_info(np, rp);
4553 if (err)
4554 goto out_err;
4555 }
4556
4557 return 0;
4558
4559out_err:
4560 niu_free_channels(np);
4561 return err;
4562}
4563
4564static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4565{
4566 int limit = 1000;
4567
4568 while (--limit > 0) {
4569 u64 val = nr64(TX_CS(channel));
4570 if (val & TX_CS_SNG_STATE)
4571 return 0;
4572 }
4573 return -ENODEV;
4574}
4575
4576static int niu_tx_channel_stop(struct niu *np, int channel)
4577{
4578 u64 val = nr64(TX_CS(channel));
4579
4580 val |= TX_CS_STOP_N_GO;
4581 nw64(TX_CS(channel), val);
4582
4583 return niu_tx_cs_sng_poll(np, channel);
4584}
4585
4586static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4587{
4588 int limit = 1000;
4589
4590 while (--limit > 0) {
4591 u64 val = nr64(TX_CS(channel));
4592 if (!(val & TX_CS_RST))
4593 return 0;
4594 }
4595 return -ENODEV;
4596}
4597
4598static int niu_tx_channel_reset(struct niu *np, int channel)
4599{
4600 u64 val = nr64(TX_CS(channel));
4601 int err;
4602
4603 val |= TX_CS_RST;
4604 nw64(TX_CS(channel), val);
4605
4606 err = niu_tx_cs_reset_poll(np, channel);
4607 if (!err)
4608 nw64(TX_RING_KICK(channel), 0);
4609
4610 return err;
4611}
4612
4613static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4614{
4615 u64 val;
4616
4617 nw64(TX_LOG_MASK1(channel), 0);
4618 nw64(TX_LOG_VAL1(channel), 0);
4619 nw64(TX_LOG_MASK2(channel), 0);
4620 nw64(TX_LOG_VAL2(channel), 0);
4621 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4622 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4623 nw64(TX_LOG_PAGE_HDL(channel), 0);
4624
4625 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4626 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4627 nw64(TX_LOG_PAGE_VLD(channel), val);
4628
4629 /* XXX TXDMA 32bit mode? XXX */
4630
4631 return 0;
4632}
4633
4634static void niu_txc_enable_port(struct niu *np, int on)
4635{
4636 unsigned long flags;
4637 u64 val, mask;
4638
4639 niu_lock_parent(np, flags);
4640 val = nr64(TXC_CONTROL);
4641 mask = (u64)1 << np->port;
4642 if (on) {
4643 val |= TXC_CONTROL_ENABLE | mask;
4644 } else {
4645 val &= ~mask;
4646 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4647 val &= ~TXC_CONTROL_ENABLE;
4648 }
4649 nw64(TXC_CONTROL, val);
4650 niu_unlock_parent(np, flags);
4651}
4652
4653static void niu_txc_set_imask(struct niu *np, u64 imask)
4654{
4655 unsigned long flags;
4656 u64 val;
4657
4658 niu_lock_parent(np, flags);
4659 val = nr64(TXC_INT_MASK);
4660 val &= ~TXC_INT_MASK_VAL(np->port);
4661 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4662 niu_unlock_parent(np, flags);
4663}
4664
4665static void niu_txc_port_dma_enable(struct niu *np, int on)
4666{
4667 u64 val = 0;
4668
4669 if (on) {
4670 int i;
4671
4672 for (i = 0; i < np->num_tx_rings; i++)
4673 val |= (1 << np->tx_rings[i].tx_channel);
4674 }
4675 nw64(TXC_PORT_DMA(np->port), val);
4676}
4677
4678static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4679{
4680 int err, channel = rp->tx_channel;
4681 u64 val, ring_len;
4682
4683 err = niu_tx_channel_stop(np, channel);
4684 if (err)
4685 return err;
4686
4687 err = niu_tx_channel_reset(np, channel);
4688 if (err)
4689 return err;
4690
4691 err = niu_tx_channel_lpage_init(np, channel);
4692 if (err)
4693 return err;
4694
4695 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4696 nw64(TX_ENT_MSK(channel), 0);
4697
4698 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4699 TX_RNG_CFIG_STADDR)) {
4700 dev_err(np->device, PFX "%s: TX ring channel %d "
4701 "DMA addr (%llx) is not aligned.\n",
4702 np->dev->name, channel,
4703 (unsigned long long) rp->descr_dma);
4704 return -EINVAL;
4705 }
4706
4707 /* The length field in TX_RNG_CFIG is measured in 64-byte
4708 * blocks. rp->pending is the number of TX descriptors in
4709 * our ring, 8 bytes each, thus we divide by 8 bytes more
4710 * to get the proper value the chip wants.
4711 */
4712 ring_len = (rp->pending / 8);
4713
4714 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4715 rp->descr_dma);
4716 nw64(TX_RNG_CFIG(channel), val);
4717
4718 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4719 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4720 dev_err(np->device, PFX "%s: TX ring channel %d "
4721 "MBOX addr (%llx) is has illegal bits.\n",
4722 np->dev->name, channel,
4723 (unsigned long long) rp->mbox_dma);
4724 return -EINVAL;
4725 }
4726 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4727 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4728
4729 nw64(TX_CS(channel), 0);
4730
4731 rp->last_pkt_cnt = 0;
4732
4733 return 0;
4734}
4735
4736static void niu_init_rdc_groups(struct niu *np)
4737{
4738 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4739 int i, first_table_num = tp->first_table_num;
4740
4741 for (i = 0; i < tp->num_tables; i++) {
4742 struct rdc_table *tbl = &tp->tables[i];
4743 int this_table = first_table_num + i;
4744 int slot;
4745
4746 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4747 nw64(RDC_TBL(this_table, slot),
4748 tbl->rxdma_channel[slot]);
4749 }
4750
4751 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4752}
4753
4754static void niu_init_drr_weight(struct niu *np)
4755{
4756 int type = phy_decode(np->parent->port_phy, np->port);
4757 u64 val;
4758
4759 switch (type) {
4760 case PORT_TYPE_10G:
4761 val = PT_DRR_WEIGHT_DEFAULT_10G;
4762 break;
4763
4764 case PORT_TYPE_1G:
4765 default:
4766 val = PT_DRR_WEIGHT_DEFAULT_1G;
4767 break;
4768 }
4769 nw64(PT_DRR_WT(np->port), val);
4770}
4771
4772static int niu_init_hostinfo(struct niu *np)
4773{
4774 struct niu_parent *parent = np->parent;
4775 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4776 int i, err, num_alt = niu_num_alt_addr(np);
4777 int first_rdc_table = tp->first_table_num;
4778
4779 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4780 if (err)
4781 return err;
4782
4783 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4784 if (err)
4785 return err;
4786
4787 for (i = 0; i < num_alt; i++) {
4788 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4789 if (err)
4790 return err;
4791 }
4792
4793 return 0;
4794}
4795
4796static int niu_rx_channel_reset(struct niu *np, int channel)
4797{
4798 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4799 RXDMA_CFIG1_RST, 1000, 10,
4800 "RXDMA_CFIG1");
4801}
4802
4803static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4804{
4805 u64 val;
4806
4807 nw64(RX_LOG_MASK1(channel), 0);
4808 nw64(RX_LOG_VAL1(channel), 0);
4809 nw64(RX_LOG_MASK2(channel), 0);
4810 nw64(RX_LOG_VAL2(channel), 0);
4811 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4812 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4813 nw64(RX_LOG_PAGE_HDL(channel), 0);
4814
4815 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4816 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4817 nw64(RX_LOG_PAGE_VLD(channel), val);
4818
4819 return 0;
4820}
4821
4822static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4823{
4824 u64 val;
4825
4826 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4827 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4828 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4829 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4830 nw64(RDC_RED_PARA(rp->rx_channel), val);
4831}
4832
4833static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4834{
4835 u64 val = 0;
4836
4837 switch (rp->rbr_block_size) {
4838 case 4 * 1024:
4839 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4840 break;
4841 case 8 * 1024:
4842 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4843 break;
4844 case 16 * 1024:
4845 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4846 break;
4847 case 32 * 1024:
4848 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4849 break;
4850 default:
4851 return -EINVAL;
4852 }
4853 val |= RBR_CFIG_B_VLD2;
4854 switch (rp->rbr_sizes[2]) {
4855 case 2 * 1024:
4856 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4857 break;
4858 case 4 * 1024:
4859 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4860 break;
4861 case 8 * 1024:
4862 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4863 break;
4864 case 16 * 1024:
4865 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4866 break;
4867
4868 default:
4869 return -EINVAL;
4870 }
4871 val |= RBR_CFIG_B_VLD1;
4872 switch (rp->rbr_sizes[1]) {
4873 case 1 * 1024:
4874 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4875 break;
4876 case 2 * 1024:
4877 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4878 break;
4879 case 4 * 1024:
4880 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4881 break;
4882 case 8 * 1024:
4883 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4884 break;
4885
4886 default:
4887 return -EINVAL;
4888 }
4889 val |= RBR_CFIG_B_VLD0;
4890 switch (rp->rbr_sizes[0]) {
4891 case 256:
4892 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4893 break;
4894 case 512:
4895 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4896 break;
4897 case 1 * 1024:
4898 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4899 break;
4900 case 2 * 1024:
4901 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4902 break;
4903
4904 default:
4905 return -EINVAL;
4906 }
4907
4908 *ret = val;
4909 return 0;
4910}
4911
4912static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4913{
4914 u64 val = nr64(RXDMA_CFIG1(channel));
4915 int limit;
4916
4917 if (on)
4918 val |= RXDMA_CFIG1_EN;
4919 else
4920 val &= ~RXDMA_CFIG1_EN;
4921 nw64(RXDMA_CFIG1(channel), val);
4922
4923 limit = 1000;
4924 while (--limit > 0) {
4925 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4926 break;
4927 udelay(10);
4928 }
4929 if (limit <= 0)
4930 return -ENODEV;
4931 return 0;
4932}
4933
4934static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4935{
4936 int err, channel = rp->rx_channel;
4937 u64 val;
4938
4939 err = niu_rx_channel_reset(np, channel);
4940 if (err)
4941 return err;
4942
4943 err = niu_rx_channel_lpage_init(np, channel);
4944 if (err)
4945 return err;
4946
4947 niu_rx_channel_wred_init(np, rp);
4948
4949 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4950 nw64(RX_DMA_CTL_STAT(channel),
4951 (RX_DMA_CTL_STAT_MEX |
4952 RX_DMA_CTL_STAT_RCRTHRES |
4953 RX_DMA_CTL_STAT_RCRTO |
4954 RX_DMA_CTL_STAT_RBR_EMPTY));
4955 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4956 nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4957 nw64(RBR_CFIG_A(channel),
4958 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4959 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4960 err = niu_compute_rbr_cfig_b(rp, &val);
4961 if (err)
4962 return err;
4963 nw64(RBR_CFIG_B(channel), val);
4964 nw64(RCRCFIG_A(channel),
4965 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4966 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4967 nw64(RCRCFIG_B(channel),
4968 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4969 RCRCFIG_B_ENTOUT |
4970 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4971
4972 err = niu_enable_rx_channel(np, channel, 1);
4973 if (err)
4974 return err;
4975
4976 nw64(RBR_KICK(channel), rp->rbr_index);
4977
4978 val = nr64(RX_DMA_CTL_STAT(channel));
4979 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4980 nw64(RX_DMA_CTL_STAT(channel), val);
4981
4982 return 0;
4983}
4984
4985static int niu_init_rx_channels(struct niu *np)
4986{
4987 unsigned long flags;
4988 u64 seed = jiffies_64;
4989 int err, i;
4990
4991 niu_lock_parent(np, flags);
4992 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4993 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4994 niu_unlock_parent(np, flags);
4995
4996 /* XXX RXDMA 32bit mode? XXX */
4997
4998 niu_init_rdc_groups(np);
4999 niu_init_drr_weight(np);
5000
5001 err = niu_init_hostinfo(np);
5002 if (err)
5003 return err;
5004
5005 for (i = 0; i < np->num_rx_rings; i++) {
5006 struct rx_ring_info *rp = &np->rx_rings[i];
5007
5008 err = niu_init_one_rx_channel(np, rp);
5009 if (err)
5010 return err;
5011 }
5012
5013 return 0;
5014}
5015
5016static int niu_set_ip_frag_rule(struct niu *np)
5017{
5018 struct niu_parent *parent = np->parent;
5019 struct niu_classifier *cp = &np->clas;
5020 struct niu_tcam_entry *tp;
5021 int index, err;
5022
2d96cf8c 5023 index = cp->tcam_top;
a3138df9
DM		 5024 tp = &parent->tcam[index];
5025
5026 /* Note that the noport bit is the same in both ipv4 and
5027 * ipv6 format TCAM entries.
5028 */
5029 memset(tp, 0, sizeof(*tp));
5030 tp->key[1] = TCAM_V4KEY1_NOPORT;
5031 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5032 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5033 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5034 err = tcam_write(np, index, tp->key, tp->key_mask);
5035 if (err)
5036 return err;
5037 err = tcam_assoc_write(np, index, tp->assoc_data);
5038 if (err)
5039 return err;
2d96cf8c
SB		 5040 tp->valid = 1;
5041 cp->tcam_valid_entries++;
a3138df9
DM		 5042
5043 return 0;
5044}
5045
5046static int niu_init_classifier_hw(struct niu *np)
5047{
5048 struct niu_parent *parent = np->parent;
5049 struct niu_classifier *cp = &np->clas;
5050 int i, err;
5051
5052 nw64(H1POLY, cp->h1_init);
5053 nw64(H2POLY, cp->h2_init);
5054
5055 err = niu_init_hostinfo(np);
5056 if (err)
5057 return err;
5058
5059 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5060 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5061
5062 vlan_tbl_write(np, i, np->port,
5063 vp->vlan_pref, vp->rdc_num);
5064 }
5065
5066 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5067 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5068
5069 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5070 ap->rdc_num, ap->mac_pref);
5071 if (err)
5072 return err;
5073 }
5074
5075 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5076 int index = i - CLASS_CODE_USER_PROG1;
5077
5078 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5079 if (err)
5080 return err;
5081 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5082 if (err)
5083 return err;
5084 }
5085
5086 err = niu_set_ip_frag_rule(np);
5087 if (err)
5088 return err;
5089
5090 tcam_enable(np, 1);
5091
5092 return 0;
5093}
5094
5095static int niu_zcp_write(struct niu *np, int index, u64 *data)
5096{
5097 nw64(ZCP_RAM_DATA0, data[0]);
5098 nw64(ZCP_RAM_DATA1, data[1]);
5099 nw64(ZCP_RAM_DATA2, data[2]);
5100 nw64(ZCP_RAM_DATA3, data[3]);
5101 nw64(ZCP_RAM_DATA4, data[4]);
5102 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5103 nw64(ZCP_RAM_ACC,
5104 (ZCP_RAM_ACC_WRITE |
5105 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5106 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5107
5108 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5109 1000, 100);
5110}
5111
5112static int niu_zcp_read(struct niu *np, int index, u64 *data)
5113{
5114 int err;
5115
5116 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5117 1000, 100);
5118 if (err) {
5119 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
5120 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
5121 (unsigned long long) nr64(ZCP_RAM_ACC));
5122 return err;
5123 }
5124
5125 nw64(ZCP_RAM_ACC,
5126 (ZCP_RAM_ACC_READ |
5127 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5128 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5129
5130 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5131 1000, 100);
5132 if (err) {
5133 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
5134 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
5135 (unsigned long long) nr64(ZCP_RAM_ACC));
5136 return err;
5137 }
5138
5139 data[0] = nr64(ZCP_RAM_DATA0);
5140 data[1] = nr64(ZCP_RAM_DATA1);
5141 data[2] = nr64(ZCP_RAM_DATA2);
5142 data[3] = nr64(ZCP_RAM_DATA3);
5143 data[4] = nr64(ZCP_RAM_DATA4);
5144
5145 return 0;
5146}
5147
5148static void niu_zcp_cfifo_reset(struct niu *np)
5149{
5150 u64 val = nr64(RESET_CFIFO);
5151
5152 val |= RESET_CFIFO_RST(np->port);
5153 nw64(RESET_CFIFO, val);
5154 udelay(10);
5155
5156 val &= ~RESET_CFIFO_RST(np->port);
5157 nw64(RESET_CFIFO, val);
5158}
5159
5160static int niu_init_zcp(struct niu *np)
5161{
5162 u64 data[5], rbuf[5];
5163 int i, max, err;
5164
5165 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5166 if (np->port == 0 || np->port == 1)
5167 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5168 else
5169 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5170 } else
5171 max = NIU_CFIFO_ENTRIES;
5172
5173 data[0] = 0;
5174 data[1] = 0;
5175 data[2] = 0;
5176 data[3] = 0;
5177 data[4] = 0;
5178
5179 for (i = 0; i < max; i++) {
5180 err = niu_zcp_write(np, i, data);
5181 if (err)
5182 return err;
5183 err = niu_zcp_read(np, i, rbuf);
5184 if (err)
5185 return err;
5186 }
5187
5188 niu_zcp_cfifo_reset(np);
5189 nw64(CFIFO_ECC(np->port), 0);
5190 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5191 (void) nr64(ZCP_INT_STAT);
5192 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5193
5194 return 0;
5195}
5196
5197static void niu_ipp_write(struct niu *np, int index, u64 *data)
5198{
5199 u64 val = nr64_ipp(IPP_CFIG);
5200
5201 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5202 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5203 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5204 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5205 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5206 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5207 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5208 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5209}
5210
5211static void niu_ipp_read(struct niu *np, int index, u64 *data)
5212{
5213 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5214 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5215 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5216 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5217 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5218 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5219}
5220
5221static int niu_ipp_reset(struct niu *np)
5222{
5223 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5224 1000, 100, "IPP_CFIG");
5225}
5226
5227static int niu_init_ipp(struct niu *np)
5228{
5229 u64 data[5], rbuf[5], val;
5230 int i, max, err;
5231
5232 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5233 if (np->port == 0 || np->port == 1)
5234 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5235 else
5236 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5237 } else
5238 max = NIU_DFIFO_ENTRIES;
5239
5240 data[0] = 0;
5241 data[1] = 0;
5242 data[2] = 0;
5243 data[3] = 0;
5244 data[4] = 0;
5245
5246 for (i = 0; i < max; i++) {
5247 niu_ipp_write(np, i, data);
5248 niu_ipp_read(np, i, rbuf);
5249 }
5250
5251 (void) nr64_ipp(IPP_INT_STAT);
5252 (void) nr64_ipp(IPP_INT_STAT);
5253
5254 err = niu_ipp_reset(np);
5255 if (err)
5256 return err;
5257
5258 (void) nr64_ipp(IPP_PKT_DIS);
5259 (void) nr64_ipp(IPP_BAD_CS_CNT);
5260 (void) nr64_ipp(IPP_ECC);
5261
5262 (void) nr64_ipp(IPP_INT_STAT);
5263
5264 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5265
5266 val = nr64_ipp(IPP_CFIG);
5267 val &= ~IPP_CFIG_IP_MAX_PKT;
5268 val |= (IPP_CFIG_IPP_ENABLE |
5269 IPP_CFIG_DFIFO_ECC_EN |
5270 IPP_CFIG_DROP_BAD_CRC |
5271 IPP_CFIG_CKSUM_EN |
5272 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5273 nw64_ipp(IPP_CFIG, val);
5274
5275 return 0;
5276}
5277
0c3b091b 5278static void niu_handle_led(struct niu *np, int status)
a3138df9 5279{
a3138df9 5280 u64 val;
a3138df9
DM		 5281 val = nr64_mac(XMAC_CONFIG);
5282
5283 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5284 (np->flags & NIU_FLAGS_FIBER) != 0) {
0c3b091b 5285 if (status) {
a3138df9
DM		 5286 val |= XMAC_CONFIG_LED_POLARITY;
5287 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5288 } else {
5289 val |= XMAC_CONFIG_FORCE_LED_ON;
5290 val &= ~XMAC_CONFIG_LED_POLARITY;
5291 }
5292 }
5293
0c3b091b
ML		 5294 nw64_mac(XMAC_CONFIG, val);
5295}
5296
5297static void niu_init_xif_xmac(struct niu *np)
5298{
5299 struct niu_link_config *lp = &np->link_config;
5300 u64 val;
5301
5fbd7e24
MW		 5302 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5303 val = nr64(MIF_CONFIG);
5304 val |= MIF_CONFIG_ATCA_GE;
5305 nw64(MIF_CONFIG, val);
5306 }
5307
0c3b091b 5308 val = nr64_mac(XMAC_CONFIG);
a3138df9
DM		 5309 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5310
5311 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5312
5313 if (lp->loopback_mode == LOOPBACK_MAC) {
5314 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5315 val |= XMAC_CONFIG_LOOPBACK;
5316 } else {
5317 val &= ~XMAC_CONFIG_LOOPBACK;
5318 }
5319
5320 if (np->flags & NIU_FLAGS_10G) {
5321 val &= ~XMAC_CONFIG_LFS_DISABLE;
5322 } else {
5323 val |= XMAC_CONFIG_LFS_DISABLE;
5fbd7e24
MW		 5324 if (!(np->flags & NIU_FLAGS_FIBER) &&
5325 !(np->flags & NIU_FLAGS_XCVR_SERDES))
a3138df9
DM		 5326 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5327 else
5328 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5329 }
5330
5331 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5332
5333 if (lp->active_speed == SPEED_100)
5334 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5335 else
5336 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5337
5338 nw64_mac(XMAC_CONFIG, val);
5339
5340 val = nr64_mac(XMAC_CONFIG);
5341 val &= ~XMAC_CONFIG_MODE_MASK;
5342 if (np->flags & NIU_FLAGS_10G) {
5343 val |= XMAC_CONFIG_MODE_XGMII;
5344 } else {
38bb045d 5345 if (lp->active_speed == SPEED_1000)
a3138df9 5346 val |= XMAC_CONFIG_MODE_GMII;
38bb045d
CB		 5347 else
5348 val |= XMAC_CONFIG_MODE_MII;
a3138df9
DM		 5349 }
5350
5351 nw64_mac(XMAC_CONFIG, val);
5352}
5353
5354static void niu_init_xif_bmac(struct niu *np)
5355{
5356 struct niu_link_config *lp = &np->link_config;
5357 u64 val;
5358
5359 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5360
5361 if (lp->loopback_mode == LOOPBACK_MAC)
5362 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5363 else
5364 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5365
5366 if (lp->active_speed == SPEED_1000)
5367 val |= BMAC_XIF_CONFIG_GMII_MODE;
5368 else
5369 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5370
5371 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5372 BMAC_XIF_CONFIG_LED_POLARITY);
5373
5374 if (!(np->flags & NIU_FLAGS_10G) &&
5375 !(np->flags & NIU_FLAGS_FIBER) &&
5376 lp->active_speed == SPEED_100)
5377 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5378 else
5379 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5380
5381 nw64_mac(BMAC_XIF_CONFIG, val);
5382}
5383
5384static void niu_init_xif(struct niu *np)
5385{
5386 if (np->flags & NIU_FLAGS_XMAC)
5387 niu_init_xif_xmac(np);
5388 else
5389 niu_init_xif_bmac(np);
5390}
5391
5392static void niu_pcs_mii_reset(struct niu *np)
5393{
5fbd7e24 5394 int limit = 1000;
a3138df9
DM		 5395 u64 val = nr64_pcs(PCS_MII_CTL);
5396 val |= PCS_MII_CTL_RST;
5397 nw64_pcs(PCS_MII_CTL, val);
5fbd7e24
MW		 5398 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5399 udelay(100);
5400 val = nr64_pcs(PCS_MII_CTL);
5401 }
a3138df9
DM		 5402}
5403
5404static void niu_xpcs_reset(struct niu *np)
5405{
5fbd7e24 5406 int limit = 1000;
a3138df9
DM		 5407 u64 val = nr64_xpcs(XPCS_CONTROL1);
5408 val |= XPCS_CONTROL1_RESET;
5409 nw64_xpcs(XPCS_CONTROL1, val);
5fbd7e24
MW		 5410 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5411 udelay(100);
5412 val = nr64_xpcs(XPCS_CONTROL1);
5413 }
a3138df9
DM		 5414}
5415
5416static int niu_init_pcs(struct niu *np)
5417{
5418 struct niu_link_config *lp = &np->link_config;
5419 u64 val;
5420
5fbd7e24
MW		 5421 switch (np->flags & (NIU_FLAGS_10G |
5422 NIU_FLAGS_FIBER |
5423 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 5424 case NIU_FLAGS_FIBER:
5425 /* 1G fiber */
5426 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5427 nw64_pcs(PCS_DPATH_MODE, 0);
5428 niu_pcs_mii_reset(np);
5429 break;
5430
5431 case NIU_FLAGS_10G:
5432 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5fbd7e24
MW		 5433 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5434 /* 10G SERDES */
a3138df9
DM		 5435 if (!(np->flags & NIU_FLAGS_XMAC))
5436 return -EINVAL;
5437
5438 /* 10G copper or fiber */
5439 val = nr64_mac(XMAC_CONFIG);
5440 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5441 nw64_mac(XMAC_CONFIG, val);
5442
5443 niu_xpcs_reset(np);
5444
5445 val = nr64_xpcs(XPCS_CONTROL1);
5446 if (lp->loopback_mode == LOOPBACK_PHY)
5447 val |= XPCS_CONTROL1_LOOPBACK;
5448 else
5449 val &= ~XPCS_CONTROL1_LOOPBACK;
5450 nw64_xpcs(XPCS_CONTROL1, val);
5451
5452 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5453 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5454 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5455 break;
5456
5fbd7e24
MW		 5457
5458 case NIU_FLAGS_XCVR_SERDES:
5459 /* 1G SERDES */
5460 niu_pcs_mii_reset(np);
5461 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5462 nw64_pcs(PCS_DPATH_MODE, 0);
5463 break;
5464
a3138df9
DM		 5465 case 0:
5466 /* 1G copper */
5fbd7e24
MW		 5467 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5468 /* 1G RGMII FIBER */
a3138df9
DM		 5469 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5470 niu_pcs_mii_reset(np);
5471 break;
5472
5473 default:
5474 return -EINVAL;
5475 }
5476
5477 return 0;
5478}
5479
5480static int niu_reset_tx_xmac(struct niu *np)
5481{
5482 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5483 (XTXMAC_SW_RST_REG_RS |
5484 XTXMAC_SW_RST_SOFT_RST),
5485 1000, 100, "XTXMAC_SW_RST");
5486}
5487
5488static int niu_reset_tx_bmac(struct niu *np)
5489{
5490 int limit;
5491
5492 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5493 limit = 1000;
5494 while (--limit >= 0) {
5495 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5496 break;
5497 udelay(100);
5498 }
5499 if (limit < 0) {
5500 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
5501 "BTXMAC_SW_RST[%llx]\n",
5502 np->port,
5503 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5504 return -ENODEV;
5505 }
5506
5507 return 0;
5508}
5509
5510static int niu_reset_tx_mac(struct niu *np)
5511{
5512 if (np->flags & NIU_FLAGS_XMAC)
5513 return niu_reset_tx_xmac(np);
5514 else
5515 return niu_reset_tx_bmac(np);
5516}
5517
5518static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5519{
5520 u64 val;
5521
5522 val = nr64_mac(XMAC_MIN);
5523 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5524 XMAC_MIN_RX_MIN_PKT_SIZE);
5525 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5526 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5527 nw64_mac(XMAC_MIN, val);
5528
5529 nw64_mac(XMAC_MAX, max);
5530
5531 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5532
5533 val = nr64_mac(XMAC_IPG);
5534 if (np->flags & NIU_FLAGS_10G) {
5535 val &= ~XMAC_IPG_IPG_XGMII;
5536 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5537 } else {
5538 val &= ~XMAC_IPG_IPG_MII_GMII;
5539 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5540 }
5541 nw64_mac(XMAC_IPG, val);
5542
5543 val = nr64_mac(XMAC_CONFIG);
5544 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5545 XMAC_CONFIG_STRETCH_MODE |
5546 XMAC_CONFIG_VAR_MIN_IPG_EN |
5547 XMAC_CONFIG_TX_ENABLE);
5548 nw64_mac(XMAC_CONFIG, val);
5549
5550 nw64_mac(TXMAC_FRM_CNT, 0);
5551 nw64_mac(TXMAC_BYTE_CNT, 0);
5552}
5553
5554static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5555{
5556 u64 val;
5557
5558 nw64_mac(BMAC_MIN_FRAME, min);
5559 nw64_mac(BMAC_MAX_FRAME, max);
5560
5561 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5562 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5563 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5564
5565 val = nr64_mac(BTXMAC_CONFIG);
5566 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5567 BTXMAC_CONFIG_ENABLE);
5568 nw64_mac(BTXMAC_CONFIG, val);
5569}
5570
5571static void niu_init_tx_mac(struct niu *np)
5572{
5573 u64 min, max;
5574
5575 min = 64;
5576 if (np->dev->mtu > ETH_DATA_LEN)
5577 max = 9216;
5578 else
5579 max = 1522;
5580
5581 /* The XMAC_MIN register only accepts values for TX min which
5582 * have the low 3 bits cleared.
5583 */
5584 BUILD_BUG_ON(min & 0x7);
5585
5586 if (np->flags & NIU_FLAGS_XMAC)
5587 niu_init_tx_xmac(np, min, max);
5588 else
5589 niu_init_tx_bmac(np, min, max);
5590}
5591
5592static int niu_reset_rx_xmac(struct niu *np)
5593{
5594 int limit;
5595
5596 nw64_mac(XRXMAC_SW_RST,
5597 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5598 limit = 1000;
5599 while (--limit >= 0) {
5600 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5601 XRXMAC_SW_RST_SOFT_RST)))
5602 break;
5603 udelay(100);
5604 }
5605 if (limit < 0) {
5606 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
5607 "XRXMAC_SW_RST[%llx]\n",
5608 np->port,
5609 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5610 return -ENODEV;
5611 }
5612
5613 return 0;
5614}
5615
5616static int niu_reset_rx_bmac(struct niu *np)
5617{
5618 int limit;
5619
5620 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5621 limit = 1000;
5622 while (--limit >= 0) {
5623 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5624 break;
5625 udelay(100);
5626 }
5627 if (limit < 0) {
5628 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
5629 "BRXMAC_SW_RST[%llx]\n",
5630 np->port,
5631 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5632 return -ENODEV;
5633 }
5634
5635 return 0;
5636}
5637
5638static int niu_reset_rx_mac(struct niu *np)
5639{
5640 if (np->flags & NIU_FLAGS_XMAC)
5641 return niu_reset_rx_xmac(np);
5642 else
5643 return niu_reset_rx_bmac(np);
5644}
5645
5646static void niu_init_rx_xmac(struct niu *np)
5647{
5648 struct niu_parent *parent = np->parent;
5649 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5650 int first_rdc_table = tp->first_table_num;
5651 unsigned long i;
5652 u64 val;
5653
5654 nw64_mac(XMAC_ADD_FILT0, 0);
5655 nw64_mac(XMAC_ADD_FILT1, 0);
5656 nw64_mac(XMAC_ADD_FILT2, 0);
5657 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5658 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5659 for (i = 0; i < MAC_NUM_HASH; i++)
5660 nw64_mac(XMAC_HASH_TBL(i), 0);
5661 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5662 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5663 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5664
5665 val = nr64_mac(XMAC_CONFIG);
5666 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5667 XMAC_CONFIG_PROMISCUOUS |
5668 XMAC_CONFIG_PROMISC_GROUP |
5669 XMAC_CONFIG_ERR_CHK_DIS |
5670 XMAC_CONFIG_RX_CRC_CHK_DIS |
5671 XMAC_CONFIG_RESERVED_MULTICAST |
5672 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5673 XMAC_CONFIG_ADDR_FILTER_EN |
5674 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5675 XMAC_CONFIG_STRIP_CRC |
5676 XMAC_CONFIG_PASS_FLOW_CTRL |
5677 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5678 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5679 nw64_mac(XMAC_CONFIG, val);
5680
5681 nw64_mac(RXMAC_BT_CNT, 0);
5682 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5683 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5684 nw64_mac(RXMAC_FRAG_CNT, 0);
5685 nw64_mac(RXMAC_HIST_CNT1, 0);
5686 nw64_mac(RXMAC_HIST_CNT2, 0);
5687 nw64_mac(RXMAC_HIST_CNT3, 0);
5688 nw64_mac(RXMAC_HIST_CNT4, 0);
5689 nw64_mac(RXMAC_HIST_CNT5, 0);
5690 nw64_mac(RXMAC_HIST_CNT6, 0);
5691 nw64_mac(RXMAC_HIST_CNT7, 0);
5692 nw64_mac(RXMAC_MPSZER_CNT, 0);
5693 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5694 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5695 nw64_mac(LINK_FAULT_CNT, 0);
5696}
5697
5698static void niu_init_rx_bmac(struct niu *np)
5699{
5700 struct niu_parent *parent = np->parent;
5701 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5702 int first_rdc_table = tp->first_table_num;
5703 unsigned long i;
5704 u64 val;
5705
5706 nw64_mac(BMAC_ADD_FILT0, 0);
5707 nw64_mac(BMAC_ADD_FILT1, 0);
5708 nw64_mac(BMAC_ADD_FILT2, 0);
5709 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5710 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5711 for (i = 0; i < MAC_NUM_HASH; i++)
5712 nw64_mac(BMAC_HASH_TBL(i), 0);
5713 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5714 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5715 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5716
5717 val = nr64_mac(BRXMAC_CONFIG);
5718 val &= ~(BRXMAC_CONFIG_ENABLE |
5719 BRXMAC_CONFIG_STRIP_PAD |
5720 BRXMAC_CONFIG_STRIP_FCS |
5721 BRXMAC_CONFIG_PROMISC |
5722 BRXMAC_CONFIG_PROMISC_GRP |
5723 BRXMAC_CONFIG_ADDR_FILT_EN |
5724 BRXMAC_CONFIG_DISCARD_DIS);
5725 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5726 nw64_mac(BRXMAC_CONFIG, val);
5727
5728 val = nr64_mac(BMAC_ADDR_CMPEN);
5729 val |= BMAC_ADDR_CMPEN_EN0;
5730 nw64_mac(BMAC_ADDR_CMPEN, val);
5731}
5732
5733static void niu_init_rx_mac(struct niu *np)
5734{
5735 niu_set_primary_mac(np, np->dev->dev_addr);
5736
5737 if (np->flags & NIU_FLAGS_XMAC)
5738 niu_init_rx_xmac(np);
5739 else
5740 niu_init_rx_bmac(np);
5741}
5742
5743static void niu_enable_tx_xmac(struct niu *np, int on)
5744{
5745 u64 val = nr64_mac(XMAC_CONFIG);
5746
5747 if (on)
5748 val |= XMAC_CONFIG_TX_ENABLE;
5749 else
5750 val &= ~XMAC_CONFIG_TX_ENABLE;
5751 nw64_mac(XMAC_CONFIG, val);
5752}
5753
5754static void niu_enable_tx_bmac(struct niu *np, int on)
5755{
5756 u64 val = nr64_mac(BTXMAC_CONFIG);
5757
5758 if (on)
5759 val |= BTXMAC_CONFIG_ENABLE;
5760 else
5761 val &= ~BTXMAC_CONFIG_ENABLE;
5762 nw64_mac(BTXMAC_CONFIG, val);
5763}
5764
5765static void niu_enable_tx_mac(struct niu *np, int on)
5766{
5767 if (np->flags & NIU_FLAGS_XMAC)
5768 niu_enable_tx_xmac(np, on);
5769 else
5770 niu_enable_tx_bmac(np, on);
5771}
5772
5773static void niu_enable_rx_xmac(struct niu *np, int on)
5774{
5775 u64 val = nr64_mac(XMAC_CONFIG);
5776
5777 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5778 XMAC_CONFIG_PROMISCUOUS);
5779
5780 if (np->flags & NIU_FLAGS_MCAST)
5781 val |= XMAC_CONFIG_HASH_FILTER_EN;
5782 if (np->flags & NIU_FLAGS_PROMISC)
5783 val |= XMAC_CONFIG_PROMISCUOUS;
5784
5785 if (on)
5786 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5787 else
5788 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5789 nw64_mac(XMAC_CONFIG, val);
5790}
5791
5792static void niu_enable_rx_bmac(struct niu *np, int on)
5793{
5794 u64 val = nr64_mac(BRXMAC_CONFIG);
5795
5796 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5797 BRXMAC_CONFIG_PROMISC);
5798
5799 if (np->flags & NIU_FLAGS_MCAST)
5800 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5801 if (np->flags & NIU_FLAGS_PROMISC)
5802 val |= BRXMAC_CONFIG_PROMISC;
5803
5804 if (on)
5805 val |= BRXMAC_CONFIG_ENABLE;
5806 else
5807 val &= ~BRXMAC_CONFIG_ENABLE;
5808 nw64_mac(BRXMAC_CONFIG, val);
5809}
5810
5811static void niu_enable_rx_mac(struct niu *np, int on)
5812{
5813 if (np->flags & NIU_FLAGS_XMAC)
5814 niu_enable_rx_xmac(np, on);
5815 else
5816 niu_enable_rx_bmac(np, on);
5817}
5818
5819static int niu_init_mac(struct niu *np)
5820{
5821 int err;
5822
5823 niu_init_xif(np);
5824 err = niu_init_pcs(np);
5825 if (err)
5826 return err;
5827
5828 err = niu_reset_tx_mac(np);
5829 if (err)
5830 return err;
5831 niu_init_tx_mac(np);
5832 err = niu_reset_rx_mac(np);
5833 if (err)
5834 return err;
5835 niu_init_rx_mac(np);
5836
5837 /* This looks hookey but the RX MAC reset we just did will
5838 * undo some of the state we setup in niu_init_tx_mac() so we
5839 * have to call it again. In particular, the RX MAC reset will
5840 * set the XMAC_MAX register back to it's default value.
5841 */
5842 niu_init_tx_mac(np);
5843 niu_enable_tx_mac(np, 1);
5844
5845 niu_enable_rx_mac(np, 1);
5846
5847 return 0;
5848}
5849
5850static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5851{
5852 (void) niu_tx_channel_stop(np, rp->tx_channel);
5853}
5854
5855static void niu_stop_tx_channels(struct niu *np)
5856{
5857 int i;
5858
5859 for (i = 0; i < np->num_tx_rings; i++) {
5860 struct tx_ring_info *rp = &np->tx_rings[i];
5861
5862 niu_stop_one_tx_channel(np, rp);
5863 }
5864}
5865
5866static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5867{
5868 (void) niu_tx_channel_reset(np, rp->tx_channel);
5869}
5870
5871static void niu_reset_tx_channels(struct niu *np)
5872{
5873 int i;
5874
5875 for (i = 0; i < np->num_tx_rings; i++) {
5876 struct tx_ring_info *rp = &np->tx_rings[i];
5877
5878 niu_reset_one_tx_channel(np, rp);
5879 }
5880}
5881
5882static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5883{
5884 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5885}
5886
5887static void niu_stop_rx_channels(struct niu *np)
5888{
5889 int i;
5890
5891 for (i = 0; i < np->num_rx_rings; i++) {
5892 struct rx_ring_info *rp = &np->rx_rings[i];
5893
5894 niu_stop_one_rx_channel(np, rp);
5895 }
5896}
5897
5898static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5899{
5900 int channel = rp->rx_channel;
5901
5902 (void) niu_rx_channel_reset(np, channel);
5903 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5904 nw64(RX_DMA_CTL_STAT(channel), 0);
5905 (void) niu_enable_rx_channel(np, channel, 0);
5906}
5907
5908static void niu_reset_rx_channels(struct niu *np)
5909{
5910 int i;
5911
5912 for (i = 0; i < np->num_rx_rings; i++) {
5913 struct rx_ring_info *rp = &np->rx_rings[i];
5914
5915 niu_reset_one_rx_channel(np, rp);
5916 }
5917}
5918
5919static void niu_disable_ipp(struct niu *np)
5920{
5921 u64 rd, wr, val;
5922 int limit;
5923
5924 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5925 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5926 limit = 100;
5927 while (--limit >= 0 && (rd != wr)) {
5928 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5929 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5930 }
5931 if (limit < 0 &&
5932 (rd != 0 && wr != 1)) {
5933 dev_err(np->device, PFX "%s: IPP would not quiesce, "
5934 "rd_ptr[%llx] wr_ptr[%llx]\n",
5935 np->dev->name,
5936 (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
5937 (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
5938 }
5939
5940 val = nr64_ipp(IPP_CFIG);
5941 val &= ~(IPP_CFIG_IPP_ENABLE |
5942 IPP_CFIG_DFIFO_ECC_EN |
5943 IPP_CFIG_DROP_BAD_CRC |
5944 IPP_CFIG_CKSUM_EN);
5945 nw64_ipp(IPP_CFIG, val);
5946
5947 (void) niu_ipp_reset(np);
5948}
5949
5950static int niu_init_hw(struct niu *np)
5951{
5952 int i, err;
5953
5954 niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
5955 niu_txc_enable_port(np, 1);
5956 niu_txc_port_dma_enable(np, 1);
5957 niu_txc_set_imask(np, 0);
5958
5959 niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
5960 for (i = 0; i < np->num_tx_rings; i++) {
5961 struct tx_ring_info *rp = &np->tx_rings[i];
5962
5963 err = niu_init_one_tx_channel(np, rp);
5964 if (err)
5965 return err;
5966 }
5967
5968 niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
5969 err = niu_init_rx_channels(np);
5970 if (err)
5971 goto out_uninit_tx_channels;
5972
5973 niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
5974 err = niu_init_classifier_hw(np);
5975 if (err)
5976 goto out_uninit_rx_channels;
5977
5978 niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
5979 err = niu_init_zcp(np);
5980 if (err)
5981 goto out_uninit_rx_channels;
5982
5983 niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
5984 err = niu_init_ipp(np);
5985 if (err)
5986 goto out_uninit_rx_channels;
5987
5988 niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
5989 err = niu_init_mac(np);
5990 if (err)
5991 goto out_uninit_ipp;
5992
5993 return 0;
5994
5995out_uninit_ipp:
5996 niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
5997 niu_disable_ipp(np);
5998
5999out_uninit_rx_channels:
6000 niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
6001 niu_stop_rx_channels(np);
6002 niu_reset_rx_channels(np);
6003
6004out_uninit_tx_channels:
6005 niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
6006 niu_stop_tx_channels(np);
6007 niu_reset_tx_channels(np);
6008
6009 return err;
6010}
6011
6012static void niu_stop_hw(struct niu *np)
6013{
6014 niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
6015 niu_enable_interrupts(np, 0);
6016
6017 niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
6018 niu_enable_rx_mac(np, 0);
6019
6020 niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
6021 niu_disable_ipp(np);
6022
6023 niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
6024 niu_stop_tx_channels(np);
6025
6026 niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
6027 niu_stop_rx_channels(np);
6028
6029 niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
6030 niu_reset_tx_channels(np);
6031
6032 niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
6033 niu_reset_rx_channels(np);
6034}
6035
70340d72
RO		 6036static void niu_set_irq_name(struct niu *np)
6037{
6038 int port = np->port;
6039 int i, j = 1;
6040
6041 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6042
6043 if (port == 0) {
6044 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6045 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6046 j = 3;
6047 }
6048
6049 for (i = 0; i < np->num_ldg - j; i++) {
6050 if (i < np->num_rx_rings)
6051 sprintf(np->irq_name[i+j], "%s-rx-%d",
6052 np->dev->name, i);
6053 else if (i < np->num_tx_rings + np->num_rx_rings)
6054 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6055 i - np->num_rx_rings);
6056 }
6057}
6058
a3138df9
DM		 6059static int niu_request_irq(struct niu *np)
6060{
6061 int i, j, err;
6062
70340d72
RO		 6063 niu_set_irq_name(np);
6064
a3138df9
DM		 6065 err = 0;
6066 for (i = 0; i < np->num_ldg; i++) {
6067 struct niu_ldg *lp = &np->ldg[i];
6068
6069 err = request_irq(lp->irq, niu_interrupt,
6070 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
70340d72 6071 np->irq_name[i], lp);
a3138df9
DM		 6072 if (err)
6073 goto out_free_irqs;
6074
6075 }
6076
6077 return 0;
6078
6079out_free_irqs:
6080 for (j = 0; j < i; j++) {
6081 struct niu_ldg *lp = &np->ldg[j];
6082
6083 free_irq(lp->irq, lp);
6084 }
6085 return err;
6086}
6087
6088static void niu_free_irq(struct niu *np)
6089{
6090 int i;
6091
6092 for (i = 0; i < np->num_ldg; i++) {
6093 struct niu_ldg *lp = &np->ldg[i];
6094
6095 free_irq(lp->irq, lp);
6096 }
6097}
6098
6099static void niu_enable_napi(struct niu *np)
6100{
6101 int i;
6102
6103 for (i = 0; i < np->num_ldg; i++)
6104 napi_enable(&np->ldg[i].napi);
6105}
6106
6107static void niu_disable_napi(struct niu *np)
6108{
6109 int i;
6110
6111 for (i = 0; i < np->num_ldg; i++)
6112 napi_disable(&np->ldg[i].napi);
6113}
6114
6115static int niu_open(struct net_device *dev)
6116{
6117 struct niu *np = netdev_priv(dev);
6118 int err;
6119
6120 netif_carrier_off(dev);
6121
6122 err = niu_alloc_channels(np);
6123 if (err)
6124 goto out_err;
6125
6126 err = niu_enable_interrupts(np, 0);
6127 if (err)
6128 goto out_free_channels;
6129
6130 err = niu_request_irq(np);
6131 if (err)
6132 goto out_free_channels;
6133
6134 niu_enable_napi(np);
6135
6136 spin_lock_irq(&np->lock);
6137
6138 err = niu_init_hw(np);
6139 if (!err) {
6140 init_timer(&np->timer);
6141 np->timer.expires = jiffies + HZ;
6142 np->timer.data = (unsigned long) np;
6143 np->timer.function = niu_timer;
6144
6145 err = niu_enable_interrupts(np, 1);
6146 if (err)
6147 niu_stop_hw(np);
6148 }
6149
6150 spin_unlock_irq(&np->lock);
6151
6152 if (err) {
6153 niu_disable_napi(np);
6154 goto out_free_irq;
6155 }
6156
b4c21639 6157 netif_tx_start_all_queues(dev);
a3138df9
DM		 6158
6159 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6160 netif_carrier_on(dev);
6161
6162 add_timer(&np->timer);
6163
6164 return 0;
6165
6166out_free_irq:
6167 niu_free_irq(np);
6168
6169out_free_channels:
6170 niu_free_channels(np);
6171
6172out_err:
6173 return err;
6174}
6175
6176static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6177{
6178 cancel_work_sync(&np->reset_task);
6179
6180 niu_disable_napi(np);
b4c21639 6181 netif_tx_stop_all_queues(dev);
a3138df9
DM		 6182
6183 del_timer_sync(&np->timer);
6184
6185 spin_lock_irq(&np->lock);
6186
6187 niu_stop_hw(np);
6188
6189 spin_unlock_irq(&np->lock);
6190}
6191
6192static int niu_close(struct net_device *dev)
6193{
6194 struct niu *np = netdev_priv(dev);
6195
6196 niu_full_shutdown(np, dev);
6197
6198 niu_free_irq(np);
6199
6200 niu_free_channels(np);
6201
0c3b091b
ML		 6202 niu_handle_led(np, 0);
6203
a3138df9
DM		 6204 return 0;
6205}
6206
6207static void niu_sync_xmac_stats(struct niu *np)
6208{
6209 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6210
6211 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6212 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6213
6214 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6215 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6216 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6217 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6218 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6219 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6220 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6221 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6222 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6223 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6224 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6225 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6226 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6227 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6228 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6229 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6230}
6231
6232static void niu_sync_bmac_stats(struct niu *np)
6233{
6234 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6235
6236 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6237 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6238
6239 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6240 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6241 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6242 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6243}
6244
6245static void niu_sync_mac_stats(struct niu *np)
6246{
6247 if (np->flags & NIU_FLAGS_XMAC)
6248 niu_sync_xmac_stats(np);
6249 else
6250 niu_sync_bmac_stats(np);
6251}
6252
6253static void niu_get_rx_stats(struct niu *np)
6254{
6255 unsigned long pkts, dropped, errors, bytes;
6256 int i;
6257
6258 pkts = dropped = errors = bytes = 0;
6259 for (i = 0; i < np->num_rx_rings; i++) {
6260 struct rx_ring_info *rp = &np->rx_rings[i];
6261
b8a606b8
JDB		 6262 niu_sync_rx_discard_stats(np, rp, 0);
6263
a3138df9
DM		 6264 pkts += rp->rx_packets;
6265 bytes += rp->rx_bytes;
6266 dropped += rp->rx_dropped;
6267 errors += rp->rx_errors;
6268 }
9fd42876
IJ		 6269 np->dev->stats.rx_packets = pkts;
6270 np->dev->stats.rx_bytes = bytes;
6271 np->dev->stats.rx_dropped = dropped;
6272 np->dev->stats.rx_errors = errors;
a3138df9
DM		 6273}
6274
6275static void niu_get_tx_stats(struct niu *np)
6276{
6277 unsigned long pkts, errors, bytes;
6278 int i;
6279
6280 pkts = errors = bytes = 0;
6281 for (i = 0; i < np->num_tx_rings; i++) {
6282 struct tx_ring_info *rp = &np->tx_rings[i];
6283
6284 pkts += rp->tx_packets;
6285 bytes += rp->tx_bytes;
6286 errors += rp->tx_errors;
6287 }
9fd42876
IJ		 6288 np->dev->stats.tx_packets = pkts;
6289 np->dev->stats.tx_bytes = bytes;
6290 np->dev->stats.tx_errors = errors;
a3138df9
DM		 6291}
6292
6293static struct net_device_stats *niu_get_stats(struct net_device *dev)
6294{
6295 struct niu *np = netdev_priv(dev);
6296
6297 niu_get_rx_stats(np);
6298 niu_get_tx_stats(np);
6299
9fd42876 6300 return &dev->stats;
a3138df9
DM		 6301}
6302
6303static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6304{
6305 int i;
6306
6307 for (i = 0; i < 16; i++)
6308 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6309}
6310
6311static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6312{
6313 int i;
6314
6315 for (i = 0; i < 16; i++)
6316 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6317}
6318
6319static void niu_load_hash(struct niu *np, u16 *hash)
6320{
6321 if (np->flags & NIU_FLAGS_XMAC)
6322 niu_load_hash_xmac(np, hash);
6323 else
6324 niu_load_hash_bmac(np, hash);
6325}
6326
6327static void niu_set_rx_mode(struct net_device *dev)
6328{
6329 struct niu *np = netdev_priv(dev);
6330 int i, alt_cnt, err;
6331 struct dev_addr_list *addr;
6332 unsigned long flags;
6333 u16 hash[16] = { 0, };
6334
6335 spin_lock_irqsave(&np->lock, flags);
6336 niu_enable_rx_mac(np, 0);
6337
6338 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6339 if (dev->flags & IFF_PROMISC)
6340 np->flags |= NIU_FLAGS_PROMISC;
6341 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
6342 np->flags |= NIU_FLAGS_MCAST;
6343
6344 alt_cnt = dev->uc_count;
6345 if (alt_cnt > niu_num_alt_addr(np)) {
6346 alt_cnt = 0;
6347 np->flags |= NIU_FLAGS_PROMISC;
6348 }
6349
6350 if (alt_cnt) {
6351 int index = 0;
6352
6353 for (addr = dev->uc_list; addr; addr = addr->next) {
6354 err = niu_set_alt_mac(np, index,
6355 addr->da_addr);
6356 if (err)
6357 printk(KERN_WARNING PFX "%s: Error %d "
6358 "adding alt mac %d\n",
6359 dev->name, err, index);
6360 err = niu_enable_alt_mac(np, index, 1);
6361 if (err)
6362 printk(KERN_WARNING PFX "%s: Error %d "
6363 "enabling alt mac %d\n",
6364 dev->name, err, index);
6365
6366 index++;
6367 }
6368 } else {
3b5bcede
MW		 6369 int alt_start;
6370 if (np->flags & NIU_FLAGS_XMAC)
6371 alt_start = 0;
6372 else
6373 alt_start = 1;
6374 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
a3138df9
DM		 6375 err = niu_enable_alt_mac(np, i, 0);
6376 if (err)
6377 printk(KERN_WARNING PFX "%s: Error %d "
6378 "disabling alt mac %d\n",
6379 dev->name, err, i);
6380 }
6381 }
6382 if (dev->flags & IFF_ALLMULTI) {
6383 for (i = 0; i < 16; i++)
6384 hash[i] = 0xffff;
6385 } else if (dev->mc_count > 0) {
6386 for (addr = dev->mc_list; addr; addr = addr->next) {
6387 u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
6388
6389 crc >>= 24;
6390 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6391 }
6392 }
6393
6394 if (np->flags & NIU_FLAGS_MCAST)
6395 niu_load_hash(np, hash);
6396
6397 niu_enable_rx_mac(np, 1);
6398 spin_unlock_irqrestore(&np->lock, flags);
6399}
6400
6401static int niu_set_mac_addr(struct net_device *dev, void *p)
6402{
6403 struct niu *np = netdev_priv(dev);
6404 struct sockaddr *addr = p;
6405 unsigned long flags;
6406
6407 if (!is_valid_ether_addr(addr->sa_data))
6408 return -EINVAL;
6409
6410 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6411
6412 if (!netif_running(dev))
6413 return 0;
6414
6415 spin_lock_irqsave(&np->lock, flags);
6416 niu_enable_rx_mac(np, 0);
6417 niu_set_primary_mac(np, dev->dev_addr);
6418 niu_enable_rx_mac(np, 1);
6419 spin_unlock_irqrestore(&np->lock, flags);
6420
6421 return 0;
6422}
6423
6424static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6425{
6426 return -EOPNOTSUPP;
6427}
6428
6429static void niu_netif_stop(struct niu *np)
6430{
6431 np->dev->trans_start = jiffies; /* prevent tx timeout */
6432
6433 niu_disable_napi(np);
6434
6435 netif_tx_disable(np->dev);
6436}
6437
6438static void niu_netif_start(struct niu *np)
6439{
6440 /* NOTE: unconditional netif_wake_queue is only appropriate
6441 * so long as all callers are assured to have free tx slots
6442 * (such as after niu_init_hw).
6443 */
b4c21639 6444 netif_tx_wake_all_queues(np->dev);
a3138df9
DM		 6445
6446 niu_enable_napi(np);
6447
6448 niu_enable_interrupts(np, 1);
6449}
6450
cff502a3
SB		 6451static void niu_reset_buffers(struct niu *np)
6452{
6453 int i, j, k, err;
6454
6455 if (np->rx_rings) {
6456 for (i = 0; i < np->num_rx_rings; i++) {
6457 struct rx_ring_info *rp = &np->rx_rings[i];
6458
6459 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6460 struct page *page;
6461
6462 page = rp->rxhash[j];
6463 while (page) {
6464 struct page *next =
6465 (struct page *) page->mapping;
6466 u64 base = page->index;
6467 base = base >> RBR_DESCR_ADDR_SHIFT;
6468 rp->rbr[k++] = cpu_to_le32(base);
6469 page = next;
6470 }
6471 }
6472 for (; k < MAX_RBR_RING_SIZE; k++) {
6473 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6474 if (unlikely(err))
6475 break;
6476 }
6477
6478 rp->rbr_index = rp->rbr_table_size - 1;
6479 rp->rcr_index = 0;
6480 rp->rbr_pending = 0;
6481 rp->rbr_refill_pending = 0;
6482 }
6483 }
6484 if (np->tx_rings) {
6485 for (i = 0; i < np->num_tx_rings; i++) {
6486 struct tx_ring_info *rp = &np->tx_rings[i];
6487
6488 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6489 if (rp->tx_buffs[j].skb)
6490 (void) release_tx_packet(np, rp, j);
6491 }
6492
6493 rp->pending = MAX_TX_RING_SIZE;
6494 rp->prod = 0;
6495 rp->cons = 0;
6496 rp->wrap_bit = 0;
6497 }
6498 }
6499}
6500
a3138df9
DM		 6501static void niu_reset_task(struct work_struct *work)
6502{
6503 struct niu *np = container_of(work, struct niu, reset_task);
6504 unsigned long flags;
6505 int err;
6506
6507 spin_lock_irqsave(&np->lock, flags);
6508 if (!netif_running(np->dev)) {
6509 spin_unlock_irqrestore(&np->lock, flags);
6510 return;
6511 }
6512
6513 spin_unlock_irqrestore(&np->lock, flags);
6514
6515 del_timer_sync(&np->timer);
6516
6517 niu_netif_stop(np);
6518
6519 spin_lock_irqsave(&np->lock, flags);
6520
6521 niu_stop_hw(np);
6522
cff502a3
SB		 6523 spin_unlock_irqrestore(&np->lock, flags);
6524
6525 niu_reset_buffers(np);
6526
6527 spin_lock_irqsave(&np->lock, flags);
6528
a3138df9
DM		 6529 err = niu_init_hw(np);
6530 if (!err) {
6531 np->timer.expires = jiffies + HZ;
6532 add_timer(&np->timer);
6533 niu_netif_start(np);
6534 }
6535
6536 spin_unlock_irqrestore(&np->lock, flags);
6537}
6538
6539static void niu_tx_timeout(struct net_device *dev)
6540{
6541 struct niu *np = netdev_priv(dev);
6542
6543 dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
6544 dev->name);
6545
6546 schedule_work(&np->reset_task);
6547}
6548
6549static void niu_set_txd(struct tx_ring_info *rp, int index,
6550 u64 mapping, u64 len, u64 mark,
6551 u64 n_frags)
6552{
6553 __le64 *desc = &rp->descr[index];
6554
6555 *desc = cpu_to_le64(mark |
6556 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6557 (len << TX_DESC_TR_LEN_SHIFT) |
6558 (mapping & TX_DESC_SAD));
6559}
6560
6561static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6562 u64 pad_bytes, u64 len)
6563{
6564 u16 eth_proto, eth_proto_inner;
6565 u64 csum_bits, l3off, ihl, ret;
6566 u8 ip_proto;
6567 int ipv6;
6568
6569 eth_proto = be16_to_cpu(ehdr->h_proto);
6570 eth_proto_inner = eth_proto;
6571 if (eth_proto == ETH_P_8021Q) {
6572 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6573 __be16 val = vp->h_vlan_encapsulated_proto;
6574
6575 eth_proto_inner = be16_to_cpu(val);
6576 }
6577
6578 ipv6 = ihl = 0;
6579 switch (skb->protocol) {
09640e63 6580 case cpu_to_be16(ETH_P_IP):
a3138df9
DM		 6581 ip_proto = ip_hdr(skb)->protocol;
6582 ihl = ip_hdr(skb)->ihl;
6583 break;
09640e63 6584 case cpu_to_be16(ETH_P_IPV6):
a3138df9
DM		 6585 ip_proto = ipv6_hdr(skb)->nexthdr;
6586 ihl = (40 >> 2);
6587 ipv6 = 1;
6588 break;
6589 default:
6590 ip_proto = ihl = 0;
6591 break;
6592 }
6593
6594 csum_bits = TXHDR_CSUM_NONE;
6595 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6596 u64 start, stuff;
6597
6598 csum_bits = (ip_proto == IPPROTO_TCP ?
6599 TXHDR_CSUM_TCP :
6600 (ip_proto == IPPROTO_UDP ?
6601 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6602
6603 start = skb_transport_offset(skb) -
6604 (pad_bytes + sizeof(struct tx_pkt_hdr));
6605 stuff = start + skb->csum_offset;
6606
6607 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6608 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6609 }
6610
6611 l3off = skb_network_offset(skb) -
6612 (pad_bytes + sizeof(struct tx_pkt_hdr));
6613
6614 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6615 (len << TXHDR_LEN_SHIFT) |
6616 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6617 (ihl << TXHDR_IHL_SHIFT) |
6618 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6619 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6620 (ipv6 ? TXHDR_IP_VER : 0) |
6621 csum_bits);
6622
6623 return ret;
6624}
6625
a3138df9
DM		 6626static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
6627{
6628 struct niu *np = netdev_priv(dev);
6629 unsigned long align, headroom;
b4c21639 6630 struct netdev_queue *txq;
a3138df9
DM		 6631 struct tx_ring_info *rp;
6632 struct tx_pkt_hdr *tp;
6633 unsigned int len, nfg;
6634 struct ethhdr *ehdr;
6635 int prod, i, tlen;
6636 u64 mapping, mrk;
6637
b4c21639
DM		 6638 i = skb_get_queue_mapping(skb);
6639 rp = &np->tx_rings[i];
6640 txq = netdev_get_tx_queue(dev, i);
a3138df9
DM		 6641
6642 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
b4c21639 6643 netif_tx_stop_queue(txq);
a3138df9
DM		 6644 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
6645 "queue awake!\n", dev->name);
6646 rp->tx_errors++;
6647 return NETDEV_TX_BUSY;
6648 }
6649
6650 if (skb->len < ETH_ZLEN) {
6651 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6652
6653 if (skb_pad(skb, pad_bytes))
6654 goto out;
6655 skb_put(skb, pad_bytes);
6656 }
6657
6658 len = sizeof(struct tx_pkt_hdr) + 15;
6659 if (skb_headroom(skb) < len) {
6660 struct sk_buff *skb_new;
6661
6662 skb_new = skb_realloc_headroom(skb, len);
6663 if (!skb_new) {
6664 rp->tx_errors++;
6665 goto out_drop;
6666 }
6667 kfree_skb(skb);
6668 skb = skb_new;
3ebebccf
DM		 6669 } else
6670 skb_orphan(skb);
a3138df9
DM		 6671
6672 align = ((unsigned long) skb->data & (16 - 1));
6673 headroom = align + sizeof(struct tx_pkt_hdr);
6674
6675 ehdr = (struct ethhdr *) skb->data;
6676 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6677
6678 len = skb->len - sizeof(struct tx_pkt_hdr);
6679 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6680 tp->resv = 0;
6681
6682 len = skb_headlen(skb);
6683 mapping = np->ops->map_single(np->device, skb->data,
6684 len, DMA_TO_DEVICE);
6685
6686 prod = rp->prod;
6687
6688 rp->tx_buffs[prod].skb = skb;
6689 rp->tx_buffs[prod].mapping = mapping;
6690
6691 mrk = TX_DESC_SOP;
6692 if (++rp->mark_counter == rp->mark_freq) {
6693 rp->mark_counter = 0;
6694 mrk |= TX_DESC_MARK;
6695 rp->mark_pending++;
6696 }
6697
6698 tlen = len;
6699 nfg = skb_shinfo(skb)->nr_frags;
6700 while (tlen > 0) {
6701 tlen -= MAX_TX_DESC_LEN;
6702 nfg++;
6703 }
6704
6705 while (len > 0) {
6706 unsigned int this_len = len;
6707
6708 if (this_len > MAX_TX_DESC_LEN)
6709 this_len = MAX_TX_DESC_LEN;
6710
6711 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6712 mrk = nfg = 0;
6713
6714 prod = NEXT_TX(rp, prod);
6715 mapping += this_len;
6716 len -= this_len;
6717 }
6718
6719 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6720 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6721
6722 len = frag->size;
6723 mapping = np->ops->map_page(np->device, frag->page,
6724 frag->page_offset, len,
6725 DMA_TO_DEVICE);
6726
6727 rp->tx_buffs[prod].skb = NULL;
6728 rp->tx_buffs[prod].mapping = mapping;
6729
6730 niu_set_txd(rp, prod, mapping, len, 0, 0);
6731
6732 prod = NEXT_TX(rp, prod);
6733 }
6734
6735 if (prod < rp->prod)
6736 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6737 rp->prod = prod;
6738
6739 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6740
6741 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
b4c21639 6742 netif_tx_stop_queue(txq);
a3138df9 6743 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
b4c21639 6744 netif_tx_wake_queue(txq);
a3138df9
DM		 6745 }
6746
6747 dev->trans_start = jiffies;
6748
6749out:
6750 return NETDEV_TX_OK;
6751
6752out_drop:
6753 rp->tx_errors++;
6754 kfree_skb(skb);
6755 goto out;
6756}
6757
6758static int niu_change_mtu(struct net_device *dev, int new_mtu)
6759{
6760 struct niu *np = netdev_priv(dev);
6761 int err, orig_jumbo, new_jumbo;
6762
6763 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6764 return -EINVAL;
6765
6766 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6767 new_jumbo = (new_mtu > ETH_DATA_LEN);
6768
6769 dev->mtu = new_mtu;
6770
6771 if (!netif_running(dev) ||
6772 (orig_jumbo == new_jumbo))
6773 return 0;
6774
6775 niu_full_shutdown(np, dev);
6776
6777 niu_free_channels(np);
6778
6779 niu_enable_napi(np);
6780
6781 err = niu_alloc_channels(np);
6782 if (err)
6783 return err;
6784
6785 spin_lock_irq(&np->lock);
6786
6787 err = niu_init_hw(np);
6788 if (!err) {
6789 init_timer(&np->timer);
6790 np->timer.expires = jiffies + HZ;
6791 np->timer.data = (unsigned long) np;
6792 np->timer.function = niu_timer;
6793
6794 err = niu_enable_interrupts(np, 1);
6795 if (err)
6796 niu_stop_hw(np);
6797 }
6798
6799 spin_unlock_irq(&np->lock);
6800
6801 if (!err) {
b4c21639 6802 netif_tx_start_all_queues(dev);
a3138df9
DM		 6803 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6804 netif_carrier_on(dev);
6805
6806 add_timer(&np->timer);
6807 }
6808
6809 return err;
6810}
6811
6812static void niu_get_drvinfo(struct net_device *dev,
6813 struct ethtool_drvinfo *info)
6814{
6815 struct niu *np = netdev_priv(dev);
6816 struct niu_vpd *vpd = &np->vpd;
6817
6818 strcpy(info->driver, DRV_MODULE_NAME);
6819 strcpy(info->version, DRV_MODULE_VERSION);
6820 sprintf(info->fw_version, "%d.%d",
6821 vpd->fcode_major, vpd->fcode_minor);
6822 if (np->parent->plat_type != PLAT_TYPE_NIU)
6823 strcpy(info->bus_info, pci_name(np->pdev));
6824}
6825
6826static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6827{
6828 struct niu *np = netdev_priv(dev);
6829 struct niu_link_config *lp;
6830
6831 lp = &np->link_config;
6832
6833 memset(cmd, 0, sizeof(*cmd));
6834 cmd->phy_address = np->phy_addr;
6835 cmd->supported = lp->supported;
38bb045d
CB		 6836 cmd->advertising = lp->active_advertising;
6837 cmd->autoneg = lp->active_autoneg;
a3138df9
DM		 6838 cmd->speed = lp->active_speed;
6839 cmd->duplex = lp->active_duplex;
38bb045d
CB		 6840 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6841 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6842 XCVR_EXTERNAL : XCVR_INTERNAL;
a3138df9
DM		 6843
6844 return 0;
6845}
6846
6847static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6848{
38bb045d
CB		 6849 struct niu *np = netdev_priv(dev);
6850 struct niu_link_config *lp = &np->link_config;
6851
6852 lp->advertising = cmd->advertising;
6853 lp->speed = cmd->speed;
6854 lp->duplex = cmd->duplex;
6855 lp->autoneg = cmd->autoneg;
6856 return niu_init_link(np);
a3138df9
DM		 6857}
6858
6859static u32 niu_get_msglevel(struct net_device *dev)
6860{
6861 struct niu *np = netdev_priv(dev);
6862 return np->msg_enable;
6863}
6864
6865static void niu_set_msglevel(struct net_device *dev, u32 value)
6866{
6867 struct niu *np = netdev_priv(dev);
6868 np->msg_enable = value;
6869}
6870
38bb045d
CB		 6871static int niu_nway_reset(struct net_device *dev)
6872{
6873 struct niu *np = netdev_priv(dev);
6874
6875 if (np->link_config.autoneg)
6876 return niu_init_link(np);
6877
6878 return 0;
6879}
6880
a3138df9
DM		 6881static int niu_get_eeprom_len(struct net_device *dev)
6882{
6883 struct niu *np = netdev_priv(dev);
6884
6885 return np->eeprom_len;
6886}
6887
6888static int niu_get_eeprom(struct net_device *dev,
6889 struct ethtool_eeprom *eeprom, u8 *data)
6890{
6891 struct niu *np = netdev_priv(dev);
6892 u32 offset, len, val;
6893
6894 offset = eeprom->offset;
6895 len = eeprom->len;
6896
6897 if (offset + len < offset)
6898 return -EINVAL;
6899 if (offset >= np->eeprom_len)
6900 return -EINVAL;
6901 if (offset + len > np->eeprom_len)
6902 len = eeprom->len = np->eeprom_len - offset;
6903
6904 if (offset & 3) {
6905 u32 b_offset, b_count;
6906
6907 b_offset = offset & 3;
6908 b_count = 4 - b_offset;
6909 if (b_count > len)
6910 b_count = len;
6911
6912 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6913 memcpy(data, ((char *)&val) + b_offset, b_count);
6914 data += b_count;
6915 len -= b_count;
6916 offset += b_count;
6917 }
6918 while (len >= 4) {
6919 val = nr64(ESPC_NCR(offset / 4));
6920 memcpy(data, &val, 4);
6921 data += 4;
6922 len -= 4;
6923 offset += 4;
6924 }
6925 if (len) {
6926 val = nr64(ESPC_NCR(offset / 4));
6927 memcpy(data, &val, len);
6928 }
6929 return 0;
6930}
6931
2d96cf8c
SB		 6932static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6933{
6934 switch (flow_type) {
6935 case TCP_V4_FLOW:
6936 case TCP_V6_FLOW:
6937 *pid = IPPROTO_TCP;
6938 break;
6939 case UDP_V4_FLOW:
6940 case UDP_V6_FLOW:
6941 *pid = IPPROTO_UDP;
6942 break;
6943 case SCTP_V4_FLOW:
6944 case SCTP_V6_FLOW:
6945 *pid = IPPROTO_SCTP;
6946 break;
6947 case AH_V4_FLOW:
6948 case AH_V6_FLOW:
6949 *pid = IPPROTO_AH;
6950 break;
6951 case ESP_V4_FLOW:
6952 case ESP_V6_FLOW:
6953 *pid = IPPROTO_ESP;
6954 break;
6955 default:
6956 *pid = 0;
6957 break;
6958 }
6959}
6960
6961static int niu_class_to_ethflow(u64 class, int *flow_type)
6962{
6963 switch (class) {
6964 case CLASS_CODE_TCP_IPV4:
6965 *flow_type = TCP_V4_FLOW;
6966 break;
6967 case CLASS_CODE_UDP_IPV4:
6968 *flow_type = UDP_V4_FLOW;
6969 break;
6970 case CLASS_CODE_AH_ESP_IPV4:
6971 *flow_type = AH_V4_FLOW;
6972 break;
6973 case CLASS_CODE_SCTP_IPV4:
6974 *flow_type = SCTP_V4_FLOW;
6975 break;
6976 case CLASS_CODE_TCP_IPV6:
6977 *flow_type = TCP_V6_FLOW;
6978 break;
6979 case CLASS_CODE_UDP_IPV6:
6980 *flow_type = UDP_V6_FLOW;
6981 break;
6982 case CLASS_CODE_AH_ESP_IPV6:
6983 *flow_type = AH_V6_FLOW;
6984 break;
6985 case CLASS_CODE_SCTP_IPV6:
6986 *flow_type = SCTP_V6_FLOW;
6987 break;
6988 case CLASS_CODE_USER_PROG1:
6989 case CLASS_CODE_USER_PROG2:
6990 case CLASS_CODE_USER_PROG3:
6991 case CLASS_CODE_USER_PROG4:
6992 *flow_type = IP_USER_FLOW;
6993 break;
6994 default:
6995 return 0;
6996 }
6997
6998 return 1;
6999}
7000
b4653e99
SB		 7001static int niu_ethflow_to_class(int flow_type, u64 *class)
7002{
7003 switch (flow_type) {
7004 case TCP_V4_FLOW:
7005 *class = CLASS_CODE_TCP_IPV4;
7006 break;
7007 case UDP_V4_FLOW:
7008 *class = CLASS_CODE_UDP_IPV4;
7009 break;
2d96cf8c
SB		 7010 case AH_V4_FLOW:
7011 case ESP_V4_FLOW:
b4653e99
SB		 7012 *class = CLASS_CODE_AH_ESP_IPV4;
7013 break;
7014 case SCTP_V4_FLOW:
7015 *class = CLASS_CODE_SCTP_IPV4;
7016 break;
7017 case TCP_V6_FLOW:
7018 *class = CLASS_CODE_TCP_IPV6;
7019 break;
7020 case UDP_V6_FLOW:
7021 *class = CLASS_CODE_UDP_IPV6;
7022 break;
2d96cf8c
SB		 7023 case AH_V6_FLOW:
7024 case ESP_V6_FLOW:
b4653e99
SB		 7025 *class = CLASS_CODE_AH_ESP_IPV6;
7026 break;
7027 case SCTP_V6_FLOW:
7028 *class = CLASS_CODE_SCTP_IPV6;
7029 break;
7030 default:
38c080ff 7031 return 0;
b4653e99
SB		 7032 }
7033
7034 return 1;
7035}
7036
7037static u64 niu_flowkey_to_ethflow(u64 flow_key)
7038{
7039 u64 ethflow = 0;
7040
b4653e99
SB		 7041 if (flow_key & FLOW_KEY_L2DA)
7042 ethflow |= RXH_L2DA;
7043 if (flow_key & FLOW_KEY_VLAN)
7044 ethflow |= RXH_VLAN;
7045 if (flow_key & FLOW_KEY_IPSA)
7046 ethflow |= RXH_IP_SRC;
7047 if (flow_key & FLOW_KEY_IPDA)
7048 ethflow |= RXH_IP_DST;
7049 if (flow_key & FLOW_KEY_PROTO)
7050 ethflow |= RXH_L3_PROTO;
7051 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7052 ethflow |= RXH_L4_B_0_1;
7053 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7054 ethflow |= RXH_L4_B_2_3;
7055
7056 return ethflow;
7057
7058}
7059
7060static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7061{
7062 u64 key = 0;
7063
b4653e99
SB		 7064 if (ethflow & RXH_L2DA)
7065 key |= FLOW_KEY_L2DA;
7066 if (ethflow & RXH_VLAN)
7067 key |= FLOW_KEY_VLAN;
7068 if (ethflow & RXH_IP_SRC)
7069 key |= FLOW_KEY_IPSA;
7070 if (ethflow & RXH_IP_DST)
7071 key |= FLOW_KEY_IPDA;
7072 if (ethflow & RXH_L3_PROTO)
7073 key |= FLOW_KEY_PROTO;
7074 if (ethflow & RXH_L4_B_0_1)
7075 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7076 if (ethflow & RXH_L4_B_2_3)
7077 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7078
7079 *flow_key = key;
7080
7081 return 1;
7082
7083}
7084
2d96cf8c 7085static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
b4653e99 7086{
b4653e99
SB		 7087 u64 class;
7088
2d96cf8c 7089 nfc->data = 0;
b4653e99 7090
2d96cf8c 7091 if (!niu_ethflow_to_class(nfc->flow_type, &class))
b4653e99
SB		 7092 return -EINVAL;
7093
7094 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7095 TCAM_KEY_DISC)
2d96cf8c 7096 nfc->data = RXH_DISCARD;
b4653e99 7097 else
2d96cf8c 7098 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
b4653e99
SB		 7099 CLASS_CODE_USER_PROG1]);
7100 return 0;
7101}
7102
2d96cf8c
SB		 7103static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7104 struct ethtool_rx_flow_spec *fsp)
7105{
7106
7107 fsp->h_u.tcp_ip4_spec.ip4src = (tp->key[3] & TCAM_V4KEY3_SADDR) >>
7108 TCAM_V4KEY3_SADDR_SHIFT;
7109 fsp->h_u.tcp_ip4_spec.ip4dst = (tp->key[3] & TCAM_V4KEY3_DADDR) >>
7110 TCAM_V4KEY3_DADDR_SHIFT;
7111 fsp->m_u.tcp_ip4_spec.ip4src = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >>
7112 TCAM_V4KEY3_SADDR_SHIFT;
7113 fsp->m_u.tcp_ip4_spec.ip4dst = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >>
7114 TCAM_V4KEY3_DADDR_SHIFT;
7115
7116 fsp->h_u.tcp_ip4_spec.ip4src =
7117 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4src);
7118 fsp->m_u.tcp_ip4_spec.ip4src =
7119 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4src);
7120 fsp->h_u.tcp_ip4_spec.ip4dst =
7121 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4dst);
7122 fsp->m_u.tcp_ip4_spec.ip4dst =
7123 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4dst);
7124
7125 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7126 TCAM_V4KEY2_TOS_SHIFT;
7127 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7128 TCAM_V4KEY2_TOS_SHIFT;
7129
7130 switch (fsp->flow_type) {
7131 case TCP_V4_FLOW:
7132 case UDP_V4_FLOW:
7133 case SCTP_V4_FLOW:
7134 fsp->h_u.tcp_ip4_spec.psrc =
7135 ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7136 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7137 fsp->h_u.tcp_ip4_spec.pdst =
7138 ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7139 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7140 fsp->m_u.tcp_ip4_spec.psrc =
7141 ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7142 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7143 fsp->m_u.tcp_ip4_spec.pdst =
7144 ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7145 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7146
7147 fsp->h_u.tcp_ip4_spec.psrc =
7148 cpu_to_be16(fsp->h_u.tcp_ip4_spec.psrc);
7149 fsp->h_u.tcp_ip4_spec.pdst =
7150 cpu_to_be16(fsp->h_u.tcp_ip4_spec.pdst);
7151 fsp->m_u.tcp_ip4_spec.psrc =
7152 cpu_to_be16(fsp->m_u.tcp_ip4_spec.psrc);
7153 fsp->m_u.tcp_ip4_spec.pdst =
7154 cpu_to_be16(fsp->m_u.tcp_ip4_spec.pdst);
7155 break;
7156 case AH_V4_FLOW:
7157 case ESP_V4_FLOW:
7158 fsp->h_u.ah_ip4_spec.spi =
7159 (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7160 TCAM_V4KEY2_PORT_SPI_SHIFT;
7161 fsp->m_u.ah_ip4_spec.spi =
7162 (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7163 TCAM_V4KEY2_PORT_SPI_SHIFT;
7164
7165 fsp->h_u.ah_ip4_spec.spi =
7166 cpu_to_be32(fsp->h_u.ah_ip4_spec.spi);
7167 fsp->m_u.ah_ip4_spec.spi =
7168 cpu_to_be32(fsp->m_u.ah_ip4_spec.spi);
7169 break;
7170 case IP_USER_FLOW:
7171 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7172 (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7173 TCAM_V4KEY2_PORT_SPI_SHIFT;
7174 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7175 (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7176 TCAM_V4KEY2_PORT_SPI_SHIFT;
7177
7178 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7179 cpu_to_be32(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7180 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7181 cpu_to_be32(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7182
7183 fsp->h_u.usr_ip4_spec.proto =
7184 (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7185 TCAM_V4KEY2_PROTO_SHIFT;
7186 fsp->m_u.usr_ip4_spec.proto =
7187 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7188 TCAM_V4KEY2_PROTO_SHIFT;
7189
7190 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7191 break;
7192 default:
7193 break;
7194 }
7195}
7196
7197static int niu_get_ethtool_tcam_entry(struct niu *np,
7198 struct ethtool_rxnfc *nfc)
7199{
7200 struct niu_parent *parent = np->parent;
7201 struct niu_tcam_entry *tp;
7202 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7203 u16 idx;
7204 u64 class;
7205 int ret = 0;
7206
7207 idx = tcam_get_index(np, (u16)nfc->fs.location);
7208
7209 tp = &parent->tcam[idx];
7210 if (!tp->valid) {
7211 pr_info(PFX "niu%d: %s entry [%d] invalid for idx[%d]\n",
7212 parent->index, np->dev->name, (u16)nfc->fs.location, idx);
7213 return -EINVAL;
7214 }
7215
7216 /* fill the flow spec entry */
7217 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7218 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7219 ret = niu_class_to_ethflow(class, &fsp->flow_type);
7220
7221 if (ret < 0) {
7222 pr_info(PFX "niu%d: %s niu_class_to_ethflow failed\n",
7223 parent->index, np->dev->name);
7224 ret = -EINVAL;
7225 goto out;
7226 }
7227
7228 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7229 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7230 TCAM_V4KEY2_PROTO_SHIFT;
7231 if (proto == IPPROTO_ESP) {
7232 if (fsp->flow_type == AH_V4_FLOW)
7233 fsp->flow_type = ESP_V4_FLOW;
7234 else
7235 fsp->flow_type = ESP_V6_FLOW;
7236 }
7237 }
7238
7239 switch (fsp->flow_type) {
7240 case TCP_V4_FLOW:
7241 case UDP_V4_FLOW:
7242 case SCTP_V4_FLOW:
7243 case AH_V4_FLOW:
7244 case ESP_V4_FLOW:
7245 niu_get_ip4fs_from_tcam_key(tp, fsp);
7246 break;
7247 case TCP_V6_FLOW:
7248 case UDP_V6_FLOW:
7249 case SCTP_V6_FLOW:
7250 case AH_V6_FLOW:
7251 case ESP_V6_FLOW:
7252 /* Not yet implemented */
7253 ret = -EINVAL;
7254 break;
7255 case IP_USER_FLOW:
7256 niu_get_ip4fs_from_tcam_key(tp, fsp);
7257 break;
7258 default:
7259 ret = -EINVAL;
7260 break;
7261 }
7262
7263 if (ret < 0)
7264 goto out;
7265
7266 if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7267 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7268 else
7269 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7270 TCAM_ASSOCDATA_OFFSET_SHIFT;
7271
7272 /* put the tcam size here */
7273 nfc->data = tcam_get_size(np);
7274out:
7275 return ret;
7276}
7277
7278static int niu_get_ethtool_tcam_all(struct niu *np,
7279 struct ethtool_rxnfc *nfc,
7280 u32 *rule_locs)
7281{
7282 struct niu_parent *parent = np->parent;
7283 struct niu_tcam_entry *tp;
7284 int i, idx, cnt;
7285 u16 n_entries;
7286 unsigned long flags;
7287
7288
7289 /* put the tcam size here */
7290 nfc->data = tcam_get_size(np);
7291
7292 niu_lock_parent(np, flags);
7293 n_entries = nfc->rule_cnt;
7294 for (cnt = 0, i = 0; i < nfc->data; i++) {
7295 idx = tcam_get_index(np, i);
7296 tp = &parent->tcam[idx];
7297 if (!tp->valid)
7298 continue;
7299 rule_locs[cnt] = i;
7300 cnt++;
7301 }
7302 niu_unlock_parent(np, flags);
7303
7304 if (n_entries != cnt) {
7305 /* print warning, this should not happen */
7306 pr_info(PFX "niu%d: %s In niu_get_ethtool_tcam_all, "
7307 "n_entries[%d] != cnt[%d]!!!\n\n",
7308 np->parent->index, np->dev->name, n_entries, cnt);
7309 }
7310
7311 return 0;
7312}
7313
7314static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7315 void *rule_locs)
b4653e99
SB		 7316{
7317 struct niu *np = netdev_priv(dev);
2d96cf8c
SB		 7318 int ret = 0;
7319
7320 switch (cmd->cmd) {
7321 case ETHTOOL_GRXFH:
7322 ret = niu_get_hash_opts(np, cmd);
7323 break;
7324 case ETHTOOL_GRXRINGS:
7325 cmd->data = np->num_rx_rings;
7326 break;
7327 case ETHTOOL_GRXCLSRLCNT:
7328 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7329 break;
7330 case ETHTOOL_GRXCLSRULE:
7331 ret = niu_get_ethtool_tcam_entry(np, cmd);
7332 break;
7333 case ETHTOOL_GRXCLSRLALL:
7334 ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs);
7335 break;
7336 default:
7337 ret = -EINVAL;
7338 break;
7339 }
7340
7341 return ret;
7342}
7343
7344static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7345{
b4653e99
SB		 7346 u64 class;
7347 u64 flow_key = 0;
7348 unsigned long flags;
7349
2d96cf8c 7350 if (!niu_ethflow_to_class(nfc->flow_type, &class))
b4653e99
SB		 7351 return -EINVAL;
7352
7353 if (class < CLASS_CODE_USER_PROG1 ||
7354 class > CLASS_CODE_SCTP_IPV6)
7355 return -EINVAL;
7356
2d96cf8c 7357 if (nfc->data & RXH_DISCARD) {
b4653e99
SB		 7358 niu_lock_parent(np, flags);
7359 flow_key = np->parent->tcam_key[class -
7360 CLASS_CODE_USER_PROG1];
7361 flow_key |= TCAM_KEY_DISC;
7362 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7363 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7364 niu_unlock_parent(np, flags);
7365 return 0;
7366 } else {
7367 /* Discard was set before, but is not set now */
7368 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7369 TCAM_KEY_DISC) {
7370 niu_lock_parent(np, flags);
7371 flow_key = np->parent->tcam_key[class -
7372 CLASS_CODE_USER_PROG1];
7373 flow_key &= ~TCAM_KEY_DISC;
7374 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7375 flow_key);
7376 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7377 flow_key;
7378 niu_unlock_parent(np, flags);
7379 }
7380 }
7381
2d96cf8c 7382 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
b4653e99
SB		 7383 return -EINVAL;
7384
7385 niu_lock_parent(np, flags);
7386 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7387 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7388 niu_unlock_parent(np, flags);
7389
7390 return 0;
7391}
7392
2d96cf8c
SB		 7393static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7394 struct niu_tcam_entry *tp,
7395 int l2_rdc_tab, u64 class)
7396{
7397 u8 pid = 0;
7398 u32 sip, dip, sipm, dipm, spi, spim;
7399 u16 sport, dport, spm, dpm;
7400
7401 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7402 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7403 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7404 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7405
7406 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7407 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7408 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7409 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7410
7411 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7412 tp->key[3] |= dip;
7413
7414 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7415 tp->key_mask[3] |= dipm;
7416
7417 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7418 TCAM_V4KEY2_TOS_SHIFT);
7419 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7420 TCAM_V4KEY2_TOS_SHIFT);
7421 switch (fsp->flow_type) {
7422 case TCP_V4_FLOW:
7423 case UDP_V4_FLOW:
7424 case SCTP_V4_FLOW:
7425 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7426 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7427 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7428 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7429
7430 tp->key[2] |= (((u64)sport << 16) | dport);
7431 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7432 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7433 break;
7434 case AH_V4_FLOW:
7435 case ESP_V4_FLOW:
7436 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7437 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7438
7439 tp->key[2] |= spi;
7440 tp->key_mask[2] |= spim;
7441 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7442 break;
7443 case IP_USER_FLOW:
7444 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7445 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7446
7447 tp->key[2] |= spi;
7448 tp->key_mask[2] |= spim;
7449 pid = fsp->h_u.usr_ip4_spec.proto;
7450 break;
7451 default:
7452 break;
7453 }
7454
7455 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7456 if (pid) {
7457 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7458 }
7459}
7460
7461static int niu_add_ethtool_tcam_entry(struct niu *np,
7462 struct ethtool_rxnfc *nfc)
7463{
7464 struct niu_parent *parent = np->parent;
7465 struct niu_tcam_entry *tp;
7466 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7467 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7468 int l2_rdc_table = rdc_table->first_table_num;
7469 u16 idx;
7470 u64 class;
7471 unsigned long flags;
7472 int err, ret;
7473
7474 ret = 0;
7475
7476 idx = nfc->fs.location;
7477 if (idx >= tcam_get_size(np))
7478 return -EINVAL;
7479
7480 if (fsp->flow_type == IP_USER_FLOW) {
7481 int i;
7482 int add_usr_cls = 0;
7483 int ipv6 = 0;
7484 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7485 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7486
7487 niu_lock_parent(np, flags);
7488
7489 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7490 if (parent->l3_cls[i]) {
7491 if (uspec->proto == parent->l3_cls_pid[i]) {
7492 class = parent->l3_cls[i];
7493 parent->l3_cls_refcnt[i]++;
7494 add_usr_cls = 1;
7495 break;
7496 }
7497 } else {
7498 /* Program new user IP class */
7499 switch (i) {
7500 case 0:
7501 class = CLASS_CODE_USER_PROG1;
7502 break;
7503 case 1:
7504 class = CLASS_CODE_USER_PROG2;
7505 break;
7506 case 2:
7507 class = CLASS_CODE_USER_PROG3;
7508 break;
7509 case 3:
7510 class = CLASS_CODE_USER_PROG4;
7511 break;
7512 default:
7513 break;
7514 }
7515 if (uspec->ip_ver == ETH_RX_NFC_IP6)
7516 ipv6 = 1;
7517 ret = tcam_user_ip_class_set(np, class, ipv6,
7518 uspec->proto,
7519 uspec->tos,
7520 umask->tos);
7521 if (ret)
7522 goto out;
7523
7524 ret = tcam_user_ip_class_enable(np, class, 1);
7525 if (ret)
7526 goto out;
7527 parent->l3_cls[i] = class;
7528 parent->l3_cls_pid[i] = uspec->proto;
7529 parent->l3_cls_refcnt[i]++;
7530 add_usr_cls = 1;
7531 break;
7532 }
7533 }
7534 if (!add_usr_cls) {
7535 pr_info(PFX "niu%d: %s niu_add_ethtool_tcam_entry: "
7536 "Could not find/insert class for pid %d\n",
7537 parent->index, np->dev->name, uspec->proto);
7538 ret = -EINVAL;
7539 goto out;
7540 }
7541 niu_unlock_parent(np, flags);
7542 } else {
7543 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7544 return -EINVAL;
7545 }
7546 }
7547
7548 niu_lock_parent(np, flags);
7549
7550 idx = tcam_get_index(np, idx);
7551 tp = &parent->tcam[idx];
7552
7553 memset(tp, 0, sizeof(*tp));
7554
7555 /* fill in the tcam key and mask */
7556 switch (fsp->flow_type) {
7557 case TCP_V4_FLOW:
7558 case UDP_V4_FLOW:
7559 case SCTP_V4_FLOW:
7560 case AH_V4_FLOW:
7561 case ESP_V4_FLOW:
7562 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7563 break;
7564 case TCP_V6_FLOW:
7565 case UDP_V6_FLOW:
7566 case SCTP_V6_FLOW:
7567 case AH_V6_FLOW:
7568 case ESP_V6_FLOW:
7569 /* Not yet implemented */
7570 pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: "
7571 "flow %d for IPv6 not implemented\n\n",
7572 parent->index, np->dev->name, fsp->flow_type);
7573 ret = -EINVAL;
7574 goto out;
7575 case IP_USER_FLOW:
7576 if (fsp->h_u.usr_ip4_spec.ip_ver == ETH_RX_NFC_IP4) {
7577 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table,
7578 class);
7579 } else {
7580 /* Not yet implemented */
7581 pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: "
7582 "usr flow for IPv6 not implemented\n\n",
7583 parent->index, np->dev->name);
7584 ret = -EINVAL;
7585 goto out;
7586 }
7587 break;
7588 default:
7589 pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: "
7590 "Unknown flow type %d\n\n",
7591 parent->index, np->dev->name, fsp->flow_type);
7592 ret = -EINVAL;
7593 goto out;
7594 }
7595
7596 /* fill in the assoc data */
7597 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7598 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7599 } else {
7600 if (fsp->ring_cookie >= np->num_rx_rings) {
7601 pr_info(PFX "niu%d: %s In niu_add_ethtool_tcam_entry: "
7602 "Invalid RX ring %lld\n\n",
7603 parent->index, np->dev->name,
7604 (long long) fsp->ring_cookie);
7605 ret = -EINVAL;
7606 goto out;
7607 }
7608 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7609 (fsp->ring_cookie <<
7610 TCAM_ASSOCDATA_OFFSET_SHIFT));
7611 }
7612
7613 err = tcam_write(np, idx, tp->key, tp->key_mask);
7614 if (err) {
7615 ret = -EINVAL;
7616 goto out;
7617 }
7618 err = tcam_assoc_write(np, idx, tp->assoc_data);
7619 if (err) {
7620 ret = -EINVAL;
7621 goto out;
7622 }
7623
7624 /* validate the entry */
7625 tp->valid = 1;
7626 np->clas.tcam_valid_entries++;
7627out:
7628 niu_unlock_parent(np, flags);
7629
7630 return ret;
7631}
7632
7633static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7634{
7635 struct niu_parent *parent = np->parent;
7636 struct niu_tcam_entry *tp;
7637 u16 idx;
7638 unsigned long flags;
7639 u64 class;
7640 int ret = 0;
7641
7642 if (loc >= tcam_get_size(np))
7643 return -EINVAL;
7644
7645 niu_lock_parent(np, flags);
7646
7647 idx = tcam_get_index(np, loc);
7648 tp = &parent->tcam[idx];
7649
7650 /* if the entry is of a user defined class, then update*/
7651 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7652 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7653
7654 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7655 int i;
7656 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7657 if (parent->l3_cls[i] == class) {
7658 parent->l3_cls_refcnt[i]--;
7659 if (!parent->l3_cls_refcnt[i]) {
7660 /* disable class */
7661 ret = tcam_user_ip_class_enable(np,
7662 class,
7663 0);
7664 if (ret)
7665 goto out;
7666 parent->l3_cls[i] = 0;
7667 parent->l3_cls_pid[i] = 0;
7668 }
7669 break;
7670 }
7671 }
7672 if (i == NIU_L3_PROG_CLS) {
7673 pr_info(PFX "niu%d: %s In niu_del_ethtool_tcam_entry,"
7674 "Usr class 0x%llx not found \n",
7675 parent->index, np->dev->name,
7676 (unsigned long long) class);
7677 ret = -EINVAL;
7678 goto out;
7679 }
7680 }
7681
7682 ret = tcam_flush(np, idx);
7683 if (ret)
7684 goto out;
7685
7686 /* invalidate the entry */
7687 tp->valid = 0;
7688 np->clas.tcam_valid_entries--;
7689out:
7690 niu_unlock_parent(np, flags);
7691
7692 return ret;
7693}
7694
7695static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7696{
7697 struct niu *np = netdev_priv(dev);
7698 int ret = 0;
7699
7700 switch (cmd->cmd) {
7701 case ETHTOOL_SRXFH:
7702 ret = niu_set_hash_opts(np, cmd);
7703 break;
7704 case ETHTOOL_SRXCLSRLINS:
7705 ret = niu_add_ethtool_tcam_entry(np, cmd);
7706 break;
7707 case ETHTOOL_SRXCLSRLDEL:
7708 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7709 break;
7710 default:
7711 ret = -EINVAL;
7712 break;
7713 }
7714
7715 return ret;
7716}
7717
a3138df9
DM		 7718static const struct {
7719 const char string[ETH_GSTRING_LEN];
7720} niu_xmac_stat_keys[] = {
7721 { "tx_frames" },
7722 { "tx_bytes" },
7723 { "tx_fifo_errors" },
7724 { "tx_overflow_errors" },
7725 { "tx_max_pkt_size_errors" },
7726 { "tx_underflow_errors" },
7727 { "rx_local_faults" },
7728 { "rx_remote_faults" },
7729 { "rx_link_faults" },
7730 { "rx_align_errors" },
7731 { "rx_frags" },
7732 { "rx_mcasts" },
7733 { "rx_bcasts" },
7734 { "rx_hist_cnt1" },
7735 { "rx_hist_cnt2" },
7736 { "rx_hist_cnt3" },
7737 { "rx_hist_cnt4" },
7738 { "rx_hist_cnt5" },
7739 { "rx_hist_cnt6" },
7740 { "rx_hist_cnt7" },
7741 { "rx_octets" },
7742 { "rx_code_violations" },
7743 { "rx_len_errors" },
7744 { "rx_crc_errors" },
7745 { "rx_underflows" },
7746 { "rx_overflows" },
7747 { "pause_off_state" },
7748 { "pause_on_state" },
7749 { "pause_received" },
7750};
7751
7752#define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7753
7754static const struct {
7755 const char string[ETH_GSTRING_LEN];
7756} niu_bmac_stat_keys[] = {
7757 { "tx_underflow_errors" },
7758 { "tx_max_pkt_size_errors" },
7759 { "tx_bytes" },
7760 { "tx_frames" },
7761 { "rx_overflows" },
7762 { "rx_frames" },
7763 { "rx_align_errors" },
7764 { "rx_crc_errors" },
7765 { "rx_len_errors" },
7766 { "pause_off_state" },
7767 { "pause_on_state" },
7768 { "pause_received" },
7769};
7770
7771#define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7772
7773static const struct {
7774 const char string[ETH_GSTRING_LEN];
7775} niu_rxchan_stat_keys[] = {
7776 { "rx_channel" },
7777 { "rx_packets" },
7778 { "rx_bytes" },
7779 { "rx_dropped" },
7780 { "rx_errors" },
7781};
7782
7783#define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7784
7785static const struct {
7786 const char string[ETH_GSTRING_LEN];
7787} niu_txchan_stat_keys[] = {
7788 { "tx_channel" },
7789 { "tx_packets" },
7790 { "tx_bytes" },
7791 { "tx_errors" },
7792};
7793
7794#define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7795
7796static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7797{
7798 struct niu *np = netdev_priv(dev);
7799 int i;
7800
7801 if (stringset != ETH_SS_STATS)
7802 return;
7803
7804 if (np->flags & NIU_FLAGS_XMAC) {
7805 memcpy(data, niu_xmac_stat_keys,
7806 sizeof(niu_xmac_stat_keys));
7807 data += sizeof(niu_xmac_stat_keys);
7808 } else {
7809 memcpy(data, niu_bmac_stat_keys,
7810 sizeof(niu_bmac_stat_keys));
7811 data += sizeof(niu_bmac_stat_keys);
7812 }
7813 for (i = 0; i < np->num_rx_rings; i++) {
7814 memcpy(data, niu_rxchan_stat_keys,
7815 sizeof(niu_rxchan_stat_keys));
7816 data += sizeof(niu_rxchan_stat_keys);
7817 }
7818 for (i = 0; i < np->num_tx_rings; i++) {
7819 memcpy(data, niu_txchan_stat_keys,
7820 sizeof(niu_txchan_stat_keys));
7821 data += sizeof(niu_txchan_stat_keys);
7822 }
7823}
7824
7825static int niu_get_stats_count(struct net_device *dev)
7826{
7827 struct niu *np = netdev_priv(dev);
7828
7829 return ((np->flags & NIU_FLAGS_XMAC ?
7830 NUM_XMAC_STAT_KEYS :
7831 NUM_BMAC_STAT_KEYS) +
7832 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7833 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
7834}
7835
7836static void niu_get_ethtool_stats(struct net_device *dev,
7837 struct ethtool_stats *stats, u64 *data)
7838{
7839 struct niu *np = netdev_priv(dev);
7840 int i;
7841
7842 niu_sync_mac_stats(np);
7843 if (np->flags & NIU_FLAGS_XMAC) {
7844 memcpy(data, &np->mac_stats.xmac,
7845 sizeof(struct niu_xmac_stats));
7846 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7847 } else {
7848 memcpy(data, &np->mac_stats.bmac,
7849 sizeof(struct niu_bmac_stats));
7850 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7851 }
7852 for (i = 0; i < np->num_rx_rings; i++) {
7853 struct rx_ring_info *rp = &np->rx_rings[i];
7854
b8a606b8
JDB		 7855 niu_sync_rx_discard_stats(np, rp, 0);
7856
a3138df9
DM		 7857 data[0] = rp->rx_channel;
7858 data[1] = rp->rx_packets;
7859 data[2] = rp->rx_bytes;
7860 data[3] = rp->rx_dropped;
7861 data[4] = rp->rx_errors;
7862 data += 5;
7863 }
7864 for (i = 0; i < np->num_tx_rings; i++) {
7865 struct tx_ring_info *rp = &np->tx_rings[i];
7866
7867 data[0] = rp->tx_channel;
7868 data[1] = rp->tx_packets;
7869 data[2] = rp->tx_bytes;
7870 data[3] = rp->tx_errors;
7871 data += 4;
7872 }
7873}
7874
7875static u64 niu_led_state_save(struct niu *np)
7876{
7877 if (np->flags & NIU_FLAGS_XMAC)
7878 return nr64_mac(XMAC_CONFIG);
7879 else
7880 return nr64_mac(BMAC_XIF_CONFIG);
7881}
7882
7883static void niu_led_state_restore(struct niu *np, u64 val)
7884{
7885 if (np->flags & NIU_FLAGS_XMAC)
7886 nw64_mac(XMAC_CONFIG, val);
7887 else
7888 nw64_mac(BMAC_XIF_CONFIG, val);
7889}
7890
7891static void niu_force_led(struct niu *np, int on)
7892{
7893 u64 val, reg, bit;
7894
7895 if (np->flags & NIU_FLAGS_XMAC) {
7896 reg = XMAC_CONFIG;
7897 bit = XMAC_CONFIG_FORCE_LED_ON;
7898 } else {
7899 reg = BMAC_XIF_CONFIG;
7900 bit = BMAC_XIF_CONFIG_LINK_LED;
7901 }
7902
7903 val = nr64_mac(reg);
7904 if (on)
7905 val |= bit;
7906 else
7907 val &= ~bit;
7908 nw64_mac(reg, val);
7909}
7910
7911static int niu_phys_id(struct net_device *dev, u32 data)
7912{
7913 struct niu *np = netdev_priv(dev);
7914 u64 orig_led_state;
7915 int i;
7916
7917 if (!netif_running(dev))
7918 return -EAGAIN;
7919
7920 if (data == 0)
7921 data = 2;
7922
7923 orig_led_state = niu_led_state_save(np);
7924 for (i = 0; i < (data * 2); i++) {
7925 int on = ((i % 2) == 0);
7926
7927 niu_force_led(np, on);
7928
7929 if (msleep_interruptible(500))
7930 break;
7931 }
7932 niu_led_state_restore(np, orig_led_state);
7933
7934 return 0;
7935}
7936
7937static const struct ethtool_ops niu_ethtool_ops = {
7938 .get_drvinfo = niu_get_drvinfo,
7939 .get_link = ethtool_op_get_link,
7940 .get_msglevel = niu_get_msglevel,
7941 .set_msglevel = niu_set_msglevel,
38bb045d 7942 .nway_reset = niu_nway_reset,
a3138df9
DM		 7943 .get_eeprom_len = niu_get_eeprom_len,
7944 .get_eeprom = niu_get_eeprom,
7945 .get_settings = niu_get_settings,
7946 .set_settings = niu_set_settings,
7947 .get_strings = niu_get_strings,
7948 .get_stats_count = niu_get_stats_count,
7949 .get_ethtool_stats = niu_get_ethtool_stats,
7950 .phys_id = niu_phys_id,
2d96cf8c
SB		 7951 .get_rxnfc = niu_get_nfc,
7952 .set_rxnfc = niu_set_nfc,
a3138df9
DM		 7953};
7954
7955static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7956 int ldg, int ldn)
7957{
7958 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7959 return -EINVAL;
7960 if (ldn < 0 || ldn > LDN_MAX)
7961 return -EINVAL;
7962
7963 parent->ldg_map[ldn] = ldg;
7964
7965 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7966 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7967 * the firmware, and we're not supposed to change them.
7968 * Validate the mapping, because if it's wrong we probably
7969 * won't get any interrupts and that's painful to debug.
7970 */
7971 if (nr64(LDG_NUM(ldn)) != ldg) {
7972 dev_err(np->device, PFX "Port %u, mis-matched "
7973 "LDG assignment "
7974 "for ldn %d, should be %d is %llu\n",
7975 np->port, ldn, ldg,
7976 (unsigned long long) nr64(LDG_NUM(ldn)));
7977 return -EINVAL;
7978 }
7979 } else
7980 nw64(LDG_NUM(ldn), ldg);
7981
7982 return 0;
7983}
7984
7985static int niu_set_ldg_timer_res(struct niu *np, int res)
7986{
7987 if (res < 0 || res > LDG_TIMER_RES_VAL)
7988 return -EINVAL;
7989
7990
7991 nw64(LDG_TIMER_RES, res);
7992
7993 return 0;
7994}
7995
7996static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7997{
7998 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7999 (func < 0 || func > 3) ||
8000 (vector < 0 || vector > 0x1f))
8001 return -EINVAL;
8002
8003 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
8004
8005 return 0;
8006}
8007
8008static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
8009{
8010 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
8011 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
8012 int limit;
8013
8014 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
8015 return -EINVAL;
8016
8017 frame = frame_base;
8018 nw64(ESPC_PIO_STAT, frame);
8019 limit = 64;
8020 do {
8021 udelay(5);
8022 frame = nr64(ESPC_PIO_STAT);
8023 if (frame & ESPC_PIO_STAT_READ_END)
8024 break;
8025 } while (limit--);
8026 if (!(frame & ESPC_PIO_STAT_READ_END)) {
8027 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
8028 (unsigned long long) frame);
8029 return -ENODEV;
8030 }
8031
8032 frame = frame_base;
8033 nw64(ESPC_PIO_STAT, frame);
8034 limit = 64;
8035 do {
8036 udelay(5);
8037 frame = nr64(ESPC_PIO_STAT);
8038 if (frame & ESPC_PIO_STAT_READ_END)
8039 break;
8040 } while (limit--);
8041 if (!(frame & ESPC_PIO_STAT_READ_END)) {
8042 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
8043 (unsigned long long) frame);
8044 return -ENODEV;
8045 }
8046
8047 frame = nr64(ESPC_PIO_STAT);
8048 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8049}
8050
8051static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8052{
8053 int err = niu_pci_eeprom_read(np, off);
8054 u16 val;
8055
8056 if (err < 0)
8057 return err;
8058 val = (err << 8);
8059 err = niu_pci_eeprom_read(np, off + 1);
8060 if (err < 0)
8061 return err;
8062 val |= (err & 0xff);
8063
8064 return val;
8065}
8066
8067static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8068{
8069 int err = niu_pci_eeprom_read(np, off);
8070 u16 val;
8071
8072 if (err < 0)
8073 return err;
8074
8075 val = (err & 0xff);
8076 err = niu_pci_eeprom_read(np, off + 1);
8077 if (err < 0)
8078 return err;
8079
8080 val |= (err & 0xff) << 8;
8081
8082 return val;
8083}
8084
8085static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8086 u32 off,
8087 char *namebuf,
8088 int namebuf_len)
8089{
8090 int i;
8091
8092 for (i = 0; i < namebuf_len; i++) {
8093 int err = niu_pci_eeprom_read(np, off + i);
8094 if (err < 0)
8095 return err;
8096 *namebuf++ = err;
8097 if (!err)
8098 break;
8099 }
8100 if (i >= namebuf_len)
8101 return -EINVAL;
8102
8103 return i + 1;
8104}
8105
8106static void __devinit niu_vpd_parse_version(struct niu *np)
8107{
8108 struct niu_vpd *vpd = &np->vpd;
8109 int len = strlen(vpd->version) + 1;
8110 const char *s = vpd->version;
8111 int i;
8112
8113 for (i = 0; i < len - 5; i++) {
8114 if (!strncmp(s + i, "FCode ", 5))
8115 break;
8116 }
8117 if (i >= len - 5)
8118 return;
8119
8120 s += i + 5;
8121 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8122
8123 niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8124 vpd->fcode_major, vpd->fcode_minor);
8125 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8126 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8127 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8128 np->flags |= NIU_FLAGS_VPD_VALID;
8129}
8130
8131/* ESPC_PIO_EN_ENABLE must be set */
8132static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8133 u32 start, u32 end)
8134{
8135 unsigned int found_mask = 0;
8136#define FOUND_MASK_MODEL 0x00000001
8137#define FOUND_MASK_BMODEL 0x00000002
8138#define FOUND_MASK_VERS 0x00000004
8139#define FOUND_MASK_MAC 0x00000008
8140#define FOUND_MASK_NMAC 0x00000010
8141#define FOUND_MASK_PHY 0x00000020
8142#define FOUND_MASK_ALL 0x0000003f
8143
8144 niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
8145 start, end);
8146 while (start < end) {
8147 int len, err, instance, type, prop_len;
8148 char namebuf[64];
8149 u8 *prop_buf;
8150 int max_len;
8151
8152 if (found_mask == FOUND_MASK_ALL) {
8153 niu_vpd_parse_version(np);
8154 return 1;
8155 }
8156
8157 err = niu_pci_eeprom_read(np, start + 2);
8158 if (err < 0)
8159 return err;
8160 len = err;
8161 start += 3;
8162
8163 instance = niu_pci_eeprom_read(np, start);
8164 type = niu_pci_eeprom_read(np, start + 3);
8165 prop_len = niu_pci_eeprom_read(np, start + 4);
8166 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8167 if (err < 0)
8168 return err;
8169
8170 prop_buf = NULL;
8171 max_len = 0;
8172 if (!strcmp(namebuf, "model")) {
8173 prop_buf = np->vpd.model;
8174 max_len = NIU_VPD_MODEL_MAX;
8175 found_mask |= FOUND_MASK_MODEL;
8176 } else if (!strcmp(namebuf, "board-model")) {
8177 prop_buf = np->vpd.board_model;
8178 max_len = NIU_VPD_BD_MODEL_MAX;
8179 found_mask |= FOUND_MASK_BMODEL;
8180 } else if (!strcmp(namebuf, "version")) {
8181 prop_buf = np->vpd.version;
8182 max_len = NIU_VPD_VERSION_MAX;
8183 found_mask |= FOUND_MASK_VERS;
8184 } else if (!strcmp(namebuf, "local-mac-address")) {
8185 prop_buf = np->vpd.local_mac;
8186 max_len = ETH_ALEN;
8187 found_mask |= FOUND_MASK_MAC;
8188 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8189 prop_buf = &np->vpd.mac_num;
8190 max_len = 1;
8191 found_mask |= FOUND_MASK_NMAC;
8192 } else if (!strcmp(namebuf, "phy-type")) {
8193 prop_buf = np->vpd.phy_type;
8194 max_len = NIU_VPD_PHY_TYPE_MAX;
8195 found_mask |= FOUND_MASK_PHY;
8196 }
8197
8198 if (max_len && prop_len > max_len) {
8199 dev_err(np->device, PFX "Property '%s' length (%d) is "
8200 "too long.\n", namebuf, prop_len);
8201 return -EINVAL;
8202 }
8203
8204 if (prop_buf) {
8205 u32 off = start + 5 + err;
8206 int i;
8207
8208 niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
8209 "len[%d]\n", namebuf, prop_len);
8210 for (i = 0; i < prop_len; i++)
8211 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8212 }
8213
8214 start += len;
8215 }
8216
8217 return 0;
8218}
8219
8220/* ESPC_PIO_EN_ENABLE must be set */
8221static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8222{
8223 u32 offset;
8224 int err;
8225
8226 err = niu_pci_eeprom_read16_swp(np, start + 1);
8227 if (err < 0)
8228 return;
8229
8230 offset = err + 3;
8231
8232 while (start + offset < ESPC_EEPROM_SIZE) {
8233 u32 here = start + offset;
8234 u32 end;
8235
8236 err = niu_pci_eeprom_read(np, here);
8237 if (err != 0x90)
8238 return;
8239
8240 err = niu_pci_eeprom_read16_swp(np, here + 1);
8241 if (err < 0)
8242 return;
8243
8244 here = start + offset + 3;
8245 end = start + offset + err;
8246
8247 offset += err;
8248
8249 err = niu_pci_vpd_scan_props(np, here, end);
8250 if (err < 0 || err == 1)
8251 return;
8252 }
8253}
8254
8255/* ESPC_PIO_EN_ENABLE must be set */
8256static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8257{
8258 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8259 int err;
8260
8261 while (start < end) {
8262 ret = start;
8263
8264 /* ROM header signature? */
8265 err = niu_pci_eeprom_read16(np, start + 0);
8266 if (err != 0x55aa)
8267 return 0;
8268
8269 /* Apply offset to PCI data structure. */
8270 err = niu_pci_eeprom_read16(np, start + 23);
8271 if (err < 0)
8272 return 0;
8273 start += err;
8274
8275 /* Check for "PCIR" signature. */
8276 err = niu_pci_eeprom_read16(np, start + 0);
8277 if (err != 0x5043)
8278 return 0;
8279 err = niu_pci_eeprom_read16(np, start + 2);
8280 if (err != 0x4952)
8281 return 0;
8282
8283 /* Check for OBP image type. */
8284 err = niu_pci_eeprom_read(np, start + 20);
8285 if (err < 0)
8286 return 0;
8287 if (err != 0x01) {
8288 err = niu_pci_eeprom_read(np, ret + 2);
8289 if (err < 0)
8290 return 0;
8291
8292 start = ret + (err * 512);
8293 continue;
8294 }
8295
8296 err = niu_pci_eeprom_read16_swp(np, start + 8);
8297 if (err < 0)
8298 return err;
8299 ret += err;
8300
8301 err = niu_pci_eeprom_read(np, ret + 0);
8302 if (err != 0x82)
8303 return 0;
8304
8305 return ret;
8306 }
8307
8308 return 0;
8309}
8310
8311static int __devinit niu_phy_type_prop_decode(struct niu *np,
8312 const char *phy_prop)
8313{
8314 if (!strcmp(phy_prop, "mif")) {
8315 /* 1G copper, MII */
8316 np->flags &= ~(NIU_FLAGS_FIBER |
8317 NIU_FLAGS_10G);
8318 np->mac_xcvr = MAC_XCVR_MII;
8319 } else if (!strcmp(phy_prop, "xgf")) {
8320 /* 10G fiber, XPCS */
8321 np->flags |= (NIU_FLAGS_10G |
8322 NIU_FLAGS_FIBER);
8323 np->mac_xcvr = MAC_XCVR_XPCS;
8324 } else if (!strcmp(phy_prop, "pcs")) {
8325 /* 1G fiber, PCS */
8326 np->flags &= ~NIU_FLAGS_10G;
8327 np->flags |= NIU_FLAGS_FIBER;
8328 np->mac_xcvr = MAC_XCVR_PCS;
8329 } else if (!strcmp(phy_prop, "xgc")) {
8330 /* 10G copper, XPCS */
8331 np->flags |= NIU_FLAGS_10G;
8332 np->flags &= ~NIU_FLAGS_FIBER;
8333 np->mac_xcvr = MAC_XCVR_XPCS;
e3e081e1
SB		 8334 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8335 /* 10G Serdes or 1G Serdes, default to 10G */
8336 np->flags |= NIU_FLAGS_10G;
8337 np->flags &= ~NIU_FLAGS_FIBER;
8338 np->flags |= NIU_FLAGS_XCVR_SERDES;
8339 np->mac_xcvr = MAC_XCVR_XPCS;
a3138df9
DM		 8340 } else {
8341 return -EINVAL;
8342 }
8343 return 0;
8344}
8345
7f7c4072
MW		 8346static int niu_pci_vpd_get_nports(struct niu *np)
8347{
8348 int ports = 0;
8349
f9af8574
MW		 8350 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8351 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8352 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8353 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8354 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
7f7c4072 8355 ports = 4;
f9af8574
MW		 8356 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8357 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8358 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8359 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
7f7c4072
MW		 8360 ports = 2;
8361 }
8362
8363 return ports;
8364}
8365
a3138df9
DM		 8366static void __devinit niu_pci_vpd_validate(struct niu *np)
8367{
8368 struct net_device *dev = np->dev;
8369 struct niu_vpd *vpd = &np->vpd;
8370 u8 val8;
8371
8372 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
8373 dev_err(np->device, PFX "VPD MAC invalid, "
8374 "falling back to SPROM.\n");
8375
8376 np->flags &= ~NIU_FLAGS_VPD_VALID;
8377 return;
8378 }
8379
f9af8574
MW		 8380 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8381 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8382 np->flags |= NIU_FLAGS_10G;
8383 np->flags &= ~NIU_FLAGS_FIBER;
8384 np->flags |= NIU_FLAGS_XCVR_SERDES;
8385 np->mac_xcvr = MAC_XCVR_PCS;
8386 if (np->port > 1) {
8387 np->flags |= NIU_FLAGS_FIBER;
8388 np->flags &= ~NIU_FLAGS_10G;
8389 }
8390 if (np->flags & NIU_FLAGS_10G)
8391 np->mac_xcvr = MAC_XCVR_XPCS;
f9af8574 8392 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8393 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8394 NIU_FLAGS_HOTPLUG_PHY);
5fbd7e24 8395 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
a3138df9
DM		 8396 dev_err(np->device, PFX "Illegal phy string [%s].\n",
8397 np->vpd.phy_type);
8398 dev_err(np->device, PFX "Falling back to SPROM.\n");
8399 np->flags &= ~NIU_FLAGS_VPD_VALID;
8400 return;
8401 }
8402
8403 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8404
8405 val8 = dev->perm_addr[5];
8406 dev->perm_addr[5] += np->port;
8407 if (dev->perm_addr[5] < val8)
8408 dev->perm_addr[4]++;
8409
8410 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8411}
8412
8413static int __devinit niu_pci_probe_sprom(struct niu *np)
8414{
8415 struct net_device *dev = np->dev;
8416 int len, i;
8417 u64 val, sum;
8418 u8 val8;
8419
8420 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8421 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8422 len = val / 4;
8423
8424 np->eeprom_len = len;
8425
8426 niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
8427
8428 sum = 0;
8429 for (i = 0; i < len; i++) {
8430 val = nr64(ESPC_NCR(i));
8431 sum += (val >> 0) & 0xff;
8432 sum += (val >> 8) & 0xff;
8433 sum += (val >> 16) & 0xff;
8434 sum += (val >> 24) & 0xff;
8435 }
8436 niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
8437 if ((sum & 0xff) != 0xab) {
8438 dev_err(np->device, PFX "Bad SPROM checksum "
8439 "(%x, should be 0xab)\n", (int) (sum & 0xff));
8440 return -EINVAL;
8441 }
8442
8443 val = nr64(ESPC_PHY_TYPE);
8444 switch (np->port) {
8445 case 0:
a9d41192 8446 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
a3138df9
DM		 8447 ESPC_PHY_TYPE_PORT0_SHIFT;
8448 break;
8449 case 1:
a9d41192 8450 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
a3138df9
DM		 8451 ESPC_PHY_TYPE_PORT1_SHIFT;
8452 break;
8453 case 2:
a9d41192 8454 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
a3138df9
DM		 8455 ESPC_PHY_TYPE_PORT2_SHIFT;
8456 break;
8457 case 3:
a9d41192 8458 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
a3138df9
DM		 8459 ESPC_PHY_TYPE_PORT3_SHIFT;
8460 break;
8461 default:
8462 dev_err(np->device, PFX "Bogus port number %u\n",
8463 np->port);
8464 return -EINVAL;
8465 }
a9d41192 8466 niudbg(PROBE, "SPROM: PHY type %x\n", val8);
a3138df9 8467
a9d41192 8468 switch (val8) {
a3138df9
DM		 8469 case ESPC_PHY_TYPE_1G_COPPER:
8470 /* 1G copper, MII */
8471 np->flags &= ~(NIU_FLAGS_FIBER |
8472 NIU_FLAGS_10G);
8473 np->mac_xcvr = MAC_XCVR_MII;
8474 break;
8475
8476 case ESPC_PHY_TYPE_1G_FIBER:
8477 /* 1G fiber, PCS */
8478 np->flags &= ~NIU_FLAGS_10G;
8479 np->flags |= NIU_FLAGS_FIBER;
8480 np->mac_xcvr = MAC_XCVR_PCS;
8481 break;
8482
8483 case ESPC_PHY_TYPE_10G_COPPER:
8484 /* 10G copper, XPCS */
8485 np->flags |= NIU_FLAGS_10G;
8486 np->flags &= ~NIU_FLAGS_FIBER;
8487 np->mac_xcvr = MAC_XCVR_XPCS;
8488 break;
8489
8490 case ESPC_PHY_TYPE_10G_FIBER:
8491 /* 10G fiber, XPCS */
8492 np->flags |= (NIU_FLAGS_10G |
8493 NIU_FLAGS_FIBER);
8494 np->mac_xcvr = MAC_XCVR_XPCS;
8495 break;
8496
8497 default:
a9d41192 8498 dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
a3138df9
DM		 8499 return -EINVAL;
8500 }
8501
8502 val = nr64(ESPC_MAC_ADDR0);
8503 niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
8504 (unsigned long long) val);
8505 dev->perm_addr[0] = (val >> 0) & 0xff;
8506 dev->perm_addr[1] = (val >> 8) & 0xff;
8507 dev->perm_addr[2] = (val >> 16) & 0xff;
8508 dev->perm_addr[3] = (val >> 24) & 0xff;
8509
8510 val = nr64(ESPC_MAC_ADDR1);
8511 niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
8512 (unsigned long long) val);
8513 dev->perm_addr[4] = (val >> 0) & 0xff;
8514 dev->perm_addr[5] = (val >> 8) & 0xff;
8515
8516 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8517 dev_err(np->device, PFX "SPROM MAC address invalid\n");
8518 dev_err(np->device, PFX "[ \n");
8519 for (i = 0; i < 6; i++)
8520 printk("%02x ", dev->perm_addr[i]);
8521 printk("]\n");
8522 return -EINVAL;
8523 }
8524
8525 val8 = dev->perm_addr[5];
8526 dev->perm_addr[5] += np->port;
8527 if (dev->perm_addr[5] < val8)
8528 dev->perm_addr[4]++;
8529
8530 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8531
8532 val = nr64(ESPC_MOD_STR_LEN);
8533 niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
8534 (unsigned long long) val);
e6a5fdf5 8535 if (val >= 8 * 4)
a3138df9
DM		 8536 return -EINVAL;
8537
8538 for (i = 0; i < val; i += 4) {
8539 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8540
8541 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
8542 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
8543 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8544 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8545 }
8546 np->vpd.model[val] = '\0';
8547
8548 val = nr64(ESPC_BD_MOD_STR_LEN);
8549 niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
8550 (unsigned long long) val);
e6a5fdf5 8551 if (val >= 4 * 4)
a3138df9
DM		 8552 return -EINVAL;
8553
8554 for (i = 0; i < val; i += 4) {
8555 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8556
8557 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
8558 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
8559 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8560 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8561 }
8562 np->vpd.board_model[val] = '\0';
8563
8564 np->vpd.mac_num =
8565 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8566 niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
8567 np->vpd.mac_num);
8568
8569 return 0;
8570}
8571
8572static int __devinit niu_get_and_validate_port(struct niu *np)
8573{
8574 struct niu_parent *parent = np->parent;
8575
8576 if (np->port <= 1)
8577 np->flags |= NIU_FLAGS_XMAC;
8578
8579 if (!parent->num_ports) {
8580 if (parent->plat_type == PLAT_TYPE_NIU) {
8581 parent->num_ports = 2;
8582 } else {
7f7c4072
MW		 8583 parent->num_ports = niu_pci_vpd_get_nports(np);
8584 if (!parent->num_ports) {
8585 /* Fall back to SPROM as last resort.
8586 * This will fail on most cards.
8587 */
8588 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8589 ESPC_NUM_PORTS_MACS_VAL;
8590
be0c007a
DM		 8591 /* All of the current probing methods fail on
8592 * Maramba on-board parts.
8593 */
7f7c4072 8594 if (!parent->num_ports)
be0c007a 8595 parent->num_ports = 4;
7f7c4072 8596 }
a3138df9
DM		 8597 }
8598 }
8599
8600 niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
8601 np->port, parent->num_ports);
8602 if (np->port >= parent->num_ports)
8603 return -ENODEV;
8604
8605 return 0;
8606}
8607
8608static int __devinit phy_record(struct niu_parent *parent,
8609 struct phy_probe_info *p,
8610 int dev_id_1, int dev_id_2, u8 phy_port,
8611 int type)
8612{
8613 u32 id = (dev_id_1 << 16) | dev_id_2;
8614 u8 idx;
8615
8616 if (dev_id_1 < 0 || dev_id_2 < 0)
8617 return 0;
8618 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
b0de8e40 8619 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
a5d6ab56
MW		 8620 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
8621 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
a3138df9
DM		 8622 return 0;
8623 } else {
8624 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8625 return 0;
8626 }
8627
8628 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8629 parent->index, id,
8630 (type == PHY_TYPE_PMA_PMD ?
8631 "PMA/PMD" :
8632 (type == PHY_TYPE_PCS ?
8633 "PCS" : "MII")),
8634 phy_port);
8635
8636 if (p->cur[type] >= NIU_MAX_PORTS) {
8637 printk(KERN_ERR PFX "Too many PHY ports.\n");
8638 return -EINVAL;
8639 }
8640 idx = p->cur[type];
8641 p->phy_id[type][idx] = id;
8642 p->phy_port[type][idx] = phy_port;
8643 p->cur[type] = idx + 1;
8644 return 0;
8645}
8646
8647static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8648{
8649 int i;
8650
8651 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8652 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8653 return 1;
8654 }
8655 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8656 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8657 return 1;
8658 }
8659
8660 return 0;
8661}
8662
8663static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8664{
8665 int port, cnt;
8666
8667 cnt = 0;
8668 *lowest = 32;
8669 for (port = 8; port < 32; port++) {
8670 if (port_has_10g(p, port)) {
8671 if (!cnt)
8672 *lowest = port;
8673 cnt++;
8674 }
8675 }
8676
8677 return cnt;
8678}
8679
8680static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8681{
8682 *lowest = 32;
8683 if (p->cur[PHY_TYPE_MII])
8684 *lowest = p->phy_port[PHY_TYPE_MII][0];
8685
8686 return p->cur[PHY_TYPE_MII];
8687}
8688
8689static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8690{
8691 int num_ports = parent->num_ports;
8692 int i;
8693
8694 for (i = 0; i < num_ports; i++) {
8695 parent->rxchan_per_port[i] = (16 / num_ports);
8696 parent->txchan_per_port[i] = (16 / num_ports);
8697
8698 pr_info(PFX "niu%d: Port %u [%u RX chans] "
8699 "[%u TX chans]\n",
8700 parent->index, i,
8701 parent->rxchan_per_port[i],
8702 parent->txchan_per_port[i]);
8703 }
8704}
8705
8706static void __devinit niu_divide_channels(struct niu_parent *parent,
8707 int num_10g, int num_1g)
8708{
8709 int num_ports = parent->num_ports;
8710 int rx_chans_per_10g, rx_chans_per_1g;
8711 int tx_chans_per_10g, tx_chans_per_1g;
8712 int i, tot_rx, tot_tx;
8713
8714 if (!num_10g || !num_1g) {
8715 rx_chans_per_10g = rx_chans_per_1g =
8716 (NIU_NUM_RXCHAN / num_ports);
8717 tx_chans_per_10g = tx_chans_per_1g =
8718 (NIU_NUM_TXCHAN / num_ports);
8719 } else {
8720 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8721 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8722 (rx_chans_per_1g * num_1g)) /
8723 num_10g;
8724
8725 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8726 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8727 (tx_chans_per_1g * num_1g)) /
8728 num_10g;
8729 }
8730
8731 tot_rx = tot_tx = 0;
8732 for (i = 0; i < num_ports; i++) {
8733 int type = phy_decode(parent->port_phy, i);
8734
8735 if (type == PORT_TYPE_10G) {
8736 parent->rxchan_per_port[i] = rx_chans_per_10g;
8737 parent->txchan_per_port[i] = tx_chans_per_10g;
8738 } else {
8739 parent->rxchan_per_port[i] = rx_chans_per_1g;
8740 parent->txchan_per_port[i] = tx_chans_per_1g;
8741 }
8742 pr_info(PFX "niu%d: Port %u [%u RX chans] "
8743 "[%u TX chans]\n",
8744 parent->index, i,
8745 parent->rxchan_per_port[i],
8746 parent->txchan_per_port[i]);
8747 tot_rx += parent->rxchan_per_port[i];
8748 tot_tx += parent->txchan_per_port[i];
8749 }
8750
8751 if (tot_rx > NIU_NUM_RXCHAN) {
8752 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
8753 "resetting to one per port.\n",
8754 parent->index, tot_rx);
8755 for (i = 0; i < num_ports; i++)
8756 parent->rxchan_per_port[i] = 1;
8757 }
8758 if (tot_tx > NIU_NUM_TXCHAN) {
8759 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
8760 "resetting to one per port.\n",
8761 parent->index, tot_tx);
8762 for (i = 0; i < num_ports; i++)
8763 parent->txchan_per_port[i] = 1;
8764 }
8765 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8766 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
8767 "RX[%d] TX[%d]\n",
8768 parent->index, tot_rx, tot_tx);
8769 }
8770}
8771
8772static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8773 int num_10g, int num_1g)
8774{
8775 int i, num_ports = parent->num_ports;
8776 int rdc_group, rdc_groups_per_port;
8777 int rdc_channel_base;
8778
8779 rdc_group = 0;
8780 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8781
8782 rdc_channel_base = 0;
8783
8784 for (i = 0; i < num_ports; i++) {
8785 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8786 int grp, num_channels = parent->rxchan_per_port[i];
8787 int this_channel_offset;
8788
8789 tp->first_table_num = rdc_group;
8790 tp->num_tables = rdc_groups_per_port;
8791 this_channel_offset = 0;
8792 for (grp = 0; grp < tp->num_tables; grp++) {
8793 struct rdc_table *rt = &tp->tables[grp];
8794 int slot;
8795
8796 pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
8797 parent->index, i, tp->first_table_num + grp);
8798 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8799 rt->rxdma_channel[slot] =
8800 rdc_channel_base + this_channel_offset;
8801
8802 printk("%d ", rt->rxdma_channel[slot]);
8803
8804 if (++this_channel_offset == num_channels)
8805 this_channel_offset = 0;
8806 }
8807 printk("]\n");
8808 }
8809
8810 parent->rdc_default[i] = rdc_channel_base;
8811
8812 rdc_channel_base += num_channels;
8813 rdc_group += rdc_groups_per_port;
8814 }
8815}
8816
8817static int __devinit fill_phy_probe_info(struct niu *np,
8818 struct niu_parent *parent,
8819 struct phy_probe_info *info)
8820{
8821 unsigned long flags;
8822 int port, err;
8823
8824 memset(info, 0, sizeof(*info));
8825
8826 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8827 niu_lock_parent(np, flags);
8828 err = 0;
8829 for (port = 8; port < 32; port++) {
8830 int dev_id_1, dev_id_2;
8831
8832 dev_id_1 = mdio_read(np, port,
8833 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8834 dev_id_2 = mdio_read(np, port,
8835 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8836 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8837 PHY_TYPE_PMA_PMD);
8838 if (err)
8839 break;
8840 dev_id_1 = mdio_read(np, port,
8841 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8842 dev_id_2 = mdio_read(np, port,
8843 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8844 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8845 PHY_TYPE_PCS);
8846 if (err)
8847 break;
8848 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8849 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8850 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8851 PHY_TYPE_MII);
8852 if (err)
8853 break;
8854 }
8855 niu_unlock_parent(np, flags);
8856
8857 return err;
8858}
8859
8860static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8861{
8862 struct phy_probe_info *info = &parent->phy_probe_info;
8863 int lowest_10g, lowest_1g;
8864 int num_10g, num_1g;
8865 u32 val;
8866 int err;
8867
e3e081e1
SB		 8868 num_10g = num_1g = 0;
8869
f9af8574
MW		 8870 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8871 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8872 num_10g = 0;
8873 num_1g = 2;
8874 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8875 parent->num_ports = 4;
8876 val = (phy_encode(PORT_TYPE_1G, 0) |
8877 phy_encode(PORT_TYPE_1G, 1) |
a3138df9
DM		 8878 phy_encode(PORT_TYPE_1G, 2) |
8879 phy_encode(PORT_TYPE_1G, 3));
f9af8574 8880 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8881 num_10g = 2;
8882 num_1g = 0;
8883 parent->num_ports = 2;
8884 val = (phy_encode(PORT_TYPE_10G, 0) |
8885 phy_encode(PORT_TYPE_10G, 1));
e3e081e1
SB		 8886 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8887 (parent->plat_type == PLAT_TYPE_NIU)) {
8888 /* this is the Monza case */
8889 if (np->flags & NIU_FLAGS_10G) {
8890 val = (phy_encode(PORT_TYPE_10G, 0) |
8891 phy_encode(PORT_TYPE_10G, 1));
8892 } else {
8893 val = (phy_encode(PORT_TYPE_1G, 0) |
8894 phy_encode(PORT_TYPE_1G, 1));
8895 }
5fbd7e24
MW		 8896 } else {
8897 err = fill_phy_probe_info(np, parent, info);
8898 if (err)
8899 return err;
a3138df9 8900
5fbd7e24
MW		 8901 num_10g = count_10g_ports(info, &lowest_10g);
8902 num_1g = count_1g_ports(info, &lowest_1g);
a3138df9 8903
5fbd7e24
MW		 8904 switch ((num_10g << 4) | num_1g) {
8905 case 0x24:
8906 if (lowest_1g == 10)
8907 parent->plat_type = PLAT_TYPE_VF_P0;
8908 else if (lowest_1g == 26)
8909 parent->plat_type = PLAT_TYPE_VF_P1;
8910 else
8911 goto unknown_vg_1g_port;
a3138df9 8912
5fbd7e24
MW		 8913 /* fallthru */
8914 case 0x22:
a3138df9 8915 val = (phy_encode(PORT_TYPE_10G, 0) |
a3138df9
DM		 8916 phy_encode(PORT_TYPE_10G, 1) |
8917 phy_encode(PORT_TYPE_1G, 2) |
8918 phy_encode(PORT_TYPE_1G, 3));
5fbd7e24 8919 break;
a3138df9 8920
5fbd7e24
MW		 8921 case 0x20:
8922 val = (phy_encode(PORT_TYPE_10G, 0) |
8923 phy_encode(PORT_TYPE_10G, 1));
8924 break;
a3138df9 8925
5fbd7e24
MW		 8926 case 0x10:
8927 val = phy_encode(PORT_TYPE_10G, np->port);
8928 break;
a3138df9 8929
5fbd7e24
MW		 8930 case 0x14:
8931 if (lowest_1g == 10)
8932 parent->plat_type = PLAT_TYPE_VF_P0;
8933 else if (lowest_1g == 26)
8934 parent->plat_type = PLAT_TYPE_VF_P1;
8935 else
8936 goto unknown_vg_1g_port;
8937
8938 /* fallthru */
8939 case 0x13:
8940 if ((lowest_10g & 0x7) == 0)
8941 val = (phy_encode(PORT_TYPE_10G, 0) |
8942 phy_encode(PORT_TYPE_1G, 1) |
8943 phy_encode(PORT_TYPE_1G, 2) |
8944 phy_encode(PORT_TYPE_1G, 3));
8945 else
8946 val = (phy_encode(PORT_TYPE_1G, 0) |
8947 phy_encode(PORT_TYPE_10G, 1) |
8948 phy_encode(PORT_TYPE_1G, 2) |
8949 phy_encode(PORT_TYPE_1G, 3));
8950 break;
8951
8952 case 0x04:
8953 if (lowest_1g == 10)
8954 parent->plat_type = PLAT_TYPE_VF_P0;
8955 else if (lowest_1g == 26)
8956 parent->plat_type = PLAT_TYPE_VF_P1;
8957 else
8958 goto unknown_vg_1g_port;
8959
8960 val = (phy_encode(PORT_TYPE_1G, 0) |
8961 phy_encode(PORT_TYPE_1G, 1) |
8962 phy_encode(PORT_TYPE_1G, 2) |
8963 phy_encode(PORT_TYPE_1G, 3));
8964 break;
8965
8966 default:
8967 printk(KERN_ERR PFX "Unsupported port config "
8968 "10G[%d] 1G[%d]\n",
8969 num_10g, num_1g);
8970 return -EINVAL;
8971 }
a3138df9
DM		 8972 }
8973
8974 parent->port_phy = val;
8975
8976 if (parent->plat_type == PLAT_TYPE_NIU)
8977 niu_n2_divide_channels(parent);
8978 else
8979 niu_divide_channels(parent, num_10g, num_1g);
8980
8981 niu_divide_rdc_groups(parent, num_10g, num_1g);
8982
8983 return 0;
8984
8985unknown_vg_1g_port:
8986 printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
8987 lowest_1g);
8988 return -EINVAL;
8989}
8990
8991static int __devinit niu_probe_ports(struct niu *np)
8992{
8993 struct niu_parent *parent = np->parent;
8994 int err, i;
8995
8996 niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
8997 parent->port_phy);
8998
8999 if (parent->port_phy == PORT_PHY_UNKNOWN) {
9000 err = walk_phys(np, parent);
9001 if (err)
9002 return err;
9003
9004 niu_set_ldg_timer_res(np, 2);
9005 for (i = 0; i <= LDN_MAX; i++)
9006 niu_ldn_irq_enable(np, i, 0);
9007 }
9008
9009 if (parent->port_phy == PORT_PHY_INVALID)
9010 return -EINVAL;
9011
9012 return 0;
9013}
9014
9015static int __devinit niu_classifier_swstate_init(struct niu *np)
9016{
9017 struct niu_classifier *cp = &np->clas;
9018
9019 niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
9020 np->parent->tcam_num_entries);
9021
2d96cf8c
SB		 9022 cp->tcam_top = (u16) np->port;
9023 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
a3138df9
DM		 9024 cp->h1_init = 0xffffffff;
9025 cp->h2_init = 0xffff;
9026
9027 return fflp_early_init(np);
9028}
9029
9030static void __devinit niu_link_config_init(struct niu *np)
9031{
9032 struct niu_link_config *lp = &np->link_config;
9033
9034 lp->advertising = (ADVERTISED_10baseT_Half |
9035 ADVERTISED_10baseT_Full |
9036 ADVERTISED_100baseT_Half |
9037 ADVERTISED_100baseT_Full |
9038 ADVERTISED_1000baseT_Half |
9039 ADVERTISED_1000baseT_Full |
9040 ADVERTISED_10000baseT_Full |
9041 ADVERTISED_Autoneg);
9042 lp->speed = lp->active_speed = SPEED_INVALID;
38bb045d
CB		 9043 lp->duplex = DUPLEX_FULL;
9044 lp->active_duplex = DUPLEX_INVALID;
9045 lp->autoneg = 1;
a3138df9
DM		 9046#if 0
9047 lp->loopback_mode = LOOPBACK_MAC;
9048 lp->active_speed = SPEED_10000;
9049 lp->active_duplex = DUPLEX_FULL;
9050#else
9051 lp->loopback_mode = LOOPBACK_DISABLED;
9052#endif
9053}
9054
9055static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
9056{
9057 switch (np->port) {
9058 case 0:
9059 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9060 np->ipp_off = 0x00000;
9061 np->pcs_off = 0x04000;
9062 np->xpcs_off = 0x02000;
9063 break;
9064
9065 case 1:
9066 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9067 np->ipp_off = 0x08000;
9068 np->pcs_off = 0x0a000;
9069 np->xpcs_off = 0x08000;
9070 break;
9071
9072 case 2:
9073 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9074 np->ipp_off = 0x04000;
9075 np->pcs_off = 0x0e000;
9076 np->xpcs_off = ~0UL;
9077 break;
9078
9079 case 3:
9080 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9081 np->ipp_off = 0x0c000;
9082 np->pcs_off = 0x12000;
9083 np->xpcs_off = ~0UL;
9084 break;
9085
9086 default:
9087 dev_err(np->device, PFX "Port %u is invalid, cannot "
9088 "compute MAC block offset.\n", np->port);
9089 return -EINVAL;
9090 }
9091
9092 return 0;
9093}
9094
9095static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9096{
9097 struct msix_entry msi_vec[NIU_NUM_LDG];
9098 struct niu_parent *parent = np->parent;
9099 struct pci_dev *pdev = np->pdev;
9100 int i, num_irqs, err;
9101 u8 first_ldg;
9102
9103 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9104 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9105 ldg_num_map[i] = first_ldg + i;
9106
9107 num_irqs = (parent->rxchan_per_port[np->port] +
9108 parent->txchan_per_port[np->port] +
9109 (np->port == 0 ? 3 : 1));
9110 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9111
9112retry:
9113 for (i = 0; i < num_irqs; i++) {
9114 msi_vec[i].vector = 0;
9115 msi_vec[i].entry = i;
9116 }
9117
9118 err = pci_enable_msix(pdev, msi_vec, num_irqs);
9119 if (err < 0) {
9120 np->flags &= ~NIU_FLAGS_MSIX;
9121 return;
9122 }
9123 if (err > 0) {
9124 num_irqs = err;
9125 goto retry;
9126 }
9127
9128 np->flags |= NIU_FLAGS_MSIX;
9129 for (i = 0; i < num_irqs; i++)
9130 np->ldg[i].irq = msi_vec[i].vector;
9131 np->num_ldg = num_irqs;
9132}
9133
9134static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9135{
9136#ifdef CONFIG_SPARC64
9137 struct of_device *op = np->op;
9138 const u32 *int_prop;
9139 int i;
9140
9141 int_prop = of_get_property(op->node, "interrupts", NULL);
9142 if (!int_prop)
9143 return -ENODEV;
9144
9145 for (i = 0; i < op->num_irqs; i++) {
9146 ldg_num_map[i] = int_prop[i];
9147 np->ldg[i].irq = op->irqs[i];
9148 }
9149
9150 np->num_ldg = op->num_irqs;
9151
9152 return 0;
9153#else
9154 return -EINVAL;
9155#endif
9156}
9157
9158static int __devinit niu_ldg_init(struct niu *np)
9159{
9160 struct niu_parent *parent = np->parent;
9161 u8 ldg_num_map[NIU_NUM_LDG];
9162 int first_chan, num_chan;
9163 int i, err, ldg_rotor;
9164 u8 port;
9165
9166 np->num_ldg = 1;
9167 np->ldg[0].irq = np->dev->irq;
9168 if (parent->plat_type == PLAT_TYPE_NIU) {
9169 err = niu_n2_irq_init(np, ldg_num_map);
9170 if (err)
9171 return err;
9172 } else
9173 niu_try_msix(np, ldg_num_map);
9174
9175 port = np->port;
9176 for (i = 0; i < np->num_ldg; i++) {
9177 struct niu_ldg *lp = &np->ldg[i];
9178
9179 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9180
9181 lp->np = np;
9182 lp->ldg_num = ldg_num_map[i];
9183 lp->timer = 2; /* XXX */
9184
9185 /* On N2 NIU the firmware has setup the SID mappings so they go
9186 * to the correct values that will route the LDG to the proper
9187 * interrupt in the NCU interrupt table.
9188 */
9189 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9190 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9191 if (err)
9192 return err;
9193 }
9194 }
9195
9196 /* We adopt the LDG assignment ordering used by the N2 NIU
9197 * 'interrupt' properties because that simplifies a lot of
9198 * things. This ordering is:
9199 *
9200 * MAC
9201 * MIF (if port zero)
9202 * SYSERR (if port zero)
9203 * RX channels
9204 * TX channels
9205 */
9206
9207 ldg_rotor = 0;
9208
9209 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9210 LDN_MAC(port));
9211 if (err)
9212 return err;
9213
9214 ldg_rotor++;
9215 if (ldg_rotor == np->num_ldg)
9216 ldg_rotor = 0;
9217
9218 if (port == 0) {
9219 err = niu_ldg_assign_ldn(np, parent,
9220 ldg_num_map[ldg_rotor],
9221 LDN_MIF);
9222 if (err)
9223 return err;
9224
9225 ldg_rotor++;
9226 if (ldg_rotor == np->num_ldg)
9227 ldg_rotor = 0;
9228
9229 err = niu_ldg_assign_ldn(np, parent,
9230 ldg_num_map[ldg_rotor],
9231 LDN_DEVICE_ERROR);
9232 if (err)
9233 return err;
9234
9235 ldg_rotor++;
9236 if (ldg_rotor == np->num_ldg)
9237 ldg_rotor = 0;
9238
9239 }
9240
9241 first_chan = 0;
9242 for (i = 0; i < port; i++)
9243 first_chan += parent->rxchan_per_port[port];
9244 num_chan = parent->rxchan_per_port[port];
9245
9246 for (i = first_chan; i < (first_chan + num_chan); i++) {
9247 err = niu_ldg_assign_ldn(np, parent,
9248 ldg_num_map[ldg_rotor],
9249 LDN_RXDMA(i));
9250 if (err)
9251 return err;
9252 ldg_rotor++;
9253 if (ldg_rotor == np->num_ldg)
9254 ldg_rotor = 0;
9255 }
9256
9257 first_chan = 0;
9258 for (i = 0; i < port; i++)
9259 first_chan += parent->txchan_per_port[port];
9260 num_chan = parent->txchan_per_port[port];
9261 for (i = first_chan; i < (first_chan + num_chan); i++) {
9262 err = niu_ldg_assign_ldn(np, parent,
9263 ldg_num_map[ldg_rotor],
9264 LDN_TXDMA(i));
9265 if (err)
9266 return err;
9267 ldg_rotor++;
9268 if (ldg_rotor == np->num_ldg)
9269 ldg_rotor = 0;
9270 }
9271
9272 return 0;
9273}
9274
9275static void __devexit niu_ldg_free(struct niu *np)
9276{
9277 if (np->flags & NIU_FLAGS_MSIX)
9278 pci_disable_msix(np->pdev);
9279}
9280
9281static int __devinit niu_get_of_props(struct niu *np)
9282{
9283#ifdef CONFIG_SPARC64
9284 struct net_device *dev = np->dev;
9285 struct device_node *dp;
9286 const char *phy_type;
9287 const u8 *mac_addr;
f9af8574 9288 const char *model;
a3138df9
DM		 9289 int prop_len;
9290
9291 if (np->parent->plat_type == PLAT_TYPE_NIU)
9292 dp = np->op->node;
9293 else
9294 dp = pci_device_to_OF_node(np->pdev);
9295
9296 phy_type = of_get_property(dp, "phy-type", &prop_len);
9297 if (!phy_type) {
9298 dev_err(np->device, PFX "%s: OF node lacks "
9299 "phy-type property\n",
9300 dp->full_name);
9301 return -EINVAL;
9302 }
9303
9304 if (!strcmp(phy_type, "none"))
9305 return -ENODEV;
9306
9307 strcpy(np->vpd.phy_type, phy_type);
9308
9309 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
9310 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
9311 dp->full_name, np->vpd.phy_type);
9312 return -EINVAL;
9313 }
9314
9315 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9316 if (!mac_addr) {
9317 dev_err(np->device, PFX "%s: OF node lacks "
9318 "local-mac-address property\n",
9319 dp->full_name);
9320 return -EINVAL;
9321 }
9322 if (prop_len != dev->addr_len) {
9323 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
9324 "is wrong.\n",
9325 dp->full_name, prop_len);
9326 }
9327 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9328 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
9329 int i;
9330
9331 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
9332 dp->full_name);
9333 dev_err(np->device, PFX "%s: [ \n",
9334 dp->full_name);
9335 for (i = 0; i < 6; i++)
9336 printk("%02x ", dev->perm_addr[i]);
9337 printk("]\n");
9338 return -EINVAL;
9339 }
9340
9341 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
f9af8574
MW		 9342
9343 model = of_get_property(dp, "model", &prop_len);
9344
9345 if (model)
9346 strcpy(np->vpd.model, model);
a3138df9
DM		 9347
9348 return 0;
9349#else
9350 return -EINVAL;
9351#endif
9352}
9353
9354static int __devinit niu_get_invariants(struct niu *np)
9355{
9356 int err, have_props;
9357 u32 offset;
9358
9359 err = niu_get_of_props(np);
9360 if (err == -ENODEV)
9361 return err;
9362
9363 have_props = !err;
9364
a3138df9
DM		 9365 err = niu_init_mac_ipp_pcs_base(np);
9366 if (err)
9367 return err;
9368
7f7c4072
MW		 9369 if (have_props) {
9370 err = niu_get_and_validate_port(np);
9371 if (err)
9372 return err;
9373
9374 } else {
a3138df9
DM		 9375 if (np->parent->plat_type == PLAT_TYPE_NIU)
9376 return -EINVAL;
9377
9378 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9379 offset = niu_pci_vpd_offset(np);
9380 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
9381 offset);
9382 if (offset)
9383 niu_pci_vpd_fetch(np, offset);
9384 nw64(ESPC_PIO_EN, 0);
9385
7f7c4072 9386 if (np->flags & NIU_FLAGS_VPD_VALID) {
a3138df9 9387 niu_pci_vpd_validate(np);
7f7c4072
MW		 9388 err = niu_get_and_validate_port(np);
9389 if (err)
9390 return err;
9391 }
a3138df9
DM		 9392
9393 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
7f7c4072
MW		 9394 err = niu_get_and_validate_port(np);
9395 if (err)
9396 return err;
a3138df9
DM		 9397 err = niu_pci_probe_sprom(np);
9398 if (err)
9399 return err;
9400 }
9401 }
9402
9403 err = niu_probe_ports(np);
9404 if (err)
9405 return err;
9406
9407 niu_ldg_init(np);
9408
9409 niu_classifier_swstate_init(np);
9410 niu_link_config_init(np);
9411
9412 err = niu_determine_phy_disposition(np);
9413 if (!err)
9414 err = niu_init_link(np);
9415
9416 return err;
9417}
9418
9419static LIST_HEAD(niu_parent_list);
9420static DEFINE_MUTEX(niu_parent_lock);
9421static int niu_parent_index;
9422
9423static ssize_t show_port_phy(struct device *dev,
9424 struct device_attribute *attr, char *buf)
9425{
9426 struct platform_device *plat_dev = to_platform_device(dev);
9427 struct niu_parent *p = plat_dev->dev.platform_data;
9428 u32 port_phy = p->port_phy;
9429 char *orig_buf = buf;
9430 int i;
9431
9432 if (port_phy == PORT_PHY_UNKNOWN ||
9433 port_phy == PORT_PHY_INVALID)
9434 return 0;
9435
9436 for (i = 0; i < p->num_ports; i++) {
9437 const char *type_str;
9438 int type;
9439
9440 type = phy_decode(port_phy, i);
9441 if (type == PORT_TYPE_10G)
9442 type_str = "10G";
9443 else
9444 type_str = "1G";
9445 buf += sprintf(buf,
9446 (i == 0) ? "%s" : " %s",
9447 type_str);
9448 }
9449 buf += sprintf(buf, "\n");
9450 return buf - orig_buf;
9451}
9452
9453static ssize_t show_plat_type(struct device *dev,
9454 struct device_attribute *attr, char *buf)
9455{
9456 struct platform_device *plat_dev = to_platform_device(dev);
9457 struct niu_parent *p = plat_dev->dev.platform_data;
9458 const char *type_str;
9459
9460 switch (p->plat_type) {
9461 case PLAT_TYPE_ATLAS:
9462 type_str = "atlas";
9463 break;
9464 case PLAT_TYPE_NIU:
9465 type_str = "niu";
9466 break;
9467 case PLAT_TYPE_VF_P0:
9468 type_str = "vf_p0";
9469 break;
9470 case PLAT_TYPE_VF_P1:
9471 type_str = "vf_p1";
9472 break;
9473 default:
9474 type_str = "unknown";
9475 break;
9476 }
9477
9478 return sprintf(buf, "%s\n", type_str);
9479}
9480
9481static ssize_t __show_chan_per_port(struct device *dev,
9482 struct device_attribute *attr, char *buf,
9483 int rx)
9484{
9485 struct platform_device *plat_dev = to_platform_device(dev);
9486 struct niu_parent *p = plat_dev->dev.platform_data;
9487 char *orig_buf = buf;
9488 u8 *arr;
9489 int i;
9490
9491 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9492
9493 for (i = 0; i < p->num_ports; i++) {
9494 buf += sprintf(buf,
9495 (i == 0) ? "%d" : " %d",
9496 arr[i]);
9497 }
9498 buf += sprintf(buf, "\n");
9499
9500 return buf - orig_buf;
9501}
9502
9503static ssize_t show_rxchan_per_port(struct device *dev,
9504 struct device_attribute *attr, char *buf)
9505{
9506 return __show_chan_per_port(dev, attr, buf, 1);
9507}
9508
9509static ssize_t show_txchan_per_port(struct device *dev,
9510 struct device_attribute *attr, char *buf)
9511{
9512 return __show_chan_per_port(dev, attr, buf, 1);
9513}
9514
9515static ssize_t show_num_ports(struct device *dev,
9516 struct device_attribute *attr, char *buf)
9517{
9518 struct platform_device *plat_dev = to_platform_device(dev);
9519 struct niu_parent *p = plat_dev->dev.platform_data;
9520
9521 return sprintf(buf, "%d\n", p->num_ports);
9522}
9523
9524static struct device_attribute niu_parent_attributes[] = {
9525 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9526 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9527 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9528 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9529 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9530 {}
9531};
9532
9533static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9534 union niu_parent_id *id,
9535 u8 ptype)
9536{
9537 struct platform_device *plat_dev;
9538 struct niu_parent *p;
9539 int i;
9540
9541 niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
9542
9543 plat_dev = platform_device_register_simple("niu", niu_parent_index,
9544 NULL, 0);
9545 if (!plat_dev)
9546 return NULL;
9547
9548 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9549 int err = device_create_file(&plat_dev->dev,
9550 &niu_parent_attributes[i]);
9551 if (err)
9552 goto fail_unregister;
9553 }
9554
9555 p = kzalloc(sizeof(*p), GFP_KERNEL);
9556 if (!p)
9557 goto fail_unregister;
9558
9559 p->index = niu_parent_index++;
9560
9561 plat_dev->dev.platform_data = p;
9562 p->plat_dev = plat_dev;
9563
9564 memcpy(&p->id, id, sizeof(*id));
9565 p->plat_type = ptype;
9566 INIT_LIST_HEAD(&p->list);
9567 atomic_set(&p->refcnt, 0);
9568 list_add(&p->list, &niu_parent_list);
9569 spin_lock_init(&p->lock);
9570
9571 p->rxdma_clock_divider = 7500;
9572
9573 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9574 if (p->plat_type == PLAT_TYPE_NIU)
9575 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9576
9577 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9578 int index = i - CLASS_CODE_USER_PROG1;
9579
9580 p->tcam_key[index] = TCAM_KEY_TSEL;
9581 p->flow_key[index] = (FLOW_KEY_IPSA |
9582 FLOW_KEY_IPDA |
9583 FLOW_KEY_PROTO |
9584 (FLOW_KEY_L4_BYTE12 <<
9585 FLOW_KEY_L4_0_SHIFT) |
9586 (FLOW_KEY_L4_BYTE12 <<
9587 FLOW_KEY_L4_1_SHIFT));
9588 }
9589
9590 for (i = 0; i < LDN_MAX + 1; i++)
9591 p->ldg_map[i] = LDG_INVALID;
9592
9593 return p;
9594
9595fail_unregister:
9596 platform_device_unregister(plat_dev);
9597 return NULL;
9598}
9599
9600static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9601 union niu_parent_id *id,
9602 u8 ptype)
9603{
9604 struct niu_parent *p, *tmp;
9605 int port = np->port;
9606
9607 niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
9608 ptype, port);
9609
9610 mutex_lock(&niu_parent_lock);
9611 p = NULL;
9612 list_for_each_entry(tmp, &niu_parent_list, list) {
9613 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9614 p = tmp;
9615 break;
9616 }
9617 }
9618 if (!p)
9619 p = niu_new_parent(np, id, ptype);
9620
9621 if (p) {
9622 char port_name[6];
9623 int err;
9624
9625 sprintf(port_name, "port%d", port);
9626 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9627 &np->device->kobj,
9628 port_name);
9629 if (!err) {
9630 p->ports[port] = np;
9631 atomic_inc(&p->refcnt);
9632 }
9633 }
9634 mutex_unlock(&niu_parent_lock);
9635
9636 return p;
9637}
9638
9639static void niu_put_parent(struct niu *np)
9640{
9641 struct niu_parent *p = np->parent;
9642 u8 port = np->port;
9643 char port_name[6];
9644
9645 BUG_ON(!p || p->ports[port] != np);
9646
9647 niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
9648
9649 sprintf(port_name, "port%d", port);
9650
9651 mutex_lock(&niu_parent_lock);
9652
9653 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9654
9655 p->ports[port] = NULL;
9656 np->parent = NULL;
9657
9658 if (atomic_dec_and_test(&p->refcnt)) {
9659 list_del(&p->list);
9660 platform_device_unregister(p->plat_dev);
9661 }
9662
9663 mutex_unlock(&niu_parent_lock);
9664}
9665
9666static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9667 u64 *handle, gfp_t flag)
9668{
9669 dma_addr_t dh;
9670 void *ret;
9671
9672 ret = dma_alloc_coherent(dev, size, &dh, flag);
9673 if (ret)
9674 *handle = dh;
9675 return ret;
9676}
9677
9678static void niu_pci_free_coherent(struct device *dev, size_t size,
9679 void *cpu_addr, u64 handle)
9680{
9681 dma_free_coherent(dev, size, cpu_addr, handle);
9682}
9683
9684static u64 niu_pci_map_page(struct device *dev, struct page *page,
9685 unsigned long offset, size_t size,
9686 enum dma_data_direction direction)
9687{
9688 return dma_map_page(dev, page, offset, size, direction);
9689}
9690
9691static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9692 size_t size, enum dma_data_direction direction)
9693{
a08b32df 9694 dma_unmap_page(dev, dma_address, size, direction);
a3138df9
DM		 9695}
9696
9697static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9698 size_t size,
9699 enum dma_data_direction direction)
9700{
9701 return dma_map_single(dev, cpu_addr, size, direction);
9702}
9703
9704static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9705 size_t size,
9706 enum dma_data_direction direction)
9707{
9708 dma_unmap_single(dev, dma_address, size, direction);
9709}
9710
9711static const struct niu_ops niu_pci_ops = {
9712 .alloc_coherent = niu_pci_alloc_coherent,
9713 .free_coherent = niu_pci_free_coherent,
9714 .map_page = niu_pci_map_page,
9715 .unmap_page = niu_pci_unmap_page,
9716 .map_single = niu_pci_map_single,
9717 .unmap_single = niu_pci_unmap_single,
9718};
9719
9720static void __devinit niu_driver_version(void)
9721{
9722 static int niu_version_printed;
9723
9724 if (niu_version_printed++ == 0)
9725 pr_info("%s", version);
9726}
9727
9728static struct net_device * __devinit niu_alloc_and_init(
9729 struct device *gen_dev, struct pci_dev *pdev,
9730 struct of_device *op, const struct niu_ops *ops,
9731 u8 port)
9732{
b4c21639 9733 struct net_device *dev;
a3138df9
DM		 9734 struct niu *np;
9735
b4c21639 9736 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
a3138df9
DM		 9737 if (!dev) {
9738 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
9739 return NULL;
9740 }
9741
9742 SET_NETDEV_DEV(dev, gen_dev);
9743
9744 np = netdev_priv(dev);
9745 np->dev = dev;
9746 np->pdev = pdev;
9747 np->op = op;
9748 np->device = gen_dev;
9749 np->ops = ops;
9750
9751 np->msg_enable = niu_debug;
9752
9753 spin_lock_init(&np->lock);
9754 INIT_WORK(&np->reset_task, niu_reset_task);
9755
9756 np->port = port;
9757
9758 return dev;
9759}
9760
2c9171d4
SH		 9761static const struct net_device_ops niu_netdev_ops = {
9762 .ndo_open = niu_open,
9763 .ndo_stop = niu_close,
00829823 9764 .ndo_start_xmit = niu_start_xmit,
2c9171d4
SH		 9765 .ndo_get_stats = niu_get_stats,
9766 .ndo_set_multicast_list = niu_set_rx_mode,
9767 .ndo_validate_addr = eth_validate_addr,
9768 .ndo_set_mac_address = niu_set_mac_addr,
9769 .ndo_do_ioctl = niu_ioctl,
9770 .ndo_tx_timeout = niu_tx_timeout,
9771 .ndo_change_mtu = niu_change_mtu,
9772};
9773
a3138df9
DM		 9774static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9775{
2c9171d4 9776 dev->netdev_ops = &niu_netdev_ops;
a3138df9
DM		 9777 dev->ethtool_ops = &niu_ethtool_ops;
9778 dev->watchdog_timeo = NIU_TX_TIMEOUT;
a3138df9
DM		 9779}
9780
9781static void __devinit niu_device_announce(struct niu *np)
9782{
9783 struct net_device *dev = np->dev;
a3138df9 9784
e174961c 9785 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
a3138df9 9786
5fbd7e24
MW		 9787 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9788 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9789 dev->name,
9790 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9791 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9792 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9793 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9794 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9795 np->vpd.phy_type);
9796 } else {
9797 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9798 dev->name,
9799 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9800 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
e3e081e1
SB		 9801 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9802 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9803 "COPPER")),
5fbd7e24
MW		 9804 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9805 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9806 np->vpd.phy_type);
9807 }
a3138df9
DM		 9808}
9809
9810static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9811 const struct pci_device_id *ent)
9812{
a3138df9
DM		 9813 union niu_parent_id parent_id;
9814 struct net_device *dev;
9815 struct niu *np;
9816 int err, pos;
9817 u64 dma_mask;
9818 u16 val16;
9819
9820 niu_driver_version();
9821
9822 err = pci_enable_device(pdev);
9823 if (err) {
9824 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
9825 "aborting.\n");
9826 return err;
9827 }
9828
9829 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9830 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9831 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
9832 "base addresses, aborting.\n");
9833 err = -ENODEV;
9834 goto err_out_disable_pdev;
9835 }
9836
9837 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9838 if (err) {
9839 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
9840 "aborting.\n");
9841 goto err_out_disable_pdev;
9842 }
9843
9844 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9845 if (pos <= 0) {
9846 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
9847 "aborting.\n");
9848 goto err_out_free_res;
9849 }
9850
9851 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9852 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9853 if (!dev) {
9854 err = -ENOMEM;
9855 goto err_out_free_res;
9856 }
9857 np = netdev_priv(dev);
9858
9859 memset(&parent_id, 0, sizeof(parent_id));
9860 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9861 parent_id.pci.bus = pdev->bus->number;
9862 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9863
9864 np->parent = niu_get_parent(np, &parent_id,
9865 PLAT_TYPE_ATLAS);
9866 if (!np->parent) {
9867 err = -ENOMEM;
9868 goto err_out_free_dev;
9869 }
9870
9871 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9872 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9873 val16 |= (PCI_EXP_DEVCTL_CERE |
9874 PCI_EXP_DEVCTL_NFERE |
9875 PCI_EXP_DEVCTL_FERE |
9876 PCI_EXP_DEVCTL_URRE |
9877 PCI_EXP_DEVCTL_RELAX_EN);
9878 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9879
9880 dma_mask = DMA_44BIT_MASK;
9881 err = pci_set_dma_mask(pdev, dma_mask);
9882 if (!err) {
9883 dev->features |= NETIF_F_HIGHDMA;
9884 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9885 if (err) {
9886 dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
9887 "DMA for consistent allocations, "
9888 "aborting.\n");
9889 goto err_out_release_parent;
9890 }
9891 }
9892 if (err || dma_mask == DMA_32BIT_MASK) {
9893 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
9894 if (err) {
9895 dev_err(&pdev->dev, PFX "No usable DMA configuration, "
9896 "aborting.\n");
9897 goto err_out_release_parent;
9898 }
9899 }
9900
9901 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9902
19ecb6ba 9903 np->regs = pci_ioremap_bar(pdev, 0);
a3138df9
DM		 9904 if (!np->regs) {
9905 dev_err(&pdev->dev, PFX "Cannot map device registers, "
9906 "aborting.\n");
9907 err = -ENOMEM;
9908 goto err_out_release_parent;
9909 }
9910
9911 pci_set_master(pdev);
9912 pci_save_state(pdev);
9913
9914 dev->irq = pdev->irq;
9915
9916 niu_assign_netdev_ops(dev);
9917
9918 err = niu_get_invariants(np);
9919 if (err) {
9920 if (err != -ENODEV)
9921 dev_err(&pdev->dev, PFX "Problem fetching invariants "
9922 "of chip, aborting.\n");
9923 goto err_out_iounmap;
9924 }
9925
9926 err = register_netdev(dev);
9927 if (err) {
9928 dev_err(&pdev->dev, PFX "Cannot register net device, "
9929 "aborting.\n");
9930 goto err_out_iounmap;
9931 }
9932
9933 pci_set_drvdata(pdev, dev);
9934
9935 niu_device_announce(np);
9936
9937 return 0;
9938
9939err_out_iounmap:
9940 if (np->regs) {
9941 iounmap(np->regs);
9942 np->regs = NULL;
9943 }
9944
9945err_out_release_parent:
9946 niu_put_parent(np);
9947
9948err_out_free_dev:
9949 free_netdev(dev);
9950
9951err_out_free_res:
9952 pci_release_regions(pdev);
9953
9954err_out_disable_pdev:
9955 pci_disable_device(pdev);
9956 pci_set_drvdata(pdev, NULL);
9957
9958 return err;
9959}
9960
9961static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9962{
9963 struct net_device *dev = pci_get_drvdata(pdev);
9964
9965 if (dev) {
9966 struct niu *np = netdev_priv(dev);
9967
9968 unregister_netdev(dev);
9969 if (np->regs) {
9970 iounmap(np->regs);
9971 np->regs = NULL;
9972 }
9973
9974 niu_ldg_free(np);
9975
9976 niu_put_parent(np);
9977
9978 free_netdev(dev);
9979 pci_release_regions(pdev);
9980 pci_disable_device(pdev);
9981 pci_set_drvdata(pdev, NULL);
9982 }
9983}
9984
9985static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9986{
9987 struct net_device *dev = pci_get_drvdata(pdev);
9988 struct niu *np = netdev_priv(dev);
9989 unsigned long flags;
9990
9991 if (!netif_running(dev))
9992 return 0;
9993
9994 flush_scheduled_work();
9995 niu_netif_stop(np);
9996
9997 del_timer_sync(&np->timer);
9998
9999 spin_lock_irqsave(&np->lock, flags);
10000 niu_enable_interrupts(np, 0);
10001 spin_unlock_irqrestore(&np->lock, flags);
10002
10003 netif_device_detach(dev);
10004
10005 spin_lock_irqsave(&np->lock, flags);
10006 niu_stop_hw(np);
10007 spin_unlock_irqrestore(&np->lock, flags);
10008
10009 pci_save_state(pdev);
10010
10011 return 0;
10012}
10013
10014static int niu_resume(struct pci_dev *pdev)
10015{
10016 struct net_device *dev = pci_get_drvdata(pdev);
10017 struct niu *np = netdev_priv(dev);
10018 unsigned long flags;
10019 int err;
10020
10021 if (!netif_running(dev))
10022 return 0;
10023
10024 pci_restore_state(pdev);
10025
10026 netif_device_attach(dev);
10027
10028 spin_lock_irqsave(&np->lock, flags);
10029
10030 err = niu_init_hw(np);
10031 if (!err) {
10032 np->timer.expires = jiffies + HZ;
10033 add_timer(&np->timer);
10034 niu_netif_start(np);
10035 }
10036
10037 spin_unlock_irqrestore(&np->lock, flags);
10038
10039 return err;
10040}
10041
10042static struct pci_driver niu_pci_driver = {
10043 .name = DRV_MODULE_NAME,
10044 .id_table = niu_pci_tbl,
10045 .probe = niu_pci_init_one,
10046 .remove = __devexit_p(niu_pci_remove_one),
10047 .suspend = niu_suspend,
10048 .resume = niu_resume,
10049};
10050
10051#ifdef CONFIG_SPARC64
10052static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
10053 u64 *dma_addr, gfp_t flag)
10054{
10055 unsigned long order = get_order(size);
10056 unsigned long page = __get_free_pages(flag, order);
10057
10058 if (page == 0UL)
10059 return NULL;
10060 memset((char *)page, 0, PAGE_SIZE << order);
10061 *dma_addr = __pa(page);
10062
10063 return (void *) page;
10064}
10065
10066static void niu_phys_free_coherent(struct device *dev, size_t size,
10067 void *cpu_addr, u64 handle)
10068{
10069 unsigned long order = get_order(size);
10070
10071 free_pages((unsigned long) cpu_addr, order);
10072}
10073
10074static u64 niu_phys_map_page(struct device *dev, struct page *page,
10075 unsigned long offset, size_t size,
10076 enum dma_data_direction direction)
10077{
10078 return page_to_phys(page) + offset;
10079}
10080
10081static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10082 size_t size, enum dma_data_direction direction)
10083{
10084 /* Nothing to do. */
10085}
10086
10087static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10088 size_t size,
10089 enum dma_data_direction direction)
10090{
10091 return __pa(cpu_addr);
10092}
10093
10094static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10095 size_t size,
10096 enum dma_data_direction direction)
10097{
10098 /* Nothing to do. */
10099}
10100
10101static const struct niu_ops niu_phys_ops = {
10102 .alloc_coherent = niu_phys_alloc_coherent,
10103 .free_coherent = niu_phys_free_coherent,
10104 .map_page = niu_phys_map_page,
10105 .unmap_page = niu_phys_unmap_page,
10106 .map_single = niu_phys_map_single,
10107 .unmap_single = niu_phys_unmap_single,
10108};
10109
10110static unsigned long res_size(struct resource *r)
10111{
10112 return r->end - r->start + 1UL;
10113}
10114
10115static int __devinit niu_of_probe(struct of_device *op,
10116 const struct of_device_id *match)
10117{
10118 union niu_parent_id parent_id;
10119 struct net_device *dev;
10120 struct niu *np;
10121 const u32 *reg;
10122 int err;
10123
10124 niu_driver_version();
10125
10126 reg = of_get_property(op->node, "reg", NULL);
10127 if (!reg) {
10128 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
10129 op->node->full_name);
10130 return -ENODEV;
10131 }
10132
10133 dev = niu_alloc_and_init(&op->dev, NULL, op,
10134 &niu_phys_ops, reg[0] & 0x1);
10135 if (!dev) {
10136 err = -ENOMEM;
10137 goto err_out;
10138 }
10139 np = netdev_priv(dev);
10140
10141 memset(&parent_id, 0, sizeof(parent_id));
10142 parent_id.of = of_get_parent(op->node);
10143
10144 np->parent = niu_get_parent(np, &parent_id,
10145 PLAT_TYPE_NIU);
10146 if (!np->parent) {
10147 err = -ENOMEM;
10148 goto err_out_free_dev;
10149 }
10150
10151 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
10152
10153 np->regs = of_ioremap(&op->resource[1], 0,
10154 res_size(&op->resource[1]),
10155 "niu regs");
10156 if (!np->regs) {
10157 dev_err(&op->dev, PFX "Cannot map device registers, "
10158 "aborting.\n");
10159 err = -ENOMEM;
10160 goto err_out_release_parent;
10161 }
10162
10163 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
10164 res_size(&op->resource[2]),
10165 "niu vregs-1");
10166 if (!np->vir_regs_1) {
10167 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
10168 "aborting.\n");
10169 err = -ENOMEM;
10170 goto err_out_iounmap;
10171 }
10172
10173 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
10174 res_size(&op->resource[3]),
10175 "niu vregs-2");
10176 if (!np->vir_regs_2) {
10177 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
10178 "aborting.\n");
10179 err = -ENOMEM;
10180 goto err_out_iounmap;
10181 }
10182
10183 niu_assign_netdev_ops(dev);
10184
10185 err = niu_get_invariants(np);
10186 if (err) {
10187 if (err != -ENODEV)
10188 dev_err(&op->dev, PFX "Problem fetching invariants "
10189 "of chip, aborting.\n");
10190 goto err_out_iounmap;
10191 }
10192
10193 err = register_netdev(dev);
10194 if (err) {
10195 dev_err(&op->dev, PFX "Cannot register net device, "
10196 "aborting.\n");
10197 goto err_out_iounmap;
10198 }
10199
10200 dev_set_drvdata(&op->dev, dev);
10201
10202 niu_device_announce(np);
10203
10204 return 0;
10205
10206err_out_iounmap:
10207 if (np->vir_regs_1) {
10208 of_iounmap(&op->resource[2], np->vir_regs_1,
10209 res_size(&op->resource[2]));
10210 np->vir_regs_1 = NULL;
10211 }
10212
10213 if (np->vir_regs_2) {
10214 of_iounmap(&op->resource[3], np->vir_regs_2,
10215 res_size(&op->resource[3]));
10216 np->vir_regs_2 = NULL;
10217 }
10218
10219 if (np->regs) {
10220 of_iounmap(&op->resource[1], np->regs,
10221 res_size(&op->resource[1]));
10222 np->regs = NULL;
10223 }
10224
10225err_out_release_parent:
10226 niu_put_parent(np);
10227
10228err_out_free_dev:
10229 free_netdev(dev);
10230
10231err_out:
10232 return err;
10233}
10234
10235static int __devexit niu_of_remove(struct of_device *op)
10236{
10237 struct net_device *dev = dev_get_drvdata(&op->dev);
10238
10239 if (dev) {
10240 struct niu *np = netdev_priv(dev);
10241
10242 unregister_netdev(dev);
10243
10244 if (np->vir_regs_1) {
10245 of_iounmap(&op->resource[2], np->vir_regs_1,
10246 res_size(&op->resource[2]));
10247 np->vir_regs_1 = NULL;
10248 }
10249
10250 if (np->vir_regs_2) {
10251 of_iounmap(&op->resource[3], np->vir_regs_2,
10252 res_size(&op->resource[3]));
10253 np->vir_regs_2 = NULL;
10254 }
10255
10256 if (np->regs) {
10257 of_iounmap(&op->resource[1], np->regs,
10258 res_size(&op->resource[1]));
10259 np->regs = NULL;
10260 }
10261
10262 niu_ldg_free(np);
10263
10264 niu_put_parent(np);
10265
10266 free_netdev(dev);
10267 dev_set_drvdata(&op->dev, NULL);
10268 }
10269 return 0;
10270}
10271
fd098316 10272static const struct of_device_id niu_match[] = {
a3138df9
DM		 10273 {
10274 .name = "network",
10275 .compatible = "SUNW,niusl",
10276 },
10277 {},
10278};
10279MODULE_DEVICE_TABLE(of, niu_match);
10280
10281static struct of_platform_driver niu_of_driver = {
10282 .name = "niu",
10283 .match_table = niu_match,
10284 .probe = niu_of_probe,
10285 .remove = __devexit_p(niu_of_remove),
10286};
10287
10288#endif /* CONFIG_SPARC64 */
10289
10290static int __init niu_init(void)
10291{
10292 int err = 0;
10293
81429973 10294 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
a3138df9
DM		 10295
10296 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10297
10298#ifdef CONFIG_SPARC64
10299 err = of_register_driver(&niu_of_driver, &of_bus_type);
10300#endif
10301
10302 if (!err) {
10303 err = pci_register_driver(&niu_pci_driver);
10304#ifdef CONFIG_SPARC64
10305 if (err)
10306 of_unregister_driver(&niu_of_driver);
10307#endif
10308 }
10309
10310 return err;
10311}
10312
10313static void __exit niu_exit(void)
10314{
10315 pci_unregister_driver(&niu_pci_driver);
10316#ifdef CONFIG_SPARC64
10317 of_unregister_driver(&niu_of_driver);
10318#endif
10319}
10320
10321module_init(niu_init);
10322module_exit(niu_exit);
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