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netxen: mask correctable error
[net-next-2.6.git] / drivers / net / netxen / netxen_nic_hw.c
CommitLineData
3d396eb1 1/*
5d242f1c 2 * Copyright (C) 2003 - 2009 NetXen, Inc.
13af7a6e 3 * Copyright (C) 2009 - QLogic Corporation.
3d396eb1 4 * All rights reserved.
80922fbc 5 *
3d396eb1
AK		 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
cb8011ad 10 *
3d396eb1
AK		 11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
cb8011ad 15 *
3d396eb1
AK		 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
80922fbc 20 *
3d396eb1 21 * The full GNU General Public License is included in this distribution
4d21fef4 22 * in the file called "COPYING".
80922fbc 23 *
3d396eb1
AK		 24 */
25
5a0e3ad6 26#include <linux/slab.h>
3d396eb1
AK		 27#include "netxen_nic.h"
28#include "netxen_nic_hw.h"
3d396eb1 29
c9bdd4b5
ACM		 30#include <net/ip.h>
31
3ce06a32
DP		 32#define MASK(n) ((1ULL<<(n))-1)
33#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
34#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
35#define MS_WIN(addr) (addr & 0x0ffc0000)
36
37#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
38
39#define CRB_BLK(off) ((off >> 20) & 0x3f)
40#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
41#define CRB_WINDOW_2M (0x130060)
42#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
43#define CRB_INDIRECT_2M (0x1e0000UL)
44
f03b0ebd
DP		 45static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
46 void __iomem *addr, u32 data);
47static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
48 void __iomem *addr);
49
e98e3350
DP		 50#ifndef readq
51static inline u64 readq(void __iomem *addr)
52{
53 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
54}
55#endif
56
57#ifndef writeq
58static inline void writeq(u64 val, void __iomem *addr)
59{
60 writel(((u32) (val)), (addr));
61 writel(((u32) (val >> 32)), (addr + 4));
62}
63#endif
64
1fbe6323
DP		 65#define PCI_OFFSET_FIRST_RANGE(adapter, off) \
66 ((adapter)->ahw.pci_base0 + (off))
67#define PCI_OFFSET_SECOND_RANGE(adapter, off) \
68 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
69#define PCI_OFFSET_THIRD_RANGE(adapter, off) \
70 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
71
72static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
73 unsigned long off)
74{
75 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
76 return PCI_OFFSET_FIRST_RANGE(adapter, off);
77
78 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
79 return PCI_OFFSET_SECOND_RANGE(adapter, off);
80
81 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
82 return PCI_OFFSET_THIRD_RANGE(adapter, off);
83
84 return NULL;
85}
86
ea7eaa39
DP		 87static crb_128M_2M_block_map_t
88crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
3ce06a32
DP		 89 {{{0, 0, 0, 0} } }, /* 0: PCI */
90 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
91 {1, 0x0110000, 0x0120000, 0x130000},
92 {1, 0x0120000, 0x0122000, 0x124000},
93 {1, 0x0130000, 0x0132000, 0x126000},
94 {1, 0x0140000, 0x0142000, 0x128000},
95 {1, 0x0150000, 0x0152000, 0x12a000},
96 {1, 0x0160000, 0x0170000, 0x110000},
97 {1, 0x0170000, 0x0172000, 0x12e000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {1, 0x01e0000, 0x01e0800, 0x122000},
105 {0, 0x0000000, 0x0000000, 0x000000} } },
106 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
107 {{{0, 0, 0, 0} } }, /* 3: */
108 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
109 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
110 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
111 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
112 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {1, 0x08f0000, 0x08f2000, 0x172000} } },
128 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {1, 0x09f0000, 0x09f2000, 0x176000} } },
144 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
160 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
176 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
177 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
178 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
179 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
180 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
181 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
182 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
183 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
184 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
185 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
186 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
187 {{{0, 0, 0, 0} } }, /* 23: */
188 {{{0, 0, 0, 0} } }, /* 24: */
189 {{{0, 0, 0, 0} } }, /* 25: */
190 {{{0, 0, 0, 0} } }, /* 26: */
191 {{{0, 0, 0, 0} } }, /* 27: */
192 {{{0, 0, 0, 0} } }, /* 28: */
193 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
194 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
195 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
196 {{{0} } }, /* 32: PCI */
197 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
198 {1, 0x2110000, 0x2120000, 0x130000},
199 {1, 0x2120000, 0x2122000, 0x124000},
200 {1, 0x2130000, 0x2132000, 0x126000},
201 {1, 0x2140000, 0x2142000, 0x128000},
202 {1, 0x2150000, 0x2152000, 0x12a000},
203 {1, 0x2160000, 0x2170000, 0x110000},
204 {1, 0x2170000, 0x2172000, 0x12e000},
205 {0, 0x0000000, 0x0000000, 0x000000},
206 {0, 0x0000000, 0x0000000, 0x000000},
207 {0, 0x0000000, 0x0000000, 0x000000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000},
212 {0, 0x0000000, 0x0000000, 0x000000} } },
213 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
214 {{{0} } }, /* 35: */
215 {{{0} } }, /* 36: */
216 {{{0} } }, /* 37: */
217 {{{0} } }, /* 38: */
218 {{{0} } }, /* 39: */
219 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
220 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
221 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
222 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
223 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
224 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
225 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
226 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
227 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
228 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
229 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
230 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
231 {{{0} } }, /* 52: */
232 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
233 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
234 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
235 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
236 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
237 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
238 {{{0} } }, /* 59: I2C0 */
239 {{{0} } }, /* 60: I2C1 */
240 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
241 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
242 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
243};
244
245/*
246 * top 12 bits of crb internal address (hub, agent)
247 */
248static unsigned crb_hub_agt[64] =
249{
250 0,
251 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
252 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
253 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
254 0,
255 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
256 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
257 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
258 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
259 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
260 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
261 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
262 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
263 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
264 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
265 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
266 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
267 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
268 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
277 0,
278 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
279 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
280 0,
281 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
282 0,
283 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
284 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
285 0,
286 0,
287 0,
288 0,
289 0,
290 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
291 0,
292 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
293 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
294 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
299 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
300 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
301 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
302 0,
303 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
304 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
305 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
306 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
307 0,
308 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
309 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
310 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
311 0,
312 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
313 0,
314};
315
3d396eb1
AK		 316/* PCI Windowing for DDR regions. */
317
3ce06a32 318#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
3d396eb1 319
c9517e58
DP		 320#define NETXEN_PCIE_SEM_TIMEOUT 10000
321
322int
323netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
324{
325 int done = 0, timeout = 0;
326
327 while (!done) {
328 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
329 if (done == 1)
330 break;
331 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
7cecdca1 332 return -EIO;
c9517e58
DP		 333 msleep(1);
334 }
335
336 if (id_reg)
337 NXWR32(adapter, id_reg, adapter->portnum);
338
339 return 0;
340}
341
342void
343netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
344{
581e8ae4 345 NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
c9517e58
DP		 346}
347
3ad4467c
DP		 348int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
349{
350 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
351 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
352 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
353 }
354
355 return 0;
356}
357
358/* Disable an XG interface */
359int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
360{
361 __u32 mac_cfg;
362 u32 port = adapter->physical_port;
363
364 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
365 return 0;
366
367 if (port > NETXEN_NIU_MAX_XG_PORTS)
368 return -EINVAL;
369
370 mac_cfg = 0;
371 if (NXWR32(adapter,
372 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
373 return -EIO;
374 return 0;
375}
376
623621b0
DP		 377#define NETXEN_UNICAST_ADDR(port, index) \
378 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
379#define NETXEN_MCAST_ADDR(port, index) \
380 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
381#define MAC_HI(addr) \
382 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
383#define MAC_LO(addr) \
384 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
385
3ad4467c
DP		 386int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
387{
a7483b0a
NK		 388 u32 mac_cfg;
389 u32 cnt = 0;
390 __u32 reg = 0x0200;
3ad4467c 391 u32 port = adapter->physical_port;
a7483b0a 392 u16 board_type = adapter->ahw.board_type;
3ad4467c
DP		 393
394 if (port > NETXEN_NIU_MAX_XG_PORTS)
395 return -EINVAL;
396
a7483b0a
NK		 397 mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port));
398 mac_cfg &= ~0x4;
399 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
3ad4467c 400
a7483b0a
NK		 401 if ((board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) ||
402 (board_type == NETXEN_BRDTYPE_P2_SB31_10G_HMEZ))
403 reg = (0x20 << port);
3ad4467c 404
a7483b0a
NK		 405 NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg);
406
407 mdelay(10);
408
409 while (NXRD32(adapter, NETXEN_NIU_FRAME_COUNT) && ++cnt < 20)
410 mdelay(10);
411
412 if (cnt < 20) {
413
414 reg = NXRD32(adapter,
415 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
416
417 if (mode == NETXEN_NIU_PROMISC_MODE)
418 reg = (reg | 0x2000UL);
419 else
420 reg = (reg & ~0x2000UL);
421
422 if (mode == NETXEN_NIU_ALLMULTI_MODE)
423 reg = (reg | 0x1000UL);
424 else
425 reg = (reg & ~0x1000UL);
426
427 NXWR32(adapter,
428 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
429 }
430
431 mac_cfg |= 0x4;
432 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
3ad4467c
DP		 433
434 return 0;
435}
436
437int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
438{
439 u32 mac_hi, mac_lo;
440 u32 reg_hi, reg_lo;
441
442 u8 phy = adapter->physical_port;
443
444 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
445 return -EINVAL;
446
447 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
448 mac_hi = addr[2] | ((u32)addr[3] << 8) |
449 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
450
451 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
452 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
453
454 /* write twice to flush */
455 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
456 return -EIO;
457 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
458 return -EIO;
459
460 return 0;
461}
462
623621b0
DP		 463static int
464netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
465{
466 u32 val = 0;
467 u16 port = adapter->physical_port;
5d09e534 468 u8 *addr = adapter->mac_addr;
623621b0
DP		 469
470 if (adapter->mc_enabled)
471 return 0;
472
f98a9f69 473 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
623621b0 474 val |= (1UL << (28+port));
f98a9f69 475 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
623621b0
DP		 476
477 /* add broadcast addr to filter */
478 val = 0xffffff;
f98a9f69
DP		 479 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
480 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
623621b0
DP		 481
482 /* add station addr to filter */
483 val = MAC_HI(addr);
f98a9f69 484 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
623621b0 485 val = MAC_LO(addr);
f98a9f69 486 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
623621b0
DP		 487
488 adapter->mc_enabled = 1;
489 return 0;
490}
491
492static int
493netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
494{
495 u32 val = 0;
496 u16 port = adapter->physical_port;
5d09e534 497 u8 *addr = adapter->mac_addr;
623621b0
DP		 498
499 if (!adapter->mc_enabled)
500 return 0;
501
f98a9f69 502 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
623621b0 503 val &= ~(1UL << (28+port));
f98a9f69 504 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
623621b0
DP		 505
506 val = MAC_HI(addr);
f98a9f69 507 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
623621b0 508 val = MAC_LO(addr);
f98a9f69 509 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
623621b0 510
f98a9f69
DP		 511 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
512 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
623621b0
DP		 513
514 adapter->mc_enabled = 0;
515 return 0;
516}
517
518static int
519netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
520 int index, u8 *addr)
521{
522 u32 hi = 0, lo = 0;
523 u16 port = adapter->physical_port;
524
525 lo = MAC_LO(addr);
526 hi = MAC_HI(addr);
527
f98a9f69
DP		 528 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
529 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
623621b0
DP		 530
531 return 0;
532}
533
c9fc891f 534void netxen_p2_nic_set_multi(struct net_device *netdev)
3d396eb1 535{
3176ff3e 536 struct netxen_adapter *adapter = netdev_priv(netdev);
22bedad3 537 struct netdev_hw_addr *ha;
623621b0 538 u8 null_addr[6];
f9dcbcc9 539 int i;
623621b0
DP		 540
541 memset(null_addr, 0, 6);
3d396eb1 542
3d396eb1 543 if (netdev->flags & IFF_PROMISC) {
623621b0
DP		 544
545 adapter->set_promisc(adapter,
546 NETXEN_NIU_PROMISC_MODE);
547
548 /* Full promiscuous mode */
549 netxen_nic_disable_mcast_filter(adapter);
550
551 return;
552 }
553
4cd24eaf 554 if (netdev_mc_empty(netdev)) {
623621b0
DP		 555 adapter->set_promisc(adapter,
556 NETXEN_NIU_NON_PROMISC_MODE);
557 netxen_nic_disable_mcast_filter(adapter);
558 return;
559 }
560
561 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
562 if (netdev->flags & IFF_ALLMULTI ||
4cd24eaf 563 netdev_mc_count(netdev) > adapter->max_mc_count) {
623621b0
DP		 564 netxen_nic_disable_mcast_filter(adapter);
565 return;
3d396eb1 566 }
623621b0
DP		 567
568 netxen_nic_enable_mcast_filter(adapter);
569
f9dcbcc9 570 i = 0;
22bedad3
JP		 571 netdev_for_each_mc_addr(ha, netdev)
572 netxen_nic_set_mcast_addr(adapter, i++, ha->addr);
623621b0
DP		 573
574 /* Clear out remaining addresses */
f9dcbcc9
JP		 575 while (i < adapter->max_mc_count)
576 netxen_nic_set_mcast_addr(adapter, i++, null_addr);
3d396eb1
AK		 577}
578
c9fc891f
DP		 579static int
580netxen_send_cmd_descs(struct netxen_adapter *adapter,
d877f1e3 581 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
c9fc891f 582{
d877f1e3 583 u32 i, producer, consumer;
c9fc891f
DP		 584 struct netxen_cmd_buffer *pbuf;
585 struct cmd_desc_type0 *cmd_desc;
d877f1e3 586 struct nx_host_tx_ring *tx_ring;
c9fc891f
DP		 587
588 i = 0;
589
db4cfd8a
DP		 590 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
591 return -EIO;
592
4ea528a1 593 tx_ring = adapter->tx_ring;
b2af9cb0 594 __netif_tx_lock_bh(tx_ring->txq);
03e678ee 595
d877f1e3
DP		 596 producer = tx_ring->producer;
597 consumer = tx_ring->sw_consumer;
598
b2af9cb0
DP		 599 if (nr_desc >= netxen_tx_avail(tx_ring)) {
600 netif_tx_stop_queue(tx_ring->txq);
7a9905e6
RB		 601 smp_mb();
602 if (netxen_tx_avail(tx_ring) > nr_desc) {
603 if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
604 netif_tx_wake_queue(tx_ring->txq);
605 } else {
606 __netif_tx_unlock_bh(tx_ring->txq);
607 return -EBUSY;
608 }
d877f1e3
DP		 609 }
610
c9fc891f
DP		 611 do {
612 cmd_desc = &cmd_desc_arr[i];
613
d877f1e3 614 pbuf = &tx_ring->cmd_buf_arr[producer];
c9fc891f 615 pbuf->skb = NULL;
c9fc891f 616 pbuf->frag_count = 0;
c9fc891f 617
d877f1e3 618 memcpy(&tx_ring->desc_head[producer],
c9fc891f
DP		 619 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
620
d877f1e3 621 producer = get_next_index(producer, tx_ring->num_desc);
c9fc891f
DP		 622 i++;
623
d877f1e3 624 } while (i != nr_desc);
c9fc891f 625
d877f1e3 626 tx_ring->producer = producer;
c9fc891f 627
cb2107be 628 netxen_nic_update_cmd_producer(adapter, tx_ring);
c9fc891f 629
b2af9cb0 630 __netif_tx_unlock_bh(tx_ring->txq);
03e678ee 631
c9fc891f
DP		 632 return 0;
633}
634
5cf4d323
DP		 635static int
636nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
c9fc891f 637{
c9fc891f 638 nx_nic_req_t req;
2edbb454
DP		 639 nx_mac_req_t *mac_req;
640 u64 word;
c9fc891f
DP		 641
642 memset(&req, 0, sizeof(nx_nic_req_t));
2edbb454
DP		 643 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
644
645 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
646 req.req_hdr = cpu_to_le64(word);
647
648 mac_req = (nx_mac_req_t *)&req.words[0];
649 mac_req->op = op;
650 memcpy(mac_req->mac_addr, addr, 6);
c9fc891f 651
5cf4d323
DP		 652 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
653}
654
655static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
656 u8 *addr, struct list_head *del_list)
657{
658 struct list_head *head;
659 nx_mac_list_t *cur;
660
661 /* look up if already exists */
662 list_for_each(head, del_list) {
663 cur = list_entry(head, nx_mac_list_t, list);
664
665 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
666 list_move_tail(head, &adapter->mac_list);
667 return 0;
668 }
c9fc891f
DP		 669 }
670
5cf4d323
DP		 671 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
672 if (cur == NULL) {
673 printk(KERN_ERR "%s: failed to add mac address filter\n",
674 adapter->netdev->name);
675 return -ENOMEM;
676 }
677 memcpy(cur->mac_addr, addr, ETH_ALEN);
678 list_add_tail(&cur->list, &adapter->mac_list);
679 return nx_p3_sre_macaddr_change(adapter,
680 cur->mac_addr, NETXEN_MAC_ADD);
c9fc891f
DP		 681}
682
683void netxen_p3_nic_set_multi(struct net_device *netdev)
684{
685 struct netxen_adapter *adapter = netdev_priv(netdev);
22bedad3 686 struct netdev_hw_addr *ha;
c9fc891f 687 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
9ad27643 688 u32 mode = VPORT_MISS_MODE_DROP;
5cf4d323
DP		 689 LIST_HEAD(del_list);
690 struct list_head *head;
691 nx_mac_list_t *cur;
c9fc891f 692
d49c9640
AKS		 693 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
694 return;
695
5cf4d323 696 list_splice_tail_init(&adapter->mac_list, &del_list);
c9fc891f 697
5d09e534 698 nx_p3_nic_add_mac(adapter, adapter->mac_addr, &del_list);
5cf4d323 699 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
9ad27643
DP		 700
701 if (netdev->flags & IFF_PROMISC) {
702 mode = VPORT_MISS_MODE_ACCEPT_ALL;
703 goto send_fw_cmd;
704 }
705
706 if ((netdev->flags & IFF_ALLMULTI) ||
4cd24eaf 707 (netdev_mc_count(netdev) > adapter->max_mc_count)) {
9ad27643
DP		 708 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
709 goto send_fw_cmd;
710 }
711
4cd24eaf 712 if (!netdev_mc_empty(netdev)) {
22bedad3
JP		 713 netdev_for_each_mc_addr(ha, netdev)
714 nx_p3_nic_add_mac(adapter, ha->addr, &del_list);
c9fc891f 715 }
9ad27643
DP		 716
717send_fw_cmd:
718 adapter->set_promisc(adapter, mode);
5cf4d323
DP		 719 head = &del_list;
720 while (!list_empty(head)) {
721 cur = list_entry(head->next, nx_mac_list_t, list);
722
723 nx_p3_sre_macaddr_change(adapter,
724 cur->mac_addr, NETXEN_MAC_DEL);
725 list_del(&cur->list);
c9fc891f 726 kfree(cur);
c9fc891f
DP		 727 }
728}
729
9ad27643
DP		 730int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
731{
732 nx_nic_req_t req;
2edbb454 733 u64 word;
9ad27643
DP		 734
735 memset(&req, 0, sizeof(nx_nic_req_t));
736
2edbb454
DP		 737 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
738
739 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
740 ((u64)adapter->portnum << 16);
741 req.req_hdr = cpu_to_le64(word);
742
9ad27643
DP		 743 req.words[0] = cpu_to_le64(mode);
744
745 return netxen_send_cmd_descs(adapter,
746 (struct cmd_desc_type0 *)&req, 1);
747}
748
06e9d9f9
DP		 749void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
750{
5cf4d323
DP		 751 nx_mac_list_t *cur;
752 struct list_head *head = &adapter->mac_list;
753
754 while (!list_empty(head)) {
755 cur = list_entry(head->next, nx_mac_list_t, list);
756 nx_p3_sre_macaddr_change(adapter,
757 cur->mac_addr, NETXEN_MAC_DEL);
758 list_del(&cur->list);
06e9d9f9 759 kfree(cur);
06e9d9f9
DP		 760 }
761}
762
3d0a3cc9
DP		 763int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
764{
765 /* assuming caller has already copied new addr to netdev */
766 netxen_p3_nic_set_multi(adapter->netdev);
767 return 0;
768}
769
cd1f8160
DP		 770#define NETXEN_CONFIG_INTR_COALESCE 3
771
772/*
773 * Send the interrupt coalescing parameter set by ethtool to the card.
774 */
775int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
776{
777 nx_nic_req_t req;
c0703950
AKS		 778 u64 word[6];
779 int rv, i;
cd1f8160
DP		 780
781 memset(&req, 0, sizeof(nx_nic_req_t));
c0703950 782 memset(word, 0, sizeof(word));
cd1f8160 783
1bb482f8 784 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
2edbb454 785
c0703950
AKS		 786 word[0] = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
787 req.req_hdr = cpu_to_le64(word[0]);
cd1f8160 788
c0703950
AKS		 789 memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
790 for (i = 0; i < 6; i++)
791 req.words[i] = cpu_to_le64(word[i]);
cd1f8160
DP		 792
793 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
794 if (rv != 0) {
795 printk(KERN_ERR "ERROR. Could not send "
796 "interrupt coalescing parameters\n");
797 }
798
799 return rv;
800}
801
1bb482f8
NK		 802int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
803{
804 nx_nic_req_t req;
805 u64 word;
806 int rv = 0;
807
808 if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable)
809 return 0;
810
811 memset(&req, 0, sizeof(nx_nic_req_t));
812
813 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
814
815 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
816 req.req_hdr = cpu_to_le64(word);
817
818 req.words[0] = cpu_to_le64(enable);
819
820 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
821 if (rv != 0) {
822 printk(KERN_ERR "ERROR. Could not send "
823 "configure hw lro request\n");
824 }
825
826 adapter->flags ^= NETXEN_NIC_LRO_ENABLED;
827
828 return rv;
829}
830
fa3ce355
NK		 831int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
832{
833 nx_nic_req_t req;
834 u64 word;
835 int rv = 0;
836
837 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
838 return rv;
839
840 memset(&req, 0, sizeof(nx_nic_req_t));
841
842 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
843
844 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
845 ((u64)adapter->portnum << 16);
846 req.req_hdr = cpu_to_le64(word);
847
848 req.words[0] = cpu_to_le64(enable);
849
850 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
851 if (rv != 0) {
852 printk(KERN_ERR "ERROR. Could not send "
853 "configure bridge mode request\n");
854 }
855
856 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
857
858 return rv;
859}
860
861
d8b100c5
DP		 862#define RSS_HASHTYPE_IP_TCP 0x3
863
864int netxen_config_rss(struct netxen_adapter *adapter, int enable)
865{
866 nx_nic_req_t req;
867 u64 word;
868 int i, rv;
869
870 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
871 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
872 0x255b0ec26d5a56daULL };
873
874
875 memset(&req, 0, sizeof(nx_nic_req_t));
876 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
877
878 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
879 req.req_hdr = cpu_to_le64(word);
880
881 /*
882 * RSS request:
883 * bits 3-0: hash_method
884 * 5-4: hash_type_ipv4
885 * 7-6: hash_type_ipv6
886 * 8: enable
887 * 9: use indirection table
888 * 47-10: reserved
889 * 63-48: indirection table mask
890 */
891 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
892 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
893 ((u64)(enable & 0x1) << 8) |
894 ((0x7ULL) << 48);
895 req.words[0] = cpu_to_le64(word);
896 for (i = 0; i < 5; i++)
897 req.words[i+1] = cpu_to_le64(key[i]);
898
899
900 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
901 if (rv != 0) {
902 printk(KERN_ERR "%s: could not configure RSS\n",
903 adapter->netdev->name);
904 }
905
906 return rv;
907}
908
6598b169
DP		 909int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
910{
911 nx_nic_req_t req;
912 u64 word;
913 int rv;
914
915 memset(&req, 0, sizeof(nx_nic_req_t));
916 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
917
918 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
919 req.req_hdr = cpu_to_le64(word);
920
921 req.words[0] = cpu_to_le64(cmd);
922 req.words[1] = cpu_to_le64(ip);
923
924 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
925 if (rv != 0) {
926 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
927 adapter->netdev->name,
928 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
929 }
930 return rv;
931}
932
3bf26ce3
DP		 933int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
934{
935 nx_nic_req_t req;
936 u64 word;
937 int rv;
938
939 memset(&req, 0, sizeof(nx_nic_req_t));
940 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
941
942 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
943 req.req_hdr = cpu_to_le64(word);
22527864 944 req.words[0] = cpu_to_le64(enable | (enable << 8));
3bf26ce3
DP		 945
946 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
947 if (rv != 0) {
948 printk(KERN_ERR "%s: could not configure link notification\n",
949 adapter->netdev->name);
950 }
951
952 return rv;
953}
954
1bb482f8
NK		 955int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
956{
957 nx_nic_req_t req;
958 u64 word;
959 int rv;
960
961 memset(&req, 0, sizeof(nx_nic_req_t));
962 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
963
964 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
965 ((u64)adapter->portnum << 16) |
966 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
967
968 req.req_hdr = cpu_to_le64(word);
969
970 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
971 if (rv != 0) {
972 printk(KERN_ERR "%s: could not cleanup lro flows\n",
973 adapter->netdev->name);
974 }
975 return rv;
976}
977
3d396eb1
AK		 978/*
979 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
980 * @returns 0 on success, negative on failure
981 */
c9fc891f
DP		 982
983#define MTU_FUDGE_FACTOR 100
984
3d396eb1
AK		 985int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
986{
3176ff3e 987 struct netxen_adapter *adapter = netdev_priv(netdev);
c9fc891f 988 int max_mtu;
9ad27643 989 int rc = 0;
3d396eb1 990
c9fc891f
DP		 991 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
992 max_mtu = P3_MAX_MTU;
993 else
994 max_mtu = P2_MAX_MTU;
995
996 if (mtu > max_mtu) {
997 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
998 netdev->name, max_mtu);
3d396eb1
AK		 999 return -EINVAL;
1000 }
1001
80922fbc 1002 if (adapter->set_mtu)
9ad27643 1003 rc = adapter->set_mtu(adapter, mtu);
3d396eb1 1004
9ad27643
DP		 1005 if (!rc)
1006 netdev->mtu = mtu;
c9fc891f 1007
9ad27643 1008 return rc;
3d396eb1
AK		 1009}
1010
3d396eb1 1011static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
f305f789 1012 int size, __le32 * buf)
3d396eb1 1013{
1e2d0059 1014 int i, v, addr;
f305f789 1015 __le32 *ptr32;
3d396eb1
AK		 1016
1017 addr = base;
1018 ptr32 = buf;
1019 for (i = 0; i < size / sizeof(u32); i++) {
f305f789 1020 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 1021 return -1;
f305f789 1022 *ptr32 = cpu_to_le32(v);
3d396eb1
AK		 1023 ptr32++;
1024 addr += sizeof(u32);
1025 }
1026 if ((char *)buf + size > (char *)ptr32) {
f305f789
AV		 1027 __le32 local;
1028 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 1029 return -1;
f305f789 1030 local = cpu_to_le32(v);
3d396eb1
AK		 1031 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
1032 }
1033
1034 return 0;
1035}
1036
a03d2451 1037int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac)
3d396eb1 1038{
9dc28efe
DP		 1039 __le32 *pmac = (__le32 *) mac;
1040 u32 offset;
3d396eb1 1041
06db58c0 1042 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
9dc28efe
DP		 1043
1044 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
3d396eb1 1045 return -1;
9dc28efe 1046
f305f789 1047 if (*mac == cpu_to_le64(~0ULL)) {
9dc28efe 1048
06db58c0
DP		 1049 offset = NX_OLD_MAC_ADDR_OFFSET +
1050 (adapter->portnum * sizeof(u64));
9dc28efe 1051
3d396eb1 1052 if (netxen_get_flash_block(adapter,
9dc28efe 1053 offset, sizeof(u64), pmac) == -1)
3d396eb1 1054 return -1;
9dc28efe 1055
f305f789 1056 if (*mac == cpu_to_le64(~0ULL))
3d396eb1
AK		 1057 return -1;
1058 }
1059 return 0;
1060}
1061
a03d2451 1062int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac)
9dc28efe
DP		 1063{
1064 uint32_t crbaddr, mac_hi, mac_lo;
1065 int pci_func = adapter->ahw.pci_func;
1066
1067 crbaddr = CRB_MAC_BLOCK_START +
1068 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1069
f98a9f69
DP		 1070 mac_lo = NXRD32(adapter, crbaddr);
1071 mac_hi = NXRD32(adapter, crbaddr+4);
9dc28efe 1072
9dc28efe 1073 if (pci_func & 1)
2edbb454 1074 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
9dc28efe 1075 else
2edbb454 1076 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
9dc28efe
DP		 1077
1078 return 0;
1079}
1080
3d396eb1
AK		 1081/*
1082 * Changes the CRB window to the specified window.
1083 */
195c5f98 1084static void
907fa120
DP		 1085netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter *adapter,
1086 u32 window)
3d396eb1
AK		 1087{
1088 void __iomem *offset;
907fa120
DP		 1089 int count = 10;
1090 u8 func = adapter->ahw.pci_func;
3d396eb1 1091
907fa120 1092 if (adapter->ahw.crb_win == window)
3d396eb1 1093 return;
907fa120 1094
e4c93c81
DP		 1095 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1096 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
3d396eb1 1097
907fa120
DP		 1098 writel(window, offset);
1099 do {
1100 if (window == readl(offset))
1101 break;
3d396eb1 1102
907fa120
DP		 1103 if (printk_ratelimit())
1104 dev_warn(&adapter->pdev->dev,
1105 "failed to set CRB window to %d\n",
1106 (window == NETXEN_WINDOW_ONE));
1107 udelay(1);
3d396eb1 1108
907fa120 1109 } while (--count > 0);
3d396eb1 1110
907fa120
DP		 1111 if (count > 0)
1112 adapter->ahw.crb_win = window;
3d396eb1
AK		 1113}
1114
3ce06a32 1115/*
7cecdca1 1116 * Returns < 0 if off is not valid,
3ce06a32
DP		 1117 * 1 if window access is needed. 'off' is set to offset from
1118 * CRB space in 128M pci map
1119 * 0 if no window access is needed. 'off' is set to 2M addr
1120 * In: 'off' is offset from base in 128M pci map
1121 */
1122static int
a9ac07de
DP		 1123netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
1124 ulong off, void __iomem **addr)
3ce06a32 1125{
3ce06a32
DP		 1126 crb_128M_2M_sub_block_map_t *m;
1127
1128
a9ac07de 1129 if ((off >= NETXEN_CRB_MAX) || (off < NETXEN_PCI_CRBSPACE))
7cecdca1 1130 return -EINVAL;
3ce06a32 1131
a9ac07de 1132 off -= NETXEN_PCI_CRBSPACE;
3ce06a32
DP		 1133
1134 /*
1135 * Try direct map
1136 */
a9ac07de 1137 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
3ce06a32 1138
a9ac07de
DP		 1139 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1140 *addr = adapter->ahw.pci_base0 + m->start_2M +
1141 (off - m->start_128M);
3ce06a32
DP		 1142 return 0;
1143 }
1144
1145 /*
1146 * Not in direct map, use crb window
1147 */
a9ac07de
DP		 1148 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M +
1149 (off & MASK(16));
3ce06a32
DP		 1150 return 1;
1151}
1152
1153/*
1154 * In: 'off' is offset from CRB space in 128M pci map
1155 * Out: 'off' is 2M pci map addr
1156 * side effect: lock crb window
1157 */
1158static void
a9ac07de 1159netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong off)
3ce06a32 1160{
907fa120
DP		 1161 u32 window;
1162 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
3ce06a32 1163
a9ac07de
DP		 1164 off -= NETXEN_PCI_CRBSPACE;
1165
1166 window = CRB_HI(off);
907fa120 1167
907fa120
DP		 1168 writel(window, addr);
1169 if (readl(addr) != window) {
1170 if (printk_ratelimit())
1171 dev_warn(&adapter->pdev->dev,
1172 "failed to set CRB window to %d off 0x%lx\n",
a9ac07de 1173 window, off);
3ce06a32 1174 }
3ce06a32
DP		 1175}
1176
f58dbd73
NK		 1177static void __iomem *
1178netxen_nic_map_indirect_address_128M(struct netxen_adapter *adapter,
1179 ulong win_off, void __iomem **mem_ptr)
1180{
1181 ulong off = win_off;
1182 void __iomem *addr;
1183 resource_size_t mem_base;
1184
1185 if (ADDR_IN_WINDOW1(win_off))
1186 off = NETXEN_CRB_NORMAL(win_off);
1187
1188 addr = pci_base_offset(adapter, off);
1189 if (addr)
1190 return addr;
1191
1192 if (adapter->ahw.pci_len0 == 0)
1193 off -= NETXEN_PCI_CRBSPACE;
1194
1195 mem_base = pci_resource_start(adapter->pdev, 0);
1196 *mem_ptr = ioremap(mem_base + (off & PAGE_MASK), PAGE_SIZE);
1197 if (*mem_ptr)
1198 addr = *mem_ptr + (off & (PAGE_SIZE - 1));
1199
1200 return addr;
1201}
1202
195c5f98 1203static int
1fbe6323 1204netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
3d396eb1 1205{
195c5f98 1206 unsigned long flags;
f58dbd73 1207 void __iomem *addr, *mem_ptr = NULL;
3d396eb1 1208
f58dbd73
NK		 1209 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1210 if (!addr)
1211 return -EIO;
195c5f98 1212
f58dbd73 1213 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
f03b0ebd 1214 netxen_nic_io_write_128M(adapter, addr, data);
f58dbd73 1215 } else { /* Window 0 */
f03b0ebd 1216 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
907fa120 1217 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
195c5f98 1218 writel(data, addr);
907fa120
DP		 1219 netxen_nic_pci_set_crbwindow_128M(adapter,
1220 NETXEN_WINDOW_ONE);
f03b0ebd 1221 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
cb8011ad
AK		 1222 }
1223
f58dbd73
NK		 1224 if (mem_ptr)
1225 iounmap(mem_ptr);
1226
3d396eb1
AK		 1227 return 0;
1228}
1229
195c5f98 1230static u32
1fbe6323 1231netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
3d396eb1 1232{
195c5f98 1233 unsigned long flags;
f58dbd73 1234 void __iomem *addr, *mem_ptr = NULL;
1fbe6323 1235 u32 data;
d8313ce0 1236
f58dbd73
NK		 1237 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1238 if (!addr)
1239 return -EIO;
3d396eb1 1240
f58dbd73 1241 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
f03b0ebd 1242 data = netxen_nic_io_read_128M(adapter, addr);
f58dbd73 1243 } else { /* Window 0 */
f03b0ebd 1244 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
907fa120 1245 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
195c5f98 1246 data = readl(addr);
907fa120
DP		 1247 netxen_nic_pci_set_crbwindow_128M(adapter,
1248 NETXEN_WINDOW_ONE);
f03b0ebd 1249 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
195c5f98 1250 }
3d396eb1 1251
f58dbd73
NK		 1252 if (mem_ptr)
1253 iounmap(mem_ptr);
1254
1fbe6323 1255 return data;
3d396eb1
AK		 1256}
1257
195c5f98 1258static int
1fbe6323 1259netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
3ce06a32 1260{
195c5f98 1261 unsigned long flags;
3ce06a32 1262 int rv;
a9ac07de 1263 void __iomem *addr = NULL;
3d396eb1 1264
a9ac07de 1265 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
3d396eb1 1266
7cecdca1 1267 if (rv == 0) {
a9ac07de 1268 writel(data, addr);
7cecdca1 1269 return 0;
3ce06a32
DP		 1270 }
1271
7cecdca1
DP		 1272 if (rv > 0) {
1273 /* indirect access */
f03b0ebd 1274 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
3ce06a32 1275 crb_win_lock(adapter);
a9ac07de
DP		 1276 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1277 writel(data, addr);
3ce06a32 1278 crb_win_unlock(adapter);
f03b0ebd 1279 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
7cecdca1
DP		 1280 return 0;
1281 }
3ce06a32 1282
7cecdca1
DP		 1283 dev_err(&adapter->pdev->dev,
1284 "%s: invalid offset: 0x%016lx\n", __func__, off);
1285 dump_stack();
1286 return -EIO;
3d396eb1
AK		 1287}
1288
195c5f98 1289static u32
1fbe6323 1290netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
3ce06a32 1291{
195c5f98 1292 unsigned long flags;
3ce06a32 1293 int rv;
1fbe6323 1294 u32 data;
a9ac07de 1295 void __iomem *addr = NULL;
3d396eb1 1296
a9ac07de 1297 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
3ce06a32 1298
7cecdca1 1299 if (rv == 0)
a9ac07de 1300 return readl(addr);
3ce06a32 1301
7cecdca1
DP		 1302 if (rv > 0) {
1303 /* indirect access */
f03b0ebd 1304 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
3ce06a32 1305 crb_win_lock(adapter);
a9ac07de
DP		 1306 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1307 data = readl(addr);
3ce06a32 1308 crb_win_unlock(adapter);
f03b0ebd 1309 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
7cecdca1
DP		 1310 return data;
1311 }
3ce06a32 1312
7cecdca1
DP		 1313 dev_err(&adapter->pdev->dev,
1314 "%s: invalid offset: 0x%016lx\n", __func__, off);
1315 dump_stack();
1316 return -1;
3ce06a32
DP		 1317}
1318
195c5f98
AKS		 1319/* window 1 registers only */
1320static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
1321 void __iomem *addr, u32 data)
3ce06a32 1322{
f03b0ebd 1323 read_lock(&adapter->ahw.crb_lock);
195c5f98 1324 writel(data, addr);
f03b0ebd 1325 read_unlock(&adapter->ahw.crb_lock);
195c5f98
AKS		 1326}
1327
1328static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
1329 void __iomem *addr)
1330{
1331 u32 val;
1332
f03b0ebd 1333 read_lock(&adapter->ahw.crb_lock);
195c5f98 1334 val = readl(addr);
f03b0ebd 1335 read_unlock(&adapter->ahw.crb_lock);
195c5f98
AKS		 1336
1337 return val;
3ce06a32
DP		 1338}
1339
195c5f98
AKS		 1340static void netxen_nic_io_write_2M(struct netxen_adapter *adapter,
1341 void __iomem *addr, u32 data)
3ce06a32 1342{
195c5f98
AKS		 1343 writel(data, addr);
1344}
1345
1346static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter,
1347 void __iomem *addr)
1348{
1349 return readl(addr);
1350}
1351
1352void __iomem *
1353netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset)
1354{
a9ac07de 1355 void __iomem *addr = NULL;
195c5f98
AKS		 1356
1357 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
a9ac07de
DP		 1358 if ((offset < NETXEN_CRB_PCIX_HOST2) &&
1359 (offset > NETXEN_CRB_PCIX_HOST))
1360 addr = PCI_OFFSET_SECOND_RANGE(adapter, offset);
1361 else
1362 addr = NETXEN_CRB_NORMALIZE(adapter, offset);
1363 } else {
1364 WARN_ON(netxen_nic_pci_get_crb_addr_2M(adapter,
1365 offset, &addr));
195c5f98
AKS		 1366 }
1367
a9ac07de 1368 return addr;
3ce06a32
DP		 1369}
1370
47abe356
DP		 1371static int
1372netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1373 u64 addr, u32 *start)
3ce06a32 1374{
47abe356
DP		 1375 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1376 *start = (addr - NETXEN_ADDR_OCM0 + NETXEN_PCI_OCM0);
1377 return 0;
3ce06a32 1378 } else if (ADDR_IN_RANGE(addr,
47abe356
DP		 1379 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1380 *start = (addr - NETXEN_ADDR_OCM1 + NETXEN_PCI_OCM1);
1381 return 0;
1382 }
3ce06a32 1383
47abe356
DP		 1384 return -EIO;
1385}
3ce06a32 1386
47abe356
DP		 1387static int
1388netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1389 u64 addr, u32 *start)
1390{
6abb4b83 1391 u32 window;
3ce06a32 1392
14e2cfbb 1393 window = OCM_WIN(addr);
6abb4b83 1394
47abe356 1395 writel(window, adapter->ahw.ocm_win_crb);
6abb4b83
AKS		 1396 /* read back to flush */
1397 readl(adapter->ahw.ocm_win_crb);
47abe356
DP		 1398
1399 adapter->ahw.ocm_win = window;
1400 *start = NETXEN_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
1401 return 0;
3ce06a32 1402}
47abe356
DP		 1403
1404static int
1405netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off,
1406 u64 *data, int op)
1407{
1408 void __iomem *addr, *mem_ptr = NULL;
1409 resource_size_t mem_base;
14e2cfbb 1410 int ret;
47abe356
DP		 1411 u32 start;
1412
f03b0ebd 1413 spin_lock(&adapter->ahw.mem_lock);
47abe356
DP		 1414
1415 ret = adapter->pci_set_window(adapter, off, &start);
1416 if (ret != 0)
1417 goto unlock;
1418
14e2cfbb
SC		 1419 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
1420 addr = adapter->ahw.pci_base0 + start;
1421 } else {
1422 addr = pci_base_offset(adapter, start);
1423 if (addr)
1424 goto noremap;
1425
1426 mem_base = pci_resource_start(adapter->pdev, 0) +
1427 (start & PAGE_MASK);
1428 mem_ptr = ioremap(mem_base, PAGE_SIZE);
1429 if (mem_ptr == NULL) {
1430 ret = -EIO;
1431 goto unlock;
1432 }
47abe356 1433
14e2cfbb 1434 addr = mem_ptr + (start & (PAGE_SIZE-1));
3d396eb1 1435 }
47abe356
DP		 1436noremap:
1437 if (op == 0) /* read */
1438 *data = readq(addr);
1439 else /* write */
1440 writeq(*data, addr);
1441
1442unlock:
f03b0ebd
DP		 1443 spin_unlock(&adapter->ahw.mem_lock);
1444
47abe356
DP		 1445 if (mem_ptr)
1446 iounmap(mem_ptr);
1447 return ret;
3d396eb1
AK		 1448}
1449
0b9715e6
AKS		 1450void
1451netxen_pci_camqm_read_2M(struct netxen_adapter *adapter, u64 off, u64 *data)
1452{
1453 void __iomem *addr = adapter->ahw.pci_base0 +
1454 NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM);
1455
1456 spin_lock(&adapter->ahw.mem_lock);
1457 *data = readq(addr);
1458 spin_unlock(&adapter->ahw.mem_lock);
1459}
1460
1461void
1462netxen_pci_camqm_write_2M(struct netxen_adapter *adapter, u64 off, u64 data)
1463{
1464 void __iomem *addr = adapter->ahw.pci_base0 +
1465 NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM);
1466
1467 spin_lock(&adapter->ahw.mem_lock);
1468 writeq(data, addr);
1469 spin_unlock(&adapter->ahw.mem_lock);
1470}
1471
3ce06a32
DP		 1472#define MAX_CTL_CHECK 1000
1473
195c5f98 1474static int
3ce06a32 1475netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1f5e055d 1476 u64 off, u64 data)
3ce06a32 1477{
1f5e055d
AKS		 1478 int j, ret;
1479 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
d8313ce0 1480 void __iomem *mem_crb;
3ce06a32 1481
1f5e055d
AKS		 1482 /* Only 64-bit aligned access */
1483 if (off & 7)
ea6828b8
DP		 1484 return -EIO;
1485
1f5e055d 1486 /* P2 has different SIU and MIU test agent base addr */
ea6828b8
DP		 1487 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1488 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1f5e055d
AKS		 1489 mem_crb = pci_base_offset(adapter,
1490 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1491 addr_hi = SIU_TEST_AGT_ADDR_HI;
1492 data_lo = SIU_TEST_AGT_WRDATA_LO;
1493 data_hi = SIU_TEST_AGT_WRDATA_HI;
1494 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1495 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
ea6828b8
DP		 1496 goto correct;
1497 }
3ce06a32 1498
ea6828b8 1499 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1f5e055d
AKS		 1500 mem_crb = pci_base_offset(adapter,
1501 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1502 addr_hi = MIU_TEST_AGT_ADDR_HI;
1503 data_lo = MIU_TEST_AGT_WRDATA_LO;
1504 data_hi = MIU_TEST_AGT_WRDATA_HI;
1505 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1506 off_hi = 0;
ea6828b8
DP		 1507 goto correct;
1508 }
1509
47abe356
DP		 1510 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1511 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1512 if (adapter->ahw.pci_len0 != 0) {
1513 return netxen_nic_pci_mem_access_direct(adapter,
1514 off, &data, 1);
1515 }
1516 }
1517
ea6828b8
DP		 1518 return -EIO;
1519
1520correct:
f03b0ebd 1521 spin_lock(&adapter->ahw.mem_lock);
907fa120 1522 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
3ce06a32 1523
1f5e055d
AKS		 1524 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1525 writel(off_hi, (mem_crb + addr_hi));
1526 writel(data & 0xffffffff, (mem_crb + data_lo));
1527 writel((data >> 32) & 0xffffffff, (mem_crb + data_hi));
1528 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1529 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1530 (mem_crb + TEST_AGT_CTRL));
1531
1532 for (j = 0; j < MAX_CTL_CHECK; j++) {
1533 temp = readl((mem_crb + TEST_AGT_CTRL));
1534 if ((temp & TA_CTL_BUSY) == 0)
3ce06a32 1535 break;
3ce06a32
DP		 1536 }
1537
1f5e055d
AKS		 1538 if (j >= MAX_CTL_CHECK) {
1539 if (printk_ratelimit())
1540 dev_err(&adapter->pdev->dev,
1541 "failed to write through agent\n");
1542 ret = -EIO;
1543 } else
1544 ret = 0;
1545
907fa120 1546 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
f03b0ebd 1547 spin_unlock(&adapter->ahw.mem_lock);
3ce06a32
DP		 1548 return ret;
1549}
1550
195c5f98 1551static int
3ce06a32 1552netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1f5e055d 1553 u64 off, u64 *data)
3ce06a32 1554{
1f5e055d
AKS		 1555 int j, ret;
1556 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1557 u64 val;
d8313ce0 1558 void __iomem *mem_crb;
3ce06a32 1559
1f5e055d
AKS		 1560 /* Only 64-bit aligned access */
1561 if (off & 7)
ea6828b8
DP		 1562 return -EIO;
1563
1f5e055d 1564 /* P2 has different SIU and MIU test agent base addr */
ea6828b8
DP		 1565 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1566 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1f5e055d
AKS		 1567 mem_crb = pci_base_offset(adapter,
1568 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1569 addr_hi = SIU_TEST_AGT_ADDR_HI;
1570 data_lo = SIU_TEST_AGT_RDDATA_LO;
1571 data_hi = SIU_TEST_AGT_RDDATA_HI;
1572 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1573 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
ea6828b8
DP		 1574 goto correct;
1575 }
3ce06a32 1576
ea6828b8 1577 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1f5e055d
AKS		 1578 mem_crb = pci_base_offset(adapter,
1579 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1580 addr_hi = MIU_TEST_AGT_ADDR_HI;
1581 data_lo = MIU_TEST_AGT_RDDATA_LO;
1582 data_hi = MIU_TEST_AGT_RDDATA_HI;
1583 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1584 off_hi = 0;
ea6828b8
DP		 1585 goto correct;
1586 }
1587
47abe356
DP		 1588 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1589 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1590 if (adapter->ahw.pci_len0 != 0) {
1591 return netxen_nic_pci_mem_access_direct(adapter,
1592 off, data, 0);
1593 }
1594 }
1595
ea6828b8 1596 return -EIO;
3ce06a32 1597
ea6828b8 1598correct:
f03b0ebd 1599 spin_lock(&adapter->ahw.mem_lock);
907fa120 1600 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
3ce06a32 1601
1f5e055d
AKS		 1602 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1603 writel(off_hi, (mem_crb + addr_hi));
1604 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1605 writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
3ce06a32 1606
1f5e055d
AKS		 1607 for (j = 0; j < MAX_CTL_CHECK; j++) {
1608 temp = readl(mem_crb + TEST_AGT_CTRL);
1609 if ((temp & TA_CTL_BUSY) == 0)
3ce06a32 1610 break;
1f5e055d 1611 }
3ce06a32 1612
1f5e055d
AKS		 1613 if (j >= MAX_CTL_CHECK) {
1614 if (printk_ratelimit())
1615 dev_err(&adapter->pdev->dev,
1616 "failed to read through agent\n");
1617 ret = -EIO;
1618 } else {
1619
1620 temp = readl(mem_crb + data_hi);
1621 val = ((u64)temp << 32);
1622 val |= readl(mem_crb + data_lo);
1623 *data = val;
1624 ret = 0;
3ce06a32
DP		 1625 }
1626
907fa120 1627 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
f03b0ebd 1628 spin_unlock(&adapter->ahw.mem_lock);
3ce06a32 1629
1f5e055d 1630 return ret;
3ce06a32
DP		 1631}
1632
195c5f98 1633static int
3ce06a32 1634netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1f5e055d 1635 u64 off, u64 data)
3ce06a32 1636{
215387a4 1637 int j, ret;
1f5e055d 1638 u32 temp, off8;
ea6828b8 1639 void __iomem *mem_crb;
3ce06a32 1640
1f5e055d
AKS		 1641 /* Only 64-bit aligned access */
1642 if (off & 7)
ea6828b8
DP		 1643 return -EIO;
1644
1f5e055d 1645 /* P3 onward, test agent base for MIU and SIU is same */
ea6828b8
DP		 1646 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1647 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1f5e055d
AKS		 1648 mem_crb = netxen_get_ioaddr(adapter,
1649 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
ea6828b8
DP		 1650 goto correct;
1651 }
1652
1653 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1f5e055d
AKS		 1654 mem_crb = netxen_get_ioaddr(adapter,
1655 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
ea6828b8 1656 goto correct;
3ce06a32
DP		 1657 }
1658
47abe356
DP		 1659 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX))
1660 return netxen_nic_pci_mem_access_direct(adapter, off, &data, 1);
1661
ea6828b8
DP		 1662 return -EIO;
1663
1664correct:
215387a4 1665 off8 = off & 0xfffffff8;
3ce06a32 1666
f03b0ebd 1667 spin_lock(&adapter->ahw.mem_lock);
3ce06a32 1668
1f5e055d
AKS		 1669 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1670 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
fb1f6a43 1671
fb1f6a43 1672 writel(data & 0xffffffff,
215387a4 1673 mem_crb + MIU_TEST_AGT_WRDATA_LO);
fb1f6a43 1674 writel((data >> 32) & 0xffffffff,
215387a4 1675 mem_crb + MIU_TEST_AGT_WRDATA_HI);
fb1f6a43 1676
1f5e055d
AKS		 1677 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1678 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1679 (mem_crb + TEST_AGT_CTRL));
1680
1681 for (j = 0; j < MAX_CTL_CHECK; j++) {
1682 temp = readl(mem_crb + TEST_AGT_CTRL);
1683 if ((temp & TA_CTL_BUSY) == 0)
1684 break;
3ce06a32
DP		 1685 }
1686
1f5e055d
AKS		 1687 if (j >= MAX_CTL_CHECK) {
1688 if (printk_ratelimit())
1689 dev_err(&adapter->pdev->dev,
39754f44 1690 "failed to write through agent\n");
1f5e055d
AKS		 1691 ret = -EIO;
1692 } else
1693 ret = 0;
1694
f03b0ebd 1695 spin_unlock(&adapter->ahw.mem_lock);
3ce06a32 1696
3ce06a32
DP		 1697 return ret;
1698}
1699
195c5f98 1700static int
3ce06a32 1701netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1f5e055d 1702 u64 off, u64 *data)
3ce06a32 1703{
1f5e055d
AKS		 1704 int j, ret;
1705 u32 temp, off8;
215387a4 1706 u64 val;
ea6828b8 1707 void __iomem *mem_crb;
3ce06a32 1708
1f5e055d
AKS		 1709 /* Only 64-bit aligned access */
1710 if (off & 7)
ea6828b8 1711 return -EIO;
3ce06a32 1712
1f5e055d 1713 /* P3 onward, test agent base for MIU and SIU is same */
ea6828b8
DP		 1714 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1715 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1f5e055d
AKS		 1716 mem_crb = netxen_get_ioaddr(adapter,
1717 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
ea6828b8 1718 goto correct;
3ce06a32
DP		 1719 }
1720
ea6828b8 1721 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1f5e055d
AKS		 1722 mem_crb = netxen_get_ioaddr(adapter,
1723 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
ea6828b8
DP		 1724 goto correct;
1725 }
1726
907fa120
DP		 1727 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1728 return netxen_nic_pci_mem_access_direct(adapter,
1729 off, data, 0);
1730 }
47abe356 1731
ea6828b8
DP		 1732 return -EIO;
1733
1734correct:
215387a4 1735 off8 = off & 0xfffffff8;
3ce06a32 1736
f03b0ebd 1737 spin_lock(&adapter->ahw.mem_lock);
3ce06a32 1738
1f5e055d
AKS		 1739 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1740 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1741 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1742 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
3ce06a32 1743
1f5e055d
AKS		 1744 for (j = 0; j < MAX_CTL_CHECK; j++) {
1745 temp = readl(mem_crb + TEST_AGT_CTRL);
1746 if ((temp & TA_CTL_BUSY) == 0)
3ce06a32 1747 break;
3ce06a32
DP		 1748 }
1749
1f5e055d
AKS		 1750 if (j >= MAX_CTL_CHECK) {
1751 if (printk_ratelimit())
1752 dev_err(&adapter->pdev->dev,
1753 "failed to read through agent\n");
1754 ret = -EIO;
3ce06a32 1755 } else {
215387a4
SC		 1756 val = (u64)(readl(mem_crb + MIU_TEST_AGT_RDDATA_HI)) << 32;
1757 val |= readl(mem_crb + MIU_TEST_AGT_RDDATA_LO);
1f5e055d
AKS		 1758 *data = val;
1759 ret = 0;
3ce06a32
DP		 1760 }
1761
f03b0ebd 1762 spin_unlock(&adapter->ahw.mem_lock);
1f5e055d
AKS		 1763
1764 return ret;
3ce06a32
DP		 1765}
1766
195c5f98
AKS		 1767void
1768netxen_setup_hwops(struct netxen_adapter *adapter)
3ce06a32 1769{
195c5f98
AKS		 1770 adapter->init_port = netxen_niu_xg_init_port;
1771 adapter->stop_port = netxen_niu_disable_xg_port;
3ce06a32 1772
195c5f98
AKS		 1773 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1774 adapter->crb_read = netxen_nic_hw_read_wx_128M,
1775 adapter->crb_write = netxen_nic_hw_write_wx_128M,
1776 adapter->pci_set_window = netxen_nic_pci_set_window_128M,
1777 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M,
1778 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M,
1779 adapter->io_read = netxen_nic_io_read_128M,
1780 adapter->io_write = netxen_nic_io_write_128M,
1781
1782 adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
1783 adapter->set_multi = netxen_p2_nic_set_multi;
1784 adapter->set_mtu = netxen_nic_set_mtu_xgb;
1785 adapter->set_promisc = netxen_p2_nic_set_promisc;
3ce06a32 1786
195c5f98
AKS		 1787 } else {
1788 adapter->crb_read = netxen_nic_hw_read_wx_2M,
1789 adapter->crb_write = netxen_nic_hw_write_wx_2M,
1790 adapter->pci_set_window = netxen_nic_pci_set_window_2M,
1791 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M,
1792 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M,
1793 adapter->io_read = netxen_nic_io_read_2M,
1794 adapter->io_write = netxen_nic_io_write_2M,
1795
1796 adapter->set_mtu = nx_fw_cmd_set_mtu;
1797 adapter->set_promisc = netxen_p3_nic_set_promisc;
1798 adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
1799 adapter->set_multi = netxen_p3_nic_set_multi;
1800
1801 adapter->phy_read = nx_fw_cmd_query_phy;
1802 adapter->phy_write = nx_fw_cmd_set_phy;
1803 }
3ce06a32
DP		 1804}
1805
3d396eb1
AK		 1806int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1807{
0dc6d9cb 1808 int offset, board_type, magic;
1e2d0059 1809 struct pci_dev *pdev = adapter->pdev;
3d396eb1 1810
06db58c0 1811 offset = NX_FW_MAGIC_OFFSET;
1e2d0059
DP		 1812 if (netxen_rom_fast_read(adapter, offset, &magic))
1813 return -EIO;
3d396eb1 1814
0dc6d9cb
DP		 1815 if (magic != NETXEN_BDINFO_MAGIC) {
1816 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1817 magic);
1e2d0059 1818 return -EIO;
3d396eb1
AK		 1819 }
1820
06db58c0 1821 offset = NX_BRDTYPE_OFFSET;
1e2d0059
DP		 1822 if (netxen_rom_fast_read(adapter, offset, &board_type))
1823 return -EIO;
1824
1e2d0059 1825 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
f98a9f69 1826 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
c7860a2a 1827 if ((gpio & 0x8000) == 0)
1e2d0059 1828 board_type = NETXEN_BRDTYPE_P3_10G_TP;
c7860a2a
DP		 1829 }
1830
dce87b96 1831 adapter->ahw.board_type = board_type;
1832
e98e3350 1833 switch (board_type) {
3d396eb1 1834 case NETXEN_BRDTYPE_P2_SB35_4G:
1e2d0059 1835 adapter->ahw.port_type = NETXEN_NIC_GBE;
3d396eb1
AK		 1836 break;
1837 case NETXEN_BRDTYPE_P2_SB31_10G:
1838 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1839 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1840 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
e4c93c81
DP		 1841 case NETXEN_BRDTYPE_P3_HMEZ:
1842 case NETXEN_BRDTYPE_P3_XG_LOM:
1843 case NETXEN_BRDTYPE_P3_10G_CX4:
1844 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1845 case NETXEN_BRDTYPE_P3_IMEZ:
1846 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
a70f9393
DP		 1847 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1848 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
e4c93c81
DP		 1849 case NETXEN_BRDTYPE_P3_10G_XFP:
1850 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1e2d0059 1851 adapter->ahw.port_type = NETXEN_NIC_XGBE;
3d396eb1
AK		 1852 break;
1853 case NETXEN_BRDTYPE_P1_BD:
1854 case NETXEN_BRDTYPE_P1_SB:
1855 case NETXEN_BRDTYPE_P1_SMAX:
1856 case NETXEN_BRDTYPE_P1_SOCK:
e4c93c81
DP		 1857 case NETXEN_BRDTYPE_P3_REF_QG:
1858 case NETXEN_BRDTYPE_P3_4_GB:
1859 case NETXEN_BRDTYPE_P3_4_GB_MM:
1e2d0059 1860 adapter->ahw.port_type = NETXEN_NIC_GBE;
3d396eb1 1861 break;
c7860a2a 1862 case NETXEN_BRDTYPE_P3_10G_TP:
1e2d0059 1863 adapter->ahw.port_type = (adapter->portnum < 2) ?
c7860a2a
DP		 1864 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1865 break;
3d396eb1 1866 default:
1e2d0059
DP		 1867 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1868 adapter->ahw.port_type = NETXEN_NIC_XGBE;
3d396eb1
AK		 1869 break;
1870 }
1871
1e2d0059 1872 return 0;
3d396eb1
AK		 1873}
1874
1875/* NIU access sections */
1876
3176ff3e 1877int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 1878{
9ad27643 1879 new_mtu += MTU_FUDGE_FACTOR;
f98a9f69 1880 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
3276fbad 1881 new_mtu);
3d396eb1
AK		 1882 return 0;
1883}
1884
3176ff3e 1885int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 1886{
9ad27643 1887 new_mtu += MTU_FUDGE_FACTOR;
3276fbad 1888 if (adapter->physical_port == 0)
f98a9f69 1889 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
4790654c 1890 else
f98a9f69 1891 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
3d396eb1
AK		 1892 return 0;
1893}
1894
3176ff3e 1895void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
3d396eb1 1896{
a608ab9c
AV		 1897 __u32 status;
1898 __u32 autoneg;
24a7a455 1899 __u32 port_mode;
3d396eb1 1900
c7860a2a
DP		 1901 if (!netif_carrier_ok(adapter->netdev)) {
1902 adapter->link_speed = 0;
1903 adapter->link_duplex = -1;
1904 adapter->link_autoneg = AUTONEG_ENABLE;
1905 return;
1906 }
24a7a455 1907
1e2d0059 1908 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
f98a9f69 1909 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
24a7a455
DP		 1910 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
1911 adapter->link_speed = SPEED_1000;
1912 adapter->link_duplex = DUPLEX_FULL;
1913 adapter->link_autoneg = AUTONEG_DISABLE;
1914 return;
1915 }
1916
8e95a202
JP		 1917 if (adapter->phy_read &&
1918 adapter->phy_read(adapter,
1919 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1920 &status) == 0) {
3d396eb1
AK		 1921 if (netxen_get_phy_link(status)) {
1922 switch (netxen_get_phy_speed(status)) {
1923 case 0:
3176ff3e 1924 adapter->link_speed = SPEED_10;
3d396eb1
AK		 1925 break;
1926 case 1:
3176ff3e 1927 adapter->link_speed = SPEED_100;
3d396eb1
AK		 1928 break;
1929 case 2:
3176ff3e 1930 adapter->link_speed = SPEED_1000;
3d396eb1
AK		 1931 break;
1932 default:
c7860a2a 1933 adapter->link_speed = 0;
3d396eb1
AK		 1934 break;
1935 }
1936 switch (netxen_get_phy_duplex(status)) {
1937 case 0:
3176ff3e 1938 adapter->link_duplex = DUPLEX_HALF;
3d396eb1
AK		 1939 break;
1940 case 1:
3176ff3e 1941 adapter->link_duplex = DUPLEX_FULL;
3d396eb1
AK		 1942 break;
1943 default:
3176ff3e 1944 adapter->link_duplex = -1;
3d396eb1
AK		 1945 break;
1946 }
8e95a202
JP		 1947 if (adapter->phy_read &&
1948 adapter->phy_read(adapter,
1949 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1950 &autoneg) != 0)
3176ff3e 1951 adapter->link_autoneg = autoneg;
3d396eb1
AK		 1952 } else
1953 goto link_down;
1954 } else {
1955 link_down:
c7860a2a 1956 adapter->link_speed = 0;
3176ff3e 1957 adapter->link_duplex = -1;
3d396eb1
AK		 1958 }
1959 }
1960}
1961
0b72e659
DP		 1962int
1963netxen_nic_wol_supported(struct netxen_adapter *adapter)
1964{
1965 u32 wol_cfg;
1966
1967 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1968 return 0;
1969
f98a9f69 1970 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
0b72e659 1971 if (wol_cfg & (1UL << adapter->portnum)) {
f98a9f69 1972 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
0b72e659
DP		 1973 if (wol_cfg & (1 << adapter->portnum))
1974 return 1;
1975 }
1976
1977 return 0;
1978}
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