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1da177e4
LT		 1/* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
2/*
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
b27a16b7 6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org>
1da177e4
LT		 7
8 This software may be used and distributed according to the terms of
9 the GNU General Public License (GPL), incorporated herein by reference.
10 Drivers based on or derived from this code fall under the GPL and must
11 retain the authorship, copyright and license notice. This file is not
12 a complete program and may only be used when the entire operating
13 system is licensed under the GPL. License for under other terms may be
14 available. Contact the original author for details.
15
16 The original author may be reached as becker@scyld.com, or at
17 Scyld Computing Corporation
18 410 Severn Ave., Suite 210
19 Annapolis MD 21403
20
21 Support information and updates available at
22 http://www.scyld.com/network/netsemi.html
23
24
25 Linux kernel modifications:
26
27 Version 1.0.1:
28 - Spinlock fixes
29 - Bug fixes and better intr performance (Tjeerd)
30 Version 1.0.2:
31 - Now reads correct MAC address from eeprom
32 Version 1.0.3:
33 - Eliminate redundant priv->tx_full flag
34 - Call netif_start_queue from dev->tx_timeout
35 - wmb() in start_tx() to flush data
36 - Update Tx locking
37 - Clean up PCI enable (davej)
38 Version 1.0.4:
39 - Merge Donald Becker's natsemi.c version 1.07
40 Version 1.0.5:
41 - { fill me in }
42 Version 1.0.6:
43 * ethtool support (jgarzik)
44 * Proper initialization of the card (which sometimes
45 fails to occur and leaves the card in a non-functional
46 state). (uzi)
47
48 * Some documented register settings to optimize some
49 of the 100Mbit autodetection circuitry in rev C cards. (uzi)
50
51 * Polling of the PHY intr for stuff like link state
52 change and auto- negotiation to finally work properly. (uzi)
53
54 * One-liner removal of a duplicate declaration of
55 netdev_error(). (uzi)
56
57 Version 1.0.7: (Manfred Spraul)
58 * pci dma
59 * SMP locking update
60 * full reset added into tx_timeout
61 * correct multicast hash generation (both big and little endian)
62 [copied from a natsemi driver version
63 from Myrio Corporation, Greg Smith]
64 * suspend/resume
65
66 version 1.0.8 (Tim Hockin <thockin@sun.com>)
67 * ETHTOOL_* support
68 * Wake on lan support (Erik Gilling)
69 * MXDMA fixes for serverworks
70 * EEPROM reload
71
72 version 1.0.9 (Manfred Spraul)
73 * Main change: fix lack of synchronize
74 netif_close/netif_suspend against a last interrupt
75 or packet.
76 * do not enable superflous interrupts (e.g. the
77 drivers relies on TxDone - TxIntr not needed)
78 * wait that the hardware has really stopped in close
79 and suspend.
80 * workaround for the (at least) gcc-2.95.1 compiler
81 problem. Also simplifies the code a bit.
82 * disable_irq() in tx_timeout - needed to protect
83 against rx interrupts.
84 * stop the nic before switching into silent rx mode
85 for wol (required according to docu).
86
87 version 1.0.10:
88 * use long for ee_addr (various)
89 * print pointers properly (DaveM)
90 * include asm/irq.h (?)
91
92 version 1.0.11:
93 * check and reset if PHY errors appear (Adrian Sun)
94 * WoL cleanup (Tim Hockin)
95 * Magic number cleanup (Tim Hockin)
96 * Don't reload EEPROM on every reset (Tim Hockin)
97 * Save and restore EEPROM state across reset (Tim Hockin)
98 * MDIO Cleanup (Tim Hockin)
99 * Reformat register offsets/bits (jgarzik)
100
101 version 1.0.12:
102 * ETHTOOL_* further support (Tim Hockin)
103
104 version 1.0.13:
105 * ETHTOOL_[G]EEPROM support (Tim Hockin)
106
107 version 1.0.13:
108 * crc cleanup (Matt Domsch <Matt_Domsch@dell.com>)
109
110 version 1.0.14:
111 * Cleanup some messages and autoneg in ethtool (Tim Hockin)
112
113 version 1.0.15:
114 * Get rid of cable_magic flag
115 * use new (National provided) solution for cable magic issue
116
117 version 1.0.16:
118 * call netdev_rx() for RxErrors (Manfred Spraul)
119 * formatting and cleanups
120 * change options and full_duplex arrays to be zero
121 initialized
122 * enable only the WoL and PHY interrupts in wol mode
123
124 version 1.0.17:
125 * only do cable_magic on 83815 and early 83816 (Tim Hockin)
126 * create a function for rx refill (Manfred Spraul)
127 * combine drain_ring and init_ring (Manfred Spraul)
128 * oom handling (Manfred Spraul)
129 * hands_off instead of playing with netif_device_{de,a}ttach
130 (Manfred Spraul)
131 * be sure to write the MAC back to the chip (Manfred Spraul)
132 * lengthen EEPROM timeout, and always warn about timeouts
133 (Manfred Spraul)
134 * comments update (Manfred)
135 * do the right thing on a phy-reset (Manfred and Tim)
136
137 TODO:
138 * big endian support with CFG:BEM instead of cpu_to_le32
1da177e4
LT		 139*/
140
141#include <linux/config.h>
142#include <linux/module.h>
143#include <linux/kernel.h>
144#include <linux/string.h>
145#include <linux/timer.h>
146#include <linux/errno.h>
147#include <linux/ioport.h>
148#include <linux/slab.h>
149#include <linux/interrupt.h>
150#include <linux/pci.h>
151#include <linux/netdevice.h>
152#include <linux/etherdevice.h>
153#include <linux/skbuff.h>
154#include <linux/init.h>
155#include <linux/spinlock.h>
156#include <linux/ethtool.h>
157#include <linux/delay.h>
158#include <linux/rtnetlink.h>
159#include <linux/mii.h>
160#include <linux/crc32.h>
161#include <linux/bitops.h>
b27a16b7 162#include <linux/prefetch.h>
1da177e4
LT		 163#include <asm/processor.h> /* Processor type for cache alignment. */
164#include <asm/io.h>
165#include <asm/irq.h>
166#include <asm/uaccess.h>
167
168#define DRV_NAME "natsemi"
169#define DRV_VERSION "1.07+LK1.0.17"
170#define DRV_RELDATE "Sep 27, 2002"
171
172#define RX_OFFSET 2
173
174/* Updated to recommendations in pci-skeleton v2.03. */
175
176/* The user-configurable values.
177 These may be modified when a driver module is loaded.*/
178
179#define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
180 NETIF_MSG_LINK | \
181 NETIF_MSG_WOL | \
182 NETIF_MSG_RX_ERR | \
183 NETIF_MSG_TX_ERR)
184static int debug = -1;
185
1da177e4
LT		 186static int mtu;
187
188/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
189 This chip uses a 512 element hash table based on the Ethernet CRC. */
f71e1309 190static const int multicast_filter_limit = 100;
1da177e4
LT		 191
192/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
193 Setting to > 1518 effectively disables this feature. */
194static int rx_copybreak;
195
196/* Used to pass the media type, etc.
197 Both 'options[]' and 'full_duplex[]' should exist for driver
198 interoperability.
199 The media type is usually passed in 'options[]'.
200*/
201#define MAX_UNITS 8 /* More are supported, limit only on options */
202static int options[MAX_UNITS];
203static int full_duplex[MAX_UNITS];
204
205/* Operational parameters that are set at compile time. */
206
207/* Keep the ring sizes a power of two for compile efficiency.
208 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
209 Making the Tx ring too large decreases the effectiveness of channel
210 bonding and packet priority.
211 There are no ill effects from too-large receive rings. */
212#define TX_RING_SIZE 16
213#define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
214#define RX_RING_SIZE 32
215
216/* Operational parameters that usually are not changed. */
217/* Time in jiffies before concluding the transmitter is hung. */
218#define TX_TIMEOUT (2*HZ)
219
220#define NATSEMI_HW_TIMEOUT 400
221#define NATSEMI_TIMER_FREQ 3*HZ
222#define NATSEMI_PG0_NREGS 64
223#define NATSEMI_RFDR_NREGS 8
224#define NATSEMI_PG1_NREGS 4
225#define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
226 NATSEMI_PG1_NREGS)
227#define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
228#define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
229#define NATSEMI_EEPROM_SIZE 24 /* 12 16-bit values */
230
231/* Buffer sizes:
232 * The nic writes 32-bit values, even if the upper bytes of
233 * a 32-bit value are beyond the end of the buffer.
234 */
235#define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
236#define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
237#define NATSEMI_LONGPKT 1518 /* limit for normal packets */
238#define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
239
240/* These identify the driver base version and may not be removed. */
241static char version[] __devinitdata =
242 KERN_INFO DRV_NAME " dp8381x driver, version "
243 DRV_VERSION ", " DRV_RELDATE "\n"
244 KERN_INFO " originally by Donald Becker <becker@scyld.com>\n"
245 KERN_INFO " http://www.scyld.com/network/natsemi.html\n"
246 KERN_INFO " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
247
248MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
249MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
250MODULE_LICENSE("GPL");
251
1da177e4
LT		 252module_param(mtu, int, 0);
253module_param(debug, int, 0);
254module_param(rx_copybreak, int, 0);
255module_param_array(options, int, NULL, 0);
256module_param_array(full_duplex, int, NULL, 0);
1da177e4
LT		 257MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
258MODULE_PARM_DESC(debug, "DP8381x default debug level");
259MODULE_PARM_DESC(rx_copybreak,
260 "DP8381x copy breakpoint for copy-only-tiny-frames");
261MODULE_PARM_DESC(options,
262 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
263MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
264
265/*
266 Theory of Operation
267
268I. Board Compatibility
269
270This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
271It also works with other chips in in the DP83810 series.
272
273II. Board-specific settings
274
275This driver requires the PCI interrupt line to be valid.
276It honors the EEPROM-set values.
277
278III. Driver operation
279
280IIIa. Ring buffers
281
282This driver uses two statically allocated fixed-size descriptor lists
283formed into rings by a branch from the final descriptor to the beginning of
284the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
285The NatSemi design uses a 'next descriptor' pointer that the driver forms
286into a list.
287
288IIIb/c. Transmit/Receive Structure
289
290This driver uses a zero-copy receive and transmit scheme.
291The driver allocates full frame size skbuffs for the Rx ring buffers at
292open() time and passes the skb->data field to the chip as receive data
293buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
294a fresh skbuff is allocated and the frame is copied to the new skbuff.
295When the incoming frame is larger, the skbuff is passed directly up the
296protocol stack. Buffers consumed this way are replaced by newly allocated
297skbuffs in a later phase of receives.
298
299The RX_COPYBREAK value is chosen to trade-off the memory wasted by
300using a full-sized skbuff for small frames vs. the copying costs of larger
301frames. New boards are typically used in generously configured machines
302and the underfilled buffers have negligible impact compared to the benefit of
303a single allocation size, so the default value of zero results in never
304copying packets. When copying is done, the cost is usually mitigated by using
305a combined copy/checksum routine. Copying also preloads the cache, which is
306most useful with small frames.
307
308A subtle aspect of the operation is that unaligned buffers are not permitted
309by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
310longword aligned for further processing. On copies frames are put into the
311skbuff at an offset of "+2", 16-byte aligning the IP header.
312
313IIId. Synchronization
314
315Most operations are synchronized on the np->lock irq spinlock, except the
316performance critical codepaths:
317
318The rx process only runs in the interrupt handler. Access from outside
319the interrupt handler is only permitted after disable_irq().
320
321The rx process usually runs under the dev->xmit_lock. If np->intr_tx_reap
322is set, then access is permitted under spin_lock_irq(&np->lock).
323
324Thus configuration functions that want to access everything must call
325 disable_irq(dev->irq);
326 spin_lock_bh(dev->xmit_lock);
327 spin_lock_irq(&np->lock);
328
329IV. Notes
330
331NatSemi PCI network controllers are very uncommon.
332
333IVb. References
334
335http://www.scyld.com/expert/100mbps.html
336http://www.scyld.com/expert/NWay.html
337Datasheet is available from:
338http://www.national.com/pf/DP/DP83815.html
339
340IVc. Errata
341
342None characterised.
343*/
344
345
346
347enum pcistuff {
348 PCI_USES_IO = 0x01,
349 PCI_USES_MEM = 0x02,
350 PCI_USES_MASTER = 0x04,
351 PCI_ADDR0 = 0x08,
352 PCI_ADDR1 = 0x10,
353};
354
355/* MMIO operations required */
356#define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_MEM | PCI_ADDR1)
357
358
359/*
360 * Support for fibre connections on Am79C874:
361 * This phy needs a special setup when connected to a fibre cable.
362 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
363 */
364#define PHYID_AM79C874 0x0022561b
365
366#define MII_MCTRL 0x15 /* mode control register */
367#define MII_FX_SEL 0x0001 /* 100BASE-FX (fiber) */
368#define MII_EN_SCRM 0x0004 /* enable scrambler (tp) */
369
370
371/* array of board data directly indexed by pci_tbl[x].driver_data */
f71e1309 372static const struct {
1da177e4
LT		 373 const char *name;
374 unsigned long flags;
375} natsemi_pci_info[] __devinitdata = {
376 { "NatSemi DP8381[56]", PCI_IOTYPE },
377};
378
379static struct pci_device_id natsemi_pci_tbl[] = {
380 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID, PCI_ANY_ID, },
381 { 0, },
382};
383MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
384
385/* Offsets to the device registers.
386 Unlike software-only systems, device drivers interact with complex hardware.
387 It's not useful to define symbolic names for every register bit in the
388 device.
389*/
390enum register_offsets {
391 ChipCmd = 0x00,
392 ChipConfig = 0x04,
393 EECtrl = 0x08,
394 PCIBusCfg = 0x0C,
395 IntrStatus = 0x10,
396 IntrMask = 0x14,
397 IntrEnable = 0x18,
398 IntrHoldoff = 0x1C, /* DP83816 only */
399 TxRingPtr = 0x20,
400 TxConfig = 0x24,
401 RxRingPtr = 0x30,
402 RxConfig = 0x34,
403 ClkRun = 0x3C,
404 WOLCmd = 0x40,
405 PauseCmd = 0x44,
406 RxFilterAddr = 0x48,
407 RxFilterData = 0x4C,
408 BootRomAddr = 0x50,
409 BootRomData = 0x54,
410 SiliconRev = 0x58,
411 StatsCtrl = 0x5C,
412 StatsData = 0x60,
413 RxPktErrs = 0x60,
414 RxMissed = 0x68,
415 RxCRCErrs = 0x64,
416 BasicControl = 0x80,
417 BasicStatus = 0x84,
418 AnegAdv = 0x90,
419 AnegPeer = 0x94,
420 PhyStatus = 0xC0,
421 MIntrCtrl = 0xC4,
422 MIntrStatus = 0xC8,
423 PhyCtrl = 0xE4,
424
425 /* These are from the spec, around page 78... on a separate table.
426 * The meaning of these registers depend on the value of PGSEL. */
427 PGSEL = 0xCC,
428 PMDCSR = 0xE4,
429 TSTDAT = 0xFC,
430 DSPCFG = 0xF4,
431 SDCFG = 0xF8
432};
433/* the values for the 'magic' registers above (PGSEL=1) */
434#define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
435#define TSTDAT_VAL 0x0
436#define DSPCFG_VAL 0x5040
437#define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
438#define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
439#define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
440#define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
441
442/* misc PCI space registers */
443enum pci_register_offsets {
444 PCIPM = 0x44,
445};
446
447enum ChipCmd_bits {
448 ChipReset = 0x100,
449 RxReset = 0x20,
450 TxReset = 0x10,
451 RxOff = 0x08,
452 RxOn = 0x04,
453 TxOff = 0x02,
454 TxOn = 0x01,
455};
456
457enum ChipConfig_bits {
458 CfgPhyDis = 0x200,
459 CfgPhyRst = 0x400,
460 CfgExtPhy = 0x1000,
461 CfgAnegEnable = 0x2000,
462 CfgAneg100 = 0x4000,
463 CfgAnegFull = 0x8000,
464 CfgAnegDone = 0x8000000,
465 CfgFullDuplex = 0x20000000,
466 CfgSpeed100 = 0x40000000,
467 CfgLink = 0x80000000,
468};
469
470enum EECtrl_bits {
471 EE_ShiftClk = 0x04,
472 EE_DataIn = 0x01,
473 EE_ChipSelect = 0x08,
474 EE_DataOut = 0x02,
475 MII_Data = 0x10,
476 MII_Write = 0x20,
477 MII_ShiftClk = 0x40,
478};
479
480enum PCIBusCfg_bits {
481 EepromReload = 0x4,
482};
483
484/* Bits in the interrupt status/mask registers. */
485enum IntrStatus_bits {
486 IntrRxDone = 0x0001,
487 IntrRxIntr = 0x0002,
488 IntrRxErr = 0x0004,
489 IntrRxEarly = 0x0008,
490 IntrRxIdle = 0x0010,
491 IntrRxOverrun = 0x0020,
492 IntrTxDone = 0x0040,
493 IntrTxIntr = 0x0080,
494 IntrTxErr = 0x0100,
495 IntrTxIdle = 0x0200,
496 IntrTxUnderrun = 0x0400,
497 StatsMax = 0x0800,
498 SWInt = 0x1000,
499 WOLPkt = 0x2000,
500 LinkChange = 0x4000,
501 IntrHighBits = 0x8000,
502 RxStatusFIFOOver = 0x10000,
503 IntrPCIErr = 0xf00000,
504 RxResetDone = 0x1000000,
505 TxResetDone = 0x2000000,
506 IntrAbnormalSummary = 0xCD20,
507};
508
509/*
510 * Default Interrupts:
511 * Rx OK, Rx Packet Error, Rx Overrun,
512 * Tx OK, Tx Packet Error, Tx Underrun,
513 * MIB Service, Phy Interrupt, High Bits,
514 * Rx Status FIFO overrun,
515 * Received Target Abort, Received Master Abort,
516 * Signalled System Error, Received Parity Error
517 */
518#define DEFAULT_INTR 0x00f1cd65
519
520enum TxConfig_bits {
521 TxDrthMask = 0x3f,
522 TxFlthMask = 0x3f00,
523 TxMxdmaMask = 0x700000,
524 TxMxdma_512 = 0x0,
525 TxMxdma_4 = 0x100000,
526 TxMxdma_8 = 0x200000,
527 TxMxdma_16 = 0x300000,
528 TxMxdma_32 = 0x400000,
529 TxMxdma_64 = 0x500000,
530 TxMxdma_128 = 0x600000,
531 TxMxdma_256 = 0x700000,
532 TxCollRetry = 0x800000,
533 TxAutoPad = 0x10000000,
534 TxMacLoop = 0x20000000,
535 TxHeartIgn = 0x40000000,
536 TxCarrierIgn = 0x80000000
537};
538
539/*
540 * Tx Configuration:
541 * - 256 byte DMA burst length
542 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
543 * - 64 bytes initial drain threshold (i.e. begin actual transmission
544 * when 64 byte are in the fifo)
545 * - on tx underruns, increase drain threshold by 64.
546 * - at most use a drain threshold of 1472 bytes: The sum of the fill
547 * threshold and the drain threshold must be less than 2016 bytes.
548 *
549 */
550#define TX_FLTH_VAL ((512/32) << 8)
551#define TX_DRTH_VAL_START (64/32)
552#define TX_DRTH_VAL_INC 2
553#define TX_DRTH_VAL_LIMIT (1472/32)
554
555enum RxConfig_bits {
556 RxDrthMask = 0x3e,
557 RxMxdmaMask = 0x700000,
558 RxMxdma_512 = 0x0,
559 RxMxdma_4 = 0x100000,
560 RxMxdma_8 = 0x200000,
561 RxMxdma_16 = 0x300000,
562 RxMxdma_32 = 0x400000,
563 RxMxdma_64 = 0x500000,
564 RxMxdma_128 = 0x600000,
565 RxMxdma_256 = 0x700000,
566 RxAcceptLong = 0x8000000,
567 RxAcceptTx = 0x10000000,
568 RxAcceptRunt = 0x40000000,
569 RxAcceptErr = 0x80000000
570};
571#define RX_DRTH_VAL (128/8)
572
573enum ClkRun_bits {
574 PMEEnable = 0x100,
575 PMEStatus = 0x8000,
576};
577
578enum WolCmd_bits {
579 WakePhy = 0x1,
580 WakeUnicast = 0x2,
581 WakeMulticast = 0x4,
582 WakeBroadcast = 0x8,
583 WakeArp = 0x10,
584 WakePMatch0 = 0x20,
585 WakePMatch1 = 0x40,
586 WakePMatch2 = 0x80,
587 WakePMatch3 = 0x100,
588 WakeMagic = 0x200,
589 WakeMagicSecure = 0x400,
590 SecureHack = 0x100000,
591 WokePhy = 0x400000,
592 WokeUnicast = 0x800000,
593 WokeMulticast = 0x1000000,
594 WokeBroadcast = 0x2000000,
595 WokeArp = 0x4000000,
596 WokePMatch0 = 0x8000000,
597 WokePMatch1 = 0x10000000,
598 WokePMatch2 = 0x20000000,
599 WokePMatch3 = 0x40000000,
600 WokeMagic = 0x80000000,
601 WakeOptsSummary = 0x7ff
602};
603
604enum RxFilterAddr_bits {
605 RFCRAddressMask = 0x3ff,
606 AcceptMulticast = 0x00200000,
607 AcceptMyPhys = 0x08000000,
608 AcceptAllPhys = 0x10000000,
609 AcceptAllMulticast = 0x20000000,
610 AcceptBroadcast = 0x40000000,
611 RxFilterEnable = 0x80000000
612};
613
614enum StatsCtrl_bits {
615 StatsWarn = 0x1,
616 StatsFreeze = 0x2,
617 StatsClear = 0x4,
618 StatsStrobe = 0x8,
619};
620
621enum MIntrCtrl_bits {
622 MICRIntEn = 0x2,
623};
624
625enum PhyCtrl_bits {
626 PhyAddrMask = 0x1f,
627};
628
629#define PHY_ADDR_NONE 32
630#define PHY_ADDR_INTERNAL 1
631
632/* values we might find in the silicon revision register */
633#define SRR_DP83815_C 0x0302
634#define SRR_DP83815_D 0x0403
635#define SRR_DP83816_A4 0x0504
636#define SRR_DP83816_A5 0x0505
637
638/* The Rx and Tx buffer descriptors. */
639/* Note that using only 32 bit fields simplifies conversion to big-endian
640 architectures. */
641struct netdev_desc {
642 u32 next_desc;
643 s32 cmd_status;
644 u32 addr;
645 u32 software_use;
646};
647
648/* Bits in network_desc.status */
649enum desc_status_bits {
650 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
651 DescNoCRC=0x10000000, DescPktOK=0x08000000,
652 DescSizeMask=0xfff,
653
654 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
655 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
656 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
657 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
658
659 DescRxAbort=0x04000000, DescRxOver=0x02000000,
660 DescRxDest=0x01800000, DescRxLong=0x00400000,
661 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
662 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
663 DescRxLoop=0x00020000, DesRxColl=0x00010000,
664};
665
666struct netdev_private {
667 /* Descriptor rings first for alignment */
668 dma_addr_t ring_dma;
669 struct netdev_desc *rx_ring;
670 struct netdev_desc *tx_ring;
671 /* The addresses of receive-in-place skbuffs */
672 struct sk_buff *rx_skbuff[RX_RING_SIZE];
673 dma_addr_t rx_dma[RX_RING_SIZE];
674 /* address of a sent-in-place packet/buffer, for later free() */
675 struct sk_buff *tx_skbuff[TX_RING_SIZE];
676 dma_addr_t tx_dma[TX_RING_SIZE];
677 struct net_device_stats stats;
678 /* Media monitoring timer */
679 struct timer_list timer;
680 /* Frequently used values: keep some adjacent for cache effect */
681 struct pci_dev *pci_dev;
682 struct netdev_desc *rx_head_desc;
683 /* Producer/consumer ring indices */
684 unsigned int cur_rx, dirty_rx;
685 unsigned int cur_tx, dirty_tx;
686 /* Based on MTU+slack. */
687 unsigned int rx_buf_sz;
688 int oom;
b27a16b7
MB		 689 /* Interrupt status */
690 u32 intr_status;
1da177e4
LT		 691 /* Do not touch the nic registers */
692 int hands_off;
693 /* external phy that is used: only valid if dev->if_port != PORT_TP */
694 int mii;
695 int phy_addr_external;
696 unsigned int full_duplex;
697 /* Rx filter */
698 u32 cur_rx_mode;
699 u32 rx_filter[16];
700 /* FIFO and PCI burst thresholds */
701 u32 tx_config, rx_config;
702 /* original contents of ClkRun register */
703 u32 SavedClkRun;
704 /* silicon revision */
705 u32 srr;
706 /* expected DSPCFG value */
707 u16 dspcfg;
708 /* parms saved in ethtool format */
709 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
710 u8 duplex; /* Duplex, half or full */
711 u8 autoneg; /* Autonegotiation enabled */
712 /* MII transceiver section */
713 u16 advertising;
714 unsigned int iosize;
715 spinlock_t lock;
716 u32 msg_enable;
717};
718
719static void move_int_phy(struct net_device *dev, int addr);
720static int eeprom_read(void __iomem *ioaddr, int location);
721static int mdio_read(struct net_device *dev, int reg);
722static void mdio_write(struct net_device *dev, int reg, u16 data);
723static void init_phy_fixup(struct net_device *dev);
724static int miiport_read(struct net_device *dev, int phy_id, int reg);
725static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
726static int find_mii(struct net_device *dev);
727static void natsemi_reset(struct net_device *dev);
728static void natsemi_reload_eeprom(struct net_device *dev);
729static void natsemi_stop_rxtx(struct net_device *dev);
730static int netdev_open(struct net_device *dev);
731static void do_cable_magic(struct net_device *dev);
732static void undo_cable_magic(struct net_device *dev);
733static void check_link(struct net_device *dev);
734static void netdev_timer(unsigned long data);
735static void dump_ring(struct net_device *dev);
736static void tx_timeout(struct net_device *dev);
737static int alloc_ring(struct net_device *dev);
738static void refill_rx(struct net_device *dev);
739static void init_ring(struct net_device *dev);
740static void drain_tx(struct net_device *dev);
741static void drain_ring(struct net_device *dev);
742static void free_ring(struct net_device *dev);
743static void reinit_ring(struct net_device *dev);
744static void init_registers(struct net_device *dev);
745static int start_tx(struct sk_buff *skb, struct net_device *dev);
746static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
747static void netdev_error(struct net_device *dev, int intr_status);
b27a16b7
MB		 748static int natsemi_poll(struct net_device *dev, int *budget);
749static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
1da177e4
LT		 750static void netdev_tx_done(struct net_device *dev);
751static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
752#ifdef CONFIG_NET_POLL_CONTROLLER
753static void natsemi_poll_controller(struct net_device *dev);
754#endif
755static void __set_rx_mode(struct net_device *dev);
756static void set_rx_mode(struct net_device *dev);
757static void __get_stats(struct net_device *dev);
758static struct net_device_stats *get_stats(struct net_device *dev);
759static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
760static int netdev_set_wol(struct net_device *dev, u32 newval);
761static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
762static int netdev_set_sopass(struct net_device *dev, u8 *newval);
763static int netdev_get_sopass(struct net_device *dev, u8 *data);
764static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
765static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
766static void enable_wol_mode(struct net_device *dev, int enable_intr);
767static int netdev_close(struct net_device *dev);
768static int netdev_get_regs(struct net_device *dev, u8 *buf);
769static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
770static struct ethtool_ops ethtool_ops;
771
772static inline void __iomem *ns_ioaddr(struct net_device *dev)
773{
774 return (void __iomem *) dev->base_addr;
775}
776
b27a16b7
MB		 777static inline void natsemi_irq_enable(struct net_device *dev)
778{
779 writel(1, ns_ioaddr(dev) + IntrEnable);
780 readl(ns_ioaddr(dev) + IntrEnable);
781}
782
783static inline void natsemi_irq_disable(struct net_device *dev)
784{
785 writel(0, ns_ioaddr(dev) + IntrEnable);
786 readl(ns_ioaddr(dev) + IntrEnable);
787}
788
1da177e4
LT		 789static void move_int_phy(struct net_device *dev, int addr)
790{
791 struct netdev_private *np = netdev_priv(dev);
792 void __iomem *ioaddr = ns_ioaddr(dev);
793 int target = 31;
794
795 /*
796 * The internal phy is visible on the external mii bus. Therefore we must
797 * move it away before we can send commands to an external phy.
798 * There are two addresses we must avoid:
799 * - the address on the external phy that is used for transmission.
800 * - the address that we want to access. User space can access phys
801 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independant from the
802 * phy that is used for transmission.
803 */
804
805 if (target == addr)
806 target--;
807 if (target == np->phy_addr_external)
808 target--;
809 writew(target, ioaddr + PhyCtrl);
810 readw(ioaddr + PhyCtrl);
811 udelay(1);
812}
813
814static int __devinit natsemi_probe1 (struct pci_dev *pdev,
815 const struct pci_device_id *ent)
816{
817 struct net_device *dev;
818 struct netdev_private *np;
819 int i, option, irq, chip_idx = ent->driver_data;
820 static int find_cnt = -1;
821 unsigned long iostart, iosize;
822 void __iomem *ioaddr;
823 const int pcibar = 1; /* PCI base address register */
824 int prev_eedata;
825 u32 tmp;
826
827/* when built into the kernel, we only print version if device is found */
828#ifndef MODULE
829 static int printed_version;
830 if (!printed_version++)
831 printk(version);
832#endif
833
834 i = pci_enable_device(pdev);
835 if (i) return i;
836
837 /* natsemi has a non-standard PM control register
838 * in PCI config space. Some boards apparently need
839 * to be brought to D0 in this manner.
840 */
841 pci_read_config_dword(pdev, PCIPM, &tmp);
842 if (tmp & PCI_PM_CTRL_STATE_MASK) {
843 /* D0 state, disable PME assertion */
844 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
845 pci_write_config_dword(pdev, PCIPM, newtmp);
846 }
847
848 find_cnt++;
849 iostart = pci_resource_start(pdev, pcibar);
850 iosize = pci_resource_len(pdev, pcibar);
851 irq = pdev->irq;
852
853 if (natsemi_pci_info[chip_idx].flags & PCI_USES_MASTER)
854 pci_set_master(pdev);
855
856 dev = alloc_etherdev(sizeof (struct netdev_private));
857 if (!dev)
858 return -ENOMEM;
859 SET_MODULE_OWNER(dev);
860 SET_NETDEV_DEV(dev, &pdev->dev);
861
862 i = pci_request_regions(pdev, DRV_NAME);
863 if (i)
864 goto err_pci_request_regions;
865
866 ioaddr = ioremap(iostart, iosize);
867 if (!ioaddr) {
868 i = -ENOMEM;
869 goto err_ioremap;
870 }
871
872 /* Work around the dropped serial bit. */
873 prev_eedata = eeprom_read(ioaddr, 6);
874 for (i = 0; i < 3; i++) {
875 int eedata = eeprom_read(ioaddr, i + 7);
876 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
877 dev->dev_addr[i*2+1] = eedata >> 7;
878 prev_eedata = eedata;
879 }
880
881 dev->base_addr = (unsigned long __force) ioaddr;
882 dev->irq = irq;
883
884 np = netdev_priv(dev);
885
886 np->pci_dev = pdev;
887 pci_set_drvdata(pdev, dev);
888 np->iosize = iosize;
889 spin_lock_init(&np->lock);
890 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
891 np->hands_off = 0;
b27a16b7 892 np->intr_status = 0;
1da177e4
LT		 893
894 /* Initial port:
895 * - If the nic was configured to use an external phy and if find_mii
896 * finds a phy: use external port, first phy that replies.
897 * - Otherwise: internal port.
898 * Note that the phy address for the internal phy doesn't matter:
899 * The address would be used to access a phy over the mii bus, but
900 * the internal phy is accessed through mapped registers.
901 */
902 if (readl(ioaddr + ChipConfig) & CfgExtPhy)
903 dev->if_port = PORT_MII;
904 else
905 dev->if_port = PORT_TP;
906 /* Reset the chip to erase previous misconfiguration. */
907 natsemi_reload_eeprom(dev);
908 natsemi_reset(dev);
909
910 if (dev->if_port != PORT_TP) {
911 np->phy_addr_external = find_mii(dev);
912 if (np->phy_addr_external == PHY_ADDR_NONE) {
913 dev->if_port = PORT_TP;
914 np->phy_addr_external = PHY_ADDR_INTERNAL;
915 }
916 } else {
917 np->phy_addr_external = PHY_ADDR_INTERNAL;
918 }
919
920 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
921 if (dev->mem_start)
922 option = dev->mem_start;
923
924 /* The lower four bits are the media type. */
925 if (option) {
926 if (option & 0x200)
927 np->full_duplex = 1;
928 if (option & 15)
929 printk(KERN_INFO
930 "natsemi %s: ignoring user supplied media type %d",
931 pci_name(np->pci_dev), option & 15);
932 }
933 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
934 np->full_duplex = 1;
935
936 /* The chip-specific entries in the device structure. */
937 dev->open = &netdev_open;
938 dev->hard_start_xmit = &start_tx;
939 dev->stop = &netdev_close;
940 dev->get_stats = &get_stats;
941 dev->set_multicast_list = &set_rx_mode;
942 dev->change_mtu = &natsemi_change_mtu;
943 dev->do_ioctl = &netdev_ioctl;
944 dev->tx_timeout = &tx_timeout;
945 dev->watchdog_timeo = TX_TIMEOUT;
b27a16b7
MB		 946 dev->poll = natsemi_poll;
947 dev->weight = 64;
948
1da177e4
LT		 949#ifdef CONFIG_NET_POLL_CONTROLLER
950 dev->poll_controller = &natsemi_poll_controller;
951#endif
952 SET_ETHTOOL_OPS(dev, &ethtool_ops);
953
954 if (mtu)
955 dev->mtu = mtu;
956
957 netif_carrier_off(dev);
958
959 /* get the initial settings from hardware */
960 tmp = mdio_read(dev, MII_BMCR);
961 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
962 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
963 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
964 np->advertising= mdio_read(dev, MII_ADVERTISE);
965
966 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL
967 && netif_msg_probe(np)) {
968 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
969 "10%s %s duplex.\n",
970 pci_name(np->pci_dev),
971 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
972 "enabled, advertise" : "disabled, force",
973 (np->advertising &
974 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
975 "0" : "",
976 (np->advertising &
977 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
978 "full" : "half");
979 }
980 if (netif_msg_probe(np))
981 printk(KERN_INFO
982 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
983 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
984 np->advertising);
985
986 /* save the silicon revision for later querying */
987 np->srr = readl(ioaddr + SiliconRev);
988 if (netif_msg_hw(np))
989 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
990 pci_name(np->pci_dev), np->srr);
991
992 i = register_netdev(dev);
993 if (i)
994 goto err_register_netdev;
995
996 if (netif_msg_drv(np)) {
997 printk(KERN_INFO "natsemi %s: %s at %#08lx (%s), ",
998 dev->name, natsemi_pci_info[chip_idx].name, iostart,
999 pci_name(np->pci_dev));
1000 for (i = 0; i < ETH_ALEN-1; i++)
1001 printk("%02x:", dev->dev_addr[i]);
1002 printk("%02x, IRQ %d", dev->dev_addr[i], irq);
1003 if (dev->if_port == PORT_TP)
1004 printk(", port TP.\n");
1005 else
1006 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
1007 }
1008 return 0;
1009
1010 err_register_netdev:
1011 iounmap(ioaddr);
1012
1013 err_ioremap:
1014 pci_release_regions(pdev);
1015 pci_set_drvdata(pdev, NULL);
1016
1017 err_pci_request_regions:
1018 free_netdev(dev);
1019 return i;
1020}
1021
1022
1023/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
1024 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
1025
1026/* Delay between EEPROM clock transitions.
1027 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
1028 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
1029 made udelay() unreliable.
1030 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
1031 depricated.
1032*/
1033#define eeprom_delay(ee_addr) readl(ee_addr)
1034
1035#define EE_Write0 (EE_ChipSelect)
1036#define EE_Write1 (EE_ChipSelect | EE_DataIn)
1037
1038/* The EEPROM commands include the alway-set leading bit. */
1039enum EEPROM_Cmds {
1040 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1041};
1042
1043static int eeprom_read(void __iomem *addr, int location)
1044{
1045 int i;
1046 int retval = 0;
1047 void __iomem *ee_addr = addr + EECtrl;
1048 int read_cmd = location | EE_ReadCmd;
1049
1050 writel(EE_Write0, ee_addr);
1051
1052 /* Shift the read command bits out. */
1053 for (i = 10; i >= 0; i--) {
1054 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1055 writel(dataval, ee_addr);
1056 eeprom_delay(ee_addr);
1057 writel(dataval | EE_ShiftClk, ee_addr);
1058 eeprom_delay(ee_addr);
1059 }
1060 writel(EE_ChipSelect, ee_addr);
1061 eeprom_delay(ee_addr);
1062
1063 for (i = 0; i < 16; i++) {
1064 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1065 eeprom_delay(ee_addr);
1066 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1067 writel(EE_ChipSelect, ee_addr);
1068 eeprom_delay(ee_addr);
1069 }
1070
1071 /* Terminate the EEPROM access. */
1072 writel(EE_Write0, ee_addr);
1073 writel(0, ee_addr);
1074 return retval;
1075}
1076
1077/* MII transceiver control section.
1078 * The 83815 series has an internal transceiver, and we present the
1079 * internal management registers as if they were MII connected.
1080 * External Phy registers are referenced through the MII interface.
1081 */
1082
1083/* clock transitions >= 20ns (25MHz)
1084 * One readl should be good to PCI @ 100MHz
1085 */
1086#define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1087
1088static int mii_getbit (struct net_device *dev)
1089{
1090 int data;
1091 void __iomem *ioaddr = ns_ioaddr(dev);
1092
1093 writel(MII_ShiftClk, ioaddr + EECtrl);
1094 data = readl(ioaddr + EECtrl);
1095 writel(0, ioaddr + EECtrl);
1096 mii_delay(ioaddr);
1097 return (data & MII_Data)? 1 : 0;
1098}
1099
1100static void mii_send_bits (struct net_device *dev, u32 data, int len)
1101{
1102 u32 i;
1103 void __iomem *ioaddr = ns_ioaddr(dev);
1104
1105 for (i = (1 << (len-1)); i; i >>= 1)
1106 {
1107 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1108 writel(mdio_val, ioaddr + EECtrl);
1109 mii_delay(ioaddr);
1110 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1111 mii_delay(ioaddr);
1112 }
1113 writel(0, ioaddr + EECtrl);
1114 mii_delay(ioaddr);
1115}
1116
1117static int miiport_read(struct net_device *dev, int phy_id, int reg)
1118{
1119 u32 cmd;
1120 int i;
1121 u32 retval = 0;
1122
1123 /* Ensure sync */
1124 mii_send_bits (dev, 0xffffffff, 32);
1125 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1126 /* ST,OP = 0110'b for read operation */
1127 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1128 mii_send_bits (dev, cmd, 14);
1129 /* Turnaround */
1130 if (mii_getbit (dev))
1131 return 0;
1132 /* Read data */
1133 for (i = 0; i < 16; i++) {
1134 retval <<= 1;
1135 retval |= mii_getbit (dev);
1136 }
1137 /* End cycle */
1138 mii_getbit (dev);
1139 return retval;
1140}
1141
1142static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1143{
1144 u32 cmd;
1145
1146 /* Ensure sync */
1147 mii_send_bits (dev, 0xffffffff, 32);
1148 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1149 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1150 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1151 mii_send_bits (dev, cmd, 32);
1152 /* End cycle */
1153 mii_getbit (dev);
1154}
1155
1156static int mdio_read(struct net_device *dev, int reg)
1157{
1158 struct netdev_private *np = netdev_priv(dev);
1159 void __iomem *ioaddr = ns_ioaddr(dev);
1160
1161 /* The 83815 series has two ports:
1162 * - an internal transceiver
1163 * - an external mii bus
1164 */
1165 if (dev->if_port == PORT_TP)
1166 return readw(ioaddr+BasicControl+(reg<<2));
1167 else
1168 return miiport_read(dev, np->phy_addr_external, reg);
1169}
1170
1171static void mdio_write(struct net_device *dev, int reg, u16 data)
1172{
1173 struct netdev_private *np = netdev_priv(dev);
1174 void __iomem *ioaddr = ns_ioaddr(dev);
1175
1176 /* The 83815 series has an internal transceiver; handle separately */
1177 if (dev->if_port == PORT_TP)
1178 writew(data, ioaddr+BasicControl+(reg<<2));
1179 else
1180 miiport_write(dev, np->phy_addr_external, reg, data);
1181}
1182
1183static void init_phy_fixup(struct net_device *dev)
1184{
1185 struct netdev_private *np = netdev_priv(dev);
1186 void __iomem *ioaddr = ns_ioaddr(dev);
1187 int i;
1188 u32 cfg;
1189 u16 tmp;
1190
1191 /* restore stuff lost when power was out */
1192 tmp = mdio_read(dev, MII_BMCR);
1193 if (np->autoneg == AUTONEG_ENABLE) {
1194 /* renegotiate if something changed */
1195 if ((tmp & BMCR_ANENABLE) == 0
1196 || np->advertising != mdio_read(dev, MII_ADVERTISE))
1197 {
1198 /* turn on autonegotiation and force negotiation */
1199 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1200 mdio_write(dev, MII_ADVERTISE, np->advertising);
1201 }
1202 } else {
1203 /* turn off auto negotiation, set speed and duplexity */
1204 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1205 if (np->speed == SPEED_100)
1206 tmp |= BMCR_SPEED100;
1207 if (np->duplex == DUPLEX_FULL)
1208 tmp |= BMCR_FULLDPLX;
1209 /*
1210 * Note: there is no good way to inform the link partner
1211 * that our capabilities changed. The user has to unplug
1212 * and replug the network cable after some changes, e.g.
1213 * after switching from 10HD, autoneg off to 100 HD,
1214 * autoneg off.
1215 */
1216 }
1217 mdio_write(dev, MII_BMCR, tmp);
1218 readl(ioaddr + ChipConfig);
1219 udelay(1);
1220
1221 /* find out what phy this is */
1222 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1223 + mdio_read(dev, MII_PHYSID2);
1224
1225 /* handle external phys here */
1226 switch (np->mii) {
1227 case PHYID_AM79C874:
1228 /* phy specific configuration for fibre/tp operation */
1229 tmp = mdio_read(dev, MII_MCTRL);
1230 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1231 if (dev->if_port == PORT_FIBRE)
1232 tmp |= MII_FX_SEL;
1233 else
1234 tmp |= MII_EN_SCRM;
1235 mdio_write(dev, MII_MCTRL, tmp);
1236 break;
1237 default:
1238 break;
1239 }
1240 cfg = readl(ioaddr + ChipConfig);
1241 if (cfg & CfgExtPhy)
1242 return;
1243
1244 /* On page 78 of the spec, they recommend some settings for "optimum
1245 performance" to be done in sequence. These settings optimize some
1246 of the 100Mbit autodetection circuitry. They say we only want to
1247 do this for rev C of the chip, but engineers at NSC (Bradley
1248 Kennedy) recommends always setting them. If you don't, you get
1249 errors on some autonegotiations that make the device unusable.
1250
1251 It seems that the DSP needs a few usec to reinitialize after
1252 the start of the phy. Just retry writing these values until they
1253 stick.
1254 */
1255 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1256
1257 int dspcfg;
1258 writew(1, ioaddr + PGSEL);
1259 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1260 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1261 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1262 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1263 writew(np->dspcfg, ioaddr + DSPCFG);
1264 writew(SDCFG_VAL, ioaddr + SDCFG);
1265 writew(0, ioaddr + PGSEL);
1266 readl(ioaddr + ChipConfig);
1267 udelay(10);
1268
1269 writew(1, ioaddr + PGSEL);
1270 dspcfg = readw(ioaddr + DSPCFG);
1271 writew(0, ioaddr + PGSEL);
1272 if (np->dspcfg == dspcfg)
1273 break;
1274 }
1275
1276 if (netif_msg_link(np)) {
1277 if (i==NATSEMI_HW_TIMEOUT) {
1278 printk(KERN_INFO
1279 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1280 dev->name, i*10);
1281 } else {
1282 printk(KERN_INFO
1283 "%s: DSPCFG accepted after %d usec.\n",
1284 dev->name, i*10);
1285 }
1286 }
1287 /*
1288 * Enable PHY Specific event based interrupts. Link state change
1289 * and Auto-Negotiation Completion are among the affected.
1290 * Read the intr status to clear it (needed for wake events).
1291 */
1292 readw(ioaddr + MIntrStatus);
1293 writew(MICRIntEn, ioaddr + MIntrCtrl);
1294}
1295
1296static int switch_port_external(struct net_device *dev)
1297{
1298 struct netdev_private *np = netdev_priv(dev);
1299 void __iomem *ioaddr = ns_ioaddr(dev);
1300 u32 cfg;
1301
1302 cfg = readl(ioaddr + ChipConfig);
1303 if (cfg & CfgExtPhy)
1304 return 0;
1305
1306 if (netif_msg_link(np)) {
1307 printk(KERN_INFO "%s: switching to external transceiver.\n",
1308 dev->name);
1309 }
1310
1311 /* 1) switch back to external phy */
1312 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1313 readl(ioaddr + ChipConfig);
1314 udelay(1);
1315
1316 /* 2) reset the external phy: */
1317 /* resetting the external PHY has been known to cause a hub supplying
1318 * power over Ethernet to kill the power. We don't want to kill
1319 * power to this computer, so we avoid resetting the phy.
1320 */
1321
1322 /* 3) reinit the phy fixup, it got lost during power down. */
1323 move_int_phy(dev, np->phy_addr_external);
1324 init_phy_fixup(dev);
1325
1326 return 1;
1327}
1328
1329static int switch_port_internal(struct net_device *dev)
1330{
1331 struct netdev_private *np = netdev_priv(dev);
1332 void __iomem *ioaddr = ns_ioaddr(dev);
1333 int i;
1334 u32 cfg;
1335 u16 bmcr;
1336
1337 cfg = readl(ioaddr + ChipConfig);
1338 if (!(cfg &CfgExtPhy))
1339 return 0;
1340
1341 if (netif_msg_link(np)) {
1342 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1343 dev->name);
1344 }
1345 /* 1) switch back to internal phy: */
1346 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1347 writel(cfg, ioaddr + ChipConfig);
1348 readl(ioaddr + ChipConfig);
1349 udelay(1);
1350
1351 /* 2) reset the internal phy: */
1352 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1353 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1354 readl(ioaddr + ChipConfig);
1355 udelay(10);
1356 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1357 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1358 if (!(bmcr & BMCR_RESET))
1359 break;
1360 udelay(10);
1361 }
1362 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1363 printk(KERN_INFO
1364 "%s: phy reset did not complete in %d usec.\n",
1365 dev->name, i*10);
1366 }
1367 /* 3) reinit the phy fixup, it got lost during power down. */
1368 init_phy_fixup(dev);
1369
1370 return 1;
1371}
1372
1373/* Scan for a PHY on the external mii bus.
1374 * There are two tricky points:
1375 * - Do not scan while the internal phy is enabled. The internal phy will
1376 * crash: e.g. reads from the DSPCFG register will return odd values and
1377 * the nasty random phy reset code will reset the nic every few seconds.
1378 * - The internal phy must be moved around, an external phy could
1379 * have the same address as the internal phy.
1380 */
1381static int find_mii(struct net_device *dev)
1382{
1383 struct netdev_private *np = netdev_priv(dev);
1384 int tmp;
1385 int i;
1386 int did_switch;
1387
1388 /* Switch to external phy */
1389 did_switch = switch_port_external(dev);
1390
1391 /* Scan the possible phy addresses:
1392 *
1393 * PHY address 0 means that the phy is in isolate mode. Not yet
1394 * supported due to lack of test hardware. User space should
1395 * handle it through ethtool.
1396 */
1397 for (i = 1; i <= 31; i++) {
1398 move_int_phy(dev, i);
1399 tmp = miiport_read(dev, i, MII_BMSR);
1400 if (tmp != 0xffff && tmp != 0x0000) {
1401 /* found something! */
1402 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1403 + mdio_read(dev, MII_PHYSID2);
1404 if (netif_msg_probe(np)) {
1405 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1406 pci_name(np->pci_dev), np->mii, i);
1407 }
1408 break;
1409 }
1410 }
1411 /* And switch back to internal phy: */
1412 if (did_switch)
1413 switch_port_internal(dev);
1414 return i;
1415}
1416
1417/* CFG bits [13:16] [18:23] */
1418#define CFG_RESET_SAVE 0xfde000
1419/* WCSR bits [0:4] [9:10] */
1420#define WCSR_RESET_SAVE 0x61f
1421/* RFCR bits [20] [22] [27:31] */
1422#define RFCR_RESET_SAVE 0xf8500000;
1423
1424static void natsemi_reset(struct net_device *dev)
1425{
1426 int i;
1427 u32 cfg;
1428 u32 wcsr;
1429 u32 rfcr;
1430 u16 pmatch[3];
1431 u16 sopass[3];
1432 struct netdev_private *np = netdev_priv(dev);
1433 void __iomem *ioaddr = ns_ioaddr(dev);
1434
1435 /*
1436 * Resetting the chip causes some registers to be lost.
1437 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1438 * we save the state that would have been loaded from EEPROM
1439 * on a normal power-up (see the spec EEPROM map). This assumes
1440 * whoever calls this will follow up with init_registers() eventually.
1441 */
1442
1443 /* CFG */
1444 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1445 /* WCSR */
1446 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1447 /* RFCR */
1448 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1449 /* PMATCH */
1450 for (i = 0; i < 3; i++) {
1451 writel(i*2, ioaddr + RxFilterAddr);
1452 pmatch[i] = readw(ioaddr + RxFilterData);
1453 }
1454 /* SOPAS */
1455 for (i = 0; i < 3; i++) {
1456 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1457 sopass[i] = readw(ioaddr + RxFilterData);
1458 }
1459
1460 /* now whack the chip */
1461 writel(ChipReset, ioaddr + ChipCmd);
1462 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1463 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1464 break;
1465 udelay(5);
1466 }
1467 if (i==NATSEMI_HW_TIMEOUT) {
1468 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1469 dev->name, i*5);
1470 } else if (netif_msg_hw(np)) {
1471 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1472 dev->name, i*5);
1473 }
1474
1475 /* restore CFG */
1476 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1477 /* turn on external phy if it was selected */
1478 if (dev->if_port == PORT_TP)
1479 cfg &= ~(CfgExtPhy | CfgPhyDis);
1480 else
1481 cfg |= (CfgExtPhy | CfgPhyDis);
1482 writel(cfg, ioaddr + ChipConfig);
1483 /* restore WCSR */
1484 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1485 writel(wcsr, ioaddr + WOLCmd);
1486 /* read RFCR */
1487 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1488 /* restore PMATCH */
1489 for (i = 0; i < 3; i++) {
1490 writel(i*2, ioaddr + RxFilterAddr);
1491 writew(pmatch[i], ioaddr + RxFilterData);
1492 }
1493 for (i = 0; i < 3; i++) {
1494 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1495 writew(sopass[i], ioaddr + RxFilterData);
1496 }
1497 /* restore RFCR */
1498 writel(rfcr, ioaddr + RxFilterAddr);
1499}
1500
e72fd96e
MB		 1501static void reset_rx(struct net_device *dev)
1502{
1503 int i;
1504 struct netdev_private *np = netdev_priv(dev);
1505 void __iomem *ioaddr = ns_ioaddr(dev);
1506
1507 np->intr_status &= ~RxResetDone;
1508
1509 writel(RxReset, ioaddr + ChipCmd);
1510
1511 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1512 np->intr_status |= readl(ioaddr + IntrStatus);
1513 if (np->intr_status & RxResetDone)
1514 break;
1515 udelay(15);
1516 }
1517 if (i==NATSEMI_HW_TIMEOUT) {
1518 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n",
1519 dev->name, i*15);
1520 } else if (netif_msg_hw(np)) {
1521 printk(KERN_WARNING "%s: RX reset took %d usec.\n",
1522 dev->name, i*15);
1523 }
1524}
1525
1da177e4
LT		 1526static void natsemi_reload_eeprom(struct net_device *dev)
1527{
1528 struct netdev_private *np = netdev_priv(dev);
1529 void __iomem *ioaddr = ns_ioaddr(dev);
1530 int i;
1531
1532 writel(EepromReload, ioaddr + PCIBusCfg);
1533 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1534 udelay(50);
1535 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1536 break;
1537 }
1538 if (i==NATSEMI_HW_TIMEOUT) {
1539 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1540 pci_name(np->pci_dev), i*50);
1541 } else if (netif_msg_hw(np)) {
1542 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1543 pci_name(np->pci_dev), i*50);
1544 }
1545}
1546
1547static void natsemi_stop_rxtx(struct net_device *dev)
1548{
1549 void __iomem * ioaddr = ns_ioaddr(dev);
1550 struct netdev_private *np = netdev_priv(dev);
1551 int i;
1552
1553 writel(RxOff | TxOff, ioaddr + ChipCmd);
1554 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1555 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1556 break;
1557 udelay(5);
1558 }
1559 if (i==NATSEMI_HW_TIMEOUT) {
1560 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1561 dev->name, i*5);
1562 } else if (netif_msg_hw(np)) {
1563 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1564 dev->name, i*5);
1565 }
1566}
1567
1568static int netdev_open(struct net_device *dev)
1569{
1570 struct netdev_private *np = netdev_priv(dev);
1571 void __iomem * ioaddr = ns_ioaddr(dev);
1572 int i;
1573
1574 /* Reset the chip, just in case. */
1575 natsemi_reset(dev);
1576
1577 i = request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev);
1578 if (i) return i;
1579
1580 if (netif_msg_ifup(np))
1581 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1582 dev->name, dev->irq);
1583 i = alloc_ring(dev);
1584 if (i < 0) {
1585 free_irq(dev->irq, dev);
1586 return i;
1587 }
1588 init_ring(dev);
1589 spin_lock_irq(&np->lock);
1590 init_registers(dev);
1591 /* now set the MAC address according to dev->dev_addr */
1592 for (i = 0; i < 3; i++) {
1593 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1594
1595 writel(i*2, ioaddr + RxFilterAddr);
1596 writew(mac, ioaddr + RxFilterData);
1597 }
1598 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1599 spin_unlock_irq(&np->lock);
1600
1601 netif_start_queue(dev);
1602
1603 if (netif_msg_ifup(np))
1604 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1605 dev->name, (int)readl(ioaddr + ChipCmd));
1606
1607 /* Set the timer to check for link beat. */
1608 init_timer(&np->timer);
1609 np->timer.expires = jiffies + NATSEMI_TIMER_FREQ;
1610 np->timer.data = (unsigned long)dev;
1611 np->timer.function = &netdev_timer; /* timer handler */
1612 add_timer(&np->timer);
1613
1614 return 0;
1615}
1616
1617static void do_cable_magic(struct net_device *dev)
1618{
1619 struct netdev_private *np = netdev_priv(dev);
1620 void __iomem *ioaddr = ns_ioaddr(dev);
1621
1622 if (dev->if_port != PORT_TP)
1623 return;
1624
1625 if (np->srr >= SRR_DP83816_A5)
1626 return;
1627
1628 /*
1629 * 100 MBit links with short cables can trip an issue with the chip.
1630 * The problem manifests as lots of CRC errors and/or flickering
1631 * activity LED while idle. This process is based on instructions
1632 * from engineers at National.
1633 */
1634 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1635 u16 data;
1636
1637 writew(1, ioaddr + PGSEL);
1638 /*
1639 * coefficient visibility should already be enabled via
1640 * DSPCFG | 0x1000
1641 */
1642 data = readw(ioaddr + TSTDAT) & 0xff;
1643 /*
1644 * the value must be negative, and within certain values
1645 * (these values all come from National)
1646 */
1647 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
1648 struct netdev_private *np = netdev_priv(dev);
1649
1650 /* the bug has been triggered - fix the coefficient */
1651 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1652 /* lock the value */
1653 data = readw(ioaddr + DSPCFG);
1654 np->dspcfg = data | DSPCFG_LOCK;
1655 writew(np->dspcfg, ioaddr + DSPCFG);
1656 }
1657 writew(0, ioaddr + PGSEL);
1658 }
1659}
1660
1661static void undo_cable_magic(struct net_device *dev)
1662{
1663 u16 data;
1664 struct netdev_private *np = netdev_priv(dev);
1665 void __iomem * ioaddr = ns_ioaddr(dev);
1666
1667 if (dev->if_port != PORT_TP)
1668 return;
1669
1670 if (np->srr >= SRR_DP83816_A5)
1671 return;
1672
1673 writew(1, ioaddr + PGSEL);
1674 /* make sure the lock bit is clear */
1675 data = readw(ioaddr + DSPCFG);
1676 np->dspcfg = data & ~DSPCFG_LOCK;
1677 writew(np->dspcfg, ioaddr + DSPCFG);
1678 writew(0, ioaddr + PGSEL);
1679}
1680
1681static void check_link(struct net_device *dev)
1682{
1683 struct netdev_private *np = netdev_priv(dev);
1684 void __iomem * ioaddr = ns_ioaddr(dev);
1685 int duplex;
1686 u16 bmsr;
1687
1688 /* The link status field is latched: it remains low after a temporary
1689 * link failure until it's read. We need the current link status,
1690 * thus read twice.
1691 */
1692 mdio_read(dev, MII_BMSR);
1693 bmsr = mdio_read(dev, MII_BMSR);
1694
1695 if (!(bmsr & BMSR_LSTATUS)) {
1696 if (netif_carrier_ok(dev)) {
1697 if (netif_msg_link(np))
1698 printk(KERN_NOTICE "%s: link down.\n",
1699 dev->name);
1700 netif_carrier_off(dev);
1701 undo_cable_magic(dev);
1702 }
1703 return;
1704 }
1705 if (!netif_carrier_ok(dev)) {
1706 if (netif_msg_link(np))
1707 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1708 netif_carrier_on(dev);
1709 do_cable_magic(dev);
1710 }
1711
1712 duplex = np->full_duplex;
1713 if (!duplex) {
1714 if (bmsr & BMSR_ANEGCOMPLETE) {
1715 int tmp = mii_nway_result(
1716 np->advertising & mdio_read(dev, MII_LPA));
1717 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1718 duplex = 1;
1719 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1720 duplex = 1;
1721 }
1722
1723 /* if duplex is set then bit 28 must be set, too */
1724 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1725 if (netif_msg_link(np))
1726 printk(KERN_INFO
1727 "%s: Setting %s-duplex based on negotiated "
1728 "link capability.\n", dev->name,
1729 duplex ? "full" : "half");
1730 if (duplex) {
1731 np->rx_config |= RxAcceptTx;
1732 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1733 } else {
1734 np->rx_config &= ~RxAcceptTx;
1735 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1736 }
1737 writel(np->tx_config, ioaddr + TxConfig);
1738 writel(np->rx_config, ioaddr + RxConfig);
1739 }
1740}
1741
1742static void init_registers(struct net_device *dev)
1743{
1744 struct netdev_private *np = netdev_priv(dev);
1745 void __iomem * ioaddr = ns_ioaddr(dev);
1746
1747 init_phy_fixup(dev);
1748
1749 /* clear any interrupts that are pending, such as wake events */
1750 readl(ioaddr + IntrStatus);
1751
1752 writel(np->ring_dma, ioaddr + RxRingPtr);
1753 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1754 ioaddr + TxRingPtr);
1755
1756 /* Initialize other registers.
1757 * Configure the PCI bus bursts and FIFO thresholds.
1758 * Configure for standard, in-spec Ethernet.
1759 * Start with half-duplex. check_link will update
1760 * to the correct settings.
1761 */
1762
1763 /* DRTH: 2: start tx if 64 bytes are in the fifo
1764 * FLTH: 0x10: refill with next packet if 512 bytes are free
1765 * MXDMA: 0: up to 256 byte bursts.
1766 * MXDMA must be <= FLTH
1767 * ECRETRY=1
1768 * ATP=1
1769 */
1770 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1771 TX_FLTH_VAL | TX_DRTH_VAL_START;
1772 writel(np->tx_config, ioaddr + TxConfig);
1773
1774 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1775 * MXDMA 0: up to 256 byte bursts
1776 */
1777 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1778 /* if receive ring now has bigger buffers than normal, enable jumbo */
1779 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1780 np->rx_config |= RxAcceptLong;
1781
1782 writel(np->rx_config, ioaddr + RxConfig);
1783
1784 /* Disable PME:
1785 * The PME bit is initialized from the EEPROM contents.
1786 * PCI cards probably have PME disabled, but motherboard
1787 * implementations may have PME set to enable WakeOnLan.
1788 * With PME set the chip will scan incoming packets but
1789 * nothing will be written to memory. */
1790 np->SavedClkRun = readl(ioaddr + ClkRun);
1791 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1792 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1793 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1794 dev->name, readl(ioaddr + WOLCmd));
1795 }
1796
1797 check_link(dev);
1798 __set_rx_mode(dev);
1799
1800 /* Enable interrupts by setting the interrupt mask. */
1801 writel(DEFAULT_INTR, ioaddr + IntrMask);
1802 writel(1, ioaddr + IntrEnable);
1803
1804 writel(RxOn | TxOn, ioaddr + ChipCmd);
1805 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1806}
1807
1808/*
1809 * netdev_timer:
1810 * Purpose:
1811 * 1) check for link changes. Usually they are handled by the MII interrupt
1812 * but it doesn't hurt to check twice.
1813 * 2) check for sudden death of the NIC:
1814 * It seems that a reference set for this chip went out with incorrect info,
1815 * and there exist boards that aren't quite right. An unexpected voltage
1816 * drop can cause the PHY to get itself in a weird state (basically reset).
1817 * NOTE: this only seems to affect revC chips.
1818 * 3) check of death of the RX path due to OOM
1819 */
1820static void netdev_timer(unsigned long data)
1821{
1822 struct net_device *dev = (struct net_device *)data;
1823 struct netdev_private *np = netdev_priv(dev);
1824 void __iomem * ioaddr = ns_ioaddr(dev);
1825 int next_tick = 5*HZ;
1826
1827 if (netif_msg_timer(np)) {
1828 /* DO NOT read the IntrStatus register,
1829 * a read clears any pending interrupts.
1830 */
1831 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1832 dev->name);
1833 }
1834
1835 if (dev->if_port == PORT_TP) {
1836 u16 dspcfg;
1837
1838 spin_lock_irq(&np->lock);
1839 /* check for a nasty random phy-reset - use dspcfg as a flag */
1840 writew(1, ioaddr+PGSEL);
1841 dspcfg = readw(ioaddr+DSPCFG);
1842 writew(0, ioaddr+PGSEL);
1843 if (dspcfg != np->dspcfg) {
1844 if (!netif_queue_stopped(dev)) {
1845 spin_unlock_irq(&np->lock);
1846 if (netif_msg_hw(np))
1847 printk(KERN_NOTICE "%s: possible phy reset: "
1848 "re-initializing\n", dev->name);
1849 disable_irq(dev->irq);
1850 spin_lock_irq(&np->lock);
1851 natsemi_stop_rxtx(dev);
1852 dump_ring(dev);
1853 reinit_ring(dev);
1854 init_registers(dev);
1855 spin_unlock_irq(&np->lock);
1856 enable_irq(dev->irq);
1857 } else {
1858 /* hurry back */
1859 next_tick = HZ;
1860 spin_unlock_irq(&np->lock);
1861 }
1862 } else {
1863 /* init_registers() calls check_link() for the above case */
1864 check_link(dev);
1865 spin_unlock_irq(&np->lock);
1866 }
1867 } else {
1868 spin_lock_irq(&np->lock);
1869 check_link(dev);
1870 spin_unlock_irq(&np->lock);
1871 }
1872 if (np->oom) {
1873 disable_irq(dev->irq);
1874 np->oom = 0;
1875 refill_rx(dev);
1876 enable_irq(dev->irq);
1877 if (!np->oom) {
1878 writel(RxOn, ioaddr + ChipCmd);
1879 } else {
1880 next_tick = 1;
1881 }
1882 }
1883 mod_timer(&np->timer, jiffies + next_tick);
1884}
1885
1886static void dump_ring(struct net_device *dev)
1887{
1888 struct netdev_private *np = netdev_priv(dev);
1889
1890 if (netif_msg_pktdata(np)) {
1891 int i;
1892 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1893 for (i = 0; i < TX_RING_SIZE; i++) {
1894 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1895 i, np->tx_ring[i].next_desc,
1896 np->tx_ring[i].cmd_status,
1897 np->tx_ring[i].addr);
1898 }
1899 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1900 for (i = 0; i < RX_RING_SIZE; i++) {
1901 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1902 i, np->rx_ring[i].next_desc,
1903 np->rx_ring[i].cmd_status,
1904 np->rx_ring[i].addr);
1905 }
1906 }
1907}
1908
1909static void tx_timeout(struct net_device *dev)
1910{
1911 struct netdev_private *np = netdev_priv(dev);
1912 void __iomem * ioaddr = ns_ioaddr(dev);
1913
1914 disable_irq(dev->irq);
1915 spin_lock_irq(&np->lock);
1916 if (!np->hands_off) {
1917 if (netif_msg_tx_err(np))
1918 printk(KERN_WARNING
1919 "%s: Transmit timed out, status %#08x,"
1920 " resetting...\n",
1921 dev->name, readl(ioaddr + IntrStatus));
1922 dump_ring(dev);
1923
1924 natsemi_reset(dev);
1925 reinit_ring(dev);
1926 init_registers(dev);
1927 } else {
1928 printk(KERN_WARNING
1929 "%s: tx_timeout while in hands_off state?\n",
1930 dev->name);
1931 }
1932 spin_unlock_irq(&np->lock);
1933 enable_irq(dev->irq);
1934
1935 dev->trans_start = jiffies;
1936 np->stats.tx_errors++;
1937 netif_wake_queue(dev);
1938}
1939
1940static int alloc_ring(struct net_device *dev)
1941{
1942 struct netdev_private *np = netdev_priv(dev);
1943 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1944 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1945 &np->ring_dma);
1946 if (!np->rx_ring)
1947 return -ENOMEM;
1948 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1949 return 0;
1950}
1951
1952static void refill_rx(struct net_device *dev)
1953{
1954 struct netdev_private *np = netdev_priv(dev);
1955
1956 /* Refill the Rx ring buffers. */
1957 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1958 struct sk_buff *skb;
1959 int entry = np->dirty_rx % RX_RING_SIZE;
1960 if (np->rx_skbuff[entry] == NULL) {
1961 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1962 skb = dev_alloc_skb(buflen);
1963 np->rx_skbuff[entry] = skb;
1964 if (skb == NULL)
1965 break; /* Better luck next round. */
1966 skb->dev = dev; /* Mark as being used by this device. */
1967 np->rx_dma[entry] = pci_map_single(np->pci_dev,
689be439 1968 skb->data, buflen, PCI_DMA_FROMDEVICE);
1da177e4
LT		 1969 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1970 }
1971 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1972 }
1973 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1974 if (netif_msg_rx_err(np))
1975 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1976 np->oom = 1;
1977 }
1978}
1979
1980static void set_bufsize(struct net_device *dev)
1981{
1982 struct netdev_private *np = netdev_priv(dev);
1983 if (dev->mtu <= ETH_DATA_LEN)
1984 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1985 else
1986 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1987}
1988
1989/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1990static void init_ring(struct net_device *dev)
1991{
1992 struct netdev_private *np = netdev_priv(dev);
1993 int i;
1994
1995 /* 1) TX ring */
1996 np->dirty_tx = np->cur_tx = 0;
1997 for (i = 0; i < TX_RING_SIZE; i++) {
1998 np->tx_skbuff[i] = NULL;
1999 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
2000 +sizeof(struct netdev_desc)
2001 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
2002 np->tx_ring[i].cmd_status = 0;
2003 }
2004
2005 /* 2) RX ring */
2006 np->dirty_rx = 0;
2007 np->cur_rx = RX_RING_SIZE;
2008 np->oom = 0;
2009 set_bufsize(dev);
2010
2011 np->rx_head_desc = &np->rx_ring[0];
2012
2013 /* Please be carefull before changing this loop - at least gcc-2.95.1
2014 * miscompiles it otherwise.
2015 */
2016 /* Initialize all Rx descriptors. */
2017 for (i = 0; i < RX_RING_SIZE; i++) {
2018 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
2019 +sizeof(struct netdev_desc)
2020 *((i+1)%RX_RING_SIZE));
2021 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2022 np->rx_skbuff[i] = NULL;
2023 }
2024 refill_rx(dev);
2025 dump_ring(dev);
2026}
2027
2028static void drain_tx(struct net_device *dev)
2029{
2030 struct netdev_private *np = netdev_priv(dev);
2031 int i;
2032
2033 for (i = 0; i < TX_RING_SIZE; i++) {
2034 if (np->tx_skbuff[i]) {
2035 pci_unmap_single(np->pci_dev,
2036 np->tx_dma[i], np->tx_skbuff[i]->len,
2037 PCI_DMA_TODEVICE);
2038 dev_kfree_skb(np->tx_skbuff[i]);
2039 np->stats.tx_dropped++;
2040 }
2041 np->tx_skbuff[i] = NULL;
2042 }
2043}
2044
2045static void drain_rx(struct net_device *dev)
2046{
2047 struct netdev_private *np = netdev_priv(dev);
2048 unsigned int buflen = np->rx_buf_sz;
2049 int i;
2050
2051 /* Free all the skbuffs in the Rx queue. */
2052 for (i = 0; i < RX_RING_SIZE; i++) {
2053 np->rx_ring[i].cmd_status = 0;
2054 np->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
2055 if (np->rx_skbuff[i]) {
2056 pci_unmap_single(np->pci_dev,
2057 np->rx_dma[i], buflen,
2058 PCI_DMA_FROMDEVICE);
2059 dev_kfree_skb(np->rx_skbuff[i]);
2060 }
2061 np->rx_skbuff[i] = NULL;
2062 }
2063}
2064
2065static void drain_ring(struct net_device *dev)
2066{
2067 drain_rx(dev);
2068 drain_tx(dev);
2069}
2070
2071static void free_ring(struct net_device *dev)
2072{
2073 struct netdev_private *np = netdev_priv(dev);
2074 pci_free_consistent(np->pci_dev,
2075 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2076 np->rx_ring, np->ring_dma);
2077}
2078
2079static void reinit_rx(struct net_device *dev)
2080{
2081 struct netdev_private *np = netdev_priv(dev);
2082 int i;
2083
2084 /* RX Ring */
2085 np->dirty_rx = 0;
2086 np->cur_rx = RX_RING_SIZE;
2087 np->rx_head_desc = &np->rx_ring[0];
2088 /* Initialize all Rx descriptors. */
2089 for (i = 0; i < RX_RING_SIZE; i++)
2090 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2091
2092 refill_rx(dev);
2093}
2094
2095static void reinit_ring(struct net_device *dev)
2096{
2097 struct netdev_private *np = netdev_priv(dev);
2098 int i;
2099
2100 /* drain TX ring */
2101 drain_tx(dev);
2102 np->dirty_tx = np->cur_tx = 0;
2103 for (i=0;i<TX_RING_SIZE;i++)
2104 np->tx_ring[i].cmd_status = 0;
2105
2106 reinit_rx(dev);
2107}
2108
2109static int start_tx(struct sk_buff *skb, struct net_device *dev)
2110{
2111 struct netdev_private *np = netdev_priv(dev);
2112 void __iomem * ioaddr = ns_ioaddr(dev);
2113 unsigned entry;
2114
2115 /* Note: Ordering is important here, set the field with the
2116 "ownership" bit last, and only then increment cur_tx. */
2117
2118 /* Calculate the next Tx descriptor entry. */
2119 entry = np->cur_tx % TX_RING_SIZE;
2120
2121 np->tx_skbuff[entry] = skb;
2122 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2123 skb->data,skb->len, PCI_DMA_TODEVICE);
2124
2125 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2126
2127 spin_lock_irq(&np->lock);
2128
2129 if (!np->hands_off) {
2130 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2131 /* StrongARM: Explicitly cache flush np->tx_ring and
2132 * skb->data,skb->len. */
2133 wmb();
2134 np->cur_tx++;
2135 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2136 netdev_tx_done(dev);
2137 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2138 netif_stop_queue(dev);
2139 }
2140 /* Wake the potentially-idle transmit channel. */
2141 writel(TxOn, ioaddr + ChipCmd);
2142 } else {
2143 dev_kfree_skb_irq(skb);
2144 np->stats.tx_dropped++;
2145 }
2146 spin_unlock_irq(&np->lock);
2147
2148 dev->trans_start = jiffies;
2149
2150 if (netif_msg_tx_queued(np)) {
2151 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2152 dev->name, np->cur_tx, entry);
2153 }
2154 return 0;
2155}
2156
2157static void netdev_tx_done(struct net_device *dev)
2158{
2159 struct netdev_private *np = netdev_priv(dev);
2160
2161 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2162 int entry = np->dirty_tx % TX_RING_SIZE;
2163 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2164 break;
2165 if (netif_msg_tx_done(np))
2166 printk(KERN_DEBUG
2167 "%s: tx frame #%d finished, status %#08x.\n",
2168 dev->name, np->dirty_tx,
2169 le32_to_cpu(np->tx_ring[entry].cmd_status));
2170 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2171 np->stats.tx_packets++;
2172 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
2173 } else { /* Various Tx errors */
2174 int tx_status =
2175 le32_to_cpu(np->tx_ring[entry].cmd_status);
2176 if (tx_status & (DescTxAbort|DescTxExcColl))
2177 np->stats.tx_aborted_errors++;
2178 if (tx_status & DescTxFIFO)
2179 np->stats.tx_fifo_errors++;
2180 if (tx_status & DescTxCarrier)
2181 np->stats.tx_carrier_errors++;
2182 if (tx_status & DescTxOOWCol)
2183 np->stats.tx_window_errors++;
2184 np->stats.tx_errors++;
2185 }
2186 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2187 np->tx_skbuff[entry]->len,
2188 PCI_DMA_TODEVICE);
2189 /* Free the original skb. */
2190 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2191 np->tx_skbuff[entry] = NULL;
2192 }
2193 if (netif_queue_stopped(dev)
2194 && np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
2195 /* The ring is no longer full, wake queue. */
2196 netif_wake_queue(dev);
2197 }
2198}
2199
b27a16b7
MB		 2200/* The interrupt handler doesn't actually handle interrupts itself, it
2201 * schedules a NAPI poll if there is anything to do. */
1da177e4
LT		 2202static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
2203{
2204 struct net_device *dev = dev_instance;
2205 struct netdev_private *np = netdev_priv(dev);
2206 void __iomem * ioaddr = ns_ioaddr(dev);
1da177e4
LT		 2207
2208 if (np->hands_off)
2209 return IRQ_NONE;
b27a16b7
MB		 2210
2211 /* Reading automatically acknowledges. */
2212 np->intr_status = readl(ioaddr + IntrStatus);
1da177e4 2213
b27a16b7
MB		 2214 if (netif_msg_intr(np))
2215 printk(KERN_DEBUG
2216 "%s: Interrupt, status %#08x, mask %#08x.\n",
2217 dev->name, np->intr_status,
2218 readl(ioaddr + IntrMask));
1da177e4 2219
b27a16b7
MB		 2220 if (!np->intr_status)
2221 return IRQ_NONE;
1da177e4 2222
b27a16b7
MB		 2223 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
2224
2225 if (netif_rx_schedule_prep(dev)) {
2226 /* Disable interrupts and register for poll */
2227 natsemi_irq_disable(dev);
2228 __netif_rx_schedule(dev);
2229 }
2230 return IRQ_HANDLED;
2231}
2232
2233/* This is the NAPI poll routine. As well as the standard RX handling
2234 * it also handles all other interrupts that the chip might raise.
2235 */
2236static int natsemi_poll(struct net_device *dev, int *budget)
2237{
2238 struct netdev_private *np = netdev_priv(dev);
2239 void __iomem * ioaddr = ns_ioaddr(dev);
1da177e4 2240
b27a16b7
MB		 2241 int work_to_do = min(*budget, dev->quota);
2242 int work_done = 0;
2243
2244 do {
2245 if (np->intr_status &
2246 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
1da177e4
LT		 2247 spin_lock(&np->lock);
2248 netdev_tx_done(dev);
2249 spin_unlock(&np->lock);
2250 }
2251
2252 /* Abnormal error summary/uncommon events handlers. */
b27a16b7
MB		 2253 if (np->intr_status & IntrAbnormalSummary)
2254 netdev_error(dev, np->intr_status);
2255
2256 if (np->intr_status &
2257 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2258 IntrRxErr | IntrRxOverrun)) {
2259 netdev_rx(dev, &work_done, work_to_do);
1da177e4 2260 }
b27a16b7
MB		 2261
2262 *budget -= work_done;
2263 dev->quota -= work_done;
1da177e4 2264
b27a16b7
MB		 2265 if (work_done >= work_to_do)
2266 return 1;
2267
2268 np->intr_status = readl(ioaddr + IntrStatus);
2269 } while (np->intr_status);
1da177e4 2270
b27a16b7
MB		 2271 netif_rx_complete(dev);
2272
2273 /* Reenable interrupts providing nothing is trying to shut
2274 * the chip down. */
2275 spin_lock(&np->lock);
2276 if (!np->hands_off && netif_running(dev))
2277 natsemi_irq_enable(dev);
2278 spin_unlock(&np->lock);
2279
2280 return 0;
1da177e4
LT		 2281}
2282
2283/* This routine is logically part of the interrupt handler, but separated
2284 for clarity and better register allocation. */
b27a16b7 2285static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
1da177e4
LT		 2286{
2287 struct netdev_private *np = netdev_priv(dev);
2288 int entry = np->cur_rx % RX_RING_SIZE;
2289 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2290 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2291 unsigned int buflen = np->rx_buf_sz;
2292 void __iomem * ioaddr = ns_ioaddr(dev);
2293
2294 /* If the driver owns the next entry it's a new packet. Send it up. */
2295 while (desc_status < 0) { /* e.g. & DescOwn */
2296 int pkt_len;
2297 if (netif_msg_rx_status(np))
2298 printk(KERN_DEBUG
2299 " netdev_rx() entry %d status was %#08x.\n",
2300 entry, desc_status);
2301 if (--boguscnt < 0)
2302 break;
b27a16b7
MB		 2303
2304 if (*work_done >= work_to_do)
2305 break;
2306
2307 (*work_done)++;
2308
1da177e4
LT		 2309 pkt_len = (desc_status & DescSizeMask) - 4;
2310 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2311 if (desc_status & DescMore) {
2312 if (netif_msg_rx_err(np))
2313 printk(KERN_WARNING
2314 "%s: Oversized(?) Ethernet "
2315 "frame spanned multiple "
2316 "buffers, entry %#08x "
2317 "status %#08x.\n", dev->name,
2318 np->cur_rx, desc_status);
2319 np->stats.rx_length_errors++;
e72fd96e
MB		 2320
2321 /* The RX state machine has probably
2322 * locked up beneath us. Follow the
2323 * reset procedure documented in
2324 * AN-1287. */
2325
2326 spin_lock_irq(&np->lock);
2327 reset_rx(dev);
2328 reinit_rx(dev);
2329 writel(np->ring_dma, ioaddr + RxRingPtr);
2330 check_link(dev);
2331 spin_unlock_irq(&np->lock);
2332
2333 /* We'll enable RX on exit from this
2334 * function. */
2335 break;
2336
1da177e4
LT		 2337 } else {
2338 /* There was an error. */
2339 np->stats.rx_errors++;
2340 if (desc_status & (DescRxAbort|DescRxOver))
2341 np->stats.rx_over_errors++;
2342 if (desc_status & (DescRxLong|DescRxRunt))
2343 np->stats.rx_length_errors++;
2344 if (desc_status & (DescRxInvalid|DescRxAlign))
2345 np->stats.rx_frame_errors++;
2346 if (desc_status & DescRxCRC)
2347 np->stats.rx_crc_errors++;
2348 }
2349 } else if (pkt_len > np->rx_buf_sz) {
2350 /* if this is the tail of a double buffer
2351 * packet, we've already counted the error
2352 * on the first part. Ignore the second half.
2353 */
2354 } else {
2355 struct sk_buff *skb;
2356 /* Omit CRC size. */
2357 /* Check if the packet is long enough to accept
2358 * without copying to a minimally-sized skbuff. */
2359 if (pkt_len < rx_copybreak
2360 && (skb = dev_alloc_skb(pkt_len + RX_OFFSET)) != NULL) {
2361 skb->dev = dev;
2362 /* 16 byte align the IP header */
2363 skb_reserve(skb, RX_OFFSET);
2364 pci_dma_sync_single_for_cpu(np->pci_dev,
2365 np->rx_dma[entry],
2366 buflen,
2367 PCI_DMA_FROMDEVICE);
2368 eth_copy_and_sum(skb,
689be439 2369 np->rx_skbuff[entry]->data, pkt_len, 0);
1da177e4
LT		 2370 skb_put(skb, pkt_len);
2371 pci_dma_sync_single_for_device(np->pci_dev,
2372 np->rx_dma[entry],
2373 buflen,
2374 PCI_DMA_FROMDEVICE);
2375 } else {
2376 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2377 buflen, PCI_DMA_FROMDEVICE);
2378 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2379 np->rx_skbuff[entry] = NULL;
2380 }
2381 skb->protocol = eth_type_trans(skb, dev);
b27a16b7 2382 netif_receive_skb(skb);
1da177e4
LT		 2383 dev->last_rx = jiffies;
2384 np->stats.rx_packets++;
2385 np->stats.rx_bytes += pkt_len;
2386 }
2387 entry = (++np->cur_rx) % RX_RING_SIZE;
2388 np->rx_head_desc = &np->rx_ring[entry];
2389 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2390 }
2391 refill_rx(dev);
2392
2393 /* Restart Rx engine if stopped. */
2394 if (np->oom)
2395 mod_timer(&np->timer, jiffies + 1);
2396 else
2397 writel(RxOn, ioaddr + ChipCmd);
2398}
2399
2400static void netdev_error(struct net_device *dev, int intr_status)
2401{
2402 struct netdev_private *np = netdev_priv(dev);
2403 void __iomem * ioaddr = ns_ioaddr(dev);
2404
2405 spin_lock(&np->lock);
2406 if (intr_status & LinkChange) {
2407 u16 lpa = mdio_read(dev, MII_LPA);
2408 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE
2409 && netif_msg_link(np)) {
2410 printk(KERN_INFO
2411 "%s: Autonegotiation advertising"
2412 " %#04x partner %#04x.\n", dev->name,
2413 np->advertising, lpa);
2414 }
2415
2416 /* read MII int status to clear the flag */
2417 readw(ioaddr + MIntrStatus);
2418 check_link(dev);
2419 }
2420 if (intr_status & StatsMax) {
2421 __get_stats(dev);
2422 }
2423 if (intr_status & IntrTxUnderrun) {
2424 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2425 np->tx_config += TX_DRTH_VAL_INC;
2426 if (netif_msg_tx_err(np))
2427 printk(KERN_NOTICE
2428 "%s: increased tx threshold, txcfg %#08x.\n",
2429 dev->name, np->tx_config);
2430 } else {
2431 if (netif_msg_tx_err(np))
2432 printk(KERN_NOTICE
2433 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2434 dev->name, np->tx_config);
2435 }
2436 writel(np->tx_config, ioaddr + TxConfig);
2437 }
2438 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2439 int wol_status = readl(ioaddr + WOLCmd);
2440 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2441 dev->name, wol_status);
2442 }
2443 if (intr_status & RxStatusFIFOOver) {
2444 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2445 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2446 dev->name);
2447 }
2448 np->stats.rx_fifo_errors++;
2449 }
2450 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2451 if (intr_status & IntrPCIErr) {
2452 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2453 intr_status & IntrPCIErr);
2454 np->stats.tx_fifo_errors++;
2455 np->stats.rx_fifo_errors++;
2456 }
2457 spin_unlock(&np->lock);
2458}
2459
2460static void __get_stats(struct net_device *dev)
2461{
2462 void __iomem * ioaddr = ns_ioaddr(dev);
2463 struct netdev_private *np = netdev_priv(dev);
2464
2465 /* The chip only need report frame silently dropped. */
2466 np->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2467 np->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2468}
2469
2470static struct net_device_stats *get_stats(struct net_device *dev)
2471{
2472 struct netdev_private *np = netdev_priv(dev);
2473
2474 /* The chip only need report frame silently dropped. */
2475 spin_lock_irq(&np->lock);
2476 if (netif_running(dev) && !np->hands_off)
2477 __get_stats(dev);
2478 spin_unlock_irq(&np->lock);
2479
2480 return &np->stats;
2481}
2482
2483#ifdef CONFIG_NET_POLL_CONTROLLER
2484static void natsemi_poll_controller(struct net_device *dev)
2485{
2486 disable_irq(dev->irq);
2487 intr_handler(dev->irq, dev, NULL);
2488 enable_irq(dev->irq);
2489}
2490#endif
2491
2492#define HASH_TABLE 0x200
2493static void __set_rx_mode(struct net_device *dev)
2494{
2495 void __iomem * ioaddr = ns_ioaddr(dev);
2496 struct netdev_private *np = netdev_priv(dev);
2497 u8 mc_filter[64]; /* Multicast hash filter */
2498 u32 rx_mode;
2499
2500 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2501 /* Unconditionally log net taps. */
2502 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2503 dev->name);
2504 rx_mode = RxFilterEnable | AcceptBroadcast
2505 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
2506 } else if ((dev->mc_count > multicast_filter_limit)
2507 || (dev->flags & IFF_ALLMULTI)) {
2508 rx_mode = RxFilterEnable | AcceptBroadcast
2509 | AcceptAllMulticast | AcceptMyPhys;
2510 } else {
2511 struct dev_mc_list *mclist;
2512 int i;
2513 memset(mc_filter, 0, sizeof(mc_filter));
2514 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2515 i++, mclist = mclist->next) {
2516 int i = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 23) & 0x1ff;
2517 mc_filter[i/8] |= (1 << (i & 0x07));
2518 }
2519 rx_mode = RxFilterEnable | AcceptBroadcast
2520 | AcceptMulticast | AcceptMyPhys;
2521 for (i = 0; i < 64; i += 2) {
760f86d7
HX		 2522 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2523 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2524 ioaddr + RxFilterData);
1da177e4
LT		 2525 }
2526 }
2527 writel(rx_mode, ioaddr + RxFilterAddr);
2528 np->cur_rx_mode = rx_mode;
2529}
2530
2531static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2532{
2533 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS)
2534 return -EINVAL;
2535
2536 dev->mtu = new_mtu;
2537
2538 /* synchronized against open : rtnl_lock() held by caller */
2539 if (netif_running(dev)) {
2540 struct netdev_private *np = netdev_priv(dev);
2541 void __iomem * ioaddr = ns_ioaddr(dev);
2542
2543 disable_irq(dev->irq);
2544 spin_lock(&np->lock);
2545 /* stop engines */
2546 natsemi_stop_rxtx(dev);
2547 /* drain rx queue */
2548 drain_rx(dev);
2549 /* change buffers */
2550 set_bufsize(dev);
2551 reinit_rx(dev);
2552 writel(np->ring_dma, ioaddr + RxRingPtr);
2553 /* restart engines */
2554 writel(RxOn | TxOn, ioaddr + ChipCmd);
2555 spin_unlock(&np->lock);
2556 enable_irq(dev->irq);
2557 }
2558 return 0;
2559}
2560
2561static void set_rx_mode(struct net_device *dev)
2562{
2563 struct netdev_private *np = netdev_priv(dev);
2564 spin_lock_irq(&np->lock);
2565 if (!np->hands_off)
2566 __set_rx_mode(dev);
2567 spin_unlock_irq(&np->lock);
2568}
2569
2570static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2571{
2572 struct netdev_private *np = netdev_priv(dev);
2573 strncpy(info->driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
2574 strncpy(info->version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
2575 strncpy(info->bus_info, pci_name(np->pci_dev), ETHTOOL_BUSINFO_LEN);
2576}
2577
2578static int get_regs_len(struct net_device *dev)
2579{
2580 return NATSEMI_REGS_SIZE;
2581}
2582
2583static int get_eeprom_len(struct net_device *dev)
2584{
2585 return NATSEMI_EEPROM_SIZE;
2586}
2587
2588static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2589{
2590 struct netdev_private *np = netdev_priv(dev);
2591 spin_lock_irq(&np->lock);
2592 netdev_get_ecmd(dev, ecmd);
2593 spin_unlock_irq(&np->lock);
2594 return 0;
2595}
2596
2597static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2598{
2599 struct netdev_private *np = netdev_priv(dev);
2600 int res;
2601 spin_lock_irq(&np->lock);
2602 res = netdev_set_ecmd(dev, ecmd);
2603 spin_unlock_irq(&np->lock);
2604 return res;
2605}
2606
2607static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2608{
2609 struct netdev_private *np = netdev_priv(dev);
2610 spin_lock_irq(&np->lock);
2611 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2612 netdev_get_sopass(dev, wol->sopass);
2613 spin_unlock_irq(&np->lock);
2614}
2615
2616static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2617{
2618 struct netdev_private *np = netdev_priv(dev);
2619 int res;
2620 spin_lock_irq(&np->lock);
2621 netdev_set_wol(dev, wol->wolopts);
2622 res = netdev_set_sopass(dev, wol->sopass);
2623 spin_unlock_irq(&np->lock);
2624 return res;
2625}
2626
2627static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2628{
2629 struct netdev_private *np = netdev_priv(dev);
2630 regs->version = NATSEMI_REGS_VER;
2631 spin_lock_irq(&np->lock);
2632 netdev_get_regs(dev, buf);
2633 spin_unlock_irq(&np->lock);
2634}
2635
2636static u32 get_msglevel(struct net_device *dev)
2637{
2638 struct netdev_private *np = netdev_priv(dev);
2639 return np->msg_enable;
2640}
2641
2642static void set_msglevel(struct net_device *dev, u32 val)
2643{
2644 struct netdev_private *np = netdev_priv(dev);
2645 np->msg_enable = val;
2646}
2647
2648static int nway_reset(struct net_device *dev)
2649{
2650 int tmp;
2651 int r = -EINVAL;
2652 /* if autoneg is off, it's an error */
2653 tmp = mdio_read(dev, MII_BMCR);
2654 if (tmp & BMCR_ANENABLE) {
2655 tmp |= (BMCR_ANRESTART);
2656 mdio_write(dev, MII_BMCR, tmp);
2657 r = 0;
2658 }
2659 return r;
2660}
2661
2662static u32 get_link(struct net_device *dev)
2663{
2664 /* LSTATUS is latched low until a read - so read twice */
2665 mdio_read(dev, MII_BMSR);
2666 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2667}
2668
2669static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2670{
2671 struct netdev_private *np = netdev_priv(dev);
2672 u8 eebuf[NATSEMI_EEPROM_SIZE];
2673 int res;
2674
2675 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2676 spin_lock_irq(&np->lock);
2677 res = netdev_get_eeprom(dev, eebuf);
2678 spin_unlock_irq(&np->lock);
2679 if (!res)
2680 memcpy(data, eebuf+eeprom->offset, eeprom->len);
2681 return res;
2682}
2683
2684static struct ethtool_ops ethtool_ops = {
2685 .get_drvinfo = get_drvinfo,
2686 .get_regs_len = get_regs_len,
2687 .get_eeprom_len = get_eeprom_len,
2688 .get_settings = get_settings,
2689 .set_settings = set_settings,
2690 .get_wol = get_wol,
2691 .set_wol = set_wol,
2692 .get_regs = get_regs,
2693 .get_msglevel = get_msglevel,
2694 .set_msglevel = set_msglevel,
2695 .nway_reset = nway_reset,
2696 .get_link = get_link,
2697 .get_eeprom = get_eeprom,
2698};
2699
2700static int netdev_set_wol(struct net_device *dev, u32 newval)
2701{
2702 struct netdev_private *np = netdev_priv(dev);
2703 void __iomem * ioaddr = ns_ioaddr(dev);
2704 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2705
2706 /* translate to bitmasks this chip understands */
2707 if (newval & WAKE_PHY)
2708 data |= WakePhy;
2709 if (newval & WAKE_UCAST)
2710 data |= WakeUnicast;
2711 if (newval & WAKE_MCAST)
2712 data |= WakeMulticast;
2713 if (newval & WAKE_BCAST)
2714 data |= WakeBroadcast;
2715 if (newval & WAKE_ARP)
2716 data |= WakeArp;
2717 if (newval & WAKE_MAGIC)
2718 data |= WakeMagic;
2719 if (np->srr >= SRR_DP83815_D) {
2720 if (newval & WAKE_MAGICSECURE) {
2721 data |= WakeMagicSecure;
2722 }
2723 }
2724
2725 writel(data, ioaddr + WOLCmd);
2726
2727 return 0;
2728}
2729
2730static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2731{
2732 struct netdev_private *np = netdev_priv(dev);
2733 void __iomem * ioaddr = ns_ioaddr(dev);
2734 u32 regval = readl(ioaddr + WOLCmd);
2735
2736 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2737 | WAKE_ARP | WAKE_MAGIC);
2738
2739 if (np->srr >= SRR_DP83815_D) {
2740 /* SOPASS works on revD and higher */
2741 *supported |= WAKE_MAGICSECURE;
2742 }
2743 *cur = 0;
2744
2745 /* translate from chip bitmasks */
2746 if (regval & WakePhy)
2747 *cur |= WAKE_PHY;
2748 if (regval & WakeUnicast)
2749 *cur |= WAKE_UCAST;
2750 if (regval & WakeMulticast)
2751 *cur |= WAKE_MCAST;
2752 if (regval & WakeBroadcast)
2753 *cur |= WAKE_BCAST;
2754 if (regval & WakeArp)
2755 *cur |= WAKE_ARP;
2756 if (regval & WakeMagic)
2757 *cur |= WAKE_MAGIC;
2758 if (regval & WakeMagicSecure) {
2759 /* this can be on in revC, but it's broken */
2760 *cur |= WAKE_MAGICSECURE;
2761 }
2762
2763 return 0;
2764}
2765
2766static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2767{
2768 struct netdev_private *np = netdev_priv(dev);
2769 void __iomem * ioaddr = ns_ioaddr(dev);
2770 u16 *sval = (u16 *)newval;
2771 u32 addr;
2772
2773 if (np->srr < SRR_DP83815_D) {
2774 return 0;
2775 }
2776
2777 /* enable writing to these registers by disabling the RX filter */
2778 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2779 addr &= ~RxFilterEnable;
2780 writel(addr, ioaddr + RxFilterAddr);
2781
2782 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2783 writel(addr | 0xa, ioaddr + RxFilterAddr);
2784 writew(sval[0], ioaddr + RxFilterData);
2785
2786 writel(addr | 0xc, ioaddr + RxFilterAddr);
2787 writew(sval[1], ioaddr + RxFilterData);
2788
2789 writel(addr | 0xe, ioaddr + RxFilterAddr);
2790 writew(sval[2], ioaddr + RxFilterData);
2791
2792 /* re-enable the RX filter */
2793 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2794
2795 return 0;
2796}
2797
2798static int netdev_get_sopass(struct net_device *dev, u8 *data)
2799{
2800 struct netdev_private *np = netdev_priv(dev);
2801 void __iomem * ioaddr = ns_ioaddr(dev);
2802 u16 *sval = (u16 *)data;
2803 u32 addr;
2804
2805 if (np->srr < SRR_DP83815_D) {
2806 sval[0] = sval[1] = sval[2] = 0;
2807 return 0;
2808 }
2809
2810 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2811 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2812
2813 writel(addr | 0xa, ioaddr + RxFilterAddr);
2814 sval[0] = readw(ioaddr + RxFilterData);
2815
2816 writel(addr | 0xc, ioaddr + RxFilterAddr);
2817 sval[1] = readw(ioaddr + RxFilterData);
2818
2819 writel(addr | 0xe, ioaddr + RxFilterAddr);
2820 sval[2] = readw(ioaddr + RxFilterData);
2821
2822 writel(addr, ioaddr + RxFilterAddr);
2823
2824 return 0;
2825}
2826
2827static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2828{
2829 struct netdev_private *np = netdev_priv(dev);
2830 u32 tmp;
2831
2832 ecmd->port = dev->if_port;
2833 ecmd->speed = np->speed;
2834 ecmd->duplex = np->duplex;
2835 ecmd->autoneg = np->autoneg;
2836 ecmd->advertising = 0;
2837 if (np->advertising & ADVERTISE_10HALF)
2838 ecmd->advertising |= ADVERTISED_10baseT_Half;
2839 if (np->advertising & ADVERTISE_10FULL)
2840 ecmd->advertising |= ADVERTISED_10baseT_Full;
2841 if (np->advertising & ADVERTISE_100HALF)
2842 ecmd->advertising |= ADVERTISED_100baseT_Half;
2843 if (np->advertising & ADVERTISE_100FULL)
2844 ecmd->advertising |= ADVERTISED_100baseT_Full;
2845 ecmd->supported = (SUPPORTED_Autoneg |
2846 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2847 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2848 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2849 ecmd->phy_address = np->phy_addr_external;
2850 /*
2851 * We intentionally report the phy address of the external
2852 * phy, even if the internal phy is used. This is necessary
2853 * to work around a deficiency of the ethtool interface:
2854 * It's only possible to query the settings of the active
2855 * port. Therefore
2856 * # ethtool -s ethX port mii
2857 * actually sends an ioctl to switch to port mii with the
2858 * settings that are used for the current active port.
2859 * If we would report a different phy address in this
2860 * command, then
2861 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2862 * would unintentionally change the phy address.
2863 *
2864 * Fortunately the phy address doesn't matter with the
2865 * internal phy...
2866 */
2867
2868 /* set information based on active port type */
2869 switch (ecmd->port) {
2870 default:
2871 case PORT_TP:
2872 ecmd->advertising |= ADVERTISED_TP;
2873 ecmd->transceiver = XCVR_INTERNAL;
2874 break;
2875 case PORT_MII:
2876 ecmd->advertising |= ADVERTISED_MII;
2877 ecmd->transceiver = XCVR_EXTERNAL;
2878 break;
2879 case PORT_FIBRE:
2880 ecmd->advertising |= ADVERTISED_FIBRE;
2881 ecmd->transceiver = XCVR_EXTERNAL;
2882 break;
2883 }
2884
2885 /* if autonegotiation is on, try to return the active speed/duplex */
2886 if (ecmd->autoneg == AUTONEG_ENABLE) {
2887 ecmd->advertising |= ADVERTISED_Autoneg;
2888 tmp = mii_nway_result(
2889 np->advertising & mdio_read(dev, MII_LPA));
2890 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2891 ecmd->speed = SPEED_100;
2892 else
2893 ecmd->speed = SPEED_10;
2894 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2895 ecmd->duplex = DUPLEX_FULL;
2896 else
2897 ecmd->duplex = DUPLEX_HALF;
2898 }
2899
2900 /* ignore maxtxpkt, maxrxpkt for now */
2901
2902 return 0;
2903}
2904
2905static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2906{
2907 struct netdev_private *np = netdev_priv(dev);
2908
2909 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
2910 return -EINVAL;
2911 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
2912 return -EINVAL;
2913 if (ecmd->autoneg == AUTONEG_ENABLE) {
2914 if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
2915 ADVERTISED_10baseT_Full |
2916 ADVERTISED_100baseT_Half |
2917 ADVERTISED_100baseT_Full)) == 0) {
2918 return -EINVAL;
2919 }
2920 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2921 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2922 return -EINVAL;
2923 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2924 return -EINVAL;
2925 } else {
2926 return -EINVAL;
2927 }
2928
2929 /*
2930 * maxtxpkt, maxrxpkt: ignored for now.
2931 *
2932 * transceiver:
2933 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2934 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2935 * selects based on ecmd->port.
2936 *
2937 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2938 * phys that are connected to the mii bus. It's used to apply fibre
2939 * specific updates.
2940 */
2941
2942 /* WHEW! now lets bang some bits */
2943
2944 /* save the parms */
2945 dev->if_port = ecmd->port;
2946 np->autoneg = ecmd->autoneg;
2947 np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
2948 if (np->autoneg == AUTONEG_ENABLE) {
2949 /* advertise only what has been requested */
2950 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2951 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2952 np->advertising |= ADVERTISE_10HALF;
2953 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2954 np->advertising |= ADVERTISE_10FULL;
2955 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2956 np->advertising |= ADVERTISE_100HALF;
2957 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2958 np->advertising |= ADVERTISE_100FULL;
2959 } else {
2960 np->speed = ecmd->speed;
2961 np->duplex = ecmd->duplex;
2962 /* user overriding the initial full duplex parm? */
2963 if (np->duplex == DUPLEX_HALF)
2964 np->full_duplex = 0;
2965 }
2966
2967 /* get the right phy enabled */
2968 if (ecmd->port == PORT_TP)
2969 switch_port_internal(dev);
2970 else
2971 switch_port_external(dev);
2972
2973 /* set parms and see how this affected our link status */
2974 init_phy_fixup(dev);
2975 check_link(dev);
2976 return 0;
2977}
2978
2979static int netdev_get_regs(struct net_device *dev, u8 *buf)
2980{
2981 int i;
2982 int j;
2983 u32 rfcr;
2984 u32 *rbuf = (u32 *)buf;
2985 void __iomem * ioaddr = ns_ioaddr(dev);
2986
2987 /* read non-mii page 0 of registers */
2988 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
2989 rbuf[i] = readl(ioaddr + i*4);
2990 }
2991
2992 /* read current mii registers */
2993 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
2994 rbuf[i] = mdio_read(dev, i & 0x1f);
2995
2996 /* read only the 'magic' registers from page 1 */
2997 writew(1, ioaddr + PGSEL);
2998 rbuf[i++] = readw(ioaddr + PMDCSR);
2999 rbuf[i++] = readw(ioaddr + TSTDAT);
3000 rbuf[i++] = readw(ioaddr + DSPCFG);
3001 rbuf[i++] = readw(ioaddr + SDCFG);
3002 writew(0, ioaddr + PGSEL);
3003
3004 /* read RFCR indexed registers */
3005 rfcr = readl(ioaddr + RxFilterAddr);
3006 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
3007 writel(j*2, ioaddr + RxFilterAddr);
3008 rbuf[i++] = readw(ioaddr + RxFilterData);
3009 }
3010 writel(rfcr, ioaddr + RxFilterAddr);
3011
3012 /* the interrupt status is clear-on-read - see if we missed any */
3013 if (rbuf[4] & rbuf[5]) {
3014 printk(KERN_WARNING
3015 "%s: shoot, we dropped an interrupt (%#08x)\n",
3016 dev->name, rbuf[4] & rbuf[5]);
3017 }
3018
3019 return 0;
3020}
3021
3022#define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
3023 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
3024 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
3025 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
3026 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
3027 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
3028 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
3029 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
3030
3031static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
3032{
3033 int i;
3034 u16 *ebuf = (u16 *)buf;
3035 void __iomem * ioaddr = ns_ioaddr(dev);
3036
3037 /* eeprom_read reads 16 bits, and indexes by 16 bits */
3038 for (i = 0; i < NATSEMI_EEPROM_SIZE/2; i++) {
3039 ebuf[i] = eeprom_read(ioaddr, i);
3040 /* The EEPROM itself stores data bit-swapped, but eeprom_read
3041 * reads it back "sanely". So we swap it back here in order to
3042 * present it to userland as it is stored. */
3043 ebuf[i] = SWAP_BITS(ebuf[i]);
3044 }
3045 return 0;
3046}
3047
3048static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3049{
3050 struct mii_ioctl_data *data = if_mii(rq);
3051 struct netdev_private *np = netdev_priv(dev);
3052
3053 switch(cmd) {
3054 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
3055 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
3056 data->phy_id = np->phy_addr_external;
3057 /* Fall Through */
3058
3059 case SIOCGMIIREG: /* Read MII PHY register. */
3060 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
3061 /* The phy_id is not enough to uniquely identify
3062 * the intended target. Therefore the command is sent to
3063 * the given mii on the current port.
3064 */
3065 if (dev->if_port == PORT_TP) {
3066 if ((data->phy_id & 0x1f) == np->phy_addr_external)
3067 data->val_out = mdio_read(dev,
3068 data->reg_num & 0x1f);
3069 else
3070 data->val_out = 0;
3071 } else {
3072 move_int_phy(dev, data->phy_id & 0x1f);
3073 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
3074 data->reg_num & 0x1f);
3075 }
3076 return 0;
3077
3078 case SIOCSMIIREG: /* Write MII PHY register. */
3079 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
3080 if (!capable(CAP_NET_ADMIN))
3081 return -EPERM;
3082 if (dev->if_port == PORT_TP) {
3083 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3084 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3085 np->advertising = data->val_in;
3086 mdio_write(dev, data->reg_num & 0x1f,
3087 data->val_in);
3088 }
3089 } else {
3090 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3091 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3092 np->advertising = data->val_in;
3093 }
3094 move_int_phy(dev, data->phy_id & 0x1f);
3095 miiport_write(dev, data->phy_id & 0x1f,
3096 data->reg_num & 0x1f,
3097 data->val_in);
3098 }
3099 return 0;
3100 default:
3101 return -EOPNOTSUPP;
3102 }
3103}
3104
3105static void enable_wol_mode(struct net_device *dev, int enable_intr)
3106{
3107 void __iomem * ioaddr = ns_ioaddr(dev);
3108 struct netdev_private *np = netdev_priv(dev);
3109
3110 if (netif_msg_wol(np))
3111 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3112 dev->name);
3113
3114 /* For WOL we must restart the rx process in silent mode.
3115 * Write NULL to the RxRingPtr. Only possible if
3116 * rx process is stopped
3117 */
3118 writel(0, ioaddr + RxRingPtr);
3119
3120 /* read WoL status to clear */
3121 readl(ioaddr + WOLCmd);
3122
3123 /* PME on, clear status */
3124 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3125
3126 /* and restart the rx process */
3127 writel(RxOn, ioaddr + ChipCmd);
3128
3129 if (enable_intr) {
3130 /* enable the WOL interrupt.
3131 * Could be used to send a netlink message.
3132 */
3133 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
3134 writel(1, ioaddr + IntrEnable);
3135 }
3136}
3137
3138static int netdev_close(struct net_device *dev)
3139{
3140 void __iomem * ioaddr = ns_ioaddr(dev);
3141 struct netdev_private *np = netdev_priv(dev);
3142
3143 if (netif_msg_ifdown(np))
3144 printk(KERN_DEBUG
3145 "%s: Shutting down ethercard, status was %#04x.\n",
3146 dev->name, (int)readl(ioaddr + ChipCmd));
3147 if (netif_msg_pktdata(np))
3148 printk(KERN_DEBUG
3149 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3150 dev->name, np->cur_tx, np->dirty_tx,
3151 np->cur_rx, np->dirty_rx);
3152
3153 /*
3154 * FIXME: what if someone tries to close a device
3155 * that is suspended?
3156 * Should we reenable the nic to switch to
3157 * the final WOL settings?
3158 */
3159
3160 del_timer_sync(&np->timer);
3161 disable_irq(dev->irq);
3162 spin_lock_irq(&np->lock);
b27a16b7 3163 natsemi_irq_disable(dev);
1da177e4
LT		 3164 np->hands_off = 1;
3165 spin_unlock_irq(&np->lock);
3166 enable_irq(dev->irq);
3167
3168 free_irq(dev->irq, dev);
3169
3170 /* Interrupt disabled, interrupt handler released,
3171 * queue stopped, timer deleted, rtnl_lock held
3172 * All async codepaths that access the driver are disabled.
3173 */
3174 spin_lock_irq(&np->lock);
3175 np->hands_off = 0;
3176 readl(ioaddr + IntrMask);
3177 readw(ioaddr + MIntrStatus);
3178
3179 /* Freeze Stats */
3180 writel(StatsFreeze, ioaddr + StatsCtrl);
3181
3182 /* Stop the chip's Tx and Rx processes. */
3183 natsemi_stop_rxtx(dev);
3184
3185 __get_stats(dev);
3186 spin_unlock_irq(&np->lock);
3187
3188 /* clear the carrier last - an interrupt could reenable it otherwise */
3189 netif_carrier_off(dev);
3190 netif_stop_queue(dev);
3191
3192 dump_ring(dev);
3193 drain_ring(dev);
3194 free_ring(dev);
3195
3196 {
3197 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3198 if (wol) {
3199 /* restart the NIC in WOL mode.
3200 * The nic must be stopped for this.
3201 */
3202 enable_wol_mode(dev, 0);
3203 } else {
3204 /* Restore PME enable bit unmolested */
3205 writel(np->SavedClkRun, ioaddr + ClkRun);
3206 }
3207 }
3208 return 0;
3209}
3210
3211
3212static void __devexit natsemi_remove1 (struct pci_dev *pdev)
3213{
3214 struct net_device *dev = pci_get_drvdata(pdev);
3215 void __iomem * ioaddr = ns_ioaddr(dev);
3216
3217 unregister_netdev (dev);
3218 pci_release_regions (pdev);
3219 iounmap(ioaddr);
3220 free_netdev (dev);
3221 pci_set_drvdata(pdev, NULL);
3222}
3223
3224#ifdef CONFIG_PM
3225
3226/*
3227 * The ns83815 chip doesn't have explicit RxStop bits.
3228 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3229 * of the nic, thus this function must be very careful:
3230 *
3231 * suspend/resume synchronization:
3232 * entry points:
3233 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
3234 * start_tx, tx_timeout
3235 *
3236 * No function accesses the hardware without checking np->hands_off.
3237 * the check occurs under spin_lock_irq(&np->lock);
3238 * exceptions:
3239 * * netdev_ioctl: noncritical access.
3240 * * netdev_open: cannot happen due to the device_detach
3241 * * netdev_close: doesn't hurt.
3242 * * netdev_timer: timer stopped by natsemi_suspend.
3243 * * intr_handler: doesn't acquire the spinlock. suspend calls
3244 * disable_irq() to enforce synchronization.
b27a16b7
MB		 3245 * * natsemi_poll: checks before reenabling interrupts. suspend
3246 * sets hands_off, disables interrupts and then waits with
3247 * netif_poll_disable().
1da177e4
LT		 3248 *
3249 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3250 */
3251
3252static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3253{
3254 struct net_device *dev = pci_get_drvdata (pdev);
3255 struct netdev_private *np = netdev_priv(dev);
3256 void __iomem * ioaddr = ns_ioaddr(dev);
3257
3258 rtnl_lock();
3259 if (netif_running (dev)) {
3260 del_timer_sync(&np->timer);
3261
3262 disable_irq(dev->irq);
3263 spin_lock_irq(&np->lock);
3264
3265 writel(0, ioaddr + IntrEnable);
3266 np->hands_off = 1;
3267 natsemi_stop_rxtx(dev);
3268 netif_stop_queue(dev);
3269
3270 spin_unlock_irq(&np->lock);
3271 enable_irq(dev->irq);
3272
b27a16b7
MB		 3273 netif_poll_disable(dev);
3274
1da177e4
LT		 3275 /* Update the error counts. */
3276 __get_stats(dev);
3277
3278 /* pci_power_off(pdev, -1); */
3279 drain_ring(dev);
3280 {
3281 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3282 /* Restore PME enable bit */
3283 if (wol) {
3284 /* restart the NIC in WOL mode.
3285 * The nic must be stopped for this.
3286 * FIXME: use the WOL interrupt
3287 */
3288 enable_wol_mode(dev, 0);
3289 } else {
3290 /* Restore PME enable bit unmolested */
3291 writel(np->SavedClkRun, ioaddr + ClkRun);
3292 }
3293 }
3294 }
3295 netif_device_detach(dev);
3296 rtnl_unlock();
3297 return 0;
3298}
3299
3300
3301static int natsemi_resume (struct pci_dev *pdev)
3302{
3303 struct net_device *dev = pci_get_drvdata (pdev);
3304 struct netdev_private *np = netdev_priv(dev);
3305
3306 rtnl_lock();
3307 if (netif_device_present(dev))
3308 goto out;
3309 if (netif_running(dev)) {
3310 BUG_ON(!np->hands_off);
3311 pci_enable_device(pdev);
3312 /* pci_power_on(pdev); */
3313
3314 natsemi_reset(dev);
3315 init_ring(dev);
3316 disable_irq(dev->irq);
3317 spin_lock_irq(&np->lock);
3318 np->hands_off = 0;
3319 init_registers(dev);
3320 netif_device_attach(dev);
3321 spin_unlock_irq(&np->lock);
3322 enable_irq(dev->irq);
3323
3324 mod_timer(&np->timer, jiffies + 1*HZ);
3325 }
3326 netif_device_attach(dev);
b27a16b7 3327 netif_poll_enable(dev);
1da177e4
LT		 3328out:
3329 rtnl_unlock();
3330 return 0;
3331}
3332
3333#endif /* CONFIG_PM */
3334
3335static struct pci_driver natsemi_driver = {
3336 .name = DRV_NAME,
3337 .id_table = natsemi_pci_tbl,
3338 .probe = natsemi_probe1,
3339 .remove = __devexit_p(natsemi_remove1),
3340#ifdef CONFIG_PM
3341 .suspend = natsemi_suspend,
3342 .resume = natsemi_resume,
3343#endif
3344};
3345
3346static int __init natsemi_init_mod (void)
3347{
3348/* when a module, this is printed whether or not devices are found in probe */
3349#ifdef MODULE
3350 printk(version);
3351#endif
3352
3353 return pci_module_init (&natsemi_driver);
3354}
3355
3356static void __exit natsemi_exit_mod (void)
3357{
3358 pci_unregister_driver (&natsemi_driver);
3359}
3360
3361module_init(natsemi_init_mod);
3362module_exit(natsemi_exit_mod);
3363
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