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[net-next-2.6.git] / drivers / net / natsemi.c
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1da177e4
LT		 1/* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
2/*
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
b27a16b7 6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org>
1da177e4
LT		 7
8 This software may be used and distributed according to the terms of
9 the GNU General Public License (GPL), incorporated herein by reference.
10 Drivers based on or derived from this code fall under the GPL and must
11 retain the authorship, copyright and license notice. This file is not
12 a complete program and may only be used when the entire operating
13 system is licensed under the GPL. License for under other terms may be
14 available. Contact the original author for details.
15
16 The original author may be reached as becker@scyld.com, or at
17 Scyld Computing Corporation
18 410 Severn Ave., Suite 210
19 Annapolis MD 21403
20
21 Support information and updates available at
22 http://www.scyld.com/network/netsemi.html
03a8c661 23 [link no longer provides useful info -jgarzik]
1da177e4
LT		 24
25
1da177e4
LT		 26 TODO:
27 * big endian support with CFG:BEM instead of cpu_to_le32
1da177e4
LT		 28*/
29
1da177e4
LT		 30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/string.h>
33#include <linux/timer.h>
34#include <linux/errno.h>
35#include <linux/ioport.h>
36#include <linux/slab.h>
37#include <linux/interrupt.h>
38#include <linux/pci.h>
39#include <linux/netdevice.h>
40#include <linux/etherdevice.h>
41#include <linux/skbuff.h>
42#include <linux/init.h>
43#include <linux/spinlock.h>
44#include <linux/ethtool.h>
45#include <linux/delay.h>
46#include <linux/rtnetlink.h>
47#include <linux/mii.h>
48#include <linux/crc32.h>
49#include <linux/bitops.h>
b27a16b7 50#include <linux/prefetch.h>
1da177e4
LT		 51#include <asm/processor.h> /* Processor type for cache alignment. */
52#include <asm/io.h>
53#include <asm/irq.h>
54#include <asm/uaccess.h>
55
56#define DRV_NAME "natsemi"
d5b20697
AG		 57#define DRV_VERSION "2.1"
58#define DRV_RELDATE "Sept 11, 2006"
1da177e4
LT		 59
60#define RX_OFFSET 2
61
62/* Updated to recommendations in pci-skeleton v2.03. */
63
64/* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
66
67#define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
68 NETIF_MSG_LINK | \
69 NETIF_MSG_WOL | \
70 NETIF_MSG_RX_ERR | \
71 NETIF_MSG_TX_ERR)
72static int debug = -1;
73
1da177e4
LT		 74static int mtu;
75
76/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
77 This chip uses a 512 element hash table based on the Ethernet CRC. */
f71e1309 78static const int multicast_filter_limit = 100;
1da177e4
LT		 79
80/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
81 Setting to > 1518 effectively disables this feature. */
82static int rx_copybreak;
83
1a147809
MB		 84static int dspcfg_workaround = 1;
85
1da177e4
LT		 86/* Used to pass the media type, etc.
87 Both 'options[]' and 'full_duplex[]' should exist for driver
88 interoperability.
89 The media type is usually passed in 'options[]'.
90*/
91#define MAX_UNITS 8 /* More are supported, limit only on options */
92static int options[MAX_UNITS];
93static int full_duplex[MAX_UNITS];
94
95/* Operational parameters that are set at compile time. */
96
97/* Keep the ring sizes a power of two for compile efficiency.
98 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
99 Making the Tx ring too large decreases the effectiveness of channel
100 bonding and packet priority.
101 There are no ill effects from too-large receive rings. */
102#define TX_RING_SIZE 16
103#define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
104#define RX_RING_SIZE 32
105
106/* Operational parameters that usually are not changed. */
107/* Time in jiffies before concluding the transmitter is hung. */
108#define TX_TIMEOUT (2*HZ)
109
110#define NATSEMI_HW_TIMEOUT 400
f2cade13 111#define NATSEMI_TIMER_FREQ 5*HZ
1da177e4
LT		 112#define NATSEMI_PG0_NREGS 64
113#define NATSEMI_RFDR_NREGS 8
114#define NATSEMI_PG1_NREGS 4
115#define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
116 NATSEMI_PG1_NREGS)
117#define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
118#define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
1da177e4
LT		 119
120/* Buffer sizes:
121 * The nic writes 32-bit values, even if the upper bytes of
122 * a 32-bit value are beyond the end of the buffer.
123 */
124#define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
125#define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
126#define NATSEMI_LONGPKT 1518 /* limit for normal packets */
127#define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
128
129/* These identify the driver base version and may not be removed. */
23410495 130static const char version[] __devinitconst =
1da177e4
LT		 131 KERN_INFO DRV_NAME " dp8381x driver, version "
132 DRV_VERSION ", " DRV_RELDATE "\n"
ad361c98
JP		 133 " originally by Donald Becker <becker@scyld.com>\n"
134 " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
1da177e4
LT		 135
136MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
137MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
138MODULE_LICENSE("GPL");
139
1da177e4
LT		 140module_param(mtu, int, 0);
141module_param(debug, int, 0);
142module_param(rx_copybreak, int, 0);
1a147809 143module_param(dspcfg_workaround, int, 1);
1da177e4
LT		 144module_param_array(options, int, NULL, 0);
145module_param_array(full_duplex, int, NULL, 0);
1da177e4
LT		 146MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
147MODULE_PARM_DESC(debug, "DP8381x default debug level");
6aa20a22 148MODULE_PARM_DESC(rx_copybreak,
1da177e4 149 "DP8381x copy breakpoint for copy-only-tiny-frames");
1a147809 150MODULE_PARM_DESC(dspcfg_workaround, "DP8381x: control DspCfg workaround");
6aa20a22 151MODULE_PARM_DESC(options,
1da177e4
LT		 152 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
153MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
154
155/*
156 Theory of Operation
157
158I. Board Compatibility
159
160This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
161It also works with other chips in in the DP83810 series.
162
163II. Board-specific settings
164
165This driver requires the PCI interrupt line to be valid.
166It honors the EEPROM-set values.
167
168III. Driver operation
169
170IIIa. Ring buffers
171
172This driver uses two statically allocated fixed-size descriptor lists
173formed into rings by a branch from the final descriptor to the beginning of
174the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
175The NatSemi design uses a 'next descriptor' pointer that the driver forms
176into a list.
177
178IIIb/c. Transmit/Receive Structure
179
180This driver uses a zero-copy receive and transmit scheme.
181The driver allocates full frame size skbuffs for the Rx ring buffers at
182open() time and passes the skb->data field to the chip as receive data
183buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
184a fresh skbuff is allocated and the frame is copied to the new skbuff.
185When the incoming frame is larger, the skbuff is passed directly up the
186protocol stack. Buffers consumed this way are replaced by newly allocated
187skbuffs in a later phase of receives.
188
189The RX_COPYBREAK value is chosen to trade-off the memory wasted by
190using a full-sized skbuff for small frames vs. the copying costs of larger
191frames. New boards are typically used in generously configured machines
192and the underfilled buffers have negligible impact compared to the benefit of
193a single allocation size, so the default value of zero results in never
194copying packets. When copying is done, the cost is usually mitigated by using
195a combined copy/checksum routine. Copying also preloads the cache, which is
196most useful with small frames.
197
198A subtle aspect of the operation is that unaligned buffers are not permitted
199by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
200longword aligned for further processing. On copies frames are put into the
201skbuff at an offset of "+2", 16-byte aligning the IP header.
202
203IIId. Synchronization
204
205Most operations are synchronized on the np->lock irq spinlock, except the
6344f052
MB		 206recieve and transmit paths which are synchronised using a combination of
207hardware descriptor ownership, disabling interrupts and NAPI poll scheduling.
1da177e4
LT		 208
209IVb. References
210
211http://www.scyld.com/expert/100mbps.html
212http://www.scyld.com/expert/NWay.html
213Datasheet is available from:
214http://www.national.com/pf/DP/DP83815.html
215
216IVc. Errata
217
218None characterised.
219*/
220
221
222
1da177e4
LT		 223/*
224 * Support for fibre connections on Am79C874:
225 * This phy needs a special setup when connected to a fibre cable.
226 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
227 */
228#define PHYID_AM79C874 0x0022561b
229
a2b524b2
JG		 230enum {
231 MII_MCTRL = 0x15, /* mode control register */
232 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
233 MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
234};
1da177e4 235
6aab4447
MB		 236enum {
237 NATSEMI_FLAG_IGNORE_PHY = 0x1,
238};
6aa20a22 239
1da177e4 240/* array of board data directly indexed by pci_tbl[x].driver_data */
aa738adf 241static struct {
1da177e4
LT		 242 const char *name;
243 unsigned long flags;
a2b524b2 244 unsigned int eeprom_size;
1da177e4 245} natsemi_pci_info[] __devinitdata = {
6aab4447 246 { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 },
a2b524b2 247 { "NatSemi DP8381[56]", 0, 24 },
1da177e4
LT		 248};
249
a3aa1884 250static DEFINE_PCI_DEVICE_TABLE(natsemi_pci_tbl) = {
6aab4447 251 { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 },
36c843d5 252 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
a2b524b2 253 { } /* terminate list */
1da177e4
LT		 254};
255MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
256
257/* Offsets to the device registers.
258 Unlike software-only systems, device drivers interact with complex hardware.
259 It's not useful to define symbolic names for every register bit in the
260 device.
261*/
262enum register_offsets {
263 ChipCmd = 0x00,
264 ChipConfig = 0x04,
265 EECtrl = 0x08,
266 PCIBusCfg = 0x0C,
267 IntrStatus = 0x10,
268 IntrMask = 0x14,
269 IntrEnable = 0x18,
270 IntrHoldoff = 0x1C, /* DP83816 only */
271 TxRingPtr = 0x20,
272 TxConfig = 0x24,
273 RxRingPtr = 0x30,
274 RxConfig = 0x34,
275 ClkRun = 0x3C,
276 WOLCmd = 0x40,
277 PauseCmd = 0x44,
278 RxFilterAddr = 0x48,
279 RxFilterData = 0x4C,
280 BootRomAddr = 0x50,
281 BootRomData = 0x54,
282 SiliconRev = 0x58,
283 StatsCtrl = 0x5C,
284 StatsData = 0x60,
285 RxPktErrs = 0x60,
286 RxMissed = 0x68,
287 RxCRCErrs = 0x64,
288 BasicControl = 0x80,
289 BasicStatus = 0x84,
290 AnegAdv = 0x90,
291 AnegPeer = 0x94,
292 PhyStatus = 0xC0,
293 MIntrCtrl = 0xC4,
294 MIntrStatus = 0xC8,
295 PhyCtrl = 0xE4,
296
297 /* These are from the spec, around page 78... on a separate table.
298 * The meaning of these registers depend on the value of PGSEL. */
299 PGSEL = 0xCC,
300 PMDCSR = 0xE4,
301 TSTDAT = 0xFC,
302 DSPCFG = 0xF4,
303 SDCFG = 0xF8
304};
305/* the values for the 'magic' registers above (PGSEL=1) */
306#define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
307#define TSTDAT_VAL 0x0
308#define DSPCFG_VAL 0x5040
309#define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
310#define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
311#define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
312#define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
313
314/* misc PCI space registers */
315enum pci_register_offsets {
316 PCIPM = 0x44,
317};
318
319enum ChipCmd_bits {
320 ChipReset = 0x100,
321 RxReset = 0x20,
322 TxReset = 0x10,
323 RxOff = 0x08,
324 RxOn = 0x04,
325 TxOff = 0x02,
326 TxOn = 0x01,
327};
328
329enum ChipConfig_bits {
330 CfgPhyDis = 0x200,
331 CfgPhyRst = 0x400,
332 CfgExtPhy = 0x1000,
333 CfgAnegEnable = 0x2000,
334 CfgAneg100 = 0x4000,
335 CfgAnegFull = 0x8000,
336 CfgAnegDone = 0x8000000,
337 CfgFullDuplex = 0x20000000,
338 CfgSpeed100 = 0x40000000,
339 CfgLink = 0x80000000,
340};
341
342enum EECtrl_bits {
343 EE_ShiftClk = 0x04,
344 EE_DataIn = 0x01,
345 EE_ChipSelect = 0x08,
346 EE_DataOut = 0x02,
347 MII_Data = 0x10,
348 MII_Write = 0x20,
349 MII_ShiftClk = 0x40,
350};
351
352enum PCIBusCfg_bits {
353 EepromReload = 0x4,
354};
355
356/* Bits in the interrupt status/mask registers. */
357enum IntrStatus_bits {
358 IntrRxDone = 0x0001,
359 IntrRxIntr = 0x0002,
360 IntrRxErr = 0x0004,
361 IntrRxEarly = 0x0008,
362 IntrRxIdle = 0x0010,
363 IntrRxOverrun = 0x0020,
364 IntrTxDone = 0x0040,
365 IntrTxIntr = 0x0080,
366 IntrTxErr = 0x0100,
367 IntrTxIdle = 0x0200,
368 IntrTxUnderrun = 0x0400,
369 StatsMax = 0x0800,
370 SWInt = 0x1000,
371 WOLPkt = 0x2000,
372 LinkChange = 0x4000,
373 IntrHighBits = 0x8000,
374 RxStatusFIFOOver = 0x10000,
375 IntrPCIErr = 0xf00000,
376 RxResetDone = 0x1000000,
377 TxResetDone = 0x2000000,
378 IntrAbnormalSummary = 0xCD20,
379};
380
381/*
382 * Default Interrupts:
383 * Rx OK, Rx Packet Error, Rx Overrun,
384 * Tx OK, Tx Packet Error, Tx Underrun,
385 * MIB Service, Phy Interrupt, High Bits,
386 * Rx Status FIFO overrun,
387 * Received Target Abort, Received Master Abort,
388 * Signalled System Error, Received Parity Error
389 */
390#define DEFAULT_INTR 0x00f1cd65
391
392enum TxConfig_bits {
393 TxDrthMask = 0x3f,
394 TxFlthMask = 0x3f00,
395 TxMxdmaMask = 0x700000,
396 TxMxdma_512 = 0x0,
397 TxMxdma_4 = 0x100000,
398 TxMxdma_8 = 0x200000,
399 TxMxdma_16 = 0x300000,
400 TxMxdma_32 = 0x400000,
401 TxMxdma_64 = 0x500000,
402 TxMxdma_128 = 0x600000,
403 TxMxdma_256 = 0x700000,
404 TxCollRetry = 0x800000,
405 TxAutoPad = 0x10000000,
406 TxMacLoop = 0x20000000,
407 TxHeartIgn = 0x40000000,
408 TxCarrierIgn = 0x80000000
409};
410
6aa20a22 411/*
1da177e4
LT		 412 * Tx Configuration:
413 * - 256 byte DMA burst length
414 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
415 * - 64 bytes initial drain threshold (i.e. begin actual transmission
416 * when 64 byte are in the fifo)
417 * - on tx underruns, increase drain threshold by 64.
418 * - at most use a drain threshold of 1472 bytes: The sum of the fill
419 * threshold and the drain threshold must be less than 2016 bytes.
420 *
421 */
422#define TX_FLTH_VAL ((512/32) << 8)
423#define TX_DRTH_VAL_START (64/32)
424#define TX_DRTH_VAL_INC 2
425#define TX_DRTH_VAL_LIMIT (1472/32)
426
427enum RxConfig_bits {
428 RxDrthMask = 0x3e,
429 RxMxdmaMask = 0x700000,
430 RxMxdma_512 = 0x0,
431 RxMxdma_4 = 0x100000,
432 RxMxdma_8 = 0x200000,
433 RxMxdma_16 = 0x300000,
434 RxMxdma_32 = 0x400000,
435 RxMxdma_64 = 0x500000,
436 RxMxdma_128 = 0x600000,
437 RxMxdma_256 = 0x700000,
438 RxAcceptLong = 0x8000000,
439 RxAcceptTx = 0x10000000,
440 RxAcceptRunt = 0x40000000,
441 RxAcceptErr = 0x80000000
442};
443#define RX_DRTH_VAL (128/8)
444
445enum ClkRun_bits {
446 PMEEnable = 0x100,
447 PMEStatus = 0x8000,
448};
449
450enum WolCmd_bits {
451 WakePhy = 0x1,
452 WakeUnicast = 0x2,
453 WakeMulticast = 0x4,
454 WakeBroadcast = 0x8,
455 WakeArp = 0x10,
456 WakePMatch0 = 0x20,
457 WakePMatch1 = 0x40,
458 WakePMatch2 = 0x80,
459 WakePMatch3 = 0x100,
460 WakeMagic = 0x200,
461 WakeMagicSecure = 0x400,
462 SecureHack = 0x100000,
463 WokePhy = 0x400000,
464 WokeUnicast = 0x800000,
465 WokeMulticast = 0x1000000,
466 WokeBroadcast = 0x2000000,
467 WokeArp = 0x4000000,
468 WokePMatch0 = 0x8000000,
469 WokePMatch1 = 0x10000000,
470 WokePMatch2 = 0x20000000,
471 WokePMatch3 = 0x40000000,
472 WokeMagic = 0x80000000,
473 WakeOptsSummary = 0x7ff
474};
475
476enum RxFilterAddr_bits {
477 RFCRAddressMask = 0x3ff,
478 AcceptMulticast = 0x00200000,
479 AcceptMyPhys = 0x08000000,
480 AcceptAllPhys = 0x10000000,
481 AcceptAllMulticast = 0x20000000,
482 AcceptBroadcast = 0x40000000,
483 RxFilterEnable = 0x80000000
484};
485
486enum StatsCtrl_bits {
487 StatsWarn = 0x1,
488 StatsFreeze = 0x2,
489 StatsClear = 0x4,
490 StatsStrobe = 0x8,
491};
492
493enum MIntrCtrl_bits {
494 MICRIntEn = 0x2,
495};
496
497enum PhyCtrl_bits {
498 PhyAddrMask = 0x1f,
499};
500
501#define PHY_ADDR_NONE 32
502#define PHY_ADDR_INTERNAL 1
503
504/* values we might find in the silicon revision register */
505#define SRR_DP83815_C 0x0302
506#define SRR_DP83815_D 0x0403
507#define SRR_DP83816_A4 0x0504
508#define SRR_DP83816_A5 0x0505
509
510/* The Rx and Tx buffer descriptors. */
511/* Note that using only 32 bit fields simplifies conversion to big-endian
512 architectures. */
513struct netdev_desc {
eca1ad82
AV		 514 __le32 next_desc;
515 __le32 cmd_status;
516 __le32 addr;
517 __le32 software_use;
1da177e4
LT		 518};
519
520/* Bits in network_desc.status */
521enum desc_status_bits {
522 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
523 DescNoCRC=0x10000000, DescPktOK=0x08000000,
524 DescSizeMask=0xfff,
525
526 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
527 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
528 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
529 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
530
531 DescRxAbort=0x04000000, DescRxOver=0x02000000,
532 DescRxDest=0x01800000, DescRxLong=0x00400000,
533 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
534 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
535 DescRxLoop=0x00020000, DesRxColl=0x00010000,
536};
537
538struct netdev_private {
539 /* Descriptor rings first for alignment */
540 dma_addr_t ring_dma;
541 struct netdev_desc *rx_ring;
542 struct netdev_desc *tx_ring;
543 /* The addresses of receive-in-place skbuffs */
544 struct sk_buff *rx_skbuff[RX_RING_SIZE];
545 dma_addr_t rx_dma[RX_RING_SIZE];
546 /* address of a sent-in-place packet/buffer, for later free() */
547 struct sk_buff *tx_skbuff[TX_RING_SIZE];
548 dma_addr_t tx_dma[TX_RING_SIZE];
bea3348e
SH		 549 struct net_device *dev;
550 struct napi_struct napi;
1da177e4
LT		 551 /* Media monitoring timer */
552 struct timer_list timer;
553 /* Frequently used values: keep some adjacent for cache effect */
554 struct pci_dev *pci_dev;
555 struct netdev_desc *rx_head_desc;
556 /* Producer/consumer ring indices */
557 unsigned int cur_rx, dirty_rx;
558 unsigned int cur_tx, dirty_tx;
559 /* Based on MTU+slack. */
560 unsigned int rx_buf_sz;
561 int oom;
b27a16b7
MB		 562 /* Interrupt status */
563 u32 intr_status;
1da177e4
LT		 564 /* Do not touch the nic registers */
565 int hands_off;
68c90166
MB		 566 /* Don't pay attention to the reported link state. */
567 int ignore_phy;
1da177e4
LT		 568 /* external phy that is used: only valid if dev->if_port != PORT_TP */
569 int mii;
570 int phy_addr_external;
571 unsigned int full_duplex;
572 /* Rx filter */
573 u32 cur_rx_mode;
574 u32 rx_filter[16];
575 /* FIFO and PCI burst thresholds */
576 u32 tx_config, rx_config;
577 /* original contents of ClkRun register */
578 u32 SavedClkRun;
579 /* silicon revision */
580 u32 srr;
581 /* expected DSPCFG value */
582 u16 dspcfg;
1a147809 583 int dspcfg_workaround;
1da177e4
LT		 584 /* parms saved in ethtool format */
585 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
586 u8 duplex; /* Duplex, half or full */
587 u8 autoneg; /* Autonegotiation enabled */
588 /* MII transceiver section */
589 u16 advertising;
590 unsigned int iosize;
591 spinlock_t lock;
592 u32 msg_enable;
a8b4cf42
MB		 593 /* EEPROM data */
594 int eeprom_size;
1da177e4
LT		 595};
596
597static void move_int_phy(struct net_device *dev, int addr);
598static int eeprom_read(void __iomem *ioaddr, int location);
599static int mdio_read(struct net_device *dev, int reg);
600static void mdio_write(struct net_device *dev, int reg, u16 data);
601static void init_phy_fixup(struct net_device *dev);
602static int miiport_read(struct net_device *dev, int phy_id, int reg);
603static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
604static int find_mii(struct net_device *dev);
605static void natsemi_reset(struct net_device *dev);
606static void natsemi_reload_eeprom(struct net_device *dev);
607static void natsemi_stop_rxtx(struct net_device *dev);
608static int netdev_open(struct net_device *dev);
609static void do_cable_magic(struct net_device *dev);
610static void undo_cable_magic(struct net_device *dev);
611static void check_link(struct net_device *dev);
612static void netdev_timer(unsigned long data);
613static void dump_ring(struct net_device *dev);
ed4cb133 614static void ns_tx_timeout(struct net_device *dev);
1da177e4
LT		 615static int alloc_ring(struct net_device *dev);
616static void refill_rx(struct net_device *dev);
617static void init_ring(struct net_device *dev);
618static void drain_tx(struct net_device *dev);
619static void drain_ring(struct net_device *dev);
620static void free_ring(struct net_device *dev);
621static void reinit_ring(struct net_device *dev);
622static void init_registers(struct net_device *dev);
61357325 623static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
7d12e780 624static irqreturn_t intr_handler(int irq, void *dev_instance);
1da177e4 625static void netdev_error(struct net_device *dev, int intr_status);
bea3348e 626static int natsemi_poll(struct napi_struct *napi, int budget);
b27a16b7 627static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
1da177e4
LT		 628static void netdev_tx_done(struct net_device *dev);
629static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
630#ifdef CONFIG_NET_POLL_CONTROLLER
631static void natsemi_poll_controller(struct net_device *dev);
632#endif
633static void __set_rx_mode(struct net_device *dev);
634static void set_rx_mode(struct net_device *dev);
635static void __get_stats(struct net_device *dev);
636static struct net_device_stats *get_stats(struct net_device *dev);
637static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
638static int netdev_set_wol(struct net_device *dev, u32 newval);
639static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
640static int netdev_set_sopass(struct net_device *dev, u8 *newval);
641static int netdev_get_sopass(struct net_device *dev, u8 *data);
642static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
643static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
644static void enable_wol_mode(struct net_device *dev, int enable_intr);
645static int netdev_close(struct net_device *dev);
646static int netdev_get_regs(struct net_device *dev, u8 *buf);
647static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
7282d491 648static const struct ethtool_ops ethtool_ops;
1da177e4 649
1a147809
MB		 650#define NATSEMI_ATTR(_name) \
651static ssize_t natsemi_show_##_name(struct device *dev, \
652 struct device_attribute *attr, char *buf); \
653 static ssize_t natsemi_set_##_name(struct device *dev, \
654 struct device_attribute *attr, \
655 const char *buf, size_t count); \
656 static DEVICE_ATTR(_name, 0644, natsemi_show_##_name, natsemi_set_##_name)
657
658#define NATSEMI_CREATE_FILE(_dev, _name) \
659 device_create_file(&_dev->dev, &dev_attr_##_name)
660#define NATSEMI_REMOVE_FILE(_dev, _name) \
f6c42865 661 device_remove_file(&_dev->dev, &dev_attr_##_name)
1a147809
MB		 662
663NATSEMI_ATTR(dspcfg_workaround);
664
665static ssize_t natsemi_show_dspcfg_workaround(struct device *dev,
7d2e3cb7 666 struct device_attribute *attr,
1a147809
MB		 667 char *buf)
668{
669 struct netdev_private *np = netdev_priv(to_net_dev(dev));
670
671 return sprintf(buf, "%s\n", np->dspcfg_workaround ? "on" : "off");
672}
673
674static ssize_t natsemi_set_dspcfg_workaround(struct device *dev,
675 struct device_attribute *attr,
676 const char *buf, size_t count)
677{
678 struct netdev_private *np = netdev_priv(to_net_dev(dev));
679 int new_setting;
d41f2d17 680 unsigned long flags;
1a147809
MB		 681
682 /* Find out the new setting */
683 if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1))
684 new_setting = 1;
8e95a202
JP		 685 else if (!strncmp("off", buf, count - 1) ||
686 !strncmp("0", buf, count - 1))
1a147809
MB		 687 new_setting = 0;
688 else
7d2e3cb7 689 return count;
1a147809
MB		 690
691 spin_lock_irqsave(&np->lock, flags);
692
693 np->dspcfg_workaround = new_setting;
694
695 spin_unlock_irqrestore(&np->lock, flags);
696
697 return count;
698}
699
1da177e4
LT		 700static inline void __iomem *ns_ioaddr(struct net_device *dev)
701{
702 return (void __iomem *) dev->base_addr;
703}
704
b27a16b7
MB		 705static inline void natsemi_irq_enable(struct net_device *dev)
706{
707 writel(1, ns_ioaddr(dev) + IntrEnable);
708 readl(ns_ioaddr(dev) + IntrEnable);
709}
710
711static inline void natsemi_irq_disable(struct net_device *dev)
712{
713 writel(0, ns_ioaddr(dev) + IntrEnable);
714 readl(ns_ioaddr(dev) + IntrEnable);
715}
716
1da177e4
LT		 717static void move_int_phy(struct net_device *dev, int addr)
718{
719 struct netdev_private *np = netdev_priv(dev);
720 void __iomem *ioaddr = ns_ioaddr(dev);
721 int target = 31;
722
6aa20a22 723 /*
1da177e4
LT		 724 * The internal phy is visible on the external mii bus. Therefore we must
725 * move it away before we can send commands to an external phy.
726 * There are two addresses we must avoid:
727 * - the address on the external phy that is used for transmission.
728 * - the address that we want to access. User space can access phys
729 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independant from the
730 * phy that is used for transmission.
731 */
732
733 if (target == addr)
734 target--;
735 if (target == np->phy_addr_external)
736 target--;
737 writew(target, ioaddr + PhyCtrl);
738 readw(ioaddr + PhyCtrl);
739 udelay(1);
740}
741
5a40f09b
JG		 742static void __devinit natsemi_init_media (struct net_device *dev)
743{
744 struct netdev_private *np = netdev_priv(dev);
745 u32 tmp;
746
68c90166
MB		 747 if (np->ignore_phy)
748 netif_carrier_on(dev);
749 else
750 netif_carrier_off(dev);
5a40f09b
JG		 751
752 /* get the initial settings from hardware */
753 tmp = mdio_read(dev, MII_BMCR);
754 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
755 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
756 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
757 np->advertising= mdio_read(dev, MII_ADVERTISE);
758
8e95a202
JP		 759 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL &&
760 netif_msg_probe(np)) {
5a40f09b
JG		 761 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
762 "10%s %s duplex.\n",
763 pci_name(np->pci_dev),
764 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
765 "enabled, advertise" : "disabled, force",
766 (np->advertising &
767 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
768 "0" : "",
769 (np->advertising &
770 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
771 "full" : "half");
772 }
773 if (netif_msg_probe(np))
774 printk(KERN_INFO
775 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
776 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
777 np->advertising);
778
779}
780
2b7d0c70
SH		 781static const struct net_device_ops natsemi_netdev_ops = {
782 .ndo_open = netdev_open,
783 .ndo_stop = netdev_close,
784 .ndo_start_xmit = start_tx,
785 .ndo_get_stats = get_stats,
786 .ndo_set_multicast_list = set_rx_mode,
787 .ndo_change_mtu = natsemi_change_mtu,
788 .ndo_do_ioctl = netdev_ioctl,
789 .ndo_tx_timeout = ns_tx_timeout,
790 .ndo_set_mac_address = eth_mac_addr,
791 .ndo_validate_addr = eth_validate_addr,
792#ifdef CONFIG_NET_POLL_CONTROLLER
793 .ndo_poll_controller = natsemi_poll_controller,
794#endif
795};
796
1da177e4
LT		 797static int __devinit natsemi_probe1 (struct pci_dev *pdev,
798 const struct pci_device_id *ent)
799{
800 struct net_device *dev;
801 struct netdev_private *np;
802 int i, option, irq, chip_idx = ent->driver_data;
803 static int find_cnt = -1;
703bb99c
SS		 804 resource_size_t iostart;
805 unsigned long iosize;
1da177e4
LT		 806 void __iomem *ioaddr;
807 const int pcibar = 1; /* PCI base address register */
808 int prev_eedata;
809 u32 tmp;
810
811/* when built into the kernel, we only print version if device is found */
812#ifndef MODULE
813 static int printed_version;
814 if (!printed_version++)
815 printk(version);
816#endif
817
818 i = pci_enable_device(pdev);
819 if (i) return i;
820
821 /* natsemi has a non-standard PM control register
822 * in PCI config space. Some boards apparently need
823 * to be brought to D0 in this manner.
824 */
825 pci_read_config_dword(pdev, PCIPM, &tmp);
826 if (tmp & PCI_PM_CTRL_STATE_MASK) {
827 /* D0 state, disable PME assertion */
828 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
829 pci_write_config_dword(pdev, PCIPM, newtmp);
830 }
831
832 find_cnt++;
833 iostart = pci_resource_start(pdev, pcibar);
834 iosize = pci_resource_len(pdev, pcibar);
835 irq = pdev->irq;
836
a2b524b2 837 pci_set_master(pdev);
1da177e4
LT		 838
839 dev = alloc_etherdev(sizeof (struct netdev_private));
840 if (!dev)
841 return -ENOMEM;
1da177e4
LT		 842 SET_NETDEV_DEV(dev, &pdev->dev);
843
844 i = pci_request_regions(pdev, DRV_NAME);
845 if (i)
846 goto err_pci_request_regions;
847
848 ioaddr = ioremap(iostart, iosize);
849 if (!ioaddr) {
850 i = -ENOMEM;
851 goto err_ioremap;
852 }
853
854 /* Work around the dropped serial bit. */
855 prev_eedata = eeprom_read(ioaddr, 6);
856 for (i = 0; i < 3; i++) {
857 int eedata = eeprom_read(ioaddr, i + 7);
858 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
859 dev->dev_addr[i*2+1] = eedata >> 7;
860 prev_eedata = eedata;
861 }
862
863 dev->base_addr = (unsigned long __force) ioaddr;
864 dev->irq = irq;
865
866 np = netdev_priv(dev);
bea3348e 867 netif_napi_add(dev, &np->napi, natsemi_poll, 64);
bbbab5ca 868 np->dev = dev;
1da177e4
LT		 869
870 np->pci_dev = pdev;
871 pci_set_drvdata(pdev, dev);
872 np->iosize = iosize;
873 spin_lock_init(&np->lock);
874 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
875 np->hands_off = 0;
b27a16b7 876 np->intr_status = 0;
a2b524b2 877 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size;
6aab4447
MB		 878 if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY)
879 np->ignore_phy = 1;
880 else
881 np->ignore_phy = 0;
1a147809 882 np->dspcfg_workaround = dspcfg_workaround;
1da177e4
LT		 883
884 /* Initial port:
68c90166 885 * - If configured to ignore the PHY set up for external.
1da177e4
LT		 886 * - If the nic was configured to use an external phy and if find_mii
887 * finds a phy: use external port, first phy that replies.
888 * - Otherwise: internal port.
889 * Note that the phy address for the internal phy doesn't matter:
890 * The address would be used to access a phy over the mii bus, but
891 * the internal phy is accessed through mapped registers.
892 */
68c90166 893 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)
1da177e4
LT		 894 dev->if_port = PORT_MII;
895 else
896 dev->if_port = PORT_TP;
897 /* Reset the chip to erase previous misconfiguration. */
898 natsemi_reload_eeprom(dev);
899 natsemi_reset(dev);
900
901 if (dev->if_port != PORT_TP) {
902 np->phy_addr_external = find_mii(dev);
68c90166
MB		 903 /* If we're ignoring the PHY it doesn't matter if we can't
904 * find one. */
905 if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) {
1da177e4
LT		 906 dev->if_port = PORT_TP;
907 np->phy_addr_external = PHY_ADDR_INTERNAL;
908 }
909 } else {
910 np->phy_addr_external = PHY_ADDR_INTERNAL;
911 }
912
913 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
914 if (dev->mem_start)
915 option = dev->mem_start;
916
917 /* The lower four bits are the media type. */
918 if (option) {
919 if (option & 0x200)
920 np->full_duplex = 1;
921 if (option & 15)
922 printk(KERN_INFO
923 "natsemi %s: ignoring user supplied media type %d",
924 pci_name(np->pci_dev), option & 15);
925 }
926 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
927 np->full_duplex = 1;
928
2b7d0c70 929 dev->netdev_ops = &natsemi_netdev_ops;
1da177e4 930 dev->watchdog_timeo = TX_TIMEOUT;
b27a16b7 931
1da177e4
LT		 932 SET_ETHTOOL_OPS(dev, &ethtool_ops);
933
934 if (mtu)
935 dev->mtu = mtu;
936
5a40f09b 937 natsemi_init_media(dev);
1da177e4
LT		 938
939 /* save the silicon revision for later querying */
940 np->srr = readl(ioaddr + SiliconRev);
941 if (netif_msg_hw(np))
942 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
943 pci_name(np->pci_dev), np->srr);
944
945 i = register_netdev(dev);
946 if (i)
947 goto err_register_netdev;
948
1a147809
MB		 949 if (NATSEMI_CREATE_FILE(pdev, dspcfg_workaround))
950 goto err_create_file;
951
1da177e4 952 if (netif_msg_drv(np)) {
703bb99c 953 printk(KERN_INFO "natsemi %s: %s at %#08llx "
e174961c 954 "(%s), %pM, IRQ %d",
703bb99c
SS		 955 dev->name, natsemi_pci_info[chip_idx].name,
956 (unsigned long long)iostart, pci_name(np->pci_dev),
e174961c 957 dev->dev_addr, irq);
1da177e4
LT		 958 if (dev->if_port == PORT_TP)
959 printk(", port TP.\n");
68c90166
MB		 960 else if (np->ignore_phy)
961 printk(", port MII, ignoring PHY\n");
1da177e4
LT		 962 else
963 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
964 }
965 return 0;
966
1a147809
MB		 967 err_create_file:
968 unregister_netdev(dev);
969
1da177e4
LT		 970 err_register_netdev:
971 iounmap(ioaddr);
972
973 err_ioremap:
974 pci_release_regions(pdev);
975 pci_set_drvdata(pdev, NULL);
976
977 err_pci_request_regions:
978 free_netdev(dev);
979 return i;
980}
981
982
983/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
984 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
985
986/* Delay between EEPROM clock transitions.
987 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
988 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
989 made udelay() unreliable.
990 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
405bbe9f 991 deprecated.
1da177e4
LT		 992*/
993#define eeprom_delay(ee_addr) readl(ee_addr)
994
995#define EE_Write0 (EE_ChipSelect)
996#define EE_Write1 (EE_ChipSelect | EE_DataIn)
997
998/* The EEPROM commands include the alway-set leading bit. */
999enum EEPROM_Cmds {
1000 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1001};
1002
1003static int eeprom_read(void __iomem *addr, int location)
1004{
1005 int i;
1006 int retval = 0;
1007 void __iomem *ee_addr = addr + EECtrl;
1008 int read_cmd = location | EE_ReadCmd;
1009
1010 writel(EE_Write0, ee_addr);
1011
1012 /* Shift the read command bits out. */
1013 for (i = 10; i >= 0; i--) {
1014 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1015 writel(dataval, ee_addr);
1016 eeprom_delay(ee_addr);
1017 writel(dataval | EE_ShiftClk, ee_addr);
1018 eeprom_delay(ee_addr);
1019 }
1020 writel(EE_ChipSelect, ee_addr);
1021 eeprom_delay(ee_addr);
1022
1023 for (i = 0; i < 16; i++) {
1024 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1025 eeprom_delay(ee_addr);
1026 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1027 writel(EE_ChipSelect, ee_addr);
1028 eeprom_delay(ee_addr);
1029 }
1030
1031 /* Terminate the EEPROM access. */
1032 writel(EE_Write0, ee_addr);
1033 writel(0, ee_addr);
1034 return retval;
1035}
1036
1037/* MII transceiver control section.
1038 * The 83815 series has an internal transceiver, and we present the
1039 * internal management registers as if they were MII connected.
1040 * External Phy registers are referenced through the MII interface.
1041 */
1042
1043/* clock transitions >= 20ns (25MHz)
1044 * One readl should be good to PCI @ 100MHz
1045 */
1046#define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1047
1048static int mii_getbit (struct net_device *dev)
1049{
1050 int data;
1051 void __iomem *ioaddr = ns_ioaddr(dev);
1052
1053 writel(MII_ShiftClk, ioaddr + EECtrl);
1054 data = readl(ioaddr + EECtrl);
1055 writel(0, ioaddr + EECtrl);
1056 mii_delay(ioaddr);
1057 return (data & MII_Data)? 1 : 0;
1058}
1059
1060static void mii_send_bits (struct net_device *dev, u32 data, int len)
1061{
1062 u32 i;
1063 void __iomem *ioaddr = ns_ioaddr(dev);
1064
1065 for (i = (1 << (len-1)); i; i >>= 1)
1066 {
1067 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1068 writel(mdio_val, ioaddr + EECtrl);
1069 mii_delay(ioaddr);
1070 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1071 mii_delay(ioaddr);
1072 }
1073 writel(0, ioaddr + EECtrl);
1074 mii_delay(ioaddr);
1075}
1076
1077static int miiport_read(struct net_device *dev, int phy_id, int reg)
1078{
1079 u32 cmd;
1080 int i;
1081 u32 retval = 0;
1082
1083 /* Ensure sync */
1084 mii_send_bits (dev, 0xffffffff, 32);
1085 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1086 /* ST,OP = 0110'b for read operation */
1087 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1088 mii_send_bits (dev, cmd, 14);
1089 /* Turnaround */
1090 if (mii_getbit (dev))
1091 return 0;
1092 /* Read data */
1093 for (i = 0; i < 16; i++) {
1094 retval <<= 1;
1095 retval |= mii_getbit (dev);
1096 }
1097 /* End cycle */
1098 mii_getbit (dev);
1099 return retval;
1100}
1101
1102static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1103{
1104 u32 cmd;
1105
1106 /* Ensure sync */
1107 mii_send_bits (dev, 0xffffffff, 32);
1108 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1109 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1110 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1111 mii_send_bits (dev, cmd, 32);
1112 /* End cycle */
1113 mii_getbit (dev);
1114}
1115
1116static int mdio_read(struct net_device *dev, int reg)
1117{
1118 struct netdev_private *np = netdev_priv(dev);
1119 void __iomem *ioaddr = ns_ioaddr(dev);
1120
1121 /* The 83815 series has two ports:
1122 * - an internal transceiver
1123 * - an external mii bus
1124 */
1125 if (dev->if_port == PORT_TP)
1126 return readw(ioaddr+BasicControl+(reg<<2));
1127 else
1128 return miiport_read(dev, np->phy_addr_external, reg);
1129}
1130
1131static void mdio_write(struct net_device *dev, int reg, u16 data)
1132{
1133 struct netdev_private *np = netdev_priv(dev);
1134 void __iomem *ioaddr = ns_ioaddr(dev);
1135
1136 /* The 83815 series has an internal transceiver; handle separately */
1137 if (dev->if_port == PORT_TP)
1138 writew(data, ioaddr+BasicControl+(reg<<2));
1139 else
1140 miiport_write(dev, np->phy_addr_external, reg, data);
1141}
1142
1143static void init_phy_fixup(struct net_device *dev)
1144{
1145 struct netdev_private *np = netdev_priv(dev);
1146 void __iomem *ioaddr = ns_ioaddr(dev);
1147 int i;
1148 u32 cfg;
1149 u16 tmp;
1150
1151 /* restore stuff lost when power was out */
1152 tmp = mdio_read(dev, MII_BMCR);
1153 if (np->autoneg == AUTONEG_ENABLE) {
1154 /* renegotiate if something changed */
8e95a202
JP		 1155 if ((tmp & BMCR_ANENABLE) == 0 ||
1156 np->advertising != mdio_read(dev, MII_ADVERTISE))
1da177e4
LT		 1157 {
1158 /* turn on autonegotiation and force negotiation */
1159 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1160 mdio_write(dev, MII_ADVERTISE, np->advertising);
1161 }
1162 } else {
1163 /* turn off auto negotiation, set speed and duplexity */
1164 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1165 if (np->speed == SPEED_100)
1166 tmp |= BMCR_SPEED100;
1167 if (np->duplex == DUPLEX_FULL)
1168 tmp |= BMCR_FULLDPLX;
6aa20a22 1169 /*
1da177e4
LT		 1170 * Note: there is no good way to inform the link partner
1171 * that our capabilities changed. The user has to unplug
1172 * and replug the network cable after some changes, e.g.
1173 * after switching from 10HD, autoneg off to 100 HD,
1174 * autoneg off.
1175 */
1176 }
1177 mdio_write(dev, MII_BMCR, tmp);
1178 readl(ioaddr + ChipConfig);
1179 udelay(1);
1180
1181 /* find out what phy this is */
1182 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1183 + mdio_read(dev, MII_PHYSID2);
1184
1185 /* handle external phys here */
1186 switch (np->mii) {
1187 case PHYID_AM79C874:
1188 /* phy specific configuration for fibre/tp operation */
1189 tmp = mdio_read(dev, MII_MCTRL);
1190 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1191 if (dev->if_port == PORT_FIBRE)
1192 tmp |= MII_FX_SEL;
1193 else
1194 tmp |= MII_EN_SCRM;
1195 mdio_write(dev, MII_MCTRL, tmp);
1196 break;
1197 default:
1198 break;
1199 }
1200 cfg = readl(ioaddr + ChipConfig);
1201 if (cfg & CfgExtPhy)
1202 return;
1203
1204 /* On page 78 of the spec, they recommend some settings for "optimum
1205 performance" to be done in sequence. These settings optimize some
1206 of the 100Mbit autodetection circuitry. They say we only want to
1207 do this for rev C of the chip, but engineers at NSC (Bradley
1208 Kennedy) recommends always setting them. If you don't, you get
1209 errors on some autonegotiations that make the device unusable.
1210
1211 It seems that the DSP needs a few usec to reinitialize after
1212 the start of the phy. Just retry writing these values until they
1213 stick.
1214 */
1215 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1216
1217 int dspcfg;
1218 writew(1, ioaddr + PGSEL);
1219 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1220 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1221 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1222 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1223 writew(np->dspcfg, ioaddr + DSPCFG);
1224 writew(SDCFG_VAL, ioaddr + SDCFG);
1225 writew(0, ioaddr + PGSEL);
1226 readl(ioaddr + ChipConfig);
1227 udelay(10);
1228
1229 writew(1, ioaddr + PGSEL);
1230 dspcfg = readw(ioaddr + DSPCFG);
1231 writew(0, ioaddr + PGSEL);
1232 if (np->dspcfg == dspcfg)
1233 break;
1234 }
1235
1236 if (netif_msg_link(np)) {
1237 if (i==NATSEMI_HW_TIMEOUT) {
1238 printk(KERN_INFO
1239 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1240 dev->name, i*10);
1241 } else {
1242 printk(KERN_INFO
1243 "%s: DSPCFG accepted after %d usec.\n",
1244 dev->name, i*10);
1245 }
1246 }
1247 /*
1248 * Enable PHY Specific event based interrupts. Link state change
1249 * and Auto-Negotiation Completion are among the affected.
1250 * Read the intr status to clear it (needed for wake events).
1251 */
1252 readw(ioaddr + MIntrStatus);
1253 writew(MICRIntEn, ioaddr + MIntrCtrl);
1254}
1255
1256static int switch_port_external(struct net_device *dev)
1257{
1258 struct netdev_private *np = netdev_priv(dev);
1259 void __iomem *ioaddr = ns_ioaddr(dev);
1260 u32 cfg;
1261
1262 cfg = readl(ioaddr + ChipConfig);
1263 if (cfg & CfgExtPhy)
1264 return 0;
1265
1266 if (netif_msg_link(np)) {
1267 printk(KERN_INFO "%s: switching to external transceiver.\n",
1268 dev->name);
1269 }
1270
1271 /* 1) switch back to external phy */
1272 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1273 readl(ioaddr + ChipConfig);
1274 udelay(1);
1275
1276 /* 2) reset the external phy: */
1277 /* resetting the external PHY has been known to cause a hub supplying
1278 * power over Ethernet to kill the power. We don't want to kill
1279 * power to this computer, so we avoid resetting the phy.
1280 */
1281
1282 /* 3) reinit the phy fixup, it got lost during power down. */
1283 move_int_phy(dev, np->phy_addr_external);
1284 init_phy_fixup(dev);
1285
1286 return 1;
1287}
1288
1289static int switch_port_internal(struct net_device *dev)
1290{
1291 struct netdev_private *np = netdev_priv(dev);
1292 void __iomem *ioaddr = ns_ioaddr(dev);
1293 int i;
1294 u32 cfg;
1295 u16 bmcr;
1296
1297 cfg = readl(ioaddr + ChipConfig);
1298 if (!(cfg &CfgExtPhy))
1299 return 0;
1300
1301 if (netif_msg_link(np)) {
1302 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1303 dev->name);
1304 }
1305 /* 1) switch back to internal phy: */
1306 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1307 writel(cfg, ioaddr + ChipConfig);
1308 readl(ioaddr + ChipConfig);
1309 udelay(1);
6aa20a22 1310
1da177e4
LT		 1311 /* 2) reset the internal phy: */
1312 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1313 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1314 readl(ioaddr + ChipConfig);
1315 udelay(10);
1316 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1317 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1318 if (!(bmcr & BMCR_RESET))
1319 break;
1320 udelay(10);
1321 }
1322 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1323 printk(KERN_INFO
1324 "%s: phy reset did not complete in %d usec.\n",
1325 dev->name, i*10);
1326 }
1327 /* 3) reinit the phy fixup, it got lost during power down. */
1328 init_phy_fixup(dev);
1329
1330 return 1;
1331}
1332
1333/* Scan for a PHY on the external mii bus.
1334 * There are two tricky points:
1335 * - Do not scan while the internal phy is enabled. The internal phy will
1336 * crash: e.g. reads from the DSPCFG register will return odd values and
1337 * the nasty random phy reset code will reset the nic every few seconds.
1338 * - The internal phy must be moved around, an external phy could
1339 * have the same address as the internal phy.
1340 */
1341static int find_mii(struct net_device *dev)
1342{
1343 struct netdev_private *np = netdev_priv(dev);
1344 int tmp;
1345 int i;
1346 int did_switch;
1347
1348 /* Switch to external phy */
1349 did_switch = switch_port_external(dev);
6aa20a22 1350
1da177e4
LT		 1351 /* Scan the possible phy addresses:
1352 *
1353 * PHY address 0 means that the phy is in isolate mode. Not yet
1354 * supported due to lack of test hardware. User space should
1355 * handle it through ethtool.
1356 */
1357 for (i = 1; i <= 31; i++) {
1358 move_int_phy(dev, i);
1359 tmp = miiport_read(dev, i, MII_BMSR);
1360 if (tmp != 0xffff && tmp != 0x0000) {
1361 /* found something! */
1362 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1363 + mdio_read(dev, MII_PHYSID2);
1364 if (netif_msg_probe(np)) {
1365 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1366 pci_name(np->pci_dev), np->mii, i);
1367 }
1368 break;
1369 }
1370 }
1371 /* And switch back to internal phy: */
1372 if (did_switch)
1373 switch_port_internal(dev);
1374 return i;
1375}
1376
1377/* CFG bits [13:16] [18:23] */
1378#define CFG_RESET_SAVE 0xfde000
1379/* WCSR bits [0:4] [9:10] */
1380#define WCSR_RESET_SAVE 0x61f
1381/* RFCR bits [20] [22] [27:31] */
1382#define RFCR_RESET_SAVE 0xf8500000;
1383
1384static void natsemi_reset(struct net_device *dev)
1385{
1386 int i;
1387 u32 cfg;
1388 u32 wcsr;
1389 u32 rfcr;
1390 u16 pmatch[3];
1391 u16 sopass[3];
1392 struct netdev_private *np = netdev_priv(dev);
1393 void __iomem *ioaddr = ns_ioaddr(dev);
1394
1395 /*
1396 * Resetting the chip causes some registers to be lost.
1397 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1398 * we save the state that would have been loaded from EEPROM
1399 * on a normal power-up (see the spec EEPROM map). This assumes
1400 * whoever calls this will follow up with init_registers() eventually.
1401 */
1402
1403 /* CFG */
1404 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1405 /* WCSR */
1406 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1407 /* RFCR */
1408 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1409 /* PMATCH */
1410 for (i = 0; i < 3; i++) {
1411 writel(i*2, ioaddr + RxFilterAddr);
1412 pmatch[i] = readw(ioaddr + RxFilterData);
1413 }
1414 /* SOPAS */
1415 for (i = 0; i < 3; i++) {
1416 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1417 sopass[i] = readw(ioaddr + RxFilterData);
1418 }
1419
1420 /* now whack the chip */
1421 writel(ChipReset, ioaddr + ChipCmd);
1422 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1423 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1424 break;
1425 udelay(5);
1426 }
1427 if (i==NATSEMI_HW_TIMEOUT) {
1428 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1429 dev->name, i*5);
1430 } else if (netif_msg_hw(np)) {
1431 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1432 dev->name, i*5);
1433 }
1434
1435 /* restore CFG */
1436 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1437 /* turn on external phy if it was selected */
1438 if (dev->if_port == PORT_TP)
1439 cfg &= ~(CfgExtPhy | CfgPhyDis);
1440 else
1441 cfg |= (CfgExtPhy | CfgPhyDis);
1442 writel(cfg, ioaddr + ChipConfig);
1443 /* restore WCSR */
1444 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1445 writel(wcsr, ioaddr + WOLCmd);
1446 /* read RFCR */
1447 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1448 /* restore PMATCH */
1449 for (i = 0; i < 3; i++) {
1450 writel(i*2, ioaddr + RxFilterAddr);
1451 writew(pmatch[i], ioaddr + RxFilterData);
1452 }
1453 for (i = 0; i < 3; i++) {
1454 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1455 writew(sopass[i], ioaddr + RxFilterData);
1456 }
1457 /* restore RFCR */
1458 writel(rfcr, ioaddr + RxFilterAddr);
1459}
1460
e72fd96e
MB		 1461static void reset_rx(struct net_device *dev)
1462{
1463 int i;
1464 struct netdev_private *np = netdev_priv(dev);
1465 void __iomem *ioaddr = ns_ioaddr(dev);
1466
1467 np->intr_status &= ~RxResetDone;
1468
1469 writel(RxReset, ioaddr + ChipCmd);
1470
1471 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1472 np->intr_status |= readl(ioaddr + IntrStatus);
1473 if (np->intr_status & RxResetDone)
1474 break;
1475 udelay(15);
1476 }
1477 if (i==NATSEMI_HW_TIMEOUT) {
1478 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n",
1479 dev->name, i*15);
1480 } else if (netif_msg_hw(np)) {
1481 printk(KERN_WARNING "%s: RX reset took %d usec.\n",
1482 dev->name, i*15);
1483 }
1484}
1485
1da177e4
LT		 1486static void natsemi_reload_eeprom(struct net_device *dev)
1487{
1488 struct netdev_private *np = netdev_priv(dev);
1489 void __iomem *ioaddr = ns_ioaddr(dev);
1490 int i;
1491
1492 writel(EepromReload, ioaddr + PCIBusCfg);
1493 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1494 udelay(50);
1495 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1496 break;
1497 }
1498 if (i==NATSEMI_HW_TIMEOUT) {
1499 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1500 pci_name(np->pci_dev), i*50);
1501 } else if (netif_msg_hw(np)) {
1502 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1503 pci_name(np->pci_dev), i*50);
1504 }
1505}
1506
1507static void natsemi_stop_rxtx(struct net_device *dev)
1508{
1509 void __iomem * ioaddr = ns_ioaddr(dev);
1510 struct netdev_private *np = netdev_priv(dev);
1511 int i;
1512
1513 writel(RxOff | TxOff, ioaddr + ChipCmd);
1514 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1515 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1516 break;
1517 udelay(5);
1518 }
1519 if (i==NATSEMI_HW_TIMEOUT) {
1520 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1521 dev->name, i*5);
1522 } else if (netif_msg_hw(np)) {
1523 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1524 dev->name, i*5);
1525 }
1526}
1527
1528static int netdev_open(struct net_device *dev)
1529{
1530 struct netdev_private *np = netdev_priv(dev);
1531 void __iomem * ioaddr = ns_ioaddr(dev);
1532 int i;
1533
1534 /* Reset the chip, just in case. */
1535 natsemi_reset(dev);
1536
a0607fd3 1537 i = request_irq(dev->irq, intr_handler, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1538 if (i) return i;
1539
1540 if (netif_msg_ifup(np))
1541 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1542 dev->name, dev->irq);
1543 i = alloc_ring(dev);
1544 if (i < 0) {
1545 free_irq(dev->irq, dev);
1546 return i;
1547 }
bea3348e
SH		 1548 napi_enable(&np->napi);
1549
1da177e4
LT		 1550 init_ring(dev);
1551 spin_lock_irq(&np->lock);
1552 init_registers(dev);
1553 /* now set the MAC address according to dev->dev_addr */
1554 for (i = 0; i < 3; i++) {
1555 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1556
1557 writel(i*2, ioaddr + RxFilterAddr);
1558 writew(mac, ioaddr + RxFilterData);
1559 }
1560 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1561 spin_unlock_irq(&np->lock);
1562
1563 netif_start_queue(dev);
1564
1565 if (netif_msg_ifup(np))
1566 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1567 dev->name, (int)readl(ioaddr + ChipCmd));
1568
1569 /* Set the timer to check for link beat. */
1570 init_timer(&np->timer);
0e5d5442 1571 np->timer.expires = round_jiffies(jiffies + NATSEMI_TIMER_FREQ);
1da177e4 1572 np->timer.data = (unsigned long)dev;
c061b18d 1573 np->timer.function = netdev_timer; /* timer handler */
1da177e4
LT		 1574 add_timer(&np->timer);
1575
1576 return 0;
1577}
1578
1579static void do_cable_magic(struct net_device *dev)
1580{
1581 struct netdev_private *np = netdev_priv(dev);
1582 void __iomem *ioaddr = ns_ioaddr(dev);
1583
1584 if (dev->if_port != PORT_TP)
1585 return;
1586
1587 if (np->srr >= SRR_DP83816_A5)
1588 return;
1589
1590 /*
1591 * 100 MBit links with short cables can trip an issue with the chip.
1592 * The problem manifests as lots of CRC errors and/or flickering
1593 * activity LED while idle. This process is based on instructions
1594 * from engineers at National.
1595 */
1596 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1597 u16 data;
1598
1599 writew(1, ioaddr + PGSEL);
1600 /*
1601 * coefficient visibility should already be enabled via
1602 * DSPCFG | 0x1000
1603 */
1604 data = readw(ioaddr + TSTDAT) & 0xff;
1605 /*
1606 * the value must be negative, and within certain values
1607 * (these values all come from National)
1608 */
1609 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
ddfce6bb 1610 np = netdev_priv(dev);
1da177e4
LT		 1611
1612 /* the bug has been triggered - fix the coefficient */
1613 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1614 /* lock the value */
1615 data = readw(ioaddr + DSPCFG);
1616 np->dspcfg = data | DSPCFG_LOCK;
1617 writew(np->dspcfg, ioaddr + DSPCFG);
1618 }
1619 writew(0, ioaddr + PGSEL);
1620 }
1621}
1622
1623static void undo_cable_magic(struct net_device *dev)
1624{
1625 u16 data;
1626 struct netdev_private *np = netdev_priv(dev);
1627 void __iomem * ioaddr = ns_ioaddr(dev);
1628
1629 if (dev->if_port != PORT_TP)
1630 return;
1631
1632 if (np->srr >= SRR_DP83816_A5)
1633 return;
1634
1635 writew(1, ioaddr + PGSEL);
1636 /* make sure the lock bit is clear */
1637 data = readw(ioaddr + DSPCFG);
1638 np->dspcfg = data & ~DSPCFG_LOCK;
1639 writew(np->dspcfg, ioaddr + DSPCFG);
1640 writew(0, ioaddr + PGSEL);
1641}
1642
1643static void check_link(struct net_device *dev)
1644{
1645 struct netdev_private *np = netdev_priv(dev);
1646 void __iomem * ioaddr = ns_ioaddr(dev);
68c90166 1647 int duplex = np->duplex;
1da177e4 1648 u16 bmsr;
6aa20a22 1649
68c90166
MB		 1650 /* If we are ignoring the PHY then don't try reading it. */
1651 if (np->ignore_phy)
1652 goto propagate_state;
1653
1da177e4
LT		 1654 /* The link status field is latched: it remains low after a temporary
1655 * link failure until it's read. We need the current link status,
1656 * thus read twice.
1657 */
1658 mdio_read(dev, MII_BMSR);
1659 bmsr = mdio_read(dev, MII_BMSR);
1660
1661 if (!(bmsr & BMSR_LSTATUS)) {
1662 if (netif_carrier_ok(dev)) {
1663 if (netif_msg_link(np))
1664 printk(KERN_NOTICE "%s: link down.\n",
68c90166 1665 dev->name);
1da177e4
LT		 1666 netif_carrier_off(dev);
1667 undo_cable_magic(dev);
1668 }
1669 return;
1670 }
1671 if (!netif_carrier_ok(dev)) {
1672 if (netif_msg_link(np))
1673 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1674 netif_carrier_on(dev);
1675 do_cable_magic(dev);
1676 }
1677
1678 duplex = np->full_duplex;
1679 if (!duplex) {
1680 if (bmsr & BMSR_ANEGCOMPLETE) {
1681 int tmp = mii_nway_result(
1682 np->advertising & mdio_read(dev, MII_LPA));
1683 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1684 duplex = 1;
1685 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1686 duplex = 1;
1687 }
1688
68c90166 1689propagate_state:
1da177e4
LT		 1690 /* if duplex is set then bit 28 must be set, too */
1691 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1692 if (netif_msg_link(np))
1693 printk(KERN_INFO
1694 "%s: Setting %s-duplex based on negotiated "
1695 "link capability.\n", dev->name,
1696 duplex ? "full" : "half");
1697 if (duplex) {
1698 np->rx_config |= RxAcceptTx;
1699 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1700 } else {
1701 np->rx_config &= ~RxAcceptTx;
1702 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1703 }
1704 writel(np->tx_config, ioaddr + TxConfig);
1705 writel(np->rx_config, ioaddr + RxConfig);
1706 }
1707}
1708
1709static void init_registers(struct net_device *dev)
1710{
1711 struct netdev_private *np = netdev_priv(dev);
1712 void __iomem * ioaddr = ns_ioaddr(dev);
1713
1714 init_phy_fixup(dev);
1715
1716 /* clear any interrupts that are pending, such as wake events */
1717 readl(ioaddr + IntrStatus);
1718
1719 writel(np->ring_dma, ioaddr + RxRingPtr);
1720 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1721 ioaddr + TxRingPtr);
1722
1723 /* Initialize other registers.
1724 * Configure the PCI bus bursts and FIFO thresholds.
1725 * Configure for standard, in-spec Ethernet.
1726 * Start with half-duplex. check_link will update
1727 * to the correct settings.
1728 */
1729
1730 /* DRTH: 2: start tx if 64 bytes are in the fifo
1731 * FLTH: 0x10: refill with next packet if 512 bytes are free
1732 * MXDMA: 0: up to 256 byte bursts.
1733 * MXDMA must be <= FLTH
1734 * ECRETRY=1
1735 * ATP=1
1736 */
1737 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1738 TX_FLTH_VAL | TX_DRTH_VAL_START;
1739 writel(np->tx_config, ioaddr + TxConfig);
1740
1741 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1742 * MXDMA 0: up to 256 byte bursts
1743 */
1744 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1745 /* if receive ring now has bigger buffers than normal, enable jumbo */
1746 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1747 np->rx_config |= RxAcceptLong;
1748
1749 writel(np->rx_config, ioaddr + RxConfig);
1750
1751 /* Disable PME:
1752 * The PME bit is initialized from the EEPROM contents.
1753 * PCI cards probably have PME disabled, but motherboard
1754 * implementations may have PME set to enable WakeOnLan.
1755 * With PME set the chip will scan incoming packets but
1756 * nothing will be written to memory. */
1757 np->SavedClkRun = readl(ioaddr + ClkRun);
1758 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1759 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1760 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1761 dev->name, readl(ioaddr + WOLCmd));
1762 }
1763
1764 check_link(dev);
1765 __set_rx_mode(dev);
1766
1767 /* Enable interrupts by setting the interrupt mask. */
1768 writel(DEFAULT_INTR, ioaddr + IntrMask);
14fdd90e 1769 natsemi_irq_enable(dev);
1da177e4
LT		 1770
1771 writel(RxOn | TxOn, ioaddr + ChipCmd);
1772 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1773}
1774
1775/*
1776 * netdev_timer:
1777 * Purpose:
1778 * 1) check for link changes. Usually they are handled by the MII interrupt
1779 * but it doesn't hurt to check twice.
1780 * 2) check for sudden death of the NIC:
1781 * It seems that a reference set for this chip went out with incorrect info,
1782 * and there exist boards that aren't quite right. An unexpected voltage
1783 * drop can cause the PHY to get itself in a weird state (basically reset).
1a147809
MB		 1784 * NOTE: this only seems to affect revC chips. The user can disable
1785 * this check via dspcfg_workaround sysfs option.
1da177e4
LT		 1786 * 3) check of death of the RX path due to OOM
1787 */
1788static void netdev_timer(unsigned long data)
1789{
1790 struct net_device *dev = (struct net_device *)data;
1791 struct netdev_private *np = netdev_priv(dev);
1792 void __iomem * ioaddr = ns_ioaddr(dev);
f2cade13 1793 int next_tick = NATSEMI_TIMER_FREQ;
1da177e4
LT		 1794
1795 if (netif_msg_timer(np)) {
1796 /* DO NOT read the IntrStatus register,
1797 * a read clears any pending interrupts.
1798 */
1799 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1800 dev->name);
1801 }
1802
1803 if (dev->if_port == PORT_TP) {
1804 u16 dspcfg;
1805
1806 spin_lock_irq(&np->lock);
1807 /* check for a nasty random phy-reset - use dspcfg as a flag */
1808 writew(1, ioaddr+PGSEL);
1809 dspcfg = readw(ioaddr+DSPCFG);
1810 writew(0, ioaddr+PGSEL);
1a147809 1811 if (np->dspcfg_workaround && dspcfg != np->dspcfg) {
1da177e4
LT		 1812 if (!netif_queue_stopped(dev)) {
1813 spin_unlock_irq(&np->lock);
d0ed4864 1814 if (netif_msg_drv(np))
1da177e4
LT		 1815 printk(KERN_NOTICE "%s: possible phy reset: "
1816 "re-initializing\n", dev->name);
1817 disable_irq(dev->irq);
1818 spin_lock_irq(&np->lock);
1819 natsemi_stop_rxtx(dev);
1820 dump_ring(dev);
1821 reinit_ring(dev);
1822 init_registers(dev);
1823 spin_unlock_irq(&np->lock);
1824 enable_irq(dev->irq);
1825 } else {
1826 /* hurry back */
1827 next_tick = HZ;
1828 spin_unlock_irq(&np->lock);
1829 }
1830 } else {
1831 /* init_registers() calls check_link() for the above case */
1832 check_link(dev);
1833 spin_unlock_irq(&np->lock);
1834 }
1835 } else {
1836 spin_lock_irq(&np->lock);
1837 check_link(dev);
1838 spin_unlock_irq(&np->lock);
1839 }
1840 if (np->oom) {
1841 disable_irq(dev->irq);
1842 np->oom = 0;
1843 refill_rx(dev);
1844 enable_irq(dev->irq);
1845 if (!np->oom) {
1846 writel(RxOn, ioaddr + ChipCmd);
1847 } else {
1848 next_tick = 1;
1849 }
1850 }
0e5d5442
MB		 1851
1852 if (next_tick > 1)
1853 mod_timer(&np->timer, round_jiffies(jiffies + next_tick));
1854 else
1855 mod_timer(&np->timer, jiffies + next_tick);
1da177e4
LT		 1856}
1857
1858static void dump_ring(struct net_device *dev)
1859{
1860 struct netdev_private *np = netdev_priv(dev);
1861
1862 if (netif_msg_pktdata(np)) {
1863 int i;
1864 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1865 for (i = 0; i < TX_RING_SIZE; i++) {
1866 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1867 i, np->tx_ring[i].next_desc,
1868 np->tx_ring[i].cmd_status,
1869 np->tx_ring[i].addr);
1870 }
1871 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1872 for (i = 0; i < RX_RING_SIZE; i++) {
1873 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1874 i, np->rx_ring[i].next_desc,
1875 np->rx_ring[i].cmd_status,
1876 np->rx_ring[i].addr);
1877 }
1878 }
1879}
1880
ed4cb133 1881static void ns_tx_timeout(struct net_device *dev)
1da177e4
LT		 1882{
1883 struct netdev_private *np = netdev_priv(dev);
1884 void __iomem * ioaddr = ns_ioaddr(dev);
1885
1886 disable_irq(dev->irq);
1887 spin_lock_irq(&np->lock);
1888 if (!np->hands_off) {
1889 if (netif_msg_tx_err(np))
1890 printk(KERN_WARNING
1891 "%s: Transmit timed out, status %#08x,"
1892 " resetting...\n",
1893 dev->name, readl(ioaddr + IntrStatus));
1894 dump_ring(dev);
1895
1896 natsemi_reset(dev);
1897 reinit_ring(dev);
1898 init_registers(dev);
1899 } else {
1900 printk(KERN_WARNING
1901 "%s: tx_timeout while in hands_off state?\n",
1902 dev->name);
1903 }
1904 spin_unlock_irq(&np->lock);
1905 enable_irq(dev->irq);
1906
1ae5dc34 1907 dev->trans_start = jiffies; /* prevent tx timeout */
2321e80a 1908 dev->stats.tx_errors++;
1da177e4
LT		 1909 netif_wake_queue(dev);
1910}
1911
1912static int alloc_ring(struct net_device *dev)
1913{
1914 struct netdev_private *np = netdev_priv(dev);
1915 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1916 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1917 &np->ring_dma);
1918 if (!np->rx_ring)
1919 return -ENOMEM;
1920 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1921 return 0;
1922}
1923
1924static void refill_rx(struct net_device *dev)
1925{
1926 struct netdev_private *np = netdev_priv(dev);
1927
1928 /* Refill the Rx ring buffers. */
1929 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1930 struct sk_buff *skb;
1931 int entry = np->dirty_rx % RX_RING_SIZE;
1932 if (np->rx_skbuff[entry] == NULL) {
1933 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1934 skb = dev_alloc_skb(buflen);
1935 np->rx_skbuff[entry] = skb;
1936 if (skb == NULL)
1937 break; /* Better luck next round. */
1938 skb->dev = dev; /* Mark as being used by this device. */
1939 np->rx_dma[entry] = pci_map_single(np->pci_dev,
689be439 1940 skb->data, buflen, PCI_DMA_FROMDEVICE);
1da177e4
LT		 1941 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1942 }
1943 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1944 }
1945 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1946 if (netif_msg_rx_err(np))
1947 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1948 np->oom = 1;
1949 }
1950}
1951
1952static void set_bufsize(struct net_device *dev)
1953{
1954 struct netdev_private *np = netdev_priv(dev);
1955 if (dev->mtu <= ETH_DATA_LEN)
1956 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1957 else
1958 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1959}
1960
1961/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1962static void init_ring(struct net_device *dev)
1963{
1964 struct netdev_private *np = netdev_priv(dev);
1965 int i;
1966
1967 /* 1) TX ring */
1968 np->dirty_tx = np->cur_tx = 0;
1969 for (i = 0; i < TX_RING_SIZE; i++) {
1970 np->tx_skbuff[i] = NULL;
1971 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1972 +sizeof(struct netdev_desc)
1973 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1974 np->tx_ring[i].cmd_status = 0;
1975 }
1976
1977 /* 2) RX ring */
1978 np->dirty_rx = 0;
1979 np->cur_rx = RX_RING_SIZE;
1980 np->oom = 0;
1981 set_bufsize(dev);
1982
1983 np->rx_head_desc = &np->rx_ring[0];
1984
1985 /* Please be carefull before changing this loop - at least gcc-2.95.1
1986 * miscompiles it otherwise.
1987 */
1988 /* Initialize all Rx descriptors. */
1989 for (i = 0; i < RX_RING_SIZE; i++) {
1990 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1991 +sizeof(struct netdev_desc)
1992 *((i+1)%RX_RING_SIZE));
1993 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
1994 np->rx_skbuff[i] = NULL;
1995 }
1996 refill_rx(dev);
1997 dump_ring(dev);
1998}
1999
2000static void drain_tx(struct net_device *dev)
2001{
2002 struct netdev_private *np = netdev_priv(dev);
2003 int i;
2004
2005 for (i = 0; i < TX_RING_SIZE; i++) {
2006 if (np->tx_skbuff[i]) {
2007 pci_unmap_single(np->pci_dev,
2008 np->tx_dma[i], np->tx_skbuff[i]->len,
2009 PCI_DMA_TODEVICE);
2010 dev_kfree_skb(np->tx_skbuff[i]);
2321e80a 2011 dev->stats.tx_dropped++;
1da177e4
LT		 2012 }
2013 np->tx_skbuff[i] = NULL;
2014 }
2015}
2016
2017static void drain_rx(struct net_device *dev)
2018{
2019 struct netdev_private *np = netdev_priv(dev);
2020 unsigned int buflen = np->rx_buf_sz;
2021 int i;
2022
2023 /* Free all the skbuffs in the Rx queue. */
2024 for (i = 0; i < RX_RING_SIZE; i++) {
2025 np->rx_ring[i].cmd_status = 0;
eca1ad82 2026 np->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1da177e4
LT		 2027 if (np->rx_skbuff[i]) {
2028 pci_unmap_single(np->pci_dev,
2029 np->rx_dma[i], buflen,
2030 PCI_DMA_FROMDEVICE);
2031 dev_kfree_skb(np->rx_skbuff[i]);
2032 }
2033 np->rx_skbuff[i] = NULL;
2034 }
2035}
2036
2037static void drain_ring(struct net_device *dev)
2038{
2039 drain_rx(dev);
2040 drain_tx(dev);
2041}
2042
2043static void free_ring(struct net_device *dev)
2044{
2045 struct netdev_private *np = netdev_priv(dev);
2046 pci_free_consistent(np->pci_dev,
2047 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2048 np->rx_ring, np->ring_dma);
2049}
2050
2051static void reinit_rx(struct net_device *dev)
2052{
2053 struct netdev_private *np = netdev_priv(dev);
2054 int i;
2055
2056 /* RX Ring */
2057 np->dirty_rx = 0;
2058 np->cur_rx = RX_RING_SIZE;
2059 np->rx_head_desc = &np->rx_ring[0];
2060 /* Initialize all Rx descriptors. */
2061 for (i = 0; i < RX_RING_SIZE; i++)
2062 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2063
2064 refill_rx(dev);
2065}
2066
2067static void reinit_ring(struct net_device *dev)
2068{
2069 struct netdev_private *np = netdev_priv(dev);
2070 int i;
2071
2072 /* drain TX ring */
2073 drain_tx(dev);
2074 np->dirty_tx = np->cur_tx = 0;
2075 for (i=0;i<TX_RING_SIZE;i++)
2076 np->tx_ring[i].cmd_status = 0;
2077
2078 reinit_rx(dev);
2079}
2080
61357325 2081static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 2082{
2083 struct netdev_private *np = netdev_priv(dev);
2084 void __iomem * ioaddr = ns_ioaddr(dev);
2085 unsigned entry;
6006f7f5 2086 unsigned long flags;
1da177e4
LT		 2087
2088 /* Note: Ordering is important here, set the field with the
2089 "ownership" bit last, and only then increment cur_tx. */
2090
2091 /* Calculate the next Tx descriptor entry. */
2092 entry = np->cur_tx % TX_RING_SIZE;
2093
2094 np->tx_skbuff[entry] = skb;
2095 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2096 skb->data,skb->len, PCI_DMA_TODEVICE);
2097
2098 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2099
6006f7f5 2100 spin_lock_irqsave(&np->lock, flags);
1da177e4
LT		 2101
2102 if (!np->hands_off) {
2103 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2104 /* StrongARM: Explicitly cache flush np->tx_ring and
2105 * skb->data,skb->len. */
2106 wmb();
2107 np->cur_tx++;
2108 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2109 netdev_tx_done(dev);
2110 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2111 netif_stop_queue(dev);
2112 }
2113 /* Wake the potentially-idle transmit channel. */
2114 writel(TxOn, ioaddr + ChipCmd);
2115 } else {
2116 dev_kfree_skb_irq(skb);
2321e80a 2117 dev->stats.tx_dropped++;
1da177e4 2118 }
6006f7f5 2119 spin_unlock_irqrestore(&np->lock, flags);
1da177e4 2120
1da177e4
LT		 2121 if (netif_msg_tx_queued(np)) {
2122 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2123 dev->name, np->cur_tx, entry);
2124 }
6ed10654 2125 return NETDEV_TX_OK;
1da177e4
LT		 2126}
2127
2128static void netdev_tx_done(struct net_device *dev)
2129{
2130 struct netdev_private *np = netdev_priv(dev);
2131
2132 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2133 int entry = np->dirty_tx % TX_RING_SIZE;
2134 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2135 break;
2136 if (netif_msg_tx_done(np))
2137 printk(KERN_DEBUG
2138 "%s: tx frame #%d finished, status %#08x.\n",
2139 dev->name, np->dirty_tx,
2140 le32_to_cpu(np->tx_ring[entry].cmd_status));
2141 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2321e80a
KV		 2142 dev->stats.tx_packets++;
2143 dev->stats.tx_bytes += np->tx_skbuff[entry]->len;
1da177e4
LT		 2144 } else { /* Various Tx errors */
2145 int tx_status =
2146 le32_to_cpu(np->tx_ring[entry].cmd_status);
2147 if (tx_status & (DescTxAbort|DescTxExcColl))
2321e80a 2148 dev->stats.tx_aborted_errors++;
1da177e4 2149 if (tx_status & DescTxFIFO)
2321e80a 2150 dev->stats.tx_fifo_errors++;
1da177e4 2151 if (tx_status & DescTxCarrier)
2321e80a 2152 dev->stats.tx_carrier_errors++;
1da177e4 2153 if (tx_status & DescTxOOWCol)
2321e80a
KV		 2154 dev->stats.tx_window_errors++;
2155 dev->stats.tx_errors++;
1da177e4
LT		 2156 }
2157 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2158 np->tx_skbuff[entry]->len,
2159 PCI_DMA_TODEVICE);
2160 /* Free the original skb. */
2161 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2162 np->tx_skbuff[entry] = NULL;
2163 }
8e95a202
JP		 2164 if (netif_queue_stopped(dev) &&
2165 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
1da177e4
LT		 2166 /* The ring is no longer full, wake queue. */
2167 netif_wake_queue(dev);
2168 }
2169}
2170
b27a16b7
MB		 2171/* The interrupt handler doesn't actually handle interrupts itself, it
2172 * schedules a NAPI poll if there is anything to do. */
7d12e780 2173static irqreturn_t intr_handler(int irq, void *dev_instance)
1da177e4
LT		 2174{
2175 struct net_device *dev = dev_instance;
2176 struct netdev_private *np = netdev_priv(dev);
2177 void __iomem * ioaddr = ns_ioaddr(dev);
1da177e4 2178
069f8256
MB		 2179 /* Reading IntrStatus automatically acknowledges so don't do
2180 * that while interrupts are disabled, (for example, while a
2181 * poll is scheduled). */
2182 if (np->hands_off || !readl(ioaddr + IntrEnable))
1da177e4 2183 return IRQ_NONE;
6aa20a22 2184
b27a16b7 2185 np->intr_status = readl(ioaddr + IntrStatus);
1da177e4 2186
069f8256
MB		 2187 if (!np->intr_status)
2188 return IRQ_NONE;
2189
b27a16b7
MB		 2190 if (netif_msg_intr(np))
2191 printk(KERN_DEBUG
2192 "%s: Interrupt, status %#08x, mask %#08x.\n",
2193 dev->name, np->intr_status,
2194 readl(ioaddr + IntrMask));
1da177e4 2195
b27a16b7
MB		 2196 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
2197
288379f0 2198 if (napi_schedule_prep(&np->napi)) {
b27a16b7
MB		 2199 /* Disable interrupts and register for poll */
2200 natsemi_irq_disable(dev);
288379f0 2201 __napi_schedule(&np->napi);
069f8256
MB		 2202 } else
2203 printk(KERN_WARNING
2204 "%s: Ignoring interrupt, status %#08x, mask %#08x.\n",
2205 dev->name, np->intr_status,
2206 readl(ioaddr + IntrMask));
2207
b27a16b7
MB		 2208 return IRQ_HANDLED;
2209}
2210
2211/* This is the NAPI poll routine. As well as the standard RX handling
2212 * it also handles all other interrupts that the chip might raise.
2213 */
bea3348e 2214static int natsemi_poll(struct napi_struct *napi, int budget)
b27a16b7 2215{
bea3348e
SH		 2216 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
2217 struct net_device *dev = np->dev;
b27a16b7 2218 void __iomem * ioaddr = ns_ioaddr(dev);
b27a16b7
MB		 2219 int work_done = 0;
2220
2221 do {
069f8256
MB		 2222 if (netif_msg_intr(np))
2223 printk(KERN_DEBUG
2224 "%s: Poll, status %#08x, mask %#08x.\n",
2225 dev->name, np->intr_status,
2226 readl(ioaddr + IntrMask));
2227
d2a90036
MB		 2228 /* netdev_rx() may read IntrStatus again if the RX state
2229 * machine falls over so do it first. */
2230 if (np->intr_status &
2231 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2232 IntrRxErr | IntrRxOverrun)) {
bea3348e 2233 netdev_rx(dev, &work_done, budget);
d2a90036
MB		 2234 }
2235
b27a16b7
MB		 2236 if (np->intr_status &
2237 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
1da177e4
LT		 2238 spin_lock(&np->lock);
2239 netdev_tx_done(dev);
2240 spin_unlock(&np->lock);
2241 }
2242
2243 /* Abnormal error summary/uncommon events handlers. */
b27a16b7
MB		 2244 if (np->intr_status & IntrAbnormalSummary)
2245 netdev_error(dev, np->intr_status);
6aa20a22 2246
bea3348e
SH		 2247 if (work_done >= budget)
2248 return work_done;
b27a16b7
MB		 2249
2250 np->intr_status = readl(ioaddr + IntrStatus);
2251 } while (np->intr_status);
1da177e4 2252
288379f0 2253 napi_complete(napi);
b27a16b7
MB		 2254
2255 /* Reenable interrupts providing nothing is trying to shut
2256 * the chip down. */
2257 spin_lock(&np->lock);
4ec24119 2258 if (!np->hands_off)
b27a16b7
MB		 2259 natsemi_irq_enable(dev);
2260 spin_unlock(&np->lock);
2261
bea3348e 2262 return work_done;
1da177e4
LT		 2263}
2264
2265/* This routine is logically part of the interrupt handler, but separated
2266 for clarity and better register allocation. */
b27a16b7 2267static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
1da177e4
LT		 2268{
2269 struct netdev_private *np = netdev_priv(dev);
2270 int entry = np->cur_rx % RX_RING_SIZE;
2271 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2272 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2273 unsigned int buflen = np->rx_buf_sz;
2274 void __iomem * ioaddr = ns_ioaddr(dev);
2275
2276 /* If the driver owns the next entry it's a new packet. Send it up. */
2277 while (desc_status < 0) { /* e.g. & DescOwn */
2278 int pkt_len;
2279 if (netif_msg_rx_status(np))
2280 printk(KERN_DEBUG
2281 " netdev_rx() entry %d status was %#08x.\n",
2282 entry, desc_status);
2283 if (--boguscnt < 0)
2284 break;
b27a16b7
MB		 2285
2286 if (*work_done >= work_to_do)
2287 break;
2288
2289 (*work_done)++;
2290
1da177e4
LT		 2291 pkt_len = (desc_status & DescSizeMask) - 4;
2292 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2293 if (desc_status & DescMore) {
6006f7f5
SS		 2294 unsigned long flags;
2295
1da177e4
LT		 2296 if (netif_msg_rx_err(np))
2297 printk(KERN_WARNING
2298 "%s: Oversized(?) Ethernet "
2299 "frame spanned multiple "
2300 "buffers, entry %#08x "
2301 "status %#08x.\n", dev->name,
2302 np->cur_rx, desc_status);
2321e80a 2303 dev->stats.rx_length_errors++;
e72fd96e
MB		 2304
2305 /* The RX state machine has probably
2306 * locked up beneath us. Follow the
2307 * reset procedure documented in
2308 * AN-1287. */
2309
6006f7f5 2310 spin_lock_irqsave(&np->lock, flags);
e72fd96e
MB		 2311 reset_rx(dev);
2312 reinit_rx(dev);
2313 writel(np->ring_dma, ioaddr + RxRingPtr);
2314 check_link(dev);
6006f7f5 2315 spin_unlock_irqrestore(&np->lock, flags);
e72fd96e
MB		 2316
2317 /* We'll enable RX on exit from this
2318 * function. */
2319 break;
2320
1da177e4
LT		 2321 } else {
2322 /* There was an error. */
2321e80a 2323 dev->stats.rx_errors++;
1da177e4 2324 if (desc_status & (DescRxAbort|DescRxOver))
2321e80a 2325 dev->stats.rx_over_errors++;
1da177e4 2326 if (desc_status & (DescRxLong|DescRxRunt))
2321e80a 2327 dev->stats.rx_length_errors++;
1da177e4 2328 if (desc_status & (DescRxInvalid|DescRxAlign))
2321e80a 2329 dev->stats.rx_frame_errors++;
1da177e4 2330 if (desc_status & DescRxCRC)
2321e80a 2331 dev->stats.rx_crc_errors++;
1da177e4
LT		 2332 }
2333 } else if (pkt_len > np->rx_buf_sz) {
2334 /* if this is the tail of a double buffer
2335 * packet, we've already counted the error
2336 * on the first part. Ignore the second half.
2337 */
2338 } else {
2339 struct sk_buff *skb;
2340 /* Omit CRC size. */
2341 /* Check if the packet is long enough to accept
2342 * without copying to a minimally-sized skbuff. */
8e95a202
JP		 2343 if (pkt_len < rx_copybreak &&
2344 (skb = dev_alloc_skb(pkt_len + RX_OFFSET)) != NULL) {
1da177e4
LT		 2345 /* 16 byte align the IP header */
2346 skb_reserve(skb, RX_OFFSET);
2347 pci_dma_sync_single_for_cpu(np->pci_dev,
2348 np->rx_dma[entry],
2349 buflen,
2350 PCI_DMA_FROMDEVICE);
8c7b7faa
DM		 2351 skb_copy_to_linear_data(skb,
2352 np->rx_skbuff[entry]->data, pkt_len);
1da177e4
LT		 2353 skb_put(skb, pkt_len);
2354 pci_dma_sync_single_for_device(np->pci_dev,
2355 np->rx_dma[entry],
2356 buflen,
2357 PCI_DMA_FROMDEVICE);
2358 } else {
2359 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2360 buflen, PCI_DMA_FROMDEVICE);
2361 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2362 np->rx_skbuff[entry] = NULL;
2363 }
2364 skb->protocol = eth_type_trans(skb, dev);
b27a16b7 2365 netif_receive_skb(skb);
2321e80a
KV		 2366 dev->stats.rx_packets++;
2367 dev->stats.rx_bytes += pkt_len;
1da177e4
LT		 2368 }
2369 entry = (++np->cur_rx) % RX_RING_SIZE;
2370 np->rx_head_desc = &np->rx_ring[entry];
2371 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2372 }
2373 refill_rx(dev);
2374
2375 /* Restart Rx engine if stopped. */
2376 if (np->oom)
2377 mod_timer(&np->timer, jiffies + 1);
2378 else
2379 writel(RxOn, ioaddr + ChipCmd);
2380}
2381
2382static void netdev_error(struct net_device *dev, int intr_status)
2383{
2384 struct netdev_private *np = netdev_priv(dev);
2385 void __iomem * ioaddr = ns_ioaddr(dev);
2386
2387 spin_lock(&np->lock);
2388 if (intr_status & LinkChange) {
2389 u16 lpa = mdio_read(dev, MII_LPA);
8e95a202
JP		 2390 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE &&
2391 netif_msg_link(np)) {
1da177e4
LT		 2392 printk(KERN_INFO
2393 "%s: Autonegotiation advertising"
2394 " %#04x partner %#04x.\n", dev->name,
2395 np->advertising, lpa);
2396 }
2397
2398 /* read MII int status to clear the flag */
2399 readw(ioaddr + MIntrStatus);
2400 check_link(dev);
2401 }
2402 if (intr_status & StatsMax) {
2403 __get_stats(dev);
2404 }
2405 if (intr_status & IntrTxUnderrun) {
2406 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2407 np->tx_config += TX_DRTH_VAL_INC;
2408 if (netif_msg_tx_err(np))
2409 printk(KERN_NOTICE
2410 "%s: increased tx threshold, txcfg %#08x.\n",
2411 dev->name, np->tx_config);
2412 } else {
2413 if (netif_msg_tx_err(np))
2414 printk(KERN_NOTICE
2415 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2416 dev->name, np->tx_config);
2417 }
2418 writel(np->tx_config, ioaddr + TxConfig);
2419 }
2420 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2421 int wol_status = readl(ioaddr + WOLCmd);
2422 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2423 dev->name, wol_status);
2424 }
2425 if (intr_status & RxStatusFIFOOver) {
2426 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2427 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2428 dev->name);
2429 }
2321e80a
KV		 2430 dev->stats.rx_fifo_errors++;
2431 dev->stats.rx_errors++;
1da177e4
LT		 2432 }
2433 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2434 if (intr_status & IntrPCIErr) {
2435 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2436 intr_status & IntrPCIErr);
2321e80a
KV		 2437 dev->stats.tx_fifo_errors++;
2438 dev->stats.tx_errors++;
2439 dev->stats.rx_fifo_errors++;
2440 dev->stats.rx_errors++;
1da177e4
LT		 2441 }
2442 spin_unlock(&np->lock);
2443}
2444
2445static void __get_stats(struct net_device *dev)
2446{
2447 void __iomem * ioaddr = ns_ioaddr(dev);
1da177e4
LT		 2448
2449 /* The chip only need report frame silently dropped. */
2321e80a
KV		 2450 dev->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2451 dev->stats.rx_missed_errors += readl(ioaddr + RxMissed);
1da177e4
LT		 2452}
2453
2454static struct net_device_stats *get_stats(struct net_device *dev)
2455{
2456 struct netdev_private *np = netdev_priv(dev);
2457
2458 /* The chip only need report frame silently dropped. */
2459 spin_lock_irq(&np->lock);
2460 if (netif_running(dev) && !np->hands_off)
2461 __get_stats(dev);
2462 spin_unlock_irq(&np->lock);
2463
2321e80a 2464 return &dev->stats;
1da177e4
LT		 2465}
2466
2467#ifdef CONFIG_NET_POLL_CONTROLLER
2468static void natsemi_poll_controller(struct net_device *dev)
2469{
2470 disable_irq(dev->irq);
069f8256 2471 intr_handler(dev->irq, dev);
1da177e4
LT		 2472 enable_irq(dev->irq);
2473}
2474#endif
2475
2476#define HASH_TABLE 0x200
2477static void __set_rx_mode(struct net_device *dev)
2478{
2479 void __iomem * ioaddr = ns_ioaddr(dev);
2480 struct netdev_private *np = netdev_priv(dev);
2481 u8 mc_filter[64]; /* Multicast hash filter */
2482 u32 rx_mode;
2483
2484 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4
LT		 2485 rx_mode = RxFilterEnable | AcceptBroadcast
2486 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
4cd24eaf 2487 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 2488 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 2489 rx_mode = RxFilterEnable | AcceptBroadcast
2490 | AcceptAllMulticast | AcceptMyPhys;
2491 } else {
22bedad3 2492 struct netdev_hw_addr *ha;
1da177e4 2493 int i;
f9dcbcc9 2494
1da177e4 2495 memset(mc_filter, 0, sizeof(mc_filter));
22bedad3
JP		 2496 netdev_for_each_mc_addr(ha, dev) {
2497 int b = (ether_crc(ETH_ALEN, ha->addr) >> 23) & 0x1ff;
ddfce6bb 2498 mc_filter[b/8] |= (1 << (b & 0x07));
1da177e4
LT		 2499 }
2500 rx_mode = RxFilterEnable | AcceptBroadcast
2501 | AcceptMulticast | AcceptMyPhys;
2502 for (i = 0; i < 64; i += 2) {
760f86d7
HX		 2503 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2504 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2505 ioaddr + RxFilterData);
1da177e4
LT		 2506 }
2507 }
2508 writel(rx_mode, ioaddr + RxFilterAddr);
2509 np->cur_rx_mode = rx_mode;
2510}
2511
2512static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2513{
2514 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS)
2515 return -EINVAL;
2516
2517 dev->mtu = new_mtu;
2518
2519 /* synchronized against open : rtnl_lock() held by caller */
2520 if (netif_running(dev)) {
2521 struct netdev_private *np = netdev_priv(dev);
2522 void __iomem * ioaddr = ns_ioaddr(dev);
2523
2524 disable_irq(dev->irq);
2525 spin_lock(&np->lock);
2526 /* stop engines */
2527 natsemi_stop_rxtx(dev);
2528 /* drain rx queue */
2529 drain_rx(dev);
2530 /* change buffers */
2531 set_bufsize(dev);
2532 reinit_rx(dev);
2533 writel(np->ring_dma, ioaddr + RxRingPtr);
2534 /* restart engines */
2535 writel(RxOn | TxOn, ioaddr + ChipCmd);
2536 spin_unlock(&np->lock);
2537 enable_irq(dev->irq);
2538 }
2539 return 0;
2540}
2541
2542static void set_rx_mode(struct net_device *dev)
2543{
2544 struct netdev_private *np = netdev_priv(dev);
2545 spin_lock_irq(&np->lock);
2546 if (!np->hands_off)
2547 __set_rx_mode(dev);
2548 spin_unlock_irq(&np->lock);
2549}
2550
2551static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2552{
2553 struct netdev_private *np = netdev_priv(dev);
2554 strncpy(info->driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
2555 strncpy(info->version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
2556 strncpy(info->bus_info, pci_name(np->pci_dev), ETHTOOL_BUSINFO_LEN);
2557}
2558
2559static int get_regs_len(struct net_device *dev)
2560{
2561 return NATSEMI_REGS_SIZE;
2562}
2563
2564static int get_eeprom_len(struct net_device *dev)
2565{
a8b4cf42
MB		 2566 struct netdev_private *np = netdev_priv(dev);
2567 return np->eeprom_size;
1da177e4
LT		 2568}
2569
2570static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2571{
2572 struct netdev_private *np = netdev_priv(dev);
2573 spin_lock_irq(&np->lock);
2574 netdev_get_ecmd(dev, ecmd);
2575 spin_unlock_irq(&np->lock);
2576 return 0;
2577}
2578
2579static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2580{
2581 struct netdev_private *np = netdev_priv(dev);
2582 int res;
2583 spin_lock_irq(&np->lock);
2584 res = netdev_set_ecmd(dev, ecmd);
2585 spin_unlock_irq(&np->lock);
2586 return res;
2587}
2588
2589static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2590{
2591 struct netdev_private *np = netdev_priv(dev);
2592 spin_lock_irq(&np->lock);
2593 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2594 netdev_get_sopass(dev, wol->sopass);
2595 spin_unlock_irq(&np->lock);
2596}
2597
2598static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2599{
2600 struct netdev_private *np = netdev_priv(dev);
2601 int res;
2602 spin_lock_irq(&np->lock);
2603 netdev_set_wol(dev, wol->wolopts);
2604 res = netdev_set_sopass(dev, wol->sopass);
2605 spin_unlock_irq(&np->lock);
2606 return res;
2607}
2608
2609static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2610{
2611 struct netdev_private *np = netdev_priv(dev);
2612 regs->version = NATSEMI_REGS_VER;
2613 spin_lock_irq(&np->lock);
2614 netdev_get_regs(dev, buf);
2615 spin_unlock_irq(&np->lock);
2616}
2617
2618static u32 get_msglevel(struct net_device *dev)
2619{
2620 struct netdev_private *np = netdev_priv(dev);
2621 return np->msg_enable;
2622}
2623
2624static void set_msglevel(struct net_device *dev, u32 val)
2625{
2626 struct netdev_private *np = netdev_priv(dev);
2627 np->msg_enable = val;
2628}
2629
2630static int nway_reset(struct net_device *dev)
2631{
2632 int tmp;
2633 int r = -EINVAL;
2634 /* if autoneg is off, it's an error */
2635 tmp = mdio_read(dev, MII_BMCR);
2636 if (tmp & BMCR_ANENABLE) {
2637 tmp |= (BMCR_ANRESTART);
2638 mdio_write(dev, MII_BMCR, tmp);
2639 r = 0;
2640 }
2641 return r;
2642}
2643
2644static u32 get_link(struct net_device *dev)
2645{
2646 /* LSTATUS is latched low until a read - so read twice */
2647 mdio_read(dev, MII_BMSR);
2648 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2649}
2650
2651static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2652{
2653 struct netdev_private *np = netdev_priv(dev);
a8b4cf42 2654 u8 *eebuf;
1da177e4
LT		 2655 int res;
2656
a8b4cf42
MB		 2657 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL);
2658 if (!eebuf)
2659 return -ENOMEM;
2660
1da177e4
LT		 2661 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2662 spin_lock_irq(&np->lock);
2663 res = netdev_get_eeprom(dev, eebuf);
2664 spin_unlock_irq(&np->lock);
2665 if (!res)
2666 memcpy(data, eebuf+eeprom->offset, eeprom->len);
a8b4cf42 2667 kfree(eebuf);
1da177e4
LT		 2668 return res;
2669}
2670
7282d491 2671static const struct ethtool_ops ethtool_ops = {
1da177e4
LT		 2672 .get_drvinfo = get_drvinfo,
2673 .get_regs_len = get_regs_len,
2674 .get_eeprom_len = get_eeprom_len,
2675 .get_settings = get_settings,
2676 .set_settings = set_settings,
2677 .get_wol = get_wol,
2678 .set_wol = set_wol,
2679 .get_regs = get_regs,
2680 .get_msglevel = get_msglevel,
2681 .set_msglevel = set_msglevel,
2682 .nway_reset = nway_reset,
2683 .get_link = get_link,
2684 .get_eeprom = get_eeprom,
2685};
2686
2687static int netdev_set_wol(struct net_device *dev, u32 newval)
2688{
2689 struct netdev_private *np = netdev_priv(dev);
2690 void __iomem * ioaddr = ns_ioaddr(dev);
2691 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2692
2693 /* translate to bitmasks this chip understands */
2694 if (newval & WAKE_PHY)
2695 data |= WakePhy;
2696 if (newval & WAKE_UCAST)
2697 data |= WakeUnicast;
2698 if (newval & WAKE_MCAST)
2699 data |= WakeMulticast;
2700 if (newval & WAKE_BCAST)
2701 data |= WakeBroadcast;
2702 if (newval & WAKE_ARP)
2703 data |= WakeArp;
2704 if (newval & WAKE_MAGIC)
2705 data |= WakeMagic;
2706 if (np->srr >= SRR_DP83815_D) {
2707 if (newval & WAKE_MAGICSECURE) {
2708 data |= WakeMagicSecure;
2709 }
2710 }
2711
2712 writel(data, ioaddr + WOLCmd);
2713
2714 return 0;
2715}
2716
2717static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2718{
2719 struct netdev_private *np = netdev_priv(dev);
2720 void __iomem * ioaddr = ns_ioaddr(dev);
2721 u32 regval = readl(ioaddr + WOLCmd);
2722
2723 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2724 | WAKE_ARP | WAKE_MAGIC);
2725
2726 if (np->srr >= SRR_DP83815_D) {
2727 /* SOPASS works on revD and higher */
2728 *supported |= WAKE_MAGICSECURE;
2729 }
2730 *cur = 0;
2731
2732 /* translate from chip bitmasks */
2733 if (regval & WakePhy)
2734 *cur |= WAKE_PHY;
2735 if (regval & WakeUnicast)
2736 *cur |= WAKE_UCAST;
2737 if (regval & WakeMulticast)
2738 *cur |= WAKE_MCAST;
2739 if (regval & WakeBroadcast)
2740 *cur |= WAKE_BCAST;
2741 if (regval & WakeArp)
2742 *cur |= WAKE_ARP;
2743 if (regval & WakeMagic)
2744 *cur |= WAKE_MAGIC;
2745 if (regval & WakeMagicSecure) {
2746 /* this can be on in revC, but it's broken */
2747 *cur |= WAKE_MAGICSECURE;
2748 }
2749
2750 return 0;
2751}
2752
2753static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2754{
2755 struct netdev_private *np = netdev_priv(dev);
2756 void __iomem * ioaddr = ns_ioaddr(dev);
2757 u16 *sval = (u16 *)newval;
2758 u32 addr;
2759
2760 if (np->srr < SRR_DP83815_D) {
2761 return 0;
2762 }
2763
2764 /* enable writing to these registers by disabling the RX filter */
2765 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2766 addr &= ~RxFilterEnable;
2767 writel(addr, ioaddr + RxFilterAddr);
2768
2769 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2770 writel(addr | 0xa, ioaddr + RxFilterAddr);
2771 writew(sval[0], ioaddr + RxFilterData);
2772
2773 writel(addr | 0xc, ioaddr + RxFilterAddr);
2774 writew(sval[1], ioaddr + RxFilterData);
2775
2776 writel(addr | 0xe, ioaddr + RxFilterAddr);
2777 writew(sval[2], ioaddr + RxFilterData);
2778
2779 /* re-enable the RX filter */
2780 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2781
2782 return 0;
2783}
2784
2785static int netdev_get_sopass(struct net_device *dev, u8 *data)
2786{
2787 struct netdev_private *np = netdev_priv(dev);
2788 void __iomem * ioaddr = ns_ioaddr(dev);
2789 u16 *sval = (u16 *)data;
2790 u32 addr;
2791
2792 if (np->srr < SRR_DP83815_D) {
2793 sval[0] = sval[1] = sval[2] = 0;
2794 return 0;
2795 }
2796
2797 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2798 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2799
2800 writel(addr | 0xa, ioaddr + RxFilterAddr);
2801 sval[0] = readw(ioaddr + RxFilterData);
2802
2803 writel(addr | 0xc, ioaddr + RxFilterAddr);
2804 sval[1] = readw(ioaddr + RxFilterData);
2805
2806 writel(addr | 0xe, ioaddr + RxFilterAddr);
2807 sval[2] = readw(ioaddr + RxFilterData);
2808
2809 writel(addr, ioaddr + RxFilterAddr);
2810
2811 return 0;
2812}
2813
2814static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2815{
2816 struct netdev_private *np = netdev_priv(dev);
2817 u32 tmp;
2818
2819 ecmd->port = dev->if_port;
2820 ecmd->speed = np->speed;
2821 ecmd->duplex = np->duplex;
2822 ecmd->autoneg = np->autoneg;
2823 ecmd->advertising = 0;
2824 if (np->advertising & ADVERTISE_10HALF)
2825 ecmd->advertising |= ADVERTISED_10baseT_Half;
2826 if (np->advertising & ADVERTISE_10FULL)
2827 ecmd->advertising |= ADVERTISED_10baseT_Full;
2828 if (np->advertising & ADVERTISE_100HALF)
2829 ecmd->advertising |= ADVERTISED_100baseT_Half;
2830 if (np->advertising & ADVERTISE_100FULL)
2831 ecmd->advertising |= ADVERTISED_100baseT_Full;
2832 ecmd->supported = (SUPPORTED_Autoneg |
2833 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2834 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2835 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2836 ecmd->phy_address = np->phy_addr_external;
2837 /*
2838 * We intentionally report the phy address of the external
2839 * phy, even if the internal phy is used. This is necessary
2840 * to work around a deficiency of the ethtool interface:
2841 * It's only possible to query the settings of the active
6aa20a22 2842 * port. Therefore
1da177e4
LT		 2843 * # ethtool -s ethX port mii
2844 * actually sends an ioctl to switch to port mii with the
2845 * settings that are used for the current active port.
2846 * If we would report a different phy address in this
2847 * command, then
2848 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2849 * would unintentionally change the phy address.
2850 *
2851 * Fortunately the phy address doesn't matter with the
2852 * internal phy...
2853 */
2854
2855 /* set information based on active port type */
2856 switch (ecmd->port) {
2857 default:
2858 case PORT_TP:
2859 ecmd->advertising |= ADVERTISED_TP;
2860 ecmd->transceiver = XCVR_INTERNAL;
2861 break;
2862 case PORT_MII:
2863 ecmd->advertising |= ADVERTISED_MII;
2864 ecmd->transceiver = XCVR_EXTERNAL;
2865 break;
2866 case PORT_FIBRE:
2867 ecmd->advertising |= ADVERTISED_FIBRE;
2868 ecmd->transceiver = XCVR_EXTERNAL;
2869 break;
2870 }
2871
2872 /* if autonegotiation is on, try to return the active speed/duplex */
2873 if (ecmd->autoneg == AUTONEG_ENABLE) {
2874 ecmd->advertising |= ADVERTISED_Autoneg;
2875 tmp = mii_nway_result(
2876 np->advertising & mdio_read(dev, MII_LPA));
2877 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2878 ecmd->speed = SPEED_100;
2879 else
2880 ecmd->speed = SPEED_10;
2881 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2882 ecmd->duplex = DUPLEX_FULL;
2883 else
2884 ecmd->duplex = DUPLEX_HALF;
2885 }
2886
2887 /* ignore maxtxpkt, maxrxpkt for now */
2888
2889 return 0;
2890}
2891
2892static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2893{
2894 struct netdev_private *np = netdev_priv(dev);
2895
2896 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
2897 return -EINVAL;
2898 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
2899 return -EINVAL;
2900 if (ecmd->autoneg == AUTONEG_ENABLE) {
2901 if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
2902 ADVERTISED_10baseT_Full |
2903 ADVERTISED_100baseT_Half |
2904 ADVERTISED_100baseT_Full)) == 0) {
2905 return -EINVAL;
2906 }
2907 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2908 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2909 return -EINVAL;
2910 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2911 return -EINVAL;
2912 } else {
2913 return -EINVAL;
2914 }
2915
68c90166
MB		 2916 /*
2917 * If we're ignoring the PHY then autoneg and the internal
2918 * transciever are really not going to work so don't let the
2919 * user select them.
2920 */
2921 if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE ||
2922 ecmd->port == PORT_TP))
2923 return -EINVAL;
2924
1da177e4
LT		 2925 /*
2926 * maxtxpkt, maxrxpkt: ignored for now.
2927 *
2928 * transceiver:
2929 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2930 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2931 * selects based on ecmd->port.
2932 *
2933 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2934 * phys that are connected to the mii bus. It's used to apply fibre
2935 * specific updates.
2936 */
2937
2938 /* WHEW! now lets bang some bits */
2939
2940 /* save the parms */
2941 dev->if_port = ecmd->port;
2942 np->autoneg = ecmd->autoneg;
2943 np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
2944 if (np->autoneg == AUTONEG_ENABLE) {
2945 /* advertise only what has been requested */
2946 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2947 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2948 np->advertising |= ADVERTISE_10HALF;
2949 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2950 np->advertising |= ADVERTISE_10FULL;
2951 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2952 np->advertising |= ADVERTISE_100HALF;
2953 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2954 np->advertising |= ADVERTISE_100FULL;
2955 } else {
2956 np->speed = ecmd->speed;
2957 np->duplex = ecmd->duplex;
2958 /* user overriding the initial full duplex parm? */
2959 if (np->duplex == DUPLEX_HALF)
2960 np->full_duplex = 0;
2961 }
2962
2963 /* get the right phy enabled */
2964 if (ecmd->port == PORT_TP)
2965 switch_port_internal(dev);
2966 else
2967 switch_port_external(dev);
2968
2969 /* set parms and see how this affected our link status */
2970 init_phy_fixup(dev);
2971 check_link(dev);
2972 return 0;
2973}
2974
2975static int netdev_get_regs(struct net_device *dev, u8 *buf)
2976{
2977 int i;
2978 int j;
2979 u32 rfcr;
2980 u32 *rbuf = (u32 *)buf;
2981 void __iomem * ioaddr = ns_ioaddr(dev);
2982
2983 /* read non-mii page 0 of registers */
2984 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
2985 rbuf[i] = readl(ioaddr + i*4);
2986 }
2987
2988 /* read current mii registers */
2989 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
2990 rbuf[i] = mdio_read(dev, i & 0x1f);
2991
2992 /* read only the 'magic' registers from page 1 */
2993 writew(1, ioaddr + PGSEL);
2994 rbuf[i++] = readw(ioaddr + PMDCSR);
2995 rbuf[i++] = readw(ioaddr + TSTDAT);
2996 rbuf[i++] = readw(ioaddr + DSPCFG);
2997 rbuf[i++] = readw(ioaddr + SDCFG);
2998 writew(0, ioaddr + PGSEL);
2999
3000 /* read RFCR indexed registers */
3001 rfcr = readl(ioaddr + RxFilterAddr);
3002 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
3003 writel(j*2, ioaddr + RxFilterAddr);
3004 rbuf[i++] = readw(ioaddr + RxFilterData);
3005 }
3006 writel(rfcr, ioaddr + RxFilterAddr);
3007
3008 /* the interrupt status is clear-on-read - see if we missed any */
3009 if (rbuf[4] & rbuf[5]) {
3010 printk(KERN_WARNING
3011 "%s: shoot, we dropped an interrupt (%#08x)\n",
3012 dev->name, rbuf[4] & rbuf[5]);
3013 }
3014
3015 return 0;
3016}
3017
3018#define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
3019 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
3020 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
3021 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
3022 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
3023 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
3024 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
3025 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
3026
3027static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
3028{
3029 int i;
3030 u16 *ebuf = (u16 *)buf;
3031 void __iomem * ioaddr = ns_ioaddr(dev);
a8b4cf42 3032 struct netdev_private *np = netdev_priv(dev);
1da177e4
LT		 3033
3034 /* eeprom_read reads 16 bits, and indexes by 16 bits */
a8b4cf42 3035 for (i = 0; i < np->eeprom_size/2; i++) {
1da177e4
LT		 3036 ebuf[i] = eeprom_read(ioaddr, i);
3037 /* The EEPROM itself stores data bit-swapped, but eeprom_read
3038 * reads it back "sanely". So we swap it back here in order to
3039 * present it to userland as it is stored. */
3040 ebuf[i] = SWAP_BITS(ebuf[i]);
3041 }
3042 return 0;
3043}
3044
3045static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3046{
3047 struct mii_ioctl_data *data = if_mii(rq);
3048 struct netdev_private *np = netdev_priv(dev);
3049
3050 switch(cmd) {
3051 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1da177e4
LT		 3052 data->phy_id = np->phy_addr_external;
3053 /* Fall Through */
3054
3055 case SIOCGMIIREG: /* Read MII PHY register. */
1da177e4
LT		 3056 /* The phy_id is not enough to uniquely identify
3057 * the intended target. Therefore the command is sent to
3058 * the given mii on the current port.
3059 */
3060 if (dev->if_port == PORT_TP) {
3061 if ((data->phy_id & 0x1f) == np->phy_addr_external)
3062 data->val_out = mdio_read(dev,
3063 data->reg_num & 0x1f);
3064 else
3065 data->val_out = 0;
3066 } else {
3067 move_int_phy(dev, data->phy_id & 0x1f);
3068 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
3069 data->reg_num & 0x1f);
3070 }
3071 return 0;
3072
3073 case SIOCSMIIREG: /* Write MII PHY register. */
1da177e4
LT		 3074 if (dev->if_port == PORT_TP) {
3075 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3076 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3077 np->advertising = data->val_in;
3078 mdio_write(dev, data->reg_num & 0x1f,
3079 data->val_in);
3080 }
3081 } else {
3082 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3083 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3084 np->advertising = data->val_in;
3085 }
3086 move_int_phy(dev, data->phy_id & 0x1f);
3087 miiport_write(dev, data->phy_id & 0x1f,
3088 data->reg_num & 0x1f,
3089 data->val_in);
3090 }
3091 return 0;
3092 default:
3093 return -EOPNOTSUPP;
3094 }
3095}
3096
3097static void enable_wol_mode(struct net_device *dev, int enable_intr)
3098{
3099 void __iomem * ioaddr = ns_ioaddr(dev);
3100 struct netdev_private *np = netdev_priv(dev);
3101
3102 if (netif_msg_wol(np))
3103 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3104 dev->name);
3105
3106 /* For WOL we must restart the rx process in silent mode.
3107 * Write NULL to the RxRingPtr. Only possible if
3108 * rx process is stopped
3109 */
3110 writel(0, ioaddr + RxRingPtr);
3111
3112 /* read WoL status to clear */
3113 readl(ioaddr + WOLCmd);
3114
3115 /* PME on, clear status */
3116 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3117
3118 /* and restart the rx process */
3119 writel(RxOn, ioaddr + ChipCmd);
3120
3121 if (enable_intr) {
3122 /* enable the WOL interrupt.
3123 * Could be used to send a netlink message.
3124 */
3125 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
14fdd90e 3126 natsemi_irq_enable(dev);
1da177e4
LT		 3127 }
3128}
3129
3130static int netdev_close(struct net_device *dev)
3131{
3132 void __iomem * ioaddr = ns_ioaddr(dev);
3133 struct netdev_private *np = netdev_priv(dev);
3134
3135 if (netif_msg_ifdown(np))
3136 printk(KERN_DEBUG
3137 "%s: Shutting down ethercard, status was %#04x.\n",
3138 dev->name, (int)readl(ioaddr + ChipCmd));
3139 if (netif_msg_pktdata(np))
3140 printk(KERN_DEBUG
3141 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3142 dev->name, np->cur_tx, np->dirty_tx,
3143 np->cur_rx, np->dirty_rx);
3144
bea3348e
SH		 3145 napi_disable(&np->napi);
3146
1da177e4
LT		 3147 /*
3148 * FIXME: what if someone tries to close a device
3149 * that is suspended?
3150 * Should we reenable the nic to switch to
3151 * the final WOL settings?
3152 */
3153
3154 del_timer_sync(&np->timer);
3155 disable_irq(dev->irq);
3156 spin_lock_irq(&np->lock);
b27a16b7 3157 natsemi_irq_disable(dev);
1da177e4
LT		 3158 np->hands_off = 1;
3159 spin_unlock_irq(&np->lock);
3160 enable_irq(dev->irq);
3161
3162 free_irq(dev->irq, dev);
3163
3164 /* Interrupt disabled, interrupt handler released,
3165 * queue stopped, timer deleted, rtnl_lock held
3166 * All async codepaths that access the driver are disabled.
3167 */
3168 spin_lock_irq(&np->lock);
3169 np->hands_off = 0;
3170 readl(ioaddr + IntrMask);
3171 readw(ioaddr + MIntrStatus);
3172
3173 /* Freeze Stats */
3174 writel(StatsFreeze, ioaddr + StatsCtrl);
3175
3176 /* Stop the chip's Tx and Rx processes. */
3177 natsemi_stop_rxtx(dev);
3178
3179 __get_stats(dev);
3180 spin_unlock_irq(&np->lock);
3181
3182 /* clear the carrier last - an interrupt could reenable it otherwise */
3183 netif_carrier_off(dev);
3184 netif_stop_queue(dev);
3185
3186 dump_ring(dev);
3187 drain_ring(dev);
3188 free_ring(dev);
3189
3190 {
3191 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3192 if (wol) {
3193 /* restart the NIC in WOL mode.
3194 * The nic must be stopped for this.
3195 */
3196 enable_wol_mode(dev, 0);
3197 } else {
3198 /* Restore PME enable bit unmolested */
3199 writel(np->SavedClkRun, ioaddr + ClkRun);
3200 }
3201 }
3202 return 0;
3203}
3204
3205
3206static void __devexit natsemi_remove1 (struct pci_dev *pdev)
3207{
3208 struct net_device *dev = pci_get_drvdata(pdev);
3209 void __iomem * ioaddr = ns_ioaddr(dev);
3210
1a147809 3211 NATSEMI_REMOVE_FILE(pdev, dspcfg_workaround);
1da177e4
LT		 3212 unregister_netdev (dev);
3213 pci_release_regions (pdev);
3214 iounmap(ioaddr);
3215 free_netdev (dev);
3216 pci_set_drvdata(pdev, NULL);
3217}
3218
3219#ifdef CONFIG_PM
3220
3221/*
3222 * The ns83815 chip doesn't have explicit RxStop bits.
3223 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3224 * of the nic, thus this function must be very careful:
3225 *
3226 * suspend/resume synchronization:
3227 * entry points:
3228 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
ed4cb133 3229 * start_tx, ns_tx_timeout
1da177e4
LT		 3230 *
3231 * No function accesses the hardware without checking np->hands_off.
3232 * the check occurs under spin_lock_irq(&np->lock);
3233 * exceptions:
3234 * * netdev_ioctl: noncritical access.
3235 * * netdev_open: cannot happen due to the device_detach
3236 * * netdev_close: doesn't hurt.
3237 * * netdev_timer: timer stopped by natsemi_suspend.
3238 * * intr_handler: doesn't acquire the spinlock. suspend calls
3239 * disable_irq() to enforce synchronization.
b27a16b7
MB		 3240 * * natsemi_poll: checks before reenabling interrupts. suspend
3241 * sets hands_off, disables interrupts and then waits with
bea3348e 3242 * napi_disable().
1da177e4
LT		 3243 *
3244 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3245 */
3246
3247static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3248{
3249 struct net_device *dev = pci_get_drvdata (pdev);
3250 struct netdev_private *np = netdev_priv(dev);
3251 void __iomem * ioaddr = ns_ioaddr(dev);
3252
3253 rtnl_lock();
3254 if (netif_running (dev)) {
3255 del_timer_sync(&np->timer);
3256
3257 disable_irq(dev->irq);
3258 spin_lock_irq(&np->lock);
3259
14fdd90e 3260 natsemi_irq_disable(dev);
1da177e4
LT		 3261 np->hands_off = 1;
3262 natsemi_stop_rxtx(dev);
3263 netif_stop_queue(dev);
3264
3265 spin_unlock_irq(&np->lock);
3266 enable_irq(dev->irq);
3267
bea3348e 3268 napi_disable(&np->napi);
b27a16b7 3269
1da177e4
LT		 3270 /* Update the error counts. */
3271 __get_stats(dev);
3272
3273 /* pci_power_off(pdev, -1); */
3274 drain_ring(dev);
3275 {
3276 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3277 /* Restore PME enable bit */
3278 if (wol) {
3279 /* restart the NIC in WOL mode.
3280 * The nic must be stopped for this.
3281 * FIXME: use the WOL interrupt
3282 */
3283 enable_wol_mode(dev, 0);
3284 } else {
3285 /* Restore PME enable bit unmolested */
3286 writel(np->SavedClkRun, ioaddr + ClkRun);
3287 }
3288 }
3289 }
3290 netif_device_detach(dev);
3291 rtnl_unlock();
3292 return 0;
3293}
3294
3295
3296static int natsemi_resume (struct pci_dev *pdev)
3297{
3298 struct net_device *dev = pci_get_drvdata (pdev);
3299 struct netdev_private *np = netdev_priv(dev);
a8a935da 3300 int ret = 0;
1da177e4
LT		 3301
3302 rtnl_lock();
3303 if (netif_device_present(dev))
3304 goto out;
3305 if (netif_running(dev)) {
3306 BUG_ON(!np->hands_off);
a8a935da
MB		 3307 ret = pci_enable_device(pdev);
3308 if (ret < 0) {
3309 dev_err(&pdev->dev,
3310 "pci_enable_device() failed: %d\n", ret);
3311 goto out;
3312 }
1da177e4
LT		 3313 /* pci_power_on(pdev); */
3314
bea3348e
SH		 3315 napi_enable(&np->napi);
3316
1da177e4
LT		 3317 natsemi_reset(dev);
3318 init_ring(dev);
3319 disable_irq(dev->irq);
3320 spin_lock_irq(&np->lock);
3321 np->hands_off = 0;
3322 init_registers(dev);
3323 netif_device_attach(dev);
3324 spin_unlock_irq(&np->lock);
3325 enable_irq(dev->irq);
3326
0e5d5442 3327 mod_timer(&np->timer, round_jiffies(jiffies + 1*HZ));
1da177e4
LT		 3328 }
3329 netif_device_attach(dev);
3330out:
3331 rtnl_unlock();
a8a935da 3332 return ret;
1da177e4
LT		 3333}
3334
3335#endif /* CONFIG_PM */
3336
3337static struct pci_driver natsemi_driver = {
3338 .name = DRV_NAME,
3339 .id_table = natsemi_pci_tbl,
3340 .probe = natsemi_probe1,
3341 .remove = __devexit_p(natsemi_remove1),
3342#ifdef CONFIG_PM
3343 .suspend = natsemi_suspend,
3344 .resume = natsemi_resume,
3345#endif
3346};
3347
3348static int __init natsemi_init_mod (void)
3349{
3350/* when a module, this is printed whether or not devices are found in probe */
3351#ifdef MODULE
3352 printk(version);
3353#endif
3354
29917620 3355 return pci_register_driver(&natsemi_driver);
1da177e4
LT		 3356}
3357
3358static void __exit natsemi_exit_mod (void)
3359{
3360 pci_unregister_driver (&natsemi_driver);
3361}
3362
3363module_init(natsemi_init_mod);
3364module_exit(natsemi_exit_mod);
3365
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