]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/myri10ge/myri10ge.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SK_BUFF]: Introduce icmp_hdr(), remove skb->h.icmph
[net-next-2.6.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4a2e612a 4 * Copyright (C) 2005 - 2007 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
51#include <linux/ip.h>
52#include <linux/inet.h>
53#include <linux/in.h>
54#include <linux/ethtool.h>
55#include <linux/firmware.h>
56#include <linux/delay.h>
57#include <linux/version.h>
58#include <linux/timer.h>
59#include <linux/vmalloc.h>
60#include <linux/crc32.h>
61#include <linux/moduleparam.h>
62#include <linux/io.h>
63#include <net/checksum.h>
64#include <asm/byteorder.h>
65#include <asm/io.h>
0da34b6d
BG		 66#include <asm/processor.h>
67#ifdef CONFIG_MTRR
68#include <asm/mtrr.h>
69#endif
70
71#include "myri10ge_mcp.h"
72#include "myri10ge_mcp_gen_header.h"
73
4b2281c7 74#define MYRI10GE_VERSION_STR "1.3.0-1.233"
0da34b6d
BG		 75
76MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77MODULE_AUTHOR("Maintainer: help@myri.com");
78MODULE_VERSION(MYRI10GE_VERSION_STR);
79MODULE_LICENSE("Dual BSD/GPL");
80
81#define MYRI10GE_MAX_ETHER_MTU 9014
82
83#define MYRI10GE_ETH_STOPPED 0
84#define MYRI10GE_ETH_STOPPING 1
85#define MYRI10GE_ETH_STARTING 2
86#define MYRI10GE_ETH_RUNNING 3
87#define MYRI10GE_ETH_OPEN_FAILED 4
88
89#define MYRI10GE_EEPROM_STRINGS_SIZE 256
90#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
91
40f6cff5 92#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 93#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
94
dd50f336
BG		 95#define MYRI10GE_ALLOC_ORDER 0
96#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
97#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
98
0da34b6d 99struct myri10ge_rx_buffer_state {
dd50f336
BG		 100 struct page *page;
101 int page_offset;
0da34b6d
BG		 102 DECLARE_PCI_UNMAP_ADDR(bus)
103 DECLARE_PCI_UNMAP_LEN(len)
104};
105
106struct myri10ge_tx_buffer_state {
107 struct sk_buff *skb;
108 int last;
109 DECLARE_PCI_UNMAP_ADDR(bus)
110 DECLARE_PCI_UNMAP_LEN(len)
111};
112
113struct myri10ge_cmd {
114 u32 data0;
115 u32 data1;
116 u32 data2;
117};
118
119struct myri10ge_rx_buf {
120 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
121 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
122 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
123 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 124 struct page *page;
125 dma_addr_t bus;
126 int page_offset;
0da34b6d 127 int cnt;
dd50f336 128 int fill_cnt;
0da34b6d
BG		 129 int alloc_fail;
130 int mask; /* number of rx slots -1 */
dd50f336 131 int watchdog_needed;
0da34b6d
BG		 132};
133
134struct myri10ge_tx_buf {
135 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
136 u8 __iomem *wc_fifo; /* w/c send fifo address */
137 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
138 char *req_bytes;
139 struct myri10ge_tx_buffer_state *info;
140 int mask; /* number of transmit slots -1 */
141 int boundary; /* boundary transmits cannot cross */
142 int req ____cacheline_aligned; /* transmit slots submitted */
143 int pkt_start; /* packets started */
144 int done ____cacheline_aligned; /* transmit slots completed */
145 int pkt_done; /* packets completed */
146};
147
148struct myri10ge_rx_done {
149 struct mcp_slot *entry;
150 dma_addr_t bus;
151 int cnt;
152 int idx;
153};
154
155struct myri10ge_priv {
156 int running; /* running? */
157 int csum_flag; /* rx_csums? */
158 struct myri10ge_tx_buf tx; /* transmit ring */
159 struct myri10ge_rx_buf rx_small;
160 struct myri10ge_rx_buf rx_big;
161 struct myri10ge_rx_done rx_done;
162 int small_bytes;
dd50f336 163 int big_bytes;
0da34b6d
BG		 164 struct net_device *dev;
165 struct net_device_stats stats;
166 u8 __iomem *sram;
167 int sram_size;
168 unsigned long board_span;
169 unsigned long iomem_base;
40f6cff5
AV		 170 __be32 __iomem *irq_claim;
171 __be32 __iomem *irq_deassert;
0da34b6d
BG		 172 char *mac_addr_string;
173 struct mcp_cmd_response *cmd;
174 dma_addr_t cmd_bus;
175 struct mcp_irq_data *fw_stats;
176 dma_addr_t fw_stats_bus;
177 struct pci_dev *pdev;
178 int msi_enabled;
40f6cff5 179 __be32 link_state;
0da34b6d
BG		 180 unsigned int rdma_tags_available;
181 int intr_coal_delay;
40f6cff5 182 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 183 int mtrr;
276e26c3 184 int wc_enabled;
0da34b6d
BG		 185 int wake_queue;
186 int stop_queue;
187 int down_cnt;
188 wait_queue_head_t down_wq;
189 struct work_struct watchdog_work;
190 struct timer_list watchdog_timer;
191 int watchdog_tx_done;
c54772e7 192 int watchdog_tx_req;
0da34b6d
BG		 193 int watchdog_resets;
194 int tx_linearized;
195 int pause;
196 char *fw_name;
197 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
198 char fw_version[128];
9dc6f0e7
BG		 199 int fw_ver_major;
200 int fw_ver_minor;
201 int fw_ver_tiny;
202 int adopted_rx_filter_bug;
0da34b6d
BG		 203 u8 mac_addr[6]; /* eeprom mac address */
204 unsigned long serial_number;
205 int vendor_specific_offset;
85a7ea1b 206 int fw_multicast_support;
0da34b6d
BG		 207 u32 read_dma;
208 u32 write_dma;
209 u32 read_write_dma;
c58ac5ca
BG		 210 u32 link_changes;
211 u32 msg_enable;
0da34b6d
BG		 212};
213
214static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
215static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
216
217static char *myri10ge_fw_name = NULL;
218module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
219MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
220
221static int myri10ge_ecrc_enable = 1;
222module_param(myri10ge_ecrc_enable, int, S_IRUGO);
223MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
224
225static int myri10ge_max_intr_slots = 1024;
226module_param(myri10ge_max_intr_slots, int, S_IRUGO);
227MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
228
229static int myri10ge_small_bytes = -1; /* -1 == auto */
230module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
231MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
232
233static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 234module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
0da34b6d
BG		 235MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
236
f761fae1 237static int myri10ge_intr_coal_delay = 75;
0da34b6d
BG		 238module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
239MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
240
241static int myri10ge_flow_control = 1;
242module_param(myri10ge_flow_control, int, S_IRUGO);
243MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
244
245static int myri10ge_deassert_wait = 1;
246module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
247MODULE_PARM_DESC(myri10ge_deassert_wait,
248 "Wait when deasserting legacy interrupts\n");
249
250static int myri10ge_force_firmware = 0;
251module_param(myri10ge_force_firmware, int, S_IRUGO);
252MODULE_PARM_DESC(myri10ge_force_firmware,
253 "Force firmware to assume aligned completions\n");
254
0da34b6d
BG		 255static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
256module_param(myri10ge_initial_mtu, int, S_IRUGO);
257MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
258
259static int myri10ge_napi_weight = 64;
260module_param(myri10ge_napi_weight, int, S_IRUGO);
261MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
262
263static int myri10ge_watchdog_timeout = 1;
264module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
265MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
266
267static int myri10ge_max_irq_loops = 1048576;
268module_param(myri10ge_max_irq_loops, int, S_IRUGO);
269MODULE_PARM_DESC(myri10ge_max_irq_loops,
270 "Set stuck legacy IRQ detection threshold\n");
271
c58ac5ca
BG		 272#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
273
274static int myri10ge_debug = -1; /* defaults above */
275module_param(myri10ge_debug, int, 0);
276MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
277
dd50f336
BG		 278static int myri10ge_fill_thresh = 256;
279module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
280MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
281
f761fae1 282static int myri10ge_wcfifo = 0;
6ebc087a
BG		 283module_param(myri10ge_wcfifo, int, S_IRUGO);
284MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n");
285
0da34b6d
BG		 286#define MYRI10GE_FW_OFFSET 1024*1024
287#define MYRI10GE_HIGHPART_TO_U32(X) \
288(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
289#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
290
291#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
292
6250223e 293static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 294{
6250223e 295 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 296}
297
0da34b6d
BG		 298static int
299myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
300 struct myri10ge_cmd *data, int atomic)
301{
302 struct mcp_cmd *buf;
303 char buf_bytes[sizeof(*buf) + 8];
304 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 305 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 306 u32 dma_low, dma_high, result, value;
307 int sleep_total = 0;
308
309 /* ensure buf is aligned to 8 bytes */
310 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
311
312 buf->data0 = htonl(data->data0);
313 buf->data1 = htonl(data->data1);
314 buf->data2 = htonl(data->data2);
315 buf->cmd = htonl(cmd);
316 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
317 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
318
319 buf->response_addr.low = htonl(dma_low);
320 buf->response_addr.high = htonl(dma_high);
40f6cff5 321 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 322 mb();
323 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
324
325 /* wait up to 15ms. Longest command is the DMA benchmark,
326 * which is capped at 5ms, but runs from a timeout handler
327 * that runs every 7.8ms. So a 15ms timeout leaves us with
328 * a 2.2ms margin
329 */
330 if (atomic) {
331 /* if atomic is set, do not sleep,
332 * and try to get the completion quickly
333 * (1ms will be enough for those commands) */
334 for (sleep_total = 0;
335 sleep_total < 1000
40f6cff5 336 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 337 sleep_total += 10)
338 udelay(10);
339 } else {
340 /* use msleep for most command */
341 for (sleep_total = 0;
342 sleep_total < 15
40f6cff5 343 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 344 sleep_total++)
345 msleep(1);
346 }
347
348 result = ntohl(response->result);
349 value = ntohl(response->data);
350 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
351 if (result == 0) {
352 data->data0 = value;
353 return 0;
85a7ea1b
BG		 354 } else if (result == MXGEFW_CMD_UNKNOWN) {
355 return -ENOSYS;
0da34b6d
BG		 356 } else {
357 dev_err(&mgp->pdev->dev,
358 "command %d failed, result = %d\n",
359 cmd, result);
360 return -ENXIO;
361 }
362 }
363
364 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
365 cmd, result);
366 return -EAGAIN;
367}
368
369/*
370 * The eeprom strings on the lanaiX have the format
371 * SN=x\0
372 * MAC=x:x:x:x:x:x\0
373 * PT:ddd mmm xx xx:xx:xx xx\0
374 * PV:ddd mmm xx xx:xx:xx xx\0
375 */
376static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
377{
378 char *ptr, *limit;
379 int i;
380
381 ptr = mgp->eeprom_strings;
382 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
383
384 while (*ptr != '\0' && ptr < limit) {
385 if (memcmp(ptr, "MAC=", 4) == 0) {
386 ptr += 4;
387 mgp->mac_addr_string = ptr;
388 for (i = 0; i < 6; i++) {
389 if ((ptr + 2) > limit)
390 goto abort;
391 mgp->mac_addr[i] =
392 simple_strtoul(ptr, &ptr, 16);
393 ptr += 1;
394 }
395 }
396 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
397 ptr += 3;
398 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
399 }
400 while (ptr < limit && *ptr++) ;
401 }
402
403 return 0;
404
405abort:
406 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
407 return -ENXIO;
408}
409
410/*
411 * Enable or disable periodic RDMAs from the host to make certain
412 * chipsets resend dropped PCIe messages
413 */
414
415static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
416{
417 char __iomem *submit;
40f6cff5 418 __be32 buf[16];
0da34b6d
BG		 419 u32 dma_low, dma_high;
420 int i;
421
422 /* clear confirmation addr */
423 mgp->cmd->data = 0;
424 mb();
425
426 /* send a rdma command to the PCIe engine, and wait for the
427 * response in the confirmation address. The firmware should
428 * write a -1 there to indicate it is alive and well
429 */
430 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
431 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
432
433 buf[0] = htonl(dma_high); /* confirm addr MSW */
434 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 435 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 436 buf[3] = htonl(dma_high); /* dummy addr MSW */
437 buf[4] = htonl(dma_low); /* dummy addr LSW */
438 buf[5] = htonl(enable); /* enable? */
439
e700f9f4 440 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 441
442 myri10ge_pio_copy(submit, &buf, sizeof(buf));
443 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
444 msleep(1);
445 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
446 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
447 (enable ? "enable" : "disable"));
448}
449
450static int
451myri10ge_validate_firmware(struct myri10ge_priv *mgp,
452 struct mcp_gen_header *hdr)
453{
454 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 455
456 /* check firmware type */
457 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
458 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
459 return -EINVAL;
460 }
461
462 /* save firmware version for ethtool */
463 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
464
9dc6f0e7
BG		 465 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
466 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 467
9dc6f0e7
BG		 468 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
469 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 470 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
471 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
472 MXGEFW_VERSION_MINOR);
473 return -EINVAL;
474 }
475 return 0;
476}
477
478static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
479{
480 unsigned crc, reread_crc;
481 const struct firmware *fw;
482 struct device *dev = &mgp->pdev->dev;
483 struct mcp_gen_header *hdr;
484 size_t hdr_offset;
485 int status;
e454358a 486 unsigned i;
0da34b6d
BG		 487
488 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
489 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
490 mgp->fw_name);
491 status = -EINVAL;
492 goto abort_with_nothing;
493 }
494
495 /* check size */
496
497 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
498 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
499 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
500 status = -EINVAL;
501 goto abort_with_fw;
502 }
503
504 /* check id */
40f6cff5 505 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 506 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
507 dev_err(dev, "Bad firmware file\n");
508 status = -EINVAL;
509 goto abort_with_fw;
510 }
511 hdr = (void *)(fw->data + hdr_offset);
512
513 status = myri10ge_validate_firmware(mgp, hdr);
514 if (status != 0)
515 goto abort_with_fw;
516
517 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 518 for (i = 0; i < fw->size; i += 256) {
519 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
520 fw->data + i,
521 min(256U, (unsigned)(fw->size - i)));
522 mb();
523 readb(mgp->sram);
b10c0668 524 }
0da34b6d
BG		 525 /* corruption checking is good for parity recovery and buggy chipset */
526 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
527 reread_crc = crc32(~0, fw->data, fw->size);
528 if (crc != reread_crc) {
529 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
530 (unsigned)fw->size, reread_crc, crc);
531 status = -EIO;
532 goto abort_with_fw;
533 }
534 *size = (u32) fw->size;
535
536abort_with_fw:
537 release_firmware(fw);
538
539abort_with_nothing:
540 return status;
541}
542
543static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
544{
545 struct mcp_gen_header *hdr;
546 struct device *dev = &mgp->pdev->dev;
547 const size_t bytes = sizeof(struct mcp_gen_header);
548 size_t hdr_offset;
549 int status;
550
551 /* find running firmware header */
552 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
553
554 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
555 dev_err(dev, "Running firmware has bad header offset (%d)\n",
556 (int)hdr_offset);
557 return -EIO;
558 }
559
560 /* copy header of running firmware from SRAM to host memory to
561 * validate firmware */
562 hdr = kmalloc(bytes, GFP_KERNEL);
563 if (hdr == NULL) {
564 dev_err(dev, "could not malloc firmware hdr\n");
565 return -ENOMEM;
566 }
567 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
568 status = myri10ge_validate_firmware(mgp, hdr);
569 kfree(hdr);
9dc6f0e7
BG		 570
571 /* check to see if adopted firmware has bug where adopting
572 * it will cause broadcasts to be filtered unless the NIC
573 * is kept in ALLMULTI mode */
574 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
575 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
576 mgp->adopted_rx_filter_bug = 1;
577 dev_warn(dev, "Adopting fw %d.%d.%d: "
578 "working around rx filter bug\n",
579 mgp->fw_ver_major, mgp->fw_ver_minor,
580 mgp->fw_ver_tiny);
581 }
0da34b6d
BG		 582 return status;
583}
584
585static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
586{
587 char __iomem *submit;
40f6cff5 588 __be32 buf[16];
0da34b6d
BG		 589 u32 dma_low, dma_high, size;
590 int status, i;
591
b10c0668 592 size = 0;
0da34b6d
BG		 593 status = myri10ge_load_hotplug_firmware(mgp, &size);
594 if (status) {
595 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
596
597 /* Do not attempt to adopt firmware if there
598 * was a bad crc */
599 if (status == -EIO)
600 return status;
601
602 status = myri10ge_adopt_running_firmware(mgp);
603 if (status != 0) {
604 dev_err(&mgp->pdev->dev,
605 "failed to adopt running firmware\n");
606 return status;
607 }
608 dev_info(&mgp->pdev->dev,
609 "Successfully adopted running firmware\n");
610 if (mgp->tx.boundary == 4096) {
611 dev_warn(&mgp->pdev->dev,
612 "Using firmware currently running on NIC"
613 ". For optimal\n");
614 dev_warn(&mgp->pdev->dev,
615 "performance consider loading optimized "
616 "firmware\n");
617 dev_warn(&mgp->pdev->dev, "via hotplug\n");
618 }
619
620 mgp->fw_name = "adopted";
621 mgp->tx.boundary = 2048;
622 return status;
623 }
624
625 /* clear confirmation addr */
626 mgp->cmd->data = 0;
627 mb();
628
629 /* send a reload command to the bootstrap MCP, and wait for the
630 * response in the confirmation address. The firmware should
631 * write a -1 there to indicate it is alive and well
632 */
633 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
634 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
635
636 buf[0] = htonl(dma_high); /* confirm addr MSW */
637 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 638 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 639
640 /* FIX: All newest firmware should un-protect the bottom of
641 * the sram before handoff. However, the very first interfaces
642 * do not. Therefore the handoff copy must skip the first 8 bytes
643 */
644 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
645 buf[4] = htonl(size - 8); /* length of code */
646 buf[5] = htonl(8); /* where to copy to */
647 buf[6] = htonl(0); /* where to jump to */
648
e700f9f4 649 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 650
651 myri10ge_pio_copy(submit, &buf, sizeof(buf));
652 mb();
653 msleep(1);
654 mb();
655 i = 0;
656 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
657 msleep(1);
658 i++;
659 }
660 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
661 dev_err(&mgp->pdev->dev, "handoff failed\n");
662 return -ENXIO;
663 }
664 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
9a71db72 665 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 666
667 return 0;
668}
669
670static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
671{
672 struct myri10ge_cmd cmd;
673 int status;
674
675 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
676 | (addr[2] << 8) | addr[3]);
677
678 cmd.data1 = ((addr[4] << 8) | (addr[5]));
679
680 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
681 return status;
682}
683
684static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
685{
686 struct myri10ge_cmd cmd;
687 int status, ctl;
688
689 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
690 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
691
692 if (status) {
693 printk(KERN_ERR
694 "myri10ge: %s: Failed to set flow control mode\n",
695 mgp->dev->name);
696 return status;
697 }
698 mgp->pause = pause;
699 return 0;
700}
701
702static void
703myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
704{
705 struct myri10ge_cmd cmd;
706 int status, ctl;
707
708 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
709 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
710 if (status)
711 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
712 mgp->dev->name);
713}
714
715static int myri10ge_reset(struct myri10ge_priv *mgp)
716{
717 struct myri10ge_cmd cmd;
718 int status;
719 size_t bytes;
720 u32 len;
34fdccea
BG		 721 struct page *dmatest_page;
722 dma_addr_t dmatest_bus;
0da34b6d
BG		 723
724 /* try to send a reset command to the card to see if it
725 * is alive */
726 memset(&cmd, 0, sizeof(cmd));
727 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
728 if (status != 0) {
729 dev_err(&mgp->pdev->dev, "failed reset\n");
730 return -ENXIO;
731 }
34fdccea
BG		 732 dmatest_page = alloc_page(GFP_KERNEL);
733 if (!dmatest_page)
734 return -ENOMEM;
735 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
736 DMA_BIDIRECTIONAL);
0da34b6d
BG		 737
738 /* Now exchange information about interrupts */
739
740 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
741 memset(mgp->rx_done.entry, 0, bytes);
742 cmd.data0 = (u32) bytes;
743 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
744 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
745 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
746 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
747
748 status |=
749 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
40f6cff5 750 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
df30a740
BG		 751 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
752 &cmd, 0);
753 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 754
0da34b6d
BG		 755 status |= myri10ge_send_cmd
756 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 757 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 758 if (status != 0) {
759 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
760 return status;
761 }
40f6cff5 762 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 763
764 /* Run a small DMA test.
765 * The magic multipliers to the length tell the firmware
766 * to do DMA read, write, or read+write tests. The
767 * results are returned in cmd.data0. The upper 16
768 * bits or the return is the number of transfers completed.
769 * The lower 16 bits is the time in 0.5us ticks that the
770 * transfers took to complete.
771 */
772
773 len = mgp->tx.boundary;
774
34fdccea
BG		 775 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
776 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
0da34b6d
BG		 777 cmd.data2 = len * 0x10000;
778 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
779 if (status == 0)
780 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) /
781 (cmd.data0 & 0xffff);
782 else
783 dev_warn(&mgp->pdev->dev, "DMA read benchmark failed: %d\n",
784 status);
34fdccea
BG		 785 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
786 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
0da34b6d
BG		 787 cmd.data2 = len * 0x1;
788 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
789 if (status == 0)
790 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) /
791 (cmd.data0 & 0xffff);
792 else
793 dev_warn(&mgp->pdev->dev, "DMA write benchmark failed: %d\n",
794 status);
795
34fdccea
BG		 796 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
797 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
0da34b6d
BG		 798 cmd.data2 = len * 0x10001;
799 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
800 if (status == 0)
801 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
802 (cmd.data0 & 0xffff);
803 else
804 dev_warn(&mgp->pdev->dev,
805 "DMA read/write benchmark failed: %d\n", status);
806
34fdccea
BG		 807 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
808 put_page(dmatest_page);
809
0da34b6d
BG		 810 memset(mgp->rx_done.entry, 0, bytes);
811
812 /* reset mcp/driver shared state back to 0 */
813 mgp->tx.req = 0;
814 mgp->tx.done = 0;
815 mgp->tx.pkt_start = 0;
816 mgp->tx.pkt_done = 0;
817 mgp->rx_big.cnt = 0;
818 mgp->rx_small.cnt = 0;
819 mgp->rx_done.idx = 0;
820 mgp->rx_done.cnt = 0;
c58ac5ca 821 mgp->link_changes = 0;
0da34b6d
BG		 822 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
823 myri10ge_change_promisc(mgp, 0, 0);
824 myri10ge_change_pause(mgp, mgp->pause);
9dc6f0e7
BG		 825 if (mgp->adopted_rx_filter_bug)
826 (void)myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
0da34b6d
BG		 827 return status;
828}
829
830static inline void
831myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
832 struct mcp_kreq_ether_recv *src)
833{
40f6cff5 834 __be32 low;
0da34b6d
BG		 835
836 low = src->addr_low;
40f6cff5 837 src->addr_low = htonl(DMA_32BIT_MASK);
e67bda55
BG		 838 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
839 mb();
840 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 841 mb();
842 src->addr_low = low;
40f6cff5 843 put_be32(low, &dst->addr_low);
0da34b6d
BG		 844 mb();
845}
846
40f6cff5 847static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 848{
849 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
850
40f6cff5 851 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 852 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
853 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
854 skb->csum = hw_csum;
84fa7933 855 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 856 }
857}
858
dd50f336
BG		 859static inline void
860myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
861 struct skb_frag_struct *rx_frags, int len, int hlen)
862{
863 struct skb_frag_struct *skb_frags;
864
865 skb->len = skb->data_len = len;
866 skb->truesize = len + sizeof(struct sk_buff);
867 /* attach the page(s) */
868
869 skb_frags = skb_shinfo(skb)->frags;
870 while (len > 0) {
871 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
872 len -= rx_frags->size;
873 skb_frags++;
874 rx_frags++;
875 skb_shinfo(skb)->nr_frags++;
876 }
877
878 /* pskb_may_pull is not available in irq context, but
879 * skb_pull() (for ether_pad and eth_type_trans()) requires
880 * the beginning of the packet in skb_headlen(), move it
881 * manually */
882 memcpy(skb->data, va, hlen);
883 skb_shinfo(skb)->frags[0].page_offset += hlen;
884 skb_shinfo(skb)->frags[0].size -= hlen;
885 skb->data_len -= hlen;
886 skb->tail += hlen;
887 skb_pull(skb, MXGEFW_PAD);
888}
889
890static void
891myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
892 int bytes, int watchdog)
893{
894 struct page *page;
895 int idx;
896
897 if (unlikely(rx->watchdog_needed && !watchdog))
898 return;
899
900 /* try to refill entire ring */
901 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
902 idx = rx->fill_cnt & rx->mask;
ae8509b1 903 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 904 /* we can use part of previous page */
905 get_page(rx->page);
906 } else {
907 /* we need a new page */
908 page =
909 alloc_pages(GFP_ATOMIC | __GFP_COMP,
910 MYRI10GE_ALLOC_ORDER);
911 if (unlikely(page == NULL)) {
912 if (rx->fill_cnt - rx->cnt < 16)
913 rx->watchdog_needed = 1;
914 return;
915 }
916 rx->page = page;
917 rx->page_offset = 0;
918 rx->bus = pci_map_page(mgp->pdev, page, 0,
919 MYRI10GE_ALLOC_SIZE,
920 PCI_DMA_FROMDEVICE);
921 }
922 rx->info[idx].page = rx->page;
923 rx->info[idx].page_offset = rx->page_offset;
924 /* note that this is the address of the start of the
925 * page */
926 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
927 rx->shadow[idx].addr_low =
928 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
929 rx->shadow[idx].addr_high =
930 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
931
932 /* start next packet on a cacheline boundary */
933 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 934
935#if MYRI10GE_ALLOC_SIZE > 4096
936 /* don't cross a 4KB boundary */
937 if ((rx->page_offset >> 12) !=
938 ((rx->page_offset + bytes - 1) >> 12))
939 rx->page_offset = (rx->page_offset + 4096) & ~4095;
940#endif
dd50f336
BG		 941 rx->fill_cnt++;
942
943 /* copy 8 descriptors to the firmware at a time */
944 if ((idx & 7) == 7) {
945 if (rx->wc_fifo == NULL)
946 myri10ge_submit_8rx(&rx->lanai[idx - 7],
947 &rx->shadow[idx - 7]);
948 else {
949 mb();
950 myri10ge_pio_copy(rx->wc_fifo,
951 &rx->shadow[idx - 7], 64);
952 }
953 }
954 }
955}
956
957static inline void
958myri10ge_unmap_rx_page(struct pci_dev *pdev,
959 struct myri10ge_rx_buffer_state *info, int bytes)
960{
961 /* unmap the recvd page if we're the only or last user of it */
962 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
963 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
964 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
965 & ~(MYRI10GE_ALLOC_SIZE - 1)),
966 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
967 }
968}
969
970#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
971 * page into an skb */
972
973static inline int
52ea6fb3
BG		 974myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
975 int bytes, int len, __wsum csum)
dd50f336
BG		 976{
977 struct sk_buff *skb;
978 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
979 int i, idx, hlen, remainder;
980 struct pci_dev *pdev = mgp->pdev;
981 struct net_device *dev = mgp->dev;
982 u8 *va;
983
984 len += MXGEFW_PAD;
985 idx = rx->cnt & rx->mask;
986 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
987 prefetch(va);
988 /* Fill skb_frag_struct(s) with data from our receive */
989 for (i = 0, remainder = len; remainder > 0; i++) {
990 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
991 rx_frags[i].page = rx->info[idx].page;
992 rx_frags[i].page_offset = rx->info[idx].page_offset;
993 if (remainder < MYRI10GE_ALLOC_SIZE)
994 rx_frags[i].size = remainder;
995 else
996 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
997 rx->cnt++;
998 idx = rx->cnt & rx->mask;
999 remainder -= MYRI10GE_ALLOC_SIZE;
1000 }
1001
1002 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1003
1004 /* allocate an skb to attach the page(s) to. */
1005
1006 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1007 if (unlikely(skb == NULL)) {
1008 mgp->stats.rx_dropped++;
1009 do {
1010 i--;
1011 put_page(rx_frags[i].page);
1012 } while (i != 0);
1013 return 0;
1014 }
1015
1016 /* Attach the pages to the skb, and trim off any padding */
1017 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1018 if (skb_shinfo(skb)->frags[0].size <= 0) {
1019 put_page(skb_shinfo(skb)->frags[0].page);
1020 skb_shinfo(skb)->nr_frags = 0;
1021 }
1022 skb->protocol = eth_type_trans(skb, dev);
dd50f336
BG		 1023
1024 if (mgp->csum_flag) {
1025 if ((skb->protocol == htons(ETH_P_IP)) ||
1026 (skb->protocol == htons(ETH_P_IPV6))) {
1027 skb->csum = csum;
1028 skb->ip_summed = CHECKSUM_COMPLETE;
1029 } else
1030 myri10ge_vlan_ip_csum(skb, csum);
1031 }
1032 netif_receive_skb(skb);
1033 dev->last_rx = jiffies;
1034 return 1;
1035}
1036
0da34b6d
BG		 1037static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1038{
1039 struct pci_dev *pdev = mgp->pdev;
1040 struct myri10ge_tx_buf *tx = &mgp->tx;
1041 struct sk_buff *skb;
1042 int idx, len;
1043 int limit = 0;
1044
1045 while (tx->pkt_done != mcp_index) {
1046 idx = tx->done & tx->mask;
1047 skb = tx->info[idx].skb;
1048
1049 /* Mark as free */
1050 tx->info[idx].skb = NULL;
1051 if (tx->info[idx].last) {
1052 tx->pkt_done++;
1053 tx->info[idx].last = 0;
1054 }
1055 tx->done++;
1056 len = pci_unmap_len(&tx->info[idx], len);
1057 pci_unmap_len_set(&tx->info[idx], len, 0);
1058 if (skb) {
1059 mgp->stats.tx_bytes += skb->len;
1060 mgp->stats.tx_packets++;
1061 dev_kfree_skb_irq(skb);
1062 if (len)
1063 pci_unmap_single(pdev,
1064 pci_unmap_addr(&tx->info[idx],
1065 bus), len,
1066 PCI_DMA_TODEVICE);
1067 } else {
1068 if (len)
1069 pci_unmap_page(pdev,
1070 pci_unmap_addr(&tx->info[idx],
1071 bus), len,
1072 PCI_DMA_TODEVICE);
1073 }
1074
1075 /* limit potential for livelock by only handling
1076 * 2 full tx rings per call */
1077 if (unlikely(++limit > 2 * tx->mask))
1078 break;
1079 }
1080 /* start the queue if we've stopped it */
1081 if (netif_queue_stopped(mgp->dev)
1082 && tx->req - tx->done < (tx->mask >> 1)) {
1083 mgp->wake_queue++;
1084 netif_wake_queue(mgp->dev);
1085 }
1086}
1087
1088static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit)
1089{
1090 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1091 unsigned long rx_bytes = 0;
1092 unsigned long rx_packets = 0;
1093 unsigned long rx_ok;
1094
1095 int idx = rx_done->idx;
1096 int cnt = rx_done->cnt;
1097 u16 length;
40f6cff5 1098 __wsum checksum;
0da34b6d
BG		 1099
1100 while (rx_done->entry[idx].length != 0 && *limit != 0) {
1101 length = ntohs(rx_done->entry[idx].length);
1102 rx_done->entry[idx].length = 0;
40f6cff5 1103 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1104 if (length <= mgp->small_bytes)
52ea6fb3
BG		 1105 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1106 mgp->small_bytes,
1107 length, checksum);
0da34b6d 1108 else
52ea6fb3
BG		 1109 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1110 mgp->big_bytes,
1111 length, checksum);
0da34b6d
BG		 1112 rx_packets += rx_ok;
1113 rx_bytes += rx_ok * (unsigned long)length;
1114 cnt++;
1115 idx = cnt & (myri10ge_max_intr_slots - 1);
1116
1117 /* limit potential for livelock by only handling a
1118 * limited number of frames. */
1119 (*limit)--;
1120 }
1121 rx_done->idx = idx;
1122 rx_done->cnt = cnt;
1123 mgp->stats.rx_packets += rx_packets;
1124 mgp->stats.rx_bytes += rx_bytes;
c7dab99b
BG		 1125
1126 /* restock receive rings if needed */
1127 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1128 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1129 mgp->small_bytes + MXGEFW_PAD, 0);
1130 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1131 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1132
0da34b6d
BG		 1133}
1134
1135static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1136{
1137 struct mcp_irq_data *stats = mgp->fw_stats;
1138
1139 if (unlikely(stats->stats_updated)) {
1140 if (mgp->link_state != stats->link_up) {
1141 mgp->link_state = stats->link_up;
1142 if (mgp->link_state) {
c58ac5ca
BG		 1143 if (netif_msg_link(mgp))
1144 printk(KERN_INFO
1145 "myri10ge: %s: link up\n",
1146 mgp->dev->name);
0da34b6d 1147 netif_carrier_on(mgp->dev);
c58ac5ca 1148 mgp->link_changes++;
0da34b6d 1149 } else {
c58ac5ca
BG		 1150 if (netif_msg_link(mgp))
1151 printk(KERN_INFO
1152 "myri10ge: %s: link down\n",
1153 mgp->dev->name);
0da34b6d 1154 netif_carrier_off(mgp->dev);
c58ac5ca 1155 mgp->link_changes++;
0da34b6d
BG		 1156 }
1157 }
1158 if (mgp->rdma_tags_available !=
1159 ntohl(mgp->fw_stats->rdma_tags_available)) {
1160 mgp->rdma_tags_available =
1161 ntohl(mgp->fw_stats->rdma_tags_available);
1162 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1163 "%d tags left\n", mgp->dev->name,
1164 mgp->rdma_tags_available);
1165 }
1166 mgp->down_cnt += stats->link_down;
1167 if (stats->link_down)
1168 wake_up(&mgp->down_wq);
1169 }
1170}
1171
1172static int myri10ge_poll(struct net_device *netdev, int *budget)
1173{
1174 struct myri10ge_priv *mgp = netdev_priv(netdev);
1175 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1176 int limit, orig_limit, work_done;
1177
1178 /* process as many rx events as NAPI will allow */
1179 limit = min(*budget, netdev->quota);
1180 orig_limit = limit;
1181 myri10ge_clean_rx_done(mgp, &limit);
1182 work_done = orig_limit - limit;
1183 *budget -= work_done;
1184 netdev->quota -= work_done;
1185
1186 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1187 netif_rx_complete(netdev);
40f6cff5 1188 put_be32(htonl(3), mgp->irq_claim);
0da34b6d
BG		 1189 return 0;
1190 }
1191 return 1;
1192}
1193
7d12e780 1194static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d
BG		 1195{
1196 struct myri10ge_priv *mgp = arg;
1197 struct mcp_irq_data *stats = mgp->fw_stats;
1198 struct myri10ge_tx_buf *tx = &mgp->tx;
1199 u32 send_done_count;
1200 int i;
1201
1202 /* make sure it is our IRQ, and that the DMA has finished */
1203 if (unlikely(!stats->valid))
1204 return (IRQ_NONE);
1205
1206 /* low bit indicates receives are present, so schedule
1207 * napi poll handler */
1208 if (stats->valid & 1)
1209 netif_rx_schedule(mgp->dev);
1210
1211 if (!mgp->msi_enabled) {
40f6cff5 1212 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1213 if (!myri10ge_deassert_wait)
1214 stats->valid = 0;
1215 mb();
1216 } else
1217 stats->valid = 0;
1218
1219 /* Wait for IRQ line to go low, if using INTx */
1220 i = 0;
1221 while (1) {
1222 i++;
1223 /* check for transmit completes and receives */
1224 send_done_count = ntohl(stats->send_done_count);
1225 if (send_done_count != tx->pkt_done)
1226 myri10ge_tx_done(mgp, (int)send_done_count);
1227 if (unlikely(i > myri10ge_max_irq_loops)) {
1228 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1229 mgp->dev->name);
1230 stats->valid = 0;
1231 schedule_work(&mgp->watchdog_work);
1232 }
1233 if (likely(stats->valid == 0))
1234 break;
1235 cpu_relax();
1236 barrier();
1237 }
1238
1239 myri10ge_check_statblock(mgp);
1240
40f6cff5 1241 put_be32(htonl(3), mgp->irq_claim + 1);
0da34b6d
BG		 1242 return (IRQ_HANDLED);
1243}
1244
1245static int
1246myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1247{
1248 cmd->autoneg = AUTONEG_DISABLE;
1249 cmd->speed = SPEED_10000;
1250 cmd->duplex = DUPLEX_FULL;
1251 return 0;
1252}
1253
1254static void
1255myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1256{
1257 struct myri10ge_priv *mgp = netdev_priv(netdev);
1258
1259 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1260 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1261 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1262 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1263}
1264
1265static int
1266myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1267{
1268 struct myri10ge_priv *mgp = netdev_priv(netdev);
1269 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1270 return 0;
1271}
1272
1273static int
1274myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1275{
1276 struct myri10ge_priv *mgp = netdev_priv(netdev);
1277
1278 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1279 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1280 return 0;
1281}
1282
1283static void
1284myri10ge_get_pauseparam(struct net_device *netdev,
1285 struct ethtool_pauseparam *pause)
1286{
1287 struct myri10ge_priv *mgp = netdev_priv(netdev);
1288
1289 pause->autoneg = 0;
1290 pause->rx_pause = mgp->pause;
1291 pause->tx_pause = mgp->pause;
1292}
1293
1294static int
1295myri10ge_set_pauseparam(struct net_device *netdev,
1296 struct ethtool_pauseparam *pause)
1297{
1298 struct myri10ge_priv *mgp = netdev_priv(netdev);
1299
1300 if (pause->tx_pause != mgp->pause)
1301 return myri10ge_change_pause(mgp, pause->tx_pause);
1302 if (pause->rx_pause != mgp->pause)
1303 return myri10ge_change_pause(mgp, pause->tx_pause);
1304 if (pause->autoneg != 0)
1305 return -EINVAL;
1306 return 0;
1307}
1308
1309static void
1310myri10ge_get_ringparam(struct net_device *netdev,
1311 struct ethtool_ringparam *ring)
1312{
1313 struct myri10ge_priv *mgp = netdev_priv(netdev);
1314
1315 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1316 ring->rx_max_pending = mgp->rx_big.mask + 1;
1317 ring->rx_jumbo_max_pending = 0;
1318 ring->tx_max_pending = mgp->rx_small.mask + 1;
1319 ring->rx_mini_pending = ring->rx_mini_max_pending;
1320 ring->rx_pending = ring->rx_max_pending;
1321 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1322 ring->tx_pending = ring->tx_max_pending;
1323}
1324
1325static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1326{
1327 struct myri10ge_priv *mgp = netdev_priv(netdev);
1328 if (mgp->csum_flag)
1329 return 1;
1330 else
1331 return 0;
1332}
1333
1334static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1335{
1336 struct myri10ge_priv *mgp = netdev_priv(netdev);
1337 if (csum_enabled)
1338 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1339 else
1340 mgp->csum_flag = 0;
1341 return 0;
1342}
1343
1344static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1345 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1346 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1347 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1348 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1349 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1350 "tx_heartbeat_errors", "tx_window_errors",
1351 /* device-specific stats */
2c1a1088 1352 "tx_boundary", "WC", "irq", "MSI",
0da34b6d
BG		 1353 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1354 "serial_number", "tx_pkt_start", "tx_pkt_done",
1355 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1356 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
c58ac5ca 1357 "link_changes", "link_up", "dropped_link_overflow",
85a7ea1b 1358 "dropped_link_error_or_filtered", "dropped_multicast_filtered",
0da34b6d
BG		 1359 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1360 "dropped_no_big_buffer"
1361};
1362
1363#define MYRI10GE_NET_STATS_LEN 21
1364#define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1365
1366static void
1367myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1368{
1369 switch (stringset) {
1370 case ETH_SS_STATS:
1371 memcpy(data, *myri10ge_gstrings_stats,
1372 sizeof(myri10ge_gstrings_stats));
1373 break;
1374 }
1375}
1376
1377static int myri10ge_get_stats_count(struct net_device *netdev)
1378{
1379 return MYRI10GE_STATS_LEN;
1380}
1381
1382static void
1383myri10ge_get_ethtool_stats(struct net_device *netdev,
1384 struct ethtool_stats *stats, u64 * data)
1385{
1386 struct myri10ge_priv *mgp = netdev_priv(netdev);
1387 int i;
1388
1389 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1390 data[i] = ((unsigned long *)&mgp->stats)[i];
1391
2c1a1088 1392 data[i++] = (unsigned int)mgp->tx.boundary;
276e26c3 1393 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1394 data[i++] = (unsigned int)mgp->pdev->irq;
1395 data[i++] = (unsigned int)mgp->msi_enabled;
0da34b6d
BG		 1396 data[i++] = (unsigned int)mgp->read_dma;
1397 data[i++] = (unsigned int)mgp->write_dma;
1398 data[i++] = (unsigned int)mgp->read_write_dma;
1399 data[i++] = (unsigned int)mgp->serial_number;
1400 data[i++] = (unsigned int)mgp->tx.pkt_start;
1401 data[i++] = (unsigned int)mgp->tx.pkt_done;
1402 data[i++] = (unsigned int)mgp->tx.req;
1403 data[i++] = (unsigned int)mgp->tx.done;
1404 data[i++] = (unsigned int)mgp->rx_small.cnt;
1405 data[i++] = (unsigned int)mgp->rx_big.cnt;
1406 data[i++] = (unsigned int)mgp->wake_queue;
1407 data[i++] = (unsigned int)mgp->stop_queue;
1408 data[i++] = (unsigned int)mgp->watchdog_resets;
1409 data[i++] = (unsigned int)mgp->tx_linearized;
c58ac5ca 1410 data[i++] = (unsigned int)mgp->link_changes;
0da34b6d
BG		 1411 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1412 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1413 data[i++] =
1414 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
85a7ea1b
BG		 1415 data[i++] =
1416 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
0da34b6d
BG		 1417 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1418 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1419 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1420 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1421}
1422
c58ac5ca
BG		 1423static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1424{
1425 struct myri10ge_priv *mgp = netdev_priv(netdev);
1426 mgp->msg_enable = value;
1427}
1428
1429static u32 myri10ge_get_msglevel(struct net_device *netdev)
1430{
1431 struct myri10ge_priv *mgp = netdev_priv(netdev);
1432 return mgp->msg_enable;
1433}
1434
7282d491 1435static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1436 .get_settings = myri10ge_get_settings,
1437 .get_drvinfo = myri10ge_get_drvinfo,
1438 .get_coalesce = myri10ge_get_coalesce,
1439 .set_coalesce = myri10ge_set_coalesce,
1440 .get_pauseparam = myri10ge_get_pauseparam,
1441 .set_pauseparam = myri10ge_set_pauseparam,
1442 .get_ringparam = myri10ge_get_ringparam,
1443 .get_rx_csum = myri10ge_get_rx_csum,
1444 .set_rx_csum = myri10ge_set_rx_csum,
1445 .get_tx_csum = ethtool_op_get_tx_csum,
b10c0668 1446 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d
BG		 1447 .get_sg = ethtool_op_get_sg,
1448 .set_sg = ethtool_op_set_sg,
0da34b6d
BG		 1449 .get_tso = ethtool_op_get_tso,
1450 .set_tso = ethtool_op_set_tso,
0da34b6d
BG		 1451 .get_strings = myri10ge_get_strings,
1452 .get_stats_count = myri10ge_get_stats_count,
c58ac5ca
BG		 1453 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1454 .set_msglevel = myri10ge_set_msglevel,
1455 .get_msglevel = myri10ge_get_msglevel
0da34b6d
BG		 1456};
1457
1458static int myri10ge_allocate_rings(struct net_device *dev)
1459{
1460 struct myri10ge_priv *mgp;
1461 struct myri10ge_cmd cmd;
1462 int tx_ring_size, rx_ring_size;
1463 int tx_ring_entries, rx_ring_entries;
1464 int i, status;
1465 size_t bytes;
1466
1467 mgp = netdev_priv(dev);
1468
1469 /* get ring sizes */
1470
1471 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1472 tx_ring_size = cmd.data0;
1473 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1474 if (status != 0)
1475 return status;
0da34b6d
BG		 1476 rx_ring_size = cmd.data0;
1477
1478 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1479 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1480 mgp->tx.mask = tx_ring_entries - 1;
1481 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1482
355c7265
BG		 1483 status = -ENOMEM;
1484
0da34b6d
BG		 1485 /* allocate the host shadow rings */
1486
1487 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1488 * sizeof(*mgp->tx.req_list);
1489 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1490 if (mgp->tx.req_bytes == NULL)
1491 goto abort_with_nothing;
1492
1493 /* ensure req_list entries are aligned to 8 bytes */
1494 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1495 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1496
1497 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1498 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1499 if (mgp->rx_small.shadow == NULL)
1500 goto abort_with_tx_req_bytes;
1501
1502 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1503 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1504 if (mgp->rx_big.shadow == NULL)
1505 goto abort_with_rx_small_shadow;
1506
1507 /* allocate the host info rings */
1508
1509 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1510 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1511 if (mgp->tx.info == NULL)
1512 goto abort_with_rx_big_shadow;
1513
1514 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1515 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1516 if (mgp->rx_small.info == NULL)
1517 goto abort_with_tx_info;
1518
1519 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1520 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1521 if (mgp->rx_big.info == NULL)
1522 goto abort_with_rx_small_info;
1523
1524 /* Fill the receive rings */
c7dab99b
BG		 1525 mgp->rx_big.cnt = 0;
1526 mgp->rx_small.cnt = 0;
1527 mgp->rx_big.fill_cnt = 0;
1528 mgp->rx_small.fill_cnt = 0;
1529 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1530 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1531 mgp->rx_small.watchdog_needed = 0;
1532 mgp->rx_big.watchdog_needed = 0;
1533 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1534 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1535
c7dab99b
BG		 1536 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1537 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1538 dev->name, mgp->rx_small.fill_cnt);
1539 goto abort_with_rx_small_ring;
0da34b6d
BG		 1540 }
1541
c7dab99b
BG		 1542 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1543 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1544 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1545 dev->name, mgp->rx_big.fill_cnt);
1546 goto abort_with_rx_big_ring;
0da34b6d
BG		 1547 }
1548
1549 return 0;
1550
1551abort_with_rx_big_ring:
c7dab99b
BG		 1552 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1553 int idx = i & mgp->rx_big.mask;
1554 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1555 mgp->big_bytes);
1556 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1557 }
1558
1559abort_with_rx_small_ring:
c7dab99b
BG		 1560 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1561 int idx = i & mgp->rx_small.mask;
1562 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1563 mgp->small_bytes + MXGEFW_PAD);
1564 put_page(mgp->rx_small.info[idx].page);
0da34b6d 1565 }
c7dab99b 1566
0da34b6d
BG		 1567 kfree(mgp->rx_big.info);
1568
1569abort_with_rx_small_info:
1570 kfree(mgp->rx_small.info);
1571
1572abort_with_tx_info:
1573 kfree(mgp->tx.info);
1574
1575abort_with_rx_big_shadow:
1576 kfree(mgp->rx_big.shadow);
1577
1578abort_with_rx_small_shadow:
1579 kfree(mgp->rx_small.shadow);
1580
1581abort_with_tx_req_bytes:
1582 kfree(mgp->tx.req_bytes);
1583 mgp->tx.req_bytes = NULL;
1584 mgp->tx.req_list = NULL;
1585
1586abort_with_nothing:
1587 return status;
1588}
1589
1590static void myri10ge_free_rings(struct net_device *dev)
1591{
1592 struct myri10ge_priv *mgp;
1593 struct sk_buff *skb;
1594 struct myri10ge_tx_buf *tx;
1595 int i, len, idx;
1596
1597 mgp = netdev_priv(dev);
1598
c7dab99b
BG		 1599 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1600 idx = i & mgp->rx_big.mask;
1601 if (i == mgp->rx_big.fill_cnt - 1)
1602 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1603 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1604 mgp->big_bytes);
1605 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1606 }
1607
c7dab99b
BG		 1608 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1609 idx = i & mgp->rx_small.mask;
1610 if (i == mgp->rx_small.fill_cnt - 1)
1611 mgp->rx_small.info[idx].page_offset =
1612 MYRI10GE_ALLOC_SIZE;
1613 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1614 mgp->small_bytes + MXGEFW_PAD);
1615 put_page(mgp->rx_small.info[idx].page);
1616 }
0da34b6d
BG		 1617 tx = &mgp->tx;
1618 while (tx->done != tx->req) {
1619 idx = tx->done & tx->mask;
1620 skb = tx->info[idx].skb;
1621
1622 /* Mark as free */
1623 tx->info[idx].skb = NULL;
1624 tx->done++;
1625 len = pci_unmap_len(&tx->info[idx], len);
1626 pci_unmap_len_set(&tx->info[idx], len, 0);
1627 if (skb) {
1628 mgp->stats.tx_dropped++;
1629 dev_kfree_skb_any(skb);
1630 if (len)
1631 pci_unmap_single(mgp->pdev,
1632 pci_unmap_addr(&tx->info[idx],
1633 bus), len,
1634 PCI_DMA_TODEVICE);
1635 } else {
1636 if (len)
1637 pci_unmap_page(mgp->pdev,
1638 pci_unmap_addr(&tx->info[idx],
1639 bus), len,
1640 PCI_DMA_TODEVICE);
1641 }
1642 }
1643 kfree(mgp->rx_big.info);
1644
1645 kfree(mgp->rx_small.info);
1646
1647 kfree(mgp->tx.info);
1648
1649 kfree(mgp->rx_big.shadow);
1650
1651 kfree(mgp->rx_small.shadow);
1652
1653 kfree(mgp->tx.req_bytes);
1654 mgp->tx.req_bytes = NULL;
1655 mgp->tx.req_list = NULL;
1656}
1657
df30a740
BG		 1658static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1659{
1660 struct pci_dev *pdev = mgp->pdev;
1661 int status;
1662
1663 if (myri10ge_msi) {
1664 status = pci_enable_msi(pdev);
1665 if (status != 0)
1666 dev_err(&pdev->dev,
1667 "Error %d setting up MSI; falling back to xPIC\n",
1668 status);
1669 else
1670 mgp->msi_enabled = 1;
1671 } else {
1672 mgp->msi_enabled = 0;
1673 }
1674 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1675 mgp->dev->name, mgp);
1676 if (status != 0) {
1677 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1678 if (mgp->msi_enabled)
1679 pci_disable_msi(pdev);
1680 }
1681 return status;
1682}
1683
1684static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1685{
1686 struct pci_dev *pdev = mgp->pdev;
1687
1688 free_irq(pdev->irq, mgp);
1689 if (mgp->msi_enabled)
1690 pci_disable_msi(pdev);
1691}
1692
0da34b6d
BG		 1693static int myri10ge_open(struct net_device *dev)
1694{
1695 struct myri10ge_priv *mgp;
1696 struct myri10ge_cmd cmd;
1697 int status, big_pow2;
1698
1699 mgp = netdev_priv(dev);
1700
1701 if (mgp->running != MYRI10GE_ETH_STOPPED)
1702 return -EBUSY;
1703
1704 mgp->running = MYRI10GE_ETH_STARTING;
1705 status = myri10ge_reset(mgp);
1706 if (status != 0) {
1707 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 1708 goto abort_with_nothing;
0da34b6d
BG		 1709 }
1710
df30a740
BG		 1711 status = myri10ge_request_irq(mgp);
1712 if (status != 0)
1713 goto abort_with_nothing;
1714
0da34b6d
BG		 1715 /* decide what small buffer size to use. For good TCP rx
1716 * performance, it is important to not receive 1514 byte
1717 * frames into jumbo buffers, as it confuses the socket buffer
1718 * accounting code, leading to drops and erratic performance.
1719 */
1720
1721 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 1722 /* enough for a TCP header */
1723 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1724 ? (128 - MXGEFW_PAD)
1725 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 1726 else
de3c4507
BG		 1727 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1728 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 1729
1730 /* Override the small buffer size? */
1731 if (myri10ge_small_bytes > 0)
1732 mgp->small_bytes = myri10ge_small_bytes;
1733
0da34b6d
BG		 1734 /* get the lanai pointers to the send and receive rings */
1735
1736 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1737 mgp->tx.lanai =
1738 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1739
1740 status |=
1741 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1742 mgp->rx_small.lanai =
1743 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1744
1745 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1746 mgp->rx_big.lanai =
1747 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1748
1749 if (status != 0) {
1750 printk(KERN_ERR
1751 "myri10ge: %s: failed to get ring sizes or locations\n",
1752 dev->name);
1753 mgp->running = MYRI10GE_ETH_STOPPED;
df30a740 1754 goto abort_with_irq;
0da34b6d
BG		 1755 }
1756
276e26c3 1757 if (myri10ge_wcfifo && mgp->wc_enabled) {
e700f9f4
BG		 1758 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1759 mgp->rx_small.wc_fifo =
1760 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1761 mgp->rx_big.wc_fifo =
1762 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
0da34b6d
BG		 1763 } else {
1764 mgp->tx.wc_fifo = NULL;
1765 mgp->rx_small.wc_fifo = NULL;
1766 mgp->rx_big.wc_fifo = NULL;
1767 }
1768
0da34b6d
BG		 1769 /* Firmware needs the big buff size as a power of 2. Lie and
1770 * tell him the buffer is larger, because we only use 1
1771 * buffer/pkt, and the mtu will prevent overruns.
1772 */
13348bee 1773 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1774 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
1775 while ((big_pow2 & (big_pow2 - 1)) != 0)
1776 big_pow2++;
13348bee 1777 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1778 } else {
1779 big_pow2 = MYRI10GE_ALLOC_SIZE;
1780 mgp->big_bytes = big_pow2;
1781 }
1782
1783 status = myri10ge_allocate_rings(dev);
1784 if (status != 0)
df30a740 1785 goto abort_with_irq;
0da34b6d
BG		 1786
1787 /* now give firmware buffers sizes, and MTU */
1788 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1789 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1790 cmd.data0 = mgp->small_bytes;
1791 status |=
1792 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1793 cmd.data0 = big_pow2;
1794 status |=
1795 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1796 if (status) {
1797 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1798 dev->name);
1799 goto abort_with_rings;
1800 }
1801
1802 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1803 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
85a7ea1b
BG		 1804 cmd.data2 = sizeof(struct mcp_irq_data);
1805 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1806 if (status == -ENOSYS) {
1807 dma_addr_t bus = mgp->fw_stats_bus;
1808 bus += offsetof(struct mcp_irq_data, send_done_count);
1809 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1810 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1811 status = myri10ge_send_cmd(mgp,
1812 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1813 &cmd, 0);
1814 /* Firmware cannot support multicast without STATS_DMA_V2 */
1815 mgp->fw_multicast_support = 0;
1816 } else {
1817 mgp->fw_multicast_support = 1;
1818 }
0da34b6d
BG		 1819 if (status) {
1820 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1821 dev->name);
1822 goto abort_with_rings;
1823 }
1824
40f6cff5 1825 mgp->link_state = htonl(~0U);
0da34b6d
BG		 1826 mgp->rdma_tags_available = 15;
1827
1828 netif_poll_enable(mgp->dev); /* must happen prior to any irq */
1829
1830 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1831 if (status) {
1832 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1833 dev->name);
1834 goto abort_with_rings;
1835 }
1836
1837 mgp->wake_queue = 0;
1838 mgp->stop_queue = 0;
1839 mgp->running = MYRI10GE_ETH_RUNNING;
1840 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1841 add_timer(&mgp->watchdog_timer);
1842 netif_wake_queue(dev);
1843 return 0;
1844
1845abort_with_rings:
1846 myri10ge_free_rings(dev);
1847
df30a740
BG		 1848abort_with_irq:
1849 myri10ge_free_irq(mgp);
1850
0da34b6d
BG		 1851abort_with_nothing:
1852 mgp->running = MYRI10GE_ETH_STOPPED;
1853 return -ENOMEM;
1854}
1855
1856static int myri10ge_close(struct net_device *dev)
1857{
1858 struct myri10ge_priv *mgp;
1859 struct myri10ge_cmd cmd;
1860 int status, old_down_cnt;
1861
1862 mgp = netdev_priv(dev);
1863
1864 if (mgp->running != MYRI10GE_ETH_RUNNING)
1865 return 0;
1866
1867 if (mgp->tx.req_bytes == NULL)
1868 return 0;
1869
1870 del_timer_sync(&mgp->watchdog_timer);
1871 mgp->running = MYRI10GE_ETH_STOPPING;
1872 netif_poll_disable(mgp->dev);
1873 netif_carrier_off(dev);
1874 netif_stop_queue(dev);
1875 old_down_cnt = mgp->down_cnt;
1876 mb();
1877 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
1878 if (status)
1879 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
1880 dev->name);
1881
1882 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
1883 if (old_down_cnt == mgp->down_cnt)
1884 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
1885
1886 netif_tx_disable(dev);
df30a740 1887 myri10ge_free_irq(mgp);
0da34b6d
BG		 1888 myri10ge_free_rings(dev);
1889
1890 mgp->running = MYRI10GE_ETH_STOPPED;
1891 return 0;
1892}
1893
1894/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1895 * backwards one at a time and handle ring wraps */
1896
1897static inline void
1898myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
1899 struct mcp_kreq_ether_send *src, int cnt)
1900{
1901 int idx, starting_slot;
1902 starting_slot = tx->req;
1903 while (cnt > 1) {
1904 cnt--;
1905 idx = (starting_slot + cnt) & tx->mask;
1906 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1907 mb();
1908 }
1909}
1910
1911/*
1912 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1913 * at most 32 bytes at a time, so as to avoid involving the software
1914 * pio handler in the nic. We re-write the first segment's flags
1915 * to mark them valid only after writing the entire chain.
1916 */
1917
1918static inline void
1919myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
1920 int cnt)
1921{
1922 int idx, i;
1923 struct mcp_kreq_ether_send __iomem *dstp, *dst;
1924 struct mcp_kreq_ether_send *srcp;
1925 u8 last_flags;
1926
1927 idx = tx->req & tx->mask;
1928
1929 last_flags = src->flags;
1930 src->flags = 0;
1931 mb();
1932 dst = dstp = &tx->lanai[idx];
1933 srcp = src;
1934
1935 if ((idx + cnt) < tx->mask) {
1936 for (i = 0; i < (cnt - 1); i += 2) {
1937 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1938 mb(); /* force write every 32 bytes */
1939 srcp += 2;
1940 dstp += 2;
1941 }
1942 } else {
1943 /* submit all but the first request, and ensure
1944 * that it is submitted below */
1945 myri10ge_submit_req_backwards(tx, src, cnt);
1946 i = 0;
1947 }
1948 if (i < cnt) {
1949 /* submit the first request */
1950 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
1951 mb(); /* barrier before setting valid flag */
1952 }
1953
1954 /* re-write the last 32-bits with the valid flags */
1955 src->flags = last_flags;
40f6cff5 1956 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 1957 tx->req += cnt;
1958 mb();
1959}
1960
1961static inline void
1962myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1963 struct mcp_kreq_ether_send *src, int cnt)
1964{
1965 tx->req += cnt;
1966 mb();
1967 while (cnt >= 4) {
1968 myri10ge_pio_copy(tx->wc_fifo, src, 64);
1969 mb();
1970 src += 4;
1971 cnt -= 4;
1972 }
1973 if (cnt > 0) {
1974 /* pad it to 64 bytes. The src is 64 bytes bigger than it
1975 * needs to be so that we don't overrun it */
e700f9f4
BG		 1976 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
1977 src, 64);
0da34b6d
BG		 1978 mb();
1979 }
1980}
1981
1982/*
1983 * Transmit a packet. We need to split the packet so that a single
1984 * segment does not cross myri10ge->tx.boundary, so this makes segment
1985 * counting tricky. So rather than try to count segments up front, we
1986 * just give up if there are too few segments to hold a reasonably
1987 * fragmented packet currently available. If we run
1988 * out of segments while preparing a packet for DMA, we just linearize
1989 * it and try again.
1990 */
1991
1992static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
1993{
1994 struct myri10ge_priv *mgp = netdev_priv(dev);
1995 struct mcp_kreq_ether_send *req;
1996 struct myri10ge_tx_buf *tx = &mgp->tx;
1997 struct skb_frag_struct *frag;
1998 dma_addr_t bus;
40f6cff5
AV		 1999 u32 low;
2000 __be32 high_swapped;
0da34b6d
BG		 2001 unsigned int len;
2002 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2003 u16 pseudo_hdr_offset, cksum_offset;
2004 int cum_len, seglen, boundary, rdma_count;
2005 u8 flags, odd_flag;
2006
2007again:
2008 req = tx->req_list;
2009 avail = tx->mask - 1 - (tx->req - tx->done);
2010
2011 mss = 0;
2012 max_segments = MXGEFW_MAX_SEND_DESC;
2013
917690cd 2014 if (skb_is_gso(skb)) {
7967168c 2015 mss = skb_shinfo(skb)->gso_size;
917690cd 2016 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2017 }
0da34b6d
BG		 2018
2019 if ((unlikely(avail < max_segments))) {
2020 /* we are out of transmit resources */
2021 mgp->stop_queue++;
2022 netif_stop_queue(dev);
2023 return 1;
2024 }
2025
2026 /* Setup checksum offloading, if needed */
2027 cksum_offset = 0;
2028 pseudo_hdr_offset = 0;
2029 odd_flag = 0;
2030 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2031 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2032 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2033 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2034 /* If the headers are excessively large, then we must
2035 * fall back to a software checksum */
2036 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
84fa7933 2037 if (skb_checksum_help(skb))
0da34b6d
BG		 2038 goto drop;
2039 cksum_offset = 0;
2040 pseudo_hdr_offset = 0;
2041 } else {
0da34b6d
BG		 2042 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2043 flags |= MXGEFW_FLAGS_CKSUM;
2044 }
2045 }
2046
2047 cum_len = 0;
2048
0da34b6d
BG		 2049 if (mss) { /* TSO */
2050 /* this removes any CKSUM flag from before */
2051 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2052
2053 /* negative cum_len signifies to the
2054 * send loop that we are still in the
2055 * header portion of the TSO packet.
2056 * TSO header must be at most 134 bytes long */
ea2ae17d
ACM		 2057 cum_len = -(skb_transport_offset(skb) +
2058 (skb->h.th->doff << 2));
0da34b6d
BG		 2059
2060 /* for TSO, pseudo_hdr_offset holds mss.
2061 * The firmware figures out where to put
2062 * the checksum by parsing the header. */
40f6cff5 2063 pseudo_hdr_offset = mss;
0da34b6d 2064 } else
0da34b6d
BG		 2065 /* Mark small packets, and pad out tiny packets */
2066 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2067 flags |= MXGEFW_FLAGS_SMALL;
2068
2069 /* pad frames to at least ETH_ZLEN bytes */
2070 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2071 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2072 /* The packet is gone, so we must
2073 * return 0 */
2074 mgp->stats.tx_dropped += 1;
2075 return 0;
2076 }
2077 /* adjust the len to account for the zero pad
2078 * so that the nic can know how long it is */
2079 skb->len = ETH_ZLEN;
2080 }
2081 }
2082
2083 /* map the skb for DMA */
2084 len = skb->len - skb->data_len;
2085 idx = tx->req & tx->mask;
2086 tx->info[idx].skb = skb;
2087 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2088 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2089 pci_unmap_len_set(&tx->info[idx], len, len);
2090
2091 frag_cnt = skb_shinfo(skb)->nr_frags;
2092 frag_idx = 0;
2093 count = 0;
2094 rdma_count = 0;
2095
2096 /* "rdma_count" is the number of RDMAs belonging to the
2097 * current packet BEFORE the current send request. For
2098 * non-TSO packets, this is equal to "count".
2099 * For TSO packets, rdma_count needs to be reset
2100 * to 0 after a segment cut.
2101 *
2102 * The rdma_count field of the send request is
2103 * the number of RDMAs of the packet starting at
2104 * that request. For TSO send requests with one ore more cuts
2105 * in the middle, this is the number of RDMAs starting
2106 * after the last cut in the request. All previous
2107 * segments before the last cut implicitly have 1 RDMA.
2108 *
2109 * Since the number of RDMAs is not known beforehand,
2110 * it must be filled-in retroactively - after each
2111 * segmentation cut or at the end of the entire packet.
2112 */
2113
2114 while (1) {
2115 /* Break the SKB or Fragment up into pieces which
2116 * do not cross mgp->tx.boundary */
2117 low = MYRI10GE_LOWPART_TO_U32(bus);
2118 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2119 while (len) {
2120 u8 flags_next;
2121 int cum_len_next;
2122
2123 if (unlikely(count == max_segments))
2124 goto abort_linearize;
2125
2126 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2127 seglen = boundary - low;
2128 if (seglen > len)
2129 seglen = len;
2130 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2131 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2132 if (mss) { /* TSO */
2133 (req - rdma_count)->rdma_count = rdma_count + 1;
2134
2135 if (likely(cum_len >= 0)) { /* payload */
2136 int next_is_first, chop;
2137
2138 chop = (cum_len_next > mss);
2139 cum_len_next = cum_len_next % mss;
2140 next_is_first = (cum_len_next == 0);
2141 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2142 flags_next |= next_is_first *
2143 MXGEFW_FLAGS_FIRST;
2144 rdma_count |= -(chop | next_is_first);
2145 rdma_count += chop & !next_is_first;
2146 } else if (likely(cum_len_next >= 0)) { /* header ends */
2147 int small;
2148
2149 rdma_count = -1;
2150 cum_len_next = 0;
2151 seglen = -cum_len;
2152 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2153 flags_next = MXGEFW_FLAGS_TSO_PLD |
2154 MXGEFW_FLAGS_FIRST |
2155 (small * MXGEFW_FLAGS_SMALL);
2156 }
2157 }
0da34b6d
BG		 2158 req->addr_high = high_swapped;
2159 req->addr_low = htonl(low);
40f6cff5 2160 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2161 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2162 req->rdma_count = 1;
2163 req->length = htons(seglen);
2164 req->cksum_offset = cksum_offset;
2165 req->flags = flags | ((cum_len & 1) * odd_flag);
2166
2167 low += seglen;
2168 len -= seglen;
2169 cum_len = cum_len_next;
2170 flags = flags_next;
2171 req++;
2172 count++;
2173 rdma_count++;
2174 if (unlikely(cksum_offset > seglen))
2175 cksum_offset -= seglen;
2176 else
2177 cksum_offset = 0;
2178 }
2179 if (frag_idx == frag_cnt)
2180 break;
2181
2182 /* map next fragment for DMA */
2183 idx = (count + tx->req) & tx->mask;
2184 frag = &skb_shinfo(skb)->frags[frag_idx];
2185 frag_idx++;
2186 len = frag->size;
2187 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2188 len, PCI_DMA_TODEVICE);
2189 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2190 pci_unmap_len_set(&tx->info[idx], len, len);
2191 }
2192
2193 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2194 if (mss)
2195 do {
2196 req--;
2197 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2198 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2199 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2200 idx = ((count - 1) + tx->req) & tx->mask;
2201 tx->info[idx].last = 1;
2202 if (tx->wc_fifo == NULL)
2203 myri10ge_submit_req(tx, tx->req_list, count);
2204 else
2205 myri10ge_submit_req_wc(tx, tx->req_list, count);
2206 tx->pkt_start++;
2207 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2208 mgp->stop_queue++;
2209 netif_stop_queue(dev);
2210 }
2211 dev->trans_start = jiffies;
2212 return 0;
2213
2214abort_linearize:
2215 /* Free any DMA resources we've alloced and clear out the skb
2216 * slot so as to not trip up assertions, and to avoid a
2217 * double-free if linearizing fails */
2218
2219 last_idx = (idx + 1) & tx->mask;
2220 idx = tx->req & tx->mask;
2221 tx->info[idx].skb = NULL;
2222 do {
2223 len = pci_unmap_len(&tx->info[idx], len);
2224 if (len) {
2225 if (tx->info[idx].skb != NULL)
2226 pci_unmap_single(mgp->pdev,
2227 pci_unmap_addr(&tx->info[idx],
2228 bus), len,
2229 PCI_DMA_TODEVICE);
2230 else
2231 pci_unmap_page(mgp->pdev,
2232 pci_unmap_addr(&tx->info[idx],
2233 bus), len,
2234 PCI_DMA_TODEVICE);
2235 pci_unmap_len_set(&tx->info[idx], len, 0);
2236 tx->info[idx].skb = NULL;
2237 }
2238 idx = (idx + 1) & tx->mask;
2239 } while (idx != last_idx);
89114afd 2240 if (skb_is_gso(skb)) {
0da34b6d
BG		 2241 printk(KERN_ERR
2242 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2243 mgp->dev->name);
2244 goto drop;
2245 }
2246
bec0e859 2247 if (skb_linearize(skb))
0da34b6d
BG		 2248 goto drop;
2249
2250 mgp->tx_linearized++;
2251 goto again;
2252
2253drop:
2254 dev_kfree_skb_any(skb);
2255 mgp->stats.tx_dropped += 1;
2256 return 0;
2257
2258}
2259
2260static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2261{
2262 struct myri10ge_priv *mgp = netdev_priv(dev);
2263 return &mgp->stats;
2264}
2265
2266static void myri10ge_set_multicast_list(struct net_device *dev)
2267{
85a7ea1b
BG		 2268 struct myri10ge_cmd cmd;
2269 struct myri10ge_priv *mgp;
2270 struct dev_mc_list *mc_list;
6250223e 2271 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 2272 int err;
2273
2274 mgp = netdev_priv(dev);
0da34b6d
BG		 2275 /* can be called from atomic contexts,
2276 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2277 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2278
2279 /* This firmware is known to not support multicast */
9dc6f0e7 2280 if (!mgp->fw_multicast_support || mgp->adopted_rx_filter_bug)
85a7ea1b
BG		 2281 return;
2282
2283 /* Disable multicast filtering */
2284
2285 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2286 if (err != 0) {
2287 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2288 " error status: %d\n", dev->name, err);
2289 goto abort;
2290 }
2291
2292 if (dev->flags & IFF_ALLMULTI) {
2293 /* request to disable multicast filtering, so quit here */
2294 return;
2295 }
2296
2297 /* Flush the filters */
2298
2299 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2300 &cmd, 1);
2301 if (err != 0) {
2302 printk(KERN_ERR
2303 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2304 ", error status: %d\n", dev->name, err);
2305 goto abort;
2306 }
2307
2308 /* Walk the multicast list, and add each address */
2309 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 2310 memcpy(data, &mc_list->dmi_addr, 6);
2311 cmd.data0 = ntohl(data[0]);
2312 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2313 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2314 &cmd, 1);
2315
2316 if (err != 0) {
2317 printk(KERN_ERR "myri10ge: %s: Failed "
2318 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2319 "%d\t", dev->name, err);
2320 printk(KERN_ERR "MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
2321 ((unsigned char *)&mc_list->dmi_addr)[0],
2322 ((unsigned char *)&mc_list->dmi_addr)[1],
2323 ((unsigned char *)&mc_list->dmi_addr)[2],
2324 ((unsigned char *)&mc_list->dmi_addr)[3],
2325 ((unsigned char *)&mc_list->dmi_addr)[4],
2326 ((unsigned char *)&mc_list->dmi_addr)[5]
2327 );
2328 goto abort;
2329 }
2330 }
2331 /* Enable multicast filtering */
2332 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2333 if (err != 0) {
2334 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2335 "error status: %d\n", dev->name, err);
2336 goto abort;
2337 }
2338
2339 return;
2340
2341abort:
2342 return;
0da34b6d
BG		 2343}
2344
2345static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2346{
2347 struct sockaddr *sa = addr;
2348 struct myri10ge_priv *mgp = netdev_priv(dev);
2349 int status;
2350
2351 if (!is_valid_ether_addr(sa->sa_data))
2352 return -EADDRNOTAVAIL;
2353
2354 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2355 if (status != 0) {
2356 printk(KERN_ERR
2357 "myri10ge: %s: changing mac address failed with %d\n",
2358 dev->name, status);
2359 return status;
2360 }
2361
2362 /* change the dev structure */
2363 memcpy(dev->dev_addr, sa->sa_data, 6);
2364 return 0;
2365}
2366
2367static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2368{
2369 struct myri10ge_priv *mgp = netdev_priv(dev);
2370 int error = 0;
2371
2372 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2373 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2374 dev->name, new_mtu);
2375 return -EINVAL;
2376 }
2377 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2378 dev->name, dev->mtu, new_mtu);
2379 if (mgp->running) {
2380 /* if we change the mtu on an active device, we must
2381 * reset the device so the firmware sees the change */
2382 myri10ge_close(dev);
2383 dev->mtu = new_mtu;
2384 myri10ge_open(dev);
2385 } else
2386 dev->mtu = new_mtu;
2387
2388 return error;
2389}
2390
2391/*
2392 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2393 * Only do it if the bridge is a root port since we don't want to disturb
2394 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2395 */
2396
0da34b6d
BG		 2397static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2398{
2399 struct pci_dev *bridge = mgp->pdev->bus->self;
2400 struct device *dev = &mgp->pdev->dev;
2401 unsigned cap;
2402 unsigned err_cap;
2403 u16 val;
2404 u8 ext_type;
2405 int ret;
2406
2407 if (!myri10ge_ecrc_enable || !bridge)
2408 return;
2409
2410 /* check that the bridge is a root port */
2411 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2412 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2413 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2414 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2415 if (myri10ge_ecrc_enable > 1) {
2416 struct pci_dev *old_bridge = bridge;
2417
2418 /* Walk the hierarchy up to the root port
2419 * where ECRC has to be enabled */
2420 do {
2421 bridge = bridge->bus->self;
2422 if (!bridge) {
2423 dev_err(dev,
2424 "Failed to find root port"
2425 " to force ECRC\n");
2426 return;
2427 }
2428 cap =
2429 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2430 pci_read_config_word(bridge,
2431 cap + PCI_CAP_FLAGS, &val);
2432 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2433 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2434
2435 dev_info(dev,
2436 "Forcing ECRC on non-root port %s"
2437 " (enabling on root port %s)\n",
2438 pci_name(old_bridge), pci_name(bridge));
2439 } else {
2440 dev_err(dev,
2441 "Not enabling ECRC on non-root port %s\n",
2442 pci_name(bridge));
2443 return;
2444 }
2445 }
2446
2447 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 2448 if (!cap)
2449 return;
2450
2451 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2452 if (ret) {
2453 dev_err(dev, "failed reading ext-conf-space of %s\n",
2454 pci_name(bridge));
2455 dev_err(dev, "\t pci=nommconf in use? "
2456 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2457 return;
2458 }
2459 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2460 return;
2461
2462 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2463 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2464 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2465 mgp->tx.boundary = 4096;
2466 mgp->fw_name = myri10ge_fw_aligned;
2467}
2468
2469/*
2470 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2471 * when the PCI-E Completion packets are aligned on an 8-byte
2472 * boundary. Some PCI-E chip sets always align Completion packets; on
2473 * the ones that do not, the alignment can be enforced by enabling
2474 * ECRC generation (if supported).
2475 *
2476 * When PCI-E Completion packets are not aligned, it is actually more
2477 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2478 *
2479 * If the driver can neither enable ECRC nor verify that it has
2480 * already been enabled, then it must use a firmware image which works
2481 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2482 * should also ensure that it never gives the device a Read-DMA which is
2483 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2484 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2485 * firmware image, and set tx.boundary to 4KB.
2486 */
2487
ce7f9368
BG		 2488#define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
2489#define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
f19baaea
BG		 2490#define PCI_DEVICE_ID_INTEL_6300ESB_PCIEE1 0x3510
2491#define PCI_DEVICE_ID_INTEL_6300ESB_PCIEE4 0x351b
2492#define PCI_DEVICE_ID_INTEL_E3000_PCIE 0x2779
2493#define PCI_DEVICE_ID_INTEL_E3010_PCIE 0x277a
aafa70eb
BG		 2494#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST 0x140
2495#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST 0x142
0da34b6d
BG		 2496
2497static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2498{
2499 struct pci_dev *bridge = mgp->pdev->bus->self;
2500
2501 mgp->tx.boundary = 2048;
2502 mgp->fw_name = myri10ge_fw_unaligned;
2503
2504 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 2505 int link_width, exp_cap;
2506 u16 lnk;
2507
2508 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2509 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2510 link_width = (lnk >> 4) & 0x3f;
2511
0da34b6d
BG		 2512 myri10ge_enable_ecrc(mgp);
2513
ce7f9368
BG		 2514 /* Check to see if Link is less than 8 or if the
2515 * upstream bridge is known to provide aligned
2516 * completions */
2517 if (link_width < 8) {
2518 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2519 link_width);
2520 mgp->tx.boundary = 4096;
2521 mgp->fw_name = myri10ge_fw_aligned;
2522 } else if (bridge &&
2523 /* ServerWorks HT2000/HT1000 */
2524 ((bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2525 && bridge->device ==
2526 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE)
aafa70eb
BG		 2527 /* ServerWorks HT2100 */
2528 || (bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2529 && bridge->device >=
2530 PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST
2531 && bridge->device <=
2532 PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST)
f19baaea
BG		 2533 /* All Intel E3000/E3010 PCIE ports */
2534 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2535 && (bridge->device ==
2536 PCI_DEVICE_ID_INTEL_E3000_PCIE
2537 || bridge->device ==
2538 PCI_DEVICE_ID_INTEL_E3010_PCIE))
2539 /* All Intel 6310/6311/6321ESB PCIE ports */
2540 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2541 && bridge->device >=
2542 PCI_DEVICE_ID_INTEL_6300ESB_PCIEE1
2543 && bridge->device <=
2544 PCI_DEVICE_ID_INTEL_6300ESB_PCIEE4)
ce7f9368
BG		 2545 /* All Intel E5000 PCIE ports */
2546 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2547 && bridge->device >=
2548 PCI_DEVICE_ID_INTEL_E5000_PCIE23
2549 && bridge->device <=
2550 PCI_DEVICE_ID_INTEL_E5000_PCIE47))) {
0da34b6d
BG		 2551 dev_info(&mgp->pdev->dev,
2552 "Assuming aligned completions (0x%x:0x%x)\n",
2553 bridge->vendor, bridge->device);
2554 mgp->tx.boundary = 4096;
2555 mgp->fw_name = myri10ge_fw_aligned;
4c882dd8
BG		 2556 } else if (bridge &&
2557 bridge->vendor == PCI_VENDOR_ID_SGI &&
2558 bridge->device == 0x4002 /* TIOCE pcie-port */ ) {
2559 /* this pcie bridge does not support 4K rdma request */
2560 mgp->tx.boundary = 2048;
2561 mgp->fw_name = myri10ge_fw_aligned;
0da34b6d
BG		 2562 }
2563 } else {
2564 if (myri10ge_force_firmware == 1) {
2565 dev_info(&mgp->pdev->dev,
2566 "Assuming aligned completions (forced)\n");
2567 mgp->tx.boundary = 4096;
2568 mgp->fw_name = myri10ge_fw_aligned;
2569 } else {
2570 dev_info(&mgp->pdev->dev,
2571 "Assuming unaligned completions (forced)\n");
2572 mgp->tx.boundary = 2048;
2573 mgp->fw_name = myri10ge_fw_unaligned;
2574 }
2575 }
2576 if (myri10ge_fw_name != NULL) {
2577 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2578 myri10ge_fw_name);
2579 mgp->fw_name = myri10ge_fw_name;
2580 }
2581}
2582
0da34b6d
BG		 2583#ifdef CONFIG_PM
2584
2585static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2586{
2587 struct myri10ge_priv *mgp;
2588 struct net_device *netdev;
2589
2590 mgp = pci_get_drvdata(pdev);
2591 if (mgp == NULL)
2592 return -EINVAL;
2593 netdev = mgp->dev;
2594
2595 netif_device_detach(netdev);
2596 if (netif_running(netdev)) {
2597 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2598 rtnl_lock();
2599 myri10ge_close(netdev);
2600 rtnl_unlock();
2601 }
2602 myri10ge_dummy_rdma(mgp, 0);
83f6e152 2603 pci_save_state(pdev);
0da34b6d 2604 pci_disable_device(pdev);
1a63e846
BG		 2605
2606 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 2607}
2608
2609static int myri10ge_resume(struct pci_dev *pdev)
2610{
2611 struct myri10ge_priv *mgp;
2612 struct net_device *netdev;
2613 int status;
2614 u16 vendor;
2615
2616 mgp = pci_get_drvdata(pdev);
2617 if (mgp == NULL)
2618 return -EINVAL;
2619 netdev = mgp->dev;
2620 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2621 msleep(5); /* give card time to respond */
2622 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2623 if (vendor == 0xffff) {
2624 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2625 mgp->dev->name);
2626 return -EIO;
2627 }
83f6e152 2628
1a63e846
BG		 2629 status = pci_restore_state(pdev);
2630 if (status)
2631 return status;
4c2248cc
BG		 2632
2633 status = pci_enable_device(pdev);
1a63e846 2634 if (status) {
4c2248cc 2635 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 2636 return status;
4c2248cc
BG		 2637 }
2638
0da34b6d
BG		 2639 pci_set_master(pdev);
2640
0da34b6d 2641 myri10ge_reset(mgp);
013b68bf 2642 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 2643
2644 /* Save configuration space to be restored if the
2645 * nic resets due to a parity error */
83f6e152 2646 pci_save_state(pdev);
0da34b6d
BG		 2647
2648 if (netif_running(netdev)) {
2649 rtnl_lock();
df30a740 2650 status = myri10ge_open(netdev);
0da34b6d 2651 rtnl_unlock();
df30a740
BG		 2652 if (status != 0)
2653 goto abort_with_enabled;
2654
0da34b6d
BG		 2655 }
2656 netif_device_attach(netdev);
2657
2658 return 0;
2659
4c2248cc
BG		 2660abort_with_enabled:
2661 pci_disable_device(pdev);
0da34b6d
BG		 2662 return -EIO;
2663
2664}
2665
2666#endif /* CONFIG_PM */
2667
2668static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2669{
2670 struct pci_dev *pdev = mgp->pdev;
2671 int vs = mgp->vendor_specific_offset;
2672 u32 reboot;
2673
2674 /*enter read32 mode */
2675 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2676
2677 /*read REBOOT_STATUS (0xfffffff0) */
2678 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2679 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2680 return reboot;
2681}
2682
2683/*
2684 * This watchdog is used to check whether the board has suffered
2685 * from a parity error and needs to be recovered.
2686 */
c4028958 2687static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 2688{
c4028958 2689 struct myri10ge_priv *mgp =
6250223e 2690 container_of(work, struct myri10ge_priv, watchdog_work);
0da34b6d
BG		 2691 u32 reboot;
2692 int status;
2693 u16 cmd, vendor;
2694
2695 mgp->watchdog_resets++;
2696 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2697 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2698 /* Bus master DMA disabled? Check to see
2699 * if the card rebooted due to a parity error
2700 * For now, just report it */
2701 reboot = myri10ge_read_reboot(mgp);
2702 printk(KERN_ERR
2703 "myri10ge: %s: NIC rebooted (0x%x), resetting\n",
2704 mgp->dev->name, reboot);
2705 /*
2706 * A rebooted nic will come back with config space as
2707 * it was after power was applied to PCIe bus.
2708 * Attempt to restore config space which was saved
2709 * when the driver was loaded, or the last time the
2710 * nic was resumed from power saving mode.
2711 */
83f6e152 2712 pci_restore_state(mgp->pdev);
7adda30c
BG		 2713
2714 /* save state again for accounting reasons */
83f6e152 2715 pci_save_state(mgp->pdev);
7adda30c 2716
0da34b6d
BG		 2717 } else {
2718 /* if we get back -1's from our slot, perhaps somebody
2719 * powered off our card. Don't try to reset it in
2720 * this case */
2721 if (cmd == 0xffff) {
2722 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2723 if (vendor == 0xffff) {
2724 printk(KERN_ERR
2725 "myri10ge: %s: device disappeared!\n",
2726 mgp->dev->name);
2727 return;
2728 }
2729 }
2730 /* Perhaps it is a software error. Try to reset */
2731
2732 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2733 mgp->dev->name);
2734 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2735 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2736 mgp->tx.pkt_start, mgp->tx.pkt_done,
2737 (int)ntohl(mgp->fw_stats->send_done_count));
2738 msleep(2000);
2739 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2740 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2741 mgp->tx.pkt_start, mgp->tx.pkt_done,
2742 (int)ntohl(mgp->fw_stats->send_done_count));
2743 }
2744 rtnl_lock();
2745 myri10ge_close(mgp->dev);
2746 status = myri10ge_load_firmware(mgp);
2747 if (status != 0)
2748 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2749 mgp->dev->name);
2750 else
2751 myri10ge_open(mgp->dev);
2752 rtnl_unlock();
2753}
2754
2755/*
2756 * We use our own timer routine rather than relying upon
2757 * netdev->tx_timeout because we have a very large hardware transmit
2758 * queue. Due to the large queue, the netdev->tx_timeout function
2759 * cannot detect a NIC with a parity error in a timely fashion if the
2760 * NIC is lightly loaded.
2761 */
2762static void myri10ge_watchdog_timer(unsigned long arg)
2763{
2764 struct myri10ge_priv *mgp;
2765
2766 mgp = (struct myri10ge_priv *)arg;
c7dab99b
BG		 2767
2768 if (mgp->rx_small.watchdog_needed) {
2769 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2770 mgp->small_bytes + MXGEFW_PAD, 1);
2771 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2772 myri10ge_fill_thresh)
2773 mgp->rx_small.watchdog_needed = 0;
2774 }
2775 if (mgp->rx_big.watchdog_needed) {
2776 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2777 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2778 myri10ge_fill_thresh)
2779 mgp->rx_big.watchdog_needed = 0;
2780 }
2781
0da34b6d 2782 if (mgp->tx.req != mgp->tx.done &&
c54772e7
BG		 2783 mgp->tx.done == mgp->watchdog_tx_done &&
2784 mgp->watchdog_tx_req != mgp->watchdog_tx_done)
0da34b6d
BG		 2785 /* nic seems like it might be stuck.. */
2786 schedule_work(&mgp->watchdog_work);
2787 else
2788 /* rearm timer */
2789 mod_timer(&mgp->watchdog_timer,
2790 jiffies + myri10ge_watchdog_timeout * HZ);
2791
2792 mgp->watchdog_tx_done = mgp->tx.done;
c54772e7 2793 mgp->watchdog_tx_req = mgp->tx.req;
0da34b6d
BG		 2794}
2795
2796static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2797{
2798 struct net_device *netdev;
2799 struct myri10ge_priv *mgp;
2800 struct device *dev = &pdev->dev;
2801 size_t bytes;
2802 int i;
2803 int status = -ENXIO;
2804 int cap;
2805 int dac_enabled;
2806 u16 val;
2807
2808 netdev = alloc_etherdev(sizeof(*mgp));
2809 if (netdev == NULL) {
2810 dev_err(dev, "Could not allocate ethernet device\n");
2811 return -ENOMEM;
2812 }
2813
2814 mgp = netdev_priv(netdev);
2815 memset(mgp, 0, sizeof(*mgp));
2816 mgp->dev = netdev;
2817 mgp->pdev = pdev;
2818 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2819 mgp->pause = myri10ge_flow_control;
2820 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 2821 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
0da34b6d
BG		 2822 init_waitqueue_head(&mgp->down_wq);
2823
2824 if (pci_enable_device(pdev)) {
2825 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2826 status = -ENODEV;
2827 goto abort_with_netdev;
2828 }
2829 myri10ge_select_firmware(mgp);
2830
2831 /* Find the vendor-specific cap so we can check
2832 * the reboot register later on */
2833 mgp->vendor_specific_offset
2834 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2835
2836 /* Set our max read request to 4KB */
2837 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2838 if (cap < 64) {
2839 dev_err(&pdev->dev, "Bad PCI_CAP_ID_EXP location %d\n", cap);
2840 goto abort_with_netdev;
2841 }
2842 status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val);
2843 if (status != 0) {
2844 dev_err(&pdev->dev, "Error %d reading PCI_EXP_DEVCTL\n",
2845 status);
2846 goto abort_with_netdev;
2847 }
2848 val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
2849 status = pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, val);
2850 if (status != 0) {
2851 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2852 status);
2853 goto abort_with_netdev;
2854 }
2855
2856 pci_set_master(pdev);
2857 dac_enabled = 1;
2858 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2859 if (status != 0) {
2860 dac_enabled = 0;
2861 dev_err(&pdev->dev,
2862 "64-bit pci address mask was refused, trying 32-bit");
2863 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2864 }
2865 if (status != 0) {
2866 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2867 goto abort_with_netdev;
2868 }
b10c0668
BG		 2869 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2870 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 2871 if (mgp->cmd == NULL)
2872 goto abort_with_netdev;
2873
b10c0668
BG		 2874 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2875 &mgp->fw_stats_bus, GFP_KERNEL);
0da34b6d
BG		 2876 if (mgp->fw_stats == NULL)
2877 goto abort_with_cmd;
2878
2879 mgp->board_span = pci_resource_len(pdev, 0);
2880 mgp->iomem_base = pci_resource_start(pdev, 0);
2881 mgp->mtrr = -1;
276e26c3 2882 mgp->wc_enabled = 0;
0da34b6d
BG		 2883#ifdef CONFIG_MTRR
2884 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
2885 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 2886 if (mgp->mtrr >= 0)
2887 mgp->wc_enabled = 1;
0da34b6d
BG		 2888#endif
2889 /* Hack. need to get rid of these magic numbers */
2890 mgp->sram_size =
2891 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
2892 if (mgp->sram_size > mgp->board_span) {
2893 dev_err(&pdev->dev, "board span %ld bytes too small\n",
2894 mgp->board_span);
2895 goto abort_with_wc;
2896 }
2897 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
2898 if (mgp->sram == NULL) {
2899 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
2900 mgp->board_span, mgp->iomem_base);
2901 status = -ENXIO;
2902 goto abort_with_wc;
2903 }
2904 memcpy_fromio(mgp->eeprom_strings,
2905 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
2906 MYRI10GE_EEPROM_STRINGS_SIZE);
2907 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
2908 status = myri10ge_read_mac_addr(mgp);
2909 if (status)
2910 goto abort_with_ioremap;
2911
2912 for (i = 0; i < ETH_ALEN; i++)
2913 netdev->dev_addr[i] = mgp->mac_addr[i];
2914
2915 /* allocate rx done ring */
2916 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2917 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
2918 &mgp->rx_done.bus, GFP_KERNEL);
0da34b6d
BG		 2919 if (mgp->rx_done.entry == NULL)
2920 goto abort_with_ioremap;
2921 memset(mgp->rx_done.entry, 0, bytes);
2922
2923 status = myri10ge_load_firmware(mgp);
2924 if (status != 0) {
2925 dev_err(&pdev->dev, "failed to load firmware\n");
2926 goto abort_with_rx_done;
2927 }
2928
2929 status = myri10ge_reset(mgp);
2930 if (status != 0) {
2931 dev_err(&pdev->dev, "failed reset\n");
2932 goto abort_with_firmware;
2933 }
2934
0da34b6d
BG		 2935 pci_set_drvdata(pdev, mgp);
2936 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
2937 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
2938 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
2939 myri10ge_initial_mtu = 68;
2940 netdev->mtu = myri10ge_initial_mtu;
2941 netdev->open = myri10ge_open;
2942 netdev->stop = myri10ge_close;
2943 netdev->hard_start_xmit = myri10ge_xmit;
2944 netdev->get_stats = myri10ge_get_stats;
2945 netdev->base_addr = mgp->iomem_base;
0da34b6d
BG		 2946 netdev->change_mtu = myri10ge_change_mtu;
2947 netdev->set_multicast_list = myri10ge_set_multicast_list;
2948 netdev->set_mac_address = myri10ge_set_mac_address;
2949 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
2950 if (dac_enabled)
2951 netdev->features |= NETIF_F_HIGHDMA;
2952 netdev->poll = myri10ge_poll;
2953 netdev->weight = myri10ge_napi_weight;
2954
21d05db1
BG		 2955 /* make sure we can get an irq, and that MSI can be
2956 * setup (if available). Also ensure netdev->irq
2957 * is set to correct value if MSI is enabled */
2958 status = myri10ge_request_irq(mgp);
2959 if (status != 0)
2960 goto abort_with_firmware;
2961 netdev->irq = pdev->irq;
2962 myri10ge_free_irq(mgp);
2963
0da34b6d
BG		 2964 /* Save configuration space to be restored if the
2965 * nic resets due to a parity error */
83f6e152 2966 pci_save_state(pdev);
0da34b6d
BG		 2967
2968 /* Setup the watchdog timer */
2969 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
2970 (unsigned long)mgp);
2971
2972 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 2973 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 2974 status = register_netdev(netdev);
2975 if (status != 0) {
2976 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 2977 goto abort_with_state;
0da34b6d 2978 }
21d05db1
BG		 2979 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
2980 (mgp->msi_enabled ? "MSI" : "xPIC"),
2981 netdev->irq, mgp->tx.boundary, mgp->fw_name,
276e26c3 2982 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d
BG		 2983
2984 return 0;
2985
7adda30c 2986abort_with_state:
83f6e152 2987 pci_restore_state(pdev);
0da34b6d
BG		 2988
2989abort_with_firmware:
2990 myri10ge_dummy_rdma(mgp, 0);
2991
2992abort_with_rx_done:
2993 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2994 dma_free_coherent(&pdev->dev, bytes,
2995 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 2996
2997abort_with_ioremap:
2998 iounmap(mgp->sram);
2999
3000abort_with_wc:
3001#ifdef CONFIG_MTRR
3002 if (mgp->mtrr >= 0)
3003 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3004#endif
b10c0668
BG		 3005 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3006 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d
BG		 3007
3008abort_with_cmd:
b10c0668
BG		 3009 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3010 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3011
3012abort_with_netdev:
3013
3014 free_netdev(netdev);
3015 return status;
3016}
3017
3018/*
3019 * myri10ge_remove
3020 *
3021 * Does what is necessary to shutdown one Myrinet device. Called
3022 * once for each Myrinet card by the kernel when a module is
3023 * unloaded.
3024 */
3025static void myri10ge_remove(struct pci_dev *pdev)
3026{
3027 struct myri10ge_priv *mgp;
3028 struct net_device *netdev;
3029 size_t bytes;
3030
3031 mgp = pci_get_drvdata(pdev);
3032 if (mgp == NULL)
3033 return;
3034
3035 flush_scheduled_work();
3036 netdev = mgp->dev;
3037 unregister_netdev(netdev);
0da34b6d
BG		 3038
3039 myri10ge_dummy_rdma(mgp, 0);
3040
7adda30c 3041 /* avoid a memory leak */
83f6e152 3042 pci_restore_state(pdev);
7adda30c 3043
0da34b6d 3044 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3045 dma_free_coherent(&pdev->dev, bytes,
3046 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3047
3048 iounmap(mgp->sram);
3049
3050#ifdef CONFIG_MTRR
3051 if (mgp->mtrr >= 0)
3052 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3053#endif
b10c0668
BG		 3054 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3055 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d 3056
b10c0668
BG		 3057 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3058 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3059
3060 free_netdev(netdev);
3061 pci_set_drvdata(pdev, NULL);
3062}
3063
b10c0668 3064#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
0da34b6d
BG		 3065
3066static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 3067 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
0da34b6d
BG		 3068 {0},
3069};
3070
3071static struct pci_driver myri10ge_driver = {
3072 .name = "myri10ge",
3073 .probe = myri10ge_probe,
3074 .remove = myri10ge_remove,
3075 .id_table = myri10ge_pci_tbl,
3076#ifdef CONFIG_PM
3077 .suspend = myri10ge_suspend,
3078 .resume = myri10ge_resume,
3079#endif
3080};
3081
3082static __init int myri10ge_init_module(void)
3083{
3084 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3085 MYRI10GE_VERSION_STR);
3086 return pci_register_driver(&myri10ge_driver);
3087}
3088
3089module_init(myri10ge_init_module);
3090
3091static __exit void myri10ge_cleanup_module(void)
3092{
3093 pci_unregister_driver(&myri10ge_driver);
3094}
3095
3096module_exit(myri10ge_cleanup_module);
Clone of davem's net-next-2.6 tree