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mv643xx_eth: transmit multiqueue support
[net-next-2.6.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
c4560318 58static char mv643xx_eth_driver_version[] = "1.3";
c9df406f 59
e5371493 60#define MV643XX_ETH_TX_FAST_REFILL
fbd6a754 61
fbd6a754
LB		 62/*
63 * Registers shared between all ports.
64 */
3cb4667c
LB		 65#define PHY_ADDR 0x0000
66#define SMI_REG 0x0004
45c5d3bc
LB		 67#define SMI_BUSY 0x10000000
68#define SMI_READ_VALID 0x08000000
69#define SMI_OPCODE_READ 0x04000000
70#define SMI_OPCODE_WRITE 0x00000000
71#define ERR_INT_CAUSE 0x0080
72#define ERR_INT_SMI_DONE 0x00000010
73#define ERR_INT_MASK 0x0084
3cb4667c
LB		 74#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77#define WINDOW_BAR_ENABLE 0x0290
78#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 79
80/*
81 * Per-port registers.
82 */
3cb4667c 83#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 84#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 85#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
86#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
87#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
88#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
89#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
90#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 91#define TX_FIFO_EMPTY 0x00000400
ae9ae064 92#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 93#define PORT_SPEED_MASK 0x00000030
94#define PORT_SPEED_1000 0x00000010
95#define PORT_SPEED_100 0x00000020
96#define PORT_SPEED_10 0x00000000
97#define FLOW_CONTROL_ENABLED 0x00000008
98#define FULL_DUPLEX 0x00000004
81600eea 99#define LINK_UP 0x00000002
3cb4667c 100#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 101#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
102#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 103#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 104#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 105#define INT_CAUSE(p) (0x0460 + ((p) << 10))
8fa89bf5 106#define INT_TX_END_0 0x00080000
226bb6b7 107#define INT_TX_END 0x07f80000
befefe21 108#define INT_RX 0x000003fc
073a345c 109#define INT_EXT 0x00000002
3cb4667c 110#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
befefe21
LB		 111#define INT_EXT_LINK_PHY 0x00110000
112#define INT_EXT_TX 0x000000ff
3cb4667c
LB		 113#define INT_MASK(p) (0x0468 + ((p) << 10))
114#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
115#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
1e881592
LB		 116#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
117#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
118#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
119#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
64da80a2 120#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
3cb4667c 121#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
3d6b35bc
LB		 122#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
123#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
124#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
125#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
3cb4667c
LB		 126#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
127#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
128#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
129#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 130
2679a550
LB		 131
132/*
133 * SDMA configuration register.
134 */
cd4ccf76 135#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 136#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 137#define BLM_TX_NO_SWAP (1 << 5)
cd4ccf76 138#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 139
140#if defined(__BIG_ENDIAN)
141#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76
LB		 142 RX_BURST_SIZE_16_64BIT | \
143 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 144#elif defined(__LITTLE_ENDIAN)
145#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76 146 RX_BURST_SIZE_16_64BIT | \
fbd6a754
LB		 147 BLM_RX_NO_SWAP | \
148 BLM_TX_NO_SWAP | \
cd4ccf76 149 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 150#else
151#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
152#endif
153
2beff77b
LB		 154
155/*
156 * Port serial control register.
157 */
158#define SET_MII_SPEED_TO_100 (1 << 24)
159#define SET_GMII_SPEED_TO_1000 (1 << 23)
160#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 161#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 162#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
163#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
164#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
165#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
166#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
167#define FORCE_LINK_PASS (1 << 1)
168#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 169
cc9754b3
LB		 170#define DEFAULT_RX_QUEUE_SIZE 400
171#define DEFAULT_TX_QUEUE_SIZE 800
fbd6a754 172
fbd6a754 173
7ca72a3b
LB		 174/*
175 * RX/TX descriptors.
fbd6a754
LB		 176 */
177#if defined(__BIG_ENDIAN)
cc9754b3 178struct rx_desc {
fbd6a754
LB		 179 u16 byte_cnt; /* Descriptor buffer byte count */
180 u16 buf_size; /* Buffer size */
181 u32 cmd_sts; /* Descriptor command status */
182 u32 next_desc_ptr; /* Next descriptor pointer */
183 u32 buf_ptr; /* Descriptor buffer pointer */
184};
185
cc9754b3 186struct tx_desc {
fbd6a754
LB		 187 u16 byte_cnt; /* buffer byte count */
188 u16 l4i_chk; /* CPU provided TCP checksum */
189 u32 cmd_sts; /* Command/status field */
190 u32 next_desc_ptr; /* Pointer to next descriptor */
191 u32 buf_ptr; /* pointer to buffer for this descriptor*/
192};
193#elif defined(__LITTLE_ENDIAN)
cc9754b3 194struct rx_desc {
fbd6a754
LB		 195 u32 cmd_sts; /* Descriptor command status */
196 u16 buf_size; /* Buffer size */
197 u16 byte_cnt; /* Descriptor buffer byte count */
198 u32 buf_ptr; /* Descriptor buffer pointer */
199 u32 next_desc_ptr; /* Next descriptor pointer */
200};
201
cc9754b3 202struct tx_desc {
fbd6a754
LB		 203 u32 cmd_sts; /* Command/status field */
204 u16 l4i_chk; /* CPU provided TCP checksum */
205 u16 byte_cnt; /* buffer byte count */
206 u32 buf_ptr; /* pointer to buffer for this descriptor*/
207 u32 next_desc_ptr; /* Pointer to next descriptor */
208};
209#else
210#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
211#endif
212
7ca72a3b 213/* RX & TX descriptor command */
cc9754b3 214#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 215
216/* RX & TX descriptor status */
cc9754b3 217#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 218
219/* RX descriptor status */
cc9754b3
LB		 220#define LAYER_4_CHECKSUM_OK 0x40000000
221#define RX_ENABLE_INTERRUPT 0x20000000
222#define RX_FIRST_DESC 0x08000000
223#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 224
225/* TX descriptor command */
cc9754b3
LB		 226#define TX_ENABLE_INTERRUPT 0x00800000
227#define GEN_CRC 0x00400000
228#define TX_FIRST_DESC 0x00200000
229#define TX_LAST_DESC 0x00100000
230#define ZERO_PADDING 0x00080000
231#define GEN_IP_V4_CHECKSUM 0x00040000
232#define GEN_TCP_UDP_CHECKSUM 0x00020000
233#define UDP_FRAME 0x00010000
e32b6617
LB		 234#define MAC_HDR_EXTRA_4_BYTES 0x00008000
235#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 236
cc9754b3 237#define TX_IHL_SHIFT 11
7ca72a3b
LB		 238
239
c9df406f 240/* global *******************************************************************/
e5371493 241struct mv643xx_eth_shared_private {
fc32b0e2
LB		 242 /*
243 * Ethernet controller base address.
244 */
cc9754b3 245 void __iomem *base;
c9df406f 246
fc0eb9f2
LB		 247 /*
248 * Points at the right SMI instance to use.
249 */
250 struct mv643xx_eth_shared_private *smi;
251
fc32b0e2
LB		 252 /*
253 * Protects access to SMI_REG, which is shared between ports.
254 */
2b3ba0e3 255 struct mutex phy_lock;
c9df406f 256
45c5d3bc
LB		 257 /*
258 * If we have access to the error interrupt pin (which is
259 * somewhat misnamed as it not only reflects internal errors
260 * but also reflects SMI completion), use that to wait for
261 * SMI access completion instead of polling the SMI busy bit.
262 */
263 int err_interrupt;
264 wait_queue_head_t smi_busy_wait;
265
fc32b0e2
LB		 266 /*
267 * Per-port MBUS window access register value.
268 */
c9df406f
LB		 269 u32 win_protect;
270
fc32b0e2
LB		 271 /*
272 * Hardware-specific parameters.
273 */
c9df406f 274 unsigned int t_clk;
773fc3ee 275 int extended_rx_coal_limit;
1e881592 276 int tx_bw_control_moved;
c9df406f
LB		 277};
278
279
280/* per-port *****************************************************************/
e5371493 281struct mib_counters {
fbd6a754
LB		 282 u64 good_octets_received;
283 u32 bad_octets_received;
284 u32 internal_mac_transmit_err;
285 u32 good_frames_received;
286 u32 bad_frames_received;
287 u32 broadcast_frames_received;
288 u32 multicast_frames_received;
289 u32 frames_64_octets;
290 u32 frames_65_to_127_octets;
291 u32 frames_128_to_255_octets;
292 u32 frames_256_to_511_octets;
293 u32 frames_512_to_1023_octets;
294 u32 frames_1024_to_max_octets;
295 u64 good_octets_sent;
296 u32 good_frames_sent;
297 u32 excessive_collision;
298 u32 multicast_frames_sent;
299 u32 broadcast_frames_sent;
300 u32 unrec_mac_control_received;
301 u32 fc_sent;
302 u32 good_fc_received;
303 u32 bad_fc_received;
304 u32 undersize_received;
305 u32 fragments_received;
306 u32 oversize_received;
307 u32 jabber_received;
308 u32 mac_receive_error;
309 u32 bad_crc_event;
310 u32 collision;
311 u32 late_collision;
312};
313
8a578111 314struct rx_queue {
64da80a2
LB		 315 int index;
316
8a578111
LB		 317 int rx_ring_size;
318
319 int rx_desc_count;
320 int rx_curr_desc;
321 int rx_used_desc;
322
323 struct rx_desc *rx_desc_area;
324 dma_addr_t rx_desc_dma;
325 int rx_desc_area_size;
326 struct sk_buff **rx_skb;
8a578111
LB		 327};
328
13d64285 329struct tx_queue {
3d6b35bc
LB		 330 int index;
331
13d64285 332 int tx_ring_size;
fbd6a754 333
13d64285
LB		 334 int tx_desc_count;
335 int tx_curr_desc;
336 int tx_used_desc;
fbd6a754 337
5daffe94 338 struct tx_desc *tx_desc_area;
fbd6a754
LB		 339 dma_addr_t tx_desc_dma;
340 int tx_desc_area_size;
341 struct sk_buff **tx_skb;
13d64285
LB		 342};
343
344struct mv643xx_eth_private {
345 struct mv643xx_eth_shared_private *shared;
fc32b0e2 346 int port_num;
13d64285 347
fc32b0e2 348 struct net_device *dev;
fbd6a754 349
fc32b0e2 350 int phy_addr;
fbd6a754 351
fbd6a754 352 spinlock_t lock;
fbd6a754 353
fc32b0e2
LB		 354 struct mib_counters mib_counters;
355 struct work_struct tx_timeout_task;
fbd6a754 356 struct mii_if_info mii;
8a578111
LB		 357
358 /*
359 * RX state.
360 */
361 int default_rx_ring_size;
362 unsigned long rx_desc_sram_addr;
363 int rx_desc_sram_size;
f7981c1c 364 int rxq_count;
8a578111 365 struct napi_struct napi;
2257e05c 366 struct timer_list rx_oom;
64da80a2 367 struct rx_queue rxq[8];
13d64285
LB		 368
369 /*
370 * TX state.
371 */
372 int default_tx_ring_size;
373 unsigned long tx_desc_sram_addr;
374 int tx_desc_sram_size;
f7981c1c 375 int txq_count;
3d6b35bc 376 struct tx_queue txq[8];
13d64285
LB		 377#ifdef MV643XX_ETH_TX_FAST_REFILL
378 int tx_clean_threshold;
379#endif
fbd6a754 380};
1da177e4 381
fbd6a754 382
c9df406f 383/* port register accessors **************************************************/
e5371493 384static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 385{
cc9754b3 386 return readl(mp->shared->base + offset);
c9df406f 387}
fbd6a754 388
e5371493 389static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 390{
cc9754b3 391 writel(data, mp->shared->base + offset);
c9df406f 392}
fbd6a754 393
fbd6a754 394
c9df406f 395/* rxq/txq helper functions *************************************************/
8a578111 396static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 397{
64da80a2 398 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 399}
fbd6a754 400
13d64285
LB		 401static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
402{
3d6b35bc 403 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 404}
405
8a578111 406static void rxq_enable(struct rx_queue *rxq)
c9df406f 407{
8a578111 408 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 409 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
8a578111 410}
1da177e4 411
8a578111
LB		 412static void rxq_disable(struct rx_queue *rxq)
413{
414 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 415 u8 mask = 1 << rxq->index;
1da177e4 416
8a578111
LB		 417 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
418 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
419 udelay(10);
c9df406f
LB		 420}
421
6b368f68
LB		 422static void txq_reset_hw_ptr(struct tx_queue *txq)
423{
424 struct mv643xx_eth_private *mp = txq_to_mp(txq);
425 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
426 u32 addr;
427
428 addr = (u32)txq->tx_desc_dma;
429 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
430 wrl(mp, off, addr);
431}
432
13d64285 433static void txq_enable(struct tx_queue *txq)
1da177e4 434{
13d64285 435 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 436 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
1da177e4
LT		 437}
438
13d64285 439static void txq_disable(struct tx_queue *txq)
1da177e4 440{
13d64285 441 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 442 u8 mask = 1 << txq->index;
c9df406f 443
13d64285
LB		 444 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
445 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
446 udelay(10);
447}
448
449static void __txq_maybe_wake(struct tx_queue *txq)
450{
451 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 452 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 453
17cd0a59 454 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
e5ef1de1 455 netif_tx_wake_queue(nq);
1da177e4
LT		 456}
457
c9df406f
LB		 458
459/* rx ***********************************************************************/
13d64285 460static void txq_reclaim(struct tx_queue *txq, int force);
c9df406f 461
2257e05c 462static int rxq_refill(struct rx_queue *rxq, int budget, int *oom)
1da177e4 463{
2257e05c
LB		 464 int skb_size;
465 int refilled;
1da177e4 466
2257e05c
LB		 467 /*
468 * Reserve 2+14 bytes for an ethernet header (the hardware
469 * automatically prepends 2 bytes of dummy data to each
470 * received packet), 16 bytes for up to four VLAN tags, and
471 * 4 bytes for the trailing FCS -- 36 bytes total.
472 */
473 skb_size = rxq_to_mp(rxq)->dev->mtu + 36;
474
475 /*
476 * Make sure that the skb size is a multiple of 8 bytes, as
477 * the lower three bits of the receive descriptor's buffer
478 * size field are ignored by the hardware.
479 */
480 skb_size = (skb_size + 7) & ~7;
c0d0f2ca 481
2257e05c
LB		 482 refilled = 0;
483 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
de34f225
LB		 484 struct sk_buff *skb;
485 int unaligned;
486 int rx;
487
8a578111 488 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
2257e05c
LB		 489 if (skb == NULL) {
490 *oom = 1;
1da177e4 491 break;
2257e05c 492 }
de34f225 493
908b637f 494 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
b44cd572 495 if (unaligned)
908b637f 496 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
de34f225 497
2257e05c 498 refilled++;
8a578111 499 rxq->rx_desc_count++;
9da78745
LB		 500
501 rx = rxq->rx_used_desc++;
502 if (rxq->rx_used_desc == rxq->rx_ring_size)
503 rxq->rx_used_desc = 0;
de34f225 504
8a578111
LB		 505 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
506 skb_size, DMA_FROM_DEVICE);
507 rxq->rx_desc_area[rx].buf_size = skb_size;
508 rxq->rx_skb[rx] = skb;
de34f225 509 wmb();
8a578111 510 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
de34f225
LB		 511 RX_ENABLE_INTERRUPT;
512 wmb();
513
fc32b0e2
LB		 514 /*
515 * The hardware automatically prepends 2 bytes of
516 * dummy data to each received packet, so that the
517 * IP header ends up 16-byte aligned.
518 */
519 skb_reserve(skb, 2);
1da177e4 520 }
de34f225 521
2257e05c 522 return refilled;
1da177e4
LT		 523}
524
8a578111 525static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 526{
8a578111
LB		 527 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
528 struct net_device_stats *stats = &mp->dev->stats;
529 int rx;
1da177e4 530
8a578111 531 rx = 0;
9e1f3772 532 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 533 struct rx_desc *rx_desc;
96587661 534 unsigned int cmd_sts;
fc32b0e2 535 struct sk_buff *skb;
ff561eef 536
8a578111 537 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 538
96587661 539 cmd_sts = rx_desc->cmd_sts;
2257e05c 540 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 541 break;
96587661 542 rmb();
1da177e4 543
8a578111
LB		 544 skb = rxq->rx_skb[rxq->rx_curr_desc];
545 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 546
9da78745
LB		 547 rxq->rx_curr_desc++;
548 if (rxq->rx_curr_desc == rxq->rx_ring_size)
549 rxq->rx_curr_desc = 0;
ff561eef 550
3a499481 551 dma_unmap_single(NULL, rx_desc->buf_ptr,
abe78717 552 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 553 rxq->rx_desc_count--;
554 rx++;
b1dd9ca1 555
468d09f8
DF		 556 /*
557 * Update statistics.
fc32b0e2
LB		 558 *
559 * Note that the descriptor byte count includes 2 dummy
560 * bytes automatically inserted by the hardware at the
561 * start of the packet (which we don't count), and a 4
562 * byte CRC at the end of the packet (which we do count).
468d09f8 563 */
1da177e4 564 stats->rx_packets++;
fc32b0e2 565 stats->rx_bytes += rx_desc->byte_cnt - 2;
96587661 566
1da177e4 567 /*
fc32b0e2
LB		 568 * In case we received a packet without first / last bits
569 * on, or the error summary bit is set, the packet needs
570 * to be dropped.
1da177e4 571 */
96587661 572 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 573 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 574 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 575 stats->rx_dropped++;
fc32b0e2 576
96587661 577 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 578 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 579 if (net_ratelimit())
fc32b0e2
LB		 580 dev_printk(KERN_ERR, &mp->dev->dev,
581 "received packet spanning "
582 "multiple descriptors\n");
1da177e4 583 }
fc32b0e2 584
96587661 585 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 586 stats->rx_errors++;
587
78fff83b 588 dev_kfree_skb(skb);
1da177e4
LT		 589 } else {
590 /*
591 * The -4 is for the CRC in the trailer of the
592 * received packet
593 */
fc32b0e2 594 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
1da177e4 595
96587661 596 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 597 skb->ip_summed = CHECKSUM_UNNECESSARY;
598 skb->csum = htons(
96587661 599 (cmd_sts & 0x0007fff8) >> 3);
1da177e4 600 }
8a578111 601 skb->protocol = eth_type_trans(skb, mp->dev);
1da177e4 602 netif_receive_skb(skb);
1da177e4 603 }
fc32b0e2 604
8a578111 605 mp->dev->last_rx = jiffies;
1da177e4 606 }
fc32b0e2 607
8a578111 608 return rx;
1da177e4
LT		 609}
610
e5371493 611static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
d0412d96 612{
8a578111 613 struct mv643xx_eth_private *mp;
2257e05c
LB		 614 int work_done;
615 int oom;
64da80a2 616 int i;
8a578111
LB		 617
618 mp = container_of(napi, struct mv643xx_eth_private, napi);
d0412d96 619
e5371493 620#ifdef MV643XX_ETH_TX_FAST_REFILL
c9df406f 621 if (++mp->tx_clean_threshold > 5) {
c9df406f 622 mp->tx_clean_threshold = 0;
f7981c1c
LB		 623 for (i = 0; i < mp->txq_count; i++)
624 txq_reclaim(mp->txq + i, 0);
4dfc1c87 625
4fdeca3f
LB		 626 spin_lock_irq(&mp->lock);
627 __txq_maybe_wake(mp->txq);
628 spin_unlock_irq(&mp->lock);
d0412d96 629 }
c9df406f 630#endif
d0412d96 631
2257e05c
LB		 632 work_done = 0;
633 oom = 0;
f7981c1c
LB		 634 for (i = mp->rxq_count - 1; work_done < budget && i >= 0; i--) {
635 struct rx_queue *rxq = mp->rxq + i;
d0412d96 636
f7981c1c
LB		 637 work_done += rxq_process(rxq, budget - work_done);
638 work_done += rxq_refill(rxq, budget - work_done, &oom);
2257e05c
LB		 639 }
640
641 if (work_done < budget) {
642 if (oom)
643 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
8a578111 644 netif_rx_complete(mp->dev, napi);
226bb6b7 645 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
d0412d96 646 }
c9df406f 647
2257e05c
LB		 648 return work_done;
649}
650
651static inline void oom_timer_wrapper(unsigned long data)
652{
653 struct mv643xx_eth_private *mp = (void *)data;
654
655 napi_schedule(&mp->napi);
d0412d96
JC		 656}
657
c9df406f
LB		 658
659/* tx ***********************************************************************/
c9df406f 660static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 661{
13d64285 662 int frag;
1da177e4 663
c9df406f 664 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 665 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
666 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 667 return 1;
1da177e4 668 }
13d64285 669
c9df406f
LB		 670 return 0;
671}
7303fde8 672
13d64285 673static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 674{
675 int tx_desc_curr;
d0412d96 676
13d64285 677 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 678
9da78745
LB		 679 tx_desc_curr = txq->tx_curr_desc++;
680 if (txq->tx_curr_desc == txq->tx_ring_size)
681 txq->tx_curr_desc = 0;
e4d00fa9 682
13d64285 683 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 684
c9df406f
LB		 685 return tx_desc_curr;
686}
468d09f8 687
13d64285 688static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 689{
13d64285 690 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 691 int frag;
1da177e4 692
13d64285
LB		 693 for (frag = 0; frag < nr_frags; frag++) {
694 skb_frag_t *this_frag;
695 int tx_index;
696 struct tx_desc *desc;
697
698 this_frag = &skb_shinfo(skb)->frags[frag];
699 tx_index = txq_alloc_desc_index(txq);
700 desc = &txq->tx_desc_area[tx_index];
701
702 /*
703 * The last fragment will generate an interrupt
704 * which will free the skb on TX completion.
705 */
706 if (frag == nr_frags - 1) {
707 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
708 ZERO_PADDING | TX_LAST_DESC |
709 TX_ENABLE_INTERRUPT;
710 txq->tx_skb[tx_index] = skb;
711 } else {
712 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
713 txq->tx_skb[tx_index] = NULL;
714 }
715
c9df406f
LB		 716 desc->l4i_chk = 0;
717 desc->byte_cnt = this_frag->size;
718 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
719 this_frag->page_offset,
720 this_frag->size,
721 DMA_TO_DEVICE);
722 }
1da177e4
LT		 723}
724
c9df406f
LB		 725static inline __be16 sum16_as_be(__sum16 sum)
726{
727 return (__force __be16)sum;
728}
1da177e4 729
13d64285 730static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 731{
8fa89bf5 732 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 733 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 734 int tx_index;
cc9754b3 735 struct tx_desc *desc;
c9df406f
LB		 736 u32 cmd_sts;
737 int length;
1da177e4 738
cc9754b3 739 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 740
13d64285
LB		 741 tx_index = txq_alloc_desc_index(txq);
742 desc = &txq->tx_desc_area[tx_index];
c9df406f
LB		 743
744 if (nr_frags) {
13d64285 745 txq_submit_frag_skb(txq, skb);
c9df406f
LB		 746
747 length = skb_headlen(skb);
13d64285 748 txq->tx_skb[tx_index] = NULL;
c9df406f 749 } else {
cc9754b3 750 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f 751 length = skb->len;
13d64285 752 txq->tx_skb[tx_index] = skb;
c9df406f
LB		 753 }
754
755 desc->byte_cnt = length;
756 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
757
758 if (skb->ip_summed == CHECKSUM_PARTIAL) {
e32b6617
LB		 759 int mac_hdr_len;
760
761 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
762 skb->protocol != htons(ETH_P_8021Q));
c9df406f 763
cc9754b3
LB		 764 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
765 GEN_IP_V4_CHECKSUM |
766 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f 767
e32b6617
LB		 768 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
769 switch (mac_hdr_len - ETH_HLEN) {
770 case 0:
771 break;
772 case 4:
773 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
774 break;
775 case 8:
776 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
777 break;
778 case 12:
779 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
780 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
781 break;
782 default:
783 if (net_ratelimit())
784 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
785 "mac header length is %d?!\n", mac_hdr_len);
786 break;
787 }
788
c9df406f
LB		 789 switch (ip_hdr(skb)->protocol) {
790 case IPPROTO_UDP:
cc9754b3 791 cmd_sts |= UDP_FRAME;
c9df406f
LB		 792 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
793 break;
794 case IPPROTO_TCP:
795 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
796 break;
797 default:
798 BUG();
799 }
800 } else {
801 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 802 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 803 desc->l4i_chk = 0;
804 }
805
806 /* ensure all other descriptors are written before first cmd_sts */
807 wmb();
808 desc->cmd_sts = cmd_sts;
809
8fa89bf5
LB		 810 /* clear TX_END interrupt status */
811 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
812 rdl(mp, INT_CAUSE(mp->port_num));
813
c9df406f
LB		 814 /* ensure all descriptors are written before poking hardware */
815 wmb();
13d64285 816 txq_enable(txq);
c9df406f 817
13d64285 818 txq->tx_desc_count += nr_frags + 1;
1da177e4 819}
1da177e4 820
fc32b0e2 821static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 822{
e5371493 823 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 824 struct net_device_stats *stats = &dev->stats;
e5ef1de1 825 int queue;
13d64285 826 struct tx_queue *txq;
e5ef1de1 827 struct netdev_queue *nq;
c9df406f 828 unsigned long flags;
e5ef1de1 829 int entries_left;
afdb57a2 830
c9df406f
LB		 831 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
832 stats->tx_dropped++;
fc32b0e2
LB		 833 dev_printk(KERN_DEBUG, &dev->dev,
834 "failed to linearize skb with tiny "
835 "unaligned fragment\n");
c9df406f
LB		 836 return NETDEV_TX_BUSY;
837 }
838
e5ef1de1
LB		 839 queue = skb_get_queue_mapping(skb);
840 txq = mp->txq + queue;
841 nq = netdev_get_tx_queue(dev, queue);
c9df406f 842
e5ef1de1 843 spin_lock_irqsave(&mp->lock, flags);
13d64285 844
17cd0a59 845 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
c9df406f 846 spin_unlock_irqrestore(&mp->lock, flags);
e5ef1de1
LB		 847 if (net_ratelimit())
848 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 849 kfree_skb(skb);
850 return NETDEV_TX_OK;
c9df406f
LB		 851 }
852
13d64285 853 txq_submit_skb(txq, skb);
c9df406f
LB		 854 stats->tx_bytes += skb->len;
855 stats->tx_packets++;
856 dev->trans_start = jiffies;
857
e5ef1de1
LB		 858 entries_left = txq->tx_ring_size - txq->tx_desc_count;
859 if (entries_left < MAX_SKB_FRAGS + 1)
860 netif_tx_stop_queue(nq);
c9df406f
LB		 861
862 spin_unlock_irqrestore(&mp->lock, flags);
863
864 return NETDEV_TX_OK;
1da177e4
LT		 865}
866
c9df406f 867
89df5fdc
LB		 868/* tx rate control **********************************************************/
869/*
870 * Set total maximum TX rate (shared by all TX queues for this port)
871 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
872 */
873static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
874{
875 int token_rate;
876 int mtu;
877 int bucket_size;
878
879 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
880 if (token_rate > 1023)
881 token_rate = 1023;
882
883 mtu = (mp->dev->mtu + 255) >> 8;
884 if (mtu > 63)
885 mtu = 63;
886
887 bucket_size = (burst + 255) >> 8;
888 if (bucket_size > 65535)
889 bucket_size = 65535;
890
1e881592
LB		 891 if (mp->shared->tx_bw_control_moved) {
892 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
893 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
894 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
895 } else {
896 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
897 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
898 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
899 }
89df5fdc
LB		 900}
901
902static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
903{
904 struct mv643xx_eth_private *mp = txq_to_mp(txq);
905 int token_rate;
906 int bucket_size;
907
908 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
909 if (token_rate > 1023)
910 token_rate = 1023;
911
912 bucket_size = (burst + 255) >> 8;
913 if (bucket_size > 65535)
914 bucket_size = 65535;
915
3d6b35bc
LB		 916 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
917 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
89df5fdc
LB		 918 (bucket_size << 10) | token_rate);
919}
920
921static void txq_set_fixed_prio_mode(struct tx_queue *txq)
922{
923 struct mv643xx_eth_private *mp = txq_to_mp(txq);
924 int off;
925 u32 val;
926
927 /*
928 * Turn on fixed priority mode.
929 */
1e881592
LB		 930 if (mp->shared->tx_bw_control_moved)
931 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
932 else
933 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 934
935 val = rdl(mp, off);
3d6b35bc 936 val |= 1 << txq->index;
89df5fdc
LB		 937 wrl(mp, off, val);
938}
939
940static void txq_set_wrr(struct tx_queue *txq, int weight)
941{
942 struct mv643xx_eth_private *mp = txq_to_mp(txq);
943 int off;
944 u32 val;
945
946 /*
947 * Turn off fixed priority mode.
948 */
1e881592
LB		 949 if (mp->shared->tx_bw_control_moved)
950 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
951 else
952 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 953
954 val = rdl(mp, off);
3d6b35bc 955 val &= ~(1 << txq->index);
89df5fdc
LB		 956 wrl(mp, off, val);
957
958 /*
959 * Configure WRR weight for this queue.
960 */
3d6b35bc 961 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
89df5fdc
LB		 962
963 val = rdl(mp, off);
964 val = (val & ~0xff) | (weight & 0xff);
965 wrl(mp, off, val);
966}
967
968
c9df406f 969/* mii management interface *************************************************/
45c5d3bc
LB		 970static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
971{
972 struct mv643xx_eth_shared_private *msp = dev_id;
973
974 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
975 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
976 wake_up(&msp->smi_busy_wait);
977 return IRQ_HANDLED;
978 }
979
980 return IRQ_NONE;
981}
c9df406f 982
45c5d3bc 983static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 984{
45c5d3bc
LB		 985 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
986}
1da177e4 987
45c5d3bc
LB		 988static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
989{
990 if (msp->err_interrupt == NO_IRQ) {
991 int i;
c9df406f 992
45c5d3bc
LB		 993 for (i = 0; !smi_is_done(msp); i++) {
994 if (i == 10)
995 return -ETIMEDOUT;
996 msleep(10);
c9df406f 997 }
45c5d3bc
LB		 998
999 return 0;
1000 }
1001
1002 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1003 msecs_to_jiffies(100)))
1004 return -ETIMEDOUT;
1005
1006 return 0;
1007}
1008
1009static int smi_reg_read(struct mv643xx_eth_private *mp,
1010 unsigned int addr, unsigned int reg)
1011{
fc0eb9f2 1012 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
45c5d3bc
LB		 1013 void __iomem *smi_reg = msp->base + SMI_REG;
1014 int ret;
1015
1016 mutex_lock(&msp->phy_lock);
1017
1018 if (smi_wait_ready(msp)) {
1019 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1020 ret = -ETIMEDOUT;
1021 goto out;
1da177e4
LT		 1022 }
1023
fc32b0e2 1024 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1025
45c5d3bc
LB		 1026 if (smi_wait_ready(msp)) {
1027 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1028 ret = -ETIMEDOUT;
1029 goto out;
1030 }
1031
1032 ret = readl(smi_reg);
1033 if (!(ret & SMI_READ_VALID)) {
1034 printk("%s: SMI bus read not valid\n", mp->dev->name);
1035 ret = -ENODEV;
1036 goto out;
c9df406f
LB		 1037 }
1038
45c5d3bc
LB		 1039 ret &= 0xffff;
1040
c9df406f 1041out:
45c5d3bc
LB		 1042 mutex_unlock(&msp->phy_lock);
1043
1044 return ret;
1da177e4
LT		 1045}
1046
45c5d3bc
LB		 1047static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1048 unsigned int reg, unsigned int value)
1da177e4 1049{
fc0eb9f2 1050 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
45c5d3bc 1051 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1052
45c5d3bc 1053 mutex_lock(&msp->phy_lock);
c9df406f 1054
45c5d3bc
LB		 1055 if (smi_wait_ready(msp)) {
1056 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1057 mutex_unlock(&msp->phy_lock);
1058 return -ETIMEDOUT;
1da177e4
LT		 1059 }
1060
fc32b0e2
LB		 1061 writel(SMI_OPCODE_WRITE | (reg << 21) |
1062 (addr << 16) | (value & 0xffff), smi_reg);
45c5d3bc
LB		 1063
1064 mutex_unlock(&msp->phy_lock);
1065
1066 return 0;
c9df406f 1067}
1da177e4 1068
c9df406f
LB		 1069
1070/* mib counters *************************************************************/
fc32b0e2 1071static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1072{
fc32b0e2 1073 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1074}
1075
fc32b0e2 1076static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1077{
fc32b0e2
LB		 1078 int i;
1079
1080 for (i = 0; i < 0x80; i += 4)
1081 mib_read(mp, i);
c9df406f 1082}
d0412d96 1083
fc32b0e2 1084static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1085{
e5371493 1086 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1087
fc32b0e2
LB		 1088 p->good_octets_received += mib_read(mp, 0x00);
1089 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1090 p->bad_octets_received += mib_read(mp, 0x08);
1091 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1092 p->good_frames_received += mib_read(mp, 0x10);
1093 p->bad_frames_received += mib_read(mp, 0x14);
1094 p->broadcast_frames_received += mib_read(mp, 0x18);
1095 p->multicast_frames_received += mib_read(mp, 0x1c);
1096 p->frames_64_octets += mib_read(mp, 0x20);
1097 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1098 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1099 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1100 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1101 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1102 p->good_octets_sent += mib_read(mp, 0x38);
1103 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1104 p->good_frames_sent += mib_read(mp, 0x40);
1105 p->excessive_collision += mib_read(mp, 0x44);
1106 p->multicast_frames_sent += mib_read(mp, 0x48);
1107 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1108 p->unrec_mac_control_received += mib_read(mp, 0x50);
1109 p->fc_sent += mib_read(mp, 0x54);
1110 p->good_fc_received += mib_read(mp, 0x58);
1111 p->bad_fc_received += mib_read(mp, 0x5c);
1112 p->undersize_received += mib_read(mp, 0x60);
1113 p->fragments_received += mib_read(mp, 0x64);
1114 p->oversize_received += mib_read(mp, 0x68);
1115 p->jabber_received += mib_read(mp, 0x6c);
1116 p->mac_receive_error += mib_read(mp, 0x70);
1117 p->bad_crc_event += mib_read(mp, 0x74);
1118 p->collision += mib_read(mp, 0x78);
1119 p->late_collision += mib_read(mp, 0x7c);
d0412d96
JC		 1120}
1121
c9df406f
LB		 1122
1123/* ethtool ******************************************************************/
e5371493 1124struct mv643xx_eth_stats {
c9df406f
LB		 1125 char stat_string[ETH_GSTRING_LEN];
1126 int sizeof_stat;
16820054
LB		 1127 int netdev_off;
1128 int mp_off;
c9df406f
LB		 1129};
1130
16820054
LB		 1131#define SSTAT(m) \
1132 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1133 offsetof(struct net_device, stats.m), -1 }
1134
1135#define MIBSTAT(m) \
1136 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1137 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1138
1139static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1140 SSTAT(rx_packets),
1141 SSTAT(tx_packets),
1142 SSTAT(rx_bytes),
1143 SSTAT(tx_bytes),
1144 SSTAT(rx_errors),
1145 SSTAT(tx_errors),
1146 SSTAT(rx_dropped),
1147 SSTAT(tx_dropped),
1148 MIBSTAT(good_octets_received),
1149 MIBSTAT(bad_octets_received),
1150 MIBSTAT(internal_mac_transmit_err),
1151 MIBSTAT(good_frames_received),
1152 MIBSTAT(bad_frames_received),
1153 MIBSTAT(broadcast_frames_received),
1154 MIBSTAT(multicast_frames_received),
1155 MIBSTAT(frames_64_octets),
1156 MIBSTAT(frames_65_to_127_octets),
1157 MIBSTAT(frames_128_to_255_octets),
1158 MIBSTAT(frames_256_to_511_octets),
1159 MIBSTAT(frames_512_to_1023_octets),
1160 MIBSTAT(frames_1024_to_max_octets),
1161 MIBSTAT(good_octets_sent),
1162 MIBSTAT(good_frames_sent),
1163 MIBSTAT(excessive_collision),
1164 MIBSTAT(multicast_frames_sent),
1165 MIBSTAT(broadcast_frames_sent),
1166 MIBSTAT(unrec_mac_control_received),
1167 MIBSTAT(fc_sent),
1168 MIBSTAT(good_fc_received),
1169 MIBSTAT(bad_fc_received),
1170 MIBSTAT(undersize_received),
1171 MIBSTAT(fragments_received),
1172 MIBSTAT(oversize_received),
1173 MIBSTAT(jabber_received),
1174 MIBSTAT(mac_receive_error),
1175 MIBSTAT(bad_crc_event),
1176 MIBSTAT(collision),
1177 MIBSTAT(late_collision),
c9df406f
LB		 1178};
1179
e5371493 1180static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1181{
e5371493 1182 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1183 int err;
1184
d0412d96 1185 err = mii_ethtool_gset(&mp->mii, cmd);
d0412d96 1186
fc32b0e2
LB		 1187 /*
1188 * The MAC does not support 1000baseT_Half.
1189 */
d0412d96
JC		 1190 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1191 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1192
1193 return err;
1194}
1195
bedfe324
LB		 1196static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1197{
81600eea
LB		 1198 struct mv643xx_eth_private *mp = netdev_priv(dev);
1199 u32 port_status;
1200
1201 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1202
bedfe324
LB		 1203 cmd->supported = SUPPORTED_MII;
1204 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1205 switch (port_status & PORT_SPEED_MASK) {
1206 case PORT_SPEED_10:
1207 cmd->speed = SPEED_10;
1208 break;
1209 case PORT_SPEED_100:
1210 cmd->speed = SPEED_100;
1211 break;
1212 case PORT_SPEED_1000:
1213 cmd->speed = SPEED_1000;
1214 break;
1215 default:
1216 cmd->speed = -1;
1217 break;
1218 }
1219 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1220 cmd->port = PORT_MII;
1221 cmd->phy_address = 0;
1222 cmd->transceiver = XCVR_INTERNAL;
1223 cmd->autoneg = AUTONEG_DISABLE;
1224 cmd->maxtxpkt = 1;
1225 cmd->maxrxpkt = 1;
1226
1227 return 0;
1228}
1229
e5371493 1230static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1231{
e5371493 1232 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1233
fc32b0e2
LB		 1234 /*
1235 * The MAC does not support 1000baseT_Half.
1236 */
1237 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1238
2b3ba0e3 1239 return mii_ethtool_sset(&mp->mii, cmd);
c9df406f 1240}
1da177e4 1241
bedfe324
LB		 1242static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1243{
1244 return -EINVAL;
1245}
1246
fc32b0e2
LB		 1247static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1248 struct ethtool_drvinfo *drvinfo)
c9df406f 1249{
e5371493
LB		 1250 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1251 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1252 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1253 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1254 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1255}
1da177e4 1256
fc32b0e2 1257static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1258{
e5371493 1259 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1260
c9df406f
LB		 1261 return mii_nway_restart(&mp->mii);
1262}
1da177e4 1263
bedfe324
LB		 1264static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1265{
1266 return -EINVAL;
1267}
1268
c9df406f
LB		 1269static u32 mv643xx_eth_get_link(struct net_device *dev)
1270{
e5371493 1271 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1272
c9df406f
LB		 1273 return mii_link_ok(&mp->mii);
1274}
1da177e4 1275
bedfe324
LB		 1276static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1277{
1278 return 1;
1279}
1280
fc32b0e2
LB		 1281static void mv643xx_eth_get_strings(struct net_device *dev,
1282 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1283{
1284 int i;
1da177e4 1285
fc32b0e2
LB		 1286 if (stringset == ETH_SS_STATS) {
1287 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1288 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1289 mv643xx_eth_stats[i].stat_string,
e5371493 1290 ETH_GSTRING_LEN);
c9df406f 1291 }
c9df406f
LB		 1292 }
1293}
1da177e4 1294
fc32b0e2
LB		 1295static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1296 struct ethtool_stats *stats,
1297 uint64_t *data)
c9df406f 1298{
b9873841 1299 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1300 int i;
1da177e4 1301
fc32b0e2 1302 mib_counters_update(mp);
1da177e4 1303
16820054
LB		 1304 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1305 const struct mv643xx_eth_stats *stat;
1306 void *p;
1307
1308 stat = mv643xx_eth_stats + i;
1309
1310 if (stat->netdev_off >= 0)
1311 p = ((void *)mp->dev) + stat->netdev_off;
1312 else
1313 p = ((void *)mp) + stat->mp_off;
1314
1315 data[i] = (stat->sizeof_stat == 8) ?
1316 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1317 }
c9df406f 1318}
1da177e4 1319
fc32b0e2 1320static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1321{
fc32b0e2 1322 if (sset == ETH_SS_STATS)
16820054 1323 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1324
1325 return -EOPNOTSUPP;
c9df406f 1326}
1da177e4 1327
e5371493 1328static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1329 .get_settings = mv643xx_eth_get_settings,
1330 .set_settings = mv643xx_eth_set_settings,
1331 .get_drvinfo = mv643xx_eth_get_drvinfo,
1332 .nway_reset = mv643xx_eth_nway_reset,
1333 .get_link = mv643xx_eth_get_link,
c9df406f 1334 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1335 .get_strings = mv643xx_eth_get_strings,
1336 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1337 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1338};
1da177e4 1339
bedfe324
LB		 1340static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1341 .get_settings = mv643xx_eth_get_settings_phyless,
1342 .set_settings = mv643xx_eth_set_settings_phyless,
1343 .get_drvinfo = mv643xx_eth_get_drvinfo,
1344 .nway_reset = mv643xx_eth_nway_reset_phyless,
1345 .get_link = mv643xx_eth_get_link_phyless,
1346 .set_sg = ethtool_op_set_sg,
1347 .get_strings = mv643xx_eth_get_strings,
1348 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1349 .get_sset_count = mv643xx_eth_get_sset_count,
1350};
1351
bea3348e 1352
c9df406f 1353/* address handling *********************************************************/
5daffe94 1354static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1355{
c9df406f
LB		 1356 unsigned int mac_h;
1357 unsigned int mac_l;
1da177e4 1358
fc32b0e2
LB		 1359 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1360 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1361
5daffe94
LB		 1362 addr[0] = (mac_h >> 24) & 0xff;
1363 addr[1] = (mac_h >> 16) & 0xff;
1364 addr[2] = (mac_h >> 8) & 0xff;
1365 addr[3] = mac_h & 0xff;
1366 addr[4] = (mac_l >> 8) & 0xff;
1367 addr[5] = mac_l & 0xff;
c9df406f 1368}
1da177e4 1369
e5371493 1370static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1371{
fc32b0e2 1372 int i;
1da177e4 1373
fc32b0e2
LB		 1374 for (i = 0; i < 0x100; i += 4) {
1375 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1376 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1377 }
fc32b0e2
LB		 1378
1379 for (i = 0; i < 0x10; i += 4)
1380 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1381}
d0412d96 1382
e5371493 1383static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1384 int table, unsigned char entry)
c9df406f
LB		 1385{
1386 unsigned int table_reg;
ab4384a6 1387
c9df406f 1388 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1389 table_reg = rdl(mp, table + (entry & 0xfc));
1390 table_reg |= 0x01 << (8 * (entry & 3));
1391 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1392}
1393
5daffe94 1394static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1395{
c9df406f
LB		 1396 unsigned int mac_h;
1397 unsigned int mac_l;
1398 int table;
1da177e4 1399
fc32b0e2
LB		 1400 mac_l = (addr[4] << 8) | addr[5];
1401 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1402
fc32b0e2
LB		 1403 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1404 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1405
fc32b0e2 1406 table = UNICAST_TABLE(mp->port_num);
5daffe94 1407 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1408}
1409
fc32b0e2 1410static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1411{
e5371493 1412 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1413
fc32b0e2
LB		 1414 /* +2 is for the offset of the HW addr type */
1415 memcpy(dev->dev_addr, addr + 2, 6);
1416
cc9754b3
LB		 1417 init_mac_tables(mp);
1418 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1419
1420 return 0;
1421}
1422
69876569
LB		 1423static int addr_crc(unsigned char *addr)
1424{
1425 int crc = 0;
1426 int i;
1427
1428 for (i = 0; i < 6; i++) {
1429 int j;
1430
1431 crc = (crc ^ addr[i]) << 8;
1432 for (j = 7; j >= 0; j--) {
1433 if (crc & (0x100 << j))
1434 crc ^= 0x107 << j;
1435 }
1436 }
1437
1438 return crc;
1439}
1440
fc32b0e2 1441static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1442{
fc32b0e2
LB		 1443 struct mv643xx_eth_private *mp = netdev_priv(dev);
1444 u32 port_config;
1445 struct dev_addr_list *addr;
1446 int i;
c8aaea25 1447
fc32b0e2
LB		 1448 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1449 if (dev->flags & IFF_PROMISC)
1450 port_config |= UNICAST_PROMISCUOUS_MODE;
1451 else
1452 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1453 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1454
fc32b0e2
LB		 1455 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1456 int port_num = mp->port_num;
1457 u32 accept = 0x01010101;
c8aaea25 1458
fc32b0e2
LB		 1459 for (i = 0; i < 0x100; i += 4) {
1460 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1461 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1462 }
1463 return;
1464 }
c8aaea25 1465
fc32b0e2
LB		 1466 for (i = 0; i < 0x100; i += 4) {
1467 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1468 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1469 }
1470
fc32b0e2
LB		 1471 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1472 u8 *a = addr->da_addr;
1473 int table;
324ff2c1 1474
fc32b0e2
LB		 1475 if (addr->da_addrlen != 6)
1476 continue;
1da177e4 1477
fc32b0e2
LB		 1478 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1479 table = SPECIAL_MCAST_TABLE(mp->port_num);
1480 set_filter_table_entry(mp, table, a[5]);
1481 } else {
1482 int crc = addr_crc(a);
1da177e4 1483
fc32b0e2
LB		 1484 table = OTHER_MCAST_TABLE(mp->port_num);
1485 set_filter_table_entry(mp, table, crc);
1486 }
1487 }
c9df406f 1488}
c8aaea25 1489
c8aaea25 1490
c9df406f 1491/* rx/tx queue initialisation ***********************************************/
64da80a2 1492static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1493{
64da80a2 1494 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1495 struct rx_desc *rx_desc;
1496 int size;
c9df406f
LB		 1497 int i;
1498
64da80a2
LB		 1499 rxq->index = index;
1500
8a578111
LB		 1501 rxq->rx_ring_size = mp->default_rx_ring_size;
1502
1503 rxq->rx_desc_count = 0;
1504 rxq->rx_curr_desc = 0;
1505 rxq->rx_used_desc = 0;
1506
1507 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1508
f7981c1c 1509 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1510 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1511 mp->rx_desc_sram_size);
1512 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1513 } else {
1514 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1515 &rxq->rx_desc_dma,
1516 GFP_KERNEL);
f7ea3337
PJ		 1517 }
1518
8a578111
LB		 1519 if (rxq->rx_desc_area == NULL) {
1520 dev_printk(KERN_ERR, &mp->dev->dev,
1521 "can't allocate rx ring (%d bytes)\n", size);
1522 goto out;
1523 }
1524 memset(rxq->rx_desc_area, 0, size);
1da177e4 1525
8a578111
LB		 1526 rxq->rx_desc_area_size = size;
1527 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1528 GFP_KERNEL);
1529 if (rxq->rx_skb == NULL) {
1530 dev_printk(KERN_ERR, &mp->dev->dev,
1531 "can't allocate rx skb ring\n");
1532 goto out_free;
1533 }
1534
1535 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1536 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1537 int nexti;
1538
1539 nexti = i + 1;
1540 if (nexti == rxq->rx_ring_size)
1541 nexti = 0;
1542
8a578111
LB		 1543 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1544 nexti * sizeof(struct rx_desc);
1545 }
1546
8a578111
LB		 1547 return 0;
1548
1549
1550out_free:
f7981c1c 1551 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1552 iounmap(rxq->rx_desc_area);
1553 else
1554 dma_free_coherent(NULL, size,
1555 rxq->rx_desc_area,
1556 rxq->rx_desc_dma);
1557
1558out:
1559 return -ENOMEM;
c9df406f 1560}
c8aaea25 1561
8a578111 1562static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1563{
8a578111
LB		 1564 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1565 int i;
1566
1567 rxq_disable(rxq);
c8aaea25 1568
8a578111
LB		 1569 for (i = 0; i < rxq->rx_ring_size; i++) {
1570 if (rxq->rx_skb[i]) {
1571 dev_kfree_skb(rxq->rx_skb[i]);
1572 rxq->rx_desc_count--;
1da177e4 1573 }
c8aaea25 1574 }
1da177e4 1575
8a578111
LB		 1576 if (rxq->rx_desc_count) {
1577 dev_printk(KERN_ERR, &mp->dev->dev,
1578 "error freeing rx ring -- %d skbs stuck\n",
1579 rxq->rx_desc_count);
1580 }
1581
f7981c1c 1582 if (rxq->index == 0 &&
64da80a2 1583 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1584 iounmap(rxq->rx_desc_area);
c9df406f 1585 else
8a578111
LB		 1586 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1587 rxq->rx_desc_area, rxq->rx_desc_dma);
1588
1589 kfree(rxq->rx_skb);
c9df406f 1590}
1da177e4 1591
3d6b35bc 1592static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1593{
3d6b35bc 1594 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1595 struct tx_desc *tx_desc;
1596 int size;
c9df406f 1597 int i;
1da177e4 1598
3d6b35bc
LB		 1599 txq->index = index;
1600
13d64285
LB		 1601 txq->tx_ring_size = mp->default_tx_ring_size;
1602
1603 txq->tx_desc_count = 0;
1604 txq->tx_curr_desc = 0;
1605 txq->tx_used_desc = 0;
1606
1607 size = txq->tx_ring_size * sizeof(struct tx_desc);
1608
f7981c1c 1609 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1610 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1611 mp->tx_desc_sram_size);
1612 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1613 } else {
1614 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1615 &txq->tx_desc_dma,
1616 GFP_KERNEL);
1617 }
1618
1619 if (txq->tx_desc_area == NULL) {
1620 dev_printk(KERN_ERR, &mp->dev->dev,
1621 "can't allocate tx ring (%d bytes)\n", size);
1622 goto out;
c9df406f 1623 }
13d64285
LB		 1624 memset(txq->tx_desc_area, 0, size);
1625
1626 txq->tx_desc_area_size = size;
1627 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1628 GFP_KERNEL);
1629 if (txq->tx_skb == NULL) {
1630 dev_printk(KERN_ERR, &mp->dev->dev,
1631 "can't allocate tx skb ring\n");
1632 goto out_free;
1633 }
1634
1635 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1636 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1637 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1638 int nexti;
1639
1640 nexti = i + 1;
1641 if (nexti == txq->tx_ring_size)
1642 nexti = 0;
6b368f68
LB		 1643
1644 txd->cmd_sts = 0;
1645 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1646 nexti * sizeof(struct tx_desc);
1647 }
1648
1649 return 0;
1650
c9df406f 1651
13d64285 1652out_free:
f7981c1c 1653 if (index == 0 && size <= mp->tx_desc_sram_size)
13d64285
LB		 1654 iounmap(txq->tx_desc_area);
1655 else
1656 dma_free_coherent(NULL, size,
1657 txq->tx_desc_area,
1658 txq->tx_desc_dma);
c9df406f 1659
13d64285
LB		 1660out:
1661 return -ENOMEM;
c8aaea25 1662}
1da177e4 1663
13d64285 1664static void txq_reclaim(struct tx_queue *txq, int force)
c8aaea25 1665{
13d64285 1666 struct mv643xx_eth_private *mp = txq_to_mp(txq);
c8aaea25 1667 unsigned long flags;
1da177e4 1668
13d64285
LB		 1669 spin_lock_irqsave(&mp->lock, flags);
1670 while (txq->tx_desc_count > 0) {
1671 int tx_index;
1672 struct tx_desc *desc;
1673 u32 cmd_sts;
1674 struct sk_buff *skb;
1675 dma_addr_t addr;
1676 int count;
4d64e718 1677
13d64285
LB		 1678 tx_index = txq->tx_used_desc;
1679 desc = &txq->tx_desc_area[tx_index];
c9df406f 1680 cmd_sts = desc->cmd_sts;
4d64e718 1681
6b368f68
LB		 1682 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1683 if (!force)
1684 break;
1685 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1686 }
1da177e4 1687
9da78745
LB		 1688 txq->tx_used_desc = tx_index + 1;
1689 if (txq->tx_used_desc == txq->tx_ring_size)
1690 txq->tx_used_desc = 0;
13d64285 1691 txq->tx_desc_count--;
1da177e4 1692
c9df406f
LB		 1693 addr = desc->buf_ptr;
1694 count = desc->byte_cnt;
13d64285
LB		 1695 skb = txq->tx_skb[tx_index];
1696 txq->tx_skb[tx_index] = NULL;
c8aaea25 1697
cc9754b3 1698 if (cmd_sts & ERROR_SUMMARY) {
13d64285
LB		 1699 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1700 mp->dev->stats.tx_errors++;
c9df406f 1701 }
1da177e4 1702
13d64285
LB		 1703 /*
1704 * Drop mp->lock while we free the skb.
1705 */
c9df406f 1706 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 1707
cc9754b3 1708 if (cmd_sts & TX_FIRST_DESC)
c9df406f
LB		 1709 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1710 else
1711 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
c2e5b352 1712
c9df406f
LB		 1713 if (skb)
1714 dev_kfree_skb_irq(skb);
63c9e549 1715
13d64285 1716 spin_lock_irqsave(&mp->lock, flags);
c9df406f 1717 }
13d64285 1718 spin_unlock_irqrestore(&mp->lock, flags);
c9df406f 1719}
1da177e4 1720
13d64285 1721static void txq_deinit(struct tx_queue *txq)
c9df406f 1722{
13d64285 1723 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1724
13d64285
LB		 1725 txq_disable(txq);
1726 txq_reclaim(txq, 1);
1da177e4 1727
13d64285 1728 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1729
f7981c1c 1730 if (txq->index == 0 &&
3d6b35bc 1731 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1732 iounmap(txq->tx_desc_area);
c9df406f 1733 else
13d64285
LB		 1734 dma_free_coherent(NULL, txq->tx_desc_area_size,
1735 txq->tx_desc_area, txq->tx_desc_dma);
1736
1737 kfree(txq->tx_skb);
c9df406f 1738}
1da177e4 1739
1da177e4 1740
c9df406f 1741/* netdev ops and related ***************************************************/
2f7eb47a
LB		 1742static void handle_link_event(struct mv643xx_eth_private *mp)
1743{
1744 struct net_device *dev = mp->dev;
1745 u32 port_status;
1746 int speed;
1747 int duplex;
1748 int fc;
1749
1750 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1751 if (!(port_status & LINK_UP)) {
1752 if (netif_carrier_ok(dev)) {
1753 int i;
1754
1755 printk(KERN_INFO "%s: link down\n", dev->name);
1756
1757 netif_carrier_off(dev);
2f7eb47a 1758
f7981c1c 1759 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 1760 struct tx_queue *txq = mp->txq + i;
1761
f7981c1c
LB		 1762 txq_reclaim(txq, 1);
1763 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 1764 }
1765 }
1766 return;
1767 }
1768
1769 switch (port_status & PORT_SPEED_MASK) {
1770 case PORT_SPEED_10:
1771 speed = 10;
1772 break;
1773 case PORT_SPEED_100:
1774 speed = 100;
1775 break;
1776 case PORT_SPEED_1000:
1777 speed = 1000;
1778 break;
1779 default:
1780 speed = -1;
1781 break;
1782 }
1783 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1784 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1785
1786 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1787 "flow control %sabled\n", dev->name,
1788 speed, duplex ? "full" : "half",
1789 fc ? "en" : "dis");
1790
4fdeca3f 1791 if (!netif_carrier_ok(dev))
2f7eb47a 1792 netif_carrier_on(dev);
2f7eb47a
LB		 1793}
1794
fc32b0e2 1795static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
c9df406f
LB		 1796{
1797 struct net_device *dev = (struct net_device *)dev_id;
e5371493 1798 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2
LB		 1799 u32 int_cause;
1800 u32 int_cause_ext;
ce4e2e45 1801
226bb6b7
LB		 1802 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1803 (INT_TX_END | INT_RX | INT_EXT);
fc32b0e2
LB		 1804 if (int_cause == 0)
1805 return IRQ_NONE;
1806
1807 int_cause_ext = 0;
cc9754b3 1808 if (int_cause & INT_EXT) {
13d64285 1809 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
befefe21 1810 & (INT_EXT_LINK_PHY | INT_EXT_TX);
13d64285 1811 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
c9df406f 1812 }
1da177e4 1813
befefe21 1814 if (int_cause_ext & INT_EXT_LINK_PHY)
2f7eb47a 1815 handle_link_event(mp);
1da177e4 1816
64da80a2
LB		 1817 /*
1818 * RxBuffer or RxError set for any of the 8 queues?
1819 */
cc9754b3 1820 if (int_cause & INT_RX) {
819ddcaf 1821 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_RX));
13d64285 1822 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
13d64285 1823 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1824
2257e05c 1825 napi_schedule(&mp->napi);
84dd619e 1826 }
fc32b0e2 1827
3d6b35bc
LB		 1828 /*
1829 * TxBuffer or TxError set for any of the 8 queues?
1830 */
13d64285 1831 if (int_cause_ext & INT_EXT_TX) {
3d6b35bc
LB		 1832 int i;
1833
f7981c1c
LB		 1834 for (i = 0; i < mp->txq_count; i++)
1835 txq_reclaim(mp->txq + i, 0);
8fa89bf5
LB		 1836
1837 /*
1838 * Enough space again in the primary TX queue for a
1839 * full packet?
1840 */
4fdeca3f
LB		 1841 spin_lock(&mp->lock);
1842 __txq_maybe_wake(mp->txq);
1843 spin_unlock(&mp->lock);
226bb6b7 1844 }
3d6b35bc 1845
226bb6b7
LB		 1846 /*
1847 * Any TxEnd interrupts?
1848 */
1849 if (int_cause & INT_TX_END) {
1850 int i;
1851
1852 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
8fa89bf5
LB		 1853
1854 spin_lock(&mp->lock);
226bb6b7
LB		 1855 for (i = 0; i < 8; i++) {
1856 struct tx_queue *txq = mp->txq + i;
8fa89bf5
LB		 1857 u32 hw_desc_ptr;
1858 u32 expected_ptr;
1859
1860 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1861 continue;
1862
1863 hw_desc_ptr =
1864 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1865 expected_ptr = (u32)txq->tx_desc_dma +
1866 txq->tx_curr_desc * sizeof(struct tx_desc);
1867
1868 if (hw_desc_ptr != expected_ptr)
226bb6b7
LB		 1869 txq_enable(txq);
1870 }
8fa89bf5 1871 spin_unlock(&mp->lock);
13d64285 1872 }
1da177e4 1873
c9df406f 1874 return IRQ_HANDLED;
1da177e4
LT		 1875}
1876
e5371493 1877static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1878{
45c5d3bc
LB		 1879 int data;
1880
1881 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1882 if (data < 0)
1883 return;
1da177e4 1884
7f106c1d 1885 data |= BMCR_RESET;
45c5d3bc
LB		 1886 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1887 return;
1da177e4 1888
c9df406f 1889 do {
45c5d3bc
LB		 1890 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1891 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 1892}
1893
fc32b0e2 1894static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1895{
d0412d96 1896 u32 pscr;
8a578111 1897 int i;
1da177e4 1898
bedfe324
LB		 1899 /*
1900 * Perform PHY reset, if there is a PHY.
1901 */
1902 if (mp->phy_addr != -1) {
1903 struct ethtool_cmd cmd;
1904
1905 mv643xx_eth_get_settings(mp->dev, &cmd);
1906 phy_reset(mp);
1907 mv643xx_eth_set_settings(mp->dev, &cmd);
1908 }
1da177e4 1909
81600eea
LB		 1910 /*
1911 * Configure basic link parameters.
1912 */
1913 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1914
1915 pscr |= SERIAL_PORT_ENABLE;
1916 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1917
1918 pscr |= DO_NOT_FORCE_LINK_FAIL;
1919 if (mp->phy_addr == -1)
1920 pscr |= FORCE_LINK_PASS;
1921 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1922
1923 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1924
13d64285
LB		 1925 /*
1926 * Configure TX path and queues.
1927 */
89df5fdc 1928 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 1929 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 1930 struct tx_queue *txq = mp->txq + i;
13d64285 1931
6b368f68 1932 txq_reset_hw_ptr(txq);
89df5fdc
LB		 1933 txq_set_rate(txq, 1000000000, 16777216);
1934 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1935 }
1936
fc32b0e2
LB		 1937 /*
1938 * Add configured unicast address to address filter table.
1939 */
1940 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1941
d9a073ea
LB		 1942 /*
1943 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1944 * frames to RX queue #0.
1945 */
8a578111 1946 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
01999873 1947
376489a2
LB		 1948 /*
1949 * Treat BPDUs as normal multicasts, and disable partition mode.
1950 */
8a578111 1951 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 1952
8a578111 1953 /*
64da80a2 1954 * Enable the receive queues.
8a578111 1955 */
f7981c1c 1956 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 1957 struct rx_queue *rxq = mp->rxq + i;
1958 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
8a578111 1959 u32 addr;
1da177e4 1960
8a578111
LB		 1961 addr = (u32)rxq->rx_desc_dma;
1962 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1963 wrl(mp, off, addr);
1da177e4 1964
8a578111
LB		 1965 rxq_enable(rxq);
1966 }
1da177e4
LT		 1967}
1968
ffd86bbe 1969static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1970{
c9df406f 1971 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 1972 u32 val;
1da177e4 1973
773fc3ee
LB		 1974 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1975 if (mp->shared->extended_rx_coal_limit) {
1976 if (coal > 0xffff)
1977 coal = 0xffff;
1978 val &= ~0x023fff80;
1979 val |= (coal & 0x8000) << 10;
1980 val |= (coal & 0x7fff) << 7;
1981 } else {
1982 if (coal > 0x3fff)
1983 coal = 0x3fff;
1984 val &= ~0x003fff00;
1985 val |= (coal & 0x3fff) << 8;
1986 }
1987 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1da177e4
LT		 1988}
1989
ffd86bbe 1990static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1991{
c9df406f 1992 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1993
fc32b0e2
LB		 1994 if (coal > 0x3fff)
1995 coal = 0x3fff;
1996 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 1997}
1998
c9df406f 1999static int mv643xx_eth_open(struct net_device *dev)
16e03018 2000{
e5371493 2001 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2002 int err;
2257e05c 2003 int oom;
64da80a2 2004 int i;
16e03018 2005
fc32b0e2
LB		 2006 wrl(mp, INT_CAUSE(mp->port_num), 0);
2007 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2008 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 2009
fc32b0e2 2010 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2011 IRQF_SHARED, dev->name, dev);
c9df406f 2012 if (err) {
fc32b0e2 2013 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2014 return -EAGAIN;
16e03018
DF		 2015 }
2016
fc32b0e2 2017 init_mac_tables(mp);
16e03018 2018
2257e05c
LB		 2019 napi_enable(&mp->napi);
2020
2021 oom = 0;
f7981c1c 2022 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2023 err = rxq_init(mp, i);
2024 if (err) {
2025 while (--i >= 0)
f7981c1c 2026 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2027 goto out;
2028 }
2029
2257e05c
LB		 2030 rxq_refill(mp->rxq + i, INT_MAX, &oom);
2031 }
2032
2033 if (oom) {
2034 mp->rx_oom.expires = jiffies + (HZ / 10);
2035 add_timer(&mp->rx_oom);
64da80a2 2036 }
8a578111 2037
f7981c1c 2038 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2039 err = txq_init(mp, i);
2040 if (err) {
2041 while (--i >= 0)
f7981c1c 2042 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2043 goto out_free;
2044 }
2045 }
16e03018 2046
2f7eb47a 2047 netif_carrier_off(dev);
2f7eb47a 2048
fc32b0e2 2049 port_start(mp);
16e03018 2050
ffd86bbe
LB		 2051 set_rx_coal(mp, 0);
2052 set_tx_coal(mp, 0);
16e03018 2053
befefe21 2054 wrl(mp, INT_MASK_EXT(mp->port_num), INT_EXT_LINK_PHY | INT_EXT_TX);
226bb6b7 2055 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
16e03018 2056
c9df406f
LB		 2057 return 0;
2058
13d64285 2059
fc32b0e2 2060out_free:
f7981c1c
LB		 2061 for (i = 0; i < mp->rxq_count; i++)
2062 rxq_deinit(mp->rxq + i);
fc32b0e2 2063out:
c9df406f
LB		 2064 free_irq(dev->irq, dev);
2065
2066 return err;
16e03018
DF		 2067}
2068
e5371493 2069static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2070{
fc32b0e2 2071 unsigned int data;
64da80a2 2072 int i;
1da177e4 2073
f7981c1c
LB		 2074 for (i = 0; i < mp->rxq_count; i++)
2075 rxq_disable(mp->rxq + i);
2076 for (i = 0; i < mp->txq_count; i++)
2077 txq_disable(mp->txq + i);
ae9ae064
LB		 2078
2079 while (1) {
2080 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2081
2082 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2083 break;
13d64285 2084 udelay(10);
ae9ae064 2085 }
1da177e4 2086
c9df406f 2087 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 2088 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2089 data &= ~(SERIAL_PORT_ENABLE |
2090 DO_NOT_FORCE_LINK_FAIL |
2091 FORCE_LINK_PASS);
2092 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 2093}
2094
c9df406f 2095static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2096{
e5371493 2097 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2098 int i;
1da177e4 2099
fc32b0e2
LB		 2100 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2101 rdl(mp, INT_MASK(mp->port_num));
1da177e4 2102
c9df406f 2103 napi_disable(&mp->napi);
78fff83b 2104
2257e05c
LB		 2105 del_timer_sync(&mp->rx_oom);
2106
c9df406f 2107 netif_carrier_off(dev);
1da177e4 2108
fc32b0e2
LB		 2109 free_irq(dev->irq, dev);
2110
cc9754b3 2111 port_reset(mp);
fc32b0e2 2112 mib_counters_update(mp);
1da177e4 2113
f7981c1c
LB		 2114 for (i = 0; i < mp->rxq_count; i++)
2115 rxq_deinit(mp->rxq + i);
2116 for (i = 0; i < mp->txq_count; i++)
2117 txq_deinit(mp->txq + i);
1da177e4 2118
c9df406f 2119 return 0;
1da177e4
LT		 2120}
2121
fc32b0e2 2122static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2123{
e5371493 2124 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2125
bedfe324
LB		 2126 if (mp->phy_addr != -1)
2127 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2128
2129 return -EOPNOTSUPP;
1da177e4
LT		 2130}
2131
c9df406f 2132static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2133{
89df5fdc
LB		 2134 struct mv643xx_eth_private *mp = netdev_priv(dev);
2135
fc32b0e2 2136 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2137 return -EINVAL;
1da177e4 2138
c9df406f 2139 dev->mtu = new_mtu;
89df5fdc
LB		 2140 tx_set_rate(mp, 1000000000, 16777216);
2141
c9df406f
LB		 2142 if (!netif_running(dev))
2143 return 0;
1da177e4 2144
c9df406f
LB		 2145 /*
2146 * Stop and then re-open the interface. This will allocate RX
2147 * skbs of the new MTU.
2148 * There is a possible danger that the open will not succeed,
fc32b0e2 2149 * due to memory being full.
c9df406f
LB		 2150 */
2151 mv643xx_eth_stop(dev);
2152 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2153 dev_printk(KERN_ERR, &dev->dev,
2154 "fatal error on re-opening device after "
2155 "MTU change\n");
c9df406f
LB		 2156 }
2157
2158 return 0;
1da177e4
LT		 2159}
2160
fc32b0e2 2161static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2162{
fc32b0e2 2163 struct mv643xx_eth_private *mp;
1da177e4 2164
fc32b0e2
LB		 2165 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2166 if (netif_running(mp->dev)) {
e5ef1de1 2167 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2168 port_reset(mp);
2169 port_start(mp);
e5ef1de1 2170 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2171 }
c9df406f
LB		 2172}
2173
c9df406f 2174static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2175{
e5371493 2176 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2177
fc32b0e2 2178 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2179
c9df406f 2180 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2181}
2182
c9df406f 2183#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2184static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2185{
fc32b0e2 2186 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2187
fc32b0e2
LB		 2188 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2189 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2190
fc32b0e2 2191 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2192
f2ca60f2 2193 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2194}
c9df406f 2195#endif
9f8dd319 2196
fc32b0e2 2197static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
9f8dd319 2198{
e5371493 2199 struct mv643xx_eth_private *mp = netdev_priv(dev);
45c5d3bc 2200 return smi_reg_read(mp, addr, reg);
9f8dd319
DF		 2201}
2202
fc32b0e2 2203static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
9f8dd319 2204{
e5371493 2205 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2 2206 smi_reg_write(mp, addr, reg, val);
c9df406f 2207}
9f8dd319 2208
9f8dd319 2209
c9df406f 2210/* platform glue ************************************************************/
e5371493
LB		 2211static void
2212mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2213 struct mbus_dram_target_info *dram)
c9df406f 2214{
cc9754b3 2215 void __iomem *base = msp->base;
c9df406f
LB		 2216 u32 win_enable;
2217 u32 win_protect;
2218 int i;
9f8dd319 2219
c9df406f
LB		 2220 for (i = 0; i < 6; i++) {
2221 writel(0, base + WINDOW_BASE(i));
2222 writel(0, base + WINDOW_SIZE(i));
2223 if (i < 4)
2224 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2225 }
2226
c9df406f
LB		 2227 win_enable = 0x3f;
2228 win_protect = 0;
2229
2230 for (i = 0; i < dram->num_cs; i++) {
2231 struct mbus_dram_window *cs = dram->cs + i;
2232
2233 writel((cs->base & 0xffff0000) |
2234 (cs->mbus_attr << 8) |
2235 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2236 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2237
2238 win_enable &= ~(1 << i);
2239 win_protect |= 3 << (2 * i);
2240 }
2241
2242 writel(win_enable, base + WINDOW_BAR_ENABLE);
2243 msp->win_protect = win_protect;
9f8dd319
DF		 2244}
2245
773fc3ee
LB		 2246static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2247{
2248 /*
2249 * Check whether we have a 14-bit coal limit field in bits
2250 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2251 * SDMA config register.
2252 */
2253 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2254 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2255 msp->extended_rx_coal_limit = 1;
2256 else
2257 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2258
2259 /*
2260 * Check whether the TX rate control registers are in the
2261 * old or the new place.
2262 */
2263 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2264 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2265 msp->tx_bw_control_moved = 1;
2266 else
2267 msp->tx_bw_control_moved = 0;
773fc3ee
LB		 2268}
2269
c9df406f 2270static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2271{
e5371493 2272 static int mv643xx_eth_version_printed = 0;
c9df406f 2273 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2274 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2275 struct resource *res;
2276 int ret;
9f8dd319 2277
e5371493 2278 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2279 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2280 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2281
c9df406f
LB		 2282 ret = -EINVAL;
2283 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2284 if (res == NULL)
2285 goto out;
9f8dd319 2286
c9df406f
LB		 2287 ret = -ENOMEM;
2288 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2289 if (msp == NULL)
2290 goto out;
2291 memset(msp, 0, sizeof(*msp));
2292
cc9754b3
LB		 2293 msp->base = ioremap(res->start, res->end - res->start + 1);
2294 if (msp->base == NULL)
c9df406f
LB		 2295 goto out_free;
2296
fc0eb9f2
LB		 2297 msp->smi = msp;
2298 if (pd != NULL && pd->shared_smi != NULL)
2299 msp->smi = platform_get_drvdata(pd->shared_smi);
2300
2b3ba0e3 2301 mutex_init(&msp->phy_lock);
c9df406f 2302
45c5d3bc
LB		 2303 msp->err_interrupt = NO_IRQ;
2304 init_waitqueue_head(&msp->smi_busy_wait);
2305
2306 /*
2307 * Check whether the error interrupt is hooked up.
2308 */
2309 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2310 if (res != NULL) {
2311 int err;
2312
2313 err = request_irq(res->start, mv643xx_eth_err_irq,
2314 IRQF_SHARED, "mv643xx_eth", msp);
2315 if (!err) {
2316 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2317 msp->err_interrupt = res->start;
2318 }
2319 }
2320
c9df406f
LB		 2321 /*
2322 * (Re-)program MBUS remapping windows if we are asked to.
2323 */
2324 if (pd != NULL && pd->dram != NULL)
2325 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2326
fc32b0e2
LB		 2327 /*
2328 * Detect hardware parameters.
2329 */
2330 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2331 infer_hw_params(msp);
fc32b0e2
LB		 2332
2333 platform_set_drvdata(pdev, msp);
2334
c9df406f
LB		 2335 return 0;
2336
2337out_free:
2338 kfree(msp);
2339out:
2340 return ret;
2341}
2342
2343static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2344{
e5371493 2345 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2346
45c5d3bc
LB		 2347 if (msp->err_interrupt != NO_IRQ)
2348 free_irq(msp->err_interrupt, msp);
cc9754b3 2349 iounmap(msp->base);
c9df406f
LB		 2350 kfree(msp);
2351
2352 return 0;
9f8dd319
DF		 2353}
2354
c9df406f 2355static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2356 .probe = mv643xx_eth_shared_probe,
2357 .remove = mv643xx_eth_shared_remove,
c9df406f 2358 .driver = {
fc32b0e2 2359 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2360 .owner = THIS_MODULE,
2361 },
2362};
2363
e5371493 2364static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2365{
c9df406f 2366 int addr_shift = 5 * mp->port_num;
fc32b0e2 2367 u32 data;
1da177e4 2368
fc32b0e2
LB		 2369 data = rdl(mp, PHY_ADDR);
2370 data &= ~(0x1f << addr_shift);
2371 data |= (phy_addr & 0x1f) << addr_shift;
2372 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2373}
2374
e5371493 2375static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2376{
fc32b0e2
LB		 2377 unsigned int data;
2378
2379 data = rdl(mp, PHY_ADDR);
2380
2381 return (data >> (5 * mp->port_num)) & 0x1f;
2382}
2383
2384static void set_params(struct mv643xx_eth_private *mp,
2385 struct mv643xx_eth_platform_data *pd)
2386{
2387 struct net_device *dev = mp->dev;
2388
2389 if (is_valid_ether_addr(pd->mac_addr))
2390 memcpy(dev->dev_addr, pd->mac_addr, 6);
2391 else
2392 uc_addr_get(mp, dev->dev_addr);
2393
ac840605 2394 if (pd->phy_addr == MV643XX_ETH_PHY_NONE) {
fc32b0e2
LB		 2395 mp->phy_addr = -1;
2396 } else {
ac840605 2397 if (pd->phy_addr != MV643XX_ETH_PHY_ADDR_DEFAULT) {
fc32b0e2
LB		 2398 mp->phy_addr = pd->phy_addr & 0x3f;
2399 phy_addr_set(mp, mp->phy_addr);
2400 } else {
2401 mp->phy_addr = phy_addr_get(mp);
2402 }
2403 }
1da177e4 2404
fc32b0e2
LB		 2405 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2406 if (pd->rx_queue_size)
2407 mp->default_rx_ring_size = pd->rx_queue_size;
2408 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2409 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2410
f7981c1c 2411 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2412
fc32b0e2
LB		 2413 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2414 if (pd->tx_queue_size)
2415 mp->default_tx_ring_size = pd->tx_queue_size;
2416 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2417 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2418
f7981c1c 2419 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2420}
2421
e5371493 2422static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2423{
45c5d3bc
LB		 2424 int data;
2425 int data2;
2426
2427 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2428 if (data < 0)
2429 return -ENODEV;
2430
2431 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2432 return -ENODEV;
fc32b0e2 2433
45c5d3bc
LB		 2434 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2435 if (data2 < 0)
2436 return -ENODEV;
1da177e4 2437
7f106c1d 2438 if (((data ^ data2) & BMCR_ANENABLE) == 0)
fc32b0e2 2439 return -ENODEV;
1da177e4 2440
7f106c1d 2441 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1da177e4 2442
c9df406f 2443 return 0;
1da177e4
LT		 2444}
2445
fc32b0e2
LB		 2446static int phy_init(struct mv643xx_eth_private *mp,
2447 struct mv643xx_eth_platform_data *pd)
c28a4f89 2448{
fc32b0e2
LB		 2449 struct ethtool_cmd cmd;
2450 int err;
c28a4f89 2451
fc32b0e2
LB		 2452 err = phy_detect(mp);
2453 if (err) {
2454 dev_printk(KERN_INFO, &mp->dev->dev,
2455 "no PHY detected at addr %d\n", mp->phy_addr);
2456 return err;
2457 }
2458 phy_reset(mp);
2459
2460 mp->mii.phy_id = mp->phy_addr;
2461 mp->mii.phy_id_mask = 0x3f;
2462 mp->mii.reg_num_mask = 0x1f;
2463 mp->mii.dev = mp->dev;
2464 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2465 mp->mii.mdio_write = mv643xx_eth_mdio_write;
c28a4f89 2466
fc32b0e2 2467 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
c9df406f 2468
fc32b0e2
LB		 2469 memset(&cmd, 0, sizeof(cmd));
2470
2471 cmd.port = PORT_MII;
2472 cmd.transceiver = XCVR_INTERNAL;
2473 cmd.phy_address = mp->phy_addr;
2474 if (pd->speed == 0) {
2475 cmd.autoneg = AUTONEG_ENABLE;
2476 cmd.speed = SPEED_100;
2477 cmd.advertising = ADVERTISED_10baseT_Half |
2478 ADVERTISED_10baseT_Full |
2479 ADVERTISED_100baseT_Half |
2480 ADVERTISED_100baseT_Full;
c9df406f 2481 if (mp->mii.supports_gmii)
fc32b0e2 2482 cmd.advertising |= ADVERTISED_1000baseT_Full;
c9df406f 2483 } else {
fc32b0e2
LB		 2484 cmd.autoneg = AUTONEG_DISABLE;
2485 cmd.speed = pd->speed;
2486 cmd.duplex = pd->duplex;
c9df406f 2487 }
fc32b0e2 2488
fc32b0e2
LB		 2489 mv643xx_eth_set_settings(mp->dev, &cmd);
2490
2491 return 0;
c28a4f89
JC		 2492}
2493
81600eea
LB		 2494static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2495{
2496 u32 pscr;
2497
2498 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2499 if (pscr & SERIAL_PORT_ENABLE) {
2500 pscr &= ~SERIAL_PORT_ENABLE;
2501 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2502 }
2503
2504 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2505 if (mp->phy_addr == -1) {
2506 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2507 if (speed == SPEED_1000)
2508 pscr |= SET_GMII_SPEED_TO_1000;
2509 else if (speed == SPEED_100)
2510 pscr |= SET_MII_SPEED_TO_100;
2511
2512 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2513
2514 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2515 if (duplex == DUPLEX_FULL)
2516 pscr |= SET_FULL_DUPLEX_MODE;
2517 }
2518
2519 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2520}
2521
c9df406f 2522static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2523{
c9df406f 2524 struct mv643xx_eth_platform_data *pd;
e5371493 2525 struct mv643xx_eth_private *mp;
c9df406f 2526 struct net_device *dev;
c9df406f 2527 struct resource *res;
c9df406f 2528 DECLARE_MAC_BUF(mac);
fc32b0e2 2529 int err;
1da177e4 2530
c9df406f
LB		 2531 pd = pdev->dev.platform_data;
2532 if (pd == NULL) {
fc32b0e2
LB		 2533 dev_printk(KERN_ERR, &pdev->dev,
2534 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2535 return -ENODEV;
2536 }
1da177e4 2537
c9df406f 2538 if (pd->shared == NULL) {
fc32b0e2
LB		 2539 dev_printk(KERN_ERR, &pdev->dev,
2540 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2541 return -ENODEV;
2542 }
8f518703 2543
e5ef1de1 2544 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2545 if (!dev)
2546 return -ENOMEM;
1da177e4 2547
c9df406f 2548 mp = netdev_priv(dev);
fc32b0e2
LB		 2549 platform_set_drvdata(pdev, mp);
2550
2551 mp->shared = platform_get_drvdata(pd->shared);
2552 mp->port_num = pd->port_number;
2553
c9df406f 2554 mp->dev = dev;
78fff83b 2555
fc32b0e2 2556 set_params(mp, pd);
e5ef1de1 2557 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2
LB		 2558
2559 spin_lock_init(&mp->lock);
2560
2561 mib_counters_clear(mp);
2562 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2563
bedfe324
LB		 2564 if (mp->phy_addr != -1) {
2565 err = phy_init(mp, pd);
2566 if (err)
2567 goto out;
2568
2569 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2570 } else {
2571 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2572 }
81600eea 2573 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2574
2257e05c
LB		 2575 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2576
2577 init_timer(&mp->rx_oom);
2578 mp->rx_oom.data = (unsigned long)mp;
2579 mp->rx_oom.function = oom_timer_wrapper;
2580
fc32b0e2 2581
c9df406f
LB		 2582 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2583 BUG_ON(!res);
2584 dev->irq = res->start;
1da177e4 2585
fc32b0e2 2586 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2587 dev->open = mv643xx_eth_open;
2588 dev->stop = mv643xx_eth_stop;
c9df406f 2589 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2590 dev->set_mac_address = mv643xx_eth_set_mac_address;
2591 dev->do_ioctl = mv643xx_eth_ioctl;
2592 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2593 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2594#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2595 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2596#endif
c9df406f
LB		 2597 dev->watchdog_timeo = 2 * HZ;
2598 dev->base_addr = 0;
1da177e4 2599
c9df406f 2600 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2601 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2602
fc32b0e2 2603 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2604
c9df406f 2605 if (mp->shared->win_protect)
fc32b0e2 2606 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2607
c9df406f
LB		 2608 err = register_netdev(dev);
2609 if (err)
2610 goto out;
1da177e4 2611
fc32b0e2
LB		 2612 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2613 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2614
13d64285 2615 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2616 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2617
c9df406f 2618 return 0;
1da177e4 2619
c9df406f
LB		 2620out:
2621 free_netdev(dev);
1da177e4 2622
c9df406f 2623 return err;
1da177e4
LT		 2624}
2625
c9df406f 2626static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2627{
fc32b0e2 2628 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2629
fc32b0e2 2630 unregister_netdev(mp->dev);
c9df406f 2631 flush_scheduled_work();
fc32b0e2 2632 free_netdev(mp->dev);
c9df406f 2633
c9df406f 2634 platform_set_drvdata(pdev, NULL);
fc32b0e2 2635
c9df406f 2636 return 0;
1da177e4
LT		 2637}
2638
c9df406f 2639static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2640{
fc32b0e2 2641 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2642
c9df406f 2643 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2644 wrl(mp, INT_MASK(mp->port_num), 0);
2645 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2646
fc32b0e2
LB		 2647 if (netif_running(mp->dev))
2648 port_reset(mp);
d0412d96
JC		 2649}
2650
c9df406f 2651static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2652 .probe = mv643xx_eth_probe,
2653 .remove = mv643xx_eth_remove,
2654 .shutdown = mv643xx_eth_shutdown,
c9df406f 2655 .driver = {
fc32b0e2 2656 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2657 .owner = THIS_MODULE,
2658 },
2659};
2660
e5371493 2661static int __init mv643xx_eth_init_module(void)
d0412d96 2662{
c9df406f 2663 int rc;
d0412d96 2664
c9df406f
LB		 2665 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2666 if (!rc) {
2667 rc = platform_driver_register(&mv643xx_eth_driver);
2668 if (rc)
2669 platform_driver_unregister(&mv643xx_eth_shared_driver);
2670 }
fc32b0e2 2671
c9df406f 2672 return rc;
d0412d96 2673}
fc32b0e2 2674module_init(mv643xx_eth_init_module);
d0412d96 2675
e5371493 2676static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2677{
c9df406f
LB		 2678 platform_driver_unregister(&mv643xx_eth_driver);
2679 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2680}
e5371493 2681module_exit(mv643xx_eth_cleanup_module);
1da177e4 2682
45675bc6
LB		 2683MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2684 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2685MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2686MODULE_LICENSE("GPL");
c9df406f 2687MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2688MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
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