]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/mv643xx_eth.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] mv643xx_eth: use MII library for PHY management
[net-next-2.6.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 9 * written by Manish Lachwani
1da177e4
LT		 10 *
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
12 *
13 * Copyright (C) 2004-2005 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
15 *
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33#include <linux/init.h>
34#include <linux/dma-mapping.h>
35#include <linux/tcp.h>
36#include <linux/udp.h>
37#include <linux/etherdevice.h>
78a5e534
OH		 38#include <linux/in.h>
39#include <linux/ip.h>
1da177e4
LT		 40
41#include <linux/bitops.h>
42#include <linux/delay.h>
43#include <linux/ethtool.h>
d052d1be
RK		 44#include <linux/platform_device.h>
45
1da177e4
LT		 46#include <asm/io.h>
47#include <asm/types.h>
48#include <asm/pgtable.h>
49#include <asm/system.h>
50#include <asm/delay.h>
51#include "mv643xx_eth.h"
52
53/*
54 * The first part is the high level driver of the gigE ethernet ports.
55 */
56
57/* Constants */
58#define VLAN_HLEN 4
59#define FCS_LEN 4
b44cd572
DF		 60#define DMA_ALIGN 8 /* hw requires 8-byte alignment */
61#define HW_IP_ALIGN 2 /* hw aligns IP header */
62#define WRAP HW_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
1da177e4
LT		 63#define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
64
c2e5b352
DF		 65#define INT_UNMASK_ALL 0x0007ffff
66#define INT_UNMASK_ALL_EXT 0x0011ffff
67#define INT_MASK_ALL 0x00000000
68#define INT_MASK_ALL_EXT 0x00000000
1da177e4
LT		 69#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
70#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
1da177e4
LT		 71
72#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
73#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
74#else
75#define MAX_DESCS_PER_SKB 1
76#endif
77
78#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
79#define PHY_WAIT_MICRO_SECONDS 10
80
81/* Static function declarations */
1da177e4
LT		 82static void eth_port_uc_addr_get(struct net_device *dev,
83 unsigned char *MacAddr);
16e03018 84static void eth_port_set_multicast_list(struct net_device *);
9f8dd319
DF		 85static void mv643xx_eth_port_enable_tx(unsigned int port_num,
86 unsigned int channels);
87static void mv643xx_eth_port_enable_rx(unsigned int port_num,
88 unsigned int channels);
89static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num);
90static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num);
ab4384a6
DF		 91static int mv643xx_eth_open(struct net_device *);
92static int mv643xx_eth_stop(struct net_device *);
1da177e4
LT		 93static int mv643xx_eth_change_mtu(struct net_device *, int);
94static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
95static void eth_port_init_mac_tables(unsigned int eth_port_num);
96#ifdef MV643XX_NAPI
97static int mv643xx_poll(struct net_device *dev, int *budget);
98#endif
c28a4f89 99static int ethernet_phy_get(unsigned int eth_port_num);
1da177e4
LT		 100static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
101static int ethernet_phy_detect(unsigned int eth_port_num);
c28a4f89
JC		 102static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
103static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
1da177e4
LT		 104static struct ethtool_ops mv643xx_ethtool_ops;
105
106static char mv643xx_driver_name[] = "mv643xx_eth";
107static char mv643xx_driver_version[] = "1.0";
108
109static void __iomem *mv643xx_eth_shared_base;
110
111/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
a9f6a0dd 112static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
1da177e4
LT		 113
114static inline u32 mv_read(int offset)
115{
dc074a8a 116 void __iomem *reg_base;
1da177e4
LT		 117
118 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
119
120 return readl(reg_base + offset);
121}
122
123static inline void mv_write(int offset, u32 data)
124{
dc074a8a 125 void __iomem *reg_base;
1da177e4
LT		 126
127 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
128 writel(data, reg_base + offset);
129}
130
131/*
132 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
133 *
134 * Input : pointer to ethernet interface network device structure
135 * new mtu size
136 * Output : 0 upon success, -EINVAL upon failure
137 */
138static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
139{
8f518703 140 if ((new_mtu > 9500) || (new_mtu < 64))
1da177e4 141 return -EINVAL;
1da177e4
LT		 142
143 dev->mtu = new_mtu;
144 /*
145 * Stop then re-open the interface. This will allocate RX skb's with
146 * the new MTU.
147 * There is a possible danger that the open will not successed, due
148 * to memory is full, which might fail the open function.
149 */
150 if (netif_running(dev)) {
ab4384a6
DF		 151 mv643xx_eth_stop(dev);
152 if (mv643xx_eth_open(dev))
1da177e4
LT		 153 printk(KERN_ERR
154 "%s: Fatal error on opening device\n",
155 dev->name);
156 }
157
1da177e4
LT		 158 return 0;
159}
160
161/*
162 * mv643xx_eth_rx_task
163 *
164 * Fills / refills RX queue on a certain gigabit ethernet port
165 *
166 * Input : pointer to ethernet interface network device structure
167 * Output : N/A
168 */
169static void mv643xx_eth_rx_task(void *data)
170{
171 struct net_device *dev = (struct net_device *)data;
172 struct mv643xx_private *mp = netdev_priv(dev);
173 struct pkt_info pkt_info;
174 struct sk_buff *skb;
b44cd572 175 int unaligned;
1da177e4
LT		 176
177 if (test_and_set_bit(0, &mp->rx_task_busy))
178 panic("%s: Error in test_set_bit / clear_bit", dev->name);
179
f98e36f1 180 while (mp->rx_desc_count < (mp->rx_ring_size - 5)) {
b44cd572 181 skb = dev_alloc_skb(RX_SKB_SIZE + DMA_ALIGN);
1da177e4
LT		 182 if (!skb)
183 break;
f98e36f1 184 mp->rx_desc_count++;
b44cd572
DF		 185 unaligned = (u32)skb->data & (DMA_ALIGN - 1);
186 if (unaligned)
187 skb_reserve(skb, DMA_ALIGN - unaligned);
1da177e4
LT		 188 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
189 pkt_info.byte_cnt = RX_SKB_SIZE;
190 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
191 DMA_FROM_DEVICE);
192 pkt_info.return_info = skb;
193 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
194 printk(KERN_ERR
195 "%s: Error allocating RX Ring\n", dev->name);
196 break;
197 }
b44cd572 198 skb_reserve(skb, HW_IP_ALIGN);
1da177e4
LT		 199 }
200 clear_bit(0, &mp->rx_task_busy);
201 /*
202 * If RX ring is empty of SKB, set a timer to try allocating
203 * again in a later time .
204 */
f98e36f1 205 if ((mp->rx_desc_count == 0) && (mp->rx_timer_flag == 0)) {
1da177e4
LT		 206 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
207 /* After 100mSec */
208 mp->timeout.expires = jiffies + (HZ / 10);
209 add_timer(&mp->timeout);
210 mp->rx_timer_flag = 1;
211 }
212#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
213 else {
214 /* Return interrupts */
215 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
c2e5b352 216 INT_UNMASK_ALL);
1da177e4
LT		 217 }
218#endif
219}
220
221/*
222 * mv643xx_eth_rx_task_timer_wrapper
223 *
224 * Timer routine to wake up RX queue filling task. This function is
225 * used only in case the RX queue is empty, and all alloc_skb has
226 * failed (due to out of memory event).
227 *
228 * Input : pointer to ethernet interface network device structure
229 * Output : N/A
230 */
231static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
232{
233 struct net_device *dev = (struct net_device *)data;
234 struct mv643xx_private *mp = netdev_priv(dev);
235
236 mp->rx_timer_flag = 0;
237 mv643xx_eth_rx_task((void *)data);
238}
239
240/*
241 * mv643xx_eth_update_mac_address
242 *
243 * Update the MAC address of the port in the address table
244 *
245 * Input : pointer to ethernet interface network device structure
246 * Output : N/A
247 */
248static void mv643xx_eth_update_mac_address(struct net_device *dev)
249{
250 struct mv643xx_private *mp = netdev_priv(dev);
251 unsigned int port_num = mp->port_num;
252
253 eth_port_init_mac_tables(port_num);
ed9b5d45 254 eth_port_uc_addr_set(port_num, dev->dev_addr);
1da177e4
LT		 255}
256
257/*
258 * mv643xx_eth_set_rx_mode
259 *
260 * Change from promiscuos to regular rx mode
261 *
262 * Input : pointer to ethernet interface network device structure
263 * Output : N/A
264 */
265static void mv643xx_eth_set_rx_mode(struct net_device *dev)
266{
267 struct mv643xx_private *mp = netdev_priv(dev);
1da177e4 268
1da177e4 269 if (dev->flags & IFF_PROMISC)
7342cd81 270 mp->port_config |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
1da177e4 271 else
7342cd81
DF		 272 mp->port_config &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
273
274 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), mp->port_config);
16e03018
DF		 275
276 eth_port_set_multicast_list(dev);
1da177e4
LT		 277}
278
279/*
280 * mv643xx_eth_set_mac_address
281 *
282 * Change the interface's mac address.
283 * No special hardware thing should be done because interface is always
284 * put in promiscuous mode.
285 *
286 * Input : pointer to ethernet interface network device structure and
287 * a pointer to the designated entry to be added to the cache.
288 * Output : zero upon success, negative upon failure
289 */
290static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
291{
292 int i;
293
294 for (i = 0; i < 6; i++)
295 /* +2 is for the offset of the HW addr type */
296 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
297 mv643xx_eth_update_mac_address(dev);
298 return 0;
299}
300
301/*
302 * mv643xx_eth_tx_timeout
303 *
304 * Called upon a timeout on transmitting a packet
305 *
306 * Input : pointer to ethernet interface network device structure.
307 * Output : N/A
308 */
309static void mv643xx_eth_tx_timeout(struct net_device *dev)
310{
311 struct mv643xx_private *mp = netdev_priv(dev);
312
313 printk(KERN_INFO "%s: TX timeout ", dev->name);
314
315 /* Do the reset outside of interrupt context */
316 schedule_work(&mp->tx_timeout_task);
317}
318
319/*
320 * mv643xx_eth_tx_timeout_task
321 *
322 * Actual routine to reset the adapter when a timeout on Tx has occurred
323 */
324static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
325{
326 struct mv643xx_private *mp = netdev_priv(dev);
327
328 netif_device_detach(dev);
329 eth_port_reset(mp->port_num);
ed9b5d45 330 eth_port_start(dev);
1da177e4
LT		 331 netif_device_attach(dev);
332}
333
334/*
335 * mv643xx_eth_free_tx_queue
336 *
337 * Input : dev - a pointer to the required interface
338 *
339 * Output : 0 if was able to release skb , nonzero otherwise
340 */
341static int mv643xx_eth_free_tx_queue(struct net_device *dev,
342 unsigned int eth_int_cause_ext)
343{
344 struct mv643xx_private *mp = netdev_priv(dev);
345 struct net_device_stats *stats = &mp->stats;
346 struct pkt_info pkt_info;
347 int released = 1;
348
349 if (!(eth_int_cause_ext & (BIT0 | BIT8)))
350 return released;
351
1da177e4
LT		 352 /* Check only queue 0 */
353 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
354 if (pkt_info.cmd_sts & BIT0) {
355 printk("%s: Error in TX\n", dev->name);
356 stats->tx_errors++;
357 }
358
cb415d30
PG		 359 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
360 dma_unmap_single(NULL, pkt_info.buf_ptr,
361 pkt_info.byte_cnt,
362 DMA_TO_DEVICE);
363 else
364 dma_unmap_page(NULL, pkt_info.buf_ptr,
365 pkt_info.byte_cnt,
366 DMA_TO_DEVICE);
1da177e4 367
cb415d30 368 if (pkt_info.return_info) {
1da177e4
LT		 369 dev_kfree_skb_irq(pkt_info.return_info);
370 released = 0;
cb415d30 371 }
1da177e4
LT		 372 }
373
1da177e4
LT		 374 return released;
375}
376
377/*
378 * mv643xx_eth_receive
379 *
380 * This function is forward packets that are received from the port's
381 * queues toward kernel core or FastRoute them to another interface.
382 *
383 * Input : dev - a pointer to the required interface
384 * max - maximum number to receive (0 means unlimted)
385 *
386 * Output : number of served packets
387 */
388#ifdef MV643XX_NAPI
389static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
390#else
391static int mv643xx_eth_receive_queue(struct net_device *dev)
392#endif
393{
394 struct mv643xx_private *mp = netdev_priv(dev);
395 struct net_device_stats *stats = &mp->stats;
396 unsigned int received_packets = 0;
397 struct sk_buff *skb;
398 struct pkt_info pkt_info;
399
400#ifdef MV643XX_NAPI
b1dd9ca1 401 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
1da177e4
LT		 402#else
403 while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
404#endif
f98e36f1 405 mp->rx_desc_count--;
1da177e4 406 received_packets++;
b1dd9ca1 407
1da177e4
LT		 408 /* Update statistics. Note byte count includes 4 byte CRC count */
409 stats->rx_packets++;
410 stats->rx_bytes += pkt_info.byte_cnt;
411 skb = pkt_info.return_info;
412 /*
413 * In case received a packet without first / last bits on OR
414 * the error summary bit is on, the packets needs to be dropeed.
415 */
416 if (((pkt_info.cmd_sts
417 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
418 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
419 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
420 stats->rx_dropped++;
421 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
422 ETH_RX_LAST_DESC)) !=
423 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
424 if (net_ratelimit())
425 printk(KERN_ERR
426 "%s: Received packet spread "
427 "on multiple descriptors\n",
428 dev->name);
429 }
430 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
431 stats->rx_errors++;
432
433 dev_kfree_skb_irq(skb);
434 } else {
435 /*
436 * The -4 is for the CRC in the trailer of the
437 * received packet
438 */
439 skb_put(skb, pkt_info.byte_cnt - 4);
440 skb->dev = dev;
441
442 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
443 skb->ip_summed = CHECKSUM_UNNECESSARY;
444 skb->csum = htons(
445 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
446 }
447 skb->protocol = eth_type_trans(skb, dev);
448#ifdef MV643XX_NAPI
449 netif_receive_skb(skb);
450#else
451 netif_rx(skb);
452#endif
453 }
12ad74f8 454 dev->last_rx = jiffies;
1da177e4
LT		 455 }
456
457 return received_packets;
458}
459
460/*
461 * mv643xx_eth_int_handler
462 *
463 * Main interrupt handler for the gigbit ethernet ports
464 *
465 * Input : irq - irq number (not used)
466 * dev_id - a pointer to the required interface's data structure
467 * regs - not used
468 * Output : N/A
469 */
470
471static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
b4de9051 472 struct pt_regs *regs)
1da177e4
LT		 473{
474 struct net_device *dev = (struct net_device *)dev_id;
475 struct mv643xx_private *mp = netdev_priv(dev);
476 u32 eth_int_cause, eth_int_cause_ext = 0;
477 unsigned int port_num = mp->port_num;
478
479 /* Read interrupt cause registers */
480 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
c2e5b352 481 INT_UNMASK_ALL;
1da177e4
LT		 482
483 if (eth_int_cause & BIT1)
484 eth_int_cause_ext = mv_read(
485 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
c2e5b352 486 INT_UNMASK_ALL_EXT;
1da177e4
LT		 487
488#ifdef MV643XX_NAPI
489 if (!(eth_int_cause & 0x0007fffd)) {
490 /* Dont ack the Rx interrupt */
491#endif
492 /*
493 * Clear specific ethernet port intrerrupt registers by
494 * acknowleding relevant bits.
495 */
496 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
497 ~eth_int_cause);
498 if (eth_int_cause_ext != 0x0)
499 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
500 (port_num), ~eth_int_cause_ext);
501
502 /* UDP change : We may need this */
503 if ((eth_int_cause_ext & 0x0000ffff) &&
504 (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
f98e36f1 505 (mp->tx_ring_size > mp->tx_desc_count + MAX_DESCS_PER_SKB))
1da177e4
LT		 506 netif_wake_queue(dev);
507#ifdef MV643XX_NAPI
508 } else {
509 if (netif_rx_schedule_prep(dev)) {
510 /* Mask all the interrupts */
c2e5b352
DF		 511 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
512 INT_MASK_ALL);
513 /* wait for previous write to complete */
514 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
1da177e4
LT		 515 __netif_rx_schedule(dev);
516 }
517#else
518 if (eth_int_cause & (BIT2 | BIT11))
519 mv643xx_eth_receive_queue(dev, 0);
520
521 /*
522 * After forwarded received packets to upper layer, add a task
523 * in an interrupts enabled context that refills the RX ring
524 * with skb's.
525 */
526#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
c2e5b352 527 /* Mask all interrupts on ethernet port */
1da177e4 528 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
c2e5b352 529 INT_MASK_ALL);
8f518703
DF		 530 /* wait for previous write to take effect */
531 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
532
1da177e4
LT		 533 queue_task(&mp->rx_task, &tq_immediate);
534 mark_bh(IMMEDIATE_BH);
535#else
536 mp->rx_task.func(dev);
537#endif
538#endif
539 }
540 /* PHY status changed */
541 if (eth_int_cause_ext & (BIT16 | BIT20)) {
c28a4f89
JC		 542 if (mii_link_ok(&mp->mii)) {
543 if (!netif_carrier_ok(dev)) {
544 netif_carrier_on(dev);
545 netif_wake_queue(dev);
546 /* Start TX queue */
547 mv643xx_eth_port_enable_tx(port_num,
548 mp->port_tx_queue_command);
549 }
550 } else if (netif_carrier_ok(dev)) {
1da177e4 551 netif_stop_queue(dev);
c28a4f89 552 netif_carrier_off(dev);
1da177e4
LT		 553 }
554 }
555
556 /*
557 * If no real interrupt occured, exit.
558 * This can happen when using gigE interrupt coalescing mechanism.
559 */
560 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
561 return IRQ_NONE;
562
563 return IRQ_HANDLED;
564}
565
566#ifdef MV643XX_COAL
567
568/*
569 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
570 *
571 * DESCRIPTION:
572 * This routine sets the RX coalescing interrupt mechanism parameter.
573 * This parameter is a timeout counter, that counts in 64 t_clk
574 * chunks ; that when timeout event occurs a maskable interrupt
575 * occurs.
576 * The parameter is calculated using the tClk of the MV-643xx chip
577 * , and the required delay of the interrupt in usec.
578 *
579 * INPUT:
580 * unsigned int eth_port_num Ethernet port number
581 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
582 * unsigned int delay Delay in usec
583 *
584 * OUTPUT:
585 * Interrupt coalescing mechanism value is set in MV-643xx chip.
586 *
587 * RETURN:
588 * The interrupt coalescing value set in the gigE port.
589 *
590 */
591static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
592 unsigned int t_clk, unsigned int delay)
593{
594 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
595
596 /* Set RX Coalescing mechanism */
597 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
598 ((coal & 0x3fff) << 8) |
599 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
600 & 0xffc000ff));
601
602 return coal;
603}
604#endif
605
606/*
607 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
608 *
609 * DESCRIPTION:
610 * This routine sets the TX coalescing interrupt mechanism parameter.
611 * This parameter is a timeout counter, that counts in 64 t_clk
612 * chunks ; that when timeout event occurs a maskable interrupt
613 * occurs.
614 * The parameter is calculated using the t_cLK frequency of the
615 * MV-643xx chip and the required delay in the interrupt in uSec
616 *
617 * INPUT:
618 * unsigned int eth_port_num Ethernet port number
619 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
620 * unsigned int delay Delay in uSeconds
621 *
622 * OUTPUT:
623 * Interrupt coalescing mechanism value is set in MV-643xx chip.
624 *
625 * RETURN:
626 * The interrupt coalescing value set in the gigE port.
627 *
628 */
629static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
630 unsigned int t_clk, unsigned int delay)
631{
632 unsigned int coal;
633 coal = ((t_clk / 1000000) * delay) / 64;
634 /* Set TX Coalescing mechanism */
635 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
636 coal << 4);
637 return coal;
638}
639
1da177e4
LT		 640/*
641 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
642 *
643 * DESCRIPTION:
644 * This function prepares a Rx chained list of descriptors and packet
645 * buffers in a form of a ring. The routine must be called after port
646 * initialization routine and before port start routine.
647 * The Ethernet SDMA engine uses CPU bus addresses to access the various
648 * devices in the system (i.e. DRAM). This function uses the ethernet
649 * struct 'virtual to physical' routine (set by the user) to set the ring
650 * with physical addresses.
651 *
652 * INPUT:
653 * struct mv643xx_private *mp Ethernet Port Control srtuct.
654 *
655 * OUTPUT:
656 * The routine updates the Ethernet port control struct with information
657 * regarding the Rx descriptors and buffers.
658 *
659 * RETURN:
660 * None.
661 */
662static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
663{
664 volatile struct eth_rx_desc *p_rx_desc;
665 int rx_desc_num = mp->rx_ring_size;
666 int i;
667
668 /* initialize the next_desc_ptr links in the Rx descriptors ring */
669 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
670 for (i = 0; i < rx_desc_num; i++) {
671 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
672 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
673 }
674
675 /* Save Rx desc pointer to driver struct. */
676 mp->rx_curr_desc_q = 0;
677 mp->rx_used_desc_q = 0;
678
679 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
680
9f8dd319
DF		 681 /* Enable queue 0 for this port */
682 mp->port_rx_queue_command = 1;
1da177e4
LT		 683}
684
685/*
686 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
687 *
688 * DESCRIPTION:
689 * This function prepares a Tx chained list of descriptors and packet
690 * buffers in a form of a ring. The routine must be called after port
691 * initialization routine and before port start routine.
692 * The Ethernet SDMA engine uses CPU bus addresses to access the various
693 * devices in the system (i.e. DRAM). This function uses the ethernet
694 * struct 'virtual to physical' routine (set by the user) to set the ring
695 * with physical addresses.
696 *
697 * INPUT:
698 * struct mv643xx_private *mp Ethernet Port Control srtuct.
699 *
700 * OUTPUT:
701 * The routine updates the Ethernet port control struct with information
702 * regarding the Tx descriptors and buffers.
703 *
704 * RETURN:
705 * None.
706 */
707static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
708{
709 int tx_desc_num = mp->tx_ring_size;
710 struct eth_tx_desc *p_tx_desc;
711 int i;
712
713 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
714 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
715 for (i = 0; i < tx_desc_num; i++) {
716 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
717 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
718 }
719
720 mp->tx_curr_desc_q = 0;
721 mp->tx_used_desc_q = 0;
722#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
723 mp->tx_first_desc_q = 0;
724#endif
725
726 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
727
9f8dd319
DF		 728 /* Enable queue 0 for this port */
729 mp->port_tx_queue_command = 1;
1da177e4
LT		 730}
731
ab4384a6
DF		 732/*
733 * mv643xx_eth_open
734 *
735 * This function is called when openning the network device. The function
736 * should initialize all the hardware, initialize cyclic Rx/Tx
737 * descriptors chain and buffers and allocate an IRQ to the network
738 * device.
739 *
740 * Input : a pointer to the network device structure
741 *
742 * Output : zero of success , nonzero if fails.
743 */
744
745static int mv643xx_eth_open(struct net_device *dev)
1da177e4
LT		 746{
747 struct mv643xx_private *mp = netdev_priv(dev);
748 unsigned int port_num = mp->port_num;
749 unsigned int size;
ab4384a6
DF		 750 int err;
751
752 err = request_irq(dev->irq, mv643xx_eth_int_handler,
753 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
754 if (err) {
755 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
756 port_num);
757 return -EAGAIN;
758 }
1da177e4 759
1da177e4
LT		 760 eth_port_init(mp);
761
762 INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);
763
764 memset(&mp->timeout, 0, sizeof(struct timer_list));
765 mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
766 mp->timeout.data = (unsigned long)dev;
767
768 mp->rx_task_busy = 0;
769 mp->rx_timer_flag = 0;
770
771 /* Allocate RX and TX skb rings */
772 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
773 GFP_KERNEL);
774 if (!mp->rx_skb) {
775 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
ab4384a6
DF		 776 err = -ENOMEM;
777 goto out_free_irq;
1da177e4
LT		 778 }
779 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
780 GFP_KERNEL);
781 if (!mp->tx_skb) {
782 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
ab4384a6
DF		 783 err = -ENOMEM;
784 goto out_free_rx_skb;
1da177e4
LT		 785 }
786
787 /* Allocate TX ring */
f98e36f1 788 mp->tx_desc_count = 0;
1da177e4
LT		 789 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
790 mp->tx_desc_area_size = size;
791
792 if (mp->tx_sram_size) {
793 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
794 mp->tx_sram_size);
795 mp->tx_desc_dma = mp->tx_sram_addr;
796 } else
797 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
798 &mp->tx_desc_dma,
799 GFP_KERNEL);
800
801 if (!mp->p_tx_desc_area) {
802 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
803 dev->name, size);
ab4384a6
DF		 804 err = -ENOMEM;
805 goto out_free_tx_skb;
1da177e4
LT		 806 }
807 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
808 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
809
810 ether_init_tx_desc_ring(mp);
811
812 /* Allocate RX ring */
f98e36f1 813 mp->rx_desc_count = 0;
1da177e4
LT		 814 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
815 mp->rx_desc_area_size = size;
816
817 if (mp->rx_sram_size) {
818 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
819 mp->rx_sram_size);
820 mp->rx_desc_dma = mp->rx_sram_addr;
821 } else
822 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
823 &mp->rx_desc_dma,
824 GFP_KERNEL);
825
826 if (!mp->p_rx_desc_area) {
827 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
828 dev->name, size);
829 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
830 dev->name);
831 if (mp->rx_sram_size)
dd09b1de 832 iounmap(mp->p_tx_desc_area);
1da177e4
LT		 833 else
834 dma_free_coherent(NULL, mp->tx_desc_area_size,
835 mp->p_tx_desc_area, mp->tx_desc_dma);
ab4384a6
DF		 836 err = -ENOMEM;
837 goto out_free_tx_skb;
1da177e4
LT		 838 }
839 memset((void *)mp->p_rx_desc_area, 0, size);
840
841 ether_init_rx_desc_ring(mp);
842
843 mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */
844
ed9b5d45 845 eth_port_start(dev);
1da177e4
LT		 846
847 /* Interrupt Coalescing */
848
849#ifdef MV643XX_COAL
850 mp->rx_int_coal =
851 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
852#endif
853
854 mp->tx_int_coal =
855 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
856
8f518703
DF		 857 /* Clear any pending ethernet port interrupts */
858 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
859 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
860
861 /* Unmask phy and link status changes interrupts */
862 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
c2e5b352 863 INT_UNMASK_ALL_EXT);
1da177e4 864
8f518703 865 /* Unmask RX buffer and TX end interrupt */
c2e5b352 866 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL);
1da177e4 867 return 0;
ab4384a6
DF		 868
869out_free_tx_skb:
870 kfree(mp->tx_skb);
871out_free_rx_skb:
872 kfree(mp->rx_skb);
873out_free_irq:
874 free_irq(dev->irq, dev);
875
876 return err;
1da177e4
LT		 877}
878
879static void mv643xx_eth_free_tx_rings(struct net_device *dev)
880{
881 struct mv643xx_private *mp = netdev_priv(dev);
882 unsigned int port_num = mp->port_num;
883 unsigned int curr;
4476e0e4 884 struct sk_buff *skb;
1da177e4
LT		 885
886 /* Stop Tx Queues */
9f8dd319 887 mv643xx_eth_port_disable_tx(port_num);
1da177e4
LT		 888
889 /* Free outstanding skb's on TX rings */
f98e36f1 890 for (curr = 0; mp->tx_desc_count && curr < mp->tx_ring_size; curr++) {
4476e0e4
DF		 891 skb = mp->tx_skb[curr];
892 if (skb) {
f98e36f1 893 mp->tx_desc_count -= skb_shinfo(skb)->nr_frags;
4476e0e4 894 dev_kfree_skb(skb);
f98e36f1 895 mp->tx_desc_count--;
1da177e4
LT		 896 }
897 }
f98e36f1 898 if (mp->tx_desc_count)
1da177e4 899 printk("%s: Error on Tx descriptor free - could not free %d"
f98e36f1 900 " descriptors\n", dev->name, mp->tx_desc_count);
1da177e4
LT		 901
902 /* Free TX ring */
903 if (mp->tx_sram_size)
904 iounmap(mp->p_tx_desc_area);
905 else
906 dma_free_coherent(NULL, mp->tx_desc_area_size,
907 mp->p_tx_desc_area, mp->tx_desc_dma);
908}
909
910static void mv643xx_eth_free_rx_rings(struct net_device *dev)
911{
912 struct mv643xx_private *mp = netdev_priv(dev);
913 unsigned int port_num = mp->port_num;
914 int curr;
915
916 /* Stop RX Queues */
9f8dd319 917 mv643xx_eth_port_disable_rx(port_num);
1da177e4
LT		 918
919 /* Free preallocated skb's on RX rings */
f98e36f1 920 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1da177e4
LT		 921 if (mp->rx_skb[curr]) {
922 dev_kfree_skb(mp->rx_skb[curr]);
f98e36f1 923 mp->rx_desc_count--;
1da177e4
LT		 924 }
925 }
926
f98e36f1 927 if (mp->rx_desc_count)
1da177e4
LT		 928 printk(KERN_ERR
929 "%s: Error in freeing Rx Ring. %d skb's still"
930 " stuck in RX Ring - ignoring them\n", dev->name,
f98e36f1 931 mp->rx_desc_count);
1da177e4
LT		 932 /* Free RX ring */
933 if (mp->rx_sram_size)
934 iounmap(mp->p_rx_desc_area);
935 else
936 dma_free_coherent(NULL, mp->rx_desc_area_size,
937 mp->p_rx_desc_area, mp->rx_desc_dma);
938}
939
940/*
941 * mv643xx_eth_stop
942 *
943 * This function is used when closing the network device.
944 * It updates the hardware,
945 * release all memory that holds buffers and descriptors and release the IRQ.
946 * Input : a pointer to the device structure
947 * Output : zero if success , nonzero if fails
948 */
949
ab4384a6 950static int mv643xx_eth_stop(struct net_device *dev)
1da177e4
LT		 951{
952 struct mv643xx_private *mp = netdev_priv(dev);
953 unsigned int port_num = mp->port_num;
954
c2e5b352
DF		 955 /* Mask all interrupts on ethernet port */
956 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL);
957 /* wait for previous write to complete */
8f518703
DF		 958 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
959
960#ifdef MV643XX_NAPI
961 netif_poll_disable(dev);
962#endif
1da177e4
LT		 963 netif_carrier_off(dev);
964 netif_stop_queue(dev);
965
1da177e4
LT		 966 eth_port_reset(mp->port_num);
967
8f518703
DF		 968 mv643xx_eth_free_tx_rings(dev);
969 mv643xx_eth_free_rx_rings(dev);
1da177e4 970
8f518703
DF		 971#ifdef MV643XX_NAPI
972 netif_poll_enable(dev);
973#endif
1da177e4 974
1da177e4 975 free_irq(dev->irq, dev);
1da177e4
LT		 976
977 return 0;
978}
979
980#ifdef MV643XX_NAPI
981static void mv643xx_tx(struct net_device *dev)
982{
983 struct mv643xx_private *mp = netdev_priv(dev);
984 struct pkt_info pkt_info;
985
986 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
cb415d30
PG		 987 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
988 dma_unmap_single(NULL, pkt_info.buf_ptr,
989 pkt_info.byte_cnt,
990 DMA_TO_DEVICE);
991 else
992 dma_unmap_page(NULL, pkt_info.buf_ptr,
993 pkt_info.byte_cnt,
994 DMA_TO_DEVICE);
1da177e4 995
cb415d30 996 if (pkt_info.return_info)
1da177e4 997 dev_kfree_skb_irq(pkt_info.return_info);
1da177e4
LT		 998 }
999
1000 if (netif_queue_stopped(dev) &&
f98e36f1
DF		 1001 mp->tx_ring_size >
1002 mp->tx_desc_count + MAX_DESCS_PER_SKB)
1da177e4
LT		 1003 netif_wake_queue(dev);
1004}
1005
1006/*
1007 * mv643xx_poll
1008 *
1009 * This function is used in case of NAPI
1010 */
1011static int mv643xx_poll(struct net_device *dev, int *budget)
1012{
1013 struct mv643xx_private *mp = netdev_priv(dev);
1014 int done = 1, orig_budget, work_done;
1015 unsigned int port_num = mp->port_num;
1da177e4
LT		 1016
1017#ifdef MV643XX_TX_FAST_REFILL
1018 if (++mp->tx_clean_threshold > 5) {
1da177e4
LT		 1019 mv643xx_tx(dev);
1020 mp->tx_clean_threshold = 0;
1da177e4
LT		 1021 }
1022#endif
1023
1024 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1025 != (u32) mp->rx_used_desc_q) {
1026 orig_budget = *budget;
1027 if (orig_budget > dev->quota)
1028 orig_budget = dev->quota;
1029 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1030 mp->rx_task.func(dev);
1031 *budget -= work_done;
1032 dev->quota -= work_done;
1033 if (work_done >= orig_budget)
1034 done = 0;
1035 }
1036
1037 if (done) {
8f518703 1038 netif_rx_complete(dev);
1da177e4
LT		 1039 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1040 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1041 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
c2e5b352 1042 INT_UNMASK_ALL);
1da177e4
LT		 1043 }
1044
1045 return done ? 0 : 1;
1046}
1047#endif
1048
f7ea3337
PJ		 1049/* Hardware can't handle unaligned fragments smaller than 9 bytes.
1050 * This helper function detects that case.
1051 */
1052
1053static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1054{
b4de9051
DF		 1055 unsigned int frag;
1056 skb_frag_t *fragp;
f7ea3337 1057
b4de9051
DF		 1058 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1059 fragp = &skb_shinfo(skb)->frags[frag];
1060 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1061 return 1;
1062 }
1063 return 0;
f7ea3337
PJ		 1064}
1065
1066
1da177e4
LT		 1067/*
1068 * mv643xx_eth_start_xmit
1069 *
1070 * This function is queues a packet in the Tx descriptor for
1071 * required port.
1072 *
1073 * Input : skb - a pointer to socket buffer
1074 * dev - a pointer to the required port
1075 *
1076 * Output : zero upon success
1077 */
1078static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1079{
1080 struct mv643xx_private *mp = netdev_priv(dev);
1081 struct net_device_stats *stats = &mp->stats;
1082 ETH_FUNC_RET_STATUS status;
1083 unsigned long flags;
1084 struct pkt_info pkt_info;
1085
1086 if (netif_queue_stopped(dev)) {
1087 printk(KERN_ERR
1088 "%s: Tried sending packet when interface is stopped\n",
1089 dev->name);
1090 return 1;
1091 }
1092
1093 /* This is a hard error, log it. */
f98e36f1 1094 if ((mp->tx_ring_size - mp->tx_desc_count) <=
1da177e4
LT		 1095 (skb_shinfo(skb)->nr_frags + 1)) {
1096 netif_stop_queue(dev);
1097 printk(KERN_ERR
1098 "%s: Bug in mv643xx_eth - Trying to transmit when"
1099 " queue full !\n", dev->name);
1100 return 1;
1101 }
1102
1103 /* Paranoid check - this shouldn't happen */
1104 if (skb == NULL) {
1105 stats->tx_dropped++;
1106 printk(KERN_ERR "mv64320_eth paranoid check failed\n");
1107 return 1;
1108 }
1109
f7ea3337
PJ		 1110#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1111 if (has_tiny_unaligned_frags(skb)) {
1112 if ((skb_linearize(skb, GFP_ATOMIC) != 0)) {
1113 stats->tx_dropped++;
1114 printk(KERN_DEBUG "%s: failed to linearize tiny "
1115 "unaligned fragment\n", dev->name);
1116 return 1;
1117 }
1118 }
1119
1da177e4
LT		 1120 spin_lock_irqsave(&mp->lock, flags);
1121
1da177e4 1122 if (!skb_shinfo(skb)->nr_frags) {
1da177e4 1123 if (skb->ip_summed != CHECKSUM_HW) {
26006360 1124 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1da177e4 1125 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
26006360
DF		 1126 ETH_TX_FIRST_DESC |
1127 ETH_TX_LAST_DESC |
1128 5 << ETH_TX_IHL_SHIFT;
1da177e4
LT		 1129 pkt_info.l4i_chk = 0;
1130 } else {
1da177e4 1131 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
26006360
DF		 1132 ETH_TX_FIRST_DESC |
1133 ETH_TX_LAST_DESC |
1134 ETH_GEN_TCP_UDP_CHECKSUM |
1135 ETH_GEN_IP_V_4_CHECKSUM |
1136 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1da177e4 1137 /* CPU already calculated pseudo header checksum. */
63890576
WJ		 1138 if ((skb->protocol == ETH_P_IP) &&
1139 (skb->nh.iph->protocol == IPPROTO_UDP) ) {
1da177e4
LT		 1140 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1141 pkt_info.l4i_chk = skb->h.uh->check;
63890576
WJ		 1142 } else if ((skb->protocol == ETH_P_IP) &&
1143 (skb->nh.iph->protocol == IPPROTO_TCP))
1da177e4
LT		 1144 pkt_info.l4i_chk = skb->h.th->check;
1145 else {
1146 printk(KERN_ERR
63890576 1147 "%s: chksum proto != IPv4 TCP or UDP\n",
1da177e4
LT		 1148 dev->name);
1149 spin_unlock_irqrestore(&mp->lock, flags);
1150 return 1;
1151 }
1152 }
1153 pkt_info.byte_cnt = skb->len;
1154 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1155 DMA_TO_DEVICE);
1156 pkt_info.return_info = skb;
1da177e4
LT		 1157 status = eth_port_send(mp, &pkt_info);
1158 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1159 printk(KERN_ERR "%s: Error on transmitting packet\n",
1160 dev->name);
1161 stats->tx_bytes += pkt_info.byte_cnt;
1162 } else {
1163 unsigned int frag;
1da177e4 1164
1da177e4
LT		 1165 /* first frag which is skb header */
1166 pkt_info.byte_cnt = skb_headlen(skb);
1167 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
1168 skb_headlen(skb),
1169 DMA_TO_DEVICE);
1170 pkt_info.l4i_chk = 0;
1171 pkt_info.return_info = 0;
1da177e4 1172
26006360
DF		 1173 if (skb->ip_summed != CHECKSUM_HW)
1174 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1175 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1176 5 << ETH_TX_IHL_SHIFT;
1177 else {
1178 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1179 ETH_GEN_TCP_UDP_CHECKSUM |
1180 ETH_GEN_IP_V_4_CHECKSUM |
1181 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1da177e4 1182 /* CPU already calculated pseudo header checksum. */
63890576
WJ		 1183 if ((skb->protocol == ETH_P_IP) &&
1184 (skb->nh.iph->protocol == IPPROTO_UDP)) {
1da177e4
LT		 1185 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1186 pkt_info.l4i_chk = skb->h.uh->check;
63890576
WJ		 1187 } else if ((skb->protocol == ETH_P_IP) &&
1188 (skb->nh.iph->protocol == IPPROTO_TCP))
1da177e4
LT		 1189 pkt_info.l4i_chk = skb->h.th->check;
1190 else {
1191 printk(KERN_ERR
63890576 1192 "%s: chksum proto != IPv4 TCP or UDP\n",
1da177e4
LT		 1193 dev->name);
1194 spin_unlock_irqrestore(&mp->lock, flags);
1195 return 1;
1196 }
1197 }
1198
1199 status = eth_port_send(mp, &pkt_info);
1200 if (status != ETH_OK) {
1201 if ((status == ETH_ERROR))
1202 printk(KERN_ERR
1203 "%s: Error on transmitting packet\n",
1204 dev->name);
1205 if (status == ETH_QUEUE_FULL)
1206 printk("Error on Queue Full \n");
1207 if (status == ETH_QUEUE_LAST_RESOURCE)
1208 printk("Tx resource error \n");
1209 }
1210 stats->tx_bytes += pkt_info.byte_cnt;
1211
1212 /* Check for the remaining frags */
1213 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1214 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1215 pkt_info.l4i_chk = 0x0000;
1216 pkt_info.cmd_sts = 0x00000000;
1217
1218 /* Last Frag enables interrupt and frees the skb */
1219 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1220 pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT |
1221 ETH_TX_LAST_DESC;
1222 pkt_info.return_info = skb;
1da177e4
LT		 1223 } else {
1224 pkt_info.return_info = 0;
1225 }
1226 pkt_info.l4i_chk = 0;
1227 pkt_info.byte_cnt = this_frag->size;
1228
1229 pkt_info.buf_ptr = dma_map_page(NULL, this_frag->page,
1230 this_frag->page_offset,
1231 this_frag->size,
1232 DMA_TO_DEVICE);
1233
1234 status = eth_port_send(mp, &pkt_info);
1235
1236 if (status != ETH_OK) {
1237 if ((status == ETH_ERROR))
1238 printk(KERN_ERR "%s: Error on "
1239 "transmitting packet\n",
1240 dev->name);
1241
1242 if (status == ETH_QUEUE_LAST_RESOURCE)
1243 printk("Tx resource error \n");
1244
1245 if (status == ETH_QUEUE_FULL)
1246 printk("Queue is full \n");
1247 }
1248 stats->tx_bytes += pkt_info.byte_cnt;
1249 }
1250 }
1251#else
f7ea3337
PJ		 1252 spin_lock_irqsave(&mp->lock, flags);
1253
1da177e4
LT		 1254 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | ETH_TX_FIRST_DESC |
1255 ETH_TX_LAST_DESC;
1256 pkt_info.l4i_chk = 0;
1257 pkt_info.byte_cnt = skb->len;
1258 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1259 DMA_TO_DEVICE);
1260 pkt_info.return_info = skb;
1da177e4
LT		 1261 status = eth_port_send(mp, &pkt_info);
1262 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1263 printk(KERN_ERR "%s: Error on transmitting packet\n",
1264 dev->name);
1265 stats->tx_bytes += pkt_info.byte_cnt;
1266#endif
1267
1268 /* Check if TX queue can handle another skb. If not, then
1269 * signal higher layers to stop requesting TX
1270 */
f98e36f1 1271 if (mp->tx_ring_size <= (mp->tx_desc_count + MAX_DESCS_PER_SKB))
1da177e4
LT		 1272 /*
1273 * Stop getting skb's from upper layers.
1274 * Getting skb's from upper layers will be enabled again after
1275 * packets are released.
1276 */
1277 netif_stop_queue(dev);
1278
1279 /* Update statistics and start of transmittion time */
1280 stats->tx_packets++;
1281 dev->trans_start = jiffies;
1282
1283 spin_unlock_irqrestore(&mp->lock, flags);
1284
1285 return 0; /* success */
1286}
1287
1288/*
1289 * mv643xx_eth_get_stats
1290 *
1291 * Returns a pointer to the interface statistics.
1292 *
1293 * Input : dev - a pointer to the required interface
1294 *
1295 * Output : a pointer to the interface's statistics
1296 */
1297
1298static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1299{
1300 struct mv643xx_private *mp = netdev_priv(dev);
1301
1302 return &mp->stats;
1303}
1304
63c9e549 1305#ifdef CONFIG_NET_POLL_CONTROLLER
63c9e549
DF		 1306static void mv643xx_netpoll(struct net_device *netdev)
1307{
1308 struct mv643xx_private *mp = netdev_priv(netdev);
c2e5b352
DF		 1309 int port_num = mp->port_num;
1310
1311 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL);
1312 /* wait for previous write to complete */
1313 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
63c9e549 1314
63c9e549 1315 mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
c2e5b352
DF		 1316
1317 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL);
63c9e549
DF		 1318}
1319#endif
1320
1da177e4
LT		 1321/*/
1322 * mv643xx_eth_probe
1323 *
1324 * First function called after registering the network device.
1325 * It's purpose is to initialize the device as an ethernet device,
1326 * fill the ethernet device structure with pointers * to functions,
1327 * and set the MAC address of the interface
1328 *
1329 * Input : struct device *
1330 * Output : -ENOMEM if failed , 0 if success
1331 */
3ae5eaec 1332static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 1333{
1da177e4
LT		 1334 struct mv643xx_eth_platform_data *pd;
1335 int port_num = pdev->id;
1336 struct mv643xx_private *mp;
1337 struct net_device *dev;
1338 u8 *p;
1339 struct resource *res;
1340 int err;
1341
1342 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1343 if (!dev)
1344 return -ENOMEM;
1345
3ae5eaec 1346 platform_set_drvdata(pdev, dev);
1da177e4
LT		 1347
1348 mp = netdev_priv(dev);
1349
1350 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1351 BUG_ON(!res);
1352 dev->irq = res->start;
1353
1354 mp->port_num = port_num;
1355
1356 dev->open = mv643xx_eth_open;
1357 dev->stop = mv643xx_eth_stop;
1358 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1359 dev->get_stats = mv643xx_eth_get_stats;
1360 dev->set_mac_address = mv643xx_eth_set_mac_address;
1361 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1362
1363 /* No need to Tx Timeout */
1364 dev->tx_timeout = mv643xx_eth_tx_timeout;
1365#ifdef MV643XX_NAPI
1366 dev->poll = mv643xx_poll;
1367 dev->weight = 64;
1368#endif
1369
63c9e549
DF		 1370#ifdef CONFIG_NET_POLL_CONTROLLER
1371 dev->poll_controller = mv643xx_netpoll;
1372#endif
1373
1da177e4
LT		 1374 dev->watchdog_timeo = 2 * HZ;
1375 dev->tx_queue_len = mp->tx_ring_size;
1376 dev->base_addr = 0;
1377 dev->change_mtu = mv643xx_eth_change_mtu;
1378 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1379
1380#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1381#ifdef MAX_SKB_FRAGS
1382 /*
1383 * Zero copy can only work if we use Discovery II memory. Else, we will
1384 * have to map the buffers to ISA memory which is only 16 MB
1385 */
63890576 1386 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4
LT		 1387#endif
1388#endif
1389
1390 /* Configure the timeout task */
1391 INIT_WORK(&mp->tx_timeout_task,
1392 (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
1393
1394 spin_lock_init(&mp->lock);
1395
1396 /* set default config values */
1397 eth_port_uc_addr_get(dev, dev->dev_addr);
1398 mp->port_config = MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE;
1399 mp->port_config_extend = MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE;
1400 mp->port_sdma_config = MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE;
1401 mp->port_serial_control = MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE;
1402 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1403 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1404
1405 pd = pdev->dev.platform_data;
1406 if (pd) {
1407 if (pd->mac_addr != NULL)
1408 memcpy(dev->dev_addr, pd->mac_addr, 6);
1409
1410 if (pd->phy_addr || pd->force_phy_addr)
1411 ethernet_phy_set(port_num, pd->phy_addr);
1412
1413 if (pd->port_config || pd->force_port_config)
1414 mp->port_config = pd->port_config;
1415
1416 if (pd->port_config_extend || pd->force_port_config_extend)
1417 mp->port_config_extend = pd->port_config_extend;
1418
1419 if (pd->port_sdma_config || pd->force_port_sdma_config)
1420 mp->port_sdma_config = pd->port_sdma_config;
1421
1422 if (pd->port_serial_control || pd->force_port_serial_control)
1423 mp->port_serial_control = pd->port_serial_control;
1424
1425 if (pd->rx_queue_size)
1426 mp->rx_ring_size = pd->rx_queue_size;
1427
1428 if (pd->tx_queue_size)
1429 mp->tx_ring_size = pd->tx_queue_size;
1430
1431 if (pd->tx_sram_size) {
1432 mp->tx_sram_size = pd->tx_sram_size;
1433 mp->tx_sram_addr = pd->tx_sram_addr;
1434 }
1435
1436 if (pd->rx_sram_size) {
1437 mp->rx_sram_size = pd->rx_sram_size;
1438 mp->rx_sram_addr = pd->rx_sram_addr;
1439 }
1440 }
1441
c28a4f89
JC		 1442 /* Hook up MII support for ethtool */
1443 mp->mii.dev = dev;
1444 mp->mii.mdio_read = mv643xx_mdio_read;
1445 mp->mii.mdio_write = mv643xx_mdio_write;
1446 mp->mii.phy_id = ethernet_phy_get(port_num);
1447 mp->mii.phy_id_mask = 0x3f;
1448 mp->mii.reg_num_mask = 0x1f;
1449
1da177e4
LT		 1450 err = ethernet_phy_detect(port_num);
1451 if (err) {
1452 pr_debug("MV643xx ethernet port %d: "
1453 "No PHY detected at addr %d\n",
1454 port_num, ethernet_phy_get(port_num));
1455 return err;
1456 }
1457
c28a4f89
JC		 1458 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
1459
1da177e4
LT		 1460 err = register_netdev(dev);
1461 if (err)
1462 goto out;
1463
1464 p = dev->dev_addr;
1465 printk(KERN_NOTICE
1466 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1467 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1468
1469 if (dev->features & NETIF_F_SG)
1470 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1471
1472 if (dev->features & NETIF_F_IP_CSUM)
1473 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1474 dev->name);
1475
1476#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1477 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1478#endif
1479
1480#ifdef MV643XX_COAL
1481 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1482 dev->name);
1483#endif
1484
1485#ifdef MV643XX_NAPI
1486 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1487#endif
1488
b1529871
ND		 1489 if (mp->tx_sram_size > 0)
1490 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1491
1da177e4
LT		 1492 return 0;
1493
1494out:
1495 free_netdev(dev);
1496
1497 return err;
1498}
1499
3ae5eaec 1500static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 1501{
3ae5eaec 1502 struct net_device *dev = platform_get_drvdata(pdev);
1da177e4
LT		 1503
1504 unregister_netdev(dev);
1505 flush_scheduled_work();
1506
1507 free_netdev(dev);
3ae5eaec 1508 platform_set_drvdata(pdev, NULL);
1da177e4
LT		 1509 return 0;
1510}
1511
3ae5eaec 1512static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1da177e4 1513{
1da177e4
LT		 1514 struct resource *res;
1515
1516 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1517
1518 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1519 if (res == NULL)
1520 return -ENODEV;
1521
1522 mv643xx_eth_shared_base = ioremap(res->start,
1523 MV643XX_ETH_SHARED_REGS_SIZE);
1524 if (mv643xx_eth_shared_base == NULL)
1525 return -ENOMEM;
1526
1527 return 0;
1528
1529}
1530
3ae5eaec 1531static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1da177e4
LT		 1532{
1533 iounmap(mv643xx_eth_shared_base);
1534 mv643xx_eth_shared_base = NULL;
1535
1536 return 0;
1537}
1538
3ae5eaec 1539static struct platform_driver mv643xx_eth_driver = {
1da177e4
LT		 1540 .probe = mv643xx_eth_probe,
1541 .remove = mv643xx_eth_remove,
3ae5eaec
RK		 1542 .driver = {
1543 .name = MV643XX_ETH_NAME,
1544 },
1da177e4
LT		 1545};
1546
3ae5eaec 1547static struct platform_driver mv643xx_eth_shared_driver = {
1da177e4
LT		 1548 .probe = mv643xx_eth_shared_probe,
1549 .remove = mv643xx_eth_shared_remove,
3ae5eaec
RK		 1550 .driver = {
1551 .name = MV643XX_ETH_SHARED_NAME,
1552 },
1da177e4
LT		 1553};
1554
1555/*
1556 * mv643xx_init_module
1557 *
1558 * Registers the network drivers into the Linux kernel
1559 *
1560 * Input : N/A
1561 *
1562 * Output : N/A
1563 */
1564static int __init mv643xx_init_module(void)
1565{
1566 int rc;
1567
3ae5eaec 1568 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1da177e4 1569 if (!rc) {
3ae5eaec 1570 rc = platform_driver_register(&mv643xx_eth_driver);
1da177e4 1571 if (rc)
3ae5eaec 1572 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1573 }
1574 return rc;
1575}
1576
1577/*
1578 * mv643xx_cleanup_module
1579 *
1580 * Registers the network drivers into the Linux kernel
1581 *
1582 * Input : N/A
1583 *
1584 * Output : N/A
1585 */
1586static void __exit mv643xx_cleanup_module(void)
1587{
3ae5eaec
RK		 1588 platform_driver_unregister(&mv643xx_eth_driver);
1589 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1590}
1591
1592module_init(mv643xx_init_module);
1593module_exit(mv643xx_cleanup_module);
1594
1595MODULE_LICENSE("GPL");
1596MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1597 " and Dale Farnsworth");
1598MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1599
1600/*
1601 * The second part is the low level driver of the gigE ethernet ports.
1602 */
1603
1604/*
1605 * Marvell's Gigabit Ethernet controller low level driver
1606 *
1607 * DESCRIPTION:
1608 * This file introduce low level API to Marvell's Gigabit Ethernet
1609 * controller. This Gigabit Ethernet Controller driver API controls
1610 * 1) Operations (i.e. port init, start, reset etc').
1611 * 2) Data flow (i.e. port send, receive etc').
1612 * Each Gigabit Ethernet port is controlled via
1613 * struct mv643xx_private.
1614 * This struct includes user configuration information as well as
1615 * driver internal data needed for its operations.
1616 *
1617 * Supported Features:
1618 * - This low level driver is OS independent. Allocating memory for
1619 * the descriptor rings and buffers are not within the scope of
1620 * this driver.
1621 * - The user is free from Rx/Tx queue managing.
1622 * - This low level driver introduce functionality API that enable
1623 * the to operate Marvell's Gigabit Ethernet Controller in a
1624 * convenient way.
1625 * - Simple Gigabit Ethernet port operation API.
1626 * - Simple Gigabit Ethernet port data flow API.
1627 * - Data flow and operation API support per queue functionality.
1628 * - Support cached descriptors for better performance.
1629 * - Enable access to all four DRAM banks and internal SRAM memory
1630 * spaces.
1631 * - PHY access and control API.
1632 * - Port control register configuration API.
1633 * - Full control over Unicast and Multicast MAC configurations.
1634 *
1635 * Operation flow:
1636 *
1637 * Initialization phase
1638 * This phase complete the initialization of the the
1639 * mv643xx_private struct.
1640 * User information regarding port configuration has to be set
1641 * prior to calling the port initialization routine.
1642 *
1643 * In this phase any port Tx/Rx activity is halted, MIB counters
1644 * are cleared, PHY address is set according to user parameter and
1645 * access to DRAM and internal SRAM memory spaces.
1646 *
1647 * Driver ring initialization
1648 * Allocating memory for the descriptor rings and buffers is not
1649 * within the scope of this driver. Thus, the user is required to
1650 * allocate memory for the descriptors ring and buffers. Those
1651 * memory parameters are used by the Rx and Tx ring initialization
1652 * routines in order to curve the descriptor linked list in a form
1653 * of a ring.
1654 * Note: Pay special attention to alignment issues when using
1655 * cached descriptors/buffers. In this phase the driver store
1656 * information in the mv643xx_private struct regarding each queue
1657 * ring.
1658 *
1659 * Driver start
1660 * This phase prepares the Ethernet port for Rx and Tx activity.
1661 * It uses the information stored in the mv643xx_private struct to
1662 * initialize the various port registers.
1663 *
1664 * Data flow:
1665 * All packet references to/from the driver are done using
1666 * struct pkt_info.
1667 * This struct is a unified struct used with Rx and Tx operations.
1668 * This way the user is not required to be familiar with neither
1669 * Tx nor Rx descriptors structures.
1670 * The driver's descriptors rings are management by indexes.
1671 * Those indexes controls the ring resources and used to indicate
1672 * a SW resource error:
1673 * 'current'
1674 * This index points to the current available resource for use. For
1675 * example in Rx process this index will point to the descriptor
1676 * that will be passed to the user upon calling the receive
1677 * routine. In Tx process, this index will point to the descriptor
1678 * that will be assigned with the user packet info and transmitted.
1679 * 'used'
1680 * This index points to the descriptor that need to restore its
1681 * resources. For example in Rx process, using the Rx buffer return
1682 * API will attach the buffer returned in packet info to the
1683 * descriptor pointed by 'used'. In Tx process, using the Tx
1684 * descriptor return will merely return the user packet info with
1685 * the command status of the transmitted buffer pointed by the
1686 * 'used' index. Nevertheless, it is essential to use this routine
1687 * to update the 'used' index.
1688 * 'first'
1689 * This index supports Tx Scatter-Gather. It points to the first
1690 * descriptor of a packet assembled of multiple buffers. For
1691 * example when in middle of Such packet we have a Tx resource
1692 * error the 'curr' index get the value of 'first' to indicate
1693 * that the ring returned to its state before trying to transmit
1694 * this packet.
1695 *
1696 * Receive operation:
1697 * The eth_port_receive API set the packet information struct,
1698 * passed by the caller, with received information from the
1699 * 'current' SDMA descriptor.
1700 * It is the user responsibility to return this resource back
1701 * to the Rx descriptor ring to enable the reuse of this source.
1702 * Return Rx resource is done using the eth_rx_return_buff API.
1703 *
1704 * Transmit operation:
1705 * The eth_port_send API supports Scatter-Gather which enables to
1706 * send a packet spanned over multiple buffers. This means that
1707 * for each packet info structure given by the user and put into
1708 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1709 * bit will be set in the packet info command status field. This
1710 * API also consider restriction regarding buffer alignments and
1711 * sizes.
1712 * The user must return a Tx resource after ensuring the buffer
1713 * has been transmitted to enable the Tx ring indexes to update.
1714 *
1715 * BOARD LAYOUT
1716 * This device is on-board. No jumper diagram is necessary.
1717 *
1718 * EXTERNAL INTERFACE
1719 *
1720 * Prior to calling the initialization routine eth_port_init() the user
1721 * must set the following fields under mv643xx_private struct:
1722 * port_num User Ethernet port number.
1da177e4
LT		 1723 * port_config User port configuration value.
1724 * port_config_extend User port config extend value.
1725 * port_sdma_config User port SDMA config value.
1726 * port_serial_control User port serial control value.
1727 *
1728 * This driver data flow is done using the struct pkt_info which
1729 * is a unified struct for Rx and Tx operations:
1730 *
1731 * byte_cnt Tx/Rx descriptor buffer byte count.
1732 * l4i_chk CPU provided TCP Checksum. For Tx operation
1733 * only.
1734 * cmd_sts Tx/Rx descriptor command status.
1735 * buf_ptr Tx/Rx descriptor buffer pointer.
1736 * return_info Tx/Rx user resource return information.
1737 */
1738
1da177e4
LT		 1739/* PHY routines */
1740static int ethernet_phy_get(unsigned int eth_port_num);
1741static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1742
1743/* Ethernet Port routines */
cf4086c7 1744static void eth_port_set_filter_table_entry(int table, unsigned char entry);
1da177e4
LT		 1745
1746/*
1747 * eth_port_init - Initialize the Ethernet port driver
1748 *
1749 * DESCRIPTION:
1750 * This function prepares the ethernet port to start its activity:
1751 * 1) Completes the ethernet port driver struct initialization toward port
1752 * start routine.
1753 * 2) Resets the device to a quiescent state in case of warm reboot.
1754 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1755 * 4) Clean MAC tables. The reset status of those tables is unknown.
1756 * 5) Set PHY address.
1757 * Note: Call this routine prior to eth_port_start routine and after
1758 * setting user values in the user fields of Ethernet port control
1759 * struct.
1760 *
1761 * INPUT:
1762 * struct mv643xx_private *mp Ethernet port control struct
1763 *
1764 * OUTPUT:
1765 * See description.
1766 *
1767 * RETURN:
1768 * None.
1769 */
1770static void eth_port_init(struct mv643xx_private *mp)
1771{
1da177e4
LT		 1772 mp->rx_resource_err = 0;
1773 mp->tx_resource_err = 0;
1774
1775 eth_port_reset(mp->port_num);
1776
1777 eth_port_init_mac_tables(mp->port_num);
1778
1779 ethernet_phy_reset(mp->port_num);
1780}
1781
1782/*
1783 * eth_port_start - Start the Ethernet port activity.
1784 *
1785 * DESCRIPTION:
1786 * This routine prepares the Ethernet port for Rx and Tx activity:
1787 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1788 * has been initialized a descriptor's ring (using
1789 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1790 * 2. Initialize and enable the Ethernet configuration port by writing to
1791 * the port's configuration and command registers.
1792 * 3. Initialize and enable the SDMA by writing to the SDMA's
1793 * configuration and command registers. After completing these steps,
1794 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1795 *
1796 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1797 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1798 * and ether_init_rx_desc_ring for Rx queues).
1799 *
1800 * INPUT:
ed9b5d45 1801 * dev - a pointer to the required interface
1da177e4
LT		 1802 *
1803 * OUTPUT:
1804 * Ethernet port is ready to receive and transmit.
1805 *
1806 * RETURN:
1807 * None.
1808 */
ed9b5d45 1809static void eth_port_start(struct net_device *dev)
1da177e4 1810{
ed9b5d45 1811 struct mv643xx_private *mp = netdev_priv(dev);
1da177e4
LT		 1812 unsigned int port_num = mp->port_num;
1813 int tx_curr_desc, rx_curr_desc;
1814
1815 /* Assignment of Tx CTRP of given queue */
1816 tx_curr_desc = mp->tx_curr_desc_q;
1817 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1818 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1819
1820 /* Assignment of Rx CRDP of given queue */
1821 rx_curr_desc = mp->rx_curr_desc_q;
1822 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1823 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1824
1825 /* Add the assigned Ethernet address to the port's address table */
ed9b5d45 1826 eth_port_uc_addr_set(port_num, dev->dev_addr);
1da177e4
LT		 1827
1828 /* Assign port configuration and command. */
1829 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config);
1830
1831 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1832 mp->port_config_extend);
1833
1834
1835 /* Increase the Rx side buffer size if supporting GigE */
1836 if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
1837 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1838 (mp->port_serial_control & 0xfff1ffff) | (0x5 << 17));
1839 else
1840 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1841 mp->port_serial_control);
1842
1843 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1844 mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) |
1845 MV643XX_ETH_SERIAL_PORT_ENABLE);
1846
1847 /* Assign port SDMA configuration */
1848 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1849 mp->port_sdma_config);
1850
1851 /* Enable port Rx. */
9f8dd319 1852 mv643xx_eth_port_enable_rx(port_num, mp->port_rx_queue_command);
8f543718
DF		 1853
1854 /* Disable port bandwidth limits by clearing MTU register */
1855 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
1da177e4
LT		 1856}
1857
1858/*
1859 * eth_port_uc_addr_set - This function Set the port Unicast address.
1860 *
1861 * DESCRIPTION:
1862 * This function Set the port Ethernet MAC address.
1863 *
1864 * INPUT:
1865 * unsigned int eth_port_num Port number.
1866 * char * p_addr Address to be set
1867 *
1868 * OUTPUT:
cf4086c7
DF		 1869 * Set MAC address low and high registers. also calls
1870 * eth_port_set_filter_table_entry() to set the unicast
1871 * table with the proper information.
1da177e4
LT		 1872 *
1873 * RETURN:
1874 * N/A.
1875 *
1876 */
1877static void eth_port_uc_addr_set(unsigned int eth_port_num,
1878 unsigned char *p_addr)
1879{
1880 unsigned int mac_h;
1881 unsigned int mac_l;
cf4086c7 1882 int table;
1da177e4
LT		 1883
1884 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1885 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1886 (p_addr[3] << 0);
1887
1888 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1889 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1890
1891 /* Accept frames of this address */
cf4086c7
DF		 1892 table = MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(eth_port_num);
1893 eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f);
1da177e4
LT		 1894}
1895
1896/*
1897 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1898 * (MAC address) from the ethernet hw registers.
1899 *
1900 * DESCRIPTION:
1901 * This function retrieves the port Ethernet MAC address.
1902 *
1903 * INPUT:
1904 * unsigned int eth_port_num Port number.
1905 * char *MacAddr pointer where the MAC address is stored
1906 *
1907 * OUTPUT:
1908 * Copy the MAC address to the location pointed to by MacAddr
1909 *
1910 * RETURN:
1911 * N/A.
1912 *
1913 */
1914static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1915{
1916 struct mv643xx_private *mp = netdev_priv(dev);
1917 unsigned int mac_h;
1918 unsigned int mac_l;
1919
1920 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1921 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1922
1923 p_addr[0] = (mac_h >> 24) & 0xff;
1924 p_addr[1] = (mac_h >> 16) & 0xff;
1925 p_addr[2] = (mac_h >> 8) & 0xff;
1926 p_addr[3] = mac_h & 0xff;
1927 p_addr[4] = (mac_l >> 8) & 0xff;
1928 p_addr[5] = mac_l & 0xff;
1929}
1930
16e03018
DF		 1931/*
1932 * The entries in each table are indexed by a hash of a packet's MAC
1933 * address. One bit in each entry determines whether the packet is
1934 * accepted. There are 4 entries (each 8 bits wide) in each register
1935 * of the table. The bits in each entry are defined as follows:
1936 * 0 Accept=1, Drop=0
1937 * 3-1 Queue (ETH_Q0=0)
1938 * 7-4 Reserved = 0;
1939 */
1940static void eth_port_set_filter_table_entry(int table, unsigned char entry)
1941{
1942 unsigned int table_reg;
1943 unsigned int tbl_offset;
1944 unsigned int reg_offset;
1945
1946 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1947 reg_offset = entry % 4; /* Entry offset within the register */
1948
1949 /* Set "accepts frame bit" at specified table entry */
1950 table_reg = mv_read(table + tbl_offset);
1951 table_reg |= 0x01 << (8 * reg_offset);
1952 mv_write(table + tbl_offset, table_reg);
1953}
1954
1955/*
1956 * eth_port_mc_addr - Multicast address settings.
1957 *
1958 * The MV device supports multicast using two tables:
1959 * 1) Special Multicast Table for MAC addresses of the form
1960 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
1961 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1962 * Table entries in the DA-Filter table.
1963 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1964 * is used as an index to the Other Multicast Table entries in the
1965 * DA-Filter table. This function calculates the CRC-8bit value.
1966 * In either case, eth_port_set_filter_table_entry() is then called
1967 * to set to set the actual table entry.
1968 */
1969static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
1970{
1971 unsigned int mac_h;
1972 unsigned int mac_l;
1973 unsigned char crc_result = 0;
1974 int table;
1975 int mac_array[48];
1976 int crc[8];
1977 int i;
1978
1979 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
1980 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
1981 table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
1982 (eth_port_num);
1983 eth_port_set_filter_table_entry(table, p_addr[5]);
1984 return;
1985 }
1986
1987 /* Calculate CRC-8 out of the given address */
1988 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1989 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1990 (p_addr[4] << 8) | (p_addr[5] << 0);
1991
1992 for (i = 0; i < 32; i++)
1993 mac_array[i] = (mac_l >> i) & 0x1;
1994 for (i = 32; i < 48; i++)
1995 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1996
1997 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
1998 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
1999 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
2000 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
2001 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
2002
2003 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2004 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
2005 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
2006 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
2007 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
2008 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
2009 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
2010
2011 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
2012 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
2013 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
2014 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
2015 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
2016 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
2017
2018 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2019 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
2020 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
2021 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2022 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2023 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2024
2025 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2026 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2027 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2028 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2029 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2030 mac_array[3] ^ mac_array[2];
2031
2032 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2033 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2034 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2035 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2036 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2037 mac_array[4] ^ mac_array[3];
2038
2039 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2040 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2041 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2042 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2043 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2044 mac_array[4];
2045
2046 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2047 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2048 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2049 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2050 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2051
2052 for (i = 0; i < 8; i++)
2053 crc_result = crc_result | (crc[i] << i);
2054
2055 table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
2056 eth_port_set_filter_table_entry(table, crc_result);
2057}
2058
2059/*
2060 * Set the entire multicast list based on dev->mc_list.
2061 */
2062static void eth_port_set_multicast_list(struct net_device *dev)
2063{
2064
2065 struct dev_mc_list *mc_list;
2066 int i;
2067 int table_index;
2068 struct mv643xx_private *mp = netdev_priv(dev);
2069 unsigned int eth_port_num = mp->port_num;
2070
2071 /* If the device is in promiscuous mode or in all multicast mode,
2072 * we will fully populate both multicast tables with accept.
2073 * This is guaranteed to yield a match on all multicast addresses...
2074 */
2075 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2076 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
b4de9051
DF		 2077 /* Set all entries in DA filter special multicast
2078 * table (Ex_dFSMT)
2079 * Set for ETH_Q0 for now
2080 * Bits
2081 * 0 Accept=1, Drop=0
2082 * 3-1 Queue ETH_Q0=0
2083 * 7-4 Reserved = 0;
2084 */
2085 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2086
2087 /* Set all entries in DA filter other multicast
2088 * table (Ex_dFOMT)
2089 * Set for ETH_Q0 for now
2090 * Bits
2091 * 0 Accept=1, Drop=0
2092 * 3-1 Queue ETH_Q0=0
2093 * 7-4 Reserved = 0;
2094 */
2095 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2096 }
16e03018
DF		 2097 return;
2098 }
2099
2100 /* We will clear out multicast tables every time we get the list.
2101 * Then add the entire new list...
2102 */
2103 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2104 /* Clear DA filter special multicast table (Ex_dFSMT) */
2105 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2106 (eth_port_num) + table_index, 0);
2107
2108 /* Clear DA filter other multicast table (Ex_dFOMT) */
2109 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2110 (eth_port_num) + table_index, 0);
2111 }
2112
2113 /* Get pointer to net_device multicast list and add each one... */
2114 for (i = 0, mc_list = dev->mc_list;
2115 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2116 i++, mc_list = mc_list->next)
2117 if (mc_list->dmi_addrlen == 6)
2118 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
2119}
2120
1da177e4
LT		 2121/*
2122 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2123 *
2124 * DESCRIPTION:
2125 * Go through all the DA filter tables (Unicast, Special Multicast &
2126 * Other Multicast) and set each entry to 0.
2127 *
2128 * INPUT:
2129 * unsigned int eth_port_num Ethernet Port number.
2130 *
2131 * OUTPUT:
2132 * Multicast and Unicast packets are rejected.
2133 *
2134 * RETURN:
2135 * None.
2136 */
2137static void eth_port_init_mac_tables(unsigned int eth_port_num)
2138{
2139 int table_index;
2140
2141 /* Clear DA filter unicast table (Ex_dFUT) */
2142 for (table_index = 0; table_index <= 0xC; table_index += 4)
cf4086c7
DF		 2143 mv_write(MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2144 (eth_port_num) + table_index, 0);
1da177e4
LT		 2145
2146 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2147 /* Clear DA filter special multicast table (Ex_dFSMT) */
16e03018
DF		 2148 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2149 (eth_port_num) + table_index, 0);
1da177e4 2150 /* Clear DA filter other multicast table (Ex_dFOMT) */
16e03018
DF		 2151 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2152 (eth_port_num) + table_index, 0);
1da177e4
LT		 2153 }
2154}
2155
2156/*
2157 * eth_clear_mib_counters - Clear all MIB counters
2158 *
2159 * DESCRIPTION:
2160 * This function clears all MIB counters of a specific ethernet port.
2161 * A read from the MIB counter will reset the counter.
2162 *
2163 * INPUT:
2164 * unsigned int eth_port_num Ethernet Port number.
2165 *
2166 * OUTPUT:
2167 * After reading all MIB counters, the counters resets.
2168 *
2169 * RETURN:
2170 * MIB counter value.
2171 *
2172 */
2173static void eth_clear_mib_counters(unsigned int eth_port_num)
2174{
2175 int i;
2176
2177 /* Perform dummy reads from MIB counters */
2178 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2179 i += 4)
2180 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2181}
2182
2183static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2184{
2185 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2186}
2187
2188static void eth_update_mib_counters(struct mv643xx_private *mp)
2189{
2190 struct mv643xx_mib_counters *p = &mp->mib_counters;
2191 int offset;
2192
2193 p->good_octets_received +=
2194 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2195 p->good_octets_received +=
2196 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2197
2198 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2199 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2200 offset += 4)
2201 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2202
2203 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2204 p->good_octets_sent +=
2205 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2206
2207 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2208 offset <= ETH_MIB_LATE_COLLISION;
2209 offset += 4)
2210 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2211}
2212
2213/*
2214 * ethernet_phy_detect - Detect whether a phy is present
2215 *
2216 * DESCRIPTION:
2217 * This function tests whether there is a PHY present on
2218 * the specified port.
2219 *
2220 * INPUT:
2221 * unsigned int eth_port_num Ethernet Port number.
2222 *
2223 * OUTPUT:
2224 * None
2225 *
2226 * RETURN:
2227 * 0 on success
2228 * -ENODEV on failure
2229 *
2230 */
2231static int ethernet_phy_detect(unsigned int port_num)
2232{
2233 unsigned int phy_reg_data0;
2234 int auto_neg;
2235
2236 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2237 auto_neg = phy_reg_data0 & 0x1000;
2238 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2239 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2240
2241 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2242 if ((phy_reg_data0 & 0x1000) == auto_neg)
2243 return -ENODEV; /* change didn't take */
2244
2245 phy_reg_data0 ^= 0x1000;
2246 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2247 return 0;
2248}
2249
2250/*
2251 * ethernet_phy_get - Get the ethernet port PHY address.
2252 *
2253 * DESCRIPTION:
2254 * This routine returns the given ethernet port PHY address.
2255 *
2256 * INPUT:
2257 * unsigned int eth_port_num Ethernet Port number.
2258 *
2259 * OUTPUT:
2260 * None.
2261 *
2262 * RETURN:
2263 * PHY address.
2264 *
2265 */
2266static int ethernet_phy_get(unsigned int eth_port_num)
2267{
2268 unsigned int reg_data;
2269
2270 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2271
2272 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2273}
2274
2275/*
2276 * ethernet_phy_set - Set the ethernet port PHY address.
2277 *
2278 * DESCRIPTION:
2279 * This routine sets the given ethernet port PHY address.
2280 *
2281 * INPUT:
2282 * unsigned int eth_port_num Ethernet Port number.
2283 * int phy_addr PHY address.
2284 *
2285 * OUTPUT:
2286 * None.
2287 *
2288 * RETURN:
2289 * None.
2290 *
2291 */
2292static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2293{
2294 u32 reg_data;
2295 int addr_shift = 5 * eth_port_num;
2296
2297 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2298 reg_data &= ~(0x1f << addr_shift);
2299 reg_data |= (phy_addr & 0x1f) << addr_shift;
2300 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2301}
2302
2303/*
2304 * ethernet_phy_reset - Reset Ethernet port PHY.
2305 *
2306 * DESCRIPTION:
2307 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2308 *
2309 * INPUT:
2310 * unsigned int eth_port_num Ethernet Port number.
2311 *
2312 * OUTPUT:
2313 * The PHY is reset.
2314 *
2315 * RETURN:
2316 * None.
2317 *
2318 */
2319static void ethernet_phy_reset(unsigned int eth_port_num)
2320{
2321 unsigned int phy_reg_data;
2322
2323 /* Reset the PHY */
2324 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2325 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2326 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2327}
2328
9f8dd319
DF		 2329static void mv643xx_eth_port_enable_tx(unsigned int port_num,
2330 unsigned int channels)
2331{
2332 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), channels);
2333}
2334
2335static void mv643xx_eth_port_enable_rx(unsigned int port_num,
2336 unsigned int channels)
2337{
2338 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), channels);
2339}
2340
2341static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
2342{
2343 u32 channels;
2344
2345 /* Stop Tx port activity. Check port Tx activity. */
2346 channels = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2347 & 0xFF;
2348 if (channels) {
2349 /* Issue stop command for active channels only */
2350 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
2351 (channels << 8));
2352
2353 /* Wait for all Tx activity to terminate. */
2354 /* Check port cause register that all Tx queues are stopped */
2355 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2356 & 0xFF)
2357 udelay(PHY_WAIT_MICRO_SECONDS);
2358
2359 /* Wait for Tx FIFO to empty */
2360 while (mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num)) &
2361 ETH_PORT_TX_FIFO_EMPTY)
2362 udelay(PHY_WAIT_MICRO_SECONDS);
2363 }
2364
2365 return channels;
2366}
2367
2368static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
2369{
2370 u32 channels;
2371
2372 /* Stop Rx port activity. Check port Rx activity. */
2373 channels = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num)
2374 & 0xFF);
2375 if (channels) {
2376 /* Issue stop command for active channels only */
2377 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
2378 (channels << 8));
2379
2380 /* Wait for all Rx activity to terminate. */
2381 /* Check port cause register that all Rx queues are stopped */
2382 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2383 & 0xFF)
2384 udelay(PHY_WAIT_MICRO_SECONDS);
2385 }
2386
2387 return channels;
2388}
2389
1da177e4
LT		 2390/*
2391 * eth_port_reset - Reset Ethernet port
2392 *
2393 * DESCRIPTION:
2394 * This routine resets the chip by aborting any SDMA engine activity and
2395 * clearing the MIB counters. The Receiver and the Transmit unit are in
2396 * idle state after this command is performed and the port is disabled.
2397 *
2398 * INPUT:
2399 * unsigned int eth_port_num Ethernet Port number.
2400 *
2401 * OUTPUT:
2402 * Channel activity is halted.
2403 *
2404 * RETURN:
2405 * None.
2406 *
2407 */
2408static void eth_port_reset(unsigned int port_num)
2409{
2410 unsigned int reg_data;
2411
9f8dd319
DF		 2412 mv643xx_eth_port_disable_tx(port_num);
2413 mv643xx_eth_port_disable_rx(port_num);
1da177e4
LT		 2414
2415 /* Clear all MIB counters */
2416 eth_clear_mib_counters(port_num);
2417
2418 /* Reset the Enable bit in the Configuration Register */
2419 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2420 reg_data &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
2421 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2422}
2423
1da177e4
LT		 2424
2425static int eth_port_autoneg_supported(unsigned int eth_port_num)
2426{
2427 unsigned int phy_reg_data0;
2428
2429 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data0);
2430
2431 return phy_reg_data0 & 0x1000;
2432}
2433
1da177e4
LT		 2434/*
2435 * eth_port_read_smi_reg - Read PHY registers
2436 *
2437 * DESCRIPTION:
2438 * This routine utilize the SMI interface to interact with the PHY in
2439 * order to perform PHY register read.
2440 *
2441 * INPUT:
2442 * unsigned int port_num Ethernet Port number.
2443 * unsigned int phy_reg PHY register address offset.
2444 * unsigned int *value Register value buffer.
2445 *
2446 * OUTPUT:
2447 * Write the value of a specified PHY register into given buffer.
2448 *
2449 * RETURN:
2450 * false if the PHY is busy or read data is not in valid state.
2451 * true otherwise.
2452 *
2453 */
2454static void eth_port_read_smi_reg(unsigned int port_num,
2455 unsigned int phy_reg, unsigned int *value)
2456{
2457 int phy_addr = ethernet_phy_get(port_num);
2458 unsigned long flags;
2459 int i;
2460
2461 /* the SMI register is a shared resource */
2462 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2463
2464 /* wait for the SMI register to become available */
2465 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2466 if (i == PHY_WAIT_ITERATIONS) {
2467 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2468 goto out;
2469 }
2470 udelay(PHY_WAIT_MICRO_SECONDS);
2471 }
2472
2473 mv_write(MV643XX_ETH_SMI_REG,
2474 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2475
2476 /* now wait for the data to be valid */
2477 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2478 if (i == PHY_WAIT_ITERATIONS) {
2479 printk("mv643xx PHY read timeout, port %d\n", port_num);
2480 goto out;
2481 }
2482 udelay(PHY_WAIT_MICRO_SECONDS);
2483 }
2484
2485 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2486out:
2487 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2488}
2489
2490/*
2491 * eth_port_write_smi_reg - Write to PHY registers
2492 *
2493 * DESCRIPTION:
2494 * This routine utilize the SMI interface to interact with the PHY in
2495 * order to perform writes to PHY registers.
2496 *
2497 * INPUT:
2498 * unsigned int eth_port_num Ethernet Port number.
2499 * unsigned int phy_reg PHY register address offset.
2500 * unsigned int value Register value.
2501 *
2502 * OUTPUT:
2503 * Write the given value to the specified PHY register.
2504 *
2505 * RETURN:
2506 * false if the PHY is busy.
2507 * true otherwise.
2508 *
2509 */
2510static void eth_port_write_smi_reg(unsigned int eth_port_num,
2511 unsigned int phy_reg, unsigned int value)
2512{
2513 int phy_addr;
2514 int i;
2515 unsigned long flags;
2516
2517 phy_addr = ethernet_phy_get(eth_port_num);
2518
2519 /* the SMI register is a shared resource */
2520 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2521
2522 /* wait for the SMI register to become available */
2523 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2524 if (i == PHY_WAIT_ITERATIONS) {
2525 printk("mv643xx PHY busy timeout, port %d\n",
2526 eth_port_num);
2527 goto out;
2528 }
2529 udelay(PHY_WAIT_MICRO_SECONDS);
2530 }
2531
2532 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2533 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2534out:
2535 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2536}
2537
c28a4f89
JC		 2538/*
2539 * Wrappers for MII support library.
2540 */
2541static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
2542{
2543 int val;
2544 struct mv643xx_private *mp = netdev_priv(dev);
2545
2546 eth_port_read_smi_reg(mp->port_num, location, &val);
2547 return val;
2548}
2549
2550static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
2551{
2552 struct mv643xx_private *mp = netdev_priv(dev);
2553 eth_port_write_smi_reg(mp->port_num, location, val);
2554}
2555
1da177e4
LT		 2556/*
2557 * eth_port_send - Send an Ethernet packet
2558 *
2559 * DESCRIPTION:
2560 * This routine send a given packet described by p_pktinfo parameter. It
2561 * supports transmitting of a packet spaned over multiple buffers. The
2562 * routine updates 'curr' and 'first' indexes according to the packet
2563 * segment passed to the routine. In case the packet segment is first,
2564 * the 'first' index is update. In any case, the 'curr' index is updated.
2565 * If the routine get into Tx resource error it assigns 'curr' index as
2566 * 'first'. This way the function can abort Tx process of multiple
2567 * descriptors per packet.
2568 *
2569 * INPUT:
2570 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2571 * struct pkt_info *p_pkt_info User packet buffer.
2572 *
2573 * OUTPUT:
2574 * Tx ring 'curr' and 'first' indexes are updated.
2575 *
2576 * RETURN:
2577 * ETH_QUEUE_FULL in case of Tx resource error.
2578 * ETH_ERROR in case the routine can not access Tx desc ring.
2579 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2580 * ETH_OK otherwise.
2581 *
2582 */
2583#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2584/*
2585 * Modified to include the first descriptor pointer in case of SG
2586 */
2587static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2588 struct pkt_info *p_pkt_info)
2589{
2590 int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc;
2591 struct eth_tx_desc *current_descriptor;
2592 struct eth_tx_desc *first_descriptor;
2593 u32 command;
2594
2595 /* Do not process Tx ring in case of Tx ring resource error */
2596 if (mp->tx_resource_err)
2597 return ETH_QUEUE_FULL;
2598
2599 /*
2600 * The hardware requires that each buffer that is <= 8 bytes
2601 * in length must be aligned on an 8 byte boundary.
2602 */
2603 if (p_pkt_info->byte_cnt <= 8 && p_pkt_info->buf_ptr & 0x7) {
2604 printk(KERN_ERR
2605 "mv643xx_eth port %d: packet size <= 8 problem\n",
2606 mp->port_num);
2607 return ETH_ERROR;
2608 }
2609
f98e36f1
DF		 2610 mp->tx_desc_count++;
2611 BUG_ON(mp->tx_desc_count > mp->tx_ring_size);
b111ceb6 2612
1da177e4
LT		 2613 /* Get the Tx Desc ring indexes */
2614 tx_desc_curr = mp->tx_curr_desc_q;
2615 tx_desc_used = mp->tx_used_desc_q;
2616
2617 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2618
2619 tx_next_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
2620
2621 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2622 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2623 current_descriptor->l4i_chk = p_pkt_info->l4i_chk;
2624 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2625
2626 command = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC |
2627 ETH_BUFFER_OWNED_BY_DMA;
2628 if (command & ETH_TX_FIRST_DESC) {
2629 tx_first_desc = tx_desc_curr;
2630 mp->tx_first_desc_q = tx_first_desc;
2631 first_descriptor = current_descriptor;
2632 mp->tx_first_command = command;
2633 } else {
2634 tx_first_desc = mp->tx_first_desc_q;
2635 first_descriptor = &mp->p_tx_desc_area[tx_first_desc];
2636 BUG_ON(first_descriptor == NULL);
2637 current_descriptor->cmd_sts = command;
2638 }
2639
2640 if (command & ETH_TX_LAST_DESC) {
2641 wmb();
2642 first_descriptor->cmd_sts = mp->tx_first_command;
2643
2644 wmb();
9f8dd319 2645 mv643xx_eth_port_enable_tx(mp->port_num, mp->port_tx_queue_command);
1da177e4
LT		 2646
2647 /*
2648 * Finish Tx packet. Update first desc in case of Tx resource
2649 * error */
2650 tx_first_desc = tx_next_desc;
2651 mp->tx_first_desc_q = tx_first_desc;
2652 }
2653
2654 /* Check for ring index overlap in the Tx desc ring */
2655 if (tx_next_desc == tx_desc_used) {
2656 mp->tx_resource_err = 1;
2657 mp->tx_curr_desc_q = tx_first_desc;
2658
2659 return ETH_QUEUE_LAST_RESOURCE;
2660 }
2661
2662 mp->tx_curr_desc_q = tx_next_desc;
2663
2664 return ETH_OK;
2665}
2666#else
2667static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2668 struct pkt_info *p_pkt_info)
2669{
2670 int tx_desc_curr;
2671 int tx_desc_used;
2672 struct eth_tx_desc *current_descriptor;
2673 unsigned int command_status;
2674
2675 /* Do not process Tx ring in case of Tx ring resource error */
2676 if (mp->tx_resource_err)
2677 return ETH_QUEUE_FULL;
2678
f98e36f1
DF		 2679 mp->tx_desc_count++;
2680 BUG_ON(mp->tx_desc_count > mp->tx_ring_size);
b111ceb6 2681
1da177e4
LT		 2682 /* Get the Tx Desc ring indexes */
2683 tx_desc_curr = mp->tx_curr_desc_q;
2684 tx_desc_used = mp->tx_used_desc_q;
2685 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2686
2687 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2688 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2689 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2690 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2691
2692 /* Set last desc with DMA ownership and interrupt enable. */
2693 wmb();
2694 current_descriptor->cmd_sts = command_status |
2695 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2696
2697 wmb();
9f8dd319 2698 mv643xx_eth_port_enable_tx(mp->port_num, mp->port_tx_queue_command);
1da177e4
LT		 2699
2700 /* Finish Tx packet. Update first desc in case of Tx resource error */
2701 tx_desc_curr = (tx_desc_curr + 1) % mp->tx_ring_size;
2702
2703 /* Update the current descriptor */
2704 mp->tx_curr_desc_q = tx_desc_curr;
2705
2706 /* Check for ring index overlap in the Tx desc ring */
2707 if (tx_desc_curr == tx_desc_used) {
2708 mp->tx_resource_err = 1;
2709 return ETH_QUEUE_LAST_RESOURCE;
2710 }
2711
2712 return ETH_OK;
2713}
2714#endif
2715
2716/*
2717 * eth_tx_return_desc - Free all used Tx descriptors
2718 *
2719 * DESCRIPTION:
2720 * This routine returns the transmitted packet information to the caller.
2721 * It uses the 'first' index to support Tx desc return in case a transmit
2722 * of a packet spanned over multiple buffer still in process.
2723 * In case the Tx queue was in "resource error" condition, where there are
2724 * no available Tx resources, the function resets the resource error flag.
2725 *
2726 * INPUT:
2727 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2728 * struct pkt_info *p_pkt_info User packet buffer.
2729 *
2730 * OUTPUT:
2731 * Tx ring 'first' and 'used' indexes are updated.
2732 *
2733 * RETURN:
8f518703
DF		 2734 * ETH_OK on success
2735 * ETH_ERROR otherwise.
1da177e4
LT		 2736 *
2737 */
2738static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
2739 struct pkt_info *p_pkt_info)
2740{
2741 int tx_desc_used;
8f518703
DF		 2742 int tx_busy_desc;
2743 struct eth_tx_desc *p_tx_desc_used;
2744 unsigned int command_status;
2745 unsigned long flags;
2746 int err = ETH_OK;
2747
2748 spin_lock_irqsave(&mp->lock, flags);
2749
1da177e4 2750#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
8f518703 2751 tx_busy_desc = mp->tx_first_desc_q;
1da177e4 2752#else
8f518703 2753 tx_busy_desc = mp->tx_curr_desc_q;
1da177e4 2754#endif
1da177e4
LT		 2755
2756 /* Get the Tx Desc ring indexes */
2757 tx_desc_used = mp->tx_used_desc_q;
2758
2759 p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];
2760
2761 /* Sanity check */
8f518703
DF		 2762 if (p_tx_desc_used == NULL) {
2763 err = ETH_ERROR;
2764 goto out;
2765 }
1da177e4
LT		 2766
2767 /* Stop release. About to overlap the current available Tx descriptor */
8f518703
DF		 2768 if (tx_desc_used == tx_busy_desc && !mp->tx_resource_err) {
2769 err = ETH_ERROR;
2770 goto out;
2771 }
1da177e4
LT		 2772
2773 command_status = p_tx_desc_used->cmd_sts;
2774
2775 /* Still transmitting... */
8f518703
DF		 2776 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2777 err = ETH_ERROR;
2778 goto out;
2779 }
1da177e4
LT		 2780
2781 /* Pass the packet information to the caller */
2782 p_pkt_info->cmd_sts = command_status;
2783 p_pkt_info->return_info = mp->tx_skb[tx_desc_used];
4eaa3cb3
PG		 2784 p_pkt_info->buf_ptr = p_tx_desc_used->buf_ptr;
2785 p_pkt_info->byte_cnt = p_tx_desc_used->byte_cnt;
1da177e4
LT		 2786 mp->tx_skb[tx_desc_used] = NULL;
2787
2788 /* Update the next descriptor to release. */
2789 mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size;
2790
2791 /* Any Tx return cancels the Tx resource error status */
2792 mp->tx_resource_err = 0;
2793
f98e36f1
DF		 2794 BUG_ON(mp->tx_desc_count == 0);
2795 mp->tx_desc_count--;
b111ceb6 2796
8f518703
DF		 2797out:
2798 spin_unlock_irqrestore(&mp->lock, flags);
2799
2800 return err;
1da177e4
LT		 2801}
2802
2803/*
2804 * eth_port_receive - Get received information from Rx ring.
2805 *
2806 * DESCRIPTION:
2807 * This routine returns the received data to the caller. There is no
2808 * data copying during routine operation. All information is returned
2809 * using pointer to packet information struct passed from the caller.
2810 * If the routine exhausts Rx ring resources then the resource error flag
2811 * is set.
2812 *
2813 * INPUT:
2814 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2815 * struct pkt_info *p_pkt_info User packet buffer.
2816 *
2817 * OUTPUT:
2818 * Rx ring current and used indexes are updated.
2819 *
2820 * RETURN:
2821 * ETH_ERROR in case the routine can not access Rx desc ring.
2822 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2823 * ETH_END_OF_JOB if there is no received data.
2824 * ETH_OK otherwise.
2825 */
2826static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2827 struct pkt_info *p_pkt_info)
2828{
2829 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2830 volatile struct eth_rx_desc *p_rx_desc;
2831 unsigned int command_status;
8f518703 2832 unsigned long flags;
1da177e4
LT		 2833
2834 /* Do not process Rx ring in case of Rx ring resource error */
2835 if (mp->rx_resource_err)
2836 return ETH_QUEUE_FULL;
2837
8f518703
DF		 2838 spin_lock_irqsave(&mp->lock, flags);
2839
1da177e4
LT		 2840 /* Get the Rx Desc ring 'curr and 'used' indexes */
2841 rx_curr_desc = mp->rx_curr_desc_q;
2842 rx_used_desc = mp->rx_used_desc_q;
2843
2844 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2845
2846 /* The following parameters are used to save readings from memory */
2847 command_status = p_rx_desc->cmd_sts;
2848 rmb();
2849
2850 /* Nothing to receive... */
8f518703
DF		 2851 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2852 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 2853 return ETH_END_OF_JOB;
8f518703 2854 }
1da177e4
LT		 2855
2856 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2857 p_pkt_info->cmd_sts = command_status;
2858 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2859 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2860 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2861
b4de9051
DF		 2862 /*
2863 * Clean the return info field to indicate that the
2864 * packet has been moved to the upper layers
2865 */
1da177e4
LT		 2866 mp->rx_skb[rx_curr_desc] = NULL;
2867
2868 /* Update current index in data structure */
2869 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2870 mp->rx_curr_desc_q = rx_next_curr_desc;
2871
2872 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2873 if (rx_next_curr_desc == rx_used_desc)
2874 mp->rx_resource_err = 1;
2875
8f518703
DF		 2876 spin_unlock_irqrestore(&mp->lock, flags);
2877
1da177e4
LT		 2878 return ETH_OK;
2879}
2880
2881/*
2882 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2883 *
2884 * DESCRIPTION:
2885 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2886 * next 'used' descriptor and attached the returned buffer to it.
2887 * In case the Rx ring was in "resource error" condition, where there are
2888 * no available Rx resources, the function resets the resource error flag.
2889 *
2890 * INPUT:
2891 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2892 * struct pkt_info *p_pkt_info Information on returned buffer.
2893 *
2894 * OUTPUT:
2895 * New available Rx resource in Rx descriptor ring.
2896 *
2897 * RETURN:
2898 * ETH_ERROR in case the routine can not access Rx desc ring.
2899 * ETH_OK otherwise.
2900 */
2901static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2902 struct pkt_info *p_pkt_info)
2903{
2904 int used_rx_desc; /* Where to return Rx resource */
2905 volatile struct eth_rx_desc *p_used_rx_desc;
8f518703
DF		 2906 unsigned long flags;
2907
2908 spin_lock_irqsave(&mp->lock, flags);
1da177e4
LT		 2909
2910 /* Get 'used' Rx descriptor */
2911 used_rx_desc = mp->rx_used_desc_q;
2912 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2913
2914 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2915 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2916 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2917
2918 /* Flush the write pipe */
2919
2920 /* Return the descriptor to DMA ownership */
2921 wmb();
2922 p_used_rx_desc->cmd_sts =
2923 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2924 wmb();
2925
2926 /* Move the used descriptor pointer to the next descriptor */
2927 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2928
2929 /* Any Rx return cancels the Rx resource error status */
2930 mp->rx_resource_err = 0;
2931
8f518703
DF		 2932 spin_unlock_irqrestore(&mp->lock, flags);
2933
1da177e4
LT		 2934 return ETH_OK;
2935}
2936
2937/************* Begin ethtool support *************************/
2938
2939struct mv643xx_stats {
2940 char stat_string[ETH_GSTRING_LEN];
2941 int sizeof_stat;
2942 int stat_offset;
2943};
2944
2945#define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
b4de9051 2946 offsetof(struct mv643xx_private, m)
1da177e4
LT		 2947
2948static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
2949 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
2950 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
2951 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
2952 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
2953 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
2954 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
2955 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
2956 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
2957 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
2958 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
2959 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
2960 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
2961 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
2962 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
2963 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
2964 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
2965 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
2966 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
2967 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
2968 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
2969 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
2970 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
2971 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
2972 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
2973 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
2974 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
2975 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
2976 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
2977 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
2978 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
2979 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
2980 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
2981 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
2982 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
2983 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
2984 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
2985 { "collision", MV643XX_STAT(mib_counters.collision) },
2986 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
2987};
2988
2989#define MV643XX_STATS_LEN \
2990 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
2991
2992static int
2993mv643xx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
2994{
2995 struct mv643xx_private *mp = netdev->priv;
2996 int port_num = mp->port_num;
2997 int autoneg = eth_port_autoneg_supported(port_num);
2998 int mode_10_bit;
2999 int auto_duplex;
3000 int half_duplex = 0;
3001 int full_duplex = 0;
3002 int auto_speed;
3003 int speed_10 = 0;
3004 int speed_100 = 0;
3005 int speed_1000 = 0;
3006
3007 u32 pcs = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
3008 u32 psr = mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num));
3009
3010 mode_10_bit = psr & MV643XX_ETH_PORT_STATUS_MODE_10_BIT;
3011
3012 if (mode_10_bit) {
3013 ecmd->supported = SUPPORTED_10baseT_Half;
3014 } else {
3015 ecmd->supported = (SUPPORTED_10baseT_Half |
3016 SUPPORTED_10baseT_Full |
3017 SUPPORTED_100baseT_Half |
3018 SUPPORTED_100baseT_Full |
3019 SUPPORTED_1000baseT_Full |
3020 (autoneg ? SUPPORTED_Autoneg : 0) |
3021 SUPPORTED_TP);
3022
3023 auto_duplex = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX);
3024 auto_speed = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII);
3025
3026 ecmd->advertising = ADVERTISED_TP;
3027
3028 if (autoneg) {
3029 ecmd->advertising |= ADVERTISED_Autoneg;
3030
3031 if (auto_duplex) {
3032 half_duplex = 1;
3033 full_duplex = 1;
3034 } else {
3035 if (pcs & MV643XX_ETH_SET_FULL_DUPLEX_MODE)
3036 full_duplex = 1;
3037 else
3038 half_duplex = 1;
3039 }
3040
3041 if (auto_speed) {
3042 speed_10 = 1;
3043 speed_100 = 1;
3044 speed_1000 = 1;
3045 } else {
3046 if (pcs & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
3047 speed_1000 = 1;
3048 else if (pcs & MV643XX_ETH_SET_MII_SPEED_TO_100)
3049 speed_100 = 1;
3050 else
3051 speed_10 = 1;
3052 }
3053
3054 if (speed_10 & half_duplex)
3055 ecmd->advertising |= ADVERTISED_10baseT_Half;
3056 if (speed_10 & full_duplex)
3057 ecmd->advertising |= ADVERTISED_10baseT_Full;
3058 if (speed_100 & half_duplex)
3059 ecmd->advertising |= ADVERTISED_100baseT_Half;
3060 if (speed_100 & full_duplex)
3061 ecmd->advertising |= ADVERTISED_100baseT_Full;
3062 if (speed_1000)
3063 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3064 }
3065 }
3066
3067 ecmd->port = PORT_TP;
3068 ecmd->phy_address = ethernet_phy_get(port_num);
3069
3070 ecmd->transceiver = XCVR_EXTERNAL;
3071
3072 if (netif_carrier_ok(netdev)) {
3073 if (mode_10_bit)
3074 ecmd->speed = SPEED_10;
3075 else {
3076 if (psr & MV643XX_ETH_PORT_STATUS_GMII_1000)
3077 ecmd->speed = SPEED_1000;
3078 else if (psr & MV643XX_ETH_PORT_STATUS_MII_100)
3079 ecmd->speed = SPEED_100;
3080 else
3081 ecmd->speed = SPEED_10;
3082 }
3083
3084 if (psr & MV643XX_ETH_PORT_STATUS_FULL_DUPLEX)
3085 ecmd->duplex = DUPLEX_FULL;
3086 else
3087 ecmd->duplex = DUPLEX_HALF;
3088 } else {
3089 ecmd->speed = -1;
3090 ecmd->duplex = -1;
3091 }
3092
3093 ecmd->autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3094 return 0;
3095}
3096
b4de9051
DF		 3097static void mv643xx_get_drvinfo(struct net_device *netdev,
3098 struct ethtool_drvinfo *drvinfo)
1da177e4
LT		 3099{
3100 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
3101 strncpy(drvinfo->version, mv643xx_driver_version, 32);
3102 strncpy(drvinfo->fw_version, "N/A", 32);
3103 strncpy(drvinfo->bus_info, "mv643xx", 32);
3104 drvinfo->n_stats = MV643XX_STATS_LEN;
3105}
3106
b4de9051 3107static int mv643xx_get_stats_count(struct net_device *netdev)
1da177e4
LT		 3108{
3109 return MV643XX_STATS_LEN;
3110}
3111
b4de9051
DF		 3112static void mv643xx_get_ethtool_stats(struct net_device *netdev,
3113 struct ethtool_stats *stats, uint64_t *data)
1da177e4
LT		 3114{
3115 struct mv643xx_private *mp = netdev->priv;
3116 int i;
3117
3118 eth_update_mib_counters(mp);
3119
b4de9051 3120 for (i = 0; i < MV643XX_STATS_LEN; i++) {
1da177e4 3121 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
b4de9051 3122 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
1da177e4
LT		 3123 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
3124 }
3125}
3126
b4de9051
DF		 3127static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
3128 uint8_t *data)
1da177e4
LT		 3129{
3130 int i;
3131
3132 switch(stringset) {
3133 case ETH_SS_STATS:
3134 for (i=0; i < MV643XX_STATS_LEN; i++) {
b4de9051
DF		 3135 memcpy(data + i * ETH_GSTRING_LEN,
3136 mv643xx_gstrings_stats[i].stat_string,
3137 ETH_GSTRING_LEN);
1da177e4
LT		 3138 }
3139 break;
3140 }
3141}
3142
3143static struct ethtool_ops mv643xx_ethtool_ops = {
3144 .get_settings = mv643xx_get_settings,
3145 .get_drvinfo = mv643xx_get_drvinfo,
3146 .get_link = ethtool_op_get_link,
3147 .get_sg = ethtool_op_get_sg,
3148 .set_sg = ethtool_op_set_sg,
3149 .get_strings = mv643xx_get_strings,
3150 .get_stats_count = mv643xx_get_stats_count,
3151 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3152};
3153
3154/************* End ethtool support *************************/
Clone of davem's net-next-2.6 tree