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mv643xx_eth: shrink default receive and transmit queue sizes
[net-next-2.6.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
c4560318 58static char mv643xx_eth_driver_version[] = "1.3";
c9df406f 59
fbd6a754 60
fbd6a754
LB		 61/*
62 * Registers shared between all ports.
63 */
3cb4667c
LB		 64#define PHY_ADDR 0x0000
65#define SMI_REG 0x0004
45c5d3bc
LB		 66#define SMI_BUSY 0x10000000
67#define SMI_READ_VALID 0x08000000
68#define SMI_OPCODE_READ 0x04000000
69#define SMI_OPCODE_WRITE 0x00000000
70#define ERR_INT_CAUSE 0x0080
71#define ERR_INT_SMI_DONE 0x00000010
72#define ERR_INT_MASK 0x0084
3cb4667c
LB		 73#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
74#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
75#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
76#define WINDOW_BAR_ENABLE 0x0290
77#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 78
79/*
80 * Per-port registers.
81 */
3cb4667c 82#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 83#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 84#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
85#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
86#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
87#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
88#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
89#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 90#define TX_FIFO_EMPTY 0x00000400
ae9ae064 91#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 92#define PORT_SPEED_MASK 0x00000030
93#define PORT_SPEED_1000 0x00000010
94#define PORT_SPEED_100 0x00000020
95#define PORT_SPEED_10 0x00000000
96#define FLOW_CONTROL_ENABLED 0x00000008
97#define FULL_DUPLEX 0x00000004
81600eea 98#define LINK_UP 0x00000002
3cb4667c 99#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 100#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
101#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 102#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 103#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 104#define INT_CAUSE(p) (0x0460 + ((p) << 10))
226bb6b7 105#define INT_TX_END 0x07f80000
befefe21 106#define INT_RX 0x000003fc
073a345c 107#define INT_EXT 0x00000002
3cb4667c 108#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
befefe21
LB		 109#define INT_EXT_LINK_PHY 0x00110000
110#define INT_EXT_TX 0x000000ff
3cb4667c
LB		 111#define INT_MASK(p) (0x0468 + ((p) << 10))
112#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
113#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
1e881592
LB		 114#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
115#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
116#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
117#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
64da80a2 118#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
3cb4667c 119#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
3d6b35bc
LB		 120#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
121#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
122#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
123#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
3cb4667c
LB		 124#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
125#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
126#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
127#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 128
2679a550
LB		 129
130/*
131 * SDMA configuration register.
132 */
cd4ccf76 133#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 134#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 135#define BLM_TX_NO_SWAP (1 << 5)
cd4ccf76 136#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 137
138#if defined(__BIG_ENDIAN)
139#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76
LB		 140 RX_BURST_SIZE_16_64BIT | \
141 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 142#elif defined(__LITTLE_ENDIAN)
143#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76 144 RX_BURST_SIZE_16_64BIT | \
fbd6a754
LB		 145 BLM_RX_NO_SWAP | \
146 BLM_TX_NO_SWAP | \
cd4ccf76 147 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 148#else
149#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
150#endif
151
2beff77b
LB		 152
153/*
154 * Port serial control register.
155 */
156#define SET_MII_SPEED_TO_100 (1 << 24)
157#define SET_GMII_SPEED_TO_1000 (1 << 23)
158#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 159#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 160#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
161#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
162#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
163#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
164#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
165#define FORCE_LINK_PASS (1 << 1)
166#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 167
2b4a624d
LB		 168#define DEFAULT_RX_QUEUE_SIZE 128
169#define DEFAULT_TX_QUEUE_SIZE 256
fbd6a754 170
fbd6a754 171
7ca72a3b
LB		 172/*
173 * RX/TX descriptors.
fbd6a754
LB		 174 */
175#if defined(__BIG_ENDIAN)
cc9754b3 176struct rx_desc {
fbd6a754
LB		 177 u16 byte_cnt; /* Descriptor buffer byte count */
178 u16 buf_size; /* Buffer size */
179 u32 cmd_sts; /* Descriptor command status */
180 u32 next_desc_ptr; /* Next descriptor pointer */
181 u32 buf_ptr; /* Descriptor buffer pointer */
182};
183
cc9754b3 184struct tx_desc {
fbd6a754
LB		 185 u16 byte_cnt; /* buffer byte count */
186 u16 l4i_chk; /* CPU provided TCP checksum */
187 u32 cmd_sts; /* Command/status field */
188 u32 next_desc_ptr; /* Pointer to next descriptor */
189 u32 buf_ptr; /* pointer to buffer for this descriptor*/
190};
191#elif defined(__LITTLE_ENDIAN)
cc9754b3 192struct rx_desc {
fbd6a754
LB		 193 u32 cmd_sts; /* Descriptor command status */
194 u16 buf_size; /* Buffer size */
195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 u32 next_desc_ptr; /* Next descriptor pointer */
198};
199
cc9754b3 200struct tx_desc {
fbd6a754
LB		 201 u32 cmd_sts; /* Command/status field */
202 u16 l4i_chk; /* CPU provided TCP checksum */
203 u16 byte_cnt; /* buffer byte count */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 u32 next_desc_ptr; /* Pointer to next descriptor */
206};
207#else
208#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
209#endif
210
7ca72a3b 211/* RX & TX descriptor command */
cc9754b3 212#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 213
214/* RX & TX descriptor status */
cc9754b3 215#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 216
217/* RX descriptor status */
cc9754b3
LB		 218#define LAYER_4_CHECKSUM_OK 0x40000000
219#define RX_ENABLE_INTERRUPT 0x20000000
220#define RX_FIRST_DESC 0x08000000
221#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 222
223/* TX descriptor command */
cc9754b3
LB		 224#define TX_ENABLE_INTERRUPT 0x00800000
225#define GEN_CRC 0x00400000
226#define TX_FIRST_DESC 0x00200000
227#define TX_LAST_DESC 0x00100000
228#define ZERO_PADDING 0x00080000
229#define GEN_IP_V4_CHECKSUM 0x00040000
230#define GEN_TCP_UDP_CHECKSUM 0x00020000
231#define UDP_FRAME 0x00010000
e32b6617
LB		 232#define MAC_HDR_EXTRA_4_BYTES 0x00008000
233#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 234
cc9754b3 235#define TX_IHL_SHIFT 11
7ca72a3b
LB		 236
237
c9df406f 238/* global *******************************************************************/
e5371493 239struct mv643xx_eth_shared_private {
fc32b0e2
LB		 240 /*
241 * Ethernet controller base address.
242 */
cc9754b3 243 void __iomem *base;
c9df406f 244
fc0eb9f2
LB		 245 /*
246 * Points at the right SMI instance to use.
247 */
248 struct mv643xx_eth_shared_private *smi;
249
fc32b0e2
LB		 250 /*
251 * Protects access to SMI_REG, which is shared between ports.
252 */
2b3ba0e3 253 struct mutex phy_lock;
c9df406f 254
45c5d3bc
LB		 255 /*
256 * If we have access to the error interrupt pin (which is
257 * somewhat misnamed as it not only reflects internal errors
258 * but also reflects SMI completion), use that to wait for
259 * SMI access completion instead of polling the SMI busy bit.
260 */
261 int err_interrupt;
262 wait_queue_head_t smi_busy_wait;
263
fc32b0e2
LB		 264 /*
265 * Per-port MBUS window access register value.
266 */
c9df406f
LB		 267 u32 win_protect;
268
fc32b0e2
LB		 269 /*
270 * Hardware-specific parameters.
271 */
c9df406f 272 unsigned int t_clk;
773fc3ee 273 int extended_rx_coal_limit;
1e881592 274 int tx_bw_control_moved;
c9df406f
LB		 275};
276
277
278/* per-port *****************************************************************/
e5371493 279struct mib_counters {
fbd6a754
LB		 280 u64 good_octets_received;
281 u32 bad_octets_received;
282 u32 internal_mac_transmit_err;
283 u32 good_frames_received;
284 u32 bad_frames_received;
285 u32 broadcast_frames_received;
286 u32 multicast_frames_received;
287 u32 frames_64_octets;
288 u32 frames_65_to_127_octets;
289 u32 frames_128_to_255_octets;
290 u32 frames_256_to_511_octets;
291 u32 frames_512_to_1023_octets;
292 u32 frames_1024_to_max_octets;
293 u64 good_octets_sent;
294 u32 good_frames_sent;
295 u32 excessive_collision;
296 u32 multicast_frames_sent;
297 u32 broadcast_frames_sent;
298 u32 unrec_mac_control_received;
299 u32 fc_sent;
300 u32 good_fc_received;
301 u32 bad_fc_received;
302 u32 undersize_received;
303 u32 fragments_received;
304 u32 oversize_received;
305 u32 jabber_received;
306 u32 mac_receive_error;
307 u32 bad_crc_event;
308 u32 collision;
309 u32 late_collision;
310};
311
8a578111 312struct rx_queue {
64da80a2
LB		 313 int index;
314
8a578111
LB		 315 int rx_ring_size;
316
317 int rx_desc_count;
318 int rx_curr_desc;
319 int rx_used_desc;
320
321 struct rx_desc *rx_desc_area;
322 dma_addr_t rx_desc_dma;
323 int rx_desc_area_size;
324 struct sk_buff **rx_skb;
8a578111
LB		 325};
326
13d64285 327struct tx_queue {
3d6b35bc
LB		 328 int index;
329
13d64285 330 int tx_ring_size;
fbd6a754 331
13d64285
LB		 332 int tx_desc_count;
333 int tx_curr_desc;
334 int tx_used_desc;
fbd6a754 335
5daffe94 336 struct tx_desc *tx_desc_area;
fbd6a754
LB		 337 dma_addr_t tx_desc_dma;
338 int tx_desc_area_size;
99ab08e0
LB		 339
340 struct sk_buff_head tx_skb;
8fd89211
LB		 341
342 unsigned long tx_packets;
343 unsigned long tx_bytes;
344 unsigned long tx_dropped;
13d64285
LB		 345};
346
347struct mv643xx_eth_private {
348 struct mv643xx_eth_shared_private *shared;
fc32b0e2 349 int port_num;
13d64285 350
fc32b0e2 351 struct net_device *dev;
fbd6a754 352
fc32b0e2 353 int phy_addr;
fbd6a754 354
fc32b0e2
LB		 355 struct mib_counters mib_counters;
356 struct work_struct tx_timeout_task;
fbd6a754 357 struct mii_if_info mii;
8a578111 358
1fa38c58
LB		 359 struct napi_struct napi;
360 u8 work_link;
361 u8 work_tx;
362 u8 work_tx_end;
363 u8 work_rx;
364 u8 work_rx_refill;
365 u8 work_rx_oom;
366
8a578111
LB		 367 /*
368 * RX state.
369 */
370 int default_rx_ring_size;
371 unsigned long rx_desc_sram_addr;
372 int rx_desc_sram_size;
f7981c1c 373 int rxq_count;
2257e05c 374 struct timer_list rx_oom;
64da80a2 375 struct rx_queue rxq[8];
13d64285
LB		 376
377 /*
378 * TX state.
379 */
380 int default_tx_ring_size;
381 unsigned long tx_desc_sram_addr;
382 int tx_desc_sram_size;
f7981c1c 383 int txq_count;
3d6b35bc 384 struct tx_queue txq[8];
fbd6a754 385};
1da177e4 386
fbd6a754 387
c9df406f 388/* port register accessors **************************************************/
e5371493 389static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 390{
cc9754b3 391 return readl(mp->shared->base + offset);
c9df406f 392}
fbd6a754 393
e5371493 394static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 395{
cc9754b3 396 writel(data, mp->shared->base + offset);
c9df406f 397}
fbd6a754 398
fbd6a754 399
c9df406f 400/* rxq/txq helper functions *************************************************/
8a578111 401static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 402{
64da80a2 403 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 404}
fbd6a754 405
13d64285
LB		 406static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
407{
3d6b35bc 408 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 409}
410
8a578111 411static void rxq_enable(struct rx_queue *rxq)
c9df406f 412{
8a578111 413 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 414 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
8a578111 415}
1da177e4 416
8a578111
LB		 417static void rxq_disable(struct rx_queue *rxq)
418{
419 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 420 u8 mask = 1 << rxq->index;
1da177e4 421
8a578111
LB		 422 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
423 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
424 udelay(10);
c9df406f
LB		 425}
426
6b368f68
LB		 427static void txq_reset_hw_ptr(struct tx_queue *txq)
428{
429 struct mv643xx_eth_private *mp = txq_to_mp(txq);
430 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
431 u32 addr;
432
433 addr = (u32)txq->tx_desc_dma;
434 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
435 wrl(mp, off, addr);
436}
437
13d64285 438static void txq_enable(struct tx_queue *txq)
1da177e4 439{
13d64285 440 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 441 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
1da177e4
LT		 442}
443
13d64285 444static void txq_disable(struct tx_queue *txq)
1da177e4 445{
13d64285 446 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 447 u8 mask = 1 << txq->index;
c9df406f 448
13d64285
LB		 449 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
450 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
451 udelay(10);
452}
453
1fa38c58 454static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 455{
456 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 457 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 458
8fd89211
LB		 459 if (netif_tx_queue_stopped(nq)) {
460 __netif_tx_lock(nq, smp_processor_id());
461 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
462 netif_tx_wake_queue(nq);
463 __netif_tx_unlock(nq);
464 }
1da177e4
LT		 465}
466
c9df406f 467
1fa38c58 468/* rx napi ******************************************************************/
8a578111 469static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 470{
8a578111
LB		 471 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
472 struct net_device_stats *stats = &mp->dev->stats;
473 int rx;
1da177e4 474
8a578111 475 rx = 0;
9e1f3772 476 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 477 struct rx_desc *rx_desc;
96587661 478 unsigned int cmd_sts;
fc32b0e2 479 struct sk_buff *skb;
ff561eef 480
8a578111 481 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 482
96587661 483 cmd_sts = rx_desc->cmd_sts;
2257e05c 484 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 485 break;
96587661 486 rmb();
1da177e4 487
8a578111
LB		 488 skb = rxq->rx_skb[rxq->rx_curr_desc];
489 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 490
9da78745
LB		 491 rxq->rx_curr_desc++;
492 if (rxq->rx_curr_desc == rxq->rx_ring_size)
493 rxq->rx_curr_desc = 0;
ff561eef 494
3a499481 495 dma_unmap_single(NULL, rx_desc->buf_ptr,
abe78717 496 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 497 rxq->rx_desc_count--;
498 rx++;
b1dd9ca1 499
1fa38c58
LB		 500 mp->work_rx_refill |= 1 << rxq->index;
501
468d09f8
DF		 502 /*
503 * Update statistics.
fc32b0e2
LB		 504 *
505 * Note that the descriptor byte count includes 2 dummy
506 * bytes automatically inserted by the hardware at the
507 * start of the packet (which we don't count), and a 4
508 * byte CRC at the end of the packet (which we do count).
468d09f8 509 */
1da177e4 510 stats->rx_packets++;
fc32b0e2 511 stats->rx_bytes += rx_desc->byte_cnt - 2;
96587661 512
1da177e4 513 /*
fc32b0e2
LB		 514 * In case we received a packet without first / last bits
515 * on, or the error summary bit is set, the packet needs
516 * to be dropped.
1da177e4 517 */
96587661 518 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 519 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 520 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 521 stats->rx_dropped++;
fc32b0e2 522
96587661 523 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 524 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 525 if (net_ratelimit())
fc32b0e2
LB		 526 dev_printk(KERN_ERR, &mp->dev->dev,
527 "received packet spanning "
528 "multiple descriptors\n");
1da177e4 529 }
fc32b0e2 530
96587661 531 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 532 stats->rx_errors++;
533
78fff83b 534 dev_kfree_skb(skb);
1da177e4
LT		 535 } else {
536 /*
537 * The -4 is for the CRC in the trailer of the
538 * received packet
539 */
fc32b0e2 540 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
1da177e4 541
96587661 542 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 543 skb->ip_summed = CHECKSUM_UNNECESSARY;
544 skb->csum = htons(
96587661 545 (cmd_sts & 0x0007fff8) >> 3);
1da177e4 546 }
8a578111 547 skb->protocol = eth_type_trans(skb, mp->dev);
1da177e4 548 netif_receive_skb(skb);
1da177e4 549 }
fc32b0e2 550
8a578111 551 mp->dev->last_rx = jiffies;
1da177e4 552 }
fc32b0e2 553
1fa38c58
LB		 554 if (rx < budget)
555 mp->work_rx &= ~(1 << rxq->index);
556
8a578111 557 return rx;
1da177e4
LT		 558}
559
1fa38c58 560static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 561{
1fa38c58
LB		 562 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
563 int skb_size;
564 int refilled;
8a578111 565
1fa38c58
LB		 566 /*
567 * Reserve 2+14 bytes for an ethernet header (the hardware
568 * automatically prepends 2 bytes of dummy data to each
569 * received packet), 16 bytes for up to four VLAN tags, and
570 * 4 bytes for the trailing FCS -- 36 bytes total.
571 */
572 skb_size = rxq_to_mp(rxq)->dev->mtu + 36;
d0412d96 573
1fa38c58
LB		 574 /*
575 * Make sure that the skb size is a multiple of 8 bytes, as
576 * the lower three bits of the receive descriptor's buffer
577 * size field are ignored by the hardware.
578 */
579 skb_size = (skb_size + 7) & ~7;
4dfc1c87 580
1fa38c58
LB		 581 refilled = 0;
582 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
583 struct sk_buff *skb;
584 int unaligned;
585 int rx;
d0412d96 586
1fa38c58
LB		 587 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
588 if (skb == NULL) {
589 mp->work_rx_oom |= 1 << rxq->index;
590 goto oom;
591 }
d0412d96 592
1fa38c58
LB		 593 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
594 if (unaligned)
595 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
2257e05c 596
1fa38c58
LB		 597 refilled++;
598 rxq->rx_desc_count++;
c9df406f 599
1fa38c58
LB		 600 rx = rxq->rx_used_desc++;
601 if (rxq->rx_used_desc == rxq->rx_ring_size)
602 rxq->rx_used_desc = 0;
2257e05c 603
1fa38c58
LB		 604 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
605 skb_size, DMA_FROM_DEVICE);
606 rxq->rx_desc_area[rx].buf_size = skb_size;
607 rxq->rx_skb[rx] = skb;
608 wmb();
609 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
610 RX_ENABLE_INTERRUPT;
611 wmb();
2257e05c 612
1fa38c58
LB		 613 /*
614 * The hardware automatically prepends 2 bytes of
615 * dummy data to each received packet, so that the
616 * IP header ends up 16-byte aligned.
617 */
618 skb_reserve(skb, 2);
619 }
620
621 if (refilled < budget)
622 mp->work_rx_refill &= ~(1 << rxq->index);
623
624oom:
625 return refilled;
d0412d96
JC		 626}
627
c9df406f
LB		 628
629/* tx ***********************************************************************/
c9df406f 630static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 631{
13d64285 632 int frag;
1da177e4 633
c9df406f 634 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 635 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
636 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 637 return 1;
1da177e4 638 }
13d64285 639
c9df406f
LB		 640 return 0;
641}
7303fde8 642
13d64285 643static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 644{
645 int tx_desc_curr;
d0412d96 646
13d64285 647 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 648
9da78745
LB		 649 tx_desc_curr = txq->tx_curr_desc++;
650 if (txq->tx_curr_desc == txq->tx_ring_size)
651 txq->tx_curr_desc = 0;
e4d00fa9 652
13d64285 653 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 654
c9df406f
LB		 655 return tx_desc_curr;
656}
468d09f8 657
13d64285 658static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 659{
13d64285 660 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 661 int frag;
1da177e4 662
13d64285
LB		 663 for (frag = 0; frag < nr_frags; frag++) {
664 skb_frag_t *this_frag;
665 int tx_index;
666 struct tx_desc *desc;
667
668 this_frag = &skb_shinfo(skb)->frags[frag];
669 tx_index = txq_alloc_desc_index(txq);
670 desc = &txq->tx_desc_area[tx_index];
671
672 /*
673 * The last fragment will generate an interrupt
674 * which will free the skb on TX completion.
675 */
676 if (frag == nr_frags - 1) {
677 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
678 ZERO_PADDING | TX_LAST_DESC |
679 TX_ENABLE_INTERRUPT;
13d64285
LB		 680 } else {
681 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 682 }
683
c9df406f
LB		 684 desc->l4i_chk = 0;
685 desc->byte_cnt = this_frag->size;
686 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
687 this_frag->page_offset,
688 this_frag->size,
689 DMA_TO_DEVICE);
690 }
1da177e4
LT		 691}
692
c9df406f
LB		 693static inline __be16 sum16_as_be(__sum16 sum)
694{
695 return (__force __be16)sum;
696}
1da177e4 697
13d64285 698static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 699{
8fa89bf5 700 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 701 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 702 int tx_index;
cc9754b3 703 struct tx_desc *desc;
c9df406f
LB		 704 u32 cmd_sts;
705 int length;
1da177e4 706
cc9754b3 707 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 708
13d64285
LB		 709 tx_index = txq_alloc_desc_index(txq);
710 desc = &txq->tx_desc_area[tx_index];
c9df406f
LB		 711
712 if (nr_frags) {
13d64285 713 txq_submit_frag_skb(txq, skb);
c9df406f 714 length = skb_headlen(skb);
c9df406f 715 } else {
cc9754b3 716 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f 717 length = skb->len;
c9df406f
LB		 718 }
719
720 desc->byte_cnt = length;
721 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
722
723 if (skb->ip_summed == CHECKSUM_PARTIAL) {
e32b6617
LB		 724 int mac_hdr_len;
725
726 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
727 skb->protocol != htons(ETH_P_8021Q));
c9df406f 728
cc9754b3
LB		 729 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
730 GEN_IP_V4_CHECKSUM |
731 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f 732
e32b6617
LB		 733 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
734 switch (mac_hdr_len - ETH_HLEN) {
735 case 0:
736 break;
737 case 4:
738 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
739 break;
740 case 8:
741 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
742 break;
743 case 12:
744 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
745 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
746 break;
747 default:
748 if (net_ratelimit())
749 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
750 "mac header length is %d?!\n", mac_hdr_len);
751 break;
752 }
753
c9df406f
LB		 754 switch (ip_hdr(skb)->protocol) {
755 case IPPROTO_UDP:
cc9754b3 756 cmd_sts |= UDP_FRAME;
c9df406f
LB		 757 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
758 break;
759 case IPPROTO_TCP:
760 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
761 break;
762 default:
763 BUG();
764 }
765 } else {
766 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 767 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 768 desc->l4i_chk = 0;
769 }
770
99ab08e0
LB		 771 __skb_queue_tail(&txq->tx_skb, skb);
772
c9df406f
LB		 773 /* ensure all other descriptors are written before first cmd_sts */
774 wmb();
775 desc->cmd_sts = cmd_sts;
776
1fa38c58
LB		 777 /* clear TX_END status */
778 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 779
c9df406f
LB		 780 /* ensure all descriptors are written before poking hardware */
781 wmb();
13d64285 782 txq_enable(txq);
c9df406f 783
13d64285 784 txq->tx_desc_count += nr_frags + 1;
1da177e4 785}
1da177e4 786
fc32b0e2 787static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 788{
e5371493 789 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 790 int queue;
13d64285 791 struct tx_queue *txq;
e5ef1de1 792 struct netdev_queue *nq;
e5ef1de1 793 int entries_left;
afdb57a2 794
8fd89211
LB		 795 queue = skb_get_queue_mapping(skb);
796 txq = mp->txq + queue;
797 nq = netdev_get_tx_queue(dev, queue);
798
c9df406f 799 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 800 txq->tx_dropped++;
fc32b0e2
LB		 801 dev_printk(KERN_DEBUG, &dev->dev,
802 "failed to linearize skb with tiny "
803 "unaligned fragment\n");
c9df406f
LB		 804 return NETDEV_TX_BUSY;
805 }
806
17cd0a59 807 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1
LB		 808 if (net_ratelimit())
809 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 810 kfree_skb(skb);
811 return NETDEV_TX_OK;
c9df406f
LB		 812 }
813
13d64285 814 txq_submit_skb(txq, skb);
8fd89211
LB		 815 txq->tx_bytes += skb->len;
816 txq->tx_packets++;
c9df406f
LB		 817 dev->trans_start = jiffies;
818
e5ef1de1
LB		 819 entries_left = txq->tx_ring_size - txq->tx_desc_count;
820 if (entries_left < MAX_SKB_FRAGS + 1)
821 netif_tx_stop_queue(nq);
c9df406f 822
c9df406f 823 return NETDEV_TX_OK;
1da177e4
LT		 824}
825
c9df406f 826
1fa38c58
LB		 827/* tx napi ******************************************************************/
828static void txq_kick(struct tx_queue *txq)
829{
830 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 831 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 832 u32 hw_desc_ptr;
833 u32 expected_ptr;
834
8fd89211 835 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 836
837 if (rdl(mp, TXQ_COMMAND(mp->port_num)) & (1 << txq->index))
838 goto out;
839
840 hw_desc_ptr = rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index));
841 expected_ptr = (u32)txq->tx_desc_dma +
842 txq->tx_curr_desc * sizeof(struct tx_desc);
843
844 if (hw_desc_ptr != expected_ptr)
845 txq_enable(txq);
846
847out:
8fd89211 848 __netif_tx_unlock(nq);
1fa38c58
LB		 849
850 mp->work_tx_end &= ~(1 << txq->index);
851}
852
853static int txq_reclaim(struct tx_queue *txq, int budget, int force)
854{
855 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 856 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 857 int reclaimed;
858
8fd89211 859 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 860
861 reclaimed = 0;
862 while (reclaimed < budget && txq->tx_desc_count > 0) {
863 int tx_index;
864 struct tx_desc *desc;
865 u32 cmd_sts;
866 struct sk_buff *skb;
1fa38c58
LB		 867
868 tx_index = txq->tx_used_desc;
869 desc = &txq->tx_desc_area[tx_index];
870 cmd_sts = desc->cmd_sts;
871
872 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
873 if (!force)
874 break;
875 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
876 }
877
878 txq->tx_used_desc = tx_index + 1;
879 if (txq->tx_used_desc == txq->tx_ring_size)
880 txq->tx_used_desc = 0;
881
882 reclaimed++;
883 txq->tx_desc_count--;
884
99ab08e0
LB		 885 skb = NULL;
886 if (cmd_sts & TX_LAST_DESC)
887 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 888
889 if (cmd_sts & ERROR_SUMMARY) {
890 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
891 mp->dev->stats.tx_errors++;
892 }
893
a418950c
LB		 894 if (cmd_sts & TX_FIRST_DESC) {
895 dma_unmap_single(NULL, desc->buf_ptr,
896 desc->byte_cnt, DMA_TO_DEVICE);
897 } else {
898 dma_unmap_page(NULL, desc->buf_ptr,
899 desc->byte_cnt, DMA_TO_DEVICE);
900 }
1fa38c58
LB		 901
902 if (skb)
903 dev_kfree_skb(skb);
1fa38c58
LB		 904 }
905
8fd89211
LB		 906 __netif_tx_unlock(nq);
907
1fa38c58
LB		 908 if (reclaimed < budget)
909 mp->work_tx &= ~(1 << txq->index);
910
1fa38c58
LB		 911 return reclaimed;
912}
913
914
89df5fdc
LB		 915/* tx rate control **********************************************************/
916/*
917 * Set total maximum TX rate (shared by all TX queues for this port)
918 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
919 */
920static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
921{
922 int token_rate;
923 int mtu;
924 int bucket_size;
925
926 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
927 if (token_rate > 1023)
928 token_rate = 1023;
929
930 mtu = (mp->dev->mtu + 255) >> 8;
931 if (mtu > 63)
932 mtu = 63;
933
934 bucket_size = (burst + 255) >> 8;
935 if (bucket_size > 65535)
936 bucket_size = 65535;
937
1e881592
LB		 938 if (mp->shared->tx_bw_control_moved) {
939 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
940 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
941 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
942 } else {
943 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
944 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
945 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
946 }
89df5fdc
LB		 947}
948
949static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
950{
951 struct mv643xx_eth_private *mp = txq_to_mp(txq);
952 int token_rate;
953 int bucket_size;
954
955 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
956 if (token_rate > 1023)
957 token_rate = 1023;
958
959 bucket_size = (burst + 255) >> 8;
960 if (bucket_size > 65535)
961 bucket_size = 65535;
962
3d6b35bc
LB		 963 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
964 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
89df5fdc
LB		 965 (bucket_size << 10) | token_rate);
966}
967
968static void txq_set_fixed_prio_mode(struct tx_queue *txq)
969{
970 struct mv643xx_eth_private *mp = txq_to_mp(txq);
971 int off;
972 u32 val;
973
974 /*
975 * Turn on fixed priority mode.
976 */
1e881592
LB		 977 if (mp->shared->tx_bw_control_moved)
978 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
979 else
980 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 981
982 val = rdl(mp, off);
3d6b35bc 983 val |= 1 << txq->index;
89df5fdc
LB		 984 wrl(mp, off, val);
985}
986
987static void txq_set_wrr(struct tx_queue *txq, int weight)
988{
989 struct mv643xx_eth_private *mp = txq_to_mp(txq);
990 int off;
991 u32 val;
992
993 /*
994 * Turn off fixed priority mode.
995 */
1e881592
LB		 996 if (mp->shared->tx_bw_control_moved)
997 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
998 else
999 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 1000
1001 val = rdl(mp, off);
3d6b35bc 1002 val &= ~(1 << txq->index);
89df5fdc
LB		 1003 wrl(mp, off, val);
1004
1005 /*
1006 * Configure WRR weight for this queue.
1007 */
3d6b35bc 1008 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
89df5fdc
LB		 1009
1010 val = rdl(mp, off);
1011 val = (val & ~0xff) | (weight & 0xff);
1012 wrl(mp, off, val);
1013}
1014
1015
c9df406f 1016/* mii management interface *************************************************/
45c5d3bc
LB		 1017static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1018{
1019 struct mv643xx_eth_shared_private *msp = dev_id;
1020
1021 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1022 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1023 wake_up(&msp->smi_busy_wait);
1024 return IRQ_HANDLED;
1025 }
1026
1027 return IRQ_NONE;
1028}
c9df406f 1029
45c5d3bc 1030static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1031{
45c5d3bc
LB		 1032 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1033}
1da177e4 1034
45c5d3bc
LB		 1035static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1036{
1037 if (msp->err_interrupt == NO_IRQ) {
1038 int i;
c9df406f 1039
45c5d3bc
LB		 1040 for (i = 0; !smi_is_done(msp); i++) {
1041 if (i == 10)
1042 return -ETIMEDOUT;
1043 msleep(10);
c9df406f 1044 }
45c5d3bc
LB		 1045
1046 return 0;
1047 }
1048
1049 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1050 msecs_to_jiffies(100)))
1051 return -ETIMEDOUT;
1052
1053 return 0;
1054}
1055
1056static int smi_reg_read(struct mv643xx_eth_private *mp,
1057 unsigned int addr, unsigned int reg)
1058{
fc0eb9f2 1059 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
45c5d3bc
LB		 1060 void __iomem *smi_reg = msp->base + SMI_REG;
1061 int ret;
1062
1063 mutex_lock(&msp->phy_lock);
1064
1065 if (smi_wait_ready(msp)) {
1066 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1067 ret = -ETIMEDOUT;
1068 goto out;
1da177e4
LT		 1069 }
1070
fc32b0e2 1071 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1072
45c5d3bc
LB		 1073 if (smi_wait_ready(msp)) {
1074 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1075 ret = -ETIMEDOUT;
1076 goto out;
1077 }
1078
1079 ret = readl(smi_reg);
1080 if (!(ret & SMI_READ_VALID)) {
1081 printk("%s: SMI bus read not valid\n", mp->dev->name);
1082 ret = -ENODEV;
1083 goto out;
c9df406f
LB		 1084 }
1085
45c5d3bc
LB		 1086 ret &= 0xffff;
1087
c9df406f 1088out:
45c5d3bc
LB		 1089 mutex_unlock(&msp->phy_lock);
1090
1091 return ret;
1da177e4
LT		 1092}
1093
45c5d3bc
LB		 1094static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1095 unsigned int reg, unsigned int value)
1da177e4 1096{
fc0eb9f2 1097 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
45c5d3bc 1098 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1099
45c5d3bc 1100 mutex_lock(&msp->phy_lock);
c9df406f 1101
45c5d3bc
LB		 1102 if (smi_wait_ready(msp)) {
1103 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1104 mutex_unlock(&msp->phy_lock);
1105 return -ETIMEDOUT;
1da177e4
LT		 1106 }
1107
fc32b0e2
LB		 1108 writel(SMI_OPCODE_WRITE | (reg << 21) |
1109 (addr << 16) | (value & 0xffff), smi_reg);
45c5d3bc
LB		 1110
1111 mutex_unlock(&msp->phy_lock);
1112
1113 return 0;
c9df406f 1114}
1da177e4 1115
c9df406f 1116
8fd89211
LB		 1117/* statistics ***************************************************************/
1118static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1119{
1120 struct mv643xx_eth_private *mp = netdev_priv(dev);
1121 struct net_device_stats *stats = &dev->stats;
1122 unsigned long tx_packets = 0;
1123 unsigned long tx_bytes = 0;
1124 unsigned long tx_dropped = 0;
1125 int i;
1126
1127 for (i = 0; i < mp->txq_count; i++) {
1128 struct tx_queue *txq = mp->txq + i;
1129
1130 tx_packets += txq->tx_packets;
1131 tx_bytes += txq->tx_bytes;
1132 tx_dropped += txq->tx_dropped;
1133 }
1134
1135 stats->tx_packets = tx_packets;
1136 stats->tx_bytes = tx_bytes;
1137 stats->tx_dropped = tx_dropped;
1138
1139 return stats;
1140}
1141
fc32b0e2 1142static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1143{
fc32b0e2 1144 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1145}
1146
fc32b0e2 1147static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1148{
fc32b0e2
LB		 1149 int i;
1150
1151 for (i = 0; i < 0x80; i += 4)
1152 mib_read(mp, i);
c9df406f 1153}
d0412d96 1154
fc32b0e2 1155static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1156{
e5371493 1157 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1158
fc32b0e2
LB		 1159 p->good_octets_received += mib_read(mp, 0x00);
1160 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1161 p->bad_octets_received += mib_read(mp, 0x08);
1162 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1163 p->good_frames_received += mib_read(mp, 0x10);
1164 p->bad_frames_received += mib_read(mp, 0x14);
1165 p->broadcast_frames_received += mib_read(mp, 0x18);
1166 p->multicast_frames_received += mib_read(mp, 0x1c);
1167 p->frames_64_octets += mib_read(mp, 0x20);
1168 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1169 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1170 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1171 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1172 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1173 p->good_octets_sent += mib_read(mp, 0x38);
1174 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1175 p->good_frames_sent += mib_read(mp, 0x40);
1176 p->excessive_collision += mib_read(mp, 0x44);
1177 p->multicast_frames_sent += mib_read(mp, 0x48);
1178 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1179 p->unrec_mac_control_received += mib_read(mp, 0x50);
1180 p->fc_sent += mib_read(mp, 0x54);
1181 p->good_fc_received += mib_read(mp, 0x58);
1182 p->bad_fc_received += mib_read(mp, 0x5c);
1183 p->undersize_received += mib_read(mp, 0x60);
1184 p->fragments_received += mib_read(mp, 0x64);
1185 p->oversize_received += mib_read(mp, 0x68);
1186 p->jabber_received += mib_read(mp, 0x6c);
1187 p->mac_receive_error += mib_read(mp, 0x70);
1188 p->bad_crc_event += mib_read(mp, 0x74);
1189 p->collision += mib_read(mp, 0x78);
1190 p->late_collision += mib_read(mp, 0x7c);
d0412d96
JC		 1191}
1192
c9df406f
LB		 1193
1194/* ethtool ******************************************************************/
e5371493 1195struct mv643xx_eth_stats {
c9df406f
LB		 1196 char stat_string[ETH_GSTRING_LEN];
1197 int sizeof_stat;
16820054
LB		 1198 int netdev_off;
1199 int mp_off;
c9df406f
LB		 1200};
1201
16820054
LB		 1202#define SSTAT(m) \
1203 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1204 offsetof(struct net_device, stats.m), -1 }
1205
1206#define MIBSTAT(m) \
1207 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1208 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1209
1210static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1211 SSTAT(rx_packets),
1212 SSTAT(tx_packets),
1213 SSTAT(rx_bytes),
1214 SSTAT(tx_bytes),
1215 SSTAT(rx_errors),
1216 SSTAT(tx_errors),
1217 SSTAT(rx_dropped),
1218 SSTAT(tx_dropped),
1219 MIBSTAT(good_octets_received),
1220 MIBSTAT(bad_octets_received),
1221 MIBSTAT(internal_mac_transmit_err),
1222 MIBSTAT(good_frames_received),
1223 MIBSTAT(bad_frames_received),
1224 MIBSTAT(broadcast_frames_received),
1225 MIBSTAT(multicast_frames_received),
1226 MIBSTAT(frames_64_octets),
1227 MIBSTAT(frames_65_to_127_octets),
1228 MIBSTAT(frames_128_to_255_octets),
1229 MIBSTAT(frames_256_to_511_octets),
1230 MIBSTAT(frames_512_to_1023_octets),
1231 MIBSTAT(frames_1024_to_max_octets),
1232 MIBSTAT(good_octets_sent),
1233 MIBSTAT(good_frames_sent),
1234 MIBSTAT(excessive_collision),
1235 MIBSTAT(multicast_frames_sent),
1236 MIBSTAT(broadcast_frames_sent),
1237 MIBSTAT(unrec_mac_control_received),
1238 MIBSTAT(fc_sent),
1239 MIBSTAT(good_fc_received),
1240 MIBSTAT(bad_fc_received),
1241 MIBSTAT(undersize_received),
1242 MIBSTAT(fragments_received),
1243 MIBSTAT(oversize_received),
1244 MIBSTAT(jabber_received),
1245 MIBSTAT(mac_receive_error),
1246 MIBSTAT(bad_crc_event),
1247 MIBSTAT(collision),
1248 MIBSTAT(late_collision),
c9df406f
LB		 1249};
1250
e5371493 1251static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1252{
e5371493 1253 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1254 int err;
1255
d0412d96 1256 err = mii_ethtool_gset(&mp->mii, cmd);
d0412d96 1257
fc32b0e2
LB		 1258 /*
1259 * The MAC does not support 1000baseT_Half.
1260 */
d0412d96
JC		 1261 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1262 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1263
1264 return err;
1265}
1266
bedfe324
LB		 1267static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1268{
81600eea
LB		 1269 struct mv643xx_eth_private *mp = netdev_priv(dev);
1270 u32 port_status;
1271
1272 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1273
bedfe324
LB		 1274 cmd->supported = SUPPORTED_MII;
1275 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1276 switch (port_status & PORT_SPEED_MASK) {
1277 case PORT_SPEED_10:
1278 cmd->speed = SPEED_10;
1279 break;
1280 case PORT_SPEED_100:
1281 cmd->speed = SPEED_100;
1282 break;
1283 case PORT_SPEED_1000:
1284 cmd->speed = SPEED_1000;
1285 break;
1286 default:
1287 cmd->speed = -1;
1288 break;
1289 }
1290 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1291 cmd->port = PORT_MII;
1292 cmd->phy_address = 0;
1293 cmd->transceiver = XCVR_INTERNAL;
1294 cmd->autoneg = AUTONEG_DISABLE;
1295 cmd->maxtxpkt = 1;
1296 cmd->maxrxpkt = 1;
1297
1298 return 0;
1299}
1300
e5371493 1301static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1302{
e5371493 1303 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1304
fc32b0e2
LB		 1305 /*
1306 * The MAC does not support 1000baseT_Half.
1307 */
1308 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1309
2b3ba0e3 1310 return mii_ethtool_sset(&mp->mii, cmd);
c9df406f 1311}
1da177e4 1312
bedfe324
LB		 1313static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1314{
1315 return -EINVAL;
1316}
1317
fc32b0e2
LB		 1318static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1319 struct ethtool_drvinfo *drvinfo)
c9df406f 1320{
e5371493
LB		 1321 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1322 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1323 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1324 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1325 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1326}
1da177e4 1327
fc32b0e2 1328static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1329{
e5371493 1330 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1331
c9df406f
LB		 1332 return mii_nway_restart(&mp->mii);
1333}
1da177e4 1334
bedfe324
LB		 1335static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1336{
1337 return -EINVAL;
1338}
1339
c9df406f
LB		 1340static u32 mv643xx_eth_get_link(struct net_device *dev)
1341{
e5371493 1342 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1343
c9df406f
LB		 1344 return mii_link_ok(&mp->mii);
1345}
1da177e4 1346
bedfe324
LB		 1347static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1348{
1349 return 1;
1350}
1351
fc32b0e2
LB		 1352static void mv643xx_eth_get_strings(struct net_device *dev,
1353 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1354{
1355 int i;
1da177e4 1356
fc32b0e2
LB		 1357 if (stringset == ETH_SS_STATS) {
1358 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1359 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1360 mv643xx_eth_stats[i].stat_string,
e5371493 1361 ETH_GSTRING_LEN);
c9df406f 1362 }
c9df406f
LB		 1363 }
1364}
1da177e4 1365
fc32b0e2
LB		 1366static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1367 struct ethtool_stats *stats,
1368 uint64_t *data)
c9df406f 1369{
b9873841 1370 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1371 int i;
1da177e4 1372
8fd89211 1373 mv643xx_eth_get_stats(dev);
fc32b0e2 1374 mib_counters_update(mp);
1da177e4 1375
16820054
LB		 1376 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1377 const struct mv643xx_eth_stats *stat;
1378 void *p;
1379
1380 stat = mv643xx_eth_stats + i;
1381
1382 if (stat->netdev_off >= 0)
1383 p = ((void *)mp->dev) + stat->netdev_off;
1384 else
1385 p = ((void *)mp) + stat->mp_off;
1386
1387 data[i] = (stat->sizeof_stat == 8) ?
1388 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1389 }
c9df406f 1390}
1da177e4 1391
fc32b0e2 1392static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1393{
fc32b0e2 1394 if (sset == ETH_SS_STATS)
16820054 1395 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1396
1397 return -EOPNOTSUPP;
c9df406f 1398}
1da177e4 1399
e5371493 1400static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1401 .get_settings = mv643xx_eth_get_settings,
1402 .set_settings = mv643xx_eth_set_settings,
1403 .get_drvinfo = mv643xx_eth_get_drvinfo,
1404 .nway_reset = mv643xx_eth_nway_reset,
1405 .get_link = mv643xx_eth_get_link,
c9df406f 1406 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1407 .get_strings = mv643xx_eth_get_strings,
1408 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1409 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1410};
1da177e4 1411
bedfe324
LB		 1412static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1413 .get_settings = mv643xx_eth_get_settings_phyless,
1414 .set_settings = mv643xx_eth_set_settings_phyless,
1415 .get_drvinfo = mv643xx_eth_get_drvinfo,
1416 .nway_reset = mv643xx_eth_nway_reset_phyless,
1417 .get_link = mv643xx_eth_get_link_phyless,
1418 .set_sg = ethtool_op_set_sg,
1419 .get_strings = mv643xx_eth_get_strings,
1420 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1421 .get_sset_count = mv643xx_eth_get_sset_count,
1422};
1423
bea3348e 1424
c9df406f 1425/* address handling *********************************************************/
5daffe94 1426static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1427{
c9df406f
LB		 1428 unsigned int mac_h;
1429 unsigned int mac_l;
1da177e4 1430
fc32b0e2
LB		 1431 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1432 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1433
5daffe94
LB		 1434 addr[0] = (mac_h >> 24) & 0xff;
1435 addr[1] = (mac_h >> 16) & 0xff;
1436 addr[2] = (mac_h >> 8) & 0xff;
1437 addr[3] = mac_h & 0xff;
1438 addr[4] = (mac_l >> 8) & 0xff;
1439 addr[5] = mac_l & 0xff;
c9df406f 1440}
1da177e4 1441
e5371493 1442static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1443{
fc32b0e2 1444 int i;
1da177e4 1445
fc32b0e2
LB		 1446 for (i = 0; i < 0x100; i += 4) {
1447 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1448 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1449 }
fc32b0e2
LB		 1450
1451 for (i = 0; i < 0x10; i += 4)
1452 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1453}
d0412d96 1454
e5371493 1455static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1456 int table, unsigned char entry)
c9df406f
LB		 1457{
1458 unsigned int table_reg;
ab4384a6 1459
c9df406f 1460 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1461 table_reg = rdl(mp, table + (entry & 0xfc));
1462 table_reg |= 0x01 << (8 * (entry & 3));
1463 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1464}
1465
5daffe94 1466static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1467{
c9df406f
LB		 1468 unsigned int mac_h;
1469 unsigned int mac_l;
1470 int table;
1da177e4 1471
fc32b0e2
LB		 1472 mac_l = (addr[4] << 8) | addr[5];
1473 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1474
fc32b0e2
LB		 1475 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1476 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1477
fc32b0e2 1478 table = UNICAST_TABLE(mp->port_num);
5daffe94 1479 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1480}
1481
fc32b0e2 1482static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1483{
e5371493 1484 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1485
fc32b0e2
LB		 1486 /* +2 is for the offset of the HW addr type */
1487 memcpy(dev->dev_addr, addr + 2, 6);
1488
cc9754b3
LB		 1489 init_mac_tables(mp);
1490 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1491
1492 return 0;
1493}
1494
69876569
LB		 1495static int addr_crc(unsigned char *addr)
1496{
1497 int crc = 0;
1498 int i;
1499
1500 for (i = 0; i < 6; i++) {
1501 int j;
1502
1503 crc = (crc ^ addr[i]) << 8;
1504 for (j = 7; j >= 0; j--) {
1505 if (crc & (0x100 << j))
1506 crc ^= 0x107 << j;
1507 }
1508 }
1509
1510 return crc;
1511}
1512
fc32b0e2 1513static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1514{
fc32b0e2
LB		 1515 struct mv643xx_eth_private *mp = netdev_priv(dev);
1516 u32 port_config;
1517 struct dev_addr_list *addr;
1518 int i;
c8aaea25 1519
fc32b0e2
LB		 1520 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1521 if (dev->flags & IFF_PROMISC)
1522 port_config |= UNICAST_PROMISCUOUS_MODE;
1523 else
1524 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1525 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1526
fc32b0e2
LB		 1527 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1528 int port_num = mp->port_num;
1529 u32 accept = 0x01010101;
c8aaea25 1530
fc32b0e2
LB		 1531 for (i = 0; i < 0x100; i += 4) {
1532 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1533 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1534 }
1535 return;
1536 }
c8aaea25 1537
fc32b0e2
LB		 1538 for (i = 0; i < 0x100; i += 4) {
1539 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1540 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1541 }
1542
fc32b0e2
LB		 1543 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1544 u8 *a = addr->da_addr;
1545 int table;
324ff2c1 1546
fc32b0e2
LB		 1547 if (addr->da_addrlen != 6)
1548 continue;
1da177e4 1549
fc32b0e2
LB		 1550 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1551 table = SPECIAL_MCAST_TABLE(mp->port_num);
1552 set_filter_table_entry(mp, table, a[5]);
1553 } else {
1554 int crc = addr_crc(a);
1da177e4 1555
fc32b0e2
LB		 1556 table = OTHER_MCAST_TABLE(mp->port_num);
1557 set_filter_table_entry(mp, table, crc);
1558 }
1559 }
c9df406f 1560}
c8aaea25 1561
c8aaea25 1562
c9df406f 1563/* rx/tx queue initialisation ***********************************************/
64da80a2 1564static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1565{
64da80a2 1566 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1567 struct rx_desc *rx_desc;
1568 int size;
c9df406f
LB		 1569 int i;
1570
64da80a2
LB		 1571 rxq->index = index;
1572
8a578111
LB		 1573 rxq->rx_ring_size = mp->default_rx_ring_size;
1574
1575 rxq->rx_desc_count = 0;
1576 rxq->rx_curr_desc = 0;
1577 rxq->rx_used_desc = 0;
1578
1579 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1580
f7981c1c 1581 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1582 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1583 mp->rx_desc_sram_size);
1584 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1585 } else {
1586 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1587 &rxq->rx_desc_dma,
1588 GFP_KERNEL);
f7ea3337
PJ		 1589 }
1590
8a578111
LB		 1591 if (rxq->rx_desc_area == NULL) {
1592 dev_printk(KERN_ERR, &mp->dev->dev,
1593 "can't allocate rx ring (%d bytes)\n", size);
1594 goto out;
1595 }
1596 memset(rxq->rx_desc_area, 0, size);
1da177e4 1597
8a578111
LB		 1598 rxq->rx_desc_area_size = size;
1599 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1600 GFP_KERNEL);
1601 if (rxq->rx_skb == NULL) {
1602 dev_printk(KERN_ERR, &mp->dev->dev,
1603 "can't allocate rx skb ring\n");
1604 goto out_free;
1605 }
1606
1607 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1608 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1609 int nexti;
1610
1611 nexti = i + 1;
1612 if (nexti == rxq->rx_ring_size)
1613 nexti = 0;
1614
8a578111
LB		 1615 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1616 nexti * sizeof(struct rx_desc);
1617 }
1618
8a578111
LB		 1619 return 0;
1620
1621
1622out_free:
f7981c1c 1623 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1624 iounmap(rxq->rx_desc_area);
1625 else
1626 dma_free_coherent(NULL, size,
1627 rxq->rx_desc_area,
1628 rxq->rx_desc_dma);
1629
1630out:
1631 return -ENOMEM;
c9df406f 1632}
c8aaea25 1633
8a578111 1634static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1635{
8a578111
LB		 1636 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1637 int i;
1638
1639 rxq_disable(rxq);
c8aaea25 1640
8a578111
LB		 1641 for (i = 0; i < rxq->rx_ring_size; i++) {
1642 if (rxq->rx_skb[i]) {
1643 dev_kfree_skb(rxq->rx_skb[i]);
1644 rxq->rx_desc_count--;
1da177e4 1645 }
c8aaea25 1646 }
1da177e4 1647
8a578111
LB		 1648 if (rxq->rx_desc_count) {
1649 dev_printk(KERN_ERR, &mp->dev->dev,
1650 "error freeing rx ring -- %d skbs stuck\n",
1651 rxq->rx_desc_count);
1652 }
1653
f7981c1c 1654 if (rxq->index == 0 &&
64da80a2 1655 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1656 iounmap(rxq->rx_desc_area);
c9df406f 1657 else
8a578111
LB		 1658 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1659 rxq->rx_desc_area, rxq->rx_desc_dma);
1660
1661 kfree(rxq->rx_skb);
c9df406f 1662}
1da177e4 1663
3d6b35bc 1664static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1665{
3d6b35bc 1666 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1667 struct tx_desc *tx_desc;
1668 int size;
c9df406f 1669 int i;
1da177e4 1670
3d6b35bc
LB		 1671 txq->index = index;
1672
13d64285
LB		 1673 txq->tx_ring_size = mp->default_tx_ring_size;
1674
1675 txq->tx_desc_count = 0;
1676 txq->tx_curr_desc = 0;
1677 txq->tx_used_desc = 0;
1678
1679 size = txq->tx_ring_size * sizeof(struct tx_desc);
1680
f7981c1c 1681 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1682 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1683 mp->tx_desc_sram_size);
1684 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1685 } else {
1686 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1687 &txq->tx_desc_dma,
1688 GFP_KERNEL);
1689 }
1690
1691 if (txq->tx_desc_area == NULL) {
1692 dev_printk(KERN_ERR, &mp->dev->dev,
1693 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 1694 return -ENOMEM;
c9df406f 1695 }
13d64285
LB		 1696 memset(txq->tx_desc_area, 0, size);
1697
1698 txq->tx_desc_area_size = size;
13d64285
LB		 1699
1700 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1701 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1702 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1703 int nexti;
1704
1705 nexti = i + 1;
1706 if (nexti == txq->tx_ring_size)
1707 nexti = 0;
6b368f68
LB		 1708
1709 txd->cmd_sts = 0;
1710 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1711 nexti * sizeof(struct tx_desc);
1712 }
1713
99ab08e0 1714 skb_queue_head_init(&txq->tx_skb);
c9df406f 1715
99ab08e0 1716 return 0;
c8aaea25 1717}
1da177e4 1718
13d64285 1719static void txq_deinit(struct tx_queue *txq)
c9df406f 1720{
13d64285 1721 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1722
13d64285 1723 txq_disable(txq);
1fa38c58 1724 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 1725
13d64285 1726 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1727
f7981c1c 1728 if (txq->index == 0 &&
3d6b35bc 1729 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1730 iounmap(txq->tx_desc_area);
c9df406f 1731 else
13d64285
LB		 1732 dma_free_coherent(NULL, txq->tx_desc_area_size,
1733 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 1734}
1da177e4 1735
1da177e4 1736
c9df406f 1737/* netdev ops and related ***************************************************/
1fa38c58
LB		 1738static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1739{
1740 u32 int_cause;
1741 u32 int_cause_ext;
1742
1743 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1744 (INT_TX_END | INT_RX | INT_EXT);
1745 if (int_cause == 0)
1746 return 0;
1747
1748 int_cause_ext = 0;
1749 if (int_cause & INT_EXT)
1750 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num));
1751
1752 int_cause &= INT_TX_END | INT_RX;
1753 if (int_cause) {
1754 wrl(mp, INT_CAUSE(mp->port_num), ~int_cause);
1755 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1756 ~(rdl(mp, TXQ_COMMAND(mp->port_num)) & 0xff);
1757 mp->work_rx |= (int_cause & INT_RX) >> 2;
1758 }
1759
1760 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1761 if (int_cause_ext) {
1762 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1763 if (int_cause_ext & INT_EXT_LINK_PHY)
1764 mp->work_link = 1;
1765 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1766 }
1767
1768 return 1;
1769}
1770
1771static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1772{
1773 struct net_device *dev = (struct net_device *)dev_id;
1774 struct mv643xx_eth_private *mp = netdev_priv(dev);
1775
1776 if (unlikely(!mv643xx_eth_collect_events(mp)))
1777 return IRQ_NONE;
1778
1779 wrl(mp, INT_MASK(mp->port_num), 0);
1780 napi_schedule(&mp->napi);
1781
1782 return IRQ_HANDLED;
1783}
1784
2f7eb47a
LB		 1785static void handle_link_event(struct mv643xx_eth_private *mp)
1786{
1787 struct net_device *dev = mp->dev;
1788 u32 port_status;
1789 int speed;
1790 int duplex;
1791 int fc;
1792
1793 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1794 if (!(port_status & LINK_UP)) {
1795 if (netif_carrier_ok(dev)) {
1796 int i;
1797
1798 printk(KERN_INFO "%s: link down\n", dev->name);
1799
1800 netif_carrier_off(dev);
2f7eb47a 1801
f7981c1c 1802 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 1803 struct tx_queue *txq = mp->txq + i;
1804
1fa38c58 1805 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 1806 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 1807 }
1808 }
1809 return;
1810 }
1811
1812 switch (port_status & PORT_SPEED_MASK) {
1813 case PORT_SPEED_10:
1814 speed = 10;
1815 break;
1816 case PORT_SPEED_100:
1817 speed = 100;
1818 break;
1819 case PORT_SPEED_1000:
1820 speed = 1000;
1821 break;
1822 default:
1823 speed = -1;
1824 break;
1825 }
1826 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1827 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1828
1829 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1830 "flow control %sabled\n", dev->name,
1831 speed, duplex ? "full" : "half",
1832 fc ? "en" : "dis");
1833
4fdeca3f 1834 if (!netif_carrier_ok(dev))
2f7eb47a 1835 netif_carrier_on(dev);
2f7eb47a
LB		 1836}
1837
1fa38c58 1838static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 1839{
1fa38c58
LB		 1840 struct mv643xx_eth_private *mp;
1841 int work_done;
ce4e2e45 1842
1fa38c58 1843 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 1844
1fa38c58
LB		 1845 mp->work_rx_refill |= mp->work_rx_oom;
1846 mp->work_rx_oom = 0;
1da177e4 1847
1fa38c58
LB		 1848 work_done = 0;
1849 while (work_done < budget) {
1850 u8 queue_mask;
1851 int queue;
1852 int work_tbd;
1853
1854 if (mp->work_link) {
1855 mp->work_link = 0;
1856 handle_link_event(mp);
1857 continue;
1858 }
1da177e4 1859
1fa38c58
LB		 1860 queue_mask = mp->work_tx | mp->work_tx_end |
1861 mp->work_rx | mp->work_rx_refill;
1862 if (!queue_mask) {
1863 if (mv643xx_eth_collect_events(mp))
1864 continue;
1865 break;
1866 }
1da177e4 1867
1fa38c58
LB		 1868 queue = fls(queue_mask) - 1;
1869 queue_mask = 1 << queue;
1870
1871 work_tbd = budget - work_done;
1872 if (work_tbd > 16)
1873 work_tbd = 16;
1874
1875 if (mp->work_tx_end & queue_mask) {
1876 txq_kick(mp->txq + queue);
1877 } else if (mp->work_tx & queue_mask) {
1878 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1879 txq_maybe_wake(mp->txq + queue);
1880 } else if (mp->work_rx & queue_mask) {
1881 work_done += rxq_process(mp->rxq + queue, work_tbd);
1882 } else if (mp->work_rx_refill & queue_mask) {
1883 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1884 } else {
1885 BUG();
1886 }
84dd619e 1887 }
fc32b0e2 1888
1fa38c58
LB		 1889 if (work_done < budget) {
1890 if (mp->work_rx_oom)
1891 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1892 napi_complete(napi);
1893 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
226bb6b7 1894 }
3d6b35bc 1895
1fa38c58
LB		 1896 return work_done;
1897}
8fa89bf5 1898
1fa38c58
LB		 1899static inline void oom_timer_wrapper(unsigned long data)
1900{
1901 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 1902
1fa38c58 1903 napi_schedule(&mp->napi);
1da177e4
LT		 1904}
1905
e5371493 1906static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1907{
45c5d3bc
LB		 1908 int data;
1909
1910 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1911 if (data < 0)
1912 return;
1da177e4 1913
7f106c1d 1914 data |= BMCR_RESET;
45c5d3bc
LB		 1915 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1916 return;
1da177e4 1917
c9df406f 1918 do {
45c5d3bc
LB		 1919 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1920 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 1921}
1922
fc32b0e2 1923static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1924{
d0412d96 1925 u32 pscr;
8a578111 1926 int i;
1da177e4 1927
bedfe324
LB		 1928 /*
1929 * Perform PHY reset, if there is a PHY.
1930 */
1931 if (mp->phy_addr != -1) {
1932 struct ethtool_cmd cmd;
1933
1934 mv643xx_eth_get_settings(mp->dev, &cmd);
1935 phy_reset(mp);
1936 mv643xx_eth_set_settings(mp->dev, &cmd);
1937 }
1da177e4 1938
81600eea
LB		 1939 /*
1940 * Configure basic link parameters.
1941 */
1942 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1943
1944 pscr |= SERIAL_PORT_ENABLE;
1945 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1946
1947 pscr |= DO_NOT_FORCE_LINK_FAIL;
1948 if (mp->phy_addr == -1)
1949 pscr |= FORCE_LINK_PASS;
1950 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1951
1952 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1953
13d64285
LB		 1954 /*
1955 * Configure TX path and queues.
1956 */
89df5fdc 1957 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 1958 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 1959 struct tx_queue *txq = mp->txq + i;
13d64285 1960
6b368f68 1961 txq_reset_hw_ptr(txq);
89df5fdc
LB		 1962 txq_set_rate(txq, 1000000000, 16777216);
1963 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1964 }
1965
fc32b0e2
LB		 1966 /*
1967 * Add configured unicast address to address filter table.
1968 */
1969 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1970
d9a073ea
LB		 1971 /*
1972 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1973 * frames to RX queue #0.
1974 */
8a578111 1975 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
01999873 1976
376489a2
LB		 1977 /*
1978 * Treat BPDUs as normal multicasts, and disable partition mode.
1979 */
8a578111 1980 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 1981
8a578111 1982 /*
64da80a2 1983 * Enable the receive queues.
8a578111 1984 */
f7981c1c 1985 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 1986 struct rx_queue *rxq = mp->rxq + i;
1987 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
8a578111 1988 u32 addr;
1da177e4 1989
8a578111
LB		 1990 addr = (u32)rxq->rx_desc_dma;
1991 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1992 wrl(mp, off, addr);
1da177e4 1993
8a578111
LB		 1994 rxq_enable(rxq);
1995 }
1da177e4
LT		 1996}
1997
ffd86bbe 1998static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1999{
c9df406f 2000 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 2001 u32 val;
1da177e4 2002
773fc3ee
LB		 2003 val = rdl(mp, SDMA_CONFIG(mp->port_num));
2004 if (mp->shared->extended_rx_coal_limit) {
2005 if (coal > 0xffff)
2006 coal = 0xffff;
2007 val &= ~0x023fff80;
2008 val |= (coal & 0x8000) << 10;
2009 val |= (coal & 0x7fff) << 7;
2010 } else {
2011 if (coal > 0x3fff)
2012 coal = 0x3fff;
2013 val &= ~0x003fff00;
2014 val |= (coal & 0x3fff) << 8;
2015 }
2016 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1da177e4
LT		 2017}
2018
ffd86bbe 2019static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2020{
c9df406f 2021 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 2022
fc32b0e2
LB		 2023 if (coal > 0x3fff)
2024 coal = 0x3fff;
2025 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 2026}
2027
c9df406f 2028static int mv643xx_eth_open(struct net_device *dev)
16e03018 2029{
e5371493 2030 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2031 int err;
64da80a2 2032 int i;
16e03018 2033
fc32b0e2
LB		 2034 wrl(mp, INT_CAUSE(mp->port_num), 0);
2035 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2036 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 2037
fc32b0e2 2038 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2039 IRQF_SHARED, dev->name, dev);
c9df406f 2040 if (err) {
fc32b0e2 2041 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2042 return -EAGAIN;
16e03018
DF		 2043 }
2044
fc32b0e2 2045 init_mac_tables(mp);
16e03018 2046
2257e05c
LB		 2047 napi_enable(&mp->napi);
2048
f7981c1c 2049 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2050 err = rxq_init(mp, i);
2051 if (err) {
2052 while (--i >= 0)
f7981c1c 2053 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2054 goto out;
2055 }
2056
1fa38c58 2057 rxq_refill(mp->rxq + i, INT_MAX);
2257e05c
LB		 2058 }
2059
1fa38c58 2060 if (mp->work_rx_oom) {
2257e05c
LB		 2061 mp->rx_oom.expires = jiffies + (HZ / 10);
2062 add_timer(&mp->rx_oom);
64da80a2 2063 }
8a578111 2064
f7981c1c 2065 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2066 err = txq_init(mp, i);
2067 if (err) {
2068 while (--i >= 0)
f7981c1c 2069 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2070 goto out_free;
2071 }
2072 }
16e03018 2073
2f7eb47a 2074 netif_carrier_off(dev);
2f7eb47a 2075
fc32b0e2 2076 port_start(mp);
16e03018 2077
ffd86bbe
LB		 2078 set_rx_coal(mp, 0);
2079 set_tx_coal(mp, 0);
16e03018 2080
befefe21 2081 wrl(mp, INT_MASK_EXT(mp->port_num), INT_EXT_LINK_PHY | INT_EXT_TX);
226bb6b7 2082 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
16e03018 2083
c9df406f
LB		 2084 return 0;
2085
13d64285 2086
fc32b0e2 2087out_free:
f7981c1c
LB		 2088 for (i = 0; i < mp->rxq_count; i++)
2089 rxq_deinit(mp->rxq + i);
fc32b0e2 2090out:
c9df406f
LB		 2091 free_irq(dev->irq, dev);
2092
2093 return err;
16e03018
DF		 2094}
2095
e5371493 2096static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2097{
fc32b0e2 2098 unsigned int data;
64da80a2 2099 int i;
1da177e4 2100
f7981c1c
LB		 2101 for (i = 0; i < mp->rxq_count; i++)
2102 rxq_disable(mp->rxq + i);
2103 for (i = 0; i < mp->txq_count; i++)
2104 txq_disable(mp->txq + i);
ae9ae064
LB		 2105
2106 while (1) {
2107 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2108
2109 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2110 break;
13d64285 2111 udelay(10);
ae9ae064 2112 }
1da177e4 2113
c9df406f 2114 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 2115 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2116 data &= ~(SERIAL_PORT_ENABLE |
2117 DO_NOT_FORCE_LINK_FAIL |
2118 FORCE_LINK_PASS);
2119 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 2120}
2121
c9df406f 2122static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2123{
e5371493 2124 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2125 int i;
1da177e4 2126
fc32b0e2
LB		 2127 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2128 rdl(mp, INT_MASK(mp->port_num));
1da177e4 2129
c9df406f 2130 napi_disable(&mp->napi);
78fff83b 2131
2257e05c
LB		 2132 del_timer_sync(&mp->rx_oom);
2133
c9df406f 2134 netif_carrier_off(dev);
1da177e4 2135
fc32b0e2
LB		 2136 free_irq(dev->irq, dev);
2137
cc9754b3 2138 port_reset(mp);
8fd89211 2139 mv643xx_eth_get_stats(dev);
fc32b0e2 2140 mib_counters_update(mp);
1da177e4 2141
f7981c1c
LB		 2142 for (i = 0; i < mp->rxq_count; i++)
2143 rxq_deinit(mp->rxq + i);
2144 for (i = 0; i < mp->txq_count; i++)
2145 txq_deinit(mp->txq + i);
1da177e4 2146
c9df406f 2147 return 0;
1da177e4
LT		 2148}
2149
fc32b0e2 2150static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2151{
e5371493 2152 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2153
bedfe324
LB		 2154 if (mp->phy_addr != -1)
2155 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2156
2157 return -EOPNOTSUPP;
1da177e4
LT		 2158}
2159
c9df406f 2160static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2161{
89df5fdc
LB		 2162 struct mv643xx_eth_private *mp = netdev_priv(dev);
2163
fc32b0e2 2164 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2165 return -EINVAL;
1da177e4 2166
c9df406f 2167 dev->mtu = new_mtu;
89df5fdc
LB		 2168 tx_set_rate(mp, 1000000000, 16777216);
2169
c9df406f
LB		 2170 if (!netif_running(dev))
2171 return 0;
1da177e4 2172
c9df406f
LB		 2173 /*
2174 * Stop and then re-open the interface. This will allocate RX
2175 * skbs of the new MTU.
2176 * There is a possible danger that the open will not succeed,
fc32b0e2 2177 * due to memory being full.
c9df406f
LB		 2178 */
2179 mv643xx_eth_stop(dev);
2180 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2181 dev_printk(KERN_ERR, &dev->dev,
2182 "fatal error on re-opening device after "
2183 "MTU change\n");
c9df406f
LB		 2184 }
2185
2186 return 0;
1da177e4
LT		 2187}
2188
fc32b0e2 2189static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2190{
fc32b0e2 2191 struct mv643xx_eth_private *mp;
1da177e4 2192
fc32b0e2
LB		 2193 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2194 if (netif_running(mp->dev)) {
e5ef1de1 2195 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2196 port_reset(mp);
2197 port_start(mp);
e5ef1de1 2198 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2199 }
c9df406f
LB		 2200}
2201
c9df406f 2202static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2203{
e5371493 2204 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2205
fc32b0e2 2206 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2207
c9df406f 2208 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2209}
2210
c9df406f 2211#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2212static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2213{
fc32b0e2 2214 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2215
fc32b0e2
LB		 2216 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2217 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2218
fc32b0e2 2219 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2220
f2ca60f2 2221 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2222}
c9df406f 2223#endif
9f8dd319 2224
fc32b0e2 2225static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
9f8dd319 2226{
e5371493 2227 struct mv643xx_eth_private *mp = netdev_priv(dev);
45c5d3bc 2228 return smi_reg_read(mp, addr, reg);
9f8dd319
DF		 2229}
2230
fc32b0e2 2231static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
9f8dd319 2232{
e5371493 2233 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2 2234 smi_reg_write(mp, addr, reg, val);
c9df406f 2235}
9f8dd319 2236
9f8dd319 2237
c9df406f 2238/* platform glue ************************************************************/
e5371493
LB		 2239static void
2240mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2241 struct mbus_dram_target_info *dram)
c9df406f 2242{
cc9754b3 2243 void __iomem *base = msp->base;
c9df406f
LB		 2244 u32 win_enable;
2245 u32 win_protect;
2246 int i;
9f8dd319 2247
c9df406f
LB		 2248 for (i = 0; i < 6; i++) {
2249 writel(0, base + WINDOW_BASE(i));
2250 writel(0, base + WINDOW_SIZE(i));
2251 if (i < 4)
2252 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2253 }
2254
c9df406f
LB		 2255 win_enable = 0x3f;
2256 win_protect = 0;
2257
2258 for (i = 0; i < dram->num_cs; i++) {
2259 struct mbus_dram_window *cs = dram->cs + i;
2260
2261 writel((cs->base & 0xffff0000) |
2262 (cs->mbus_attr << 8) |
2263 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2264 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2265
2266 win_enable &= ~(1 << i);
2267 win_protect |= 3 << (2 * i);
2268 }
2269
2270 writel(win_enable, base + WINDOW_BAR_ENABLE);
2271 msp->win_protect = win_protect;
9f8dd319
DF		 2272}
2273
773fc3ee
LB		 2274static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2275{
2276 /*
2277 * Check whether we have a 14-bit coal limit field in bits
2278 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2279 * SDMA config register.
2280 */
2281 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2282 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2283 msp->extended_rx_coal_limit = 1;
2284 else
2285 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2286
2287 /*
2288 * Check whether the TX rate control registers are in the
2289 * old or the new place.
2290 */
2291 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2292 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2293 msp->tx_bw_control_moved = 1;
2294 else
2295 msp->tx_bw_control_moved = 0;
773fc3ee
LB		 2296}
2297
c9df406f 2298static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2299{
e5371493 2300 static int mv643xx_eth_version_printed = 0;
c9df406f 2301 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2302 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2303 struct resource *res;
2304 int ret;
9f8dd319 2305
e5371493 2306 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2307 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2308 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2309
c9df406f
LB		 2310 ret = -EINVAL;
2311 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2312 if (res == NULL)
2313 goto out;
9f8dd319 2314
c9df406f
LB		 2315 ret = -ENOMEM;
2316 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2317 if (msp == NULL)
2318 goto out;
2319 memset(msp, 0, sizeof(*msp));
2320
cc9754b3
LB		 2321 msp->base = ioremap(res->start, res->end - res->start + 1);
2322 if (msp->base == NULL)
c9df406f
LB		 2323 goto out_free;
2324
fc0eb9f2
LB		 2325 msp->smi = msp;
2326 if (pd != NULL && pd->shared_smi != NULL)
2327 msp->smi = platform_get_drvdata(pd->shared_smi);
2328
2b3ba0e3 2329 mutex_init(&msp->phy_lock);
c9df406f 2330
45c5d3bc
LB		 2331 msp->err_interrupt = NO_IRQ;
2332 init_waitqueue_head(&msp->smi_busy_wait);
2333
2334 /*
2335 * Check whether the error interrupt is hooked up.
2336 */
2337 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2338 if (res != NULL) {
2339 int err;
2340
2341 err = request_irq(res->start, mv643xx_eth_err_irq,
2342 IRQF_SHARED, "mv643xx_eth", msp);
2343 if (!err) {
2344 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2345 msp->err_interrupt = res->start;
2346 }
2347 }
2348
c9df406f
LB		 2349 /*
2350 * (Re-)program MBUS remapping windows if we are asked to.
2351 */
2352 if (pd != NULL && pd->dram != NULL)
2353 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2354
fc32b0e2
LB		 2355 /*
2356 * Detect hardware parameters.
2357 */
2358 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2359 infer_hw_params(msp);
fc32b0e2
LB		 2360
2361 platform_set_drvdata(pdev, msp);
2362
c9df406f
LB		 2363 return 0;
2364
2365out_free:
2366 kfree(msp);
2367out:
2368 return ret;
2369}
2370
2371static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2372{
e5371493 2373 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2374
45c5d3bc
LB		 2375 if (msp->err_interrupt != NO_IRQ)
2376 free_irq(msp->err_interrupt, msp);
cc9754b3 2377 iounmap(msp->base);
c9df406f
LB		 2378 kfree(msp);
2379
2380 return 0;
9f8dd319
DF		 2381}
2382
c9df406f 2383static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2384 .probe = mv643xx_eth_shared_probe,
2385 .remove = mv643xx_eth_shared_remove,
c9df406f 2386 .driver = {
fc32b0e2 2387 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2388 .owner = THIS_MODULE,
2389 },
2390};
2391
e5371493 2392static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2393{
c9df406f 2394 int addr_shift = 5 * mp->port_num;
fc32b0e2 2395 u32 data;
1da177e4 2396
fc32b0e2
LB		 2397 data = rdl(mp, PHY_ADDR);
2398 data &= ~(0x1f << addr_shift);
2399 data |= (phy_addr & 0x1f) << addr_shift;
2400 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2401}
2402
e5371493 2403static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2404{
fc32b0e2
LB		 2405 unsigned int data;
2406
2407 data = rdl(mp, PHY_ADDR);
2408
2409 return (data >> (5 * mp->port_num)) & 0x1f;
2410}
2411
2412static void set_params(struct mv643xx_eth_private *mp,
2413 struct mv643xx_eth_platform_data *pd)
2414{
2415 struct net_device *dev = mp->dev;
2416
2417 if (is_valid_ether_addr(pd->mac_addr))
2418 memcpy(dev->dev_addr, pd->mac_addr, 6);
2419 else
2420 uc_addr_get(mp, dev->dev_addr);
2421
ac840605 2422 if (pd->phy_addr == MV643XX_ETH_PHY_NONE) {
fc32b0e2
LB		 2423 mp->phy_addr = -1;
2424 } else {
ac840605 2425 if (pd->phy_addr != MV643XX_ETH_PHY_ADDR_DEFAULT) {
fc32b0e2
LB		 2426 mp->phy_addr = pd->phy_addr & 0x3f;
2427 phy_addr_set(mp, mp->phy_addr);
2428 } else {
2429 mp->phy_addr = phy_addr_get(mp);
2430 }
2431 }
1da177e4 2432
fc32b0e2
LB		 2433 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2434 if (pd->rx_queue_size)
2435 mp->default_rx_ring_size = pd->rx_queue_size;
2436 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2437 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2438
f7981c1c 2439 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2440
fc32b0e2
LB		 2441 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2442 if (pd->tx_queue_size)
2443 mp->default_tx_ring_size = pd->tx_queue_size;
2444 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2445 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2446
f7981c1c 2447 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2448}
2449
e5371493 2450static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2451{
45c5d3bc
LB		 2452 int data;
2453 int data2;
2454
2455 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2456 if (data < 0)
2457 return -ENODEV;
2458
2459 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2460 return -ENODEV;
fc32b0e2 2461
45c5d3bc
LB		 2462 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2463 if (data2 < 0)
2464 return -ENODEV;
1da177e4 2465
7f106c1d 2466 if (((data ^ data2) & BMCR_ANENABLE) == 0)
fc32b0e2 2467 return -ENODEV;
1da177e4 2468
7f106c1d 2469 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1da177e4 2470
c9df406f 2471 return 0;
1da177e4
LT		 2472}
2473
fc32b0e2
LB		 2474static int phy_init(struct mv643xx_eth_private *mp,
2475 struct mv643xx_eth_platform_data *pd)
c28a4f89 2476{
fc32b0e2
LB		 2477 struct ethtool_cmd cmd;
2478 int err;
c28a4f89 2479
fc32b0e2
LB		 2480 err = phy_detect(mp);
2481 if (err) {
2482 dev_printk(KERN_INFO, &mp->dev->dev,
2483 "no PHY detected at addr %d\n", mp->phy_addr);
2484 return err;
2485 }
2486 phy_reset(mp);
2487
2488 mp->mii.phy_id = mp->phy_addr;
2489 mp->mii.phy_id_mask = 0x3f;
2490 mp->mii.reg_num_mask = 0x1f;
2491 mp->mii.dev = mp->dev;
2492 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2493 mp->mii.mdio_write = mv643xx_eth_mdio_write;
c28a4f89 2494
fc32b0e2 2495 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
c9df406f 2496
fc32b0e2
LB		 2497 memset(&cmd, 0, sizeof(cmd));
2498
2499 cmd.port = PORT_MII;
2500 cmd.transceiver = XCVR_INTERNAL;
2501 cmd.phy_address = mp->phy_addr;
2502 if (pd->speed == 0) {
2503 cmd.autoneg = AUTONEG_ENABLE;
2504 cmd.speed = SPEED_100;
2505 cmd.advertising = ADVERTISED_10baseT_Half |
2506 ADVERTISED_10baseT_Full |
2507 ADVERTISED_100baseT_Half |
2508 ADVERTISED_100baseT_Full;
c9df406f 2509 if (mp->mii.supports_gmii)
fc32b0e2 2510 cmd.advertising |= ADVERTISED_1000baseT_Full;
c9df406f 2511 } else {
fc32b0e2
LB		 2512 cmd.autoneg = AUTONEG_DISABLE;
2513 cmd.speed = pd->speed;
2514 cmd.duplex = pd->duplex;
c9df406f 2515 }
fc32b0e2 2516
fc32b0e2
LB		 2517 mv643xx_eth_set_settings(mp->dev, &cmd);
2518
2519 return 0;
c28a4f89
JC		 2520}
2521
81600eea
LB		 2522static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2523{
2524 u32 pscr;
2525
2526 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2527 if (pscr & SERIAL_PORT_ENABLE) {
2528 pscr &= ~SERIAL_PORT_ENABLE;
2529 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2530 }
2531
2532 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2533 if (mp->phy_addr == -1) {
2534 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2535 if (speed == SPEED_1000)
2536 pscr |= SET_GMII_SPEED_TO_1000;
2537 else if (speed == SPEED_100)
2538 pscr |= SET_MII_SPEED_TO_100;
2539
2540 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2541
2542 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2543 if (duplex == DUPLEX_FULL)
2544 pscr |= SET_FULL_DUPLEX_MODE;
2545 }
2546
2547 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2548}
2549
c9df406f 2550static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2551{
c9df406f 2552 struct mv643xx_eth_platform_data *pd;
e5371493 2553 struct mv643xx_eth_private *mp;
c9df406f 2554 struct net_device *dev;
c9df406f 2555 struct resource *res;
c9df406f 2556 DECLARE_MAC_BUF(mac);
fc32b0e2 2557 int err;
1da177e4 2558
c9df406f
LB		 2559 pd = pdev->dev.platform_data;
2560 if (pd == NULL) {
fc32b0e2
LB		 2561 dev_printk(KERN_ERR, &pdev->dev,
2562 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2563 return -ENODEV;
2564 }
1da177e4 2565
c9df406f 2566 if (pd->shared == NULL) {
fc32b0e2
LB		 2567 dev_printk(KERN_ERR, &pdev->dev,
2568 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2569 return -ENODEV;
2570 }
8f518703 2571
e5ef1de1 2572 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2573 if (!dev)
2574 return -ENOMEM;
1da177e4 2575
c9df406f 2576 mp = netdev_priv(dev);
fc32b0e2
LB		 2577 platform_set_drvdata(pdev, mp);
2578
2579 mp->shared = platform_get_drvdata(pd->shared);
2580 mp->port_num = pd->port_number;
2581
c9df406f 2582 mp->dev = dev;
78fff83b 2583
fc32b0e2 2584 set_params(mp, pd);
e5ef1de1 2585 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2 2586
fc32b0e2
LB		 2587 mib_counters_clear(mp);
2588 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2589
bedfe324
LB		 2590 if (mp->phy_addr != -1) {
2591 err = phy_init(mp, pd);
2592 if (err)
2593 goto out;
2594
2595 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2596 } else {
2597 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2598 }
81600eea 2599 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2600
2257e05c
LB		 2601 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2602
2603 init_timer(&mp->rx_oom);
2604 mp->rx_oom.data = (unsigned long)mp;
2605 mp->rx_oom.function = oom_timer_wrapper;
2606
fc32b0e2 2607
c9df406f
LB		 2608 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2609 BUG_ON(!res);
2610 dev->irq = res->start;
1da177e4 2611
8fd89211 2612 dev->get_stats = mv643xx_eth_get_stats;
fc32b0e2 2613 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2614 dev->open = mv643xx_eth_open;
2615 dev->stop = mv643xx_eth_stop;
c9df406f 2616 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2617 dev->set_mac_address = mv643xx_eth_set_mac_address;
2618 dev->do_ioctl = mv643xx_eth_ioctl;
2619 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2620 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2621#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2622 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2623#endif
c9df406f
LB		 2624 dev->watchdog_timeo = 2 * HZ;
2625 dev->base_addr = 0;
1da177e4 2626
c9df406f 2627 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2628 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2629
fc32b0e2 2630 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2631
c9df406f 2632 if (mp->shared->win_protect)
fc32b0e2 2633 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2634
c9df406f
LB		 2635 err = register_netdev(dev);
2636 if (err)
2637 goto out;
1da177e4 2638
fc32b0e2
LB		 2639 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2640 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2641
13d64285 2642 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2643 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2644
c9df406f 2645 return 0;
1da177e4 2646
c9df406f
LB		 2647out:
2648 free_netdev(dev);
1da177e4 2649
c9df406f 2650 return err;
1da177e4
LT		 2651}
2652
c9df406f 2653static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2654{
fc32b0e2 2655 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2656
fc32b0e2 2657 unregister_netdev(mp->dev);
c9df406f 2658 flush_scheduled_work();
fc32b0e2 2659 free_netdev(mp->dev);
c9df406f 2660
c9df406f 2661 platform_set_drvdata(pdev, NULL);
fc32b0e2 2662
c9df406f 2663 return 0;
1da177e4
LT		 2664}
2665
c9df406f 2666static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2667{
fc32b0e2 2668 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2669
c9df406f 2670 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2671 wrl(mp, INT_MASK(mp->port_num), 0);
2672 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2673
fc32b0e2
LB		 2674 if (netif_running(mp->dev))
2675 port_reset(mp);
d0412d96
JC		 2676}
2677
c9df406f 2678static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2679 .probe = mv643xx_eth_probe,
2680 .remove = mv643xx_eth_remove,
2681 .shutdown = mv643xx_eth_shutdown,
c9df406f 2682 .driver = {
fc32b0e2 2683 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2684 .owner = THIS_MODULE,
2685 },
2686};
2687
e5371493 2688static int __init mv643xx_eth_init_module(void)
d0412d96 2689{
c9df406f 2690 int rc;
d0412d96 2691
c9df406f
LB		 2692 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2693 if (!rc) {
2694 rc = platform_driver_register(&mv643xx_eth_driver);
2695 if (rc)
2696 platform_driver_unregister(&mv643xx_eth_shared_driver);
2697 }
fc32b0e2 2698
c9df406f 2699 return rc;
d0412d96 2700}
fc32b0e2 2701module_init(mv643xx_eth_init_module);
d0412d96 2702
e5371493 2703static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2704{
c9df406f
LB		 2705 platform_driver_unregister(&mv643xx_eth_driver);
2706 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2707}
e5371493 2708module_exit(mv643xx_eth_cleanup_module);
1da177e4 2709
45675bc6
LB		 2710MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2711 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2712MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2713MODULE_LICENSE("GPL");
c9df406f 2714MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2715MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
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