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Merge branch 'flock' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/bkl
[net-next-2.6.git] / drivers / net / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/mlx4/cmd.h>
c57e20dc 36#include <linux/cache.h>
225c7b1f
RD		 37
38#include "fw.h"
39#include "icm.h"
40
fe40900f 41enum {
5ae2a7a8
RD		 42 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
43 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
44 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 45};
46
225c7b1f
RD		 47extern void __buggy_use_of_MLX4_GET(void);
48extern void __buggy_use_of_MLX4_PUT(void);
49
51f5f0ee
JM		 50static int enable_qos;
51module_param(enable_qos, bool, 0444);
52MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
53
225c7b1f
RD		 54#define MLX4_GET(dest, source, offset) \
55 do { \
56 void *__p = (char *) (source) + (offset); \
57 switch (sizeof (dest)) { \
58 case 1: (dest) = *(u8 *) __p; break; \
59 case 2: (dest) = be16_to_cpup(__p); break; \
60 case 4: (dest) = be32_to_cpup(__p); break; \
61 case 8: (dest) = be64_to_cpup(__p); break; \
62 default: __buggy_use_of_MLX4_GET(); \
63 } \
64 } while (0)
65
66#define MLX4_PUT(dest, source, offset) \
67 do { \
68 void *__d = ((char *) (dest) + (offset)); \
69 switch (sizeof(source)) { \
70 case 1: *(u8 *) __d = (source); break; \
71 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
72 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
73 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
74 default: __buggy_use_of_MLX4_PUT(); \
75 } \
76 } while (0)
77
78static void dump_dev_cap_flags(struct mlx4_dev *dev, u32 flags)
79{
80 static const char *fname[] = {
81 [ 0] = "RC transport",
82 [ 1] = "UC transport",
83 [ 2] = "UD transport",
ea98054f 84 [ 3] = "XRC transport",
225c7b1f
RD		 85 [ 4] = "reliable multicast",
86 [ 5] = "FCoIB support",
87 [ 6] = "SRQ support",
88 [ 7] = "IPoIB checksum offload",
89 [ 8] = "P_Key violation counter",
90 [ 9] = "Q_Key violation counter",
91 [10] = "VMM",
7ff93f8b 92 [12] = "DPDP",
417608c2 93 [15] = "Big LSO headers",
225c7b1f
RD		 94 [16] = "MW support",
95 [17] = "APM support",
96 [18] = "Atomic ops support",
97 [19] = "Raw multicast support",
98 [20] = "Address vector port checking support",
99 [21] = "UD multicast support",
100 [24] = "Demand paging support",
96dfa684
EC		 101 [25] = "Router support",
102 [30] = "IBoE support"
225c7b1f
RD		 103 };
104 int i;
105
106 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 107 for (i = 0; i < ARRAY_SIZE(fname); ++i)
225c7b1f
RD		 108 if (fname[i] && (flags & (1 << i)))
109 mlx4_dbg(dev, " %s\n", fname[i]);
110}
111
2d928651
VS		 112int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
113{
114 struct mlx4_cmd_mailbox *mailbox;
115 u32 *inbox;
116 int err = 0;
117
118#define MOD_STAT_CFG_IN_SIZE 0x100
119
120#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
121#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
122
123 mailbox = mlx4_alloc_cmd_mailbox(dev);
124 if (IS_ERR(mailbox))
125 return PTR_ERR(mailbox);
126 inbox = mailbox->buf;
127
128 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
129
130 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
131 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
132
133 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
134 MLX4_CMD_TIME_CLASS_A);
135
136 mlx4_free_cmd_mailbox(dev, mailbox);
137 return err;
138}
139
225c7b1f
RD		 140int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
141{
142 struct mlx4_cmd_mailbox *mailbox;
143 u32 *outbox;
144 u8 field;
7699517d 145 u32 field32;
225c7b1f
RD		 146 u16 size;
147 u16 stat_rate;
148 int err;
5ae2a7a8 149 int i;
225c7b1f
RD		 150
151#define QUERY_DEV_CAP_OUT_SIZE 0x100
152#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
153#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
154#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
155#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
156#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
157#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
158#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
159#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
160#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
161#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
162#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
163#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
164#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
165#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
166#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
167#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
168#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
169#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
170#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
171#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
172#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 173#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
225c7b1f
RD		 174#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
175#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
176#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
177#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
178#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 179#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 180#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
181#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
182#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
0533943c 183#define QUERY_DEV_CAP_UDP_RSS_OFFSET 0x42
e7c1c2c4 184#define QUERY_DEV_CAP_ETH_UC_LOOPBACK_OFFSET 0x43
225c7b1f
RD		 185#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
186#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
187#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
188#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
189#define QUERY_DEV_CAP_BF_OFFSET 0x4c
190#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
191#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
192#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
193#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
194#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
195#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
196#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
197#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
198#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
199#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
200#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
201#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
202#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
203#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
204#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
205#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
206#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
207#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
208#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
209#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
210#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
211#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 212#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
225c7b1f
RD		 213#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
214#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
215
216 mailbox = mlx4_alloc_cmd_mailbox(dev);
217 if (IS_ERR(mailbox))
218 return PTR_ERR(mailbox);
219 outbox = mailbox->buf;
220
221 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
222 MLX4_CMD_TIME_CLASS_A);
225c7b1f
RD		 223 if (err)
224 goto out;
225
226 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
227 dev_cap->reserved_qps = 1 << (field & 0xf);
228 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
229 dev_cap->max_qps = 1 << (field & 0x1f);
230 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
231 dev_cap->reserved_srqs = 1 << (field >> 4);
232 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
233 dev_cap->max_srqs = 1 << (field & 0x1f);
234 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
235 dev_cap->max_cq_sz = 1 << field;
236 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
237 dev_cap->reserved_cqs = 1 << (field & 0xf);
238 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
239 dev_cap->max_cqs = 1 << (field & 0x1f);
240 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
241 dev_cap->max_mpts = 1 << (field & 0x3f);
242 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
be504b0b 243 dev_cap->reserved_eqs = field & 0xf;
225c7b1f 244 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 245 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 246 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
247 dev_cap->reserved_mtts = 1 << (field >> 4);
248 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
249 dev_cap->max_mrw_sz = 1 << field;
250 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
251 dev_cap->reserved_mrws = 1 << (field & 0xf);
252 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
253 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
254 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
255 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
256 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
257 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 258 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
259 field &= 0x1f;
260 if (!field)
261 dev_cap->max_gso_sz = 0;
262 else
263 dev_cap->max_gso_sz = 1 << field;
264
225c7b1f
RD		 265 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
266 dev_cap->max_rdma_global = 1 << (field & 0x3f);
267 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
268 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 269 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 270 dev_cap->num_ports = field & 0xf;
149983af
DB		 271 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
272 dev_cap->max_msg_sz = 1 << (field & 0x1f);
225c7b1f
RD		 273 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
274 dev_cap->stat_rate_support = stat_rate;
0533943c
YP		 275 MLX4_GET(field, outbox, QUERY_DEV_CAP_UDP_RSS_OFFSET);
276 dev_cap->udp_rss = field & 0x1;
e7c1c2c4
YP		 277 MLX4_GET(field, outbox, QUERY_DEV_CAP_ETH_UC_LOOPBACK_OFFSET);
278 dev_cap->loopback_support = field & 0x1;
225c7b1f
RD		 279 MLX4_GET(dev_cap->flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
280 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
281 dev_cap->reserved_uars = field >> 4;
282 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
283 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
284 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
285 dev_cap->min_page_sz = 1 << field;
286
287 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
288 if (field & 0x80) {
289 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
290 dev_cap->bf_reg_size = 1 << (field & 0x1f);
291 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
292 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
293 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
294 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
295 } else {
296 dev_cap->bf_reg_size = 0;
297 mlx4_dbg(dev, "BlueFlame not available\n");
298 }
299
300 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
301 dev_cap->max_sq_sg = field;
302 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
303 dev_cap->max_sq_desc_sz = size;
304
305 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
306 dev_cap->max_qp_per_mcg = 1 << field;
307 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
308 dev_cap->reserved_mgms = field & 0xf;
309 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
310 dev_cap->max_mcgs = 1 << field;
311 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
312 dev_cap->reserved_pds = field >> 4;
313 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
314 dev_cap->max_pds = 1 << (field & 0x3f);
315
316 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
317 dev_cap->rdmarc_entry_sz = size;
318 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
319 dev_cap->qpc_entry_sz = size;
320 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
321 dev_cap->aux_entry_sz = size;
322 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
323 dev_cap->altc_entry_sz = size;
324 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
325 dev_cap->eqc_entry_sz = size;
326 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
327 dev_cap->cqc_entry_sz = size;
328 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
329 dev_cap->srq_entry_sz = size;
330 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
331 dev_cap->cmpt_entry_sz = size;
332 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
333 dev_cap->mtt_entry_sz = size;
334 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
335 dev_cap->dmpt_entry_sz = size;
336
337 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
338 dev_cap->max_srq_sz = 1 << field;
339 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
340 dev_cap->max_qp_sz = 1 << field;
341 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
342 dev_cap->resize_srq = field & 1;
343 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
344 dev_cap->max_rq_sg = field;
345 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
346 dev_cap->max_rq_desc_sz = size;
347
348 MLX4_GET(dev_cap->bmme_flags, outbox,
349 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
350 MLX4_GET(dev_cap->reserved_lkey, outbox,
351 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
352 MLX4_GET(dev_cap->max_icm_sz, outbox,
353 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
354
5ae2a7a8
RD		 355 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
356 for (i = 1; i <= dev_cap->num_ports; ++i) {
357 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
358 dev_cap->max_vl[i] = field >> 4;
359 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 360 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 361 dev_cap->max_port_width[i] = field & 0xf;
362 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
363 dev_cap->max_gids[i] = 1 << (field & 0xf);
364 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
365 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
366 }
367 } else {
7ff93f8b 368#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 369#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 370#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 371#define QUERY_PORT_WIDTH_OFFSET 0x06
372#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 373#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 374#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 375#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 376#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
377#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
378#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 379
380 for (i = 1; i <= dev_cap->num_ports; ++i) {
381 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
382 MLX4_CMD_TIME_CLASS_B);
383 if (err)
384 goto out;
385
7ff93f8b
YP		 386 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
387 dev_cap->supported_port_types[i] = field & 3;
5ae2a7a8 388 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 389 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 390 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
391 dev_cap->max_port_width[i] = field & 0xf;
392 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
393 dev_cap->max_gids[i] = 1 << (field >> 4);
394 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
395 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
396 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 397 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
398 dev_cap->log_max_macs[i] = field & 0xf;
399 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 400 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
401 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 402 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
403 dev_cap->trans_type[i] = field32 >> 24;
404 dev_cap->vendor_oui[i] = field32 & 0xffffff;
405 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
406 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 407 }
408 }
409
95d04f07
RD		 410 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
411 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 412
413 /*
414 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
415 * we can't use any EQs whose doorbell falls on that page,
416 * even if the EQ itself isn't reserved.
417 */
418 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
419 dev_cap->reserved_eqs);
420
421 mlx4_dbg(dev, "Max ICM size %lld MB\n",
422 (unsigned long long) dev_cap->max_icm_sz >> 20);
423 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
424 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
425 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
426 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
427 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
428 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
429 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
430 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
431 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
432 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
433 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
434 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
435 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
436 dev_cap->max_pds, dev_cap->reserved_mgms);
437 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
438 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
439 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 440 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 441 dev_cap->max_port_width[1]);
225c7b1f
RD		 442 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
443 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
444 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
445 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 446 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
225c7b1f
RD		 447
448 dump_dev_cap_flags(dev, dev_cap->flags);
449
450out:
451 mlx4_free_cmd_mailbox(dev, mailbox);
452 return err;
453}
454
455int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
456{
457 struct mlx4_cmd_mailbox *mailbox;
458 struct mlx4_icm_iter iter;
459 __be64 *pages;
460 int lg;
461 int nent = 0;
462 int i;
463 int err = 0;
464 int ts = 0, tc = 0;
465
466 mailbox = mlx4_alloc_cmd_mailbox(dev);
467 if (IS_ERR(mailbox))
468 return PTR_ERR(mailbox);
469 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
470 pages = mailbox->buf;
471
472 for (mlx4_icm_first(icm, &iter);
473 !mlx4_icm_last(&iter);
474 mlx4_icm_next(&iter)) {
475 /*
476 * We have to pass pages that are aligned to their
477 * size, so find the least significant 1 in the
478 * address or size and use that as our log2 size.
479 */
480 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
481 if (lg < MLX4_ICM_PAGE_SHIFT) {
482 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
483 MLX4_ICM_PAGE_SIZE,
484 (unsigned long long) mlx4_icm_addr(&iter),
485 mlx4_icm_size(&iter));
486 err = -EINVAL;
487 goto out;
488 }
489
490 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
491 if (virt != -1) {
492 pages[nent * 2] = cpu_to_be64(virt);
493 virt += 1 << lg;
494 }
495
496 pages[nent * 2 + 1] =
497 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
498 (lg - MLX4_ICM_PAGE_SHIFT));
499 ts += 1 << (lg - 10);
500 ++tc;
501
502 if (++nent == MLX4_MAILBOX_SIZE / 16) {
503 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
504 MLX4_CMD_TIME_CLASS_B);
505 if (err)
506 goto out;
507 nent = 0;
508 }
509 }
510 }
511
512 if (nent)
513 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
514 if (err)
515 goto out;
516
517 switch (op) {
518 case MLX4_CMD_MAP_FA:
519 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
520 break;
521 case MLX4_CMD_MAP_ICM_AUX:
522 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
523 break;
524 case MLX4_CMD_MAP_ICM:
525 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
526 tc, ts, (unsigned long long) virt - (ts << 10));
527 break;
528 }
529
530out:
531 mlx4_free_cmd_mailbox(dev, mailbox);
532 return err;
533}
534
535int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
536{
537 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
538}
539
540int mlx4_UNMAP_FA(struct mlx4_dev *dev)
541{
542 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
543}
544
545
546int mlx4_RUN_FW(struct mlx4_dev *dev)
547{
548 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
549}
550
551int mlx4_QUERY_FW(struct mlx4_dev *dev)
552{
553 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
554 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
555 struct mlx4_cmd_mailbox *mailbox;
556 u32 *outbox;
557 int err = 0;
558 u64 fw_ver;
fe40900f 559 u16 cmd_if_rev;
225c7b1f
RD		 560 u8 lg;
561
562#define QUERY_FW_OUT_SIZE 0x100
563#define QUERY_FW_VER_OFFSET 0x00
fe40900f 564#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 565#define QUERY_FW_MAX_CMD_OFFSET 0x0f
566#define QUERY_FW_ERR_START_OFFSET 0x30
567#define QUERY_FW_ERR_SIZE_OFFSET 0x38
568#define QUERY_FW_ERR_BAR_OFFSET 0x3c
569
570#define QUERY_FW_SIZE_OFFSET 0x00
571#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
572#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
573
574 mailbox = mlx4_alloc_cmd_mailbox(dev);
575 if (IS_ERR(mailbox))
576 return PTR_ERR(mailbox);
577 outbox = mailbox->buf;
578
579 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
580 MLX4_CMD_TIME_CLASS_A);
581 if (err)
582 goto out;
583
584 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
585 /*
3e1db334 586 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 587 * version, so swap here.
588 */
589 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
590 ((fw_ver & 0xffff0000ull) >> 16) |
591 ((fw_ver & 0x0000ffffull) << 16);
592
fe40900f 593 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 594 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
595 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
fe40900f
RD		 596 mlx4_err(dev, "Installed FW has unsupported "
597 "command interface revision %d.\n",
598 cmd_if_rev);
599 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
600 (int) (dev->caps.fw_ver >> 32),
601 (int) (dev->caps.fw_ver >> 16) & 0xffff,
602 (int) dev->caps.fw_ver & 0xffff);
5ae2a7a8
RD		 603 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
604 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 605 err = -ENODEV;
606 goto out;
607 }
608
5ae2a7a8
RD		 609 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
610 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
611
225c7b1f
RD		 612 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
613 cmd->max_cmds = 1 << lg;
614
fe40900f 615 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 616 (int) (dev->caps.fw_ver >> 32),
617 (int) (dev->caps.fw_ver >> 16) & 0xffff,
618 (int) dev->caps.fw_ver & 0xffff,
fe40900f 619 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 620
621 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
622 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
623 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
624 fw->catas_bar = (fw->catas_bar >> 6) * 2;
625
626 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
627 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
628
629 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
630 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
631 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
632 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
633
634 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
635
636 /*
637 * Round up number of system pages needed in case
638 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
639 */
640 fw->fw_pages =
641 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
642 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
643
644 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
645 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
646
647out:
648 mlx4_free_cmd_mailbox(dev, mailbox);
649 return err;
650}
651
652static void get_board_id(void *vsd, char *board_id)
653{
654 int i;
655
656#define VSD_OFFSET_SIG1 0x00
657#define VSD_OFFSET_SIG2 0xde
658#define VSD_OFFSET_MLX_BOARD_ID 0xd0
659#define VSD_OFFSET_TS_BOARD_ID 0x20
660
661#define VSD_SIGNATURE_TOPSPIN 0x5ad
662
663 memset(board_id, 0, MLX4_BOARD_ID_LEN);
664
665 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
666 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
667 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
668 } else {
669 /*
670 * The board ID is a string but the firmware byte
671 * swaps each 4-byte word before passing it back to
672 * us. Therefore we need to swab it before printing.
673 */
674 for (i = 0; i < 4; ++i)
675 ((u32 *) board_id)[i] =
676 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
677 }
678}
679
680int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
681{
682 struct mlx4_cmd_mailbox *mailbox;
683 u32 *outbox;
684 int err;
685
686#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 687#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
688#define QUERY_ADAPTER_VSD_OFFSET 0x20
689
690 mailbox = mlx4_alloc_cmd_mailbox(dev);
691 if (IS_ERR(mailbox))
692 return PTR_ERR(mailbox);
693 outbox = mailbox->buf;
694
695 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
696 MLX4_CMD_TIME_CLASS_A);
697 if (err)
698 goto out;
699
225c7b1f
RD		 700 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
701
702 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
703 adapter->board_id);
704
705out:
706 mlx4_free_cmd_mailbox(dev, mailbox);
707 return err;
708}
709
710int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
711{
712 struct mlx4_cmd_mailbox *mailbox;
713 __be32 *inbox;
714 int err;
715
716#define INIT_HCA_IN_SIZE 0x200
717#define INIT_HCA_VERSION_OFFSET 0x000
718#define INIT_HCA_VERSION 2
c57e20dc 719#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 720#define INIT_HCA_FLAGS_OFFSET 0x014
721#define INIT_HCA_QPC_OFFSET 0x020
722#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
723#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
724#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
725#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
726#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
727#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
728#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
729#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
730#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
731#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
732#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
733#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
734#define INIT_HCA_MCAST_OFFSET 0x0c0
735#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
736#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
737#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
738#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
739#define INIT_HCA_TPT_OFFSET 0x0f0
740#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
741#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
742#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
743#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
744#define INIT_HCA_UAR_OFFSET 0x120
745#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
746#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
747
748 mailbox = mlx4_alloc_cmd_mailbox(dev);
749 if (IS_ERR(mailbox))
750 return PTR_ERR(mailbox);
751 inbox = mailbox->buf;
752
753 memset(inbox, 0, INIT_HCA_IN_SIZE);
754
755 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
756
c57e20dc
EC		 757 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
758 (ilog2(cache_line_size()) - 4) << 5;
759
225c7b1f
RD		 760#if defined(__LITTLE_ENDIAN)
761 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
762#elif defined(__BIG_ENDIAN)
763 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
764#else
765#error Host endianness not defined
766#endif
767 /* Check port for UD address vector: */
768 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
769
8ff095ec
EC		 770 /* Enable IPoIB checksumming if we can: */
771 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
772 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
773
51f5f0ee
JM		 774 /* Enable QoS support if module parameter set */
775 if (enable_qos)
776 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
777
225c7b1f
RD		 778 /* QPC/EEC/CQC/EQC/RDMARC attributes */
779
780 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
781 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
782 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
783 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
784 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
785 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
786 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
787 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
788 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
789 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
790 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
791 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
792
793 /* multicast attributes */
794
795 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
796 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
797 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
798 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
799
800 /* TPT attributes */
801
802 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
803 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
804 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
805 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
806
807 /* UAR attributes */
808
809 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
810 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
811
77109cc2 812 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
225c7b1f
RD		 813
814 if (err)
815 mlx4_err(dev, "INIT_HCA returns %d\n", err);
816
817 mlx4_free_cmd_mailbox(dev, mailbox);
818 return err;
819}
820
5ae2a7a8 821int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 822{
823 struct mlx4_cmd_mailbox *mailbox;
824 u32 *inbox;
825 int err;
826 u32 flags;
5ae2a7a8 827 u16 field;
225c7b1f 828
5ae2a7a8 829 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 830#define INIT_PORT_IN_SIZE 256
831#define INIT_PORT_FLAGS_OFFSET 0x00
832#define INIT_PORT_FLAG_SIG (1 << 18)
833#define INIT_PORT_FLAG_NG (1 << 17)
834#define INIT_PORT_FLAG_G0 (1 << 16)
835#define INIT_PORT_VL_SHIFT 4
836#define INIT_PORT_PORT_WIDTH_SHIFT 8
837#define INIT_PORT_MTU_OFFSET 0x04
838#define INIT_PORT_MAX_GID_OFFSET 0x06
839#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
840#define INIT_PORT_GUID0_OFFSET 0x10
841#define INIT_PORT_NODE_GUID_OFFSET 0x18
842#define INIT_PORT_SI_GUID_OFFSET 0x20
843
5ae2a7a8
RD		 844 mailbox = mlx4_alloc_cmd_mailbox(dev);
845 if (IS_ERR(mailbox))
846 return PTR_ERR(mailbox);
847 inbox = mailbox->buf;
225c7b1f 848
5ae2a7a8 849 memset(inbox, 0, INIT_PORT_IN_SIZE);
225c7b1f 850
5ae2a7a8
RD		 851 flags = 0;
852 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
853 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
854 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 855
b79acb49 856 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 857 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
858 field = dev->caps.gid_table_len[port];
859 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
860 field = dev->caps.pkey_table_len[port];
861 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 862
5ae2a7a8
RD		 863 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
864 MLX4_CMD_TIME_CLASS_A);
225c7b1f 865
5ae2a7a8
RD		 866 mlx4_free_cmd_mailbox(dev, mailbox);
867 } else
868 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
869 MLX4_CMD_TIME_CLASS_A);
225c7b1f
RD		 870
871 return err;
872}
873EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
874
875int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
876{
877 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
878}
879EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
880
881int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
882{
883 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
884}
885
886int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
887{
888 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
889 MLX4_CMD_SET_ICM_SIZE,
890 MLX4_CMD_TIME_CLASS_A);
891 if (ret)
892 return ret;
893
894 /*
895 * Round up number of system pages needed in case
896 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
897 */
898 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
899 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
900
901 return 0;
902}
903
904int mlx4_NOP(struct mlx4_dev *dev)
905{
906 /* Input modifier of 0x1f means "finish as soon as possible." */
907 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
908}
Clone of davem's net-next-2.6 tree