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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
ee49bd93 JM |
34 | #include <linux/workqueue.h> |
35 | ||
225c7b1f RD |
36 | #include "mlx4.h" |
37 | ||
ee49bd93 JM |
38 | enum { |
39 | MLX4_CATAS_POLL_INTERVAL = 5 * HZ, | |
40 | }; | |
41 | ||
42 | static DEFINE_SPINLOCK(catas_lock); | |
43 | ||
44 | static LIST_HEAD(catas_list); | |
ee49bd93 JM |
45 | static struct work_struct catas_work; |
46 | ||
47 | static int internal_err_reset = 1; | |
48 | module_param(internal_err_reset, int, 0644); | |
49 | MODULE_PARM_DESC(internal_err_reset, | |
50 | "Reset device on internal errors if non-zero (default 1)"); | |
51 | ||
52 | static void dump_err_buf(struct mlx4_dev *dev) | |
225c7b1f RD |
53 | { |
54 | struct mlx4_priv *priv = mlx4_priv(dev); | |
55 | ||
56 | int i; | |
57 | ||
ee49bd93 | 58 | mlx4_err(dev, "Internal error detected:\n"); |
225c7b1f RD |
59 | for (i = 0; i < priv->fw.catas_size; ++i) |
60 | mlx4_err(dev, " buf[%02x]: %08x\n", | |
61 | i, swab32(readl(priv->catas_err.map + i))); | |
ee49bd93 | 62 | } |
225c7b1f | 63 | |
ee49bd93 JM |
64 | static void poll_catas(unsigned long dev_ptr) |
65 | { | |
66 | struct mlx4_dev *dev = (struct mlx4_dev *) dev_ptr; | |
67 | struct mlx4_priv *priv = mlx4_priv(dev); | |
68 | ||
69 | if (readl(priv->catas_err.map)) { | |
70 | dump_err_buf(dev); | |
71 | ||
37608eea | 72 | mlx4_dispatch_event(dev, MLX4_DEV_EVENT_CATASTROPHIC_ERROR, 0); |
ee49bd93 JM |
73 | |
74 | if (internal_err_reset) { | |
75 | spin_lock(&catas_lock); | |
76 | list_add(&priv->catas_err.list, &catas_list); | |
77 | spin_unlock(&catas_lock); | |
78 | ||
27bf91d6 | 79 | queue_work(mlx4_wq, &catas_work); |
ee49bd93 JM |
80 | } |
81 | } else | |
82 | mod_timer(&priv->catas_err.timer, | |
83 | round_jiffies(jiffies + MLX4_CATAS_POLL_INTERVAL)); | |
225c7b1f RD |
84 | } |
85 | ||
ee49bd93 JM |
86 | static void catas_reset(struct work_struct *work) |
87 | { | |
88 | struct mlx4_priv *priv, *tmppriv; | |
89 | struct mlx4_dev *dev; | |
90 | ||
91 | LIST_HEAD(tlist); | |
92 | int ret; | |
93 | ||
94 | spin_lock_irq(&catas_lock); | |
95 | list_splice_init(&catas_list, &tlist); | |
96 | spin_unlock_irq(&catas_lock); | |
97 | ||
98 | list_for_each_entry_safe(priv, tmppriv, &tlist, catas_err.list) { | |
634354d7 VG |
99 | struct pci_dev *pdev = priv->dev.pdev; |
100 | ||
ee49bd93 | 101 | ret = mlx4_restart_one(priv->dev.pdev); |
634354d7 | 102 | /* 'priv' now is not valid */ |
ee49bd93 | 103 | if (ret) |
0a645e80 JP |
104 | pr_err("mlx4 %s: Reset failed (%d)\n", |
105 | pci_name(pdev), ret); | |
634354d7 VG |
106 | else { |
107 | dev = pci_get_drvdata(pdev); | |
ee49bd93 | 108 | mlx4_dbg(dev, "Reset succeeded\n"); |
634354d7 | 109 | } |
ee49bd93 JM |
110 | } |
111 | } | |
112 | ||
113 | void mlx4_start_catas_poll(struct mlx4_dev *dev) | |
225c7b1f RD |
114 | { |
115 | struct mlx4_priv *priv = mlx4_priv(dev); | |
116 | unsigned long addr; | |
117 | ||
ee49bd93 JM |
118 | INIT_LIST_HEAD(&priv->catas_err.list); |
119 | init_timer(&priv->catas_err.timer); | |
120 | priv->catas_err.map = NULL; | |
121 | ||
225c7b1f RD |
122 | addr = pci_resource_start(dev->pdev, priv->fw.catas_bar) + |
123 | priv->fw.catas_offset; | |
124 | ||
125 | priv->catas_err.map = ioremap(addr, priv->fw.catas_size * 4); | |
ee49bd93 JM |
126 | if (!priv->catas_err.map) { |
127 | mlx4_warn(dev, "Failed to map internal error buffer at 0x%lx\n", | |
225c7b1f | 128 | addr); |
ee49bd93 JM |
129 | return; |
130 | } | |
225c7b1f | 131 | |
ee49bd93 JM |
132 | priv->catas_err.timer.data = (unsigned long) dev; |
133 | priv->catas_err.timer.function = poll_catas; | |
134 | priv->catas_err.timer.expires = | |
135 | round_jiffies(jiffies + MLX4_CATAS_POLL_INTERVAL); | |
136 | add_timer(&priv->catas_err.timer); | |
225c7b1f RD |
137 | } |
138 | ||
ee49bd93 | 139 | void mlx4_stop_catas_poll(struct mlx4_dev *dev) |
225c7b1f RD |
140 | { |
141 | struct mlx4_priv *priv = mlx4_priv(dev); | |
142 | ||
ee49bd93 JM |
143 | del_timer_sync(&priv->catas_err.timer); |
144 | ||
225c7b1f RD |
145 | if (priv->catas_err.map) |
146 | iounmap(priv->catas_err.map); | |
ee49bd93 JM |
147 | |
148 | spin_lock_irq(&catas_lock); | |
149 | list_del(&priv->catas_err.list); | |
150 | spin_unlock_irq(&catas_lock); | |
151 | } | |
152 | ||
27bf91d6 | 153 | void __init mlx4_catas_init(void) |
ee49bd93 JM |
154 | { |
155 | INIT_WORK(&catas_work, catas_reset); | |
225c7b1f | 156 | } |