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92744989
GL		 1/*
2 * Driver for Xilinx TEMAC Ethernet device
3 *
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
7 *
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
10 *
11 * Notes:
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
21 *
22 * TODO:
92744989
GL		 23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/etherdevice.h>
32#include <linux/init.h>
33#include <linux/mii.h>
34#include <linux/module.h>
35#include <linux/mutex.h>
36#include <linux/netdevice.h>
37#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/of_mdio.h>
40#include <linux/of_platform.h>
9f1a1fca 41#include <linux/of_address.h>
92744989
GL		 42#include <linux/skbuff.h>
43#include <linux/spinlock.h>
44#include <linux/tcp.h> /* needed for sizeof(tcphdr) */
45#include <linux/udp.h> /* needed for sizeof(udphdr) */
46#include <linux/phy.h>
47#include <linux/in.h>
48#include <linux/io.h>
49#include <linux/ip.h>
5a0e3ad6 50#include <linux/slab.h>
92744989
GL		 51
52#include "ll_temac.h"
53
54#define TX_BD_NUM 64
55#define RX_BD_NUM 128
56
57/* ---------------------------------------------------------------------
58 * Low level register access functions
59 */
60
61u32 temac_ior(struct temac_local *lp, int offset)
62{
63 return in_be32((u32 *)(lp->regs + offset));
64}
65
66void temac_iow(struct temac_local *lp, int offset, u32 value)
67{
68 out_be32((u32 *) (lp->regs + offset), value);
69}
70
71int temac_indirect_busywait(struct temac_local *lp)
72{
73 long end = jiffies + 2;
74
75 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
76 if (end - jiffies <= 0) {
77 WARN_ON(1);
78 return -ETIMEDOUT;
79 }
80 msleep(1);
81 }
82 return 0;
83}
84
85/**
86 * temac_indirect_in32
87 *
88 * lp->indirect_mutex must be held when calling this function
89 */
90u32 temac_indirect_in32(struct temac_local *lp, int reg)
91{
92 u32 val;
93
94 if (temac_indirect_busywait(lp))
95 return -ETIMEDOUT;
96 temac_iow(lp, XTE_CTL0_OFFSET, reg);
97 if (temac_indirect_busywait(lp))
98 return -ETIMEDOUT;
99 val = temac_ior(lp, XTE_LSW0_OFFSET);
100
101 return val;
102}
103
104/**
105 * temac_indirect_out32
106 *
107 * lp->indirect_mutex must be held when calling this function
108 */
109void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
110{
111 if (temac_indirect_busywait(lp))
112 return;
113 temac_iow(lp, XTE_LSW0_OFFSET, value);
114 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
115}
116
e44171f1
JL		 117/**
118 * temac_dma_in32 - Memory mapped DMA read, this function expects a
119 * register input that is based on DCR word addresses which
120 * are then converted to memory mapped byte addresses
121 */
92744989
GL		 122static u32 temac_dma_in32(struct temac_local *lp, int reg)
123{
e44171f1 124 return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
92744989
GL		 125}
126
e44171f1
JL		 127/**
128 * temac_dma_out32 - Memory mapped DMA read, this function expects a
129 * register input that is based on DCR word addresses which
130 * are then converted to memory mapped byte addresses
131 */
92744989 132static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
e44171f1
JL		 133{
134 out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
135}
136
137/* DMA register access functions can be DCR based or memory mapped.
138 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
139 * memory mapped.
140 */
141#ifdef CONFIG_PPC_DCR
142
143/**
144 * temac_dma_dcr_in32 - DCR based DMA read
145 */
146static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
147{
148 return dcr_read(lp->sdma_dcrs, reg);
149}
150
151/**
152 * temac_dma_dcr_out32 - DCR based DMA write
153 */
154static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
92744989
GL		 155{
156 dcr_write(lp->sdma_dcrs, reg, value);
157}
158
e44171f1
JL		 159/**
160 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
161 * I/O functions
162 */
2dc11581 163static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
e44171f1
JL		 164 struct device_node *np)
165{
166 unsigned int dcrs;
167
168 /* setup the dcr address mapping if it's in the device tree */
169
170 dcrs = dcr_resource_start(np, 0);
171 if (dcrs != 0) {
172 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
173 lp->dma_in = temac_dma_dcr_in;
174 lp->dma_out = temac_dma_dcr_out;
175 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
176 return 0;
177 }
178 /* no DCR in the device tree, indicate a failure */
179 return -1;
180}
181
182#else
183
184/*
185 * temac_dcr_setup - This is a stub for when DCR is not supported,
186 * such as with MicroBlaze
187 */
2dc11581 188static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
e44171f1
JL		 189 struct device_node *np)
190{
191 return -1;
192}
193
194#endif
195
301e9d96
DK		 196/**
197 * * temac_dma_bd_release - Release buffer descriptor rings
198 */
199static void temac_dma_bd_release(struct net_device *ndev)
200{
201 struct temac_local *lp = netdev_priv(ndev);
202 int i;
203
204 for (i = 0; i < RX_BD_NUM; i++) {
205 if (!lp->rx_skb[i])
206 break;
207 else {
208 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
209 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
210 dev_kfree_skb(lp->rx_skb[i]);
211 }
212 }
213 if (lp->rx_bd_v)
214 dma_free_coherent(ndev->dev.parent,
215 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
216 lp->rx_bd_v, lp->rx_bd_p);
217 if (lp->tx_bd_v)
218 dma_free_coherent(ndev->dev.parent,
219 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
220 lp->tx_bd_v, lp->tx_bd_p);
221 if (lp->rx_skb)
222 kfree(lp->rx_skb);
223}
224
92744989
GL		 225/**
226 * temac_dma_bd_init - Setup buffer descriptor rings
227 */
228static int temac_dma_bd_init(struct net_device *ndev)
229{
230 struct temac_local *lp = netdev_priv(ndev);
231 struct sk_buff *skb;
232 int i;
233
5d66fe92 234 lp->rx_skb = kzalloc(sizeof(*lp->rx_skb) * RX_BD_NUM, GFP_KERNEL);
fe62c298
DK		 235 if (!lp->rx_skb) {
236 dev_err(&ndev->dev,
237 "can't allocate memory for DMA RX buffer\n");
238 goto out;
239 }
92744989
GL		 240 /* allocate the tx and rx ring buffer descriptors. */
241 /* returns a virtual addres and a physical address. */
242 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
243 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
244 &lp->tx_bd_p, GFP_KERNEL);
fe62c298
DK		 245 if (!lp->tx_bd_v) {
246 dev_err(&ndev->dev,
247 "unable to allocate DMA TX buffer descriptors");
248 goto out;
249 }
92744989
GL		 250 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
251 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
252 &lp->rx_bd_p, GFP_KERNEL);
fe62c298
DK		 253 if (!lp->rx_bd_v) {
254 dev_err(&ndev->dev,
255 "unable to allocate DMA RX buffer descriptors");
256 goto out;
257 }
92744989
GL		 258
259 memset(lp->tx_bd_v, 0, sizeof(*lp->tx_bd_v) * TX_BD_NUM);
260 for (i = 0; i < TX_BD_NUM; i++) {
261 lp->tx_bd_v[i].next = lp->tx_bd_p +
262 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
263 }
264
265 memset(lp->rx_bd_v, 0, sizeof(*lp->rx_bd_v) * RX_BD_NUM);
266 for (i = 0; i < RX_BD_NUM; i++) {
267 lp->rx_bd_v[i].next = lp->rx_bd_p +
268 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
269
e44171f1
JL		 270 skb = netdev_alloc_skb_ip_align(ndev,
271 XTE_MAX_JUMBO_FRAME_SIZE);
272
92744989
GL		 273 if (skb == 0) {
274 dev_err(&ndev->dev, "alloc_skb error %d\n", i);
fe62c298 275 goto out;
92744989
GL		 276 }
277 lp->rx_skb[i] = skb;
92744989
GL		 278 /* returns physical address of skb->data */
279 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
280 skb->data,
281 XTE_MAX_JUMBO_FRAME_SIZE,
282 DMA_FROM_DEVICE);
283 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
284 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
285 }
286
e44171f1 287 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
92744989
GL		 288 CHNL_CTRL_IRQ_EN |
289 CHNL_CTRL_IRQ_DLY_EN |
290 CHNL_CTRL_IRQ_COAL_EN);
291 /* 0x10220483 */
292 /* 0x00100483 */
23ecc4bd 293 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
92744989
GL		 294 CHNL_CTRL_IRQ_EN |
295 CHNL_CTRL_IRQ_DLY_EN |
296 CHNL_CTRL_IRQ_COAL_EN |
297 CHNL_CTRL_IRQ_IOE);
298 /* 0xff010283 */
299
e44171f1
JL		 300 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
301 lp->dma_out(lp, RX_TAILDESC_PTR,
92744989 302 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
e44171f1 303 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
92744989
GL		 304
305 return 0;
fe62c298
DK		 306
307out:
301e9d96 308 temac_dma_bd_release(ndev);
fe62c298 309 return -ENOMEM;
92744989
GL		 310}
311
312/* ---------------------------------------------------------------------
313 * net_device_ops
314 */
315
316static int temac_set_mac_address(struct net_device *ndev, void *address)
317{
318 struct temac_local *lp = netdev_priv(ndev);
319
320 if (address)
321 memcpy(ndev->dev_addr, address, ETH_ALEN);
322
323 if (!is_valid_ether_addr(ndev->dev_addr))
324 random_ether_addr(ndev->dev_addr);
325
326 /* set up unicast MAC address filter set its mac address */
327 mutex_lock(&lp->indirect_mutex);
328 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
329 (ndev->dev_addr[0]) |
330 (ndev->dev_addr[1] << 8) |
331 (ndev->dev_addr[2] << 16) |
332 (ndev->dev_addr[3] << 24));
333 /* There are reserved bits in EUAW1
334 * so don't affect them Set MAC bits [47:32] in EUAW1 */
335 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
336 (ndev->dev_addr[4] & 0x000000ff) |
337 (ndev->dev_addr[5] << 8));
338 mutex_unlock(&lp->indirect_mutex);
339
340 return 0;
341}
342
8ea7a37c
SM		 343static int netdev_set_mac_address(struct net_device *ndev, void *p)
344{
345 struct sockaddr *addr = p;
346
347 return temac_set_mac_address(ndev, addr->sa_data);
348}
349
92744989
GL		 350static void temac_set_multicast_list(struct net_device *ndev)
351{
352 struct temac_local *lp = netdev_priv(ndev);
353 u32 multi_addr_msw, multi_addr_lsw, val;
354 int i;
355
356 mutex_lock(&lp->indirect_mutex);
8e95a202 357 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
4cd24eaf 358 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
92744989
GL		 359 /*
360 * We must make the kernel realise we had to move
361 * into promisc mode or we start all out war on
362 * the cable. If it was a promisc request the
363 * flag is already set. If not we assert it.
364 */
365 ndev->flags |= IFF_PROMISC;
366 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
367 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
4cd24eaf 368 } else if (!netdev_mc_empty(ndev)) {
22bedad3 369 struct netdev_hw_addr *ha;
92744989 370
f9dcbcc9 371 i = 0;
22bedad3 372 netdev_for_each_mc_addr(ha, ndev) {
92744989
GL		 373 if (i >= MULTICAST_CAM_TABLE_NUM)
374 break;
22bedad3
JP		 375 multi_addr_msw = ((ha->addr[3] << 24) |
376 (ha->addr[2] << 16) |
377 (ha->addr[1] << 8) |
378 (ha->addr[0]));
92744989
GL		 379 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
380 multi_addr_msw);
22bedad3
JP		 381 multi_addr_lsw = ((ha->addr[5] << 8) |
382 (ha->addr[4]) | (i << 16));
92744989
GL		 383 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
384 multi_addr_lsw);
f9dcbcc9 385 i++;
92744989
GL		 386 }
387 } else {
388 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
389 temac_indirect_out32(lp, XTE_AFM_OFFSET,
390 val & ~XTE_AFM_EPPRM_MASK);
391 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
392 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
393 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
394 }
395 mutex_unlock(&lp->indirect_mutex);
396}
397
398struct temac_option {
399 int flg;
400 u32 opt;
401 u32 reg;
402 u32 m_or;
403 u32 m_and;
404} temac_options[] = {
405 /* Turn on jumbo packet support for both Rx and Tx */
406 {
407 .opt = XTE_OPTION_JUMBO,
408 .reg = XTE_TXC_OFFSET,
409 .m_or = XTE_TXC_TXJMBO_MASK,
410 },
411 {
412 .opt = XTE_OPTION_JUMBO,
413 .reg = XTE_RXC1_OFFSET,
414 .m_or =XTE_RXC1_RXJMBO_MASK,
415 },
416 /* Turn on VLAN packet support for both Rx and Tx */
417 {
418 .opt = XTE_OPTION_VLAN,
419 .reg = XTE_TXC_OFFSET,
420 .m_or =XTE_TXC_TXVLAN_MASK,
421 },
422 {
423 .opt = XTE_OPTION_VLAN,
424 .reg = XTE_RXC1_OFFSET,
425 .m_or =XTE_RXC1_RXVLAN_MASK,
426 },
427 /* Turn on FCS stripping on receive packets */
428 {
429 .opt = XTE_OPTION_FCS_STRIP,
430 .reg = XTE_RXC1_OFFSET,
431 .m_or =XTE_RXC1_RXFCS_MASK,
432 },
433 /* Turn on FCS insertion on transmit packets */
434 {
435 .opt = XTE_OPTION_FCS_INSERT,
436 .reg = XTE_TXC_OFFSET,
437 .m_or =XTE_TXC_TXFCS_MASK,
438 },
439 /* Turn on length/type field checking on receive packets */
440 {
441 .opt = XTE_OPTION_LENTYPE_ERR,
442 .reg = XTE_RXC1_OFFSET,
443 .m_or =XTE_RXC1_RXLT_MASK,
444 },
445 /* Turn on flow control */
446 {
447 .opt = XTE_OPTION_FLOW_CONTROL,
448 .reg = XTE_FCC_OFFSET,
449 .m_or =XTE_FCC_RXFLO_MASK,
450 },
451 /* Turn on flow control */
452 {
453 .opt = XTE_OPTION_FLOW_CONTROL,
454 .reg = XTE_FCC_OFFSET,
455 .m_or =XTE_FCC_TXFLO_MASK,
456 },
457 /* Turn on promiscuous frame filtering (all frames are received ) */
458 {
459 .opt = XTE_OPTION_PROMISC,
460 .reg = XTE_AFM_OFFSET,
461 .m_or =XTE_AFM_EPPRM_MASK,
462 },
463 /* Enable transmitter if not already enabled */
464 {
465 .opt = XTE_OPTION_TXEN,
466 .reg = XTE_TXC_OFFSET,
467 .m_or =XTE_TXC_TXEN_MASK,
468 },
469 /* Enable receiver? */
470 {
471 .opt = XTE_OPTION_RXEN,
472 .reg = XTE_RXC1_OFFSET,
473 .m_or =XTE_RXC1_RXEN_MASK,
474 },
475 {}
476};
477
478/**
479 * temac_setoptions
480 */
481static u32 temac_setoptions(struct net_device *ndev, u32 options)
482{
483 struct temac_local *lp = netdev_priv(ndev);
484 struct temac_option *tp = &temac_options[0];
485 int reg;
486
487 mutex_lock(&lp->indirect_mutex);
488 while (tp->opt) {
489 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
490 if (options & tp->opt)
491 reg |= tp->m_or;
492 temac_indirect_out32(lp, tp->reg, reg);
493 tp++;
494 }
495 lp->options |= options;
496 mutex_unlock(&lp->indirect_mutex);
497
807540ba 498 return 0;
92744989
GL		 499}
500
421f91d2 501/* Initialize temac */
92744989
GL		 502static void temac_device_reset(struct net_device *ndev)
503{
504 struct temac_local *lp = netdev_priv(ndev);
505 u32 timeout;
506 u32 val;
507
508 /* Perform a software reset */
509
510 /* 0x300 host enable bit ? */
511 /* reset PHY through control register ?:1 */
512
513 dev_dbg(&ndev->dev, "%s()\n", __func__);
514
515 mutex_lock(&lp->indirect_mutex);
516 /* Reset the receiver and wait for it to finish reset */
517 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
518 timeout = 1000;
519 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
520 udelay(1);
521 if (--timeout == 0) {
522 dev_err(&ndev->dev,
523 "temac_device_reset RX reset timeout!!\n");
524 break;
525 }
526 }
527
528 /* Reset the transmitter and wait for it to finish reset */
529 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
530 timeout = 1000;
531 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
532 udelay(1);
533 if (--timeout == 0) {
534 dev_err(&ndev->dev,
535 "temac_device_reset TX reset timeout!!\n");
536 break;
537 }
538 }
539
540 /* Disable the receiver */
541 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
542 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
543
544 /* Reset Local Link (DMA) */
e44171f1 545 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
92744989 546 timeout = 1000;
e44171f1 547 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
92744989
GL		 548 udelay(1);
549 if (--timeout == 0) {
550 dev_err(&ndev->dev,
551 "temac_device_reset DMA reset timeout!!\n");
552 break;
553 }
554 }
e44171f1 555 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
92744989 556
fe62c298
DK		 557 if (temac_dma_bd_init(ndev)) {
558 dev_err(&ndev->dev,
559 "temac_device_reset descriptor allocation failed\n");
560 }
92744989
GL		 561
562 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
563 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
564 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
565 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
566
567 mutex_unlock(&lp->indirect_mutex);
568
569 /* Sync default options with HW
570 * but leave receiver and transmitter disabled. */
571 temac_setoptions(ndev,
572 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
573
574 temac_set_mac_address(ndev, NULL);
575
576 /* Set address filter table */
577 temac_set_multicast_list(ndev);
578 if (temac_setoptions(ndev, lp->options))
579 dev_err(&ndev->dev, "Error setting TEMAC options\n");
580
581 /* Init Driver variable */
1ae5dc34 582 ndev->trans_start = jiffies; /* prevent tx timeout */
92744989
GL		 583}
584
585void temac_adjust_link(struct net_device *ndev)
586{
587 struct temac_local *lp = netdev_priv(ndev);
588 struct phy_device *phy = lp->phy_dev;
589 u32 mii_speed;
590 int link_state;
591
592 /* hash together the state values to decide if something has changed */
593 link_state = phy->speed | (phy->duplex << 1) | phy->link;
594
595 mutex_lock(&lp->indirect_mutex);
596 if (lp->last_link != link_state) {
597 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
598 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
599
600 switch (phy->speed) {
601 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
602 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
603 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
604 }
605
606 /* Write new speed setting out to TEMAC */
607 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
608 lp->last_link = link_state;
609 phy_print_status(phy);
610 }
611 mutex_unlock(&lp->indirect_mutex);
612}
613
614static void temac_start_xmit_done(struct net_device *ndev)
615{
616 struct temac_local *lp = netdev_priv(ndev);
617 struct cdmac_bd *cur_p;
618 unsigned int stat = 0;
619
620 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
621 stat = cur_p->app0;
622
623 while (stat & STS_CTRL_APP0_CMPLT) {
624 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
625 DMA_TO_DEVICE);
626 if (cur_p->app4)
627 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
628 cur_p->app0 = 0;
23ecc4bd
BH		 629 cur_p->app1 = 0;
630 cur_p->app2 = 0;
631 cur_p->app3 = 0;
632 cur_p->app4 = 0;
92744989
GL		 633
634 ndev->stats.tx_packets++;
635 ndev->stats.tx_bytes += cur_p->len;
636
637 lp->tx_bd_ci++;
638 if (lp->tx_bd_ci >= TX_BD_NUM)
639 lp->tx_bd_ci = 0;
640
641 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
642 stat = cur_p->app0;
643 }
644
645 netif_wake_queue(ndev);
646}
647
23ecc4bd
BH		 648static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
649{
650 struct cdmac_bd *cur_p;
651 int tail;
652
653 tail = lp->tx_bd_tail;
654 cur_p = &lp->tx_bd_v[tail];
655
656 do {
657 if (cur_p->app0)
658 return NETDEV_TX_BUSY;
659
660 tail++;
661 if (tail >= TX_BD_NUM)
662 tail = 0;
663
664 cur_p = &lp->tx_bd_v[tail];
665 num_frag--;
666 } while (num_frag >= 0);
667
668 return 0;
669}
670
92744989
GL		 671static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
672{
673 struct temac_local *lp = netdev_priv(ndev);
674 struct cdmac_bd *cur_p;
675 dma_addr_t start_p, tail_p;
676 int ii;
677 unsigned long num_frag;
678 skb_frag_t *frag;
679
680 num_frag = skb_shinfo(skb)->nr_frags;
681 frag = &skb_shinfo(skb)->frags[0];
682 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
683 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
684
23ecc4bd 685 if (temac_check_tx_bd_space(lp, num_frag)) {
92744989
GL		 686 if (!netif_queue_stopped(ndev)) {
687 netif_stop_queue(ndev);
688 return NETDEV_TX_BUSY;
689 }
690 return NETDEV_TX_BUSY;
691 }
692
693 cur_p->app0 = 0;
694 if (skb->ip_summed == CHECKSUM_PARTIAL) {
23ecc4bd
BH		 695 unsigned int csum_start_off = skb_transport_offset(skb);
696 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
697
698 cur_p->app0 |= 1; /* TX Checksum Enabled */
699 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
700 cur_p->app2 = 0; /* initial checksum seed */
92744989 701 }
23ecc4bd 702
92744989
GL		 703 cur_p->app0 |= STS_CTRL_APP0_SOP;
704 cur_p->len = skb_headlen(skb);
705 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len,
706 DMA_TO_DEVICE);
707 cur_p->app4 = (unsigned long)skb;
708
709 for (ii = 0; ii < num_frag; ii++) {
710 lp->tx_bd_tail++;
711 if (lp->tx_bd_tail >= TX_BD_NUM)
712 lp->tx_bd_tail = 0;
713
714 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
715 cur_p->phys = dma_map_single(ndev->dev.parent,
716 (void *)page_address(frag->page) +
717 frag->page_offset,
718 frag->size, DMA_TO_DEVICE);
719 cur_p->len = frag->size;
720 cur_p->app0 = 0;
721 frag++;
722 }
723 cur_p->app0 |= STS_CTRL_APP0_EOP;
724
725 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
726 lp->tx_bd_tail++;
727 if (lp->tx_bd_tail >= TX_BD_NUM)
728 lp->tx_bd_tail = 0;
729
730 /* Kick off the transfer */
e44171f1 731 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
92744989 732
6ed10654 733 return NETDEV_TX_OK;
92744989
GL		 734}
735
736
737static void ll_temac_recv(struct net_device *ndev)
738{
739 struct temac_local *lp = netdev_priv(ndev);
740 struct sk_buff *skb, *new_skb;
741 unsigned int bdstat;
742 struct cdmac_bd *cur_p;
743 dma_addr_t tail_p;
744 int length;
92744989
GL		 745 unsigned long flags;
746
747 spin_lock_irqsave(&lp->rx_lock, flags);
748
749 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
750 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
751
752 bdstat = cur_p->app0;
753 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
754
755 skb = lp->rx_skb[lp->rx_bd_ci];
c3b7c12c 756 length = cur_p->app4 & 0x3FFF;
92744989 757
33646d7f 758 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
92744989
GL		 759 DMA_FROM_DEVICE);
760
761 skb_put(skb, length);
762 skb->dev = ndev;
763 skb->protocol = eth_type_trans(skb, ndev);
bc8acf2c 764 skb_checksum_none_assert(skb);
92744989 765
23ecc4bd
BH		 766 /* if we're doing rx csum offload, set it up */
767 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
768 (skb->protocol == __constant_htons(ETH_P_IP)) &&
769 (skb->len > 64)) {
770
771 skb->csum = cur_p->app3 & 0xFFFF;
772 skb->ip_summed = CHECKSUM_COMPLETE;
773 }
774
92744989
GL		 775 netif_rx(skb);
776
777 ndev->stats.rx_packets++;
778 ndev->stats.rx_bytes += length;
779
e44171f1
JL		 780 new_skb = netdev_alloc_skb_ip_align(ndev,
781 XTE_MAX_JUMBO_FRAME_SIZE);
782
92744989
GL		 783 if (new_skb == 0) {
784 dev_err(&ndev->dev, "no memory for new sk_buff\n");
785 spin_unlock_irqrestore(&lp->rx_lock, flags);
786 return;
787 }
788
92744989
GL		 789 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
790 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
791 XTE_MAX_JUMBO_FRAME_SIZE,
792 DMA_FROM_DEVICE);
793 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
794 lp->rx_skb[lp->rx_bd_ci] = new_skb;
795
796 lp->rx_bd_ci++;
797 if (lp->rx_bd_ci >= RX_BD_NUM)
798 lp->rx_bd_ci = 0;
799
800 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
801 bdstat = cur_p->app0;
802 }
e44171f1 803 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
92744989
GL		 804
805 spin_unlock_irqrestore(&lp->rx_lock, flags);
806}
807
808static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
809{
810 struct net_device *ndev = _ndev;
811 struct temac_local *lp = netdev_priv(ndev);
812 unsigned int status;
813
e44171f1
JL		 814 status = lp->dma_in(lp, TX_IRQ_REG);
815 lp->dma_out(lp, TX_IRQ_REG, status);
92744989
GL		 816
817 if (status & (IRQ_COAL | IRQ_DLY))
818 temac_start_xmit_done(lp->ndev);
819 if (status & 0x080)
820 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
821
822 return IRQ_HANDLED;
823}
824
825static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
826{
827 struct net_device *ndev = _ndev;
828 struct temac_local *lp = netdev_priv(ndev);
829 unsigned int status;
830
831 /* Read and clear the status registers */
e44171f1
JL		 832 status = lp->dma_in(lp, RX_IRQ_REG);
833 lp->dma_out(lp, RX_IRQ_REG, status);
92744989
GL		 834
835 if (status & (IRQ_COAL | IRQ_DLY))
836 ll_temac_recv(lp->ndev);
837
838 return IRQ_HANDLED;
839}
840
841static int temac_open(struct net_device *ndev)
842{
843 struct temac_local *lp = netdev_priv(ndev);
844 int rc;
845
846 dev_dbg(&ndev->dev, "temac_open()\n");
847
848 if (lp->phy_node) {
849 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
850 temac_adjust_link, 0, 0);
851 if (!lp->phy_dev) {
852 dev_err(lp->dev, "of_phy_connect() failed\n");
853 return -ENODEV;
854 }
855
856 phy_start(lp->phy_dev);
857 }
858
859 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
860 if (rc)
861 goto err_tx_irq;
862 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
863 if (rc)
864 goto err_rx_irq;
865
866 temac_device_reset(ndev);
867 return 0;
868
869 err_rx_irq:
870 free_irq(lp->tx_irq, ndev);
871 err_tx_irq:
872 if (lp->phy_dev)
873 phy_disconnect(lp->phy_dev);
874 lp->phy_dev = NULL;
875 dev_err(lp->dev, "request_irq() failed\n");
876 return rc;
877}
878
879static int temac_stop(struct net_device *ndev)
880{
881 struct temac_local *lp = netdev_priv(ndev);
882
883 dev_dbg(&ndev->dev, "temac_close()\n");
884
885 free_irq(lp->tx_irq, ndev);
886 free_irq(lp->rx_irq, ndev);
887
888 if (lp->phy_dev)
889 phy_disconnect(lp->phy_dev);
890 lp->phy_dev = NULL;
891
301e9d96
DK		 892 temac_dma_bd_release(ndev);
893
92744989
GL		 894 return 0;
895}
896
897#ifdef CONFIG_NET_POLL_CONTROLLER
898static void
899temac_poll_controller(struct net_device *ndev)
900{
901 struct temac_local *lp = netdev_priv(ndev);
902
903 disable_irq(lp->tx_irq);
904 disable_irq(lp->rx_irq);
905
8539992f
MS		 906 ll_temac_rx_irq(lp->tx_irq, ndev);
907 ll_temac_tx_irq(lp->rx_irq, ndev);
92744989
GL		 908
909 enable_irq(lp->tx_irq);
910 enable_irq(lp->rx_irq);
911}
912#endif
913
914static const struct net_device_ops temac_netdev_ops = {
915 .ndo_open = temac_open,
916 .ndo_stop = temac_stop,
917 .ndo_start_xmit = temac_start_xmit,
8ea7a37c 918 .ndo_set_mac_address = netdev_set_mac_address,
60eb5fd1 919 .ndo_validate_addr = eth_validate_addr,
92744989
GL		 920 //.ndo_set_multicast_list = temac_set_multicast_list,
921#ifdef CONFIG_NET_POLL_CONTROLLER
922 .ndo_poll_controller = temac_poll_controller,
923#endif
924};
925
926/* ---------------------------------------------------------------------
927 * SYSFS device attributes
928 */
929static ssize_t temac_show_llink_regs(struct device *dev,
930 struct device_attribute *attr, char *buf)
931{
932 struct net_device *ndev = dev_get_drvdata(dev);
933 struct temac_local *lp = netdev_priv(ndev);
934 int i, len = 0;
935
936 for (i = 0; i < 0x11; i++)
e44171f1 937 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
92744989
GL		 938 (i % 8) == 7 ? "\n" : " ");
939 len += sprintf(buf + len, "\n");
940
941 return len;
942}
943
944static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
945
946static struct attribute *temac_device_attrs[] = {
947 &dev_attr_llink_regs.attr,
948 NULL,
949};
950
951static const struct attribute_group temac_attr_group = {
952 .attrs = temac_device_attrs,
953};
954
955static int __init
2dc11581 956temac_of_probe(struct platform_device *op, const struct of_device_id *match)
92744989
GL		 957{
958 struct device_node *np;
959 struct temac_local *lp;
960 struct net_device *ndev;
961 const void *addr;
23ecc4bd 962 __be32 *p;
92744989 963 int size, rc = 0;
92744989
GL		 964
965 /* Init network device structure */
966 ndev = alloc_etherdev(sizeof(*lp));
967 if (!ndev) {
968 dev_err(&op->dev, "could not allocate device.\n");
969 return -ENOMEM;
970 }
971 ether_setup(ndev);
972 dev_set_drvdata(&op->dev, ndev);
973 SET_NETDEV_DEV(ndev, &op->dev);
974 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
975 ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST;
976 ndev->netdev_ops = &temac_netdev_ops;
977#if 0
978 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
979 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
980 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
981 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
982 ndev->features |= NETIF_F_HW_VLAN_TX; /* Transmit VLAN hw accel */
983 ndev->features |= NETIF_F_HW_VLAN_RX; /* Receive VLAN hw acceleration */
984 ndev->features |= NETIF_F_HW_VLAN_FILTER; /* Receive VLAN filtering */
985 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
986 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
987 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
988 ndev->features |= NETIF_F_LRO; /* large receive offload */
989#endif
990
991 /* setup temac private info structure */
992 lp = netdev_priv(ndev);
993 lp->ndev = ndev;
994 lp->dev = &op->dev;
995 lp->options = XTE_OPTION_DEFAULTS;
996 spin_lock_init(&lp->rx_lock);
997 mutex_init(&lp->indirect_mutex);
998
999 /* map device registers */
61c7a080 1000 lp->regs = of_iomap(op->dev.of_node, 0);
92744989
GL		 1001 if (!lp->regs) {
1002 dev_err(&op->dev, "could not map temac regs.\n");
1003 goto nodev;
1004 }
1005
23ecc4bd
BH		 1006 /* Setup checksum offload, but default to off if not specified */
1007 lp->temac_features = 0;
1008 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
1009 if (p && be32_to_cpu(*p)) {
1010 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1011 /* Can checksum TCP/UDP over IPv4. */
1012 ndev->features |= NETIF_F_IP_CSUM;
1013 }
1014 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
1015 if (p && be32_to_cpu(*p))
1016 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1017
92744989 1018 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
61c7a080 1019 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
92744989
GL		 1020 if (!np) {
1021 dev_err(&op->dev, "could not find DMA node\n");
dfe1e8ed 1022 goto err_iounmap;
92744989
GL		 1023 }
1024
e44171f1
JL		 1025 /* Setup the DMA register accesses, could be DCR or memory mapped */
1026 if (temac_dcr_setup(lp, op, np)) {
1027
1028 /* no DCR in the device tree, try non-DCR */
1029 lp->sdma_regs = of_iomap(np, 0);
1030 if (lp->sdma_regs) {
1031 lp->dma_in = temac_dma_in32;
1032 lp->dma_out = temac_dma_out32;
1033 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
1034 } else {
1035 dev_err(&op->dev, "unable to map DMA registers\n");
7cc36f6f 1036 of_node_put(np);
dfe1e8ed 1037 goto err_iounmap;
e44171f1 1038 }
92744989 1039 }
92744989
GL		 1040
1041 lp->rx_irq = irq_of_parse_and_map(np, 0);
1042 lp->tx_irq = irq_of_parse_and_map(np, 1);
7cc36f6f
KV		 1043
1044 of_node_put(np); /* Finished with the DMA node; drop the reference */
1045
755fae0a 1046 if ((lp->rx_irq == NO_IRQ) || (lp->tx_irq == NO_IRQ)) {
92744989
GL		 1047 dev_err(&op->dev, "could not determine irqs\n");
1048 rc = -ENOMEM;
dfe1e8ed 1049 goto err_iounmap_2;
92744989
GL		 1050 }
1051
92744989
GL		 1052
1053 /* Retrieve the MAC address */
61c7a080 1054 addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
92744989
GL		 1055 if ((!addr) || (size != 6)) {
1056 dev_err(&op->dev, "could not find MAC address\n");
1057 rc = -ENODEV;
dfe1e8ed 1058 goto err_iounmap_2;
92744989
GL		 1059 }
1060 temac_set_mac_address(ndev, (void *)addr);
1061
61c7a080 1062 rc = temac_mdio_setup(lp, op->dev.of_node);
92744989
GL		 1063 if (rc)
1064 dev_warn(&op->dev, "error registering MDIO bus\n");
1065
61c7a080 1066 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
92744989
GL		 1067 if (lp->phy_node)
1068 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
1069
1070 /* Add the device attributes */
1071 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1072 if (rc) {
1073 dev_err(lp->dev, "Error creating sysfs files\n");
dfe1e8ed 1074 goto err_iounmap_2;
92744989
GL		 1075 }
1076
1077 rc = register_netdev(lp->ndev);
1078 if (rc) {
1079 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1080 goto err_register_ndev;
1081 }
1082
1083 return 0;
1084
1085 err_register_ndev:
1086 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
dfe1e8ed
DK		 1087 err_iounmap_2:
1088 if (lp->sdma_regs)
1089 iounmap(lp->sdma_regs);
1090 err_iounmap:
1091 iounmap(lp->regs);
92744989
GL		 1092 nodev:
1093 free_netdev(ndev);
1094 ndev = NULL;
1095 return rc;
1096}
1097
2dc11581 1098static int __devexit temac_of_remove(struct platform_device *op)
92744989
GL		 1099{
1100 struct net_device *ndev = dev_get_drvdata(&op->dev);
1101 struct temac_local *lp = netdev_priv(ndev);
1102
1103 temac_mdio_teardown(lp);
1104 unregister_netdev(ndev);
1105 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1106 if (lp->phy_node)
1107 of_node_put(lp->phy_node);
1108 lp->phy_node = NULL;
1109 dev_set_drvdata(&op->dev, NULL);
dfe1e8ed
DK		 1110 iounmap(lp->regs);
1111 if (lp->sdma_regs)
1112 iounmap(lp->sdma_regs);
92744989
GL		 1113 free_netdev(ndev);
1114 return 0;
1115}
1116
1117static struct of_device_id temac_of_match[] __devinitdata = {
1118 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
c3b7c12c
SM		 1119 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1120 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1121 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
92744989
GL		 1122 {},
1123};
1124MODULE_DEVICE_TABLE(of, temac_of_match);
1125
1126static struct of_platform_driver temac_of_driver = {
92744989
GL		 1127 .probe = temac_of_probe,
1128 .remove = __devexit_p(temac_of_remove),
1129 .driver = {
1130 .owner = THIS_MODULE,
1131 .name = "xilinx_temac",
4018294b 1132 .of_match_table = temac_of_match,
92744989
GL		 1133 },
1134};
1135
1136static int __init temac_init(void)
1137{
1138 return of_register_platform_driver(&temac_of_driver);
1139}
1140module_init(temac_init);
1141
1142static void __exit temac_exit(void)
1143{
1144 of_unregister_platform_driver(&temac_of_driver);
1145}
1146module_exit(temac_exit);
1147
1148MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1149MODULE_AUTHOR("Yoshio Kashiwagi");
1150MODULE_LICENSE("GPL");
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