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ixgbe: Refactor MSI-X allocation mechanism
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_type.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
b4617240 4 Copyright(c) 1999 - 2008 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_TYPE_H_
29#define _IXGBE_TYPE_H_
30
31#include <linux/types.h>
32
33/* Vendor ID */
34#define IXGBE_INTEL_VENDOR_ID 0x8086
35
36/* Device IDs */
1e336d0f 37#define IXGBE_DEV_ID_82598 0x10B6
2f21bdd3 38#define IXGBE_DEV_ID_82598_BX 0x1508
9a799d71
AK		 39#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
40#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
c4900be0 41#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
0befdb3e 42#define IXGBE_DEV_ID_82598AT 0x10C8
9a799d71 43#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
8d792cd9 44#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
c4900be0
DS		 45#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
46#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
b95f5fcb 47#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
9a799d71
AK		 48
49/* General Registers */
50#define IXGBE_CTRL 0x00000
51#define IXGBE_STATUS 0x00008
52#define IXGBE_CTRL_EXT 0x00018
53#define IXGBE_ESDP 0x00020
54#define IXGBE_EODSDP 0x00028
55#define IXGBE_LEDCTL 0x00200
56#define IXGBE_FRTIMER 0x00048
57#define IXGBE_TCPTIMER 0x0004C
58
59/* NVM Registers */
60#define IXGBE_EEC 0x10010
61#define IXGBE_EERD 0x10014
62#define IXGBE_FLA 0x1001C
63#define IXGBE_EEMNGCTL 0x10110
64#define IXGBE_EEMNGDATA 0x10114
65#define IXGBE_FLMNGCTL 0x10118
66#define IXGBE_FLMNGDATA 0x1011C
67#define IXGBE_FLMNGCNT 0x10120
68#define IXGBE_FLOP 0x1013C
69#define IXGBE_GRC 0x10200
70
71/* Interrupt Registers */
72#define IXGBE_EICR 0x00800
73#define IXGBE_EICS 0x00808
74#define IXGBE_EIMS 0x00880
75#define IXGBE_EIMC 0x00888
76#define IXGBE_EIAC 0x00810
77#define IXGBE_EIAM 0x00890
c44ade9e
JB		 78#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : (0x012300 + ((_i) * 4)))
79#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
9a799d71
AK		 80#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
81#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
c44ade9e 82#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
9a799d71
AK		 83#define IXGBE_GPIE 0x00898
84
85/* Flow Control Registers */
86#define IXGBE_PFCTOP 0x03008
87#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
88#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
89#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
90#define IXGBE_FCRTV 0x032A0
91#define IXGBE_TFCS 0x0CE00
92
93/* Receive DMA Registers */
c44ade9e
JB		 94#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : (0x0D000 + ((_i - 64) * 0x40)))
95#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : (0x0D004 + ((_i - 64) * 0x40)))
96#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : (0x0D008 + ((_i - 64) * 0x40)))
97#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : (0x0D010 + ((_i - 64) * 0x40)))
98#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : (0x0D018 + ((_i - 64) * 0x40)))
99#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : (0x0D028 + ((_i - 64) * 0x40)))
100/*
101 * Split and Replication Receive Control Registers
102 * 00-15 : 0x02100 + n*4
103 * 16-64 : 0x01014 + n*0x40
104 * 64-127: 0x0D014 + (n-64)*0x40
105 */
106#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
107 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
108 (0x0D014 + ((_i - 64) * 0x40))))
109/*
110 * Rx DCA Control Register:
111 * 00-15 : 0x02200 + n*4
112 * 16-64 : 0x0100C + n*0x40
113 * 64-127: 0x0D00C + (n-64)*0x40
114 */
115#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
116 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
117 (0x0D00C + ((_i - 64) * 0x40))))
118#define IXGBE_RDRXCTL 0x02F00
9a799d71 119#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
c44ade9e 120 /* 8 of these 0x03C00 - 0x03C1C */
9a799d71
AK		 121#define IXGBE_RXCTRL 0x03000
122#define IXGBE_DROPEN 0x03D04
123#define IXGBE_RXPBSIZE_SHIFT 10
124
125/* Receive Registers */
126#define IXGBE_RXCSUM 0x05000
127#define IXGBE_RFCTL 0x05008
c44ade9e
JB		 128#define IXGBE_DRECCCTL 0x02F08
129#define IXGBE_DRECCCTL_DISABLE 0
130/* Multicast Table Array - 128 entries */
9a799d71 131#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
c44ade9e
JB		 132#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : (0x0A200 + ((_i) * 8)))
133#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : (0x0A204 + ((_i) * 8)))
134/* Packet split receive type */
135#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : (0x0EA00 + ((_i) * 4)))
136/* array of 4096 1-bit vlan filters */
9a799d71 137#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
c44ade9e 138/*array of 4096 4-bit vlan vmdq indices */
9a799d71 139#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
9a799d71
AK		 140#define IXGBE_FCTRL 0x05080
141#define IXGBE_VLNCTRL 0x05088
142#define IXGBE_MCSTCTRL 0x05090
143#define IXGBE_MRQC 0x05818
9a799d71
AK		 144#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
145#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
146#define IXGBE_IMIRVP 0x05AC0
c44ade9e 147#define IXGBE_VMD_CTL 0x0581C
9a799d71
AK		 148#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
149#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
150
c44ade9e 151
9a799d71 152/* Transmit DMA registers */
c44ade9e 153#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
9a799d71
AK		 154#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
155#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
156#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
157#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
158#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
159#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
160#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
161#define IXGBE_DTXCTL 0x07E00
c44ade9e
JB		 162
163#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
9a799d71 164#define IXGBE_TIPG 0x0CB00
c44ade9e 165#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
9a799d71
AK		 166#define IXGBE_MNGTXMAP 0x0CD10
167#define IXGBE_TIPG_FIBER_DEFAULT 3
168#define IXGBE_TXPBSIZE_SHIFT 10
169
170/* Wake up registers */
171#define IXGBE_WUC 0x05800
172#define IXGBE_WUFC 0x05808
173#define IXGBE_WUS 0x05810
174#define IXGBE_IPAV 0x05838
175#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
176#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
c44ade9e 177
9a799d71
AK		 178#define IXGBE_WUPL 0x05900
179#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
180#define IXGBE_FHFT 0x09000 /* Flex host filter table 9000-93FC */
181
182/* Music registers */
183#define IXGBE_RMCS 0x03D00
184#define IXGBE_DPMCS 0x07F40
185#define IXGBE_PDPMCS 0x0CD00
186#define IXGBE_RUPPBMR 0x050A0
187#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
188#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
189#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
190#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
191#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
192#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
193
c44ade9e
JB		 194
195
9a799d71
AK		 196/* Stats registers */
197#define IXGBE_CRCERRS 0x04000
198#define IXGBE_ILLERRC 0x04004
199#define IXGBE_ERRBC 0x04008
200#define IXGBE_MSPDC 0x04010
201#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
202#define IXGBE_MLFC 0x04034
203#define IXGBE_MRFC 0x04038
204#define IXGBE_RLEC 0x04040
205#define IXGBE_LXONTXC 0x03F60
206#define IXGBE_LXONRXC 0x0CF60
207#define IXGBE_LXOFFTXC 0x03F68
208#define IXGBE_LXOFFRXC 0x0CF68
209#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
210#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
211#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
212#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
213#define IXGBE_PRC64 0x0405C
214#define IXGBE_PRC127 0x04060
215#define IXGBE_PRC255 0x04064
216#define IXGBE_PRC511 0x04068
217#define IXGBE_PRC1023 0x0406C
218#define IXGBE_PRC1522 0x04070
219#define IXGBE_GPRC 0x04074
220#define IXGBE_BPRC 0x04078
221#define IXGBE_MPRC 0x0407C
222#define IXGBE_GPTC 0x04080
223#define IXGBE_GORCL 0x04088
224#define IXGBE_GORCH 0x0408C
225#define IXGBE_GOTCL 0x04090
226#define IXGBE_GOTCH 0x04094
227#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
228#define IXGBE_RUC 0x040A4
229#define IXGBE_RFC 0x040A8
230#define IXGBE_ROC 0x040AC
231#define IXGBE_RJC 0x040B0
232#define IXGBE_MNGPRC 0x040B4
233#define IXGBE_MNGPDC 0x040B8
234#define IXGBE_MNGPTC 0x0CF90
235#define IXGBE_TORL 0x040C0
236#define IXGBE_TORH 0x040C4
237#define IXGBE_TPR 0x040D0
238#define IXGBE_TPT 0x040D4
239#define IXGBE_PTC64 0x040D8
240#define IXGBE_PTC127 0x040DC
241#define IXGBE_PTC255 0x040E0
242#define IXGBE_PTC511 0x040E4
243#define IXGBE_PTC1023 0x040E8
244#define IXGBE_PTC1522 0x040EC
245#define IXGBE_MPTC 0x040F0
246#define IXGBE_BPTC 0x040F4
247#define IXGBE_XEC 0x04120
248
249#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */
c44ade9e 250#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : (0x08600 + ((_i) * 4)))
9a799d71
AK		 251
252#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
253#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
254#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
255#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
256
257/* Management */
258#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
259#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
260#define IXGBE_MANC 0x05820
261#define IXGBE_MFVAL 0x05824
262#define IXGBE_MANC2H 0x05860
263#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
264#define IXGBE_MIPAF 0x058B0
265#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
266#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
267#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
268
269/* ARC Subsystem registers */
270#define IXGBE_HICR 0x15F00
271#define IXGBE_FWSTS 0x15F0C
272#define IXGBE_HSMC0R 0x15F04
273#define IXGBE_HSMC1R 0x15F08
274#define IXGBE_SWSR 0x15F10
275#define IXGBE_HFDR 0x15FE8
276#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */
277
278/* PCI-E registers */
279#define IXGBE_GCR 0x11000
280#define IXGBE_GTV 0x11004
281#define IXGBE_FUNCTAG 0x11008
282#define IXGBE_GLT 0x1100C
283#define IXGBE_GSCL_1 0x11010
284#define IXGBE_GSCL_2 0x11014
285#define IXGBE_GSCL_3 0x11018
286#define IXGBE_GSCL_4 0x1101C
287#define IXGBE_GSCN_0 0x11020
288#define IXGBE_GSCN_1 0x11024
289#define IXGBE_GSCN_2 0x11028
290#define IXGBE_GSCN_3 0x1102C
291#define IXGBE_FACTPS 0x10150
292#define IXGBE_PCIEANACTL 0x11040
293#define IXGBE_SWSM 0x10140
294#define IXGBE_FWSM 0x10148
295#define IXGBE_GSSR 0x10160
296#define IXGBE_MREVID 0x11064
297#define IXGBE_DCA_ID 0x11070
298#define IXGBE_DCA_CTRL 0x11074
299
300/* Diagnostic Registers */
c44ade9e
JB		 301#define IXGBE_RDSTATCTL 0x02C20
302#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
303#define IXGBE_RDHMPN 0x02F08
98c00a1c 304#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
c44ade9e
JB		 305#define IXGBE_RDPROBE 0x02F20
306#define IXGBE_TDSTATCTL 0x07C20
307#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
308#define IXGBE_TDHMPN 0x07F08
98c00a1c 309#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
c44ade9e
JB		 310#define IXGBE_TDPROBE 0x07F20
311#define IXGBE_TXBUFCTRL 0x0C600
9a799d71
AK		 312#define IXGBE_TXBUFDATA0 0x0C610
313#define IXGBE_TXBUFDATA1 0x0C614
314#define IXGBE_TXBUFDATA2 0x0C618
315#define IXGBE_TXBUFDATA3 0x0C61C
316#define IXGBE_RXBUFCTRL 0x03600
317#define IXGBE_RXBUFDATA0 0x03610
318#define IXGBE_RXBUFDATA1 0x03614
319#define IXGBE_RXBUFDATA2 0x03618
320#define IXGBE_RXBUFDATA3 0x0361C
321#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */
322#define IXGBE_RFVAL 0x050A4
323#define IXGBE_MDFTC1 0x042B8
324#define IXGBE_MDFTC2 0x042C0
325#define IXGBE_MDFTFIFO1 0x042C4
326#define IXGBE_MDFTFIFO2 0x042C8
327#define IXGBE_MDFTS 0x042CC
328#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
329#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
330#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
331#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
332#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
333#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
334#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
335#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
336#define IXGBE_PCIEECCCTL 0x1106C
337#define IXGBE_PBTXECC 0x0C300
338#define IXGBE_PBRXECC 0x03300
339#define IXGBE_GHECCR 0x110B0
340
341/* MAC Registers */
342#define IXGBE_PCS1GCFIG 0x04200
343#define IXGBE_PCS1GLCTL 0x04208
344#define IXGBE_PCS1GLSTA 0x0420C
345#define IXGBE_PCS1GDBG0 0x04210
346#define IXGBE_PCS1GDBG1 0x04214
347#define IXGBE_PCS1GANA 0x04218
348#define IXGBE_PCS1GANLP 0x0421C
349#define IXGBE_PCS1GANNP 0x04220
350#define IXGBE_PCS1GANLPNP 0x04224
351#define IXGBE_HLREG0 0x04240
352#define IXGBE_HLREG1 0x04244
353#define IXGBE_PAP 0x04248
354#define IXGBE_MACA 0x0424C
355#define IXGBE_APAE 0x04250
356#define IXGBE_ARD 0x04254
357#define IXGBE_AIS 0x04258
358#define IXGBE_MSCA 0x0425C
359#define IXGBE_MSRWD 0x04260
360#define IXGBE_MLADD 0x04264
361#define IXGBE_MHADD 0x04268
362#define IXGBE_TREG 0x0426C
363#define IXGBE_PCSS1 0x04288
364#define IXGBE_PCSS2 0x0428C
365#define IXGBE_XPCSS 0x04290
366#define IXGBE_SERDESC 0x04298
367#define IXGBE_MACS 0x0429C
368#define IXGBE_AUTOC 0x042A0
369#define IXGBE_LINKS 0x042A4
370#define IXGBE_AUTOC2 0x042A8
371#define IXGBE_AUTOC3 0x042AC
372#define IXGBE_ANLP1 0x042B0
373#define IXGBE_ANLP2 0x042B4
374#define IXGBE_ATLASCTL 0x04800
375
cc41ac7c
JB		 376/* RDRXCTL Bit Masks */
377#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */
378#define IXGBE_RDRXCTL_MVMEN 0x00000020
379#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
9a799d71
AK		 380
381/* CTRL Bit Masks */
382#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
383#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
384#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
385
386/* FACTPS */
387#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
388
389/* MHADD Bit Masks */
390#define IXGBE_MHADD_MFS_MASK 0xFFFF0000
391#define IXGBE_MHADD_MFS_SHIFT 16
392
393/* Extended Device Control */
394#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
395#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
396#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
397
398/* Direct Cache Access (DCA) definitions */
399#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
400#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
401
402#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
403#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
404
405#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
406#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
407#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
408#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
15005a32
DS		 409#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
410#define IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13) /* DCA Rx wr Desc Relax Order */
411#define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* DCA Rx Split Header RO */
9a799d71
AK		 412
413#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
414#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
c44ade9e 415#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
9a799d71
AK		 416#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
417
418/* MSCA Bit Masks */
419#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */
420#define IXGBE_MSCA_NP_ADDR_SHIFT 0
421#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */
422#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */
423#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */
424#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/
425#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */
426#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */
427#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */
428#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */
429#define IXGBE_MSCA_READ 0x08000000 /* OP CODE 10 (read) */
430#define IXGBE_MSCA_READ_AUTOINC 0x0C000000 /* OP CODE 11 (read, auto inc)*/
431#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */
432#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */
433#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */
434#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */
435#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */
436#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */
437
438/* MSRWD bit masks */
c44ade9e
JB		 439#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
440#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
441#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
442#define IXGBE_MSRWD_READ_DATA_SHIFT 16
9a799d71
AK		 443
444/* Atlas registers */
445#define IXGBE_ATLAS_PDN_LPBK 0x24
446#define IXGBE_ATLAS_PDN_10G 0xB
447#define IXGBE_ATLAS_PDN_1G 0xC
448#define IXGBE_ATLAS_PDN_AN 0xD
449
450/* Atlas bit masks */
451#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
452#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
453#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
454#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
455#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
456
c44ade9e 457
9a799d71
AK		 458/* Device Type definitions for new protocol MDIO commands */
459#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
460#define IXGBE_MDIO_PCS_DEV_TYPE 0x3
461#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
462#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
463#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
c4900be0 464#define IXGBE_TWINAX_DEV 1
9a799d71 465
c44ade9e
JB		 466#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
467
9a799d71
AK		 468#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
469#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
470#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
471#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
472#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
473#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
474
475#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
476#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
477#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */
478#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */
479#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/
480#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/
c44ade9e 481#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */
9a799d71
AK		 482#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
483#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
484
c44ade9e
JB		 485#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Address Reg */
486#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
487#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
488
489/* MII clause 22/28 definitions */
490#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
491
492#define IXGBE_MII_SPEED_SELECTION_REG 0x10
493#define IXGBE_MII_RESTART 0x200
494#define IXGBE_MII_AUTONEG_COMPLETE 0x20
495#define IXGBE_MII_AUTONEG_REG 0x0
496
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AK		 497#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
498#define IXGBE_MAX_PHY_ADDR 32
499
c4900be0 500/* PHY IDs */
0befdb3e
JB		 501#define TN1010_PHY_ID 0x00A19410
502#define TNX_FW_REV 0xB
9a799d71 503#define QT2022_PHY_ID 0x0043A400
c4900be0 504#define ATH_PHY_ID 0x03429050
9a799d71 505
c44ade9e
JB		 506/* PHY Types */
507#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
508
c4900be0
DS		 509/* Special PHY Init Routine */
510#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
511#define IXGBE_PHY_INIT_END_NL 0xFFFF
512#define IXGBE_CONTROL_MASK_NL 0xF000
513#define IXGBE_DATA_MASK_NL 0x0FFF
514#define IXGBE_CONTROL_SHIFT_NL 12
515#define IXGBE_DELAY_NL 0
516#define IXGBE_DATA_NL 1
517#define IXGBE_CONTROL_NL 0x000F
518#define IXGBE_CONTROL_EOL_NL 0x0FFF
519#define IXGBE_CONTROL_SOL_NL 0x0000
520
9a799d71 521/* General purpose Interrupt Enable */
c44ade9e
JB		 522#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
523#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
524#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
525#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
526#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
527#define IXGBE_GPIE_EIAME 0x40000000
528#define IXGBE_GPIE_PBA_SUPPORT 0x80000000
9a799d71
AK		 529
530/* Transmit Flow Control status */
531#define IXGBE_TFCS_TXOFF 0x00000001
532#define IXGBE_TFCS_TXOFF0 0x00000100
533#define IXGBE_TFCS_TXOFF1 0x00000200
534#define IXGBE_TFCS_TXOFF2 0x00000400
535#define IXGBE_TFCS_TXOFF3 0x00000800
536#define IXGBE_TFCS_TXOFF4 0x00001000
537#define IXGBE_TFCS_TXOFF5 0x00002000
538#define IXGBE_TFCS_TXOFF6 0x00004000
539#define IXGBE_TFCS_TXOFF7 0x00008000
540
541/* TCP Timer */
542#define IXGBE_TCPTIMER_KS 0x00000100
543#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
544#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
545#define IXGBE_TCPTIMER_LOOP 0x00000800
546#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
547
548/* HLREG0 Bit Masks */
549#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */
550#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */
551#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */
552#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */
553#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */
554#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */
555#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */
556#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */
557#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */
558#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */
559#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */
560#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */
561#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */
562#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */
563#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */
564
565/* VMD_CTL bitmasks */
566#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
567#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
568
569/* RDHMPN and TDHMPN bitmasks */
570#define IXGBE_RDHMPN_RDICADDR 0x007FF800
571#define IXGBE_RDHMPN_RDICRDREQ 0x00800000
572#define IXGBE_RDHMPN_RDICADDR_SHIFT 11
573#define IXGBE_TDHMPN_TDICADDR 0x003FF800
574#define IXGBE_TDHMPN_TDICRDREQ 0x00800000
575#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
576
577/* Receive Checksum Control */
578#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
579#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
580
581/* FCRTL Bit Masks */
582#define IXGBE_FCRTL_XONE 0x80000000 /* bit 31, XON enable */
583#define IXGBE_FCRTH_FCEN 0x80000000 /* Rx Flow control enable */
584
585/* PAP bit masks*/
586#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
587
588/* RMCS Bit Masks */
c44ade9e 589#define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */
9a799d71
AK		 590/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
591#define IXGBE_RMCS_RAC 0x00000004
592#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
593#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority flow control ena */
594#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */
595#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
596
c44ade9e 597
9a799d71
AK		 598/* Interrupt register bitmasks */
599
600/* Extended Interrupt Cause Read */
601#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
602#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
c44ade9e
JB		 603#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
604#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
605#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
9a799d71
AK		 606#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
607#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
608#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
609#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
610
611/* Extended Interrupt Cause Set */
612#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
c44ade9e
JB		 613#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
614#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
615#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
616#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
617#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
618#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
9a799d71
AK		 619#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
620#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
621
622/* Extended Interrupt Mask Set */
623#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
624#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
625#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
c44ade9e
JB		 626#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
627#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
628#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
9a799d71
AK		 629#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
630#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
631#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
632
633/* Extended Interrupt Mask Clear */
634#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
635#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
636#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
c44ade9e
JB		 637#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
638#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
639#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
640#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */
9a799d71
AK		 641#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
642#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
643
c44ade9e
JB		 644#define IXGBE_EIMS_ENABLE_MASK ( \
645 IXGBE_EIMS_RTX_QUEUE | \
646 IXGBE_EIMS_LSC | \
647 IXGBE_EIMS_TCP_TIMER | \
648 IXGBE_EIMS_OTHER)
9a799d71 649
c44ade9e 650/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
9a799d71
AK		 651#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
652#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
653#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
654#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
655#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
656#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
657#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
658#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
659#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
660#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */
661
662/* Interrupt clear mask */
663#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
664
665/* Interrupt Vector Allocation Registers */
666#define IXGBE_IVAR_REG_NUM 25
667#define IXGBE_IVAR_TXRX_ENTRY 96
668#define IXGBE_IVAR_RX_ENTRY 64
669#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
670#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
671#define IXGBE_IVAR_TX_ENTRY 32
672
673#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */
674#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */
675
676#define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
677
678#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
679
680/* VLAN Control Bit Masks */
681#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
682#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
683#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
684#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
685#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
686
c44ade9e 687
9a799d71
AK		 688#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
689
690/* STATUS Bit Masks */
691#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
692#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
693
694#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
695#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
696
697/* ESDP Bit Masks */
698#define IXGBE_ESDP_SDP4 0x00000001 /* SDP4 Data Value */
699#define IXGBE_ESDP_SDP5 0x00000002 /* SDP5 Data Value */
700#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
701#define IXGBE_ESDP_SDP5_DIR 0x00000008 /* SDP5 IO direction */
702
703/* LEDCTL Bit Masks */
704#define IXGBE_LED_IVRT_BASE 0x00000040
705#define IXGBE_LED_BLINK_BASE 0x00000080
706#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
707#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
708#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
709#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
710#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
711#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
712
713/* LED modes */
714#define IXGBE_LED_LINK_UP 0x0
715#define IXGBE_LED_LINK_10G 0x1
716#define IXGBE_LED_MAC 0x2
717#define IXGBE_LED_FILTER 0x3
718#define IXGBE_LED_LINK_ACTIVE 0x4
719#define IXGBE_LED_LINK_1G 0x5
720#define IXGBE_LED_ON 0xE
721#define IXGBE_LED_OFF 0xF
722
723/* AUTOC Bit Masks */
724#define IXGBE_AUTOC_KX4_SUPP 0x80000000
725#define IXGBE_AUTOC_KX_SUPP 0x40000000
726#define IXGBE_AUTOC_PAUSE 0x30000000
727#define IXGBE_AUTOC_RF 0x08000000
728#define IXGBE_AUTOC_PD_TMR 0x06000000
729#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
730#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
731#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
732#define IXGBE_AUTOC_AN_RESTART 0x00001000
733#define IXGBE_AUTOC_FLU 0x00000001
734#define IXGBE_AUTOC_LMS_SHIFT 13
c44ade9e
JB		 735#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
736#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
737#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
738#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
739#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
740#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
741#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
742
743#define IXGBE_AUTOC_1G_PMA_PMD 0x00000200
744#define IXGBE_AUTOC_10G_PMA_PMD 0x00000180
9a799d71
AK		 745#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
746#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
747#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
748#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
749#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
750#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
751#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
752
753/* LINKS Bit Masks */
754#define IXGBE_LINKS_KX_AN_COMP 0x80000000
755#define IXGBE_LINKS_UP 0x40000000
756#define IXGBE_LINKS_SPEED 0x20000000
757#define IXGBE_LINKS_MODE 0x18000000
758#define IXGBE_LINKS_RX_MODE 0x06000000
759#define IXGBE_LINKS_TX_MODE 0x01800000
760#define IXGBE_LINKS_XGXS_EN 0x00400000
761#define IXGBE_LINKS_PCS_1G_EN 0x00200000
762#define IXGBE_LINKS_1G_AN_EN 0x00100000
763#define IXGBE_LINKS_KX_AN_IDLE 0x00080000
764#define IXGBE_LINKS_1G_SYNC 0x00040000
765#define IXGBE_LINKS_10G_ALIGN 0x00020000
766#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
767#define IXGBE_LINKS_TL_FAULT 0x00001000
768#define IXGBE_LINKS_SIGNAL 0x00000F00
769
cf8280ee 770#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
9a799d71
AK		 771#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
772
773/* SW Semaphore Register bitmasks */
774#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
775#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
776#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
777
778/* GSSR definitions */
779#define IXGBE_GSSR_EEP_SM 0x0001
780#define IXGBE_GSSR_PHY0_SM 0x0002
781#define IXGBE_GSSR_PHY1_SM 0x0004
782#define IXGBE_GSSR_MAC_CSR_SM 0x0008
783#define IXGBE_GSSR_FLASH_SM 0x0010
784
785/* EEC Register */
786#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */
787#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */
788#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */
789#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */
790#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */
791#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */
792#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */
793#define IXGBE_EEC_FWE_SHIFT 4
794#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */
795#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
796#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
797#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
798/* EEPROM Addressing bits based on type (0-small, 1-large) */
799#define IXGBE_EEC_ADDR_SIZE 0x00000400
800#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
801
802#define IXGBE_EEC_SIZE_SHIFT 11
803#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
804#define IXGBE_EEPROM_OPCODE_BITS 8
805
806/* Checksum and EEPROM pointers */
807#define IXGBE_EEPROM_CHECKSUM 0x3F
808#define IXGBE_EEPROM_SUM 0xBABA
809#define IXGBE_PCIE_ANALOG_PTR 0x03
810#define IXGBE_ATLAS0_CONFIG_PTR 0x04
811#define IXGBE_ATLAS1_CONFIG_PTR 0x05
812#define IXGBE_PCIE_GENERAL_PTR 0x06
813#define IXGBE_PCIE_CONFIG0_PTR 0x07
814#define IXGBE_PCIE_CONFIG1_PTR 0x08
815#define IXGBE_CORE0_PTR 0x09
816#define IXGBE_CORE1_PTR 0x0A
817#define IXGBE_MAC0_PTR 0x0B
818#define IXGBE_MAC1_PTR 0x0C
819#define IXGBE_CSR0_CONFIG_PTR 0x0D
820#define IXGBE_CSR1_CONFIG_PTR 0x0E
821#define IXGBE_FW_PTR 0x0F
822#define IXGBE_PBANUM0_PTR 0x15
823#define IXGBE_PBANUM1_PTR 0x16
eb7f139c
PWJ		 824#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
825
826/* MSI-X capability fields masks */
827#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
9a799d71 828
c44ade9e
JB		 829/* Legacy EEPROM word offsets */
830#define IXGBE_ISCSI_BOOT_CAPS 0x0033
831#define IXGBE_ISCSI_SETUP_PORT_0 0x0030
832#define IXGBE_ISCSI_SETUP_PORT_1 0x0034
833
9a799d71
AK		 834/* EEPROM Commands - SPI */
835#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
836#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
837#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
838#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
839#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */
840#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */
c44ade9e 841/* EEPROM reset Write Enable latch */
9a799d71
AK		 842#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
843#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */
844#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */
845#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
846#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
847#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
848
849/* EEPROM Read Register */
850#define IXGBE_EEPROM_READ_REG_DATA 16 /* data offset in EEPROM read reg */
851#define IXGBE_EEPROM_READ_REG_DONE 2 /* Offset to READ done bit */
852#define IXGBE_EEPROM_READ_REG_START 1 /* First bit to start operation */
853#define IXGBE_EEPROM_READ_ADDR_SHIFT 2 /* Shift to the address bits */
854
855#define IXGBE_ETH_LENGTH_OF_ADDRESS 6
856
857#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
858#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
859#endif
860
861#ifndef IXGBE_EERD_ATTEMPTS
862/* Number of 5 microseconds we wait for EERD read to complete */
863#define IXGBE_EERD_ATTEMPTS 100000
864#endif
865
866/* PCI Bus Info */
867#define IXGBE_PCI_LINK_STATUS 0xB2
868#define IXGBE_PCI_LINK_WIDTH 0x3F0
869#define IXGBE_PCI_LINK_WIDTH_1 0x10
870#define IXGBE_PCI_LINK_WIDTH_2 0x20
871#define IXGBE_PCI_LINK_WIDTH_4 0x40
872#define IXGBE_PCI_LINK_WIDTH_8 0x80
873#define IXGBE_PCI_LINK_SPEED 0xF
874#define IXGBE_PCI_LINK_SPEED_2500 0x1
875#define IXGBE_PCI_LINK_SPEED_5000 0x2
876
877/* Number of 100 microseconds we wait for PCI Express master disable */
878#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
879
9a799d71
AK		 880/* Check whether address is multicast. This is little-endian specific check.*/
881#define IXGBE_IS_MULTICAST(Address) \
c44ade9e 882 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
9a799d71
AK		 883
884/* Check whether an address is broadcast. */
885#define IXGBE_IS_BROADCAST(Address) \
c44ade9e
JB		 886 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
887 (((u8 *)(Address))[1] == ((u8)0xff)))
9a799d71
AK		 888
889/* RAH */
890#define IXGBE_RAH_VIND_MASK 0x003C0000
891#define IXGBE_RAH_VIND_SHIFT 18
892#define IXGBE_RAH_AV 0x80000000
c44ade9e 893#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
9a799d71 894
9a799d71
AK		 895/* Header split receive */
896#define IXGBE_RFCTL_ISCSI_DIS 0x00000001
897#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
898#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
899#define IXGBE_RFCTL_NFSW_DIS 0x00000040
900#define IXGBE_RFCTL_NFSR_DIS 0x00000080
901#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
902#define IXGBE_RFCTL_NFS_VER_SHIFT 8
903#define IXGBE_RFCTL_NFS_VER_2 0
904#define IXGBE_RFCTL_NFS_VER_3 1
905#define IXGBE_RFCTL_NFS_VER_4 2
906#define IXGBE_RFCTL_IPV6_DIS 0x00000400
907#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
908#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
909#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
910#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
911
912/* Transmit Config masks */
913#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
914#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */
915/* Enable short packet padding to 64 bytes */
916#define IXGBE_TX_PAD_ENABLE 0x00000400
917#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */
918/* This allows for 16K packets + 4k for vlan */
919#define IXGBE_MAX_FRAME_SZ 0x40040000
920
921#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */
c44ade9e 922#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */
9a799d71
AK		 923
924/* Receive Config masks */
925#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
926#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
927#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
928
929#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
930#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
931#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
932#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
933#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
934#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
c44ade9e 935/* Receive Priority Flow Control Enable */
9a799d71
AK		 936#define IXGBE_FCTRL_RPFCE 0x00004000
937#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
938
939/* Multiple Receive Queue Control */
940#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
941#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
942#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
943#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
944#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
945#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
946#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
947#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
948#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
949#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
950#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
951
952#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
953#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
954#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
955#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
956#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
957#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
958#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
959#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
960#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
961
962/* Receive Descriptor bit definitions */
963#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
964#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
9a799d71 965#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
c44ade9e 966#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
9a799d71
AK		 967#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
968#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
969#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
970#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
971#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
972#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
973#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
974#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
975#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
976#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
977#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
978#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
979#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
980#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
981#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
c44ade9e 982#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
9a799d71
AK		 983#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
984#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
985#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
986#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
987#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
988#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
989#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
990#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
991#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
992#define IXGBE_RXD_PRI_SHIFT 13
993#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
994#define IXGBE_RXD_CFI_SHIFT 12
995
c44ade9e 996
9a799d71 997/* SRRCTL bit definitions */
c44ade9e
JB		 998#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
999#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
1000#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
1001#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
9a799d71
AK		 1002#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
1003#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
1004#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
1005#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
c44ade9e 1006#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
9a799d71
AK		 1007
1008#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
1009#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
1010
1011#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
1012#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
1013#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
1014#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
1015#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
1016#define IXGBE_RXDADV_SPH 0x8000
1017
1018/* RSS Hash results */
1019#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
1020#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
1021#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
1022#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
1023#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
1024#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
1025#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
1026#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
1027#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
1028#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
1029
1030/* RSS Packet Types as indicated in the receive descriptor. */
1031#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
1032#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
1033#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
1034#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
1035#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
1036#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
1037#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
1038#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
1039#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
9a799d71 1040/* Masks to determine if packets should be dropped due to frame errors */
c44ade9e
JB		 1041#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
1042 IXGBE_RXD_ERR_CE | \
1043 IXGBE_RXD_ERR_LE | \
1044 IXGBE_RXD_ERR_PE | \
1045 IXGBE_RXD_ERR_OSE | \
1046 IXGBE_RXD_ERR_USE)
1047
1048#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
1049 IXGBE_RXDADV_ERR_CE | \
1050 IXGBE_RXDADV_ERR_LE | \
1051 IXGBE_RXDADV_ERR_PE | \
1052 IXGBE_RXDADV_ERR_OSE | \
1053 IXGBE_RXDADV_ERR_USE)
9a799d71
AK		 1054
1055/* Multicast bit mask */
1056#define IXGBE_MCSTCTRL_MFE 0x4
1057
1058/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
1059#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
1060#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
1061#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
1062
1063/* Vlan-specific macros */
1064#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
1065#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
1066#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
1067#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
1068
c44ade9e 1069
9a799d71
AK		 1070/* Transmit Descriptor - Legacy */
1071struct ixgbe_legacy_tx_desc {
1072 u64 buffer_addr; /* Address of the descriptor's data buffer */
1073 union {
8327d000 1074 __le32 data;
9a799d71 1075 struct {
8327d000 1076 __le16 length; /* Data buffer length */
9da09bb1
JB		 1077 u8 cso; /* Checksum offset */
1078 u8 cmd; /* Descriptor control */
9a799d71
AK		 1079 } flags;
1080 } lower;
1081 union {
8327d000 1082 __le32 data;
9a799d71 1083 struct {
c44ade9e
JB		 1084 u8 status; /* Descriptor status */
1085 u8 css; /* Checksum start */
8327d000 1086 __le16 vlan;
9a799d71
AK		 1087 } fields;
1088 } upper;
1089};
1090
1091/* Transmit Descriptor - Advanced */
1092union ixgbe_adv_tx_desc {
1093 struct {
c44ade9e 1094 __le64 buffer_addr; /* Address of descriptor's data buf */
8327d000
AV		 1095 __le32 cmd_type_len;
1096 __le32 olinfo_status;
9a799d71
AK		 1097 } read;
1098 struct {
8327d000
AV		 1099 __le64 rsvd; /* Reserved */
1100 __le32 nxtseq_seed;
1101 __le32 status;
9a799d71
AK		 1102 } wb;
1103};
1104
1105/* Receive Descriptor - Legacy */
1106struct ixgbe_legacy_rx_desc {
8327d000
AV		 1107 __le64 buffer_addr; /* Address of the descriptor's data buffer */
1108 __le16 length; /* Length of data DMAed into data buffer */
9da09bb1
JB		 1109 __le16 csum; /* Packet checksum */
1110 u8 status; /* Descriptor status */
1111 u8 errors; /* Descriptor Errors */
8327d000 1112 __le16 vlan;
9a799d71
AK		 1113};
1114
1115/* Receive Descriptor - Advanced */
1116union ixgbe_adv_rx_desc {
1117 struct {
8327d000
AV		 1118 __le64 pkt_addr; /* Packet buffer address */
1119 __le64 hdr_addr; /* Header buffer address */
9a799d71
AK		 1120 } read;
1121 struct {
1122 struct {
7c6e0a43
JB		 1123 union {
1124 __le32 data;
1125 struct {
c44ade9e
JB		 1126 __le16 pkt_info; /* RSS, Pkt type */
1127 __le16 hdr_info; /* Splithdr, hdrlen */
7c6e0a43 1128 } hs_rss;
9a799d71
AK		 1129 } lo_dword;
1130 union {
8327d000 1131 __le32 rss; /* RSS Hash */
9a799d71 1132 struct {
8327d000 1133 __le16 ip_id; /* IP id */
9da09bb1 1134 __le16 csum; /* Packet Checksum */
9a799d71
AK		 1135 } csum_ip;
1136 } hi_dword;
1137 } lower;
1138 struct {
8327d000
AV		 1139 __le32 status_error; /* ext status/error */
1140 __le16 length; /* Packet length */
1141 __le16 vlan; /* VLAN tag */
9a799d71
AK		 1142 } upper;
1143 } wb; /* writeback */
1144};
1145
1146/* Context descriptors */
1147struct ixgbe_adv_tx_context_desc {
8327d000
AV		 1148 __le32 vlan_macip_lens;
1149 __le32 seqnum_seed;
1150 __le32 type_tucmd_mlhl;
1151 __le32 mss_l4len_idx;
9a799d71
AK		 1152};
1153
1154/* Adv Transmit Descriptor Config Masks */
c44ade9e 1155#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */
9a799d71
AK		 1156#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
1157#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
1158#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
1159#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
1160#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
9a799d71 1161#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
c44ade9e 1162#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
9a799d71
AK		 1163#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
1164#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
1165#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
1166#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
c44ade9e 1167#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */
9a799d71
AK		 1168#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */
1169#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
c44ade9e 1170#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */
9a799d71
AK		 1171#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
1172#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
c44ade9e 1173 IXGBE_ADVTXD_POPTS_SHIFT)
9a799d71 1174#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
c44ade9e
JB		 1175 IXGBE_ADVTXD_POPTS_SHIFT)
1176#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
1177#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
1178#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
1179#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
1180#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */
1181#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
1182#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
1183#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
1184#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
1185#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
1186#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
1187#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
1188#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
1189#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/
1190#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
1191#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
1192
1193/* Autonegotiation advertised speeds */
1194typedef u32 ixgbe_autoneg_advertised;
9a799d71 1195/* Link speed */
c44ade9e 1196typedef u32 ixgbe_link_speed;
9a799d71
AK		 1197#define IXGBE_LINK_SPEED_UNKNOWN 0
1198#define IXGBE_LINK_SPEED_100_FULL 0x0008
1199#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
1200#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
c44ade9e
JB		 1201#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
1202 IXGBE_LINK_SPEED_10GB_FULL)
1203
1204/* Physical layer type */
1205typedef u32 ixgbe_physical_layer;
1206#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
1207#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
1208#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
1209#define IXGBE_PHYSICAL_LAYER_100BASE_T 0x0004
1210#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
1211#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
1212#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
1213#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
1214#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
1215#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
1216#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
1217#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
9a799d71
AK		 1218
1219
1220enum ixgbe_eeprom_type {
1221 ixgbe_eeprom_uninitialized = 0,
1222 ixgbe_eeprom_spi,
1223 ixgbe_eeprom_none /* No NVM support */
1224};
1225
1226enum ixgbe_mac_type {
1227 ixgbe_mac_unknown = 0,
1228 ixgbe_mac_82598EB,
1229 ixgbe_num_macs
1230};
1231
1232enum ixgbe_phy_type {
1233 ixgbe_phy_unknown = 0,
0befdb3e 1234 ixgbe_phy_tn,
9a799d71 1235 ixgbe_phy_qt,
c44ade9e 1236 ixgbe_phy_xaui,
c4900be0 1237 ixgbe_phy_nl,
c44ade9e
JB		 1238 ixgbe_phy_tw_tyco,
1239 ixgbe_phy_tw_unknown,
1240 ixgbe_phy_sfp_avago,
1241 ixgbe_phy_sfp_ftl,
1242 ixgbe_phy_sfp_unknown,
1243 ixgbe_phy_generic
1244};
1245
1246/*
1247 * SFP+ module type IDs:
1248 *
1249 * ID Module Type
1250 * =============
1251 * 0 SFP_DA_CU
1252 * 1 SFP_SR
1253 * 2 SFP_LR
1254 */
1255enum ixgbe_sfp_type {
1256 ixgbe_sfp_type_da_cu = 0,
1257 ixgbe_sfp_type_sr = 1,
1258 ixgbe_sfp_type_lr = 2,
c4900be0 1259 ixgbe_sfp_type_not_present = 0xFFFE,
c44ade9e 1260 ixgbe_sfp_type_unknown = 0xFFFF
9a799d71
AK		 1261};
1262
1263enum ixgbe_media_type {
1264 ixgbe_media_type_unknown = 0,
1265 ixgbe_media_type_fiber,
1266 ixgbe_media_type_copper,
c44ade9e
JB		 1267 ixgbe_media_type_backplane,
1268 ixgbe_media_type_virtual
9a799d71
AK		 1269};
1270
1271/* Flow Control Settings */
1272enum ixgbe_fc_type {
1273 ixgbe_fc_none = 0,
1274 ixgbe_fc_rx_pause,
1275 ixgbe_fc_tx_pause,
1276 ixgbe_fc_full,
1277 ixgbe_fc_default
1278};
1279
1280struct ixgbe_addr_filter_info {
1281 u32 num_mc_addrs;
1282 u32 rar_used_count;
1283 u32 mc_addr_in_rar_count;
1284 u32 mta_in_use;
2c5645cf
CL		 1285 u32 overflow_promisc;
1286 bool user_set_promisc;
9a799d71
AK		 1287};
1288
1289/* Flow control parameters */
1290struct ixgbe_fc_info {
1291 u32 high_water; /* Flow Control High-water */
1292 u32 low_water; /* Flow Control Low-water */
1293 u16 pause_time; /* Flow Control Pause timer */
1294 bool send_xon; /* Flow control send XON */
1295 bool strict_ieee; /* Strict IEEE mode */
1296 enum ixgbe_fc_type type; /* Type of flow control */
1297 enum ixgbe_fc_type original_type;
1298};
1299
1300/* Statistics counters collected by the MAC */
1301struct ixgbe_hw_stats {
1302 u64 crcerrs;
1303 u64 illerrc;
1304 u64 errbc;
1305 u64 mspdc;
1306 u64 mpctotal;
1307 u64 mpc[8];
1308 u64 mlfc;
1309 u64 mrfc;
1310 u64 rlec;
1311 u64 lxontxc;
1312 u64 lxonrxc;
1313 u64 lxofftxc;
1314 u64 lxoffrxc;
1315 u64 pxontxc[8];
1316 u64 pxonrxc[8];
1317 u64 pxofftxc[8];
1318 u64 pxoffrxc[8];
1319 u64 prc64;
1320 u64 prc127;
1321 u64 prc255;
1322 u64 prc511;
1323 u64 prc1023;
1324 u64 prc1522;
1325 u64 gprc;
1326 u64 bprc;
1327 u64 mprc;
1328 u64 gptc;
1329 u64 gorc;
1330 u64 gotc;
1331 u64 rnbc[8];
1332 u64 ruc;
1333 u64 rfc;
1334 u64 roc;
1335 u64 rjc;
1336 u64 mngprc;
1337 u64 mngpdc;
1338 u64 mngptc;
1339 u64 tor;
1340 u64 tpr;
1341 u64 tpt;
1342 u64 ptc64;
1343 u64 ptc127;
1344 u64 ptc255;
1345 u64 ptc511;
1346 u64 ptc1023;
1347 u64 ptc1522;
1348 u64 mptc;
1349 u64 bptc;
1350 u64 xec;
1351 u64 rqsmr[16];
1352 u64 tqsmr[8];
1353 u64 qprc[16];
1354 u64 qptc[16];
1355 u64 qbrc[16];
1356 u64 qbtc[16];
1357};
1358
1359/* forward declaration */
1360struct ixgbe_hw;
1361
2c5645cf
CL		 1362/* iterator type for walking multicast address lists */
1363typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
1364 u32 *vmdq);
1365
c44ade9e
JB		 1366/* Function pointer table */
1367struct ixgbe_eeprom_operations {
1368 s32 (*init_params)(struct ixgbe_hw *);
1369 s32 (*read)(struct ixgbe_hw *, u16, u16 *);
1370 s32 (*write)(struct ixgbe_hw *, u16, u16);
1371 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
1372 s32 (*update_checksum)(struct ixgbe_hw *);
1373};
1374
9a799d71 1375struct ixgbe_mac_operations {
c44ade9e
JB		 1376 s32 (*init_hw)(struct ixgbe_hw *);
1377 s32 (*reset_hw)(struct ixgbe_hw *);
1378 s32 (*start_hw)(struct ixgbe_hw *);
1379 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
9a799d71 1380 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
c44ade9e
JB		 1381 s32 (*get_supported_physical_layer)(struct ixgbe_hw *);
1382 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
1383 s32 (*stop_adapter)(struct ixgbe_hw *);
1384 s32 (*get_bus_info)(struct ixgbe_hw *);
1385 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
1386 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
1387
1388 /* Link */
3957d63d 1389 s32 (*setup_link)(struct ixgbe_hw *);
c44ade9e
JB		 1390 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
1391 bool);
1392 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
1393 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
1394 bool *);
1395
1396 /* LED */
1397 s32 (*led_on)(struct ixgbe_hw *, u32);
1398 s32 (*led_off)(struct ixgbe_hw *, u32);
1399 s32 (*blink_led_start)(struct ixgbe_hw *, u32);
1400 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
1401
1402 /* RAR, Multicast, VLAN */
1403 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
1404 s32 (*clear_rar)(struct ixgbe_hw *, u32);
1405 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
1406 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
1407 s32 (*init_rx_addrs)(struct ixgbe_hw *);
1408 s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
1409 ixgbe_mc_addr_itr);
1410 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
1411 ixgbe_mc_addr_itr);
1412 s32 (*enable_mc)(struct ixgbe_hw *);
1413 s32 (*disable_mc)(struct ixgbe_hw *);
1414 s32 (*clear_vfta)(struct ixgbe_hw *);
1415 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
1416 s32 (*init_uta_tables)(struct ixgbe_hw *);
1417
1418 /* Flow Control */
1419 s32 (*setup_fc)(struct ixgbe_hw *, s32);
9a799d71
AK		 1420};
1421
1422struct ixgbe_phy_operations {
c44ade9e
JB		 1423 s32 (*identify)(struct ixgbe_hw *);
1424 s32 (*identify_sfp)(struct ixgbe_hw *);
1425 s32 (*reset)(struct ixgbe_hw *);
1426 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
1427 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
3957d63d 1428 s32 (*setup_link)(struct ixgbe_hw *);
c44ade9e
JB		 1429 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
1430 bool);
0befdb3e
JB		 1431 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
1432 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
c44ade9e
JB		 1433 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
1434 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
1435 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
1436 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
9a799d71
AK		 1437};
1438
9a799d71 1439struct ixgbe_eeprom_info {
c44ade9e
JB		 1440 struct ixgbe_eeprom_operations ops;
1441 enum ixgbe_eeprom_type type;
1442 u32 semaphore_delay;
1443 u16 word_size;
1444 u16 address_bits;
9a799d71
AK		 1445};
1446
c44ade9e
JB		 1447struct ixgbe_mac_info {
1448 struct ixgbe_mac_operations ops;
1449 enum ixgbe_mac_type type;
1450 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
1451 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
1452 s32 mc_filter_type;
1453 u32 mcft_size;
1454 u32 vft_size;
1455 u32 num_rar_entries;
1456 u32 max_tx_queues;
1457 u32 max_rx_queues;
eb7f139c 1458 u32 max_msix_vectors;
c44ade9e
JB		 1459 u32 link_attach_type;
1460 u32 link_mode_select;
1461 bool link_settings_loaded;
1462 bool autoneg;
1463 bool autoneg_failed;
9a799d71
AK		 1464};
1465
c44ade9e
JB		 1466struct ixgbe_phy_info {
1467 struct ixgbe_phy_operations ops;
1468 enum ixgbe_phy_type type;
1469 u32 addr;
1470 u32 id;
1471 enum ixgbe_sfp_type sfp_type;
1472 u32 revision;
1473 enum ixgbe_media_type media_type;
1474 bool reset_disable;
1475 ixgbe_autoneg_advertised autoneg_advertised;
1476 bool autoneg_wait_to_complete;
9a799d71
AK		 1477};
1478
1479struct ixgbe_hw {
1480 u8 __iomem *hw_addr;
1481 void *back;
1482 struct ixgbe_mac_info mac;
1483 struct ixgbe_addr_filter_info addr_ctrl;
1484 struct ixgbe_fc_info fc;
1485 struct ixgbe_phy_info phy;
1486 struct ixgbe_eeprom_info eeprom;
1487 u16 device_id;
1488 u16 vendor_id;
1489 u16 subsystem_device_id;
1490 u16 subsystem_vendor_id;
1491 u8 revision_id;
1492 bool adapter_stopped;
1493};
1494
c44ade9e
JB		 1495struct ixgbe_info {
1496 enum ixgbe_mac_type mac;
1497 s32 (*get_invariants)(struct ixgbe_hw *);
1498 struct ixgbe_mac_operations *mac_ops;
1499 struct ixgbe_eeprom_operations *eeprom_ops;
1500 struct ixgbe_phy_operations *phy_ops;
1501};
1502
1503
9a799d71
AK		 1504/* Error Codes */
1505#define IXGBE_ERR_EEPROM -1
1506#define IXGBE_ERR_EEPROM_CHECKSUM -2
1507#define IXGBE_ERR_PHY -3
1508#define IXGBE_ERR_CONFIG -4
1509#define IXGBE_ERR_PARAM -5
1510#define IXGBE_ERR_MAC_TYPE -6
1511#define IXGBE_ERR_UNKNOWN_PHY -7
1512#define IXGBE_ERR_LINK_SETUP -8
1513#define IXGBE_ERR_ADAPTER_STOPPED -9
1514#define IXGBE_ERR_INVALID_MAC_ADDR -10
1515#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
1516#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
1517#define IXGBE_ERR_INVALID_LINK_SETTINGS -13
1518#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
1519#define IXGBE_ERR_RESET_FAILED -15
1520#define IXGBE_ERR_SWFW_SYNC -16
1521#define IXGBE_ERR_PHY_ADDR_INVALID -17
c44ade9e
JB		 1522#define IXGBE_ERR_I2C -18
1523#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
c4900be0 1524#define IXGBE_ERR_SFP_NOT_PRESENT -20
9a799d71
AK		 1525#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
1526
1527#endif /* _IXGBE_TYPE_H_ */
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