[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_phy.c

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2008 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/sched.h>

#include "ixgbe_common.h"
#include "ixgbe_phy.h"

static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);

/**
 *  ixgbe_identify_phy_generic - Get physical layer module
 *  @hw: pointer to hardware structure
 *
 *  Determines the physical layer module found on the current adapter.
 **/
s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
{
	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
	u32 phy_addr;

	if (hw->phy.type == ixgbe_phy_unknown) {
		for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
			if (ixgbe_validate_phy_addr(hw, phy_addr)) {
				hw->phy.addr = phy_addr;
				ixgbe_get_phy_id(hw);
				hw->phy.type =
				        ixgbe_get_phy_type_from_id(hw->phy.id);
				status = 0;
				break;
			}
		}
	} else {
		status = 0;
	}

	return status;
}

/**
 *  ixgbe_validate_phy_addr - Determines phy address is valid
 *  @hw: pointer to hardware structure
 *
 **/
static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
{
	u16 phy_id = 0;
	bool valid = false;

	hw->phy.addr = phy_addr;
	hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
	                     IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);

	if (phy_id != 0xFFFF && phy_id != 0x0)
		valid = true;

	return valid;
}

/**
 *  ixgbe_get_phy_id - Get the phy type
 *  @hw: pointer to hardware structure
 *
 **/
static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
{
	u32 status;
	u16 phy_id_high = 0;
	u16 phy_id_low = 0;

	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
	                              IXGBE_MDIO_PMA_PMD_DEV_TYPE,
	                              &phy_id_high);

	if (status == 0) {
		hw->phy.id = (u32)(phy_id_high << 16);
		status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
		                              IXGBE_MDIO_PMA_PMD_DEV_TYPE,
		                              &phy_id_low);
		hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
		hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
	}
	return status;
}

/**
 *  ixgbe_get_phy_type_from_id - Get the phy type
 *  @hw: pointer to hardware structure
 *
 **/
static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
{
	enum ixgbe_phy_type phy_type;

	switch (phy_id) {
	case TN1010_PHY_ID:
		phy_type = ixgbe_phy_tn;
		break;
	case QT2022_PHY_ID:
		phy_type = ixgbe_phy_qt;
		break;
	default:
		phy_type = ixgbe_phy_unknown;
		break;
	}

	return phy_type;
}

/**
 *  ixgbe_reset_phy_generic - Performs a PHY reset
 *  @hw: pointer to hardware structure
 **/
s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
{
	/*
	 * Perform soft PHY reset to the PHY_XS.
	 * This will cause a soft reset to the PHY
	 */
	return hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
	                             IXGBE_MDIO_PHY_XS_DEV_TYPE,
	                             IXGBE_MDIO_PHY_XS_RESET);
}

/**
 *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 *  @hw: pointer to hardware structure
 *  @reg_addr: 32 bit address of PHY register to read
 *  @phy_data: Pointer to read data from PHY register
 **/
s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
                               u32 device_type, u16 *phy_data)
{
	u32 command;
	u32 i;
	u32 data;
	s32 status = 0;
	u16 gssr;

	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
		gssr = IXGBE_GSSR_PHY1_SM;
	else
		gssr = IXGBE_GSSR_PHY0_SM;

	if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
		status = IXGBE_ERR_SWFW_SYNC;

	if (status == 0) {
		/* Setup and write the address cycle command */
		command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
		           (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
		           (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
		           (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));

		IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);

		/*
		 * Check every 10 usec to see if the address cycle completed.
		 * The MDI Command bit will clear when the operation is
		 * complete
		 */
		for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
			udelay(10);

			command = IXGBE_READ_REG(hw, IXGBE_MSCA);

			if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
				break;
		}

		if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
			hw_dbg(hw, "PHY address command did not complete.\n");
			status = IXGBE_ERR_PHY;
		}

		if (status == 0) {
			/*
			 * Address cycle complete, setup and write the read
			 * command
			 */
			command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
			           (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
			           (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
			           (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));

			IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);

			/*
			 * Check every 10 usec to see if the address cycle
			 * completed. The MDI Command bit will clear when the
			 * operation is complete
			 */
			for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
				udelay(10);

				command = IXGBE_READ_REG(hw, IXGBE_MSCA);

				if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
					break;
			}

			if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
				hw_dbg(hw, "PHY read command didn't complete\n");
				status = IXGBE_ERR_PHY;
			} else {
				/*
				 * Read operation is complete.  Get the data
				 * from MSRWD
				 */
				data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
				data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
				*phy_data = (u16)(data);
			}
		}

		ixgbe_release_swfw_sync(hw, gssr);
	}

	return status;
}

/**
 *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 *  @hw: pointer to hardware structure
 *  @reg_addr: 32 bit PHY register to write
 *  @device_type: 5 bit device type
 *  @phy_data: Data to write to the PHY register
 **/
s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
                                u32 device_type, u16 phy_data)
{
	u32 command;
	u32 i;
	s32 status = 0;
	u16 gssr;

	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
		gssr = IXGBE_GSSR_PHY1_SM;
	else
		gssr = IXGBE_GSSR_PHY0_SM;

	if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
		status = IXGBE_ERR_SWFW_SYNC;

	if (status == 0) {
		/* Put the data in the MDI single read and write data register*/
		IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);

		/* Setup and write the address cycle command */
		command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
		           (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
		           (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
		           (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));

		IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);

		/*
		 * Check every 10 usec to see if the address cycle completed.
		 * The MDI Command bit will clear when the operation is
		 * complete
		 */
		for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
			udelay(10);

			command = IXGBE_READ_REG(hw, IXGBE_MSCA);

			if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
				break;
		}

		if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
			hw_dbg(hw, "PHY address cmd didn't complete\n");
			status = IXGBE_ERR_PHY;
		}

		if (status == 0) {
			/*
			 * Address cycle complete, setup and write the write
			 * command
			 */
			command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
			           (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
			           (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
			           (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));

			IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);

			/*
			 * Check every 10 usec to see if the address cycle
			 * completed. The MDI Command bit will clear when the
			 * operation is complete
			 */
			for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
				udelay(10);

				command = IXGBE_READ_REG(hw, IXGBE_MSCA);

				if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
					break;
			}

			if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
				hw_dbg(hw, "PHY address cmd didn't complete\n");
				status = IXGBE_ERR_PHY;
			}
		}

		ixgbe_release_swfw_sync(hw, gssr);
	}

	return status;
}

/**
 *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 *  @hw: pointer to hardware structure
 *
 *  Restart autonegotiation and PHY and waits for completion.
 **/
s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
{
	s32 status = IXGBE_NOT_IMPLEMENTED;
	u32 time_out;
	u32 max_time_out = 10;
	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;

	/*
	 * Set advertisement settings in PHY based on autoneg_advertised
	 * settings. If autoneg_advertised = 0, then advertise default values
	 * tnx devices cannot be "forced" to a autoneg 10G and fail.  But can
	 * for a 1G.
	 */
	hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
	                     IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);

	if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
		autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */
	else
		autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */

	hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
	                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);

	/* Restart PHY autonegotiation and wait for completion */
	hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
	                     IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);

	autoneg_reg |= IXGBE_MII_RESTART;

	hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
	                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);

	/* Wait for autonegotiation to finish */
	for (time_out = 0; time_out < max_time_out; time_out++) {
		udelay(10);
		/* Restart PHY autonegotiation and wait for completion */
		status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
		                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
		                              &autoneg_reg);

		autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
		if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
			status = 0;
			break;
		}
	}

	if (time_out == max_time_out)
		status = IXGBE_ERR_LINK_SETUP;

	return status;
}

/**
 *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 *  @hw: pointer to hardware structure
 *  @speed: new link speed
 *  @autoneg: true if autonegotiation enabled
 **/
s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
                                       ixgbe_link_speed speed,
                                       bool autoneg,
                                       bool autoneg_wait_to_complete)
{

	/*
	 * Clear autoneg_advertised and set new values based on input link
	 * speed.
	 */
	hw->phy.autoneg_advertised = 0;

	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;

	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;

	/* Setup link based on the new speed settings */
	hw->phy.ops.setup_link(hw);

	return 0;
}

/**
 *  ixgbe_check_phy_link_tnx - Determine link and speed status
 *  @hw: pointer to hardware structure
 *
 *  Reads the VS1 register to determine if link is up and the current speed for
 *  the PHY.
 **/
s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
                             bool *link_up)
{
	s32 status = 0;
	u32 time_out;
	u32 max_time_out = 10;
	u16 phy_link = 0;
	u16 phy_speed = 0;
	u16 phy_data = 0;

	/* Initialize speed and link to default case */
	*link_up = false;
	*speed = IXGBE_LINK_SPEED_10GB_FULL;

	/*
	 * Check current speed and link status of the PHY register.
	 * This is a vendor specific register and may have to
	 * be changed for other copper PHYs.
	 */
	for (time_out = 0; time_out < max_time_out; time_out++) {
		udelay(10);
		status = hw->phy.ops.read_reg(hw,
		                        IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
		                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
		                        &phy_data);
		phy_link = phy_data &
		           IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
		phy_speed = phy_data &
		            IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
		if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
			*link_up = true;
			if (phy_speed ==
			    IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
				*speed = IXGBE_LINK_SPEED_1GB_FULL;
			break;
		}
	}

	return status;
}

/**
 *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 *  @hw: pointer to hardware structure
 *  @firmware_version: pointer to the PHY Firmware Version
 **/
s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
                                       u16 *firmware_version)
{
	s32 status = 0;

	status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
	                              IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
	                              firmware_version);

	return status;
}
Commit	Line	Data
9a799d71 AK	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
b4617240	4	Copyright(c) 1999 - 2008 Intel Corporation.
9a799d71 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
9a799d71 AK	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#include <linux/pci.h>
	29	#include <linux/delay.h>
	30	#include <linux/sched.h>
	31
	32	#include "ixgbe_common.h"
	33	#include "ixgbe_phy.h"
	34
c44ade9e	35	static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
9a799d71 AK	36	static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
9a799d71 AK	37	static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
9a799d71 AK	38
9a799d71 AK	39	/**
c44ade9e	40	* ixgbe_identify_phy_generic - Get physical layer module
9a799d71 AK	41	* @hw: pointer to hardware structure
	42	*
	43	* Determines the physical layer module found on the current adapter.
	44	**/
c44ade9e	45	s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
9a799d71 AK	46	{
	47	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
	48	u32 phy_addr;
	49
c44ade9e JB	50	if (hw->phy.type == ixgbe_phy_unknown) {
	51	for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
	52	if (ixgbe_validate_phy_addr(hw, phy_addr)) {
	53	hw->phy.addr = phy_addr;
	54	ixgbe_get_phy_id(hw);
	55	hw->phy.type =
	56	ixgbe_get_phy_type_from_id(hw->phy.id);
	57	status = 0;
	58	break;
	59	}
9a799d71	60	}
c44ade9e JB	61	} else {
c44ade9e JB	62	status = 0;
9a799d71	63	}
c44ade9e	64
9a799d71 AK	65	return status;
	66	}
	67
	68	/**
	69	* ixgbe_validate_phy_addr - Determines phy address is valid
	70	* @hw: pointer to hardware structure
	71	*
	72	**/
	73	static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
	74	{
	75	u16 phy_id = 0;
	76	bool valid = false;
	77
	78	hw->phy.addr = phy_addr;
c44ade9e JB	79	hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
c44ade9e JB	80	IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
9a799d71 AK	81
	82	if (phy_id != 0xFFFF && phy_id != 0x0)
	83	valid = true;
	84
	85	return valid;
	86	}
	87
	88	/**
	89	* ixgbe_get_phy_id - Get the phy type
	90	* @hw: pointer to hardware structure
	91	*
	92	**/
	93	static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
	94	{
	95	u32 status;
	96	u16 phy_id_high = 0;
	97	u16 phy_id_low = 0;
	98
c44ade9e JB	99	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
	100	IXGBE_MDIO_PMA_PMD_DEV_TYPE,
	101	&phy_id_high);
9a799d71 AK	102
	103	if (status == 0) {
	104	hw->phy.id = (u32)(phy_id_high << 16);
c44ade9e JB	105	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
	106	IXGBE_MDIO_PMA_PMD_DEV_TYPE,
	107	&phy_id_low);
9a799d71 AK	108	hw->phy.id \|= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
	109	hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
	110	}
9a799d71 AK	111	return status;
	112	}
	113
	114	/**
	115	* ixgbe_get_phy_type_from_id - Get the phy type
	116	* @hw: pointer to hardware structure
	117	*
	118	**/
	119	static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
	120	{
	121	enum ixgbe_phy_type phy_type;
	122
	123	switch (phy_id) {
0befdb3e JB	124	case TN1010_PHY_ID:
	125	phy_type = ixgbe_phy_tn;
	126	break;
9a799d71 AK	127	case QT2022_PHY_ID:
	128	phy_type = ixgbe_phy_qt;
	129	break;
	130	default:
	131	phy_type = ixgbe_phy_unknown;
	132	break;
	133	}
	134
	135	return phy_type;
	136	}
	137
	138	/**
c44ade9e	139	* ixgbe_reset_phy_generic - Performs a PHY reset
9a799d71 AK	140	* @hw: pointer to hardware structure
9a799d71 AK	141	**/
c44ade9e	142	s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
9a799d71 AK	143	{
	144	/*
	145	* Perform soft PHY reset to the PHY_XS.
	146	* This will cause a soft reset to the PHY
	147	*/
c44ade9e JB	148	return hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
	149	IXGBE_MDIO_PHY_XS_DEV_TYPE,
	150	IXGBE_MDIO_PHY_XS_RESET);
9a799d71 AK	151	}
	152
	153	/**
c44ade9e	154	* ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
9a799d71 AK	155	* @hw: pointer to hardware structure
	156	* @reg_addr: 32 bit address of PHY register to read
	157	* @phy_data: Pointer to read data from PHY register
	158	**/
c44ade9e JB	159	s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
c44ade9e JB	160	u32 device_type, u16 *phy_data)
9a799d71 AK	161	{
	162	u32 command;
	163	u32 i;
9a799d71 AK	164	u32 data;
	165	s32 status = 0;
	166	u16 gssr;
	167
	168	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
	169	gssr = IXGBE_GSSR_PHY1_SM;
	170	else
	171	gssr = IXGBE_GSSR_PHY0_SM;
	172
	173	if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
	174	status = IXGBE_ERR_SWFW_SYNC;
	175
	176	if (status == 0) {
	177	/* Setup and write the address cycle command */
	178	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) \|
c44ade9e JB	179	(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
	180	(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) \|
	181	(IXGBE_MSCA_ADDR_CYCLE \| IXGBE_MSCA_MDI_COMMAND));
9a799d71 AK	182
	183	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
	184
	185	/*
	186	* Check every 10 usec to see if the address cycle completed.
	187	* The MDI Command bit will clear when the operation is
	188	* complete
	189	*/
c44ade9e	190	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71 AK	191	udelay(10);
	192
	193	command = IXGBE_READ_REG(hw, IXGBE_MSCA);
	194
	195	if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
	196	break;
	197	}
	198
	199	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
	200	hw_dbg(hw, "PHY address command did not complete.\n");
	201	status = IXGBE_ERR_PHY;
	202	}
	203
	204	if (status == 0) {
	205	/*
	206	* Address cycle complete, setup and write the read
	207	* command
	208	*/
	209	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) \|
c44ade9e JB	210	(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
	211	(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) \|
	212	(IXGBE_MSCA_READ \| IXGBE_MSCA_MDI_COMMAND));
9a799d71 AK	213
	214	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
	215
	216	/*
	217	* Check every 10 usec to see if the address cycle
	218	* completed. The MDI Command bit will clear when the
	219	* operation is complete
	220	*/
c44ade9e	221	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71 AK	222	udelay(10);
	223
	224	command = IXGBE_READ_REG(hw, IXGBE_MSCA);
	225
	226	if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
	227	break;
	228	}
	229
	230	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
c44ade9e	231	hw_dbg(hw, "PHY read command didn't complete\n");
9a799d71 AK	232	status = IXGBE_ERR_PHY;
	233	} else {
	234	/*
	235	* Read operation is complete. Get the data
	236	* from MSRWD
	237	*/
	238	data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
	239	data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
	240	*phy_data = (u16)(data);
	241	}
	242	}
	243
	244	ixgbe_release_swfw_sync(hw, gssr);
	245	}
c44ade9e	246
9a799d71 AK	247	return status;
	248	}
	249
	250	/**
c44ade9e	251	* ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
9a799d71 AK	252	* @hw: pointer to hardware structure
	253	* @reg_addr: 32 bit PHY register to write
	254	* @device_type: 5 bit device type
	255	* @phy_data: Data to write to the PHY register
	256	**/
c44ade9e JB	257	s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
c44ade9e JB	258	u32 device_type, u16 phy_data)
9a799d71 AK	259	{
	260	u32 command;
	261	u32 i;
9a799d71 AK	262	s32 status = 0;
	263	u16 gssr;
	264
	265	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
	266	gssr = IXGBE_GSSR_PHY1_SM;
	267	else
	268	gssr = IXGBE_GSSR_PHY0_SM;
	269
	270	if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
	271	status = IXGBE_ERR_SWFW_SYNC;
	272
	273	if (status == 0) {
	274	/* Put the data in the MDI single read and write data register*/
	275	IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
	276
	277	/* Setup and write the address cycle command */
	278	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) \|
c44ade9e JB	279	(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
	280	(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) \|
	281	(IXGBE_MSCA_ADDR_CYCLE \| IXGBE_MSCA_MDI_COMMAND));
9a799d71 AK	282
	283	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
	284
	285	/*
	286	* Check every 10 usec to see if the address cycle completed.
	287	* The MDI Command bit will clear when the operation is
	288	* complete
	289	*/
c44ade9e	290	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71 AK	291	udelay(10);
	292
	293	command = IXGBE_READ_REG(hw, IXGBE_MSCA);
	294
c44ade9e	295	if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71	296	break;
9a799d71 AK	297	}
9a799d71 AK	298
c44ade9e JB	299	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
c44ade9e JB	300	hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71	301	status = IXGBE_ERR_PHY;
c44ade9e	302	}
9a799d71 AK	303
	304	if (status == 0) {
	305	/*
	306	* Address cycle complete, setup and write the write
	307	* command
	308	*/
	309	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) \|
c44ade9e JB	310	(device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
	311	(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) \|
	312	(IXGBE_MSCA_WRITE \| IXGBE_MSCA_MDI_COMMAND));
9a799d71 AK	313
	314	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
	315
	316	/*
	317	* Check every 10 usec to see if the address cycle
	318	* completed. The MDI Command bit will clear when the
	319	* operation is complete
	320	*/
c44ade9e	321	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71 AK	322	udelay(10);
	323
	324	command = IXGBE_READ_REG(hw, IXGBE_MSCA);
	325
c44ade9e	326	if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71	327	break;
9a799d71 AK	328	}
9a799d71 AK	329
c44ade9e JB	330	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
c44ade9e JB	331	hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71	332	status = IXGBE_ERR_PHY;
c44ade9e	333	}
9a799d71 AK	334	}
	335
	336	ixgbe_release_swfw_sync(hw, gssr);
	337	}
	338
	339	return status;
	340	}
	341
	342	/**
c44ade9e	343	* ixgbe_setup_phy_link_generic - Set and restart autoneg
9a799d71 AK	344	* @hw: pointer to hardware structure
	345	*
	346	* Restart autonegotiation and PHY and waits for completion.
	347	**/
c44ade9e	348	s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
9a799d71 AK	349	{
	350	s32 status = IXGBE_NOT_IMPLEMENTED;
	351	u32 time_out;
	352	u32 max_time_out = 10;
c44ade9e	353	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
9a799d71 AK	354
	355	/*
	356	* Set advertisement settings in PHY based on autoneg_advertised
	357	* settings. If autoneg_advertised = 0, then advertise default values
c44ade9e	358	* tnx devices cannot be "forced" to a autoneg 10G and fail. But can
9a799d71 AK	359	* for a 1G.
9a799d71 AK	360	*/
c44ade9e JB	361	hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
c44ade9e JB	362	IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
9a799d71 AK	363
	364	if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
	365	autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */
	366	else
	367	autoneg_reg \|= 0x1000; /* 1 in bit 12 is 10G/1G operation */
	368
c44ade9e JB	369	hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
c44ade9e JB	370	IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
9a799d71 AK	371
9a799d71 AK	372	/* Restart PHY autonegotiation and wait for completion */
c44ade9e JB	373	hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
c44ade9e JB	374	IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
9a799d71	375
c44ade9e	376	autoneg_reg \|= IXGBE_MII_RESTART;
9a799d71	377
c44ade9e JB	378	hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
c44ade9e JB	379	IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
9a799d71 AK	380
	381	/* Wait for autonegotiation to finish */
	382	for (time_out = 0; time_out < max_time_out; time_out++) {
	383	udelay(10);
	384	/* Restart PHY autonegotiation and wait for completion */
c44ade9e JB	385	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
	386	IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
	387	&autoneg_reg);
9a799d71	388
c44ade9e JB	389	autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
c44ade9e JB	390	if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
9a799d71 AK	391	status = 0;
	392	break;
	393	}
	394	}
	395
	396	if (time_out == max_time_out)
	397	status = IXGBE_ERR_LINK_SETUP;
	398
	399	return status;
	400	}
	401
	402	/**
c44ade9e	403	* ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
9a799d71 AK	404	* @hw: pointer to hardware structure
	405	* @speed: new link speed
	406	* @autoneg: true if autonegotiation enabled
	407	**/
c44ade9e JB	408	s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
	409	ixgbe_link_speed speed,
	410	bool autoneg,
	411	bool autoneg_wait_to_complete)
9a799d71	412	{
c44ade9e	413
9a799d71 AK	414	/*
	415	* Clear autoneg_advertised and set new values based on input link
	416	* speed.
	417	*/
	418	hw->phy.autoneg_advertised = 0;
	419
	420	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
	421	hw->phy.autoneg_advertised \|= IXGBE_LINK_SPEED_10GB_FULL;
c44ade9e	422
9a799d71 AK	423	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
	424	hw->phy.autoneg_advertised \|= IXGBE_LINK_SPEED_1GB_FULL;
	425
	426	/* Setup link based on the new speed settings */
c44ade9e	427	hw->phy.ops.setup_link(hw);
9a799d71 AK	428
	429	return 0;
	430	}
c44ade9e	431
0befdb3e JB	432	/**
	433	* ixgbe_check_phy_link_tnx - Determine link and speed status
	434	* @hw: pointer to hardware structure
	435	*
	436	* Reads the VS1 register to determine if link is up and the current speed for
	437	* the PHY.
	438	**/
	439	s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw hw, ixgbe_link_speed speed,
	440	bool *link_up)
	441	{
	442	s32 status = 0;
	443	u32 time_out;
	444	u32 max_time_out = 10;
	445	u16 phy_link = 0;
	446	u16 phy_speed = 0;
	447	u16 phy_data = 0;
	448
	449	/* Initialize speed and link to default case */
	450	*link_up = false;
	451	*speed = IXGBE_LINK_SPEED_10GB_FULL;
	452
	453	/*
	454	* Check current speed and link status of the PHY register.
	455	* This is a vendor specific register and may have to
	456	* be changed for other copper PHYs.
	457	*/
	458	for (time_out = 0; time_out < max_time_out; time_out++) {
	459	udelay(10);
	460	status = hw->phy.ops.read_reg(hw,
	461	IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
	462	IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
	463	&phy_data);
	464	phy_link = phy_data &
	465	IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
	466	phy_speed = phy_data &
	467	IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
	468	if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
	469	*link_up = true;
	470	if (phy_speed ==
	471	IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
	472	*speed = IXGBE_LINK_SPEED_1GB_FULL;
	473	break;
	474	}
	475	}
	476
	477	return status;
	478	}
	479
	480	/**
	481	* ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
	482	* @hw: pointer to hardware structure
	483	* @firmware_version: pointer to the PHY Firmware Version
	484	**/
	485	s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
	486	u16 *firmware_version)
	487	{
	488	s32 status = 0;
	489
	490	status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
	491	IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
	492	firmware_version);
	493
	494	return status;
	495	}
496