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ixgbe: Add support for dcbnl_rtnl_ops.setapp/getapp
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_fcoe.c
CommitLineData
d3a2ae6d
YZ		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28
29#include "ixgbe.h"
6ee16520
YZ		 30#ifdef CONFIG_IXGBE_DCB
31#include "ixgbe_dcb_82599.h"
32#endif /* CONFIG_IXGBE_DCB */
d3a2ae6d
YZ		 33#include <linux/if_ether.h>
34#include <scsi/scsi_cmnd.h>
35#include <scsi/scsi_device.h>
36#include <scsi/fc/fc_fs.h>
37#include <scsi/fc/fc_fcoe.h>
38#include <scsi/libfc.h>
39#include <scsi/libfcoe.h>
40
d0ed8937
YZ		 41/**
42 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
43 * @rx_desc: advanced rx descriptor
44 *
45 * Returns : true if it is FCoE pkt
46 */
47static inline bool ixgbe_rx_is_fcoe(union ixgbe_adv_rx_desc *rx_desc)
48{
49 u16 p;
50
51 p = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info);
52 if (p & IXGBE_RXDADV_PKTTYPE_ETQF) {
53 p &= IXGBE_RXDADV_PKTTYPE_ETQF_MASK;
54 p >>= IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT;
55 return p == IXGBE_ETQF_FILTER_FCOE;
56 }
57 return false;
58}
59
60/**
61 * ixgbe_fcoe_clear_ddp - clear the given ddp context
62 * @ddp - ptr to the ixgbe_fcoe_ddp
63 *
64 * Returns : none
65 *
66 */
67static inline void ixgbe_fcoe_clear_ddp(struct ixgbe_fcoe_ddp *ddp)
68{
69 ddp->len = 0;
70 ddp->err = 0;
71 ddp->udl = NULL;
72 ddp->udp = 0UL;
73 ddp->sgl = NULL;
74 ddp->sgc = 0;
75}
76
77/**
78 * ixgbe_fcoe_ddp_put - free the ddp context for a given xid
79 * @netdev: the corresponding net_device
80 * @xid: the xid that corresponding ddp will be freed
81 *
82 * This is the implementation of net_device_ops.ndo_fcoe_ddp_done
83 * and it is expected to be called by ULD, i.e., FCP layer of libfc
84 * to release the corresponding ddp context when the I/O is done.
85 *
86 * Returns : data length already ddp-ed in bytes
87 */
88int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid)
89{
90 int len = 0;
91 struct ixgbe_fcoe *fcoe;
92 struct ixgbe_adapter *adapter;
93 struct ixgbe_fcoe_ddp *ddp;
94
95 if (!netdev)
96 goto out_ddp_put;
97
98 if (xid >= IXGBE_FCOE_DDP_MAX)
99 goto out_ddp_put;
100
101 adapter = netdev_priv(netdev);
102 fcoe = &adapter->fcoe;
103 ddp = &fcoe->ddp[xid];
104 if (!ddp->udl)
105 goto out_ddp_put;
106
107 len = ddp->len;
108 /* if there an error, force to invalidate ddp context */
109 if (ddp->err) {
110 spin_lock_bh(&fcoe->lock);
111 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCFLT, 0);
112 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCFLTRW,
113 (xid | IXGBE_FCFLTRW_WE));
114 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCBUFF, 0);
115 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCDMARW,
116 (xid | IXGBE_FCDMARW_WE));
117 spin_unlock_bh(&fcoe->lock);
118 }
119 if (ddp->sgl)
120 pci_unmap_sg(adapter->pdev, ddp->sgl, ddp->sgc,
121 DMA_FROM_DEVICE);
122 pci_pool_free(fcoe->pool, ddp->udl, ddp->udp);
123 ixgbe_fcoe_clear_ddp(ddp);
124
125out_ddp_put:
126 return len;
127}
128
129/**
130 * ixgbe_fcoe_ddp_get - called to set up ddp context
131 * @netdev: the corresponding net_device
132 * @xid: the exchange id requesting ddp
133 * @sgl: the scatter-gather list for this request
134 * @sgc: the number of scatter-gather items
135 *
136 * This is the implementation of net_device_ops.ndo_fcoe_ddp_setup
137 * and is expected to be called from ULD, e.g., FCP layer of libfc
138 * to set up ddp for the corresponding xid of the given sglist for
139 * the corresponding I/O.
140 *
141 * Returns : 1 for success and 0 for no ddp
142 */
143int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
144 struct scatterlist *sgl, unsigned int sgc)
145{
146 struct ixgbe_adapter *adapter;
147 struct ixgbe_hw *hw;
148 struct ixgbe_fcoe *fcoe;
149 struct ixgbe_fcoe_ddp *ddp;
150 struct scatterlist *sg;
151 unsigned int i, j, dmacount;
152 unsigned int len;
153 static const unsigned int bufflen = 4096;
154 unsigned int firstoff = 0;
155 unsigned int lastsize;
156 unsigned int thisoff = 0;
157 unsigned int thislen = 0;
158 u32 fcbuff, fcdmarw, fcfltrw;
159 dma_addr_t addr;
160
161 if (!netdev || !sgl)
162 return 0;
163
164 adapter = netdev_priv(netdev);
165 if (xid >= IXGBE_FCOE_DDP_MAX) {
166 DPRINTK(DRV, WARNING, "xid=0x%x out-of-range\n", xid);
167 return 0;
168 }
169
170 fcoe = &adapter->fcoe;
171 if (!fcoe->pool) {
172 DPRINTK(DRV, WARNING, "xid=0x%x no ddp pool for fcoe\n", xid);
173 return 0;
174 }
175
176 ddp = &fcoe->ddp[xid];
177 if (ddp->sgl) {
178 DPRINTK(DRV, ERR, "xid 0x%x w/ non-null sgl=%p nents=%d\n",
179 xid, ddp->sgl, ddp->sgc);
180 return 0;
181 }
182 ixgbe_fcoe_clear_ddp(ddp);
183
184 /* setup dma from scsi command sgl */
185 dmacount = pci_map_sg(adapter->pdev, sgl, sgc, DMA_FROM_DEVICE);
186 if (dmacount == 0) {
187 DPRINTK(DRV, ERR, "xid 0x%x DMA map error\n", xid);
188 return 0;
189 }
190
191 /* alloc the udl from our ddp pool */
192 ddp->udl = pci_pool_alloc(fcoe->pool, GFP_KERNEL, &ddp->udp);
193 if (!ddp->udl) {
194 DPRINTK(DRV, ERR, "failed allocated ddp context\n");
195 goto out_noddp_unmap;
196 }
197 ddp->sgl = sgl;
198 ddp->sgc = sgc;
199
200 j = 0;
201 for_each_sg(sgl, sg, dmacount, i) {
202 addr = sg_dma_address(sg);
203 len = sg_dma_len(sg);
204 while (len) {
205 /* get the offset of length of current buffer */
206 thisoff = addr & ((dma_addr_t)bufflen - 1);
207 thislen = min((bufflen - thisoff), len);
208 /*
209 * all but the 1st buffer (j == 0)
210 * must be aligned on bufflen
211 */
212 if ((j != 0) && (thisoff))
213 goto out_noddp_free;
214 /*
215 * all but the last buffer
216 * ((i == (dmacount - 1)) && (thislen == len))
217 * must end at bufflen
218 */
219 if (((i != (dmacount - 1)) || (thislen != len))
220 && ((thislen + thisoff) != bufflen))
221 goto out_noddp_free;
222
223 ddp->udl[j] = (u64)(addr - thisoff);
224 /* only the first buffer may have none-zero offset */
225 if (j == 0)
226 firstoff = thisoff;
227 len -= thislen;
228 addr += thislen;
229 j++;
230 /* max number of buffers allowed in one DDP context */
231 if (j > IXGBE_BUFFCNT_MAX) {
232 DPRINTK(DRV, ERR, "xid=%x:%d,%d,%d:addr=%llx "
233 "not enough descriptors\n",
234 xid, i, j, dmacount, (u64)addr);
235 goto out_noddp_free;
236 }
237 }
238 }
239 /* only the last buffer may have non-full bufflen */
240 lastsize = thisoff + thislen;
241
242 fcbuff = (IXGBE_FCBUFF_4KB << IXGBE_FCBUFF_BUFFSIZE_SHIFT);
243 fcbuff |= (j << IXGBE_FCBUFF_BUFFCNT_SHIFT);
244 fcbuff |= (firstoff << IXGBE_FCBUFF_OFFSET_SHIFT);
245 fcbuff |= (IXGBE_FCBUFF_VALID);
246
247 fcdmarw = xid;
248 fcdmarw |= IXGBE_FCDMARW_WE;
249 fcdmarw |= (lastsize << IXGBE_FCDMARW_LASTSIZE_SHIFT);
250
251 fcfltrw = xid;
252 fcfltrw |= IXGBE_FCFLTRW_WE;
253
254 /* program DMA context */
255 hw = &adapter->hw;
256 spin_lock_bh(&fcoe->lock);
8e20ce94 257 IXGBE_WRITE_REG(hw, IXGBE_FCPTRL, ddp->udp & DMA_BIT_MASK(32));
d0ed8937
YZ		 258 IXGBE_WRITE_REG(hw, IXGBE_FCPTRH, (u64)ddp->udp >> 32);
259 IXGBE_WRITE_REG(hw, IXGBE_FCBUFF, fcbuff);
260 IXGBE_WRITE_REG(hw, IXGBE_FCDMARW, fcdmarw);
261 /* program filter context */
262 IXGBE_WRITE_REG(hw, IXGBE_FCPARAM, 0);
263 IXGBE_WRITE_REG(hw, IXGBE_FCFLT, IXGBE_FCFLT_VALID);
264 IXGBE_WRITE_REG(hw, IXGBE_FCFLTRW, fcfltrw);
265 spin_unlock_bh(&fcoe->lock);
266
267 return 1;
268
269out_noddp_free:
270 pci_pool_free(fcoe->pool, ddp->udl, ddp->udp);
271 ixgbe_fcoe_clear_ddp(ddp);
272
273out_noddp_unmap:
274 pci_unmap_sg(adapter->pdev, sgl, sgc, DMA_FROM_DEVICE);
275 return 0;
276}
277
278/**
279 * ixgbe_fcoe_ddp - check ddp status and mark it done
280 * @adapter: ixgbe adapter
281 * @rx_desc: advanced rx descriptor
282 * @skb: the skb holding the received data
283 *
284 * This checks ddp status.
285 *
3d8fd385
YZ		 286 * Returns : < 0 indicates an error or not a FCiE ddp, 0 indicates
287 * not passing the skb to ULD, > 0 indicates is the length of data
288 * being ddped.
d0ed8937
YZ		 289 */
290int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
291 union ixgbe_adv_rx_desc *rx_desc,
292 struct sk_buff *skb)
293{
294 u16 xid;
295 u32 sterr, fceofe, fcerr, fcstat;
296 int rc = -EINVAL;
297 struct ixgbe_fcoe *fcoe;
298 struct ixgbe_fcoe_ddp *ddp;
299 struct fc_frame_header *fh;
300
301 if (!ixgbe_rx_is_fcoe(rx_desc))
302 goto ddp_out;
303
304 skb->ip_summed = CHECKSUM_UNNECESSARY;
305 sterr = le32_to_cpu(rx_desc->wb.upper.status_error);
306 fcerr = (sterr & IXGBE_RXDADV_ERR_FCERR);
307 fceofe = (sterr & IXGBE_RXDADV_ERR_FCEOFE);
308 if (fcerr == IXGBE_FCERR_BADCRC)
309 skb->ip_summed = CHECKSUM_NONE;
310
311 skb_reset_network_header(skb);
312 skb_set_transport_header(skb, skb_network_offset(skb) +
313 sizeof(struct fcoe_hdr));
314 fh = (struct fc_frame_header *)skb_transport_header(skb);
315 xid = be16_to_cpu(fh->fh_ox_id);
316 if (xid >= IXGBE_FCOE_DDP_MAX)
317 goto ddp_out;
318
319 fcoe = &adapter->fcoe;
320 ddp = &fcoe->ddp[xid];
321 if (!ddp->udl)
322 goto ddp_out;
323
324 ddp->err = (fcerr | fceofe);
325 if (ddp->err)
326 goto ddp_out;
327
328 fcstat = (sterr & IXGBE_RXDADV_STAT_FCSTAT);
329 if (fcstat) {
330 /* update length of DDPed data */
331 ddp->len = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
332 /* unmap the sg list when FCP_RSP is received */
333 if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_FCPRSP) {
334 pci_unmap_sg(adapter->pdev, ddp->sgl,
335 ddp->sgc, DMA_FROM_DEVICE);
336 ddp->sgl = NULL;
337 ddp->sgc = 0;
338 }
339 /* return 0 to bypass going to ULD for DDPed data */
340 if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_DDP)
341 rc = 0;
17e78b06 342 else if (ddp->len)
3d8fd385 343 rc = ddp->len;
d0ed8937
YZ		 344 }
345
346ddp_out:
347 return rc;
348}
349
bc079228
YZ		 350/**
351 * ixgbe_fso - ixgbe FCoE Sequence Offload (FSO)
352 * @adapter: ixgbe adapter
353 * @tx_ring: tx desc ring
354 * @skb: associated skb
355 * @tx_flags: tx flags
356 * @hdr_len: hdr_len to be returned
357 *
358 * This sets up large send offload for FCoE
359 *
360 * Returns : 0 indicates no FSO, > 0 for FSO, < 0 for error
361 */
362int ixgbe_fso(struct ixgbe_adapter *adapter,
363 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
364 u32 tx_flags, u8 *hdr_len)
365{
366 u8 sof, eof;
367 u32 vlan_macip_lens;
368 u32 fcoe_sof_eof;
369 u32 type_tucmd;
370 u32 mss_l4len_idx;
371 int mss = 0;
372 unsigned int i;
373 struct ixgbe_tx_buffer *tx_buffer_info;
374 struct ixgbe_adv_tx_context_desc *context_desc;
375 struct fc_frame_header *fh;
376
377 if (skb_is_gso(skb) && (skb_shinfo(skb)->gso_type != SKB_GSO_FCOE)) {
378 DPRINTK(DRV, ERR, "Wrong gso type %d:expecting SKB_GSO_FCOE\n",
379 skb_shinfo(skb)->gso_type);
380 return -EINVAL;
381 }
382
383 /* resets the header to point fcoe/fc */
384 skb_set_network_header(skb, skb->mac_len);
385 skb_set_transport_header(skb, skb->mac_len +
386 sizeof(struct fcoe_hdr));
387
388 /* sets up SOF and ORIS */
389 fcoe_sof_eof = 0;
390 sof = ((struct fcoe_hdr *)skb_network_header(skb))->fcoe_sof;
391 switch (sof) {
392 case FC_SOF_I2:
393 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIS;
394 break;
395 case FC_SOF_I3:
396 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_SOF;
397 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIS;
398 break;
399 case FC_SOF_N2:
400 break;
401 case FC_SOF_N3:
402 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_SOF;
403 break;
404 default:
405 DPRINTK(DRV, WARNING, "unknown sof = 0x%x\n", sof);
406 return -EINVAL;
407 }
408
409 /* the first byte of the last dword is EOF */
410 skb_copy_bits(skb, skb->len - 4, &eof, 1);
411 /* sets up EOF and ORIE */
412 switch (eof) {
413 case FC_EOF_N:
414 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_N;
415 break;
416 case FC_EOF_T:
417 /* lso needs ORIE */
418 if (skb_is_gso(skb)) {
419 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_N;
420 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIE;
421 } else {
422 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_T;
423 }
424 break;
425 case FC_EOF_NI:
426 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_NI;
427 break;
428 case FC_EOF_A:
429 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_A;
430 break;
431 default:
432 DPRINTK(DRV, WARNING, "unknown eof = 0x%x\n", eof);
433 return -EINVAL;
434 }
435
436 /* sets up PARINC indicating data offset */
437 fh = (struct fc_frame_header *)skb_transport_header(skb);
438 if (fh->fh_f_ctl[2] & FC_FC_REL_OFF)
439 fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_PARINC;
440
441 /* hdr_len includes fc_hdr if FCoE lso is enabled */
442 *hdr_len = sizeof(struct fcoe_crc_eof);
443 if (skb_is_gso(skb))
444 *hdr_len += (skb_transport_offset(skb) +
445 sizeof(struct fc_frame_header));
446 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
447 vlan_macip_lens = (skb_transport_offset(skb) +
448 sizeof(struct fc_frame_header));
449 vlan_macip_lens |= ((skb_transport_offset(skb) - 4)
450 << IXGBE_ADVTXD_MACLEN_SHIFT);
451 vlan_macip_lens |= (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
452
453 /* type_tycmd and mss: set TUCMD.FCoE to enable offload */
454 type_tucmd = IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT |
455 IXGBE_ADVTXT_TUCMD_FCOE;
456 if (skb_is_gso(skb))
457 mss = skb_shinfo(skb)->gso_size;
458 /* mss_l4len_id: use 1 for FSO as TSO, no need for L4LEN */
459 mss_l4len_idx = (mss << IXGBE_ADVTXD_MSS_SHIFT) |
460 (1 << IXGBE_ADVTXD_IDX_SHIFT);
461
462 /* write context desc */
463 i = tx_ring->next_to_use;
464 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
465 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
466 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
467 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
468 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
469
470 tx_buffer_info = &tx_ring->tx_buffer_info[i];
471 tx_buffer_info->time_stamp = jiffies;
472 tx_buffer_info->next_to_watch = i;
473
474 i++;
475 if (i == tx_ring->count)
476 i = 0;
477 tx_ring->next_to_use = i;
478
479 return skb_is_gso(skb);
480}
481
d3a2ae6d
YZ		 482/**
483 * ixgbe_configure_fcoe - configures registers for fcoe at start
484 * @adapter: ptr to ixgbe adapter
485 *
486 * This sets up FCoE related registers
487 *
488 * Returns : none
489 */
490void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter)
491{
29ebf6f8 492 int i, fcoe_q, fcoe_i;
d3a2ae6d 493 struct ixgbe_hw *hw = &adapter->hw;
d0ed8937 494 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
29ebf6f8 495 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
d0ed8937
YZ		 496
497 /* create the pool for ddp if not created yet */
498 if (!fcoe->pool) {
499 /* allocate ddp pool */
500 fcoe->pool = pci_pool_create("ixgbe_fcoe_ddp",
501 adapter->pdev, IXGBE_FCPTR_MAX,
502 IXGBE_FCPTR_ALIGN, PAGE_SIZE);
503 if (!fcoe->pool)
504 DPRINTK(DRV, ERR,
505 "failed to allocated FCoE DDP pool\n");
d3a2ae6d 506
d0ed8937
YZ		 507 spin_lock_init(&fcoe->lock);
508 }
29ebf6f8
YZ		 509
510 /* Enable L2 eth type filter for FCoE */
d3a2ae6d
YZ		 511 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FCOE),
512 (ETH_P_FCOE | IXGBE_ETQF_FCOE | IXGBE_ETQF_FILTER_EN));
29ebf6f8
YZ		 513 if (adapter->ring_feature[RING_F_FCOE].indices) {
514 /* Use multiple rx queues for FCoE by redirection table */
515 for (i = 0; i < IXGBE_FCRETA_SIZE; i++) {
516 fcoe_i = f->mask + i % f->indices;
517 fcoe_i &= IXGBE_FCRETA_ENTRY_MASK;
518 fcoe_q = adapter->rx_ring[fcoe_i].reg_idx;
519 IXGBE_WRITE_REG(hw, IXGBE_FCRETA(i), fcoe_q);
520 }
521 IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, IXGBE_FCRECTL_ENA);
522 IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE), 0);
523 } else {
524 /* Use single rx queue for FCoE */
525 fcoe_i = f->mask;
526 fcoe_q = adapter->rx_ring[fcoe_i].reg_idx;
527 IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, 0);
528 IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE),
529 IXGBE_ETQS_QUEUE_EN |
530 (fcoe_q << IXGBE_ETQS_RX_QUEUE_SHIFT));
531 }
532
d3a2ae6d
YZ		 533 IXGBE_WRITE_REG(hw, IXGBE_FCRXCTRL,
534 IXGBE_FCRXCTRL_FCOELLI |
535 IXGBE_FCRXCTRL_FCCRCBO |
536 (FC_FCOE_VER << IXGBE_FCRXCTRL_FCOEVER_SHIFT));
537}
d0ed8937
YZ		 538
539/**
540 * ixgbe_cleanup_fcoe - release all fcoe ddp context resources
541 * @adapter : ixgbe adapter
542 *
543 * Cleans up outstanding ddp context resources
544 *
545 * Returns : none
546 */
547void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter)
548{
549 int i;
550 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
551
552 /* release ddp resource */
553 if (fcoe->pool) {
554 for (i = 0; i < IXGBE_FCOE_DDP_MAX; i++)
555 ixgbe_fcoe_ddp_put(adapter->netdev, i);
556 pci_pool_destroy(fcoe->pool);
557 fcoe->pool = NULL;
558 }
559}
8450ff8c
YZ		 560
561/**
562 * ixgbe_fcoe_enable - turn on FCoE offload feature
563 * @netdev: the corresponding netdev
564 *
565 * Turns on FCoE offload feature in 82599.
566 *
567 * Returns : 0 indicates success or -EINVAL on failure
568 */
569int ixgbe_fcoe_enable(struct net_device *netdev)
570{
571 int rc = -EINVAL;
572 struct ixgbe_adapter *adapter = netdev_priv(netdev);
573
574
575 if (!(adapter->flags & IXGBE_FLAG_FCOE_CAPABLE))
576 goto out_enable;
577
578 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
579 goto out_enable;
580
581 DPRINTK(DRV, INFO, "Enabling FCoE offload features.\n");
582 if (netif_running(netdev))
583 netdev->netdev_ops->ndo_stop(netdev);
584
585 ixgbe_clear_interrupt_scheme(adapter);
586
587 adapter->flags |= IXGBE_FLAG_FCOE_ENABLED;
588 adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE;
589 netdev->features |= NETIF_F_FCOE_CRC;
590 netdev->features |= NETIF_F_FSO;
591 netdev->features |= NETIF_F_FCOE_MTU;
592 netdev->vlan_features |= NETIF_F_FCOE_CRC;
593 netdev->vlan_features |= NETIF_F_FSO;
594 netdev->vlan_features |= NETIF_F_FCOE_MTU;
595 netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1;
596 netdev_features_change(netdev);
597
598 ixgbe_init_interrupt_scheme(adapter);
599
600 if (netif_running(netdev))
601 netdev->netdev_ops->ndo_open(netdev);
602 rc = 0;
603
604out_enable:
605 return rc;
606}
607
608/**
609 * ixgbe_fcoe_disable - turn off FCoE offload feature
610 * @netdev: the corresponding netdev
611 *
612 * Turns off FCoE offload feature in 82599.
613 *
614 * Returns : 0 indicates success or -EINVAL on failure
615 */
616int ixgbe_fcoe_disable(struct net_device *netdev)
617{
618 int rc = -EINVAL;
619 struct ixgbe_adapter *adapter = netdev_priv(netdev);
620
621 if (!(adapter->flags & IXGBE_FLAG_FCOE_CAPABLE))
622 goto out_disable;
623
624 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
625 goto out_disable;
626
627 DPRINTK(DRV, INFO, "Disabling FCoE offload features.\n");
628 if (netif_running(netdev))
629 netdev->netdev_ops->ndo_stop(netdev);
630
631 ixgbe_clear_interrupt_scheme(adapter);
632
633 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
634 adapter->ring_feature[RING_F_FCOE].indices = 0;
635 netdev->features &= ~NETIF_F_FCOE_CRC;
636 netdev->features &= ~NETIF_F_FSO;
637 netdev->features &= ~NETIF_F_FCOE_MTU;
638 netdev->vlan_features &= ~NETIF_F_FCOE_CRC;
639 netdev->vlan_features &= ~NETIF_F_FSO;
640 netdev->vlan_features &= ~NETIF_F_FCOE_MTU;
641 netdev->fcoe_ddp_xid = 0;
642 netdev_features_change(netdev);
643
644 ixgbe_cleanup_fcoe(adapter);
645
646 ixgbe_init_interrupt_scheme(adapter);
647 if (netif_running(netdev))
648 netdev->netdev_ops->ndo_open(netdev);
649 rc = 0;
650
651out_disable:
652 return rc;
653}
6ee16520
YZ		 654
655#ifdef CONFIG_IXGBE_DCB
656/**
657 * ixgbe_fcoe_getapp - retrieves current user priority bitmap for FCoE
658 * @adapter : ixgbe adapter
659 *
660 * Finds out the corresponding user priority bitmap from the current
661 * traffic class that FCoE belongs to. Returns 0 as the invalid user
662 * priority bitmap to indicate an error.
663 *
664 * Returns : 802.1p user priority bitmap for FCoE
665 */
666u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter)
667{
668 int i;
669 u8 tc;
670 u32 up2tc;
671
672 up2tc = IXGBE_READ_REG(&adapter->hw, IXGBE_RTTUP2TC);
673 for (i = 0; i < MAX_USER_PRIORITY; i++) {
674 tc = (u8)(up2tc >> (i * IXGBE_RTTUP2TC_UP_SHIFT));
675 tc &= (MAX_TRAFFIC_CLASS - 1);
676 if (adapter->fcoe.tc == tc)
677 return 1 << i;
678 }
679
680 return 0;
681}
682
683/**
684 * ixgbe_fcoe_setapp - sets the user priority bitmap for FCoE
685 * @adapter : ixgbe adapter
686 * @up : 802.1p user priority bitmap
687 *
688 * Finds out the traffic class from the input user priority
689 * bitmap for FCoE.
690 *
691 * Returns : 0 on success otherwise returns 1 on error
692 */
693u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up)
694{
695 int i;
696 u32 up2tc;
697
698 /* valid user priority bitmap must not be 0 */
699 if (up) {
700 /* from user priority to the corresponding traffic class */
701 up2tc = IXGBE_READ_REG(&adapter->hw, IXGBE_RTTUP2TC);
702 for (i = 0; i < MAX_USER_PRIORITY; i++) {
703 if (up & (1 << i)) {
704 up2tc >>= (i * IXGBE_RTTUP2TC_UP_SHIFT);
705 up2tc &= (MAX_TRAFFIC_CLASS - 1);
706 adapter->fcoe.tc = (u8)up2tc;
707 return 0;
708 }
709 }
710 }
711
712 return 1;
713}
714#endif /* CONFIG_IXGBE_DCB */
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