[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_fcoe.c

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2009 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/


#include "ixgbe.h"
#include <linux/if_ether.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_device.h>
#include <scsi/fc/fc_fs.h>
#include <scsi/fc/fc_fcoe.h>
#include <scsi/libfc.h>
#include <scsi/libfcoe.h>

/**
 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
 * @rx_desc: advanced rx descriptor
 *
 * Returns : true if it is FCoE pkt
 */
static inline bool ixgbe_rx_is_fcoe(union ixgbe_adv_rx_desc *rx_desc)
{
	u16 p;

	p = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info);
	if (p & IXGBE_RXDADV_PKTTYPE_ETQF) {
		p &= IXGBE_RXDADV_PKTTYPE_ETQF_MASK;
		p >>= IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT;
		return p == IXGBE_ETQF_FILTER_FCOE;
	}
	return false;
}

/**
 * ixgbe_fcoe_clear_ddp - clear the given ddp context
 * @ddp - ptr to the ixgbe_fcoe_ddp
 *
 * Returns : none
 *
 */
static inline void ixgbe_fcoe_clear_ddp(struct ixgbe_fcoe_ddp *ddp)
{
	ddp->len = 0;
	ddp->err = 0;
	ddp->udl = NULL;
	ddp->udp = 0UL;
	ddp->sgl = NULL;
	ddp->sgc = 0;
}

/**
 * ixgbe_fcoe_ddp_put - free the ddp context for a given xid
 * @netdev: the corresponding net_device
 * @xid: the xid that corresponding ddp will be freed
 *
 * This is the implementation of net_device_ops.ndo_fcoe_ddp_done
 * and it is expected to be called by ULD, i.e., FCP layer of libfc
 * to release the corresponding ddp context when the I/O is done.
 *
 * Returns : data length already ddp-ed in bytes
 */
int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid)
{
	int len = 0;
	struct ixgbe_fcoe *fcoe;
	struct ixgbe_adapter *adapter;
	struct ixgbe_fcoe_ddp *ddp;

	if (!netdev)
		goto out_ddp_put;

	if (xid >= IXGBE_FCOE_DDP_MAX)
		goto out_ddp_put;

	adapter = netdev_priv(netdev);
	fcoe = &adapter->fcoe;
	ddp = &fcoe->ddp[xid];
	if (!ddp->udl)
		goto out_ddp_put;

	len = ddp->len;
	/* if there an error, force to invalidate ddp context */
	if (ddp->err) {
		spin_lock_bh(&fcoe->lock);
		IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCFLT, 0);
		IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCFLTRW,
				(xid | IXGBE_FCFLTRW_WE));
		IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCBUFF, 0);
		IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCDMARW,
				(xid | IXGBE_FCDMARW_WE));
		spin_unlock_bh(&fcoe->lock);
	}
	if (ddp->sgl)
		pci_unmap_sg(adapter->pdev, ddp->sgl, ddp->sgc,
			     DMA_FROM_DEVICE);
	pci_pool_free(fcoe->pool, ddp->udl, ddp->udp);
	ixgbe_fcoe_clear_ddp(ddp);

out_ddp_put:
	return len;
}

/**
 * ixgbe_fcoe_ddp_get - called to set up ddp context
 * @netdev: the corresponding net_device
 * @xid: the exchange id requesting ddp
 * @sgl: the scatter-gather list for this request
 * @sgc: the number of scatter-gather items
 *
 * This is the implementation of net_device_ops.ndo_fcoe_ddp_setup
 * and is expected to be called from ULD, e.g., FCP layer of libfc
 * to set up ddp for the corresponding xid of the given sglist for
 * the corresponding I/O.
 *
 * Returns : 1 for success and 0 for no ddp
 */
int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
		       struct scatterlist *sgl, unsigned int sgc)
{
	struct ixgbe_adapter *adapter;
	struct ixgbe_hw *hw;
	struct ixgbe_fcoe *fcoe;
	struct ixgbe_fcoe_ddp *ddp;
	struct scatterlist *sg;
	unsigned int i, j, dmacount;
	unsigned int len;
	static const unsigned int bufflen = 4096;
	unsigned int firstoff = 0;
	unsigned int lastsize;
	unsigned int thisoff = 0;
	unsigned int thislen = 0;
	u32 fcbuff, fcdmarw, fcfltrw;
	dma_addr_t addr;

	if (!netdev || !sgl)
		return 0;

	adapter = netdev_priv(netdev);
	if (xid >= IXGBE_FCOE_DDP_MAX) {
		DPRINTK(DRV, WARNING, "xid=0x%x out-of-range\n", xid);
		return 0;
	}

	fcoe = &adapter->fcoe;
	if (!fcoe->pool) {
		DPRINTK(DRV, WARNING, "xid=0x%x no ddp pool for fcoe\n", xid);
		return 0;
	}

	ddp = &fcoe->ddp[xid];
	if (ddp->sgl) {
		DPRINTK(DRV, ERR, "xid 0x%x w/ non-null sgl=%p nents=%d\n",
			xid, ddp->sgl, ddp->sgc);
		return 0;
	}
	ixgbe_fcoe_clear_ddp(ddp);

	/* setup dma from scsi command sgl */
	dmacount = pci_map_sg(adapter->pdev, sgl, sgc, DMA_FROM_DEVICE);
	if (dmacount == 0) {
		DPRINTK(DRV, ERR, "xid 0x%x DMA map error\n", xid);
		return 0;
	}

	/* alloc the udl from our ddp pool */
	ddp->udl = pci_pool_alloc(fcoe->pool, GFP_KERNEL, &ddp->udp);
	if (!ddp->udl) {
		DPRINTK(DRV, ERR, "failed allocated ddp context\n");
		goto out_noddp_unmap;
	}
	ddp->sgl = sgl;
	ddp->sgc = sgc;

	j = 0;
	for_each_sg(sgl, sg, dmacount, i) {
		addr = sg_dma_address(sg);
		len = sg_dma_len(sg);
		while (len) {
			/* get the offset of length of current buffer */
			thisoff = addr & ((dma_addr_t)bufflen - 1);
			thislen = min((bufflen - thisoff), len);
			/*
			 * all but the 1st buffer (j == 0)
			 * must be aligned on bufflen
			 */
			if ((j != 0) && (thisoff))
				goto out_noddp_free;
			/*
			 * all but the last buffer
			 * ((i == (dmacount - 1)) && (thislen == len))
			 * must end at bufflen
			 */
			if (((i != (dmacount - 1)) || (thislen != len))
			    && ((thislen + thisoff) != bufflen))
				goto out_noddp_free;

			ddp->udl[j] = (u64)(addr - thisoff);
			/* only the first buffer may have none-zero offset */
			if (j == 0)
				firstoff = thisoff;
			len -= thislen;
			addr += thislen;
			j++;
			/* max number of buffers allowed in one DDP context */
			if (j > IXGBE_BUFFCNT_MAX) {
				DPRINTK(DRV, ERR, "xid=%x:%d,%d,%d:addr=%llx "
					"not enough descriptors\n",
					xid, i, j, dmacount, (u64)addr);
				goto out_noddp_free;
			}
		}
	}
	/* only the last buffer may have non-full bufflen */
	lastsize = thisoff + thislen;

	fcbuff = (IXGBE_FCBUFF_4KB << IXGBE_FCBUFF_BUFFSIZE_SHIFT);
	fcbuff |= (j << IXGBE_FCBUFF_BUFFCNT_SHIFT);
	fcbuff |= (firstoff << IXGBE_FCBUFF_OFFSET_SHIFT);
	fcbuff |= (IXGBE_FCBUFF_VALID);

	fcdmarw = xid;
	fcdmarw |= IXGBE_FCDMARW_WE;
	fcdmarw |= (lastsize << IXGBE_FCDMARW_LASTSIZE_SHIFT);

	fcfltrw = xid;
	fcfltrw |= IXGBE_FCFLTRW_WE;

	/* program DMA context */
	hw = &adapter->hw;
	spin_lock_bh(&fcoe->lock);
	IXGBE_WRITE_REG(hw, IXGBE_FCPTRL, ddp->udp & DMA_32BIT_MASK);
	IXGBE_WRITE_REG(hw, IXGBE_FCPTRH, (u64)ddp->udp >> 32);
	IXGBE_WRITE_REG(hw, IXGBE_FCBUFF, fcbuff);
	IXGBE_WRITE_REG(hw, IXGBE_FCDMARW, fcdmarw);
	/* program filter context */
	IXGBE_WRITE_REG(hw, IXGBE_FCPARAM, 0);
	IXGBE_WRITE_REG(hw, IXGBE_FCFLT, IXGBE_FCFLT_VALID);
	IXGBE_WRITE_REG(hw, IXGBE_FCFLTRW, fcfltrw);
	spin_unlock_bh(&fcoe->lock);

	return 1;

out_noddp_free:
	pci_pool_free(fcoe->pool, ddp->udl, ddp->udp);
	ixgbe_fcoe_clear_ddp(ddp);

out_noddp_unmap:
	pci_unmap_sg(adapter->pdev, sgl, sgc, DMA_FROM_DEVICE);
	return 0;
}

/**
 * ixgbe_fcoe_ddp - check ddp status and mark it done
 * @adapter: ixgbe adapter
 * @rx_desc: advanced rx descriptor
 * @skb: the skb holding the received data
 *
 * This checks ddp status.
 *
 * Returns : 0 for success and skb will not be delivered to ULD
 */
int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
		   union ixgbe_adv_rx_desc *rx_desc,
		   struct sk_buff *skb)
{
	u16 xid;
	u32 sterr, fceofe, fcerr, fcstat;
	int rc = -EINVAL;
	struct ixgbe_fcoe *fcoe;
	struct ixgbe_fcoe_ddp *ddp;
	struct fc_frame_header *fh;

	if (!ixgbe_rx_is_fcoe(rx_desc))
		goto ddp_out;

	skb->ip_summed = CHECKSUM_UNNECESSARY;
	sterr = le32_to_cpu(rx_desc->wb.upper.status_error);
	fcerr = (sterr & IXGBE_RXDADV_ERR_FCERR);
	fceofe = (sterr & IXGBE_RXDADV_ERR_FCEOFE);
	if (fcerr == IXGBE_FCERR_BADCRC)
		skb->ip_summed = CHECKSUM_NONE;

	skb_reset_network_header(skb);
	skb_set_transport_header(skb, skb_network_offset(skb) +
				 sizeof(struct fcoe_hdr));
	fh = (struct fc_frame_header *)skb_transport_header(skb);
	xid =  be16_to_cpu(fh->fh_ox_id);
	if (xid >= IXGBE_FCOE_DDP_MAX)
		goto ddp_out;

	fcoe = &adapter->fcoe;
	ddp = &fcoe->ddp[xid];
	if (!ddp->udl)
		goto ddp_out;

	ddp->err = (fcerr | fceofe);
	if (ddp->err)
		goto ddp_out;

	fcstat = (sterr & IXGBE_RXDADV_STAT_FCSTAT);
	if (fcstat) {
		/* update length of DDPed data */
		ddp->len = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
		/* unmap the sg list when FCP_RSP is received */
		if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_FCPRSP) {
			pci_unmap_sg(adapter->pdev, ddp->sgl,
				     ddp->sgc, DMA_FROM_DEVICE);
			ddp->sgl = NULL;
			ddp->sgc = 0;
		}
		/* return 0 to bypass going to ULD for DDPed data */
		if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_DDP)
			rc = 0;
	}

ddp_out:
	return rc;
}

/**
 * ixgbe_fso - ixgbe FCoE Sequence Offload (FSO)
 * @adapter: ixgbe adapter
 * @tx_ring: tx desc ring
 * @skb: associated skb
 * @tx_flags: tx flags
 * @hdr_len: hdr_len to be returned
 *
 * This sets up large send offload for FCoE
 *
 * Returns : 0 indicates no FSO, > 0 for FSO, < 0 for error
 */
int ixgbe_fso(struct ixgbe_adapter *adapter,
              struct ixgbe_ring *tx_ring, struct sk_buff *skb,
              u32 tx_flags, u8 *hdr_len)
{
	u8 sof, eof;
	u32 vlan_macip_lens;
	u32 fcoe_sof_eof;
	u32 type_tucmd;
	u32 mss_l4len_idx;
	int mss = 0;
	unsigned int i;
	struct ixgbe_tx_buffer *tx_buffer_info;
	struct ixgbe_adv_tx_context_desc *context_desc;
	struct fc_frame_header *fh;

	if (skb_is_gso(skb) && (skb_shinfo(skb)->gso_type != SKB_GSO_FCOE)) {
		DPRINTK(DRV, ERR, "Wrong gso type %d:expecting SKB_GSO_FCOE\n",
			skb_shinfo(skb)->gso_type);
		return -EINVAL;
	}

	/* resets the header to point fcoe/fc */
	skb_set_network_header(skb, skb->mac_len);
	skb_set_transport_header(skb, skb->mac_len +
				 sizeof(struct fcoe_hdr));

	/* sets up SOF and ORIS */
	fcoe_sof_eof = 0;
	sof = ((struct fcoe_hdr *)skb_network_header(skb))->fcoe_sof;
	switch (sof) {
	case FC_SOF_I2:
		fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIS;
		break;
	case FC_SOF_I3:
		fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_SOF;
		fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIS;
		break;
	case FC_SOF_N2:
		break;
	case FC_SOF_N3:
		fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_SOF;
		break;
	default:
		DPRINTK(DRV, WARNING, "unknown sof = 0x%x\n", sof);
		return -EINVAL;
	}

	/* the first byte of the last dword is EOF */
	skb_copy_bits(skb, skb->len - 4, &eof, 1);
	/* sets up EOF and ORIE */
	switch (eof) {
	case FC_EOF_N:
		fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_N;
		break;
	case FC_EOF_T:
		/* lso needs ORIE */
		if (skb_is_gso(skb)) {
			fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_N;
			fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_ORIE;
		} else {
			fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_T;
		}
		break;
	case FC_EOF_NI:
		fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_NI;
		break;
	case FC_EOF_A:
		fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_EOF_A;
		break;
	default:
		DPRINTK(DRV, WARNING, "unknown eof = 0x%x\n", eof);
		return -EINVAL;
	}

	/* sets up PARINC indicating data offset */
	fh = (struct fc_frame_header *)skb_transport_header(skb);
	if (fh->fh_f_ctl[2] & FC_FC_REL_OFF)
		fcoe_sof_eof |= IXGBE_ADVTXD_FCOEF_PARINC;

	/* hdr_len includes fc_hdr if FCoE lso is enabled */
	*hdr_len = sizeof(struct fcoe_crc_eof);
	if (skb_is_gso(skb))
		*hdr_len += (skb_transport_offset(skb) +
			     sizeof(struct fc_frame_header));
	/* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
	vlan_macip_lens = (skb_transport_offset(skb) +
			  sizeof(struct fc_frame_header));
	vlan_macip_lens |= ((skb_transport_offset(skb) - 4)
			   << IXGBE_ADVTXD_MACLEN_SHIFT);
	vlan_macip_lens |= (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);

	/* type_tycmd and mss: set TUCMD.FCoE to enable offload */
	type_tucmd = IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT |
		     IXGBE_ADVTXT_TUCMD_FCOE;
	if (skb_is_gso(skb))
		mss = skb_shinfo(skb)->gso_size;
	/* mss_l4len_id: use 1 for FSO as TSO, no need for L4LEN */
	mss_l4len_idx = (mss << IXGBE_ADVTXD_MSS_SHIFT) |
			(1 << IXGBE_ADVTXD_IDX_SHIFT);

	/* write context desc */
	i = tx_ring->next_to_use;
	context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
	context_desc->vlan_macip_lens	= cpu_to_le32(vlan_macip_lens);
	context_desc->seqnum_seed	= cpu_to_le32(fcoe_sof_eof);
	context_desc->type_tucmd_mlhl	= cpu_to_le32(type_tucmd);
	context_desc->mss_l4len_idx	= cpu_to_le32(mss_l4len_idx);

	tx_buffer_info = &tx_ring->tx_buffer_info[i];
	tx_buffer_info->time_stamp = jiffies;
	tx_buffer_info->next_to_watch = i;

	i++;
	if (i == tx_ring->count)
		i = 0;
	tx_ring->next_to_use = i;

	return skb_is_gso(skb);
}

/**
 * ixgbe_configure_fcoe - configures registers for fcoe at start
 * @adapter: ptr to ixgbe adapter
 *
 * This sets up FCoE related registers
 *
 * Returns : none
 */
void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter)
{
	struct ixgbe_hw *hw = &adapter->hw;
	struct ixgbe_fcoe *fcoe = &adapter->fcoe;

	/* create the pool for ddp if not created yet */
	if (!fcoe->pool) {
		/* allocate ddp pool */
		fcoe->pool = pci_pool_create("ixgbe_fcoe_ddp",
					     adapter->pdev, IXGBE_FCPTR_MAX,
					     IXGBE_FCPTR_ALIGN, PAGE_SIZE);
		if (!fcoe->pool)
			DPRINTK(DRV, ERR,
				"failed to allocated FCoE DDP pool\n");

		spin_lock_init(&fcoe->lock);
	}
	/* L2 filter for FCoE: default to queue 0 */
	IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FCOE),
			(ETH_P_FCOE | IXGBE_ETQF_FCOE | IXGBE_ETQF_FILTER_EN));
	IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, 0);
	IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE),
			IXGBE_ETQS_QUEUE_EN);
	IXGBE_WRITE_REG(hw, IXGBE_FCRXCTRL,
			IXGBE_FCRXCTRL_FCOELLI |
			IXGBE_FCRXCTRL_FCCRCBO |
			(FC_FCOE_VER << IXGBE_FCRXCTRL_FCOEVER_SHIFT));
}

/**
 * ixgbe_cleanup_fcoe - release all fcoe ddp context resources
 * @adapter : ixgbe adapter
 *
 * Cleans up outstanding ddp context resources
 *
 * Returns : none
 */
void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter)
{
	int i;
	struct ixgbe_fcoe *fcoe = &adapter->fcoe;

	/* release ddp resource */
	if (fcoe->pool) {
		for (i = 0; i < IXGBE_FCOE_DDP_MAX; i++)
			ixgbe_fcoe_ddp_put(adapter->netdev, i);
		pci_pool_destroy(fcoe->pool);
		fcoe->pool = NULL;
	}
}
Commit	Line	Data
d3a2ae6d YZ	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
	4	Copyright(c) 1999 - 2009 Intel Corporation.
	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28
	29	#include "ixgbe.h"
	30	#include <linux/if_ether.h>
	31	#include <scsi/scsi_cmnd.h>
	32	#include <scsi/scsi_device.h>
	33	#include <scsi/fc/fc_fs.h>
	34	#include <scsi/fc/fc_fcoe.h>
	35	#include <scsi/libfc.h>
	36	#include <scsi/libfcoe.h>
	37
d0ed8937 YZ	38	/**
	39	* ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
	40	* @rx_desc: advanced rx descriptor
	41	*
	42	* Returns : true if it is FCoE pkt
	43	*/
	44	static inline bool ixgbe_rx_is_fcoe(union ixgbe_adv_rx_desc *rx_desc)
	45	{
	46	u16 p;
	47
	48	p = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info);
	49	if (p & IXGBE_RXDADV_PKTTYPE_ETQF) {
	50	p &= IXGBE_RXDADV_PKTTYPE_ETQF_MASK;
	51	p >>= IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT;
	52	return p == IXGBE_ETQF_FILTER_FCOE;
	53	}
	54	return false;
	55	}
	56
	57	/**
	58	* ixgbe_fcoe_clear_ddp - clear the given ddp context
	59	* @ddp - ptr to the ixgbe_fcoe_ddp
	60	*
	61	* Returns : none
	62	*
	63	*/
	64	static inline void ixgbe_fcoe_clear_ddp(struct ixgbe_fcoe_ddp *ddp)
	65	{
	66	ddp->len = 0;
	67	ddp->err = 0;
	68	ddp->udl = NULL;
	69	ddp->udp = 0UL;
	70	ddp->sgl = NULL;
	71	ddp->sgc = 0;
	72	}
	73
	74	/**
	75	* ixgbe_fcoe_ddp_put - free the ddp context for a given xid
	76	* @netdev: the corresponding net_device
	77	* @xid: the xid that corresponding ddp will be freed
	78	*
	79	* This is the implementation of net_device_ops.ndo_fcoe_ddp_done
	80	* and it is expected to be called by ULD, i.e., FCP layer of libfc
	81	* to release the corresponding ddp context when the I/O is done.
	82	*
	83	* Returns : data length already ddp-ed in bytes
	84	*/
	85	int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid)
	86	{
	87	int len = 0;
	88	struct ixgbe_fcoe *fcoe;
	89	struct ixgbe_adapter *adapter;
	90	struct ixgbe_fcoe_ddp *ddp;
	91
	92	if (!netdev)
	93	goto out_ddp_put;
	94
	95	if (xid >= IXGBE_FCOE_DDP_MAX)
	96	goto out_ddp_put;
	97
	98	adapter = netdev_priv(netdev);
	99	fcoe = &adapter->fcoe;
	100	ddp = &fcoe->ddp[xid];
	101	if (!ddp->udl)
102	goto out_ddp_put;
103
104	len = ddp->len;
105	/* if there an error, force to invalidate ddp context */
106	if (ddp->err) {
107	spin_lock_bh(&fcoe->lock);
108	IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCFLT, 0);
109	IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCFLTRW,
110	(xid \| IXGBE_FCFLTRW_WE));
111	IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCBUFF, 0);
112	IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCDMARW,
113	(xid \| IXGBE_FCDMARW_WE));
114	spin_unlock_bh(&fcoe->lock);
115	}
116	if (ddp->sgl)
117	pci_unmap_sg(adapter->pdev, ddp->sgl, ddp->sgc,
118	DMA_FROM_DEVICE);
119	pci_pool_free(fcoe->pool, ddp->udl, ddp->udp);
120	ixgbe_fcoe_clear_ddp(ddp);
121
122	out_ddp_put:
123	return len;
124	}
125
126	/**
127	* ixgbe_fcoe_ddp_get - called to set up ddp context
128	* @netdev: the corresponding net_device
129	* @xid: the exchange id requesting ddp
130	* @sgl: the scatter-gather list for this request
131	* @sgc: the number of scatter-gather items
132	*
133	* This is the implementation of net_device_ops.ndo_fcoe_ddp_setup
134	* and is expected to be called from ULD, e.g., FCP layer of libfc
135	* to set up ddp for the corresponding xid of the given sglist for
136	* the corresponding I/O.
137	*
138	* Returns : 1 for success and 0 for no ddp
139	*/
140	int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
141	struct scatterlist *sgl, unsigned int sgc)
142	{
143	struct ixgbe_adapter *adapter;
144	struct ixgbe_hw *hw;
145	struct ixgbe_fcoe *fcoe;
146	struct ixgbe_fcoe_ddp *ddp;
147	struct scatterlist *sg;
148	unsigned int i, j, dmacount;
149	unsigned int len;
150	static const unsigned int bufflen = 4096;
151	unsigned int firstoff = 0;
152	unsigned int lastsize;
153	unsigned int thisoff = 0;
154	unsigned int thislen = 0;
155	u32 fcbuff, fcdmarw, fcfltrw;
156	dma_addr_t addr;
157
158	if (!netdev \|\| !sgl)
159	return 0;
160
161	adapter = netdev_priv(netdev);
162	if (xid >= IXGBE_FCOE_DDP_MAX) {
163	DPRINTK(DRV, WARNING, "xid=0x%x out-of-range\n", xid);
164	return 0;
165	}
166
167	fcoe = &adapter->fcoe;
168	if (!fcoe->pool) {
169	DPRINTK(DRV, WARNING, "xid=0x%x no ddp pool for fcoe\n", xid);
170	return 0;
171	}
172
173	ddp = &fcoe->ddp[xid];
174	if (ddp->sgl) {
175	DPRINTK(DRV, ERR, "xid 0x%x w/ non-null sgl=%p nents=%d\n",
176	xid, ddp->sgl, ddp->sgc);
177	return 0;
178	}
179	ixgbe_fcoe_clear_ddp(ddp);
180
181	/* setup dma from scsi command sgl */
182	dmacount = pci_map_sg(adapter->pdev, sgl, sgc, DMA_FROM_DEVICE);
183	if (dmacount == 0) {
184	DPRINTK(DRV, ERR, "xid 0x%x DMA map error\n", xid);
185	return 0;
186	}
187
188	/* alloc the udl from our ddp pool */
189	ddp->udl = pci_pool_alloc(fcoe->pool, GFP_KERNEL, &ddp->udp);
190	if (!ddp->udl) {
191	DPRINTK(DRV, ERR, "failed allocated ddp context\n");
192	goto out_noddp_unmap;
193	}
194	ddp->sgl = sgl;
195	ddp->sgc = sgc;
196
197	j = 0;
198	for_each_sg(sgl, sg, dmacount, i) {
199	addr = sg_dma_address(sg);
200	len = sg_dma_len(sg);
201	while (len) {
202	/* get the offset of length of current buffer */
203	thisoff = addr & ((dma_addr_t)bufflen - 1);
204	thislen = min((bufflen - thisoff), len);
205	/*
206	* all but the 1st buffer (j == 0)
207	* must be aligned on bufflen
208	*/
209	if ((j != 0) && (thisoff))
210	goto out_noddp_free;
211	/*
212	* all but the last buffer
213	* ((i == (dmacount - 1)) && (thislen == len))
214	* must end at bufflen
215	*/
216	if (((i != (dmacount - 1)) \|\| (thislen != len))
217	&& ((thislen + thisoff) != bufflen))
218	goto out_noddp_free;
219
220	ddp->udl[j] = (u64)(addr - thisoff);
221	/* only the first buffer may have none-zero offset */
222	if (j == 0)
223	firstoff = thisoff;
224	len -= thislen;
225	addr += thislen;
226	j++;
227	/* max number of buffers allowed in one DDP context */
228	if (j > IXGBE_BUFFCNT_MAX) {
229	DPRINTK(DRV, ERR, "xid=%x:%d,%d,%d:addr=%llx "
230	"not enough descriptors\n",
231	xid, i, j, dmacount, (u64)addr);
232	goto out_noddp_free;
233	}
234	}
235	}
236	/* only the last buffer may have non-full bufflen */
237	lastsize = thisoff + thislen;
238
239	fcbuff = (IXGBE_FCBUFF_4KB << IXGBE_FCBUFF_BUFFSIZE_SHIFT);
240	fcbuff \|= (j << IXGBE_FCBUFF_BUFFCNT_SHIFT);
241	fcbuff \|= (firstoff << IXGBE_FCBUFF_OFFSET_SHIFT);
242	fcbuff \|= (IXGBE_FCBUFF_VALID);
243
244	fcdmarw = xid;
245	fcdmarw \|= IXGBE_FCDMARW_WE;
246	fcdmarw \|= (lastsize << IXGBE_FCDMARW_LASTSIZE_SHIFT);
247
248	fcfltrw = xid;
249	fcfltrw \|= IXGBE_FCFLTRW_WE;
250
251	/* program DMA context */
252	hw = &adapter->hw;
253	spin_lock_bh(&fcoe->lock);
254	IXGBE_WRITE_REG(hw, IXGBE_FCPTRL, ddp->udp & DMA_32BIT_MASK);
255	IXGBE_WRITE_REG(hw, IXGBE_FCPTRH, (u64)ddp->udp >> 32);
256	IXGBE_WRITE_REG(hw, IXGBE_FCBUFF, fcbuff);
257	IXGBE_WRITE_REG(hw, IXGBE_FCDMARW, fcdmarw);
258	/* program filter context */
259	IXGBE_WRITE_REG(hw, IXGBE_FCPARAM, 0);
260	IXGBE_WRITE_REG(hw, IXGBE_FCFLT, IXGBE_FCFLT_VALID);
261	IXGBE_WRITE_REG(hw, IXGBE_FCFLTRW, fcfltrw);
262	spin_unlock_bh(&fcoe->lock);
263
264	return 1;
265
266	out_noddp_free:
267	pci_pool_free(fcoe->pool, ddp->udl, ddp->udp);
268	ixgbe_fcoe_clear_ddp(ddp);
269
270	out_noddp_unmap:
271	pci_unmap_sg(adapter->pdev, sgl, sgc, DMA_FROM_DEVICE);
272	return 0;
273	}
274
275	/**
276	* ixgbe_fcoe_ddp - check ddp status and mark it done
277	* @adapter: ixgbe adapter
278	* @rx_desc: advanced rx descriptor
279	* @skb: the skb holding the received data
280	*
281	* This checks ddp status.
282	*
283	* Returns : 0 for success and skb will not be delivered to ULD
284	*/
285	int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
286	union ixgbe_adv_rx_desc *rx_desc,
287	struct sk_buff *skb)
288	{
289	u16 xid;
290	u32 sterr, fceofe, fcerr, fcstat;
291	int rc = -EINVAL;
292	struct ixgbe_fcoe *fcoe;
293	struct ixgbe_fcoe_ddp *ddp;
294	struct fc_frame_header *fh;
295
296	if (!ixgbe_rx_is_fcoe(rx_desc))
297	goto ddp_out;
298
299	skb->ip_summed = CHECKSUM_UNNECESSARY;
300	sterr = le32_to_cpu(rx_desc->wb.upper.status_error);
301	fcerr = (sterr & IXGBE_RXDADV_ERR_FCERR);
302	fceofe = (sterr & IXGBE_RXDADV_ERR_FCEOFE);
303	if (fcerr == IXGBE_FCERR_BADCRC)
304	skb->ip_summed = CHECKSUM_NONE;
305
306	skb_reset_network_header(skb);
307	skb_set_transport_header(skb, skb_network_offset(skb) +
308	sizeof(struct fcoe_hdr));
309	fh = (struct fc_frame_header *)skb_transport_header(skb);
310	xid = be16_to_cpu(fh->fh_ox_id);
311	if (xid >= IXGBE_FCOE_DDP_MAX)
312	goto ddp_out;
313
314	fcoe = &adapter->fcoe;
315	ddp = &fcoe->ddp[xid];
316	if (!ddp->udl)
317	goto ddp_out;
318
319	ddp->err = (fcerr \| fceofe);
320	if (ddp->err)
321	goto ddp_out;
322
323	fcstat = (sterr & IXGBE_RXDADV_STAT_FCSTAT);
324	if (fcstat) {
325	/* update length of DDPed data */
326	ddp->len = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
327	/* unmap the sg list when FCP_RSP is received */
328	if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_FCPRSP) {
329	pci_unmap_sg(adapter->pdev, ddp->sgl,
330	ddp->sgc, DMA_FROM_DEVICE);
331	ddp->sgl = NULL;
332	ddp->sgc = 0;
333	}
334	/* return 0 to bypass going to ULD for DDPed data */
335	if (fcstat == IXGBE_RXDADV_STAT_FCSTAT_DDP)
336	rc = 0;
337	}
338
339	ddp_out:
340	return rc;
341	}
342
bc079228 YZ	343	/**
	344	* ixgbe_fso - ixgbe FCoE Sequence Offload (FSO)
	345	* @adapter: ixgbe adapter
	346	* @tx_ring: tx desc ring
	347	* @skb: associated skb
	348	* @tx_flags: tx flags
	349	* @hdr_len: hdr_len to be returned
	350	*
	351	* This sets up large send offload for FCoE
	352	*
	353	* Returns : 0 indicates no FSO, > 0 for FSO, < 0 for error
	354	*/
	355	int ixgbe_fso(struct ixgbe_adapter *adapter,
	356	struct ixgbe_ring tx_ring, struct sk_buff skb,
	357	u32 tx_flags, u8 *hdr_len)
	358	{
	359	u8 sof, eof;
	360	u32 vlan_macip_lens;
	361	u32 fcoe_sof_eof;
	362	u32 type_tucmd;
	363	u32 mss_l4len_idx;
	364	int mss = 0;
	365	unsigned int i;
	366	struct ixgbe_tx_buffer *tx_buffer_info;
	367	struct ixgbe_adv_tx_context_desc *context_desc;
	368	struct fc_frame_header *fh;
	369
	370	if (skb_is_gso(skb) && (skb_shinfo(skb)->gso_type != SKB_GSO_FCOE)) {
	371	DPRINTK(DRV, ERR, "Wrong gso type %d:expecting SKB_GSO_FCOE\n",
	372	skb_shinfo(skb)->gso_type);
	373	return -EINVAL;
	374	}
	375
	376	/* resets the header to point fcoe/fc */
	377	skb_set_network_header(skb, skb->mac_len);
	378	skb_set_transport_header(skb, skb->mac_len +
	379	sizeof(struct fcoe_hdr));
	380
	381	/* sets up SOF and ORIS */
	382	fcoe_sof_eof = 0;
	383	sof = ((struct fcoe_hdr *)skb_network_header(skb))->fcoe_sof;
	384	switch (sof) {
	385	case FC_SOF_I2:
	386	fcoe_sof_eof \|= IXGBE_ADVTXD_FCOEF_ORIS;
	387	break;
	388	case FC_SOF_I3:
	389	fcoe_sof_eof \|= IXGBE_ADVTXD_FCOEF_SOF;
	390	fcoe_sof_eof \|= IXGBE_ADVTXD_FCOEF_ORIS;
	391	break;
	392	case FC_SOF_N2:
	393	break;
	394	case FC_SOF_N3:
	395	fcoe_sof_eof \|= IXGBE_ADVTXD_FCOEF_SOF;
	396	break;
	397	default:
	398	DPRINTK(DRV, WARNING, "unknown sof = 0x%x\n", sof);
	399	return -EINVAL;
	400	}
	401
	402	/* the first byte of the last dword is EOF */
	403	skb_copy_bits(skb, skb->len - 4, &eof, 1);
	404	/* sets up EOF and ORIE */
	405	switch (eof) {
	406	case FC_EOF_N:
407	fcoe_sof_eof \|= IXGBE_ADVTXD_FCOEF_EOF_N;
408	break;
409	case FC_EOF_T:
410	/* lso needs ORIE */
411	if (skb_is_gso(skb)) {
412	fcoe_sof_eof \|= IXGBE_ADVTXD_FCOEF_EOF_N;
413	fcoe_sof_eof \|= IXGBE_ADVTXD_FCOEF_ORIE;
414	} else {
415	fcoe_sof_eof \|= IXGBE_ADVTXD_FCOEF_EOF_T;
416	}
417	break;
418	case FC_EOF_NI:
419	fcoe_sof_eof \|= IXGBE_ADVTXD_FCOEF_EOF_NI;
420	break;
421	case FC_EOF_A:
422	fcoe_sof_eof \|= IXGBE_ADVTXD_FCOEF_EOF_A;
423	break;
424	default:
425	DPRINTK(DRV, WARNING, "unknown eof = 0x%x\n", eof);
426	return -EINVAL;
427	}
428
429	/* sets up PARINC indicating data offset */
430	fh = (struct fc_frame_header *)skb_transport_header(skb);
431	if (fh->fh_f_ctl[2] & FC_FC_REL_OFF)
432	fcoe_sof_eof \|= IXGBE_ADVTXD_FCOEF_PARINC;
433
434	/* hdr_len includes fc_hdr if FCoE lso is enabled */
435	*hdr_len = sizeof(struct fcoe_crc_eof);
436	if (skb_is_gso(skb))
437	*hdr_len += (skb_transport_offset(skb) +
438	sizeof(struct fc_frame_header));
439	/* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
440	vlan_macip_lens = (skb_transport_offset(skb) +
441	sizeof(struct fc_frame_header));
442	vlan_macip_lens \|= ((skb_transport_offset(skb) - 4)
443	<< IXGBE_ADVTXD_MACLEN_SHIFT);
444	vlan_macip_lens \|= (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
445
446	/* type_tycmd and mss: set TUCMD.FCoE to enable offload */
447	type_tucmd = IXGBE_TXD_CMD_DEXT \| IXGBE_ADVTXD_DTYP_CTXT \|
448	IXGBE_ADVTXT_TUCMD_FCOE;
449	if (skb_is_gso(skb))
450	mss = skb_shinfo(skb)->gso_size;
451	/* mss_l4len_id: use 1 for FSO as TSO, no need for L4LEN */
452	mss_l4len_idx = (mss << IXGBE_ADVTXD_MSS_SHIFT) \|
453	(1 << IXGBE_ADVTXD_IDX_SHIFT);
454
455	/* write context desc */
456	i = tx_ring->next_to_use;
457	context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
458	context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
459	context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
460	context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
461	context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
462
463	tx_buffer_info = &tx_ring->tx_buffer_info[i];
464	tx_buffer_info->time_stamp = jiffies;
465	tx_buffer_info->next_to_watch = i;
466
467	i++;
468	if (i == tx_ring->count)
469	i = 0;
470	tx_ring->next_to_use = i;
471
472	return skb_is_gso(skb);
473	}
474
d3a2ae6d YZ	475	/**
	476	* ixgbe_configure_fcoe - configures registers for fcoe at start
	477	* @adapter: ptr to ixgbe adapter
	478	*
	479	* This sets up FCoE related registers
	480	*
	481	* Returns : none
	482	*/
	483	void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter)
	484	{
	485	struct ixgbe_hw *hw = &adapter->hw;
d0ed8937 YZ	486	struct ixgbe_fcoe *fcoe = &adapter->fcoe;
	487
	488	/* create the pool for ddp if not created yet */
	489	if (!fcoe->pool) {
	490	/* allocate ddp pool */
	491	fcoe->pool = pci_pool_create("ixgbe_fcoe_ddp",
	492	adapter->pdev, IXGBE_FCPTR_MAX,
	493	IXGBE_FCPTR_ALIGN, PAGE_SIZE);
	494	if (!fcoe->pool)
	495	DPRINTK(DRV, ERR,
	496	"failed to allocated FCoE DDP pool\n");
d3a2ae6d	497
d0ed8937 YZ	498	spin_lock_init(&fcoe->lock);
d0ed8937 YZ	499	}
d3a2ae6d YZ	500	/* L2 filter for FCoE: default to queue 0 */
	501	IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FCOE),
	502	(ETH_P_FCOE \| IXGBE_ETQF_FCOE \| IXGBE_ETQF_FILTER_EN));
	503	IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, 0);
	504	IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE),
	505	IXGBE_ETQS_QUEUE_EN);
	506	IXGBE_WRITE_REG(hw, IXGBE_FCRXCTRL,
	507	IXGBE_FCRXCTRL_FCOELLI \|
	508	IXGBE_FCRXCTRL_FCCRCBO \|
	509	(FC_FCOE_VER << IXGBE_FCRXCTRL_FCOEVER_SHIFT));
	510	}
d0ed8937 YZ	511
	512	/**
	513	* ixgbe_cleanup_fcoe - release all fcoe ddp context resources
	514	* @adapter : ixgbe adapter
	515	*
	516	* Cleans up outstanding ddp context resources
	517	*
	518	* Returns : none
	519	*/
	520	void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter)
	521	{
	522	int i;
	523	struct ixgbe_fcoe *fcoe = &adapter->fcoe;
	524
	525	/* release ddp resource */
	526	if (fcoe->pool) {
	527	for (i = 0; i < IXGBE_FCOE_DDP_MAX; i++)
	528	ixgbe_fcoe_ddp_put(adapter->netdev, i);
	529	pci_pool_destroy(fcoe->pool);
	530	fcoe->pool = NULL;
	531	}
	532	}