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ixgbe: rewrite ethtool test to use standard config functions
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_ethtool.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for ixgbe */
29
30#include <linux/types.h>
31#include <linux/module.h>
5a0e3ad6 32#include <linux/slab.h>
9a799d71
AK		 33#include <linux/pci.h>
34#include <linux/netdevice.h>
35#include <linux/ethtool.h>
36#include <linux/vmalloc.h>
37#include <linux/uaccess.h>
38
39#include "ixgbe.h"
40
41
42#define IXGBE_ALL_RAR_ENTRIES 16
43
29c3a050
AK		 44enum {NETDEV_STATS, IXGBE_STATS};
45
9a799d71
AK		 46struct ixgbe_stats {
47 char stat_string[ETH_GSTRING_LEN];
29c3a050 48 int type;
9a799d71
AK		 49 int sizeof_stat;
50 int stat_offset;
51};
52
29c3a050
AK		 53#define IXGBE_STAT(m) IXGBE_STATS, \
54 sizeof(((struct ixgbe_adapter *)0)->m), \
55 offsetof(struct ixgbe_adapter, m)
56#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
55bad823
ED		 57 sizeof(((struct rtnl_link_stats64 *)0)->m), \
58 offsetof(struct rtnl_link_stats64, m)
29c3a050 59
9a799d71 60static struct ixgbe_stats ixgbe_gstrings_stats[] = {
55bad823
ED		 61 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
62 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
63 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
64 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
aad71918
BG		 65 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
66 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
67 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
68 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
9a799d71
AK		 69 {"lsc_int", IXGBE_STAT(lsc_int)},
70 {"tx_busy", IXGBE_STAT(tx_busy)},
71 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
55bad823
ED		 72 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
73 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
74 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
75 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
76 {"multicast", IXGBE_NETDEV_STAT(multicast)},
9a799d71
AK		 77 {"broadcast", IXGBE_STAT(stats.bprc)},
78 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
55bad823
ED		 79 {"collisions", IXGBE_NETDEV_STAT(collisions)},
80 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
81 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
82 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
94b982b2
MC		 83 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
84 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
c4cf55e5
PWJ		 85 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
86 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
55bad823
ED		 87 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
88 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
89 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
90 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
91 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
92 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
9a799d71
AK		 93 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
94 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
95 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
96 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
9a799d71
AK		 97 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
98 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
99 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
100 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
9a799d71 101 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
9a799d71
AK		 102 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
103 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
e8e26350 104 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
6d45522c
YZ		 105#ifdef IXGBE_FCOE
106 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
107 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
108 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
109 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
110 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
111 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
112#endif /* IXGBE_FCOE */
9a799d71
AK		 113};
114
115#define IXGBE_QUEUE_STATS_LEN \
454d7c9b
WC		 116 ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
117 ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
118 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
b4617240 119#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
2f90b865 120#define IXGBE_PB_STATS_LEN ( \
9d2f4720 121 (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
2f90b865
AD		 122 IXGBE_FLAG_DCB_ENABLED) ? \
123 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
124 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
125 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
126 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
127 / sizeof(u64) : 0)
128#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
129 IXGBE_PB_STATS_LEN + \
130 IXGBE_QUEUE_STATS_LEN)
9a799d71 131
da4dd0f7
PWJ		 132static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
133 "Register test (offline)", "Eeprom test (offline)",
134 "Interrupt test (offline)", "Loopback test (offline)",
135 "Link test (on/offline)"
136};
137#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
138
9a799d71 139static int ixgbe_get_settings(struct net_device *netdev,
b4617240 140 struct ethtool_cmd *ecmd)
9a799d71
AK		 141{
142 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb
AV		 143 struct ixgbe_hw *hw = &adapter->hw;
144 u32 link_speed = 0;
145 bool link_up;
9a799d71 146
735441fb
AV		 147 ecmd->supported = SUPPORTED_10000baseT_Full;
148 ecmd->autoneg = AUTONEG_ENABLE;
9a799d71 149 ecmd->transceiver = XCVR_EXTERNAL;
74766013 150 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 151 (hw->phy.multispeed_fiber)) {
735441fb 152 ecmd->supported |= (SUPPORTED_1000baseT_Full |
74766013 153 SUPPORTED_Autoneg);
735441fb 154
74766013 155 ecmd->advertising = ADVERTISED_Autoneg;
735441fb
AV		 156 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
157 ecmd->advertising |= ADVERTISED_10000baseT_Full;
158 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
159 ecmd->advertising |= ADVERTISED_1000baseT_Full;
7c5b8323
DS		 160 /*
161 * It's possible that phy.autoneg_advertised may not be
162 * set yet. If so display what the default would be -
163 * both 1G and 10G supported.
164 */
165 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
166 ADVERTISED_10000baseT_Full)))
167 ecmd->advertising |= (ADVERTISED_10000baseT_Full |
168 ADVERTISED_1000baseT_Full);
735441fb 169
74766013
MC		 170 if (hw->phy.media_type == ixgbe_media_type_copper) {
171 ecmd->supported |= SUPPORTED_TP;
172 ecmd->advertising |= ADVERTISED_TP;
173 ecmd->port = PORT_TP;
174 } else {
175 ecmd->supported |= SUPPORTED_FIBRE;
176 ecmd->advertising |= ADVERTISED_FIBRE;
177 ecmd->port = PORT_FIBRE;
178 }
1e336d0f
DS		 179 } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
180 /* Set as FIBRE until SERDES defined in kernel */
46a72b35 181 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
2f21bdd3
DS		 182 ecmd->supported = (SUPPORTED_1000baseT_Full |
183 SUPPORTED_FIBRE);
184 ecmd->advertising = (ADVERTISED_1000baseT_Full |
185 ADVERTISED_FIBRE);
186 ecmd->port = PORT_FIBRE;
187 ecmd->autoneg = AUTONEG_DISABLE;
46a72b35
MC		 188 } else {
189 ecmd->supported |= (SUPPORTED_1000baseT_Full |
190 SUPPORTED_FIBRE);
191 ecmd->advertising = (ADVERTISED_10000baseT_Full |
192 ADVERTISED_1000baseT_Full |
193 ADVERTISED_FIBRE);
194 ecmd->port = PORT_FIBRE;
1e336d0f 195 }
735441fb
AV		 196 } else {
197 ecmd->supported |= SUPPORTED_FIBRE;
198 ecmd->advertising = (ADVERTISED_10000baseT_Full |
b4617240 199 ADVERTISED_FIBRE);
735441fb 200 ecmd->port = PORT_FIBRE;
c44ade9e 201 ecmd->autoneg = AUTONEG_DISABLE;
735441fb 202 }
9a799d71 203
3b8626ba
PW		 204 /* Get PHY type */
205 switch (adapter->hw.phy.type) {
206 case ixgbe_phy_tn:
207 case ixgbe_phy_cu_unknown:
208 /* Copper 10G-BASET */
209 ecmd->port = PORT_TP;
210 break;
211 case ixgbe_phy_qt:
212 ecmd->port = PORT_FIBRE;
213 break;
214 case ixgbe_phy_nl:
ea0a04df
DS		 215 case ixgbe_phy_sfp_passive_tyco:
216 case ixgbe_phy_sfp_passive_unknown:
3b8626ba
PW		 217 case ixgbe_phy_sfp_ftl:
218 case ixgbe_phy_sfp_avago:
219 case ixgbe_phy_sfp_intel:
220 case ixgbe_phy_sfp_unknown:
221 switch (adapter->hw.phy.sfp_type) {
222 /* SFP+ devices, further checking needed */
223 case ixgbe_sfp_type_da_cu:
224 case ixgbe_sfp_type_da_cu_core0:
225 case ixgbe_sfp_type_da_cu_core1:
226 ecmd->port = PORT_DA;
227 break;
228 case ixgbe_sfp_type_sr:
229 case ixgbe_sfp_type_lr:
230 case ixgbe_sfp_type_srlr_core0:
231 case ixgbe_sfp_type_srlr_core1:
232 ecmd->port = PORT_FIBRE;
233 break;
234 case ixgbe_sfp_type_not_present:
235 ecmd->port = PORT_NONE;
236 break;
cb836a97
DS		 237 case ixgbe_sfp_type_1g_cu_core0:
238 case ixgbe_sfp_type_1g_cu_core1:
239 ecmd->port = PORT_TP;
240 ecmd->supported = SUPPORTED_TP;
241 ecmd->advertising = (ADVERTISED_1000baseT_Full |
242 ADVERTISED_TP);
243 break;
3b8626ba
PW		 244 case ixgbe_sfp_type_unknown:
245 default:
246 ecmd->port = PORT_OTHER;
247 break;
248 }
249 break;
250 case ixgbe_phy_xaui:
251 ecmd->port = PORT_NONE;
252 break;
253 case ixgbe_phy_unknown:
254 case ixgbe_phy_generic:
255 case ixgbe_phy_sfp_unsupported:
256 default:
257 ecmd->port = PORT_OTHER;
258 break;
259 }
260
c44ade9e 261 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
735441fb
AV		 262 if (link_up) {
263 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
b4617240 264 SPEED_10000 : SPEED_1000;
9a799d71
AK		 265 ecmd->duplex = DUPLEX_FULL;
266 } else {
267 ecmd->speed = -1;
268 ecmd->duplex = -1;
269 }
270
9a799d71
AK		 271 return 0;
272}
273
274static int ixgbe_set_settings(struct net_device *netdev,
b4617240 275 struct ethtool_cmd *ecmd)
9a799d71
AK		 276{
277 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 278 struct ixgbe_hw *hw = &adapter->hw;
0befdb3e 279 u32 advertised, old;
74766013 280 s32 err = 0;
9a799d71 281
74766013 282 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 283 (hw->phy.multispeed_fiber)) {
0befdb3e
JB		 284 /* 10000/copper and 1000/copper must autoneg
285 * this function does not support any duplex forcing, but can
286 * limit the advertising of the adapter to only 10000 or 1000 */
287 if (ecmd->autoneg == AUTONEG_DISABLE)
288 return -EINVAL;
289
290 old = hw->phy.autoneg_advertised;
291 advertised = 0;
292 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
293 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
294
295 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
296 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
297
298 if (old == advertised)
74766013 299 return err;
0befdb3e 300 /* this sets the link speed and restarts auto-neg */
74766013 301 hw->mac.autotry_restart = true;
8620a103 302 err = hw->mac.ops.setup_link(hw, advertised, true, true);
0befdb3e 303 if (err) {
396e799c 304 e_info(probe, "setup link failed with code %d\n", err);
8620a103 305 hw->mac.ops.setup_link(hw, old, true, true);
0befdb3e 306 }
74766013
MC		 307 } else {
308 /* in this case we currently only support 10Gb/FULL */
309 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
a3801379 310 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
74766013
MC		 311 (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
312 return -EINVAL;
9a799d71
AK		 313 }
314
74766013 315 return err;
9a799d71
AK		 316}
317
318static void ixgbe_get_pauseparam(struct net_device *netdev,
b4617240 319 struct ethtool_pauseparam *pause)
9a799d71
AK		 320{
321 struct ixgbe_adapter *adapter = netdev_priv(netdev);
322 struct ixgbe_hw *hw = &adapter->hw;
323
71fd570b
DS		 324 /*
325 * Flow Control Autoneg isn't on if
326 * - we didn't ask for it OR
327 * - it failed, we know this by tx & rx being off
328 */
329 if (hw->fc.disable_fc_autoneg ||
330 (hw->fc.current_mode == ixgbe_fc_none))
331 pause->autoneg = 0;
332 else
333 pause->autoneg = 1;
9a799d71 334
8756924c
PWJ		 335#ifdef CONFIG_DCB
336 if (hw->fc.current_mode == ixgbe_fc_pfc) {
337 pause->rx_pause = 0;
338 pause->tx_pause = 0;
339 }
340
341#endif
0ecc061d 342 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
9a799d71 343 pause->rx_pause = 1;
0ecc061d 344 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
9a799d71 345 pause->tx_pause = 1;
0ecc061d 346 } else if (hw->fc.current_mode == ixgbe_fc_full) {
9a799d71
AK		 347 pause->rx_pause = 1;
348 pause->tx_pause = 1;
349 }
350}
351
352static int ixgbe_set_pauseparam(struct net_device *netdev,
b4617240 353 struct ethtool_pauseparam *pause)
9a799d71
AK		 354{
355 struct ixgbe_adapter *adapter = netdev_priv(netdev);
356 struct ixgbe_hw *hw = &adapter->hw;
620fa036 357 struct ixgbe_fc_info fc;
9a799d71 358
264857b8
PWJ		 359#ifdef CONFIG_DCB
360 if (adapter->dcb_cfg.pfc_mode_enable ||
361 ((hw->mac.type == ixgbe_mac_82598EB) &&
362 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
363 return -EINVAL;
364
365#endif
620fa036
MC		 366
367 fc = hw->fc;
368
71fd570b 369 if (pause->autoneg != AUTONEG_ENABLE)
620fa036 370 fc.disable_fc_autoneg = true;
71fd570b 371 else
620fa036 372 fc.disable_fc_autoneg = false;
71fd570b 373
1c4f0ef8 374 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
620fa036 375 fc.requested_mode = ixgbe_fc_full;
9a799d71 376 else if (pause->rx_pause && !pause->tx_pause)
620fa036 377 fc.requested_mode = ixgbe_fc_rx_pause;
9a799d71 378 else if (!pause->rx_pause && pause->tx_pause)
620fa036 379 fc.requested_mode = ixgbe_fc_tx_pause;
9a799d71 380 else if (!pause->rx_pause && !pause->tx_pause)
620fa036 381 fc.requested_mode = ixgbe_fc_none;
9c83b070
AV		 382 else
383 return -EINVAL;
9a799d71 384
264857b8 385#ifdef CONFIG_DCB
620fa036 386 adapter->last_lfc_mode = fc.requested_mode;
264857b8 387#endif
620fa036
MC		 388
389 /* if the thing changed then we'll update and use new autoneg */
390 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
391 hw->fc = fc;
392 if (netif_running(netdev))
393 ixgbe_reinit_locked(adapter);
394 else
395 ixgbe_reset(adapter);
396 }
9a799d71
AK		 397
398 return 0;
399}
400
401static u32 ixgbe_get_rx_csum(struct net_device *netdev)
402{
403 struct ixgbe_adapter *adapter = netdev_priv(netdev);
404 return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
405}
406
407static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
408{
409 struct ixgbe_adapter *adapter = netdev_priv(netdev);
410 if (data)
411 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
412 else
413 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
414
d4f80882
AV		 415 if (netif_running(netdev))
416 ixgbe_reinit_locked(adapter);
417 else
9a799d71 418 ixgbe_reset(adapter);
9a799d71
AK		 419
420 return 0;
421}
422
423static u32 ixgbe_get_tx_csum(struct net_device *netdev)
424{
22f32b7a 425 return (netdev->features & NETIF_F_IP_CSUM) != 0;
9a799d71
AK		 426}
427
428static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
429{
45a5ead0
JB		 430 struct ixgbe_adapter *adapter = netdev_priv(netdev);
431
432 if (data) {
22f32b7a 433 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
45a5ead0
JB		 434 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
435 netdev->features |= NETIF_F_SCTP_CSUM;
436 } else {
3d3d6d3c 437 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
45a5ead0
JB		 438 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
439 netdev->features &= ~NETIF_F_SCTP_CSUM;
440 }
9a799d71
AK		 441
442 return 0;
443}
444
445static int ixgbe_set_tso(struct net_device *netdev, u32 data)
446{
9a799d71
AK		 447 if (data) {
448 netdev->features |= NETIF_F_TSO;
449 netdev->features |= NETIF_F_TSO6;
450 } else {
451 netdev->features &= ~NETIF_F_TSO;
452 netdev->features &= ~NETIF_F_TSO6;
453 }
454 return 0;
455}
456
457static u32 ixgbe_get_msglevel(struct net_device *netdev)
458{
459 struct ixgbe_adapter *adapter = netdev_priv(netdev);
460 return adapter->msg_enable;
461}
462
463static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
464{
465 struct ixgbe_adapter *adapter = netdev_priv(netdev);
466 adapter->msg_enable = data;
467}
468
469static int ixgbe_get_regs_len(struct net_device *netdev)
470{
471#define IXGBE_REGS_LEN 1128
472 return IXGBE_REGS_LEN * sizeof(u32);
473}
474
475#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
476
477static void ixgbe_get_regs(struct net_device *netdev,
b4617240 478 struct ethtool_regs *regs, void *p)
9a799d71
AK		 479{
480 struct ixgbe_adapter *adapter = netdev_priv(netdev);
481 struct ixgbe_hw *hw = &adapter->hw;
482 u32 *regs_buff = p;
483 u8 i;
484
485 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
486
487 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
488
489 /* General Registers */
490 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
491 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
492 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
493 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
494 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
495 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
496 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
497 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
498
499 /* NVM Register */
500 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
501 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
502 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
503 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
504 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
505 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
506 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
507 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
508 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
509 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
510
511 /* Interrupt */
98c00a1c
JB		 512 /* don't read EICR because it can clear interrupt causes, instead
513 * read EICS which is a shadow but doesn't clear EICR */
514 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
9a799d71
AK		 515 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
516 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
517 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
518 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
519 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
520 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
521 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
522 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
523 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
c44ade9e 524 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
9a799d71
AK		 525 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
526
527 /* Flow Control */
528 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
529 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
530 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
531 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
532 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
533 for (i = 0; i < 8; i++)
534 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
535 for (i = 0; i < 8; i++)
536 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
537 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
538 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
539
540 /* Receive DMA */
541 for (i = 0; i < 64; i++)
542 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
543 for (i = 0; i < 64; i++)
544 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
545 for (i = 0; i < 64; i++)
546 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
547 for (i = 0; i < 64; i++)
548 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
549 for (i = 0; i < 64; i++)
550 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
551 for (i = 0; i < 64; i++)
552 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
553 for (i = 0; i < 16; i++)
554 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
555 for (i = 0; i < 16; i++)
556 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
557 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
558 for (i = 0; i < 8; i++)
559 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
560 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
561 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
562
563 /* Receive */
564 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
565 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
566 for (i = 0; i < 16; i++)
567 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
568 for (i = 0; i < 16; i++)
569 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
c44ade9e 570 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
9a799d71
AK		 571 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
572 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
573 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
574 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
575 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
576 for (i = 0; i < 8; i++)
577 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
578 for (i = 0; i < 8; i++)
579 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
580 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
581
582 /* Transmit */
583 for (i = 0; i < 32; i++)
584 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
585 for (i = 0; i < 32; i++)
586 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
587 for (i = 0; i < 32; i++)
588 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
589 for (i = 0; i < 32; i++)
590 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
591 for (i = 0; i < 32; i++)
592 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
593 for (i = 0; i < 32; i++)
594 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
595 for (i = 0; i < 32; i++)
596 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
597 for (i = 0; i < 32; i++)
598 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
599 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
600 for (i = 0; i < 16; i++)
601 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
602 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
603 for (i = 0; i < 8; i++)
604 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
605 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
606
607 /* Wake Up */
608 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
609 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
610 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
611 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
612 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
613 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
614 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
615 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
11afc1b1 616 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
9a799d71 617
9a799d71
AK		 618 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
619 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
620 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
621 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
622 for (i = 0; i < 8; i++)
623 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
624 for (i = 0; i < 8; i++)
625 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
626 for (i = 0; i < 8; i++)
627 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
628 for (i = 0; i < 8; i++)
629 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
630 for (i = 0; i < 8; i++)
631 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
632 for (i = 0; i < 8; i++)
633 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
634
635 /* Statistics */
636 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
637 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
638 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
639 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
640 for (i = 0; i < 8; i++)
641 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
642 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
643 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
644 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
645 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
646 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
647 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
648 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
649 for (i = 0; i < 8; i++)
650 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
651 for (i = 0; i < 8; i++)
652 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
653 for (i = 0; i < 8; i++)
654 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
655 for (i = 0; i < 8; i++)
656 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
657 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
658 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
659 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
660 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
661 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
662 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
663 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
664 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
665 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
666 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
667 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
668 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
669 for (i = 0; i < 8; i++)
670 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
671 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
672 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
673 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
674 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
675 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
676 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
677 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
678 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
679 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
680 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
681 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
682 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
683 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
684 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
685 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
686 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
687 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
688 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
689 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
690 for (i = 0; i < 16; i++)
691 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
692 for (i = 0; i < 16; i++)
693 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
694 for (i = 0; i < 16; i++)
695 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
696 for (i = 0; i < 16; i++)
697 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
698
699 /* MAC */
700 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
701 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
702 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
703 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
704 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
705 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
706 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
707 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
708 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
709 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
710 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
711 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
712 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
713 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
714 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
715 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
716 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
717 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
718 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
719 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
720 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
721 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
722 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
723 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
724 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
725 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
726 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
727 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
728 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
729 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
730 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
731 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
732 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
733
734 /* Diagnostic */
735 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
736 for (i = 0; i < 8; i++)
98c00a1c 737 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
9a799d71 738 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
98c00a1c
JB		 739 for (i = 0; i < 4; i++)
740 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
9a799d71
AK		 741 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
742 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
743 for (i = 0; i < 8; i++)
98c00a1c 744 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
9a799d71 745 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
98c00a1c
JB		 746 for (i = 0; i < 4; i++)
747 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
9a799d71
AK		 748 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
749 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
750 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
751 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
752 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
753 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
754 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
755 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
756 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
757 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
758 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
759 for (i = 0; i < 8; i++)
98c00a1c 760 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
9a799d71
AK		 761 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
762 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
763 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
764 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
765 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
766 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
767 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
768 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
769 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
770}
771
772static int ixgbe_get_eeprom_len(struct net_device *netdev)
773{
774 struct ixgbe_adapter *adapter = netdev_priv(netdev);
775 return adapter->hw.eeprom.word_size * 2;
776}
777
778static int ixgbe_get_eeprom(struct net_device *netdev,
b4617240 779 struct ethtool_eeprom *eeprom, u8 *bytes)
9a799d71
AK		 780{
781 struct ixgbe_adapter *adapter = netdev_priv(netdev);
782 struct ixgbe_hw *hw = &adapter->hw;
783 u16 *eeprom_buff;
784 int first_word, last_word, eeprom_len;
785 int ret_val = 0;
786 u16 i;
787
788 if (eeprom->len == 0)
789 return -EINVAL;
790
791 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
792
793 first_word = eeprom->offset >> 1;
794 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
795 eeprom_len = last_word - first_word + 1;
796
797 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
798 if (!eeprom_buff)
799 return -ENOMEM;
800
801 for (i = 0; i < eeprom_len; i++) {
c44ade9e 802 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
b4617240 803 &eeprom_buff[i])))
9a799d71
AK		 804 break;
805 }
806
807 /* Device's eeprom is always little-endian, word addressable */
808 for (i = 0; i < eeprom_len; i++)
809 le16_to_cpus(&eeprom_buff[i]);
810
811 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
812 kfree(eeprom_buff);
813
814 return ret_val;
815}
816
817static void ixgbe_get_drvinfo(struct net_device *netdev,
b4617240 818 struct ethtool_drvinfo *drvinfo)
9a799d71
AK		 819{
820 struct ixgbe_adapter *adapter = netdev_priv(netdev);
34b0368c 821 char firmware_version[32];
9a799d71 822
083fc582
DS		 823 strncpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
824 strncpy(drvinfo->version, ixgbe_driver_version,
825 sizeof(drvinfo->version));
826
827 snprintf(firmware_version, sizeof(firmware_version), "%d.%d-%d",
828 (adapter->eeprom_version & 0xF000) >> 12,
829 (adapter->eeprom_version & 0x0FF0) >> 4,
830 adapter->eeprom_version & 0x000F);
831
832 strncpy(drvinfo->fw_version, firmware_version,
833 sizeof(drvinfo->fw_version));
834 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
835 sizeof(drvinfo->bus_info));
9a799d71 836 drvinfo->n_stats = IXGBE_STATS_LEN;
da4dd0f7 837 drvinfo->testinfo_len = IXGBE_TEST_LEN;
9a799d71
AK		 838 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
839}
840
841static void ixgbe_get_ringparam(struct net_device *netdev,
b4617240 842 struct ethtool_ringparam *ring)
9a799d71
AK		 843{
844 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4a0b9ca0
PW		 845 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
846 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
9a799d71
AK		 847
848 ring->rx_max_pending = IXGBE_MAX_RXD;
849 ring->tx_max_pending = IXGBE_MAX_TXD;
850 ring->rx_mini_max_pending = 0;
851 ring->rx_jumbo_max_pending = 0;
852 ring->rx_pending = rx_ring->count;
853 ring->tx_pending = tx_ring->count;
854 ring->rx_mini_pending = 0;
855 ring->rx_jumbo_pending = 0;
856}
857
858static int ixgbe_set_ringparam(struct net_device *netdev,
b4617240 859 struct ethtool_ringparam *ring)
9a799d71
AK		 860{
861 struct ixgbe_adapter *adapter = netdev_priv(netdev);
f9ed8854 862 struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
759884b4 863 int i, err = 0;
c431f97e 864 u32 new_rx_count, new_tx_count;
f9ed8854 865 bool need_update = false;
9a799d71
AK		 866
867 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
868 return -EINVAL;
869
870 new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
871 new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
872 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
873
874 new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
875 new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
876 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
877
4a0b9ca0
PW		 878 if ((new_tx_count == adapter->tx_ring[0]->count) &&
879 (new_rx_count == adapter->rx_ring[0]->count)) {
9a799d71
AK		 880 /* nothing to do */
881 return 0;
882 }
883
d4f80882
AV		 884 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
885 msleep(1);
886
759884b4
AD		 887 if (!netif_running(adapter->netdev)) {
888 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 889 adapter->tx_ring[i]->count = new_tx_count;
759884b4 890 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 891 adapter->rx_ring[i]->count = new_rx_count;
759884b4
AD		 892 adapter->tx_ring_count = new_tx_count;
893 adapter->rx_ring_count = new_rx_count;
4a0b9ca0 894 goto clear_reset;
759884b4
AD		 895 }
896
4a0b9ca0 897 temp_tx_ring = vmalloc(adapter->num_tx_queues * sizeof(struct ixgbe_ring));
f9ed8854
MC		 898 if (!temp_tx_ring) {
899 err = -ENOMEM;
4a0b9ca0 900 goto clear_reset;
f9ed8854
MC		 901 }
902
903 if (new_tx_count != adapter->tx_ring_count) {
9a799d71 904 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 905 memcpy(&temp_tx_ring[i], adapter->tx_ring[i],
906 sizeof(struct ixgbe_ring));
f9ed8854
MC		 907 temp_tx_ring[i].count = new_tx_count;
908 err = ixgbe_setup_tx_resources(adapter,
909 &temp_tx_ring[i]);
9a799d71 910 if (err) {
c431f97e
JB		 911 while (i) {
912 i--;
b4617240 913 ixgbe_free_tx_resources(adapter,
4a0b9ca0 914 &temp_tx_ring[i]);
c431f97e 915 }
4a0b9ca0 916 goto clear_reset;
9a799d71 917 }
9a799d71 918 }
f9ed8854 919 need_update = true;
9a799d71
AK		 920 }
921
4a0b9ca0
PW		 922 temp_rx_ring = vmalloc(adapter->num_rx_queues * sizeof(struct ixgbe_ring));
923 if (!temp_rx_ring) {
f9ed8854
MC		 924 err = -ENOMEM;
925 goto err_setup;
d3fa4721 926 }
9a799d71 927
f9ed8854 928 if (new_rx_count != adapter->rx_ring_count) {
c431f97e 929 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 930 memcpy(&temp_rx_ring[i], adapter->rx_ring[i],
931 sizeof(struct ixgbe_ring));
f9ed8854
MC		 932 temp_rx_ring[i].count = new_rx_count;
933 err = ixgbe_setup_rx_resources(adapter,
934 &temp_rx_ring[i]);
9a799d71 935 if (err) {
c431f97e
JB		 936 while (i) {
937 i--;
b4617240 938 ixgbe_free_rx_resources(adapter,
f9ed8854 939 &temp_rx_ring[i]);
c431f97e 940 }
9a799d71
AK		 941 goto err_setup;
942 }
9a799d71 943 }
f9ed8854
MC		 944 need_update = true;
945 }
946
947 /* if rings need to be updated, here's the place to do it in one shot */
948 if (need_update) {
759884b4 949 ixgbe_down(adapter);
f9ed8854
MC		 950
951 /* tx */
952 if (new_tx_count != adapter->tx_ring_count) {
4a0b9ca0
PW		 953 for (i = 0; i < adapter->num_tx_queues; i++) {
954 ixgbe_free_tx_resources(adapter,
955 adapter->tx_ring[i]);
956 memcpy(adapter->tx_ring[i], &temp_tx_ring[i],
957 sizeof(struct ixgbe_ring));
958 }
f9ed8854
MC		 959 adapter->tx_ring_count = new_tx_count;
960 }
961
962 /* rx */
963 if (new_rx_count != adapter->rx_ring_count) {
4a0b9ca0
PW		 964 for (i = 0; i < adapter->num_rx_queues; i++) {
965 ixgbe_free_rx_resources(adapter,
966 adapter->rx_ring[i]);
967 memcpy(adapter->rx_ring[i], &temp_rx_ring[i],
968 sizeof(struct ixgbe_ring));
969 }
f9ed8854
MC		 970 adapter->rx_ring_count = new_rx_count;
971 }
f9ed8854 972 ixgbe_up(adapter);
759884b4 973 }
4a0b9ca0
PW		 974
975 vfree(temp_rx_ring);
f9ed8854 976err_setup:
4a0b9ca0
PW		 977 vfree(temp_tx_ring);
978clear_reset:
d4f80882 979 clear_bit(__IXGBE_RESETTING, &adapter->state);
9a799d71
AK		 980 return err;
981}
982
b9f2c044 983static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
9a799d71 984{
b9f2c044 985 switch (sset) {
da4dd0f7
PWJ		 986 case ETH_SS_TEST:
987 return IXGBE_TEST_LEN;
b9f2c044
JG		 988 case ETH_SS_STATS:
989 return IXGBE_STATS_LEN;
9a713e7c
PW		 990 case ETH_SS_NTUPLE_FILTERS:
991 return (ETHTOOL_MAX_NTUPLE_LIST_ENTRY *
992 ETHTOOL_MAX_NTUPLE_STRING_PER_ENTRY);
b9f2c044
JG		 993 default:
994 return -EOPNOTSUPP;
995 }
9a799d71
AK		 996}
997
998static void ixgbe_get_ethtool_stats(struct net_device *netdev,
b4617240 999 struct ethtool_stats *stats, u64 *data)
9a799d71
AK		 1000{
1001 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1002 u64 *queue_stat;
1003 int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
28172739
ED		 1004 struct rtnl_link_stats64 temp;
1005 const struct rtnl_link_stats64 *net_stats;
9a799d71
AK		 1006 int j, k;
1007 int i;
29c3a050 1008 char *p = NULL;
9a799d71
AK		 1009
1010 ixgbe_update_stats(adapter);
28172739 1011 net_stats = dev_get_stats(netdev, &temp);
9a799d71 1012 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
29c3a050
AK		 1013 switch (ixgbe_gstrings_stats[i].type) {
1014 case NETDEV_STATS:
28172739 1015 p = (char *) net_stats +
29c3a050
AK		 1016 ixgbe_gstrings_stats[i].stat_offset;
1017 break;
1018 case IXGBE_STATS:
1019 p = (char *) adapter +
1020 ixgbe_gstrings_stats[i].stat_offset;
1021 break;
1022 }
1023
9a799d71 1024 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
b4617240 1025 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
9a799d71
AK		 1026 }
1027 for (j = 0; j < adapter->num_tx_queues; j++) {
4a0b9ca0 1028 queue_stat = (u64 *)&adapter->tx_ring[j]->stats;
9a799d71
AK		 1029 for (k = 0; k < stat_count; k++)
1030 data[i + k] = queue_stat[k];
1031 i += k;
1032 }
1033 for (j = 0; j < adapter->num_rx_queues; j++) {
4a0b9ca0 1034 queue_stat = (u64 *)&adapter->rx_ring[j]->stats;
9a799d71
AK		 1035 for (k = 0; k < stat_count; k++)
1036 data[i + k] = queue_stat[k];
1037 i += k;
1038 }
2f90b865
AD		 1039 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1040 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
1041 data[i++] = adapter->stats.pxontxc[j];
1042 data[i++] = adapter->stats.pxofftxc[j];
1043 }
1044 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
1045 data[i++] = adapter->stats.pxonrxc[j];
1046 data[i++] = adapter->stats.pxoffrxc[j];
1047 }
1048 }
9a799d71
AK		 1049}
1050
1051static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
b4617240 1052 u8 *data)
9a799d71
AK		 1053{
1054 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1055 char *p = (char *)data;
9a799d71
AK		 1056 int i;
1057
1058 switch (stringset) {
da4dd0f7
PWJ		 1059 case ETH_SS_TEST:
1060 memcpy(data, *ixgbe_gstrings_test,
1061 IXGBE_TEST_LEN * ETH_GSTRING_LEN);
1062 break;
9a799d71
AK		 1063 case ETH_SS_STATS:
1064 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1065 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1066 ETH_GSTRING_LEN);
1067 p += ETH_GSTRING_LEN;
1068 }
1069 for (i = 0; i < adapter->num_tx_queues; i++) {
1070 sprintf(p, "tx_queue_%u_packets", i);
1071 p += ETH_GSTRING_LEN;
1072 sprintf(p, "tx_queue_%u_bytes", i);
1073 p += ETH_GSTRING_LEN;
1074 }
1075 for (i = 0; i < adapter->num_rx_queues; i++) {
1076 sprintf(p, "rx_queue_%u_packets", i);
1077 p += ETH_GSTRING_LEN;
1078 sprintf(p, "rx_queue_%u_bytes", i);
1079 p += ETH_GSTRING_LEN;
1080 }
2f90b865
AD		 1081 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1082 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
1083 sprintf(p, "tx_pb_%u_pxon", i);
bfb8cc31
DS		 1084 p += ETH_GSTRING_LEN;
1085 sprintf(p, "tx_pb_%u_pxoff", i);
1086 p += ETH_GSTRING_LEN;
2f90b865
AD		 1087 }
1088 for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
bfb8cc31
DS		 1089 sprintf(p, "rx_pb_%u_pxon", i);
1090 p += ETH_GSTRING_LEN;
1091 sprintf(p, "rx_pb_%u_pxoff", i);
1092 p += ETH_GSTRING_LEN;
2f90b865
AD		 1093 }
1094 }
b4617240 1095 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
9a799d71
AK		 1096 break;
1097 }
1098}
1099
da4dd0f7
PWJ		 1100static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1101{
1102 struct ixgbe_hw *hw = &adapter->hw;
1103 bool link_up;
1104 u32 link_speed = 0;
1105 *data = 0;
1106
1107 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1108 if (link_up)
1109 return *data;
1110 else
1111 *data = 1;
1112 return *data;
1113}
1114
1115/* ethtool register test data */
1116struct ixgbe_reg_test {
1117 u16 reg;
1118 u8 array_len;
1119 u8 test_type;
1120 u32 mask;
1121 u32 write;
1122};
1123
1124/* In the hardware, registers are laid out either singly, in arrays
1125 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1126 * most tests take place on arrays or single registers (handled
1127 * as a single-element array) and special-case the tables.
1128 * Table tests are always pattern tests.
1129 *
1130 * We also make provision for some required setup steps by specifying
1131 * registers to be written without any read-back testing.
1132 */
1133
1134#define PATTERN_TEST 1
1135#define SET_READ_TEST 2
1136#define WRITE_NO_TEST 3
1137#define TABLE32_TEST 4
1138#define TABLE64_TEST_LO 5
1139#define TABLE64_TEST_HI 6
1140
1141/* default 82599 register test */
1142static struct ixgbe_reg_test reg_test_82599[] = {
1143 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1144 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1145 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1146 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1147 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1148 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1149 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1150 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1151 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1152 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1153 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1154 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1155 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1156 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1157 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1158 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1159 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1160 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1161 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1162 { 0, 0, 0, 0 }
1163};
1164
1165/* default 82598 register test */
1166static struct ixgbe_reg_test reg_test_82598[] = {
1167 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1168 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1169 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1170 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1171 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1172 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1173 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1174 /* Enable all four RX queues before testing. */
1175 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1176 /* RDH is read-only for 82598, only test RDT. */
1177 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1178 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1179 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1180 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1181 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1182 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1183 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1184 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1185 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1186 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1187 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1188 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1189 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1190 { 0, 0, 0, 0 }
1191};
1192
1193#define REG_PATTERN_TEST(R, M, W) \
1194{ \
1195 u32 pat, val, before; \
1196 const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1197 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { \
1198 before = readl(adapter->hw.hw_addr + R); \
1199 writel((_test[pat] & W), (adapter->hw.hw_addr + R)); \
1200 val = readl(adapter->hw.hw_addr + R); \
1201 if (val != (_test[pat] & W & M)) { \
396e799c
ET		 1202 e_err(drv, "pattern test reg %04X failed: got " \
1203 "0x%08X expected 0x%08X\n", \
849c4542 1204 R, val, (_test[pat] & W & M)); \
da4dd0f7
PWJ		 1205 *data = R; \
1206 writel(before, adapter->hw.hw_addr + R); \
1207 return 1; \
1208 } \
1209 writel(before, adapter->hw.hw_addr + R); \
1210 } \
1211}
1212
1213#define REG_SET_AND_CHECK(R, M, W) \
1214{ \
1215 u32 val, before; \
1216 before = readl(adapter->hw.hw_addr + R); \
1217 writel((W & M), (adapter->hw.hw_addr + R)); \
1218 val = readl(adapter->hw.hw_addr + R); \
1219 if ((W & M) != (val & M)) { \
396e799c
ET		 1220 e_err(drv, "set/check reg %04X test failed: got 0x%08X " \
1221 "expected 0x%08X\n", R, (val & M), (W & M)); \
da4dd0f7
PWJ		 1222 *data = R; \
1223 writel(before, (adapter->hw.hw_addr + R)); \
1224 return 1; \
1225 } \
1226 writel(before, (adapter->hw.hw_addr + R)); \
1227}
1228
1229static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1230{
1231 struct ixgbe_reg_test *test;
1232 u32 value, before, after;
1233 u32 i, toggle;
1234
1235 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1236 toggle = 0x7FFFF30F;
1237 test = reg_test_82599;
1238 } else {
1239 toggle = 0x7FFFF3FF;
1240 test = reg_test_82598;
1241 }
1242
1243 /*
1244 * Because the status register is such a special case,
1245 * we handle it separately from the rest of the register
1246 * tests. Some bits are read-only, some toggle, and some
1247 * are writeable on newer MACs.
1248 */
1249 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1250 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1251 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1252 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1253 if (value != after) {
396e799c
ET		 1254 e_err(drv, "failed STATUS register test got: 0x%08X "
1255 "expected: 0x%08X\n", after, value);
da4dd0f7
PWJ		 1256 *data = 1;
1257 return 1;
1258 }
1259 /* restore previous status */
1260 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1261
1262 /*
1263 * Perform the remainder of the register test, looping through
1264 * the test table until we either fail or reach the null entry.
1265 */
1266 while (test->reg) {
1267 for (i = 0; i < test->array_len; i++) {
1268 switch (test->test_type) {
1269 case PATTERN_TEST:
1270 REG_PATTERN_TEST(test->reg + (i * 0x40),
1271 test->mask,
1272 test->write);
1273 break;
1274 case SET_READ_TEST:
1275 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1276 test->mask,
1277 test->write);
1278 break;
1279 case WRITE_NO_TEST:
1280 writel(test->write,
1281 (adapter->hw.hw_addr + test->reg)
1282 + (i * 0x40));
1283 break;
1284 case TABLE32_TEST:
1285 REG_PATTERN_TEST(test->reg + (i * 4),
1286 test->mask,
1287 test->write);
1288 break;
1289 case TABLE64_TEST_LO:
1290 REG_PATTERN_TEST(test->reg + (i * 8),
1291 test->mask,
1292 test->write);
1293 break;
1294 case TABLE64_TEST_HI:
1295 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1296 test->mask,
1297 test->write);
1298 break;
1299 }
1300 }
1301 test++;
1302 }
1303
1304 *data = 0;
1305 return 0;
1306}
1307
1308static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1309{
1310 struct ixgbe_hw *hw = &adapter->hw;
1311 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1312 *data = 1;
1313 else
1314 *data = 0;
1315 return *data;
1316}
1317
1318static irqreturn_t ixgbe_test_intr(int irq, void *data)
1319{
1320 struct net_device *netdev = (struct net_device *) data;
1321 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1322
1323 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1324
1325 return IRQ_HANDLED;
1326}
1327
1328static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1329{
1330 struct net_device *netdev = adapter->netdev;
1331 u32 mask, i = 0, shared_int = true;
1332 u32 irq = adapter->pdev->irq;
1333
1334 *data = 0;
1335
1336 /* Hook up test interrupt handler just for this test */
1337 if (adapter->msix_entries) {
1338 /* NOTE: we don't test MSI-X interrupts here, yet */
1339 return 0;
1340 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1341 shared_int = false;
a0607fd3 1342 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
da4dd0f7
PWJ		 1343 netdev)) {
1344 *data = 1;
1345 return -1;
1346 }
a0607fd3 1347 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
da4dd0f7
PWJ		 1348 netdev->name, netdev)) {
1349 shared_int = false;
a0607fd3 1350 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
da4dd0f7
PWJ		 1351 netdev->name, netdev)) {
1352 *data = 1;
1353 return -1;
1354 }
396e799c
ET		 1355 e_info(hw, "testing %s interrupt\n", shared_int ?
1356 "shared" : "unshared");
da4dd0f7
PWJ		 1357
1358 /* Disable all the interrupts */
1359 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1360 msleep(10);
1361
1362 /* Test each interrupt */
1363 for (; i < 10; i++) {
1364 /* Interrupt to test */
1365 mask = 1 << i;
1366
1367 if (!shared_int) {
1368 /*
1369 * Disable the interrupts to be reported in
1370 * the cause register and then force the same
1371 * interrupt and see if one gets posted. If
1372 * an interrupt was posted to the bus, the
1373 * test failed.
1374 */
1375 adapter->test_icr = 0;
1376 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1377 ~mask & 0x00007FFF);
1378 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1379 ~mask & 0x00007FFF);
1380 msleep(10);
1381
1382 if (adapter->test_icr & mask) {
1383 *data = 3;
1384 break;
1385 }
1386 }
1387
1388 /*
1389 * Enable the interrupt to be reported in the cause
1390 * register and then force the same interrupt and see
1391 * if one gets posted. If an interrupt was not posted
1392 * to the bus, the test failed.
1393 */
1394 adapter->test_icr = 0;
1395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1396 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1397 msleep(10);
1398
1399 if (!(adapter->test_icr &mask)) {
1400 *data = 4;
1401 break;
1402 }
1403
1404 if (!shared_int) {
1405 /*
1406 * Disable the other interrupts to be reported in
1407 * the cause register and then force the other
1408 * interrupts and see if any get posted. If
1409 * an interrupt was posted to the bus, the
1410 * test failed.
1411 */
1412 adapter->test_icr = 0;
1413 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1414 ~mask & 0x00007FFF);
1415 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1416 ~mask & 0x00007FFF);
1417 msleep(10);
1418
1419 if (adapter->test_icr) {
1420 *data = 5;
1421 break;
1422 }
1423 }
1424 }
1425
1426 /* Disable all the interrupts */
1427 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1428 msleep(10);
1429
1430 /* Unhook test interrupt handler */
1431 free_irq(irq, netdev);
1432
1433 return *data;
1434}
1435
1436static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1437{
1438 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1439 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1440 struct ixgbe_hw *hw = &adapter->hw;
da4dd0f7 1441 u32 reg_ctl;
da4dd0f7
PWJ		 1442
1443 /* shut down the DMA engines now so they can be reinitialized later */
1444
1445 /* first Rx */
1446 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1447 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1448 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
84418e3b 1449 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rx_ring->reg_idx));
da4dd0f7 1450 reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
84418e3b 1451 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rx_ring->reg_idx), reg_ctl);
da4dd0f7
PWJ		 1452
1453 /* now Tx */
84418e3b 1454 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
da4dd0f7 1455 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
84418e3b
AD		 1456 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1457
da4dd0f7
PWJ		 1458 if (hw->mac.type == ixgbe_mac_82599EB) {
1459 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1460 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1461 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1462 }
1463
1464 ixgbe_reset(adapter);
1465
84418e3b
AD		 1466 ixgbe_free_tx_resources(adapter, &adapter->test_tx_ring);
1467 ixgbe_free_rx_resources(adapter, &adapter->test_rx_ring);
da4dd0f7
PWJ		 1468}
1469
1470static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1471{
1472 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1473 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
da4dd0f7 1474 u32 rctl, reg_data;
84418e3b
AD		 1475 int ret_val;
1476 int err;
da4dd0f7
PWJ		 1477
1478 /* Setup Tx descriptor ring and Tx buffers */
84418e3b
AD		 1479 tx_ring->count = IXGBE_DEFAULT_TXD;
1480 tx_ring->queue_index = 0;
1481 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1482 tx_ring->numa_node = adapter->node;
da4dd0f7 1483
84418e3b
AD		 1484 err = ixgbe_setup_tx_resources(adapter, tx_ring);
1485 if (err)
1486 return 1;
da4dd0f7
PWJ		 1487
1488 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1489 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1490 reg_data |= IXGBE_DMATXCTL_TE;
1491 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1492 }
f4ec443b 1493
84418e3b 1494 ixgbe_configure_tx_ring(adapter, tx_ring);
da4dd0f7
PWJ		 1495
1496 /* Setup Rx Descriptor ring and Rx buffers */
84418e3b
AD		 1497 rx_ring->count = IXGBE_DEFAULT_RXD;
1498 rx_ring->queue_index = 0;
1499 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1500 rx_ring->rx_buf_len = IXGBE_RXBUFFER_2048;
1501 rx_ring->numa_node = adapter->node;
1502
1503 err = ixgbe_setup_rx_resources(adapter, rx_ring);
1504 if (err) {
da4dd0f7
PWJ		 1505 ret_val = 4;
1506 goto err_nomem;
1507 }
1508
da4dd0f7
PWJ		 1509 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1510 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
da4dd0f7 1511
84418e3b 1512 ixgbe_configure_rx_ring(adapter, rx_ring);
da4dd0f7
PWJ		 1513
1514 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1516
da4dd0f7
PWJ		 1517 return 0;
1518
1519err_nomem:
1520 ixgbe_free_desc_rings(adapter);
1521 return ret_val;
1522}
1523
1524static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1525{
1526 struct ixgbe_hw *hw = &adapter->hw;
1527 u32 reg_data;
1528
1529 /* right now we only support MAC loopback in the driver */
da4dd0f7 1530 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
84418e3b 1531 /* Setup MAC loopback */
da4dd0f7
PWJ		 1532 reg_data |= IXGBE_HLREG0_LPBK;
1533 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1534
84418e3b
AD		 1535 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1536 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1537 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1538
da4dd0f7
PWJ		 1539 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1540 reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1541 reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1542 IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
84418e3b
AD		 1543 IXGBE_WRITE_FLUSH(&adapter->hw);
1544 msleep(10);
da4dd0f7
PWJ		 1545
1546 /* Disable Atlas Tx lanes; re-enabled in reset path */
1547 if (hw->mac.type == ixgbe_mac_82598EB) {
1548 u8 atlas;
1549
1550 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1551 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1552 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1553
1554 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1555 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1556 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1557
1558 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1559 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1560 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1561
1562 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1563 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1564 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1565 }
1566
1567 return 0;
1568}
1569
1570static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1571{
1572 u32 reg_data;
1573
1574 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1575 reg_data &= ~IXGBE_HLREG0_LPBK;
1576 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1577}
1578
1579static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1580 unsigned int frame_size)
1581{
1582 memset(skb->data, 0xFF, frame_size);
1583 frame_size &= ~1;
1584 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1585 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1586 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1587}
1588
1589static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1590 unsigned int frame_size)
1591{
1592 frame_size &= ~1;
1593 if (*(skb->data + 3) == 0xFF) {
1594 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1595 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1596 return 0;
1597 }
1598 }
1599 return 13;
1600}
1601
84418e3b
AD		 1602static u16 ixgbe_clean_test_rings(struct ixgbe_adapter *adapter,
1603 struct ixgbe_ring *rx_ring,
1604 struct ixgbe_ring *tx_ring,
1605 unsigned int size)
1606{
1607 union ixgbe_adv_rx_desc *rx_desc;
1608 struct ixgbe_rx_buffer *rx_buffer_info;
1609 struct ixgbe_tx_buffer *tx_buffer_info;
1610 const int bufsz = rx_ring->rx_buf_len;
1611 u32 staterr;
1612 u16 rx_ntc, tx_ntc, count = 0;
1613
1614 /* initialize next to clean and descriptor values */
1615 rx_ntc = rx_ring->next_to_clean;
1616 tx_ntc = tx_ring->next_to_clean;
1617 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1618 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1619
1620 while (staterr & IXGBE_RXD_STAT_DD) {
1621 /* check Rx buffer */
1622 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1623
1624 /* unmap Rx buffer, will be remapped by alloc_rx_buffers */
1625 dma_unmap_single(&adapter->pdev->dev,
1626 rx_buffer_info->dma,
1627 bufsz,
1628 DMA_FROM_DEVICE);
1629 rx_buffer_info->dma = 0;
1630
1631 /* verify contents of skb */
1632 if (!ixgbe_check_lbtest_frame(rx_buffer_info->skb, size))
1633 count++;
1634
1635 /* unmap buffer on Tx side */
1636 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1637 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
1638
1639 /* increment Rx/Tx next to clean counters */
1640 rx_ntc++;
1641 if (rx_ntc == rx_ring->count)
1642 rx_ntc = 0;
1643 tx_ntc++;
1644 if (tx_ntc == tx_ring->count)
1645 tx_ntc = 0;
1646
1647 /* fetch next descriptor */
1648 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1649 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1650 }
1651
1652 /* re-map buffers to ring, store next to clean values */
1653 ixgbe_alloc_rx_buffers(adapter, rx_ring, count);
1654 rx_ring->next_to_clean = rx_ntc;
1655 tx_ring->next_to_clean = tx_ntc;
1656
1657 return count;
1658}
1659
da4dd0f7
PWJ		 1660static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1661{
1662 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1663 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
84418e3b
AD		 1664 int i, j, lc, good_cnt, ret_val = 0;
1665 unsigned int size = 1024;
1666 netdev_tx_t tx_ret_val;
1667 struct sk_buff *skb;
1668
1669 /* allocate test skb */
1670 skb = alloc_skb(size, GFP_KERNEL);
1671 if (!skb)
1672 return 11;
da4dd0f7 1673
84418e3b
AD		 1674 /* place data into test skb */
1675 ixgbe_create_lbtest_frame(skb, size);
1676 skb_put(skb, size);
da4dd0f7
PWJ		 1677
1678 /*
1679 * Calculate the loop count based on the largest descriptor ring
1680 * The idea is to wrap the largest ring a number of times using 64
1681 * send/receive pairs during each loop
1682 */
1683
1684 if (rx_ring->count <= tx_ring->count)
1685 lc = ((tx_ring->count / 64) * 2) + 1;
1686 else
1687 lc = ((rx_ring->count / 64) * 2) + 1;
1688
da4dd0f7 1689 for (j = 0; j <= lc; j++) {
84418e3b 1690 /* reset count of good packets */
da4dd0f7 1691 good_cnt = 0;
84418e3b
AD		 1692
1693 /* place 64 packets on the transmit queue*/
1694 for (i = 0; i < 64; i++) {
1695 skb_get(skb);
1696 tx_ret_val = ixgbe_xmit_frame_ring(skb,
1697 adapter->netdev,
1698 adapter,
1699 tx_ring);
1700 if (tx_ret_val == NETDEV_TX_OK)
da4dd0f7 1701 good_cnt++;
84418e3b
AD		 1702 }
1703
da4dd0f7 1704 if (good_cnt != 64) {
84418e3b 1705 ret_val = 12;
da4dd0f7
PWJ		 1706 break;
1707 }
84418e3b
AD		 1708
1709 /* allow 200 milliseconds for packets to go from Tx to Rx */
1710 msleep(200);
1711
1712 good_cnt = ixgbe_clean_test_rings(adapter, rx_ring,
1713 tx_ring, size);
1714 if (good_cnt != 64) {
1715 ret_val = 13;
da4dd0f7
PWJ		 1716 break;
1717 }
1718 }
1719
84418e3b
AD		 1720 /* free the original skb */
1721 kfree_skb(skb);
1722
da4dd0f7
PWJ		 1723 return ret_val;
1724}
1725
1726static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1727{
1728 *data = ixgbe_setup_desc_rings(adapter);
1729 if (*data)
1730 goto out;
1731 *data = ixgbe_setup_loopback_test(adapter);
1732 if (*data)
1733 goto err_loopback;
1734 *data = ixgbe_run_loopback_test(adapter);
1735 ixgbe_loopback_cleanup(adapter);
1736
1737err_loopback:
1738 ixgbe_free_desc_rings(adapter);
1739out:
1740 return *data;
1741}
1742
1743static void ixgbe_diag_test(struct net_device *netdev,
1744 struct ethtool_test *eth_test, u64 *data)
1745{
1746 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1747 bool if_running = netif_running(netdev);
1748
1749 set_bit(__IXGBE_TESTING, &adapter->state);
1750 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1751 /* Offline tests */
1752
396e799c 1753 e_info(hw, "offline testing starting\n");
da4dd0f7
PWJ		 1754
1755 /* Link test performed before hardware reset so autoneg doesn't
1756 * interfere with test result */
1757 if (ixgbe_link_test(adapter, &data[4]))
1758 eth_test->flags |= ETH_TEST_FL_FAILED;
1759
e7d481a6
GR		 1760 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1761 int i;
1762 for (i = 0; i < adapter->num_vfs; i++) {
1763 if (adapter->vfinfo[i].clear_to_send) {
1764 netdev_warn(netdev, "%s",
1765 "offline diagnostic is not "
1766 "supported when VFs are "
1767 "present\n");
1768 data[0] = 1;
1769 data[1] = 1;
1770 data[2] = 1;
1771 data[3] = 1;
1772 eth_test->flags |= ETH_TEST_FL_FAILED;
1773 clear_bit(__IXGBE_TESTING,
1774 &adapter->state);
1775 goto skip_ol_tests;
1776 }
1777 }
1778 }
1779
da4dd0f7
PWJ		 1780 if (if_running)
1781 /* indicate we're in test mode */
1782 dev_close(netdev);
1783 else
1784 ixgbe_reset(adapter);
1785
396e799c 1786 e_info(hw, "register testing starting\n");
da4dd0f7
PWJ		 1787 if (ixgbe_reg_test(adapter, &data[0]))
1788 eth_test->flags |= ETH_TEST_FL_FAILED;
1789
1790 ixgbe_reset(adapter);
396e799c 1791 e_info(hw, "eeprom testing starting\n");
da4dd0f7
PWJ		 1792 if (ixgbe_eeprom_test(adapter, &data[1]))
1793 eth_test->flags |= ETH_TEST_FL_FAILED;
1794
1795 ixgbe_reset(adapter);
396e799c 1796 e_info(hw, "interrupt testing starting\n");
da4dd0f7
PWJ		 1797 if (ixgbe_intr_test(adapter, &data[2]))
1798 eth_test->flags |= ETH_TEST_FL_FAILED;
1799
bdbec4b8
GR		 1800 /* If SRIOV or VMDq is enabled then skip MAC
1801 * loopback diagnostic. */
1802 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1803 IXGBE_FLAG_VMDQ_ENABLED)) {
396e799c
ET		 1804 e_info(hw, "Skip MAC loopback diagnostic in VT "
1805 "mode\n");
bdbec4b8
GR		 1806 data[3] = 0;
1807 goto skip_loopback;
1808 }
1809
da4dd0f7 1810 ixgbe_reset(adapter);
396e799c 1811 e_info(hw, "loopback testing starting\n");
da4dd0f7
PWJ		 1812 if (ixgbe_loopback_test(adapter, &data[3]))
1813 eth_test->flags |= ETH_TEST_FL_FAILED;
1814
bdbec4b8 1815skip_loopback:
da4dd0f7
PWJ		 1816 ixgbe_reset(adapter);
1817
1818 clear_bit(__IXGBE_TESTING, &adapter->state);
1819 if (if_running)
1820 dev_open(netdev);
1821 } else {
396e799c 1822 e_info(hw, "online testing starting\n");
da4dd0f7
PWJ		 1823 /* Online tests */
1824 if (ixgbe_link_test(adapter, &data[4]))
1825 eth_test->flags |= ETH_TEST_FL_FAILED;
1826
1827 /* Online tests aren't run; pass by default */
1828 data[0] = 0;
1829 data[1] = 0;
1830 data[2] = 0;
1831 data[3] = 0;
1832
1833 clear_bit(__IXGBE_TESTING, &adapter->state);
1834 }
e7d481a6 1835skip_ol_tests:
da4dd0f7
PWJ		 1836 msleep_interruptible(4 * 1000);
1837}
9a799d71 1838
d6c519e1
AD		 1839static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1840 struct ethtool_wolinfo *wol)
1841{
1842 struct ixgbe_hw *hw = &adapter->hw;
1843 int retval = 1;
1844
1845 switch(hw->device_id) {
1846 case IXGBE_DEV_ID_82599_KX4:
1847 retval = 0;
1848 break;
1849 default:
1850 wol->supported = 0;
d6c519e1
AD		 1851 }
1852
1853 return retval;
1854}
1855
9a799d71 1856static void ixgbe_get_wol(struct net_device *netdev,
b4617240 1857 struct ethtool_wolinfo *wol)
9a799d71 1858{
e63d9762
PW		 1859 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1860
1861 wol->supported = WAKE_UCAST | WAKE_MCAST |
1862 WAKE_BCAST | WAKE_MAGIC;
9a799d71
AK		 1863 wol->wolopts = 0;
1864
d6c519e1
AD		 1865 if (ixgbe_wol_exclusion(adapter, wol) ||
1866 !device_can_wakeup(&adapter->pdev->dev))
e63d9762
PW		 1867 return;
1868
1869 if (adapter->wol & IXGBE_WUFC_EX)
1870 wol->wolopts |= WAKE_UCAST;
1871 if (adapter->wol & IXGBE_WUFC_MC)
1872 wol->wolopts |= WAKE_MCAST;
1873 if (adapter->wol & IXGBE_WUFC_BC)
1874 wol->wolopts |= WAKE_BCAST;
1875 if (adapter->wol & IXGBE_WUFC_MAG)
1876 wol->wolopts |= WAKE_MAGIC;
9a799d71
AK		 1877}
1878
e63d9762
PW		 1879static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1880{
1881 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1882
1883 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1884 return -EOPNOTSUPP;
1885
d6c519e1
AD		 1886 if (ixgbe_wol_exclusion(adapter, wol))
1887 return wol->wolopts ? -EOPNOTSUPP : 0;
1888
e63d9762
PW		 1889 adapter->wol = 0;
1890
1891 if (wol->wolopts & WAKE_UCAST)
1892 adapter->wol |= IXGBE_WUFC_EX;
1893 if (wol->wolopts & WAKE_MCAST)
1894 adapter->wol |= IXGBE_WUFC_MC;
1895 if (wol->wolopts & WAKE_BCAST)
1896 adapter->wol |= IXGBE_WUFC_BC;
1897 if (wol->wolopts & WAKE_MAGIC)
1898 adapter->wol |= IXGBE_WUFC_MAG;
1899
1900 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1901
1902 return 0;
1903}
1904
9a799d71
AK		 1905static int ixgbe_nway_reset(struct net_device *netdev)
1906{
1907 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1908
d4f80882
AV		 1909 if (netif_running(netdev))
1910 ixgbe_reinit_locked(adapter);
9a799d71
AK		 1911
1912 return 0;
1913}
1914
1915static int ixgbe_phys_id(struct net_device *netdev, u32 data)
1916{
1917 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e
JB		 1918 struct ixgbe_hw *hw = &adapter->hw;
1919 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
9a799d71
AK		 1920 u32 i;
1921
1922 if (!data || data > 300)
1923 data = 300;
1924
1925 for (i = 0; i < (data * 1000); i += 400) {
c44ade9e 1926 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
9a799d71 1927 msleep_interruptible(200);
c44ade9e 1928 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
9a799d71
AK		 1929 msleep_interruptible(200);
1930 }
1931
1932 /* Restore LED settings */
1933 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
1934
1935 return 0;
1936}
1937
1938static int ixgbe_get_coalesce(struct net_device *netdev,
b4617240 1939 struct ethtool_coalesce *ec)
9a799d71
AK		 1940{
1941 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1942
4a0b9ca0 1943 ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0]->work_limit;
30efa5a3
JB		 1944
1945 /* only valid if in constant ITR mode */
f7554a2b 1946 switch (adapter->rx_itr_setting) {
30efa5a3
JB		 1947 case 0:
1948 /* throttling disabled */
1949 ec->rx_coalesce_usecs = 0;
1950 break;
1951 case 1:
1952 /* dynamic ITR mode */
1953 ec->rx_coalesce_usecs = 1;
1954 break;
1955 default:
1956 /* fixed interrupt rate mode */
f7554a2b 1957 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
30efa5a3
JB		 1958 break;
1959 }
f7554a2b 1960
cfb3f91a
SN		 1961 /* if in mixed tx/rx queues per vector mode, report only rx settings */
1962 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count)
1963 return 0;
1964
f7554a2b
NS		 1965 /* only valid if in constant ITR mode */
1966 switch (adapter->tx_itr_setting) {
1967 case 0:
1968 /* throttling disabled */
1969 ec->tx_coalesce_usecs = 0;
1970 break;
1971 case 1:
1972 /* dynamic ITR mode */
1973 ec->tx_coalesce_usecs = 1;
1974 break;
1975 default:
1976 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
1977 break;
1978 }
1979
9a799d71
AK		 1980 return 0;
1981}
1982
1983static int ixgbe_set_coalesce(struct net_device *netdev,
b4617240 1984 struct ethtool_coalesce *ec)
9a799d71
AK		 1985{
1986 struct ixgbe_adapter *adapter = netdev_priv(netdev);
237057ad 1987 struct ixgbe_q_vector *q_vector;
30efa5a3 1988 int i;
ef021194 1989 bool need_reset = false;
9a799d71 1990
cfb3f91a
SN		 1991 /* don't accept tx specific changes if we've got mixed RxTx vectors */
1992 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count
1993 && ec->tx_coalesce_usecs)
f7554a2b
NS		 1994 return -EINVAL;
1995
9a799d71 1996 if (ec->tx_max_coalesced_frames_irq)
4a0b9ca0 1997 adapter->tx_ring[0]->work_limit = ec->tx_max_coalesced_frames_irq;
30efa5a3
JB		 1998
1999 if (ec->rx_coalesce_usecs > 1) {
f8d1dcaf
JB		 2000 u32 max_int;
2001 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2002 max_int = IXGBE_MAX_RSC_INT_RATE;
2003 else
2004 max_int = IXGBE_MAX_INT_RATE;
2005
509ee935 2006 /* check the limits */
f8d1dcaf 2007 if ((1000000/ec->rx_coalesce_usecs > max_int) ||
509ee935
JB		 2008 (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2009 return -EINVAL;
2010
30efa5a3 2011 /* store the value in ints/second */
f7554a2b 2012 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
30efa5a3
JB		 2013
2014 /* static value of interrupt rate */
f7554a2b 2015 adapter->rx_itr_setting = adapter->rx_eitr_param;
509ee935 2016 /* clear the lower bit as its used for dynamic state */
f7554a2b 2017 adapter->rx_itr_setting &= ~1;
30efa5a3
JB		 2018 } else if (ec->rx_coalesce_usecs == 1) {
2019 /* 1 means dynamic mode */
f7554a2b
NS		 2020 adapter->rx_eitr_param = 20000;
2021 adapter->rx_itr_setting = 1;
30efa5a3 2022 } else {
509ee935
JB		 2023 /*
2024 * any other value means disable eitr, which is best
2025 * served by setting the interrupt rate very high
2026 */
f8d1dcaf 2027 adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
f7554a2b 2028 adapter->rx_itr_setting = 0;
f8d1dcaf
JB		 2029
2030 /*
2031 * if hardware RSC is enabled, disable it when
2032 * setting low latency mode, to avoid errata, assuming
2033 * that when the user set low latency mode they want
2034 * it at the cost of anything else
2035 */
2036 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2037 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
28c8e479
AG		 2038 if (netdev->features & NETIF_F_LRO) {
2039 netdev->features &= ~NETIF_F_LRO;
396e799c
ET		 2040 e_info(probe, "rx-usecs set to 0, "
2041 "disabling RSC\n");
28c8e479 2042 }
ef021194 2043 need_reset = true;
f8d1dcaf 2044 }
f7554a2b
NS		 2045 }
2046
2047 if (ec->tx_coalesce_usecs > 1) {
f8d1dcaf
JB		 2048 /*
2049 * don't have to worry about max_int as above because
2050 * tx vectors don't do hardware RSC (an rx function)
2051 */
f7554a2b
NS		 2052 /* check the limits */
2053 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2054 (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2055 return -EINVAL;
2056
2057 /* store the value in ints/second */
2058 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2059
2060 /* static value of interrupt rate */
2061 adapter->tx_itr_setting = adapter->tx_eitr_param;
2062
2063 /* clear the lower bit as its used for dynamic state */
2064 adapter->tx_itr_setting &= ~1;
2065 } else if (ec->tx_coalesce_usecs == 1) {
2066 /* 1 means dynamic mode */
2067 adapter->tx_eitr_param = 10000;
2068 adapter->tx_itr_setting = 1;
2069 } else {
2070 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2071 adapter->tx_itr_setting = 0;
30efa5a3 2072 }
9a799d71 2073
237057ad
DS		 2074 /* MSI/MSIx Interrupt Mode */
2075 if (adapter->flags &
2076 (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2077 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2078 for (i = 0; i < num_vectors; i++) {
2079 q_vector = adapter->q_vector[i];
2080 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 2081 /* tx only */
2082 q_vector->eitr = adapter->tx_eitr_param;
237057ad
DS		 2083 else
2084 /* rx only or mixed */
f7554a2b 2085 q_vector->eitr = adapter->rx_eitr_param;
237057ad
DS		 2086 ixgbe_write_eitr(q_vector);
2087 }
2088 /* Legacy Interrupt Mode */
2089 } else {
2090 q_vector = adapter->q_vector[0];
f7554a2b 2091 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 2092 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2093 }
2094
ef021194
JB		 2095 /*
2096 * do reset here at the end to make sure EITR==0 case is handled
2097 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2098 * also locks in RSC enable/disable which requires reset
2099 */
2100 if (need_reset) {
2101 if (netif_running(netdev))
2102 ixgbe_reinit_locked(adapter);
2103 else
2104 ixgbe_reset(adapter);
2105 }
2106
9a799d71
AK		 2107 return 0;
2108}
2109
f8212f97
AD		 2110static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2111{
2112 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a713e7c 2113 bool need_reset = false;
1437ce39 2114 int rc;
f8212f97 2115
1437ce39
BH		 2116 rc = ethtool_op_set_flags(netdev, data, ETH_FLAG_LRO | ETH_FLAG_NTUPLE);
2117 if (rc)
2118 return rc;
f8212f97 2119
f8212f97 2120 /* if state changes we need to update adapter->flags and reset */
f8d1dcaf
JB		 2121 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) {
2122 /*
2123 * cast both to bool and verify if they are set the same
2124 * but only enable RSC if itr is non-zero, as
2125 * itr=0 and RSC are mutually exclusive
2126 */
2127 if (((!!(data & ETH_FLAG_LRO)) !=
2128 (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) &&
2129 adapter->rx_itr_setting) {
2130 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2131 switch (adapter->hw.mac.type) {
2132 case ixgbe_mac_82599EB:
2133 need_reset = true;
2134 break;
2135 default:
2136 break;
2137 }
2138 } else if (!adapter->rx_itr_setting) {
0a17d8c7 2139 netdev->features &= ~NETIF_F_LRO;
28c8e479 2140 if (data & ETH_FLAG_LRO)
396e799c
ET		 2141 e_info(probe, "rx-usecs set to 0, "
2142 "LRO/RSC cannot be enabled.\n");
f8d1dcaf 2143 }
9a713e7c
PW		 2144 }
2145
2146 /*
2147 * Check if Flow Director n-tuple support was enabled or disabled. If
2148 * the state changed, we need to reset.
2149 */
2150 if ((adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) &&
2151 (!(data & ETH_FLAG_NTUPLE))) {
2152 /* turn off Flow Director perfect, set hash and reset */
2153 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2154 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
2155 need_reset = true;
2156 } else if ((!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) &&
2157 (data & ETH_FLAG_NTUPLE)) {
2158 /* turn off Flow Director hash, enable perfect and reset */
2159 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
2160 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2161 need_reset = true;
2162 } else {
2163 /* no state change */
2164 }
2165
2166 if (need_reset) {
f8212f97
AD		 2167 if (netif_running(netdev))
2168 ixgbe_reinit_locked(adapter);
2169 else
2170 ixgbe_reset(adapter);
2171 }
9a713e7c 2172
f8212f97 2173 return 0;
9a713e7c
PW		 2174}
2175
2176static int ixgbe_set_rx_ntuple(struct net_device *dev,
2177 struct ethtool_rx_ntuple *cmd)
2178{
2179 struct ixgbe_adapter *adapter = netdev_priv(dev);
2180 struct ethtool_rx_ntuple_flow_spec fs = cmd->fs;
2181 struct ixgbe_atr_input input_struct;
2182 struct ixgbe_atr_input_masks input_masks;
2183 int target_queue;
2184
2185 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2186 return -EOPNOTSUPP;
2187
2188 /*
2189 * Don't allow programming if the action is a queue greater than
2190 * the number of online Tx queues.
2191 */
2192 if ((fs.action >= adapter->num_tx_queues) ||
2193 (fs.action < ETHTOOL_RXNTUPLE_ACTION_DROP))
2194 return -EINVAL;
2195
2196 memset(&input_struct, 0, sizeof(struct ixgbe_atr_input));
2197 memset(&input_masks, 0, sizeof(struct ixgbe_atr_input_masks));
2198
2199 input_masks.src_ip_mask = fs.m_u.tcp_ip4_spec.ip4src;
2200 input_masks.dst_ip_mask = fs.m_u.tcp_ip4_spec.ip4dst;
2201 input_masks.src_port_mask = fs.m_u.tcp_ip4_spec.psrc;
2202 input_masks.dst_port_mask = fs.m_u.tcp_ip4_spec.pdst;
2203 input_masks.vlan_id_mask = fs.vlan_tag_mask;
2204 /* only use the lowest 2 bytes for flex bytes */
2205 input_masks.data_mask = (fs.data_mask & 0xffff);
2206
2207 switch (fs.flow_type) {
2208 case TCP_V4_FLOW:
2209 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_TCP);
2210 break;
2211 case UDP_V4_FLOW:
2212 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_UDP);
2213 break;
2214 case SCTP_V4_FLOW:
2215 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_SCTP);
2216 break;
2217 default:
2218 return -1;
2219 }
f8212f97 2220
9a713e7c
PW		 2221 /* Mask bits from the inputs based on user-supplied mask */
2222 ixgbe_atr_set_src_ipv4_82599(&input_struct,
2223 (fs.h_u.tcp_ip4_spec.ip4src & ~fs.m_u.tcp_ip4_spec.ip4src));
2224 ixgbe_atr_set_dst_ipv4_82599(&input_struct,
2225 (fs.h_u.tcp_ip4_spec.ip4dst & ~fs.m_u.tcp_ip4_spec.ip4dst));
2226 /* 82599 expects these to be byte-swapped for perfect filtering */
2227 ixgbe_atr_set_src_port_82599(&input_struct,
2228 ((ntohs(fs.h_u.tcp_ip4_spec.psrc)) & ~fs.m_u.tcp_ip4_spec.psrc));
2229 ixgbe_atr_set_dst_port_82599(&input_struct,
2230 ((ntohs(fs.h_u.tcp_ip4_spec.pdst)) & ~fs.m_u.tcp_ip4_spec.pdst));
2231
2232 /* VLAN and Flex bytes are either completely masked or not */
2233 if (!fs.vlan_tag_mask)
2234 ixgbe_atr_set_vlan_id_82599(&input_struct, fs.vlan_tag);
2235
2236 if (!input_masks.data_mask)
2237 /* make sure we only use the first 2 bytes of user data */
2238 ixgbe_atr_set_flex_byte_82599(&input_struct,
2239 (fs.data & 0xffff));
2240
2241 /* determine if we need to drop or route the packet */
2242 if (fs.action == ETHTOOL_RXNTUPLE_ACTION_DROP)
2243 target_queue = MAX_RX_QUEUES - 1;
2244 else
2245 target_queue = fs.action;
2246
2247 spin_lock(&adapter->fdir_perfect_lock);
2248 ixgbe_fdir_add_perfect_filter_82599(&adapter->hw, &input_struct,
2249 &input_masks, 0, target_queue);
2250 spin_unlock(&adapter->fdir_perfect_lock);
2251
2252 return 0;
f8212f97 2253}
9a799d71 2254
b9804972 2255static const struct ethtool_ops ixgbe_ethtool_ops = {
9a799d71
AK		 2256 .get_settings = ixgbe_get_settings,
2257 .set_settings = ixgbe_set_settings,
2258 .get_drvinfo = ixgbe_get_drvinfo,
2259 .get_regs_len = ixgbe_get_regs_len,
2260 .get_regs = ixgbe_get_regs,
2261 .get_wol = ixgbe_get_wol,
e63d9762 2262 .set_wol = ixgbe_set_wol,
9a799d71
AK		 2263 .nway_reset = ixgbe_nway_reset,
2264 .get_link = ethtool_op_get_link,
2265 .get_eeprom_len = ixgbe_get_eeprom_len,
2266 .get_eeprom = ixgbe_get_eeprom,
2267 .get_ringparam = ixgbe_get_ringparam,
2268 .set_ringparam = ixgbe_set_ringparam,
2269 .get_pauseparam = ixgbe_get_pauseparam,
2270 .set_pauseparam = ixgbe_set_pauseparam,
2271 .get_rx_csum = ixgbe_get_rx_csum,
2272 .set_rx_csum = ixgbe_set_rx_csum,
2273 .get_tx_csum = ixgbe_get_tx_csum,
2274 .set_tx_csum = ixgbe_set_tx_csum,
2275 .get_sg = ethtool_op_get_sg,
2276 .set_sg = ethtool_op_set_sg,
2277 .get_msglevel = ixgbe_get_msglevel,
2278 .set_msglevel = ixgbe_set_msglevel,
2279 .get_tso = ethtool_op_get_tso,
2280 .set_tso = ixgbe_set_tso,
da4dd0f7 2281 .self_test = ixgbe_diag_test,
9a799d71
AK		 2282 .get_strings = ixgbe_get_strings,
2283 .phys_id = ixgbe_phys_id,
b4617240 2284 .get_sset_count = ixgbe_get_sset_count,
9a799d71
AK		 2285 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2286 .get_coalesce = ixgbe_get_coalesce,
2287 .set_coalesce = ixgbe_set_coalesce,
177db6ff 2288 .get_flags = ethtool_op_get_flags,
f8212f97 2289 .set_flags = ixgbe_set_flags,
9a713e7c 2290 .set_rx_ntuple = ixgbe_set_rx_ntuple,
9a799d71
AK		 2291};
2292
2293void ixgbe_set_ethtool_ops(struct net_device *netdev)
2294{
2295 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2296}
Clone of davem's net-next-2.6 tree