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ixgbe: Fix 82599 adapter link flickering issues
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_ethtool.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for ixgbe */
29
30#include <linux/types.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/ethtool.h>
35#include <linux/vmalloc.h>
36#include <linux/uaccess.h>
37
38#include "ixgbe.h"
39
40
41#define IXGBE_ALL_RAR_ENTRIES 16
42
43struct ixgbe_stats {
44 char stat_string[ETH_GSTRING_LEN];
45 int sizeof_stat;
46 int stat_offset;
47};
48
49#define IXGBE_STAT(m) sizeof(((struct ixgbe_adapter *)0)->m), \
b4617240 50 offsetof(struct ixgbe_adapter, m)
9a799d71
AK		 51static struct ixgbe_stats ixgbe_gstrings_stats[] = {
52 {"rx_packets", IXGBE_STAT(net_stats.rx_packets)},
53 {"tx_packets", IXGBE_STAT(net_stats.tx_packets)},
54 {"rx_bytes", IXGBE_STAT(net_stats.rx_bytes)},
55 {"tx_bytes", IXGBE_STAT(net_stats.tx_bytes)},
56 {"lsc_int", IXGBE_STAT(lsc_int)},
57 {"tx_busy", IXGBE_STAT(tx_busy)},
58 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
59 {"rx_errors", IXGBE_STAT(net_stats.rx_errors)},
60 {"tx_errors", IXGBE_STAT(net_stats.tx_errors)},
61 {"rx_dropped", IXGBE_STAT(net_stats.rx_dropped)},
62 {"tx_dropped", IXGBE_STAT(net_stats.tx_dropped)},
63 {"multicast", IXGBE_STAT(net_stats.multicast)},
64 {"broadcast", IXGBE_STAT(stats.bprc)},
65 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
66 {"collisions", IXGBE_STAT(net_stats.collisions)},
67 {"rx_over_errors", IXGBE_STAT(net_stats.rx_over_errors)},
68 {"rx_crc_errors", IXGBE_STAT(net_stats.rx_crc_errors)},
69 {"rx_frame_errors", IXGBE_STAT(net_stats.rx_frame_errors)},
f8212f97 70 {"hw_rsc_count", IXGBE_STAT(rsc_count)},
9a799d71
AK		 71 {"rx_fifo_errors", IXGBE_STAT(net_stats.rx_fifo_errors)},
72 {"rx_missed_errors", IXGBE_STAT(net_stats.rx_missed_errors)},
73 {"tx_aborted_errors", IXGBE_STAT(net_stats.tx_aborted_errors)},
74 {"tx_carrier_errors", IXGBE_STAT(net_stats.tx_carrier_errors)},
75 {"tx_fifo_errors", IXGBE_STAT(net_stats.tx_fifo_errors)},
76 {"tx_heartbeat_errors", IXGBE_STAT(net_stats.tx_heartbeat_errors)},
77 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
78 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
79 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
80 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
81 {"tx_tcp4_seg_ctxt", IXGBE_STAT(hw_tso_ctxt)},
82 {"tx_tcp6_seg_ctxt", IXGBE_STAT(hw_tso6_ctxt)},
83 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
84 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
85 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
86 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
87 {"rx_csum_offload_good", IXGBE_STAT(hw_csum_rx_good)},
88 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
89 {"tx_csum_offload_ctxt", IXGBE_STAT(hw_csum_tx_good)},
90 {"rx_header_split", IXGBE_STAT(rx_hdr_split)},
91 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
92 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
e8e26350 93 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
6d45522c
YZ		 94#ifdef IXGBE_FCOE
95 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
96 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
97 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
98 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
99 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
100 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
101#endif /* IXGBE_FCOE */
9a799d71
AK		 102};
103
104#define IXGBE_QUEUE_STATS_LEN \
454d7c9b
WC		 105 ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
106 ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
107 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
b4617240 108#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
2f90b865 109#define IXGBE_PB_STATS_LEN ( \
9d2f4720 110 (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
2f90b865
AD		 111 IXGBE_FLAG_DCB_ENABLED) ? \
112 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
113 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
114 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
115 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
116 / sizeof(u64) : 0)
117#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
118 IXGBE_PB_STATS_LEN + \
119 IXGBE_QUEUE_STATS_LEN)
9a799d71 120
da4dd0f7
PWJ		 121static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
122 "Register test (offline)", "Eeprom test (offline)",
123 "Interrupt test (offline)", "Loopback test (offline)",
124 "Link test (on/offline)"
125};
126#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
127
9a799d71 128static int ixgbe_get_settings(struct net_device *netdev,
b4617240 129 struct ethtool_cmd *ecmd)
9a799d71
AK		 130{
131 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb
AV		 132 struct ixgbe_hw *hw = &adapter->hw;
133 u32 link_speed = 0;
134 bool link_up;
9a799d71 135
735441fb
AV		 136 ecmd->supported = SUPPORTED_10000baseT_Full;
137 ecmd->autoneg = AUTONEG_ENABLE;
9a799d71 138 ecmd->transceiver = XCVR_EXTERNAL;
735441fb
AV		 139 if (hw->phy.media_type == ixgbe_media_type_copper) {
140 ecmd->supported |= (SUPPORTED_1000baseT_Full |
b4617240 141 SUPPORTED_TP | SUPPORTED_Autoneg);
735441fb
AV		 142
143 ecmd->advertising = (ADVERTISED_TP | ADVERTISED_Autoneg);
144 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
145 ecmd->advertising |= ADVERTISED_10000baseT_Full;
146 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
147 ecmd->advertising |= ADVERTISED_1000baseT_Full;
7c5b8323
DS		 148 /*
149 * It's possible that phy.autoneg_advertised may not be
150 * set yet. If so display what the default would be -
151 * both 1G and 10G supported.
152 */
153 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
154 ADVERTISED_10000baseT_Full)))
155 ecmd->advertising |= (ADVERTISED_10000baseT_Full |
156 ADVERTISED_1000baseT_Full);
735441fb
AV		 157
158 ecmd->port = PORT_TP;
1e336d0f
DS		 159 } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
160 /* Set as FIBRE until SERDES defined in kernel */
161 switch (hw->device_id) {
162 case IXGBE_DEV_ID_82598:
163 ecmd->supported |= (SUPPORTED_1000baseT_Full |
164 SUPPORTED_FIBRE);
165 ecmd->advertising = (ADVERTISED_10000baseT_Full |
166 ADVERTISED_1000baseT_Full |
167 ADVERTISED_FIBRE);
168 ecmd->port = PORT_FIBRE;
169 break;
2f21bdd3
DS		 170 case IXGBE_DEV_ID_82598_BX:
171 ecmd->supported = (SUPPORTED_1000baseT_Full |
172 SUPPORTED_FIBRE);
173 ecmd->advertising = (ADVERTISED_1000baseT_Full |
174 ADVERTISED_FIBRE);
175 ecmd->port = PORT_FIBRE;
176 ecmd->autoneg = AUTONEG_DISABLE;
177 break;
1e336d0f 178 }
735441fb
AV		 179 } else {
180 ecmd->supported |= SUPPORTED_FIBRE;
181 ecmd->advertising = (ADVERTISED_10000baseT_Full |
b4617240 182 ADVERTISED_FIBRE);
735441fb 183 ecmd->port = PORT_FIBRE;
c44ade9e 184 ecmd->autoneg = AUTONEG_DISABLE;
735441fb 185 }
9a799d71 186
c44ade9e 187 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
735441fb
AV		 188 if (link_up) {
189 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
b4617240 190 SPEED_10000 : SPEED_1000;
9a799d71
AK		 191 ecmd->duplex = DUPLEX_FULL;
192 } else {
193 ecmd->speed = -1;
194 ecmd->duplex = -1;
195 }
196
9a799d71
AK		 197 return 0;
198}
199
200static int ixgbe_set_settings(struct net_device *netdev,
b4617240 201 struct ethtool_cmd *ecmd)
9a799d71
AK		 202{
203 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 204 struct ixgbe_hw *hw = &adapter->hw;
0befdb3e
JB		 205 u32 advertised, old;
206 s32 err;
9a799d71 207
735441fb
AV		 208 switch (hw->phy.media_type) {
209 case ixgbe_media_type_fiber:
210 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
211 (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
212 return -EINVAL;
213 /* in this case we currently only support 10Gb/FULL */
214 break;
0befdb3e
JB		 215 case ixgbe_media_type_copper:
216 /* 10000/copper and 1000/copper must autoneg
217 * this function does not support any duplex forcing, but can
218 * limit the advertising of the adapter to only 10000 or 1000 */
219 if (ecmd->autoneg == AUTONEG_DISABLE)
220 return -EINVAL;
221
222 old = hw->phy.autoneg_advertised;
223 advertised = 0;
224 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
225 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
226
227 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
228 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
229
230 if (old == advertised)
231 break;
232 /* this sets the link speed and restarts auto-neg */
233 err = hw->mac.ops.setup_link_speed(hw, advertised, true, true);
234 if (err) {
235 DPRINTK(PROBE, INFO,
236 "setup link failed with code %d\n", err);
237 hw->mac.ops.setup_link_speed(hw, old, true, true);
238 }
239 break;
735441fb
AV		 240 default:
241 break;
9a799d71
AK		 242 }
243
244 return 0;
245}
246
247static void ixgbe_get_pauseparam(struct net_device *netdev,
b4617240 248 struct ethtool_pauseparam *pause)
9a799d71
AK		 249{
250 struct ixgbe_adapter *adapter = netdev_priv(netdev);
251 struct ixgbe_hw *hw = &adapter->hw;
252
71fd570b
DS		 253 /*
254 * Flow Control Autoneg isn't on if
255 * - we didn't ask for it OR
256 * - it failed, we know this by tx & rx being off
257 */
258 if (hw->fc.disable_fc_autoneg ||
259 (hw->fc.current_mode == ixgbe_fc_none))
260 pause->autoneg = 0;
261 else
262 pause->autoneg = 1;
9a799d71 263
8756924c
PWJ		 264#ifdef CONFIG_DCB
265 if (hw->fc.current_mode == ixgbe_fc_pfc) {
266 pause->rx_pause = 0;
267 pause->tx_pause = 0;
268 }
269
270#endif
0ecc061d 271 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
9a799d71 272 pause->rx_pause = 1;
0ecc061d 273 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
9a799d71 274 pause->tx_pause = 1;
0ecc061d 275 } else if (hw->fc.current_mode == ixgbe_fc_full) {
9a799d71
AK		 276 pause->rx_pause = 1;
277 pause->tx_pause = 1;
278 }
279}
280
281static int ixgbe_set_pauseparam(struct net_device *netdev,
b4617240 282 struct ethtool_pauseparam *pause)
9a799d71
AK		 283{
284 struct ixgbe_adapter *adapter = netdev_priv(netdev);
285 struct ixgbe_hw *hw = &adapter->hw;
620fa036 286 struct ixgbe_fc_info fc;
9a799d71 287
264857b8
PWJ		 288#ifdef CONFIG_DCB
289 if (adapter->dcb_cfg.pfc_mode_enable ||
290 ((hw->mac.type == ixgbe_mac_82598EB) &&
291 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
292 return -EINVAL;
293
294#endif
620fa036
MC		 295
296 fc = hw->fc;
297
71fd570b 298 if (pause->autoneg != AUTONEG_ENABLE)
620fa036 299 fc.disable_fc_autoneg = true;
71fd570b 300 else
620fa036 301 fc.disable_fc_autoneg = false;
71fd570b
DS		 302
303 if (pause->rx_pause && pause->tx_pause)
620fa036 304 fc.requested_mode = ixgbe_fc_full;
9a799d71 305 else if (pause->rx_pause && !pause->tx_pause)
620fa036 306 fc.requested_mode = ixgbe_fc_rx_pause;
9a799d71 307 else if (!pause->rx_pause && pause->tx_pause)
620fa036 308 fc.requested_mode = ixgbe_fc_tx_pause;
9a799d71 309 else if (!pause->rx_pause && !pause->tx_pause)
620fa036 310 fc.requested_mode = ixgbe_fc_none;
9c83b070
AV		 311 else
312 return -EINVAL;
9a799d71 313
264857b8 314#ifdef CONFIG_DCB
620fa036 315 adapter->last_lfc_mode = fc.requested_mode;
264857b8 316#endif
620fa036
MC		 317
318 /* if the thing changed then we'll update and use new autoneg */
319 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
320 hw->fc = fc;
321 if (netif_running(netdev))
322 ixgbe_reinit_locked(adapter);
323 else
324 ixgbe_reset(adapter);
325 }
9a799d71
AK		 326
327 return 0;
328}
329
330static u32 ixgbe_get_rx_csum(struct net_device *netdev)
331{
332 struct ixgbe_adapter *adapter = netdev_priv(netdev);
333 return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
334}
335
336static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
337{
338 struct ixgbe_adapter *adapter = netdev_priv(netdev);
339 if (data)
340 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
341 else
342 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
343
d4f80882
AV		 344 if (netif_running(netdev))
345 ixgbe_reinit_locked(adapter);
346 else
9a799d71 347 ixgbe_reset(adapter);
9a799d71
AK		 348
349 return 0;
350}
351
352static u32 ixgbe_get_tx_csum(struct net_device *netdev)
353{
22f32b7a 354 return (netdev->features & NETIF_F_IP_CSUM) != 0;
9a799d71
AK		 355}
356
357static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
358{
45a5ead0
JB		 359 struct ixgbe_adapter *adapter = netdev_priv(netdev);
360
361 if (data) {
22f32b7a 362 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
45a5ead0
JB		 363 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
364 netdev->features |= NETIF_F_SCTP_CSUM;
365 } else {
3d3d6d3c 366 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
45a5ead0
JB		 367 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
368 netdev->features &= ~NETIF_F_SCTP_CSUM;
369 }
9a799d71
AK		 370
371 return 0;
372}
373
374static int ixgbe_set_tso(struct net_device *netdev, u32 data)
375{
9a799d71
AK		 376 if (data) {
377 netdev->features |= NETIF_F_TSO;
378 netdev->features |= NETIF_F_TSO6;
379 } else {
fd2ea0a7 380 netif_tx_stop_all_queues(netdev);
9a799d71
AK		 381 netdev->features &= ~NETIF_F_TSO;
382 netdev->features &= ~NETIF_F_TSO6;
fd2ea0a7 383 netif_tx_start_all_queues(netdev);
9a799d71
AK		 384 }
385 return 0;
386}
387
388static u32 ixgbe_get_msglevel(struct net_device *netdev)
389{
390 struct ixgbe_adapter *adapter = netdev_priv(netdev);
391 return adapter->msg_enable;
392}
393
394static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
395{
396 struct ixgbe_adapter *adapter = netdev_priv(netdev);
397 adapter->msg_enable = data;
398}
399
400static int ixgbe_get_regs_len(struct net_device *netdev)
401{
402#define IXGBE_REGS_LEN 1128
403 return IXGBE_REGS_LEN * sizeof(u32);
404}
405
406#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
407
408static void ixgbe_get_regs(struct net_device *netdev,
b4617240 409 struct ethtool_regs *regs, void *p)
9a799d71
AK		 410{
411 struct ixgbe_adapter *adapter = netdev_priv(netdev);
412 struct ixgbe_hw *hw = &adapter->hw;
413 u32 *regs_buff = p;
414 u8 i;
415
416 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
417
418 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
419
420 /* General Registers */
421 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
422 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
423 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
424 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
425 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
426 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
427 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
428 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
429
430 /* NVM Register */
431 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
432 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
433 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
434 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
435 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
436 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
437 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
438 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
439 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
440 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
441
442 /* Interrupt */
98c00a1c
JB		 443 /* don't read EICR because it can clear interrupt causes, instead
444 * read EICS which is a shadow but doesn't clear EICR */
445 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
9a799d71
AK		 446 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
447 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
448 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
449 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
450 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
451 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
452 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
453 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
454 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
c44ade9e 455 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
9a799d71
AK		 456 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
457
458 /* Flow Control */
459 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
460 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
461 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
462 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
463 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
464 for (i = 0; i < 8; i++)
465 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
466 for (i = 0; i < 8; i++)
467 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
468 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
469 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
470
471 /* Receive DMA */
472 for (i = 0; i < 64; i++)
473 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
474 for (i = 0; i < 64; i++)
475 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
476 for (i = 0; i < 64; i++)
477 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
478 for (i = 0; i < 64; i++)
479 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
480 for (i = 0; i < 64; i++)
481 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
482 for (i = 0; i < 64; i++)
483 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
484 for (i = 0; i < 16; i++)
485 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
486 for (i = 0; i < 16; i++)
487 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
488 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
489 for (i = 0; i < 8; i++)
490 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
491 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
492 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
493
494 /* Receive */
495 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
496 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
497 for (i = 0; i < 16; i++)
498 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
499 for (i = 0; i < 16; i++)
500 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
c44ade9e 501 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
9a799d71
AK		 502 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
503 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
504 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
505 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
506 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
507 for (i = 0; i < 8; i++)
508 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
509 for (i = 0; i < 8; i++)
510 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
511 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
512
513 /* Transmit */
514 for (i = 0; i < 32; i++)
515 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
516 for (i = 0; i < 32; i++)
517 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
518 for (i = 0; i < 32; i++)
519 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
520 for (i = 0; i < 32; i++)
521 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
522 for (i = 0; i < 32; i++)
523 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
524 for (i = 0; i < 32; i++)
525 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
526 for (i = 0; i < 32; i++)
527 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
528 for (i = 0; i < 32; i++)
529 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
530 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
531 for (i = 0; i < 16; i++)
532 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
533 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
534 for (i = 0; i < 8; i++)
535 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
536 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
537
538 /* Wake Up */
539 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
540 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
541 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
542 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
543 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
544 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
545 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
546 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
11afc1b1 547 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
9a799d71 548
9a799d71
AK		 549 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
550 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
551 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
552 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
553 for (i = 0; i < 8; i++)
554 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
555 for (i = 0; i < 8; i++)
556 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
557 for (i = 0; i < 8; i++)
558 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
559 for (i = 0; i < 8; i++)
560 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
561 for (i = 0; i < 8; i++)
562 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
563 for (i = 0; i < 8; i++)
564 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
565
566 /* Statistics */
567 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
568 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
569 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
570 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
571 for (i = 0; i < 8; i++)
572 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
573 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
574 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
575 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
576 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
577 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
578 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
579 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
580 for (i = 0; i < 8; i++)
581 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
582 for (i = 0; i < 8; i++)
583 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
584 for (i = 0; i < 8; i++)
585 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
586 for (i = 0; i < 8; i++)
587 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
588 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
589 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
590 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
591 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
592 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
593 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
594 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
595 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
596 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
597 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
598 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
599 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
600 for (i = 0; i < 8; i++)
601 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
602 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
603 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
604 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
605 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
606 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
607 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
608 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
609 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
610 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
611 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
612 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
613 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
614 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
615 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
616 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
617 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
618 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
619 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
620 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
621 for (i = 0; i < 16; i++)
622 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
623 for (i = 0; i < 16; i++)
624 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
625 for (i = 0; i < 16; i++)
626 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
627 for (i = 0; i < 16; i++)
628 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
629
630 /* MAC */
631 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
632 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
633 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
634 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
635 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
636 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
637 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
638 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
639 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
640 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
641 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
642 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
643 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
644 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
645 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
646 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
647 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
648 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
649 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
650 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
651 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
652 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
653 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
654 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
655 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
656 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
657 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
658 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
659 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
660 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
661 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
662 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
663 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
664
665 /* Diagnostic */
666 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
667 for (i = 0; i < 8; i++)
98c00a1c 668 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
9a799d71 669 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
98c00a1c
JB		 670 for (i = 0; i < 4; i++)
671 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
9a799d71
AK		 672 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
673 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
674 for (i = 0; i < 8; i++)
98c00a1c 675 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
9a799d71 676 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
98c00a1c
JB		 677 for (i = 0; i < 4; i++)
678 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
9a799d71
AK		 679 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
680 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
681 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
682 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
683 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
684 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
685 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
686 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
687 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
688 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
689 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
690 for (i = 0; i < 8; i++)
98c00a1c 691 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
9a799d71
AK		 692 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
693 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
694 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
695 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
696 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
697 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
698 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
699 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
700 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
701}
702
703static int ixgbe_get_eeprom_len(struct net_device *netdev)
704{
705 struct ixgbe_adapter *adapter = netdev_priv(netdev);
706 return adapter->hw.eeprom.word_size * 2;
707}
708
709static int ixgbe_get_eeprom(struct net_device *netdev,
b4617240 710 struct ethtool_eeprom *eeprom, u8 *bytes)
9a799d71
AK		 711{
712 struct ixgbe_adapter *adapter = netdev_priv(netdev);
713 struct ixgbe_hw *hw = &adapter->hw;
714 u16 *eeprom_buff;
715 int first_word, last_word, eeprom_len;
716 int ret_val = 0;
717 u16 i;
718
719 if (eeprom->len == 0)
720 return -EINVAL;
721
722 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
723
724 first_word = eeprom->offset >> 1;
725 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
726 eeprom_len = last_word - first_word + 1;
727
728 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
729 if (!eeprom_buff)
730 return -ENOMEM;
731
732 for (i = 0; i < eeprom_len; i++) {
c44ade9e 733 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
b4617240 734 &eeprom_buff[i])))
9a799d71
AK		 735 break;
736 }
737
738 /* Device's eeprom is always little-endian, word addressable */
739 for (i = 0; i < eeprom_len; i++)
740 le16_to_cpus(&eeprom_buff[i]);
741
742 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
743 kfree(eeprom_buff);
744
745 return ret_val;
746}
747
748static void ixgbe_get_drvinfo(struct net_device *netdev,
b4617240 749 struct ethtool_drvinfo *drvinfo)
9a799d71
AK		 750{
751 struct ixgbe_adapter *adapter = netdev_priv(netdev);
34b0368c 752 char firmware_version[32];
9a799d71
AK		 753
754 strncpy(drvinfo->driver, ixgbe_driver_name, 32);
755 strncpy(drvinfo->version, ixgbe_driver_version, 32);
34b0368c
PWJ		 756
757 sprintf(firmware_version, "%d.%d-%d",
758 (adapter->eeprom_version & 0xF000) >> 12,
759 (adapter->eeprom_version & 0x0FF0) >> 4,
760 adapter->eeprom_version & 0x000F);
761
762 strncpy(drvinfo->fw_version, firmware_version, 32);
9a799d71
AK		 763 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
764 drvinfo->n_stats = IXGBE_STATS_LEN;
da4dd0f7 765 drvinfo->testinfo_len = IXGBE_TEST_LEN;
9a799d71
AK		 766 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
767}
768
769static void ixgbe_get_ringparam(struct net_device *netdev,
b4617240 770 struct ethtool_ringparam *ring)
9a799d71
AK		 771{
772 struct ixgbe_adapter *adapter = netdev_priv(netdev);
773 struct ixgbe_ring *tx_ring = adapter->tx_ring;
774 struct ixgbe_ring *rx_ring = adapter->rx_ring;
775
776 ring->rx_max_pending = IXGBE_MAX_RXD;
777 ring->tx_max_pending = IXGBE_MAX_TXD;
778 ring->rx_mini_max_pending = 0;
779 ring->rx_jumbo_max_pending = 0;
780 ring->rx_pending = rx_ring->count;
781 ring->tx_pending = tx_ring->count;
782 ring->rx_mini_pending = 0;
783 ring->rx_jumbo_pending = 0;
784}
785
786static int ixgbe_set_ringparam(struct net_device *netdev,
b4617240 787 struct ethtool_ringparam *ring)
9a799d71
AK		 788{
789 struct ixgbe_adapter *adapter = netdev_priv(netdev);
f9ed8854 790 struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
9a799d71 791 int i, err;
c431f97e 792 u32 new_rx_count, new_tx_count;
f9ed8854 793 bool need_update = false;
9a799d71
AK		 794
795 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
796 return -EINVAL;
797
798 new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
799 new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
800 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
801
802 new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
803 new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
804 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
805
806 if ((new_tx_count == adapter->tx_ring->count) &&
807 (new_rx_count == adapter->rx_ring->count)) {
808 /* nothing to do */
809 return 0;
810 }
811
d4f80882
AV		 812 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
813 msleep(1);
814
f9ed8854
MC		 815 temp_tx_ring = kcalloc(adapter->num_tx_queues,
816 sizeof(struct ixgbe_ring), GFP_KERNEL);
817 if (!temp_tx_ring) {
818 err = -ENOMEM;
819 goto err_setup;
820 }
821
822 if (new_tx_count != adapter->tx_ring_count) {
823 memcpy(temp_tx_ring, adapter->tx_ring,
824 adapter->num_tx_queues * sizeof(struct ixgbe_ring));
9a799d71 825 for (i = 0; i < adapter->num_tx_queues; i++) {
f9ed8854
MC		 826 temp_tx_ring[i].count = new_tx_count;
827 err = ixgbe_setup_tx_resources(adapter,
828 &temp_tx_ring[i]);
9a799d71 829 if (err) {
c431f97e
JB		 830 while (i) {
831 i--;
b4617240 832 ixgbe_free_tx_resources(adapter,
f9ed8854 833 &temp_tx_ring[i]);
c431f97e 834 }
9a799d71
AK		 835 goto err_setup;
836 }
f9ed8854 837 temp_tx_ring[i].v_idx = adapter->tx_ring[i].v_idx;
9a799d71 838 }
f9ed8854 839 need_update = true;
9a799d71
AK		 840 }
841
f9ed8854
MC		 842 temp_rx_ring = kcalloc(adapter->num_rx_queues,
843 sizeof(struct ixgbe_ring), GFP_KERNEL);
844 if ((!temp_rx_ring) && (need_update)) {
845 for (i = 0; i < adapter->num_tx_queues; i++)
846 ixgbe_free_tx_resources(adapter, &temp_tx_ring[i]);
847 kfree(temp_tx_ring);
848 err = -ENOMEM;
849 goto err_setup;
d3fa4721 850 }
9a799d71 851
f9ed8854
MC		 852 if (new_rx_count != adapter->rx_ring_count) {
853 memcpy(temp_rx_ring, adapter->rx_ring,
854 adapter->num_rx_queues * sizeof(struct ixgbe_ring));
c431f97e 855 for (i = 0; i < adapter->num_rx_queues; i++) {
f9ed8854
MC		 856 temp_rx_ring[i].count = new_rx_count;
857 err = ixgbe_setup_rx_resources(adapter,
858 &temp_rx_ring[i]);
9a799d71 859 if (err) {
c431f97e
JB		 860 while (i) {
861 i--;
b4617240 862 ixgbe_free_rx_resources(adapter,
f9ed8854 863 &temp_rx_ring[i]);
c431f97e 864 }
9a799d71
AK		 865 goto err_setup;
866 }
f9ed8854 867 temp_rx_ring[i].v_idx = adapter->rx_ring[i].v_idx;
9a799d71 868 }
f9ed8854
MC		 869 need_update = true;
870 }
871
872 /* if rings need to be updated, here's the place to do it in one shot */
873 if (need_update) {
d3fa4721 874 if (netif_running(netdev))
f9ed8854
MC		 875 ixgbe_down(adapter);
876
877 /* tx */
878 if (new_tx_count != adapter->tx_ring_count) {
879 kfree(adapter->tx_ring);
880 adapter->tx_ring = temp_tx_ring;
881 temp_tx_ring = NULL;
882 adapter->tx_ring_count = new_tx_count;
883 }
884
885 /* rx */
886 if (new_rx_count != adapter->rx_ring_count) {
887 kfree(adapter->rx_ring);
888 adapter->rx_ring = temp_rx_ring;
889 temp_rx_ring = NULL;
890 adapter->rx_ring_count = new_rx_count;
891 }
9a799d71
AK		 892 }
893
c431f97e 894 /* success! */
9a799d71 895 err = 0;
c431f97e 896 if (netif_running(netdev))
f9ed8854 897 ixgbe_up(adapter);
9a799d71 898
f9ed8854 899err_setup:
d4f80882 900 clear_bit(__IXGBE_RESETTING, &adapter->state);
9a799d71
AK		 901 return err;
902}
903
b9f2c044 904static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
9a799d71 905{
b9f2c044 906 switch (sset) {
da4dd0f7
PWJ		 907 case ETH_SS_TEST:
908 return IXGBE_TEST_LEN;
b9f2c044
JG		 909 case ETH_SS_STATS:
910 return IXGBE_STATS_LEN;
911 default:
912 return -EOPNOTSUPP;
913 }
9a799d71
AK		 914}
915
916static void ixgbe_get_ethtool_stats(struct net_device *netdev,
b4617240 917 struct ethtool_stats *stats, u64 *data)
9a799d71
AK		 918{
919 struct ixgbe_adapter *adapter = netdev_priv(netdev);
920 u64 *queue_stat;
921 int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
922 int j, k;
923 int i;
924
925 ixgbe_update_stats(adapter);
926 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
927 char *p = (char *)adapter + ixgbe_gstrings_stats[i].stat_offset;
928 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
b4617240 929 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
9a799d71
AK		 930 }
931 for (j = 0; j < adapter->num_tx_queues; j++) {
932 queue_stat = (u64 *)&adapter->tx_ring[j].stats;
933 for (k = 0; k < stat_count; k++)
934 data[i + k] = queue_stat[k];
935 i += k;
936 }
937 for (j = 0; j < adapter->num_rx_queues; j++) {
938 queue_stat = (u64 *)&adapter->rx_ring[j].stats;
939 for (k = 0; k < stat_count; k++)
940 data[i + k] = queue_stat[k];
941 i += k;
942 }
2f90b865
AD		 943 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
944 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
945 data[i++] = adapter->stats.pxontxc[j];
946 data[i++] = adapter->stats.pxofftxc[j];
947 }
948 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
949 data[i++] = adapter->stats.pxonrxc[j];
950 data[i++] = adapter->stats.pxoffrxc[j];
951 }
952 }
9a799d71
AK		 953}
954
955static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
b4617240 956 u8 *data)
9a799d71
AK		 957{
958 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 959 char *p = (char *)data;
9a799d71
AK		 960 int i;
961
962 switch (stringset) {
da4dd0f7
PWJ		 963 case ETH_SS_TEST:
964 memcpy(data, *ixgbe_gstrings_test,
965 IXGBE_TEST_LEN * ETH_GSTRING_LEN);
966 break;
9a799d71
AK		 967 case ETH_SS_STATS:
968 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
969 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
970 ETH_GSTRING_LEN);
971 p += ETH_GSTRING_LEN;
972 }
973 for (i = 0; i < adapter->num_tx_queues; i++) {
974 sprintf(p, "tx_queue_%u_packets", i);
975 p += ETH_GSTRING_LEN;
976 sprintf(p, "tx_queue_%u_bytes", i);
977 p += ETH_GSTRING_LEN;
978 }
979 for (i = 0; i < adapter->num_rx_queues; i++) {
980 sprintf(p, "rx_queue_%u_packets", i);
981 p += ETH_GSTRING_LEN;
982 sprintf(p, "rx_queue_%u_bytes", i);
983 p += ETH_GSTRING_LEN;
984 }
2f90b865
AD		 985 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
986 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
987 sprintf(p, "tx_pb_%u_pxon", i);
bfb8cc31
DS		 988 p += ETH_GSTRING_LEN;
989 sprintf(p, "tx_pb_%u_pxoff", i);
990 p += ETH_GSTRING_LEN;
2f90b865
AD		 991 }
992 for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
bfb8cc31
DS		 993 sprintf(p, "rx_pb_%u_pxon", i);
994 p += ETH_GSTRING_LEN;
995 sprintf(p, "rx_pb_%u_pxoff", i);
996 p += ETH_GSTRING_LEN;
2f90b865
AD		 997 }
998 }
b4617240 999 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
9a799d71
AK		 1000 break;
1001 }
1002}
1003
da4dd0f7
PWJ		 1004static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1005{
1006 struct ixgbe_hw *hw = &adapter->hw;
1007 bool link_up;
1008 u32 link_speed = 0;
1009 *data = 0;
1010
1011 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1012 if (link_up)
1013 return *data;
1014 else
1015 *data = 1;
1016 return *data;
1017}
1018
1019/* ethtool register test data */
1020struct ixgbe_reg_test {
1021 u16 reg;
1022 u8 array_len;
1023 u8 test_type;
1024 u32 mask;
1025 u32 write;
1026};
1027
1028/* In the hardware, registers are laid out either singly, in arrays
1029 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1030 * most tests take place on arrays or single registers (handled
1031 * as a single-element array) and special-case the tables.
1032 * Table tests are always pattern tests.
1033 *
1034 * We also make provision for some required setup steps by specifying
1035 * registers to be written without any read-back testing.
1036 */
1037
1038#define PATTERN_TEST 1
1039#define SET_READ_TEST 2
1040#define WRITE_NO_TEST 3
1041#define TABLE32_TEST 4
1042#define TABLE64_TEST_LO 5
1043#define TABLE64_TEST_HI 6
1044
1045/* default 82599 register test */
1046static struct ixgbe_reg_test reg_test_82599[] = {
1047 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1048 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1049 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1050 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1051 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1052 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1053 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1054 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1055 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1056 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1057 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1058 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1059 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1060 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1061 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1062 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1063 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1064 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1065 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1066 { 0, 0, 0, 0 }
1067};
1068
1069/* default 82598 register test */
1070static struct ixgbe_reg_test reg_test_82598[] = {
1071 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1072 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1073 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1074 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1075 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1076 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1077 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1078 /* Enable all four RX queues before testing. */
1079 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1080 /* RDH is read-only for 82598, only test RDT. */
1081 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1082 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1083 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1084 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1085 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1086 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1087 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1088 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1089 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1090 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1091 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1092 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1093 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1094 { 0, 0, 0, 0 }
1095};
1096
1097#define REG_PATTERN_TEST(R, M, W) \
1098{ \
1099 u32 pat, val, before; \
1100 const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1101 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { \
1102 before = readl(adapter->hw.hw_addr + R); \
1103 writel((_test[pat] & W), (adapter->hw.hw_addr + R)); \
1104 val = readl(adapter->hw.hw_addr + R); \
1105 if (val != (_test[pat] & W & M)) { \
1106 DPRINTK(DRV, ERR, "pattern test reg %04X failed: got "\
1107 "0x%08X expected 0x%08X\n", \
1108 R, val, (_test[pat] & W & M)); \
1109 *data = R; \
1110 writel(before, adapter->hw.hw_addr + R); \
1111 return 1; \
1112 } \
1113 writel(before, adapter->hw.hw_addr + R); \
1114 } \
1115}
1116
1117#define REG_SET_AND_CHECK(R, M, W) \
1118{ \
1119 u32 val, before; \
1120 before = readl(adapter->hw.hw_addr + R); \
1121 writel((W & M), (adapter->hw.hw_addr + R)); \
1122 val = readl(adapter->hw.hw_addr + R); \
1123 if ((W & M) != (val & M)) { \
1124 DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\
1125 "expected 0x%08X\n", R, (val & M), (W & M)); \
1126 *data = R; \
1127 writel(before, (adapter->hw.hw_addr + R)); \
1128 return 1; \
1129 } \
1130 writel(before, (adapter->hw.hw_addr + R)); \
1131}
1132
1133static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1134{
1135 struct ixgbe_reg_test *test;
1136 u32 value, before, after;
1137 u32 i, toggle;
1138
1139 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1140 toggle = 0x7FFFF30F;
1141 test = reg_test_82599;
1142 } else {
1143 toggle = 0x7FFFF3FF;
1144 test = reg_test_82598;
1145 }
1146
1147 /*
1148 * Because the status register is such a special case,
1149 * we handle it separately from the rest of the register
1150 * tests. Some bits are read-only, some toggle, and some
1151 * are writeable on newer MACs.
1152 */
1153 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1154 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1155 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1156 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1157 if (value != after) {
1158 DPRINTK(DRV, ERR, "failed STATUS register test got: "
1159 "0x%08X expected: 0x%08X\n", after, value);
1160 *data = 1;
1161 return 1;
1162 }
1163 /* restore previous status */
1164 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1165
1166 /*
1167 * Perform the remainder of the register test, looping through
1168 * the test table until we either fail or reach the null entry.
1169 */
1170 while (test->reg) {
1171 for (i = 0; i < test->array_len; i++) {
1172 switch (test->test_type) {
1173 case PATTERN_TEST:
1174 REG_PATTERN_TEST(test->reg + (i * 0x40),
1175 test->mask,
1176 test->write);
1177 break;
1178 case SET_READ_TEST:
1179 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1180 test->mask,
1181 test->write);
1182 break;
1183 case WRITE_NO_TEST:
1184 writel(test->write,
1185 (adapter->hw.hw_addr + test->reg)
1186 + (i * 0x40));
1187 break;
1188 case TABLE32_TEST:
1189 REG_PATTERN_TEST(test->reg + (i * 4),
1190 test->mask,
1191 test->write);
1192 break;
1193 case TABLE64_TEST_LO:
1194 REG_PATTERN_TEST(test->reg + (i * 8),
1195 test->mask,
1196 test->write);
1197 break;
1198 case TABLE64_TEST_HI:
1199 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1200 test->mask,
1201 test->write);
1202 break;
1203 }
1204 }
1205 test++;
1206 }
1207
1208 *data = 0;
1209 return 0;
1210}
1211
1212static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1213{
1214 struct ixgbe_hw *hw = &adapter->hw;
1215 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1216 *data = 1;
1217 else
1218 *data = 0;
1219 return *data;
1220}
1221
1222static irqreturn_t ixgbe_test_intr(int irq, void *data)
1223{
1224 struct net_device *netdev = (struct net_device *) data;
1225 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1226
1227 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1228
1229 return IRQ_HANDLED;
1230}
1231
1232static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1233{
1234 struct net_device *netdev = adapter->netdev;
1235 u32 mask, i = 0, shared_int = true;
1236 u32 irq = adapter->pdev->irq;
1237
1238 *data = 0;
1239
1240 /* Hook up test interrupt handler just for this test */
1241 if (adapter->msix_entries) {
1242 /* NOTE: we don't test MSI-X interrupts here, yet */
1243 return 0;
1244 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1245 shared_int = false;
1246 if (request_irq(irq, &ixgbe_test_intr, 0, netdev->name,
1247 netdev)) {
1248 *data = 1;
1249 return -1;
1250 }
1251 } else if (!request_irq(irq, &ixgbe_test_intr, IRQF_PROBE_SHARED,
1252 netdev->name, netdev)) {
1253 shared_int = false;
1254 } else if (request_irq(irq, &ixgbe_test_intr, IRQF_SHARED,
1255 netdev->name, netdev)) {
1256 *data = 1;
1257 return -1;
1258 }
1259 DPRINTK(HW, INFO, "testing %s interrupt\n",
1260 (shared_int ? "shared" : "unshared"));
1261
1262 /* Disable all the interrupts */
1263 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1264 msleep(10);
1265
1266 /* Test each interrupt */
1267 for (; i < 10; i++) {
1268 /* Interrupt to test */
1269 mask = 1 << i;
1270
1271 if (!shared_int) {
1272 /*
1273 * Disable the interrupts to be reported in
1274 * the cause register and then force the same
1275 * interrupt and see if one gets posted. If
1276 * an interrupt was posted to the bus, the
1277 * test failed.
1278 */
1279 adapter->test_icr = 0;
1280 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1281 ~mask & 0x00007FFF);
1282 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1283 ~mask & 0x00007FFF);
1284 msleep(10);
1285
1286 if (adapter->test_icr & mask) {
1287 *data = 3;
1288 break;
1289 }
1290 }
1291
1292 /*
1293 * Enable the interrupt to be reported in the cause
1294 * register and then force the same interrupt and see
1295 * if one gets posted. If an interrupt was not posted
1296 * to the bus, the test failed.
1297 */
1298 adapter->test_icr = 0;
1299 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1300 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1301 msleep(10);
1302
1303 if (!(adapter->test_icr &mask)) {
1304 *data = 4;
1305 break;
1306 }
1307
1308 if (!shared_int) {
1309 /*
1310 * Disable the other interrupts to be reported in
1311 * the cause register and then force the other
1312 * interrupts and see if any get posted. If
1313 * an interrupt was posted to the bus, the
1314 * test failed.
1315 */
1316 adapter->test_icr = 0;
1317 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1318 ~mask & 0x00007FFF);
1319 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1320 ~mask & 0x00007FFF);
1321 msleep(10);
1322
1323 if (adapter->test_icr) {
1324 *data = 5;
1325 break;
1326 }
1327 }
1328 }
1329
1330 /* Disable all the interrupts */
1331 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1332 msleep(10);
1333
1334 /* Unhook test interrupt handler */
1335 free_irq(irq, netdev);
1336
1337 return *data;
1338}
1339
1340static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1341{
1342 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1343 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1344 struct ixgbe_hw *hw = &adapter->hw;
1345 struct pci_dev *pdev = adapter->pdev;
1346 u32 reg_ctl;
1347 int i;
1348
1349 /* shut down the DMA engines now so they can be reinitialized later */
1350
1351 /* first Rx */
1352 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1353 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1354 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1355 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(0));
1356 reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
1357 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(0), reg_ctl);
1358
1359 /* now Tx */
1360 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(0));
1361 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1362 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(0), reg_ctl);
1363 if (hw->mac.type == ixgbe_mac_82599EB) {
1364 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1365 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1366 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1367 }
1368
1369 ixgbe_reset(adapter);
1370
1371 if (tx_ring->desc && tx_ring->tx_buffer_info) {
1372 for (i = 0; i < tx_ring->count; i++) {
1373 struct ixgbe_tx_buffer *buf =
1374 &(tx_ring->tx_buffer_info[i]);
1375 if (buf->dma)
1376 pci_unmap_single(pdev, buf->dma, buf->length,
1377 PCI_DMA_TODEVICE);
1378 if (buf->skb)
1379 dev_kfree_skb(buf->skb);
1380 }
1381 }
1382
1383 if (rx_ring->desc && rx_ring->rx_buffer_info) {
1384 for (i = 0; i < rx_ring->count; i++) {
1385 struct ixgbe_rx_buffer *buf =
1386 &(rx_ring->rx_buffer_info[i]);
1387 if (buf->dma)
1388 pci_unmap_single(pdev, buf->dma,
1389 IXGBE_RXBUFFER_2048,
1390 PCI_DMA_FROMDEVICE);
1391 if (buf->skb)
1392 dev_kfree_skb(buf->skb);
1393 }
1394 }
1395
1396 if (tx_ring->desc) {
1397 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1398 tx_ring->dma);
1399 tx_ring->desc = NULL;
1400 }
1401 if (rx_ring->desc) {
1402 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1403 rx_ring->dma);
1404 rx_ring->desc = NULL;
1405 }
1406
1407 kfree(tx_ring->tx_buffer_info);
1408 tx_ring->tx_buffer_info = NULL;
1409 kfree(rx_ring->rx_buffer_info);
1410 rx_ring->rx_buffer_info = NULL;
1411
1412 return;
1413}
1414
1415static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1416{
1417 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1418 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1419 struct pci_dev *pdev = adapter->pdev;
1420 u32 rctl, reg_data;
1421 int i, ret_val;
1422
1423 /* Setup Tx descriptor ring and Tx buffers */
1424
1425 if (!tx_ring->count)
1426 tx_ring->count = IXGBE_DEFAULT_TXD;
1427
1428 tx_ring->tx_buffer_info = kcalloc(tx_ring->count,
1429 sizeof(struct ixgbe_tx_buffer),
1430 GFP_KERNEL);
1431 if (!(tx_ring->tx_buffer_info)) {
1432 ret_val = 1;
1433 goto err_nomem;
1434 }
1435
1436 tx_ring->size = tx_ring->count * sizeof(struct ixgbe_legacy_tx_desc);
1437 tx_ring->size = ALIGN(tx_ring->size, 4096);
1438 if (!(tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1439 &tx_ring->dma))) {
1440 ret_val = 2;
1441 goto err_nomem;
1442 }
1443 tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1444
1445 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0),
1446 ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1447 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0),
1448 ((u64) tx_ring->dma >> 32));
1449 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0),
1450 tx_ring->count * sizeof(struct ixgbe_legacy_tx_desc));
1451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0);
1452 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0);
1453
1454 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1455 reg_data |= IXGBE_HLREG0_TXPADEN;
1456 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1457
1458 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1459 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1460 reg_data |= IXGBE_DMATXCTL_TE;
1461 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1462 }
1463 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0));
1464 reg_data |= IXGBE_TXDCTL_ENABLE;
1465 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data);
1466
1467 for (i = 0; i < tx_ring->count; i++) {
1468 struct ixgbe_legacy_tx_desc *desc = IXGBE_TX_DESC(*tx_ring, i);
1469 struct sk_buff *skb;
1470 unsigned int size = 1024;
1471
1472 skb = alloc_skb(size, GFP_KERNEL);
1473 if (!skb) {
1474 ret_val = 3;
1475 goto err_nomem;
1476 }
1477 skb_put(skb, size);
1478 tx_ring->tx_buffer_info[i].skb = skb;
1479 tx_ring->tx_buffer_info[i].length = skb->len;
1480 tx_ring->tx_buffer_info[i].dma =
1481 pci_map_single(pdev, skb->data, skb->len,
1482 PCI_DMA_TODEVICE);
1483 desc->buffer_addr = cpu_to_le64(tx_ring->tx_buffer_info[i].dma);
1484 desc->lower.data = cpu_to_le32(skb->len);
1485 desc->lower.data |= cpu_to_le32(IXGBE_TXD_CMD_EOP |
1486 IXGBE_TXD_CMD_IFCS |
1487 IXGBE_TXD_CMD_RS);
1488 desc->upper.data = 0;
1489 }
1490
1491 /* Setup Rx Descriptor ring and Rx buffers */
1492
1493 if (!rx_ring->count)
1494 rx_ring->count = IXGBE_DEFAULT_RXD;
1495
1496 rx_ring->rx_buffer_info = kcalloc(rx_ring->count,
1497 sizeof(struct ixgbe_rx_buffer),
1498 GFP_KERNEL);
1499 if (!(rx_ring->rx_buffer_info)) {
1500 ret_val = 4;
1501 goto err_nomem;
1502 }
1503
1504 rx_ring->size = rx_ring->count * sizeof(struct ixgbe_legacy_rx_desc);
1505 rx_ring->size = ALIGN(rx_ring->size, 4096);
1506 if (!(rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1507 &rx_ring->dma))) {
1508 ret_val = 5;
1509 goto err_nomem;
1510 }
1511 rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1512
1513 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1514 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0),
1516 ((u64)rx_ring->dma & 0xFFFFFFFF));
1517 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0),
1518 ((u64) rx_ring->dma >> 32));
1519 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size);
1520 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0);
1521 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0);
1522
1523 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1524 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1525 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1526
1527 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1528 reg_data &= ~IXGBE_HLREG0_LPBK;
1529 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1530
1531 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL);
1532#define IXGBE_RDRXCTL_RDMTS_MASK 0x00000003 /* Receive Descriptor Minimum
1533 Threshold Size mask */
1534 reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK;
1535 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data);
1536
1537 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL);
1538#define IXGBE_MCSTCTRL_MO_MASK 0x00000003 /* Multicast Offset mask */
1539 reg_data &= ~IXGBE_MCSTCTRL_MO_MASK;
1540 reg_data |= adapter->hw.mac.mc_filter_type;
1541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data);
1542
1543 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0));
1544 reg_data |= IXGBE_RXDCTL_ENABLE;
1545 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data);
1546 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1547 int j = adapter->rx_ring[0].reg_idx;
1548 u32 k;
1549 for (k = 0; k < 10; k++) {
1550 if (IXGBE_READ_REG(&adapter->hw,
1551 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1552 break;
1553 else
1554 msleep(1);
1555 }
1556 }
1557
1558 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1559 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1560
1561 for (i = 0; i < rx_ring->count; i++) {
1562 struct ixgbe_legacy_rx_desc *rx_desc =
1563 IXGBE_RX_DESC(*rx_ring, i);
1564 struct sk_buff *skb;
1565
1566 skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
1567 if (!skb) {
1568 ret_val = 6;
1569 goto err_nomem;
1570 }
1571 skb_reserve(skb, NET_IP_ALIGN);
1572 rx_ring->rx_buffer_info[i].skb = skb;
1573 rx_ring->rx_buffer_info[i].dma =
1574 pci_map_single(pdev, skb->data, IXGBE_RXBUFFER_2048,
1575 PCI_DMA_FROMDEVICE);
1576 rx_desc->buffer_addr =
1577 cpu_to_le64(rx_ring->rx_buffer_info[i].dma);
1578 memset(skb->data, 0x00, skb->len);
1579 }
1580
1581 return 0;
1582
1583err_nomem:
1584 ixgbe_free_desc_rings(adapter);
1585 return ret_val;
1586}
1587
1588static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1589{
1590 struct ixgbe_hw *hw = &adapter->hw;
1591 u32 reg_data;
1592
1593 /* right now we only support MAC loopback in the driver */
1594
1595 /* Setup MAC loopback */
1596 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1597 reg_data |= IXGBE_HLREG0_LPBK;
1598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1599
1600 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1601 reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1602 reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1603 IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
1604
1605 /* Disable Atlas Tx lanes; re-enabled in reset path */
1606 if (hw->mac.type == ixgbe_mac_82598EB) {
1607 u8 atlas;
1608
1609 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1610 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1611 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1612
1613 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1614 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1615 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1616
1617 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1618 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1619 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1620
1621 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1622 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1623 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1624 }
1625
1626 return 0;
1627}
1628
1629static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1630{
1631 u32 reg_data;
1632
1633 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1634 reg_data &= ~IXGBE_HLREG0_LPBK;
1635 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1636}
1637
1638static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1639 unsigned int frame_size)
1640{
1641 memset(skb->data, 0xFF, frame_size);
1642 frame_size &= ~1;
1643 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1644 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1645 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1646}
1647
1648static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1649 unsigned int frame_size)
1650{
1651 frame_size &= ~1;
1652 if (*(skb->data + 3) == 0xFF) {
1653 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1654 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1655 return 0;
1656 }
1657 }
1658 return 13;
1659}
1660
1661static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1662{
1663 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1664 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1665 struct pci_dev *pdev = adapter->pdev;
1666 int i, j, k, l, lc, good_cnt, ret_val = 0;
1667 unsigned long time;
1668
1669 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1);
1670
1671 /*
1672 * Calculate the loop count based on the largest descriptor ring
1673 * The idea is to wrap the largest ring a number of times using 64
1674 * send/receive pairs during each loop
1675 */
1676
1677 if (rx_ring->count <= tx_ring->count)
1678 lc = ((tx_ring->count / 64) * 2) + 1;
1679 else
1680 lc = ((rx_ring->count / 64) * 2) + 1;
1681
1682 k = l = 0;
1683 for (j = 0; j <= lc; j++) {
1684 for (i = 0; i < 64; i++) {
1685 ixgbe_create_lbtest_frame(
1686 tx_ring->tx_buffer_info[k].skb,
1687 1024);
1688 pci_dma_sync_single_for_device(pdev,
1689 tx_ring->tx_buffer_info[k].dma,
1690 tx_ring->tx_buffer_info[k].length,
1691 PCI_DMA_TODEVICE);
1692 if (unlikely(++k == tx_ring->count))
1693 k = 0;
1694 }
1695 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k);
1696 msleep(200);
1697 /* set the start time for the receive */
1698 time = jiffies;
1699 good_cnt = 0;
1700 do {
1701 /* receive the sent packets */
1702 pci_dma_sync_single_for_cpu(pdev,
1703 rx_ring->rx_buffer_info[l].dma,
1704 IXGBE_RXBUFFER_2048,
1705 PCI_DMA_FROMDEVICE);
1706 ret_val = ixgbe_check_lbtest_frame(
1707 rx_ring->rx_buffer_info[l].skb, 1024);
1708 if (!ret_val)
1709 good_cnt++;
1710 if (++l == rx_ring->count)
1711 l = 0;
1712 /*
1713 * time + 20 msecs (200 msecs on 2.4) is more than
1714 * enough time to complete the receives, if it's
1715 * exceeded, break and error off
1716 */
1717 } while (good_cnt < 64 && jiffies < (time + 20));
1718 if (good_cnt != 64) {
1719 /* ret_val is the same as mis-compare */
1720 ret_val = 13;
1721 break;
1722 }
1723 if (jiffies >= (time + 20)) {
1724 /* Error code for time out error */
1725 ret_val = 14;
1726 break;
1727 }
1728 }
1729
1730 return ret_val;
1731}
1732
1733static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1734{
1735 *data = ixgbe_setup_desc_rings(adapter);
1736 if (*data)
1737 goto out;
1738 *data = ixgbe_setup_loopback_test(adapter);
1739 if (*data)
1740 goto err_loopback;
1741 *data = ixgbe_run_loopback_test(adapter);
1742 ixgbe_loopback_cleanup(adapter);
1743
1744err_loopback:
1745 ixgbe_free_desc_rings(adapter);
1746out:
1747 return *data;
1748}
1749
1750static void ixgbe_diag_test(struct net_device *netdev,
1751 struct ethtool_test *eth_test, u64 *data)
1752{
1753 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1754 bool if_running = netif_running(netdev);
1755
1756 set_bit(__IXGBE_TESTING, &adapter->state);
1757 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1758 /* Offline tests */
1759
1760 DPRINTK(HW, INFO, "offline testing starting\n");
1761
1762 /* Link test performed before hardware reset so autoneg doesn't
1763 * interfere with test result */
1764 if (ixgbe_link_test(adapter, &data[4]))
1765 eth_test->flags |= ETH_TEST_FL_FAILED;
1766
1767 if (if_running)
1768 /* indicate we're in test mode */
1769 dev_close(netdev);
1770 else
1771 ixgbe_reset(adapter);
1772
1773 DPRINTK(HW, INFO, "register testing starting\n");
1774 if (ixgbe_reg_test(adapter, &data[0]))
1775 eth_test->flags |= ETH_TEST_FL_FAILED;
1776
1777 ixgbe_reset(adapter);
1778 DPRINTK(HW, INFO, "eeprom testing starting\n");
1779 if (ixgbe_eeprom_test(adapter, &data[1]))
1780 eth_test->flags |= ETH_TEST_FL_FAILED;
1781
1782 ixgbe_reset(adapter);
1783 DPRINTK(HW, INFO, "interrupt testing starting\n");
1784 if (ixgbe_intr_test(adapter, &data[2]))
1785 eth_test->flags |= ETH_TEST_FL_FAILED;
1786
1787 ixgbe_reset(adapter);
1788 DPRINTK(HW, INFO, "loopback testing starting\n");
1789 if (ixgbe_loopback_test(adapter, &data[3]))
1790 eth_test->flags |= ETH_TEST_FL_FAILED;
1791
1792 ixgbe_reset(adapter);
1793
1794 clear_bit(__IXGBE_TESTING, &adapter->state);
1795 if (if_running)
1796 dev_open(netdev);
1797 } else {
1798 DPRINTK(HW, INFO, "online testing starting\n");
1799 /* Online tests */
1800 if (ixgbe_link_test(adapter, &data[4]))
1801 eth_test->flags |= ETH_TEST_FL_FAILED;
1802
1803 /* Online tests aren't run; pass by default */
1804 data[0] = 0;
1805 data[1] = 0;
1806 data[2] = 0;
1807 data[3] = 0;
1808
1809 clear_bit(__IXGBE_TESTING, &adapter->state);
1810 }
1811 msleep_interruptible(4 * 1000);
1812}
9a799d71 1813
d6c519e1
AD		 1814static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1815 struct ethtool_wolinfo *wol)
1816{
1817 struct ixgbe_hw *hw = &adapter->hw;
1818 int retval = 1;
1819
1820 switch(hw->device_id) {
1821 case IXGBE_DEV_ID_82599_KX4:
1822 retval = 0;
1823 break;
1824 default:
1825 wol->supported = 0;
1826 retval = 0;
1827 }
1828
1829 return retval;
1830}
1831
9a799d71 1832static void ixgbe_get_wol(struct net_device *netdev,
b4617240 1833 struct ethtool_wolinfo *wol)
9a799d71 1834{
e63d9762
PW		 1835 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1836
1837 wol->supported = WAKE_UCAST | WAKE_MCAST |
1838 WAKE_BCAST | WAKE_MAGIC;
9a799d71
AK		 1839 wol->wolopts = 0;
1840
d6c519e1
AD		 1841 if (ixgbe_wol_exclusion(adapter, wol) ||
1842 !device_can_wakeup(&adapter->pdev->dev))
e63d9762
PW		 1843 return;
1844
1845 if (adapter->wol & IXGBE_WUFC_EX)
1846 wol->wolopts |= WAKE_UCAST;
1847 if (adapter->wol & IXGBE_WUFC_MC)
1848 wol->wolopts |= WAKE_MCAST;
1849 if (adapter->wol & IXGBE_WUFC_BC)
1850 wol->wolopts |= WAKE_BCAST;
1851 if (adapter->wol & IXGBE_WUFC_MAG)
1852 wol->wolopts |= WAKE_MAGIC;
1853
9a799d71
AK		 1854 return;
1855}
1856
e63d9762
PW		 1857static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1858{
1859 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1860
1861 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1862 return -EOPNOTSUPP;
1863
d6c519e1
AD		 1864 if (ixgbe_wol_exclusion(adapter, wol))
1865 return wol->wolopts ? -EOPNOTSUPP : 0;
1866
e63d9762
PW		 1867 adapter->wol = 0;
1868
1869 if (wol->wolopts & WAKE_UCAST)
1870 adapter->wol |= IXGBE_WUFC_EX;
1871 if (wol->wolopts & WAKE_MCAST)
1872 adapter->wol |= IXGBE_WUFC_MC;
1873 if (wol->wolopts & WAKE_BCAST)
1874 adapter->wol |= IXGBE_WUFC_BC;
1875 if (wol->wolopts & WAKE_MAGIC)
1876 adapter->wol |= IXGBE_WUFC_MAG;
1877
1878 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1879
1880 return 0;
1881}
1882
9a799d71
AK		 1883static int ixgbe_nway_reset(struct net_device *netdev)
1884{
1885 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1886
d4f80882
AV		 1887 if (netif_running(netdev))
1888 ixgbe_reinit_locked(adapter);
9a799d71
AK		 1889
1890 return 0;
1891}
1892
1893static int ixgbe_phys_id(struct net_device *netdev, u32 data)
1894{
1895 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e
JB		 1896 struct ixgbe_hw *hw = &adapter->hw;
1897 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
9a799d71
AK		 1898 u32 i;
1899
1900 if (!data || data > 300)
1901 data = 300;
1902
1903 for (i = 0; i < (data * 1000); i += 400) {
c44ade9e 1904 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
9a799d71 1905 msleep_interruptible(200);
c44ade9e 1906 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
9a799d71
AK		 1907 msleep_interruptible(200);
1908 }
1909
1910 /* Restore LED settings */
1911 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
1912
1913 return 0;
1914}
1915
1916static int ixgbe_get_coalesce(struct net_device *netdev,
b4617240 1917 struct ethtool_coalesce *ec)
9a799d71
AK		 1918{
1919 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1920
9a799d71 1921 ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0].work_limit;
30efa5a3
JB		 1922
1923 /* only valid if in constant ITR mode */
1924 switch (adapter->itr_setting) {
1925 case 0:
1926 /* throttling disabled */
1927 ec->rx_coalesce_usecs = 0;
1928 break;
1929 case 1:
1930 /* dynamic ITR mode */
1931 ec->rx_coalesce_usecs = 1;
1932 break;
1933 default:
1934 /* fixed interrupt rate mode */
1935 ec->rx_coalesce_usecs = 1000000/adapter->eitr_param;
1936 break;
1937 }
9a799d71
AK		 1938 return 0;
1939}
1940
1941static int ixgbe_set_coalesce(struct net_device *netdev,
b4617240 1942 struct ethtool_coalesce *ec)
9a799d71
AK		 1943{
1944 struct ixgbe_adapter *adapter = netdev_priv(netdev);
30efa5a3 1945 int i;
9a799d71
AK		 1946
1947 if (ec->tx_max_coalesced_frames_irq)
30efa5a3
JB		 1948 adapter->tx_ring[0].work_limit = ec->tx_max_coalesced_frames_irq;
1949
1950 if (ec->rx_coalesce_usecs > 1) {
509ee935
JB		 1951 /* check the limits */
1952 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
1953 (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
1954 return -EINVAL;
1955
30efa5a3
JB		 1956 /* store the value in ints/second */
1957 adapter->eitr_param = 1000000/ec->rx_coalesce_usecs;
1958
1959 /* static value of interrupt rate */
1960 adapter->itr_setting = adapter->eitr_param;
509ee935 1961 /* clear the lower bit as its used for dynamic state */
30efa5a3
JB		 1962 adapter->itr_setting &= ~1;
1963 } else if (ec->rx_coalesce_usecs == 1) {
1964 /* 1 means dynamic mode */
1965 adapter->eitr_param = 20000;
1966 adapter->itr_setting = 1;
1967 } else {
509ee935
JB		 1968 /*
1969 * any other value means disable eitr, which is best
1970 * served by setting the interrupt rate very high
1971 */
1972 adapter->eitr_param = IXGBE_MAX_INT_RATE;
30efa5a3
JB		 1973 adapter->itr_setting = 0;
1974 }
9a799d71 1975
30efa5a3 1976 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
7a921c93 1977 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
30efa5a3 1978 if (q_vector->txr_count && !q_vector->rxr_count)
509ee935 1979 /* tx vector gets half the rate */
30efa5a3
JB		 1980 q_vector->eitr = (adapter->eitr_param >> 1);
1981 else
1982 /* rx only or mixed */
1983 q_vector->eitr = adapter->eitr_param;
509ee935
JB		 1984 ixgbe_write_eitr(adapter, i,
1985 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 1986 }
1987
1988 return 0;
1989}
1990
f8212f97
AD		 1991static int ixgbe_set_flags(struct net_device *netdev, u32 data)
1992{
1993 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1994
1995 ethtool_op_set_flags(netdev, data);
1996
1997 if (!(adapter->flags & IXGBE_FLAG_RSC_CAPABLE))
1998 return 0;
1999
2000 /* if state changes we need to update adapter->flags and reset */
2001 if ((!!(data & ETH_FLAG_LRO)) !=
2002 (!!(adapter->flags & IXGBE_FLAG_RSC_ENABLED))) {
2003 adapter->flags ^= IXGBE_FLAG_RSC_ENABLED;
2004 if (netif_running(netdev))
2005 ixgbe_reinit_locked(adapter);
2006 else
2007 ixgbe_reset(adapter);
2008 }
2009 return 0;
2010
2011}
9a799d71 2012
b9804972 2013static const struct ethtool_ops ixgbe_ethtool_ops = {
9a799d71
AK		 2014 .get_settings = ixgbe_get_settings,
2015 .set_settings = ixgbe_set_settings,
2016 .get_drvinfo = ixgbe_get_drvinfo,
2017 .get_regs_len = ixgbe_get_regs_len,
2018 .get_regs = ixgbe_get_regs,
2019 .get_wol = ixgbe_get_wol,
e63d9762 2020 .set_wol = ixgbe_set_wol,
9a799d71
AK		 2021 .nway_reset = ixgbe_nway_reset,
2022 .get_link = ethtool_op_get_link,
2023 .get_eeprom_len = ixgbe_get_eeprom_len,
2024 .get_eeprom = ixgbe_get_eeprom,
2025 .get_ringparam = ixgbe_get_ringparam,
2026 .set_ringparam = ixgbe_set_ringparam,
2027 .get_pauseparam = ixgbe_get_pauseparam,
2028 .set_pauseparam = ixgbe_set_pauseparam,
2029 .get_rx_csum = ixgbe_get_rx_csum,
2030 .set_rx_csum = ixgbe_set_rx_csum,
2031 .get_tx_csum = ixgbe_get_tx_csum,
2032 .set_tx_csum = ixgbe_set_tx_csum,
2033 .get_sg = ethtool_op_get_sg,
2034 .set_sg = ethtool_op_set_sg,
2035 .get_msglevel = ixgbe_get_msglevel,
2036 .set_msglevel = ixgbe_set_msglevel,
2037 .get_tso = ethtool_op_get_tso,
2038 .set_tso = ixgbe_set_tso,
da4dd0f7 2039 .self_test = ixgbe_diag_test,
9a799d71
AK		 2040 .get_strings = ixgbe_get_strings,
2041 .phys_id = ixgbe_phys_id,
b4617240 2042 .get_sset_count = ixgbe_get_sset_count,
9a799d71
AK		 2043 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2044 .get_coalesce = ixgbe_get_coalesce,
2045 .set_coalesce = ixgbe_set_coalesce,
177db6ff 2046 .get_flags = ethtool_op_get_flags,
f8212f97 2047 .set_flags = ixgbe_set_flags,
9a799d71
AK		 2048};
2049
2050void ixgbe_set_ethtool_ops(struct net_device *netdev)
2051{
2052 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2053}
Clone of davem's net-next-2.6 tree