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e1000e: only perform ESB2 MDIC workaround on certain configurations
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_ethtool.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for ixgbe */
29
30#include <linux/types.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/ethtool.h>
35#include <linux/vmalloc.h>
36#include <linux/uaccess.h>
37
38#include "ixgbe.h"
39
40
41#define IXGBE_ALL_RAR_ENTRIES 16
42
29c3a050
AK		 43enum {NETDEV_STATS, IXGBE_STATS};
44
9a799d71
AK		 45struct ixgbe_stats {
46 char stat_string[ETH_GSTRING_LEN];
29c3a050 47 int type;
9a799d71
AK		 48 int sizeof_stat;
49 int stat_offset;
50};
51
29c3a050
AK		 52#define IXGBE_STAT(m) IXGBE_STATS, \
53 sizeof(((struct ixgbe_adapter *)0)->m), \
54 offsetof(struct ixgbe_adapter, m)
55#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
56 sizeof(((struct net_device *)0)->m), \
57 offsetof(struct net_device, m)
58
9a799d71 59static struct ixgbe_stats ixgbe_gstrings_stats[] = {
2d86f139
AK		 60 {"rx_packets", IXGBE_NETDEV_STAT(stats.rx_packets)},
61 {"tx_packets", IXGBE_NETDEV_STAT(stats.tx_packets)},
62 {"rx_bytes", IXGBE_NETDEV_STAT(stats.rx_bytes)},
63 {"tx_bytes", IXGBE_NETDEV_STAT(stats.tx_bytes)},
aad71918
BG		 64 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
65 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
66 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
67 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
9a799d71
AK		 68 {"lsc_int", IXGBE_STAT(lsc_int)},
69 {"tx_busy", IXGBE_STAT(tx_busy)},
70 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
2d86f139
AK		 71 {"rx_errors", IXGBE_NETDEV_STAT(stats.rx_errors)},
72 {"tx_errors", IXGBE_NETDEV_STAT(stats.tx_errors)},
73 {"rx_dropped", IXGBE_NETDEV_STAT(stats.rx_dropped)},
74 {"tx_dropped", IXGBE_NETDEV_STAT(stats.tx_dropped)},
75 {"multicast", IXGBE_NETDEV_STAT(stats.multicast)},
9a799d71
AK		 76 {"broadcast", IXGBE_STAT(stats.bprc)},
77 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
2d86f139
AK		 78 {"collisions", IXGBE_NETDEV_STAT(stats.collisions)},
79 {"rx_over_errors", IXGBE_NETDEV_STAT(stats.rx_over_errors)},
80 {"rx_crc_errors", IXGBE_NETDEV_STAT(stats.rx_crc_errors)},
81 {"rx_frame_errors", IXGBE_NETDEV_STAT(stats.rx_frame_errors)},
94b982b2
MC		 82 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
83 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
c4cf55e5
PWJ		 84 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
85 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
2d86f139
AK		 86 {"rx_fifo_errors", IXGBE_NETDEV_STAT(stats.rx_fifo_errors)},
87 {"rx_missed_errors", IXGBE_NETDEV_STAT(stats.rx_missed_errors)},
88 {"tx_aborted_errors", IXGBE_NETDEV_STAT(stats.tx_aborted_errors)},
89 {"tx_carrier_errors", IXGBE_NETDEV_STAT(stats.tx_carrier_errors)},
90 {"tx_fifo_errors", IXGBE_NETDEV_STAT(stats.tx_fifo_errors)},
91 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(stats.tx_heartbeat_errors)},
9a799d71
AK		 92 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
93 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
94 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
95 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
9a799d71
AK		 96 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
97 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
98 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
99 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
9a799d71 100 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
9a799d71
AK		 101 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
102 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
e8e26350 103 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
6d45522c
YZ		 104#ifdef IXGBE_FCOE
105 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
106 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
107 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
108 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
109 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
110 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
111#endif /* IXGBE_FCOE */
9a799d71
AK		 112};
113
114#define IXGBE_QUEUE_STATS_LEN \
454d7c9b
WC		 115 ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
116 ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
117 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
b4617240 118#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
2f90b865 119#define IXGBE_PB_STATS_LEN ( \
9d2f4720 120 (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
2f90b865
AD		 121 IXGBE_FLAG_DCB_ENABLED) ? \
122 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
123 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
124 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
125 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
126 / sizeof(u64) : 0)
127#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
128 IXGBE_PB_STATS_LEN + \
129 IXGBE_QUEUE_STATS_LEN)
9a799d71 130
da4dd0f7
PWJ		 131static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
132 "Register test (offline)", "Eeprom test (offline)",
133 "Interrupt test (offline)", "Loopback test (offline)",
134 "Link test (on/offline)"
135};
136#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
137
9a799d71 138static int ixgbe_get_settings(struct net_device *netdev,
b4617240 139 struct ethtool_cmd *ecmd)
9a799d71
AK		 140{
141 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb
AV		 142 struct ixgbe_hw *hw = &adapter->hw;
143 u32 link_speed = 0;
144 bool link_up;
9a799d71 145
735441fb
AV		 146 ecmd->supported = SUPPORTED_10000baseT_Full;
147 ecmd->autoneg = AUTONEG_ENABLE;
9a799d71 148 ecmd->transceiver = XCVR_EXTERNAL;
74766013 149 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 150 (hw->phy.multispeed_fiber)) {
735441fb 151 ecmd->supported |= (SUPPORTED_1000baseT_Full |
74766013 152 SUPPORTED_Autoneg);
735441fb 153
74766013 154 ecmd->advertising = ADVERTISED_Autoneg;
735441fb
AV		 155 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
156 ecmd->advertising |= ADVERTISED_10000baseT_Full;
157 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
158 ecmd->advertising |= ADVERTISED_1000baseT_Full;
7c5b8323
DS		 159 /*
160 * It's possible that phy.autoneg_advertised may not be
161 * set yet. If so display what the default would be -
162 * both 1G and 10G supported.
163 */
164 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
165 ADVERTISED_10000baseT_Full)))
166 ecmd->advertising |= (ADVERTISED_10000baseT_Full |
167 ADVERTISED_1000baseT_Full);
735441fb 168
74766013
MC		 169 if (hw->phy.media_type == ixgbe_media_type_copper) {
170 ecmd->supported |= SUPPORTED_TP;
171 ecmd->advertising |= ADVERTISED_TP;
172 ecmd->port = PORT_TP;
173 } else {
174 ecmd->supported |= SUPPORTED_FIBRE;
175 ecmd->advertising |= ADVERTISED_FIBRE;
176 ecmd->port = PORT_FIBRE;
177 }
1e336d0f
DS		 178 } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
179 /* Set as FIBRE until SERDES defined in kernel */
46a72b35 180 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
2f21bdd3
DS		 181 ecmd->supported = (SUPPORTED_1000baseT_Full |
182 SUPPORTED_FIBRE);
183 ecmd->advertising = (ADVERTISED_1000baseT_Full |
184 ADVERTISED_FIBRE);
185 ecmd->port = PORT_FIBRE;
186 ecmd->autoneg = AUTONEG_DISABLE;
46a72b35
MC		 187 } else {
188 ecmd->supported |= (SUPPORTED_1000baseT_Full |
189 SUPPORTED_FIBRE);
190 ecmd->advertising = (ADVERTISED_10000baseT_Full |
191 ADVERTISED_1000baseT_Full |
192 ADVERTISED_FIBRE);
193 ecmd->port = PORT_FIBRE;
1e336d0f 194 }
735441fb
AV		 195 } else {
196 ecmd->supported |= SUPPORTED_FIBRE;
197 ecmd->advertising = (ADVERTISED_10000baseT_Full |
b4617240 198 ADVERTISED_FIBRE);
735441fb 199 ecmd->port = PORT_FIBRE;
c44ade9e 200 ecmd->autoneg = AUTONEG_DISABLE;
735441fb 201 }
9a799d71 202
3b8626ba
PW		 203 /* Get PHY type */
204 switch (adapter->hw.phy.type) {
205 case ixgbe_phy_tn:
206 case ixgbe_phy_cu_unknown:
207 /* Copper 10G-BASET */
208 ecmd->port = PORT_TP;
209 break;
210 case ixgbe_phy_qt:
211 ecmd->port = PORT_FIBRE;
212 break;
213 case ixgbe_phy_nl:
214 case ixgbe_phy_tw_tyco:
215 case ixgbe_phy_tw_unknown:
216 case ixgbe_phy_sfp_ftl:
217 case ixgbe_phy_sfp_avago:
218 case ixgbe_phy_sfp_intel:
219 case ixgbe_phy_sfp_unknown:
220 switch (adapter->hw.phy.sfp_type) {
221 /* SFP+ devices, further checking needed */
222 case ixgbe_sfp_type_da_cu:
223 case ixgbe_sfp_type_da_cu_core0:
224 case ixgbe_sfp_type_da_cu_core1:
225 ecmd->port = PORT_DA;
226 break;
227 case ixgbe_sfp_type_sr:
228 case ixgbe_sfp_type_lr:
229 case ixgbe_sfp_type_srlr_core0:
230 case ixgbe_sfp_type_srlr_core1:
231 ecmd->port = PORT_FIBRE;
232 break;
233 case ixgbe_sfp_type_not_present:
234 ecmd->port = PORT_NONE;
235 break;
236 case ixgbe_sfp_type_unknown:
237 default:
238 ecmd->port = PORT_OTHER;
239 break;
240 }
241 break;
242 case ixgbe_phy_xaui:
243 ecmd->port = PORT_NONE;
244 break;
245 case ixgbe_phy_unknown:
246 case ixgbe_phy_generic:
247 case ixgbe_phy_sfp_unsupported:
248 default:
249 ecmd->port = PORT_OTHER;
250 break;
251 }
252
c44ade9e 253 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
735441fb
AV		 254 if (link_up) {
255 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
b4617240 256 SPEED_10000 : SPEED_1000;
9a799d71
AK		 257 ecmd->duplex = DUPLEX_FULL;
258 } else {
259 ecmd->speed = -1;
260 ecmd->duplex = -1;
261 }
262
9a799d71
AK		 263 return 0;
264}
265
266static int ixgbe_set_settings(struct net_device *netdev,
b4617240 267 struct ethtool_cmd *ecmd)
9a799d71
AK		 268{
269 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 270 struct ixgbe_hw *hw = &adapter->hw;
0befdb3e 271 u32 advertised, old;
74766013 272 s32 err = 0;
9a799d71 273
74766013 274 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 275 (hw->phy.multispeed_fiber)) {
0befdb3e
JB		 276 /* 10000/copper and 1000/copper must autoneg
277 * this function does not support any duplex forcing, but can
278 * limit the advertising of the adapter to only 10000 or 1000 */
279 if (ecmd->autoneg == AUTONEG_DISABLE)
280 return -EINVAL;
281
282 old = hw->phy.autoneg_advertised;
283 advertised = 0;
284 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
285 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
286
287 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
288 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
289
290 if (old == advertised)
74766013 291 return err;
0befdb3e 292 /* this sets the link speed and restarts auto-neg */
74766013 293 hw->mac.autotry_restart = true;
8620a103 294 err = hw->mac.ops.setup_link(hw, advertised, true, true);
0befdb3e
JB		 295 if (err) {
296 DPRINTK(PROBE, INFO,
297 "setup link failed with code %d\n", err);
8620a103 298 hw->mac.ops.setup_link(hw, old, true, true);
0befdb3e 299 }
74766013
MC		 300 } else {
301 /* in this case we currently only support 10Gb/FULL */
302 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
a3801379 303 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
74766013
MC		 304 (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
305 return -EINVAL;
9a799d71
AK		 306 }
307
74766013 308 return err;
9a799d71
AK		 309}
310
311static void ixgbe_get_pauseparam(struct net_device *netdev,
b4617240 312 struct ethtool_pauseparam *pause)
9a799d71
AK		 313{
314 struct ixgbe_adapter *adapter = netdev_priv(netdev);
315 struct ixgbe_hw *hw = &adapter->hw;
316
71fd570b
DS		 317 /*
318 * Flow Control Autoneg isn't on if
319 * - we didn't ask for it OR
320 * - it failed, we know this by tx & rx being off
321 */
322 if (hw->fc.disable_fc_autoneg ||
323 (hw->fc.current_mode == ixgbe_fc_none))
324 pause->autoneg = 0;
325 else
326 pause->autoneg = 1;
9a799d71 327
8756924c
PWJ		 328#ifdef CONFIG_DCB
329 if (hw->fc.current_mode == ixgbe_fc_pfc) {
330 pause->rx_pause = 0;
331 pause->tx_pause = 0;
332 }
333
334#endif
0ecc061d 335 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
9a799d71 336 pause->rx_pause = 1;
0ecc061d 337 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
9a799d71 338 pause->tx_pause = 1;
0ecc061d 339 } else if (hw->fc.current_mode == ixgbe_fc_full) {
9a799d71
AK		 340 pause->rx_pause = 1;
341 pause->tx_pause = 1;
342 }
343}
344
345static int ixgbe_set_pauseparam(struct net_device *netdev,
b4617240 346 struct ethtool_pauseparam *pause)
9a799d71
AK		 347{
348 struct ixgbe_adapter *adapter = netdev_priv(netdev);
349 struct ixgbe_hw *hw = &adapter->hw;
620fa036 350 struct ixgbe_fc_info fc;
9a799d71 351
264857b8
PWJ		 352#ifdef CONFIG_DCB
353 if (adapter->dcb_cfg.pfc_mode_enable ||
354 ((hw->mac.type == ixgbe_mac_82598EB) &&
355 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
356 return -EINVAL;
357
358#endif
620fa036
MC		 359
360 fc = hw->fc;
361
71fd570b 362 if (pause->autoneg != AUTONEG_ENABLE)
620fa036 363 fc.disable_fc_autoneg = true;
71fd570b 364 else
620fa036 365 fc.disable_fc_autoneg = false;
71fd570b
DS		 366
367 if (pause->rx_pause && pause->tx_pause)
620fa036 368 fc.requested_mode = ixgbe_fc_full;
9a799d71 369 else if (pause->rx_pause && !pause->tx_pause)
620fa036 370 fc.requested_mode = ixgbe_fc_rx_pause;
9a799d71 371 else if (!pause->rx_pause && pause->tx_pause)
620fa036 372 fc.requested_mode = ixgbe_fc_tx_pause;
9a799d71 373 else if (!pause->rx_pause && !pause->tx_pause)
620fa036 374 fc.requested_mode = ixgbe_fc_none;
9c83b070
AV		 375 else
376 return -EINVAL;
9a799d71 377
264857b8 378#ifdef CONFIG_DCB
620fa036 379 adapter->last_lfc_mode = fc.requested_mode;
264857b8 380#endif
620fa036
MC		 381
382 /* if the thing changed then we'll update and use new autoneg */
383 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
384 hw->fc = fc;
385 if (netif_running(netdev))
386 ixgbe_reinit_locked(adapter);
387 else
388 ixgbe_reset(adapter);
389 }
9a799d71
AK		 390
391 return 0;
392}
393
394static u32 ixgbe_get_rx_csum(struct net_device *netdev)
395{
396 struct ixgbe_adapter *adapter = netdev_priv(netdev);
397 return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
398}
399
400static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
401{
402 struct ixgbe_adapter *adapter = netdev_priv(netdev);
403 if (data)
404 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
405 else
406 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
407
d4f80882
AV		 408 if (netif_running(netdev))
409 ixgbe_reinit_locked(adapter);
410 else
9a799d71 411 ixgbe_reset(adapter);
9a799d71
AK		 412
413 return 0;
414}
415
416static u32 ixgbe_get_tx_csum(struct net_device *netdev)
417{
22f32b7a 418 return (netdev->features & NETIF_F_IP_CSUM) != 0;
9a799d71
AK		 419}
420
421static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
422{
45a5ead0
JB		 423 struct ixgbe_adapter *adapter = netdev_priv(netdev);
424
425 if (data) {
22f32b7a 426 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
45a5ead0
JB		 427 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
428 netdev->features |= NETIF_F_SCTP_CSUM;
429 } else {
3d3d6d3c 430 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
45a5ead0
JB		 431 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
432 netdev->features &= ~NETIF_F_SCTP_CSUM;
433 }
9a799d71
AK		 434
435 return 0;
436}
437
438static int ixgbe_set_tso(struct net_device *netdev, u32 data)
439{
9a799d71
AK		 440 if (data) {
441 netdev->features |= NETIF_F_TSO;
442 netdev->features |= NETIF_F_TSO6;
443 } else {
fd2ea0a7 444 netif_tx_stop_all_queues(netdev);
9a799d71
AK		 445 netdev->features &= ~NETIF_F_TSO;
446 netdev->features &= ~NETIF_F_TSO6;
fd2ea0a7 447 netif_tx_start_all_queues(netdev);
9a799d71
AK		 448 }
449 return 0;
450}
451
452static u32 ixgbe_get_msglevel(struct net_device *netdev)
453{
454 struct ixgbe_adapter *adapter = netdev_priv(netdev);
455 return adapter->msg_enable;
456}
457
458static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
459{
460 struct ixgbe_adapter *adapter = netdev_priv(netdev);
461 adapter->msg_enable = data;
462}
463
464static int ixgbe_get_regs_len(struct net_device *netdev)
465{
466#define IXGBE_REGS_LEN 1128
467 return IXGBE_REGS_LEN * sizeof(u32);
468}
469
470#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
471
472static void ixgbe_get_regs(struct net_device *netdev,
b4617240 473 struct ethtool_regs *regs, void *p)
9a799d71
AK		 474{
475 struct ixgbe_adapter *adapter = netdev_priv(netdev);
476 struct ixgbe_hw *hw = &adapter->hw;
477 u32 *regs_buff = p;
478 u8 i;
479
480 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
481
482 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
483
484 /* General Registers */
485 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
486 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
487 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
488 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
489 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
490 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
491 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
492 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
493
494 /* NVM Register */
495 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
496 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
497 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
498 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
499 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
500 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
501 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
502 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
503 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
504 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
505
506 /* Interrupt */
98c00a1c
JB		 507 /* don't read EICR because it can clear interrupt causes, instead
508 * read EICS which is a shadow but doesn't clear EICR */
509 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
9a799d71
AK		 510 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
511 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
512 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
513 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
514 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
515 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
516 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
517 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
518 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
c44ade9e 519 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
9a799d71
AK		 520 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
521
522 /* Flow Control */
523 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
524 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
525 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
526 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
527 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
528 for (i = 0; i < 8; i++)
529 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
530 for (i = 0; i < 8; i++)
531 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
532 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
533 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
534
535 /* Receive DMA */
536 for (i = 0; i < 64; i++)
537 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
538 for (i = 0; i < 64; i++)
539 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
540 for (i = 0; i < 64; i++)
541 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
542 for (i = 0; i < 64; i++)
543 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
544 for (i = 0; i < 64; i++)
545 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
546 for (i = 0; i < 64; i++)
547 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
548 for (i = 0; i < 16; i++)
549 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
550 for (i = 0; i < 16; i++)
551 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
552 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
553 for (i = 0; i < 8; i++)
554 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
555 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
556 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
557
558 /* Receive */
559 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
560 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
561 for (i = 0; i < 16; i++)
562 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
563 for (i = 0; i < 16; i++)
564 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
c44ade9e 565 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
9a799d71
AK		 566 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
567 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
568 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
569 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
570 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
571 for (i = 0; i < 8; i++)
572 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
573 for (i = 0; i < 8; i++)
574 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
575 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
576
577 /* Transmit */
578 for (i = 0; i < 32; i++)
579 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
580 for (i = 0; i < 32; i++)
581 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
582 for (i = 0; i < 32; i++)
583 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
584 for (i = 0; i < 32; i++)
585 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
586 for (i = 0; i < 32; i++)
587 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
588 for (i = 0; i < 32; i++)
589 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
590 for (i = 0; i < 32; i++)
591 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
592 for (i = 0; i < 32; i++)
593 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
594 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
595 for (i = 0; i < 16; i++)
596 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
597 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
598 for (i = 0; i < 8; i++)
599 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
600 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
601
602 /* Wake Up */
603 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
604 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
605 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
606 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
607 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
608 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
609 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
610 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
11afc1b1 611 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
9a799d71 612
9a799d71
AK		 613 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
614 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
615 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
616 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
617 for (i = 0; i < 8; i++)
618 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
619 for (i = 0; i < 8; i++)
620 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
621 for (i = 0; i < 8; i++)
622 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
623 for (i = 0; i < 8; i++)
624 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
625 for (i = 0; i < 8; i++)
626 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
627 for (i = 0; i < 8; i++)
628 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
629
630 /* Statistics */
631 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
632 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
633 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
634 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
635 for (i = 0; i < 8; i++)
636 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
637 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
638 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
639 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
640 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
641 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
642 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
643 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
644 for (i = 0; i < 8; i++)
645 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
646 for (i = 0; i < 8; i++)
647 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
648 for (i = 0; i < 8; i++)
649 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
650 for (i = 0; i < 8; i++)
651 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
652 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
653 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
654 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
655 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
656 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
657 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
658 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
659 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
660 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
661 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
662 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
663 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
664 for (i = 0; i < 8; i++)
665 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
666 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
667 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
668 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
669 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
670 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
671 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
672 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
673 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
674 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
675 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
676 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
677 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
678 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
679 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
680 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
681 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
682 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
683 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
684 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
685 for (i = 0; i < 16; i++)
686 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
687 for (i = 0; i < 16; i++)
688 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
689 for (i = 0; i < 16; i++)
690 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
691 for (i = 0; i < 16; i++)
692 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
693
694 /* MAC */
695 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
696 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
697 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
698 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
699 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
700 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
701 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
702 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
703 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
704 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
705 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
706 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
707 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
708 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
709 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
710 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
711 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
712 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
713 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
714 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
715 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
716 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
717 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
718 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
719 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
720 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
721 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
722 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
723 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
724 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
725 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
726 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
727 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
728
729 /* Diagnostic */
730 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
731 for (i = 0; i < 8; i++)
98c00a1c 732 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
9a799d71 733 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
98c00a1c
JB		 734 for (i = 0; i < 4; i++)
735 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
9a799d71
AK		 736 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
737 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
738 for (i = 0; i < 8; i++)
98c00a1c 739 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
9a799d71 740 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
98c00a1c
JB		 741 for (i = 0; i < 4; i++)
742 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
9a799d71
AK		 743 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
744 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
745 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
746 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
747 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
748 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
749 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
750 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
751 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
752 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
753 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
754 for (i = 0; i < 8; i++)
98c00a1c 755 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
9a799d71
AK		 756 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
757 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
758 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
759 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
760 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
761 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
762 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
763 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
764 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
765}
766
767static int ixgbe_get_eeprom_len(struct net_device *netdev)
768{
769 struct ixgbe_adapter *adapter = netdev_priv(netdev);
770 return adapter->hw.eeprom.word_size * 2;
771}
772
773static int ixgbe_get_eeprom(struct net_device *netdev,
b4617240 774 struct ethtool_eeprom *eeprom, u8 *bytes)
9a799d71
AK		 775{
776 struct ixgbe_adapter *adapter = netdev_priv(netdev);
777 struct ixgbe_hw *hw = &adapter->hw;
778 u16 *eeprom_buff;
779 int first_word, last_word, eeprom_len;
780 int ret_val = 0;
781 u16 i;
782
783 if (eeprom->len == 0)
784 return -EINVAL;
785
786 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
787
788 first_word = eeprom->offset >> 1;
789 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
790 eeprom_len = last_word - first_word + 1;
791
792 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
793 if (!eeprom_buff)
794 return -ENOMEM;
795
796 for (i = 0; i < eeprom_len; i++) {
c44ade9e 797 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
b4617240 798 &eeprom_buff[i])))
9a799d71
AK		 799 break;
800 }
801
802 /* Device's eeprom is always little-endian, word addressable */
803 for (i = 0; i < eeprom_len; i++)
804 le16_to_cpus(&eeprom_buff[i]);
805
806 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
807 kfree(eeprom_buff);
808
809 return ret_val;
810}
811
812static void ixgbe_get_drvinfo(struct net_device *netdev,
b4617240 813 struct ethtool_drvinfo *drvinfo)
9a799d71
AK		 814{
815 struct ixgbe_adapter *adapter = netdev_priv(netdev);
34b0368c 816 char firmware_version[32];
9a799d71
AK		 817
818 strncpy(drvinfo->driver, ixgbe_driver_name, 32);
819 strncpy(drvinfo->version, ixgbe_driver_version, 32);
34b0368c
PWJ		 820
821 sprintf(firmware_version, "%d.%d-%d",
822 (adapter->eeprom_version & 0xF000) >> 12,
823 (adapter->eeprom_version & 0x0FF0) >> 4,
824 adapter->eeprom_version & 0x000F);
825
826 strncpy(drvinfo->fw_version, firmware_version, 32);
9a799d71
AK		 827 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
828 drvinfo->n_stats = IXGBE_STATS_LEN;
da4dd0f7 829 drvinfo->testinfo_len = IXGBE_TEST_LEN;
9a799d71
AK		 830 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
831}
832
833static void ixgbe_get_ringparam(struct net_device *netdev,
b4617240 834 struct ethtool_ringparam *ring)
9a799d71
AK		 835{
836 struct ixgbe_adapter *adapter = netdev_priv(netdev);
837 struct ixgbe_ring *tx_ring = adapter->tx_ring;
838 struct ixgbe_ring *rx_ring = adapter->rx_ring;
839
840 ring->rx_max_pending = IXGBE_MAX_RXD;
841 ring->tx_max_pending = IXGBE_MAX_TXD;
842 ring->rx_mini_max_pending = 0;
843 ring->rx_jumbo_max_pending = 0;
844 ring->rx_pending = rx_ring->count;
845 ring->tx_pending = tx_ring->count;
846 ring->rx_mini_pending = 0;
847 ring->rx_jumbo_pending = 0;
848}
849
850static int ixgbe_set_ringparam(struct net_device *netdev,
b4617240 851 struct ethtool_ringparam *ring)
9a799d71
AK		 852{
853 struct ixgbe_adapter *adapter = netdev_priv(netdev);
f9ed8854 854 struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
759884b4 855 int i, err = 0;
c431f97e 856 u32 new_rx_count, new_tx_count;
f9ed8854 857 bool need_update = false;
9a799d71
AK		 858
859 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
860 return -EINVAL;
861
862 new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
863 new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
864 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
865
866 new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
867 new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
868 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
869
870 if ((new_tx_count == adapter->tx_ring->count) &&
871 (new_rx_count == adapter->rx_ring->count)) {
872 /* nothing to do */
873 return 0;
874 }
875
d4f80882
AV		 876 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
877 msleep(1);
878
759884b4
AD		 879 if (!netif_running(adapter->netdev)) {
880 for (i = 0; i < adapter->num_tx_queues; i++)
881 adapter->tx_ring[i].count = new_tx_count;
882 for (i = 0; i < adapter->num_rx_queues; i++)
883 adapter->rx_ring[i].count = new_rx_count;
884 adapter->tx_ring_count = new_tx_count;
885 adapter->rx_ring_count = new_rx_count;
886 goto err_setup;
887 }
888
f9ed8854
MC		 889 temp_tx_ring = kcalloc(adapter->num_tx_queues,
890 sizeof(struct ixgbe_ring), GFP_KERNEL);
891 if (!temp_tx_ring) {
892 err = -ENOMEM;
893 goto err_setup;
894 }
895
896 if (new_tx_count != adapter->tx_ring_count) {
897 memcpy(temp_tx_ring, adapter->tx_ring,
898 adapter->num_tx_queues * sizeof(struct ixgbe_ring));
9a799d71 899 for (i = 0; i < adapter->num_tx_queues; i++) {
f9ed8854
MC		 900 temp_tx_ring[i].count = new_tx_count;
901 err = ixgbe_setup_tx_resources(adapter,
902 &temp_tx_ring[i]);
9a799d71 903 if (err) {
c431f97e
JB		 904 while (i) {
905 i--;
b4617240 906 ixgbe_free_tx_resources(adapter,
f9ed8854 907 &temp_tx_ring[i]);
c431f97e 908 }
9a799d71
AK		 909 goto err_setup;
910 }
9a799d71 911 }
f9ed8854 912 need_update = true;
9a799d71
AK		 913 }
914
f9ed8854
MC		 915 temp_rx_ring = kcalloc(adapter->num_rx_queues,
916 sizeof(struct ixgbe_ring), GFP_KERNEL);
917 if ((!temp_rx_ring) && (need_update)) {
918 for (i = 0; i < adapter->num_tx_queues; i++)
919 ixgbe_free_tx_resources(adapter, &temp_tx_ring[i]);
920 kfree(temp_tx_ring);
921 err = -ENOMEM;
922 goto err_setup;
d3fa4721 923 }
9a799d71 924
f9ed8854
MC		 925 if (new_rx_count != adapter->rx_ring_count) {
926 memcpy(temp_rx_ring, adapter->rx_ring,
927 adapter->num_rx_queues * sizeof(struct ixgbe_ring));
c431f97e 928 for (i = 0; i < adapter->num_rx_queues; i++) {
f9ed8854
MC		 929 temp_rx_ring[i].count = new_rx_count;
930 err = ixgbe_setup_rx_resources(adapter,
931 &temp_rx_ring[i]);
9a799d71 932 if (err) {
c431f97e
JB		 933 while (i) {
934 i--;
b4617240 935 ixgbe_free_rx_resources(adapter,
f9ed8854 936 &temp_rx_ring[i]);
c431f97e 937 }
9a799d71
AK		 938 goto err_setup;
939 }
9a799d71 940 }
f9ed8854
MC		 941 need_update = true;
942 }
943
944 /* if rings need to be updated, here's the place to do it in one shot */
945 if (need_update) {
759884b4 946 ixgbe_down(adapter);
f9ed8854
MC		 947
948 /* tx */
949 if (new_tx_count != adapter->tx_ring_count) {
950 kfree(adapter->tx_ring);
951 adapter->tx_ring = temp_tx_ring;
952 temp_tx_ring = NULL;
953 adapter->tx_ring_count = new_tx_count;
954 }
955
956 /* rx */
957 if (new_rx_count != adapter->rx_ring_count) {
958 kfree(adapter->rx_ring);
959 adapter->rx_ring = temp_rx_ring;
960 temp_rx_ring = NULL;
961 adapter->rx_ring_count = new_rx_count;
962 }
f9ed8854 963 ixgbe_up(adapter);
759884b4 964 }
f9ed8854 965err_setup:
d4f80882 966 clear_bit(__IXGBE_RESETTING, &adapter->state);
9a799d71
AK		 967 return err;
968}
969
b9f2c044 970static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
9a799d71 971{
b9f2c044 972 switch (sset) {
da4dd0f7
PWJ		 973 case ETH_SS_TEST:
974 return IXGBE_TEST_LEN;
b9f2c044
JG		 975 case ETH_SS_STATS:
976 return IXGBE_STATS_LEN;
977 default:
978 return -EOPNOTSUPP;
979 }
9a799d71
AK		 980}
981
982static void ixgbe_get_ethtool_stats(struct net_device *netdev,
b4617240 983 struct ethtool_stats *stats, u64 *data)
9a799d71
AK		 984{
985 struct ixgbe_adapter *adapter = netdev_priv(netdev);
986 u64 *queue_stat;
987 int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
988 int j, k;
989 int i;
29c3a050 990 char *p = NULL;
9a799d71
AK		 991
992 ixgbe_update_stats(adapter);
993 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
29c3a050
AK		 994 switch (ixgbe_gstrings_stats[i].type) {
995 case NETDEV_STATS:
996 p = (char *) netdev +
997 ixgbe_gstrings_stats[i].stat_offset;
998 break;
999 case IXGBE_STATS:
1000 p = (char *) adapter +
1001 ixgbe_gstrings_stats[i].stat_offset;
1002 break;
1003 }
1004
9a799d71 1005 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
b4617240 1006 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
9a799d71
AK		 1007 }
1008 for (j = 0; j < adapter->num_tx_queues; j++) {
1009 queue_stat = (u64 *)&adapter->tx_ring[j].stats;
1010 for (k = 0; k < stat_count; k++)
1011 data[i + k] = queue_stat[k];
1012 i += k;
1013 }
1014 for (j = 0; j < adapter->num_rx_queues; j++) {
1015 queue_stat = (u64 *)&adapter->rx_ring[j].stats;
1016 for (k = 0; k < stat_count; k++)
1017 data[i + k] = queue_stat[k];
1018 i += k;
1019 }
2f90b865
AD		 1020 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1021 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
1022 data[i++] = adapter->stats.pxontxc[j];
1023 data[i++] = adapter->stats.pxofftxc[j];
1024 }
1025 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
1026 data[i++] = adapter->stats.pxonrxc[j];
1027 data[i++] = adapter->stats.pxoffrxc[j];
1028 }
1029 }
9a799d71
AK		 1030}
1031
1032static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
b4617240 1033 u8 *data)
9a799d71
AK		 1034{
1035 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1036 char *p = (char *)data;
9a799d71
AK		 1037 int i;
1038
1039 switch (stringset) {
da4dd0f7
PWJ		 1040 case ETH_SS_TEST:
1041 memcpy(data, *ixgbe_gstrings_test,
1042 IXGBE_TEST_LEN * ETH_GSTRING_LEN);
1043 break;
9a799d71
AK		 1044 case ETH_SS_STATS:
1045 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1046 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1047 ETH_GSTRING_LEN);
1048 p += ETH_GSTRING_LEN;
1049 }
1050 for (i = 0; i < adapter->num_tx_queues; i++) {
1051 sprintf(p, "tx_queue_%u_packets", i);
1052 p += ETH_GSTRING_LEN;
1053 sprintf(p, "tx_queue_%u_bytes", i);
1054 p += ETH_GSTRING_LEN;
1055 }
1056 for (i = 0; i < adapter->num_rx_queues; i++) {
1057 sprintf(p, "rx_queue_%u_packets", i);
1058 p += ETH_GSTRING_LEN;
1059 sprintf(p, "rx_queue_%u_bytes", i);
1060 p += ETH_GSTRING_LEN;
1061 }
2f90b865
AD		 1062 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1063 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
1064 sprintf(p, "tx_pb_%u_pxon", i);
bfb8cc31
DS		 1065 p += ETH_GSTRING_LEN;
1066 sprintf(p, "tx_pb_%u_pxoff", i);
1067 p += ETH_GSTRING_LEN;
2f90b865
AD		 1068 }
1069 for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
bfb8cc31
DS		 1070 sprintf(p, "rx_pb_%u_pxon", i);
1071 p += ETH_GSTRING_LEN;
1072 sprintf(p, "rx_pb_%u_pxoff", i);
1073 p += ETH_GSTRING_LEN;
2f90b865
AD		 1074 }
1075 }
b4617240 1076 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
9a799d71
AK		 1077 break;
1078 }
1079}
1080
da4dd0f7
PWJ		 1081static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1082{
1083 struct ixgbe_hw *hw = &adapter->hw;
1084 bool link_up;
1085 u32 link_speed = 0;
1086 *data = 0;
1087
1088 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1089 if (link_up)
1090 return *data;
1091 else
1092 *data = 1;
1093 return *data;
1094}
1095
1096/* ethtool register test data */
1097struct ixgbe_reg_test {
1098 u16 reg;
1099 u8 array_len;
1100 u8 test_type;
1101 u32 mask;
1102 u32 write;
1103};
1104
1105/* In the hardware, registers are laid out either singly, in arrays
1106 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1107 * most tests take place on arrays or single registers (handled
1108 * as a single-element array) and special-case the tables.
1109 * Table tests are always pattern tests.
1110 *
1111 * We also make provision for some required setup steps by specifying
1112 * registers to be written without any read-back testing.
1113 */
1114
1115#define PATTERN_TEST 1
1116#define SET_READ_TEST 2
1117#define WRITE_NO_TEST 3
1118#define TABLE32_TEST 4
1119#define TABLE64_TEST_LO 5
1120#define TABLE64_TEST_HI 6
1121
1122/* default 82599 register test */
1123static struct ixgbe_reg_test reg_test_82599[] = {
1124 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1125 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1126 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1127 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1128 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1129 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1130 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1131 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1132 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1133 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1134 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1135 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1136 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1137 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1138 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1139 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1140 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1141 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1142 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1143 { 0, 0, 0, 0 }
1144};
1145
1146/* default 82598 register test */
1147static struct ixgbe_reg_test reg_test_82598[] = {
1148 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1149 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1150 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1151 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1152 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1153 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1154 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1155 /* Enable all four RX queues before testing. */
1156 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1157 /* RDH is read-only for 82598, only test RDT. */
1158 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1159 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1160 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1161 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1162 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1163 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1164 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1165 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1166 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1167 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1168 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1169 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1170 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1171 { 0, 0, 0, 0 }
1172};
1173
1174#define REG_PATTERN_TEST(R, M, W) \
1175{ \
1176 u32 pat, val, before; \
1177 const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1178 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { \
1179 before = readl(adapter->hw.hw_addr + R); \
1180 writel((_test[pat] & W), (adapter->hw.hw_addr + R)); \
1181 val = readl(adapter->hw.hw_addr + R); \
1182 if (val != (_test[pat] & W & M)) { \
1183 DPRINTK(DRV, ERR, "pattern test reg %04X failed: got "\
1184 "0x%08X expected 0x%08X\n", \
1185 R, val, (_test[pat] & W & M)); \
1186 *data = R; \
1187 writel(before, adapter->hw.hw_addr + R); \
1188 return 1; \
1189 } \
1190 writel(before, adapter->hw.hw_addr + R); \
1191 } \
1192}
1193
1194#define REG_SET_AND_CHECK(R, M, W) \
1195{ \
1196 u32 val, before; \
1197 before = readl(adapter->hw.hw_addr + R); \
1198 writel((W & M), (adapter->hw.hw_addr + R)); \
1199 val = readl(adapter->hw.hw_addr + R); \
1200 if ((W & M) != (val & M)) { \
1201 DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\
1202 "expected 0x%08X\n", R, (val & M), (W & M)); \
1203 *data = R; \
1204 writel(before, (adapter->hw.hw_addr + R)); \
1205 return 1; \
1206 } \
1207 writel(before, (adapter->hw.hw_addr + R)); \
1208}
1209
1210static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1211{
1212 struct ixgbe_reg_test *test;
1213 u32 value, before, after;
1214 u32 i, toggle;
1215
1216 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1217 toggle = 0x7FFFF30F;
1218 test = reg_test_82599;
1219 } else {
1220 toggle = 0x7FFFF3FF;
1221 test = reg_test_82598;
1222 }
1223
1224 /*
1225 * Because the status register is such a special case,
1226 * we handle it separately from the rest of the register
1227 * tests. Some bits are read-only, some toggle, and some
1228 * are writeable on newer MACs.
1229 */
1230 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1231 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1232 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1233 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1234 if (value != after) {
1235 DPRINTK(DRV, ERR, "failed STATUS register test got: "
1236 "0x%08X expected: 0x%08X\n", after, value);
1237 *data = 1;
1238 return 1;
1239 }
1240 /* restore previous status */
1241 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1242
1243 /*
1244 * Perform the remainder of the register test, looping through
1245 * the test table until we either fail or reach the null entry.
1246 */
1247 while (test->reg) {
1248 for (i = 0; i < test->array_len; i++) {
1249 switch (test->test_type) {
1250 case PATTERN_TEST:
1251 REG_PATTERN_TEST(test->reg + (i * 0x40),
1252 test->mask,
1253 test->write);
1254 break;
1255 case SET_READ_TEST:
1256 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1257 test->mask,
1258 test->write);
1259 break;
1260 case WRITE_NO_TEST:
1261 writel(test->write,
1262 (adapter->hw.hw_addr + test->reg)
1263 + (i * 0x40));
1264 break;
1265 case TABLE32_TEST:
1266 REG_PATTERN_TEST(test->reg + (i * 4),
1267 test->mask,
1268 test->write);
1269 break;
1270 case TABLE64_TEST_LO:
1271 REG_PATTERN_TEST(test->reg + (i * 8),
1272 test->mask,
1273 test->write);
1274 break;
1275 case TABLE64_TEST_HI:
1276 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1277 test->mask,
1278 test->write);
1279 break;
1280 }
1281 }
1282 test++;
1283 }
1284
1285 *data = 0;
1286 return 0;
1287}
1288
1289static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1290{
1291 struct ixgbe_hw *hw = &adapter->hw;
1292 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1293 *data = 1;
1294 else
1295 *data = 0;
1296 return *data;
1297}
1298
1299static irqreturn_t ixgbe_test_intr(int irq, void *data)
1300{
1301 struct net_device *netdev = (struct net_device *) data;
1302 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1303
1304 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1305
1306 return IRQ_HANDLED;
1307}
1308
1309static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1310{
1311 struct net_device *netdev = adapter->netdev;
1312 u32 mask, i = 0, shared_int = true;
1313 u32 irq = adapter->pdev->irq;
1314
1315 *data = 0;
1316
1317 /* Hook up test interrupt handler just for this test */
1318 if (adapter->msix_entries) {
1319 /* NOTE: we don't test MSI-X interrupts here, yet */
1320 return 0;
1321 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1322 shared_int = false;
a0607fd3 1323 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
da4dd0f7
PWJ		 1324 netdev)) {
1325 *data = 1;
1326 return -1;
1327 }
a0607fd3 1328 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
da4dd0f7
PWJ		 1329 netdev->name, netdev)) {
1330 shared_int = false;
a0607fd3 1331 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
da4dd0f7
PWJ		 1332 netdev->name, netdev)) {
1333 *data = 1;
1334 return -1;
1335 }
1336 DPRINTK(HW, INFO, "testing %s interrupt\n",
1337 (shared_int ? "shared" : "unshared"));
1338
1339 /* Disable all the interrupts */
1340 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1341 msleep(10);
1342
1343 /* Test each interrupt */
1344 for (; i < 10; i++) {
1345 /* Interrupt to test */
1346 mask = 1 << i;
1347
1348 if (!shared_int) {
1349 /*
1350 * Disable the interrupts to be reported in
1351 * the cause register and then force the same
1352 * interrupt and see if one gets posted. If
1353 * an interrupt was posted to the bus, the
1354 * test failed.
1355 */
1356 adapter->test_icr = 0;
1357 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1358 ~mask & 0x00007FFF);
1359 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1360 ~mask & 0x00007FFF);
1361 msleep(10);
1362
1363 if (adapter->test_icr & mask) {
1364 *data = 3;
1365 break;
1366 }
1367 }
1368
1369 /*
1370 * Enable the interrupt to be reported in the cause
1371 * register and then force the same interrupt and see
1372 * if one gets posted. If an interrupt was not posted
1373 * to the bus, the test failed.
1374 */
1375 adapter->test_icr = 0;
1376 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1377 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1378 msleep(10);
1379
1380 if (!(adapter->test_icr &mask)) {
1381 *data = 4;
1382 break;
1383 }
1384
1385 if (!shared_int) {
1386 /*
1387 * Disable the other interrupts to be reported in
1388 * the cause register and then force the other
1389 * interrupts and see if any get posted. If
1390 * an interrupt was posted to the bus, the
1391 * test failed.
1392 */
1393 adapter->test_icr = 0;
1394 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1395 ~mask & 0x00007FFF);
1396 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1397 ~mask & 0x00007FFF);
1398 msleep(10);
1399
1400 if (adapter->test_icr) {
1401 *data = 5;
1402 break;
1403 }
1404 }
1405 }
1406
1407 /* Disable all the interrupts */
1408 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1409 msleep(10);
1410
1411 /* Unhook test interrupt handler */
1412 free_irq(irq, netdev);
1413
1414 return *data;
1415}
1416
1417static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1418{
1419 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1420 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1421 struct ixgbe_hw *hw = &adapter->hw;
1422 struct pci_dev *pdev = adapter->pdev;
1423 u32 reg_ctl;
1424 int i;
1425
1426 /* shut down the DMA engines now so they can be reinitialized later */
1427
1428 /* first Rx */
1429 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1430 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1431 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1432 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(0));
1433 reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
1434 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(0), reg_ctl);
1435
1436 /* now Tx */
1437 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(0));
1438 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1439 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(0), reg_ctl);
1440 if (hw->mac.type == ixgbe_mac_82599EB) {
1441 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1442 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1443 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1444 }
1445
1446 ixgbe_reset(adapter);
1447
1448 if (tx_ring->desc && tx_ring->tx_buffer_info) {
1449 for (i = 0; i < tx_ring->count; i++) {
1450 struct ixgbe_tx_buffer *buf =
1451 &(tx_ring->tx_buffer_info[i]);
1452 if (buf->dma)
1453 pci_unmap_single(pdev, buf->dma, buf->length,
1454 PCI_DMA_TODEVICE);
1455 if (buf->skb)
1456 dev_kfree_skb(buf->skb);
1457 }
1458 }
1459
1460 if (rx_ring->desc && rx_ring->rx_buffer_info) {
1461 for (i = 0; i < rx_ring->count; i++) {
1462 struct ixgbe_rx_buffer *buf =
1463 &(rx_ring->rx_buffer_info[i]);
1464 if (buf->dma)
1465 pci_unmap_single(pdev, buf->dma,
1466 IXGBE_RXBUFFER_2048,
1467 PCI_DMA_FROMDEVICE);
1468 if (buf->skb)
1469 dev_kfree_skb(buf->skb);
1470 }
1471 }
1472
1473 if (tx_ring->desc) {
1474 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1475 tx_ring->dma);
1476 tx_ring->desc = NULL;
1477 }
1478 if (rx_ring->desc) {
1479 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1480 rx_ring->dma);
1481 rx_ring->desc = NULL;
1482 }
1483
1484 kfree(tx_ring->tx_buffer_info);
1485 tx_ring->tx_buffer_info = NULL;
1486 kfree(rx_ring->rx_buffer_info);
1487 rx_ring->rx_buffer_info = NULL;
1488
1489 return;
1490}
1491
1492static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1493{
1494 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1495 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1496 struct pci_dev *pdev = adapter->pdev;
1497 u32 rctl, reg_data;
1498 int i, ret_val;
1499
1500 /* Setup Tx descriptor ring and Tx buffers */
1501
1502 if (!tx_ring->count)
1503 tx_ring->count = IXGBE_DEFAULT_TXD;
1504
1505 tx_ring->tx_buffer_info = kcalloc(tx_ring->count,
1506 sizeof(struct ixgbe_tx_buffer),
1507 GFP_KERNEL);
1508 if (!(tx_ring->tx_buffer_info)) {
1509 ret_val = 1;
1510 goto err_nomem;
1511 }
1512
f4ec443b 1513 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
da4dd0f7
PWJ		 1514 tx_ring->size = ALIGN(tx_ring->size, 4096);
1515 if (!(tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1516 &tx_ring->dma))) {
1517 ret_val = 2;
1518 goto err_nomem;
1519 }
1520 tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1521
1522 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0),
1523 ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0),
1525 ((u64) tx_ring->dma >> 32));
1526 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0),
f4ec443b 1527 tx_ring->count * sizeof(union ixgbe_adv_tx_desc));
da4dd0f7
PWJ		 1528 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0);
1529 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0);
1530
1531 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1532 reg_data |= IXGBE_HLREG0_TXPADEN;
1533 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1534
1535 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1536 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1537 reg_data |= IXGBE_DMATXCTL_TE;
1538 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1539 }
1540 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0));
1541 reg_data |= IXGBE_TXDCTL_ENABLE;
1542 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data);
1543
1544 for (i = 0; i < tx_ring->count; i++) {
f4ec443b 1545 union ixgbe_adv_tx_desc *desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
da4dd0f7
PWJ		 1546 struct sk_buff *skb;
1547 unsigned int size = 1024;
1548
1549 skb = alloc_skb(size, GFP_KERNEL);
1550 if (!skb) {
1551 ret_val = 3;
1552 goto err_nomem;
1553 }
1554 skb_put(skb, size);
1555 tx_ring->tx_buffer_info[i].skb = skb;
1556 tx_ring->tx_buffer_info[i].length = skb->len;
1557 tx_ring->tx_buffer_info[i].dma =
1558 pci_map_single(pdev, skb->data, skb->len,
f4ec443b
PWJ		 1559 PCI_DMA_TODEVICE);
1560 desc->read.buffer_addr =
1561 cpu_to_le64(tx_ring->tx_buffer_info[i].dma);
1562 desc->read.cmd_type_len = cpu_to_le32(skb->len);
1563 desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD_EOP |
1564 IXGBE_TXD_CMD_IFCS |
1565 IXGBE_TXD_CMD_RS);
1566 desc->read.olinfo_status = 0;
1567 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1568 desc->read.olinfo_status |=
1569 (skb->len << IXGBE_ADVTXD_PAYLEN_SHIFT);
1570
da4dd0f7
PWJ		 1571 }
1572
1573 /* Setup Rx Descriptor ring and Rx buffers */
1574
1575 if (!rx_ring->count)
1576 rx_ring->count = IXGBE_DEFAULT_RXD;
1577
1578 rx_ring->rx_buffer_info = kcalloc(rx_ring->count,
1579 sizeof(struct ixgbe_rx_buffer),
1580 GFP_KERNEL);
1581 if (!(rx_ring->rx_buffer_info)) {
1582 ret_val = 4;
1583 goto err_nomem;
1584 }
1585
f4ec443b 1586 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
da4dd0f7
PWJ		 1587 rx_ring->size = ALIGN(rx_ring->size, 4096);
1588 if (!(rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1589 &rx_ring->dma))) {
1590 ret_val = 5;
1591 goto err_nomem;
1592 }
1593 rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1594
1595 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1596 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1597 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0),
1598 ((u64)rx_ring->dma & 0xFFFFFFFF));
1599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0),
1600 ((u64) rx_ring->dma >> 32));
1601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size);
1602 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0);
1603 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0);
1604
1605 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1606 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1608
1609 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1610 reg_data &= ~IXGBE_HLREG0_LPBK;
1611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1612
1613 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL);
1614#define IXGBE_RDRXCTL_RDMTS_MASK 0x00000003 /* Receive Descriptor Minimum
1615 Threshold Size mask */
1616 reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK;
1617 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data);
1618
1619 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL);
1620#define IXGBE_MCSTCTRL_MO_MASK 0x00000003 /* Multicast Offset mask */
1621 reg_data &= ~IXGBE_MCSTCTRL_MO_MASK;
1622 reg_data |= adapter->hw.mac.mc_filter_type;
1623 IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data);
1624
1625 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0));
1626 reg_data |= IXGBE_RXDCTL_ENABLE;
1627 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data);
1628 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1629 int j = adapter->rx_ring[0].reg_idx;
1630 u32 k;
1631 for (k = 0; k < 10; k++) {
1632 if (IXGBE_READ_REG(&adapter->hw,
1633 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1634 break;
1635 else
1636 msleep(1);
1637 }
1638 }
1639
1640 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1641 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1642
1643 for (i = 0; i < rx_ring->count; i++) {
f4ec443b
PWJ		 1644 union ixgbe_adv_rx_desc *rx_desc =
1645 IXGBE_RX_DESC_ADV(*rx_ring, i);
da4dd0f7
PWJ		 1646 struct sk_buff *skb;
1647
1648 skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
1649 if (!skb) {
1650 ret_val = 6;
1651 goto err_nomem;
1652 }
1653 skb_reserve(skb, NET_IP_ALIGN);
1654 rx_ring->rx_buffer_info[i].skb = skb;
1655 rx_ring->rx_buffer_info[i].dma =
1656 pci_map_single(pdev, skb->data, IXGBE_RXBUFFER_2048,
1657 PCI_DMA_FROMDEVICE);
f4ec443b 1658 rx_desc->read.pkt_addr =
da4dd0f7
PWJ		 1659 cpu_to_le64(rx_ring->rx_buffer_info[i].dma);
1660 memset(skb->data, 0x00, skb->len);
1661 }
1662
1663 return 0;
1664
1665err_nomem:
1666 ixgbe_free_desc_rings(adapter);
1667 return ret_val;
1668}
1669
1670static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1671{
1672 struct ixgbe_hw *hw = &adapter->hw;
1673 u32 reg_data;
1674
1675 /* right now we only support MAC loopback in the driver */
1676
1677 /* Setup MAC loopback */
1678 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1679 reg_data |= IXGBE_HLREG0_LPBK;
1680 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1681
1682 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1683 reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1684 reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
1686
1687 /* Disable Atlas Tx lanes; re-enabled in reset path */
1688 if (hw->mac.type == ixgbe_mac_82598EB) {
1689 u8 atlas;
1690
1691 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1692 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1693 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1694
1695 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1696 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1697 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1698
1699 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1700 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1701 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1702
1703 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1704 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1705 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1706 }
1707
1708 return 0;
1709}
1710
1711static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1712{
1713 u32 reg_data;
1714
1715 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1716 reg_data &= ~IXGBE_HLREG0_LPBK;
1717 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1718}
1719
1720static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1721 unsigned int frame_size)
1722{
1723 memset(skb->data, 0xFF, frame_size);
1724 frame_size &= ~1;
1725 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1726 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1727 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1728}
1729
1730static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1731 unsigned int frame_size)
1732{
1733 frame_size &= ~1;
1734 if (*(skb->data + 3) == 0xFF) {
1735 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1736 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1737 return 0;
1738 }
1739 }
1740 return 13;
1741}
1742
1743static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1744{
1745 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1746 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1747 struct pci_dev *pdev = adapter->pdev;
1748 int i, j, k, l, lc, good_cnt, ret_val = 0;
1749 unsigned long time;
1750
1751 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1);
1752
1753 /*
1754 * Calculate the loop count based on the largest descriptor ring
1755 * The idea is to wrap the largest ring a number of times using 64
1756 * send/receive pairs during each loop
1757 */
1758
1759 if (rx_ring->count <= tx_ring->count)
1760 lc = ((tx_ring->count / 64) * 2) + 1;
1761 else
1762 lc = ((rx_ring->count / 64) * 2) + 1;
1763
1764 k = l = 0;
1765 for (j = 0; j <= lc; j++) {
1766 for (i = 0; i < 64; i++) {
1767 ixgbe_create_lbtest_frame(
1768 tx_ring->tx_buffer_info[k].skb,
1769 1024);
1770 pci_dma_sync_single_for_device(pdev,
1771 tx_ring->tx_buffer_info[k].dma,
1772 tx_ring->tx_buffer_info[k].length,
1773 PCI_DMA_TODEVICE);
1774 if (unlikely(++k == tx_ring->count))
1775 k = 0;
1776 }
1777 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k);
1778 msleep(200);
1779 /* set the start time for the receive */
1780 time = jiffies;
1781 good_cnt = 0;
1782 do {
1783 /* receive the sent packets */
1784 pci_dma_sync_single_for_cpu(pdev,
1785 rx_ring->rx_buffer_info[l].dma,
1786 IXGBE_RXBUFFER_2048,
1787 PCI_DMA_FROMDEVICE);
1788 ret_val = ixgbe_check_lbtest_frame(
1789 rx_ring->rx_buffer_info[l].skb, 1024);
1790 if (!ret_val)
1791 good_cnt++;
1792 if (++l == rx_ring->count)
1793 l = 0;
1794 /*
1795 * time + 20 msecs (200 msecs on 2.4) is more than
1796 * enough time to complete the receives, if it's
1797 * exceeded, break and error off
1798 */
1799 } while (good_cnt < 64 && jiffies < (time + 20));
1800 if (good_cnt != 64) {
1801 /* ret_val is the same as mis-compare */
1802 ret_val = 13;
1803 break;
1804 }
1805 if (jiffies >= (time + 20)) {
1806 /* Error code for time out error */
1807 ret_val = 14;
1808 break;
1809 }
1810 }
1811
1812 return ret_val;
1813}
1814
1815static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1816{
1817 *data = ixgbe_setup_desc_rings(adapter);
1818 if (*data)
1819 goto out;
1820 *data = ixgbe_setup_loopback_test(adapter);
1821 if (*data)
1822 goto err_loopback;
1823 *data = ixgbe_run_loopback_test(adapter);
1824 ixgbe_loopback_cleanup(adapter);
1825
1826err_loopback:
1827 ixgbe_free_desc_rings(adapter);
1828out:
1829 return *data;
1830}
1831
1832static void ixgbe_diag_test(struct net_device *netdev,
1833 struct ethtool_test *eth_test, u64 *data)
1834{
1835 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1836 bool if_running = netif_running(netdev);
1837
1838 set_bit(__IXGBE_TESTING, &adapter->state);
1839 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1840 /* Offline tests */
1841
1842 DPRINTK(HW, INFO, "offline testing starting\n");
1843
1844 /* Link test performed before hardware reset so autoneg doesn't
1845 * interfere with test result */
1846 if (ixgbe_link_test(adapter, &data[4]))
1847 eth_test->flags |= ETH_TEST_FL_FAILED;
1848
1849 if (if_running)
1850 /* indicate we're in test mode */
1851 dev_close(netdev);
1852 else
1853 ixgbe_reset(adapter);
1854
1855 DPRINTK(HW, INFO, "register testing starting\n");
1856 if (ixgbe_reg_test(adapter, &data[0]))
1857 eth_test->flags |= ETH_TEST_FL_FAILED;
1858
1859 ixgbe_reset(adapter);
1860 DPRINTK(HW, INFO, "eeprom testing starting\n");
1861 if (ixgbe_eeprom_test(adapter, &data[1]))
1862 eth_test->flags |= ETH_TEST_FL_FAILED;
1863
1864 ixgbe_reset(adapter);
1865 DPRINTK(HW, INFO, "interrupt testing starting\n");
1866 if (ixgbe_intr_test(adapter, &data[2]))
1867 eth_test->flags |= ETH_TEST_FL_FAILED;
1868
1869 ixgbe_reset(adapter);
1870 DPRINTK(HW, INFO, "loopback testing starting\n");
1871 if (ixgbe_loopback_test(adapter, &data[3]))
1872 eth_test->flags |= ETH_TEST_FL_FAILED;
1873
1874 ixgbe_reset(adapter);
1875
1876 clear_bit(__IXGBE_TESTING, &adapter->state);
1877 if (if_running)
1878 dev_open(netdev);
1879 } else {
1880 DPRINTK(HW, INFO, "online testing starting\n");
1881 /* Online tests */
1882 if (ixgbe_link_test(adapter, &data[4]))
1883 eth_test->flags |= ETH_TEST_FL_FAILED;
1884
1885 /* Online tests aren't run; pass by default */
1886 data[0] = 0;
1887 data[1] = 0;
1888 data[2] = 0;
1889 data[3] = 0;
1890
1891 clear_bit(__IXGBE_TESTING, &adapter->state);
1892 }
1893 msleep_interruptible(4 * 1000);
1894}
9a799d71 1895
d6c519e1
AD		 1896static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1897 struct ethtool_wolinfo *wol)
1898{
1899 struct ixgbe_hw *hw = &adapter->hw;
1900 int retval = 1;
1901
1902 switch(hw->device_id) {
1903 case IXGBE_DEV_ID_82599_KX4:
1904 retval = 0;
1905 break;
1906 default:
1907 wol->supported = 0;
d6c519e1
AD		 1908 }
1909
1910 return retval;
1911}
1912
9a799d71 1913static void ixgbe_get_wol(struct net_device *netdev,
b4617240 1914 struct ethtool_wolinfo *wol)
9a799d71 1915{
e63d9762
PW		 1916 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1917
1918 wol->supported = WAKE_UCAST | WAKE_MCAST |
1919 WAKE_BCAST | WAKE_MAGIC;
9a799d71
AK		 1920 wol->wolopts = 0;
1921
d6c519e1
AD		 1922 if (ixgbe_wol_exclusion(adapter, wol) ||
1923 !device_can_wakeup(&adapter->pdev->dev))
e63d9762
PW		 1924 return;
1925
1926 if (adapter->wol & IXGBE_WUFC_EX)
1927 wol->wolopts |= WAKE_UCAST;
1928 if (adapter->wol & IXGBE_WUFC_MC)
1929 wol->wolopts |= WAKE_MCAST;
1930 if (adapter->wol & IXGBE_WUFC_BC)
1931 wol->wolopts |= WAKE_BCAST;
1932 if (adapter->wol & IXGBE_WUFC_MAG)
1933 wol->wolopts |= WAKE_MAGIC;
1934
9a799d71
AK		 1935 return;
1936}
1937
e63d9762
PW		 1938static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1939{
1940 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1941
1942 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1943 return -EOPNOTSUPP;
1944
d6c519e1
AD		 1945 if (ixgbe_wol_exclusion(adapter, wol))
1946 return wol->wolopts ? -EOPNOTSUPP : 0;
1947
e63d9762
PW		 1948 adapter->wol = 0;
1949
1950 if (wol->wolopts & WAKE_UCAST)
1951 adapter->wol |= IXGBE_WUFC_EX;
1952 if (wol->wolopts & WAKE_MCAST)
1953 adapter->wol |= IXGBE_WUFC_MC;
1954 if (wol->wolopts & WAKE_BCAST)
1955 adapter->wol |= IXGBE_WUFC_BC;
1956 if (wol->wolopts & WAKE_MAGIC)
1957 adapter->wol |= IXGBE_WUFC_MAG;
1958
1959 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1960
1961 return 0;
1962}
1963
9a799d71
AK		 1964static int ixgbe_nway_reset(struct net_device *netdev)
1965{
1966 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1967
d4f80882
AV		 1968 if (netif_running(netdev))
1969 ixgbe_reinit_locked(adapter);
9a799d71
AK		 1970
1971 return 0;
1972}
1973
1974static int ixgbe_phys_id(struct net_device *netdev, u32 data)
1975{
1976 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e
JB		 1977 struct ixgbe_hw *hw = &adapter->hw;
1978 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
9a799d71
AK		 1979 u32 i;
1980
1981 if (!data || data > 300)
1982 data = 300;
1983
1984 for (i = 0; i < (data * 1000); i += 400) {
c44ade9e 1985 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
9a799d71 1986 msleep_interruptible(200);
c44ade9e 1987 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
9a799d71
AK		 1988 msleep_interruptible(200);
1989 }
1990
1991 /* Restore LED settings */
1992 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
1993
1994 return 0;
1995}
1996
1997static int ixgbe_get_coalesce(struct net_device *netdev,
b4617240 1998 struct ethtool_coalesce *ec)
9a799d71
AK		 1999{
2000 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2001
9a799d71 2002 ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0].work_limit;
30efa5a3
JB		 2003
2004 /* only valid if in constant ITR mode */
f7554a2b 2005 switch (adapter->rx_itr_setting) {
30efa5a3
JB		 2006 case 0:
2007 /* throttling disabled */
2008 ec->rx_coalesce_usecs = 0;
2009 break;
2010 case 1:
2011 /* dynamic ITR mode */
2012 ec->rx_coalesce_usecs = 1;
2013 break;
2014 default:
2015 /* fixed interrupt rate mode */
f7554a2b 2016 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
30efa5a3
JB		 2017 break;
2018 }
f7554a2b 2019
cfb3f91a
SN		 2020 /* if in mixed tx/rx queues per vector mode, report only rx settings */
2021 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count)
2022 return 0;
2023
f7554a2b
NS		 2024 /* only valid if in constant ITR mode */
2025 switch (adapter->tx_itr_setting) {
2026 case 0:
2027 /* throttling disabled */
2028 ec->tx_coalesce_usecs = 0;
2029 break;
2030 case 1:
2031 /* dynamic ITR mode */
2032 ec->tx_coalesce_usecs = 1;
2033 break;
2034 default:
2035 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
2036 break;
2037 }
2038
9a799d71
AK		 2039 return 0;
2040}
2041
2042static int ixgbe_set_coalesce(struct net_device *netdev,
b4617240 2043 struct ethtool_coalesce *ec)
9a799d71
AK		 2044{
2045 struct ixgbe_adapter *adapter = netdev_priv(netdev);
237057ad 2046 struct ixgbe_q_vector *q_vector;
30efa5a3 2047 int i;
9a799d71 2048
cfb3f91a
SN		 2049 /* don't accept tx specific changes if we've got mixed RxTx vectors */
2050 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count
2051 && ec->tx_coalesce_usecs)
f7554a2b
NS		 2052 return -EINVAL;
2053
9a799d71 2054 if (ec->tx_max_coalesced_frames_irq)
30efa5a3
JB		 2055 adapter->tx_ring[0].work_limit = ec->tx_max_coalesced_frames_irq;
2056
2057 if (ec->rx_coalesce_usecs > 1) {
509ee935
JB		 2058 /* check the limits */
2059 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2060 (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2061 return -EINVAL;
2062
30efa5a3 2063 /* store the value in ints/second */
f7554a2b 2064 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
30efa5a3
JB		 2065
2066 /* static value of interrupt rate */
f7554a2b 2067 adapter->rx_itr_setting = adapter->rx_eitr_param;
509ee935 2068 /* clear the lower bit as its used for dynamic state */
f7554a2b 2069 adapter->rx_itr_setting &= ~1;
30efa5a3
JB		 2070 } else if (ec->rx_coalesce_usecs == 1) {
2071 /* 1 means dynamic mode */
f7554a2b
NS		 2072 adapter->rx_eitr_param = 20000;
2073 adapter->rx_itr_setting = 1;
30efa5a3 2074 } else {
509ee935
JB		 2075 /*
2076 * any other value means disable eitr, which is best
2077 * served by setting the interrupt rate very high
2078 */
0a924578 2079 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f7554a2b 2080 adapter->rx_eitr_param = IXGBE_MAX_RSC_INT_RATE;
0a924578 2081 else
f7554a2b
NS		 2082 adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
2083 adapter->rx_itr_setting = 0;
2084 }
2085
2086 if (ec->tx_coalesce_usecs > 1) {
2087 /* check the limits */
2088 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2089 (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2090 return -EINVAL;
2091
2092 /* store the value in ints/second */
2093 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2094
2095 /* static value of interrupt rate */
2096 adapter->tx_itr_setting = adapter->tx_eitr_param;
2097
2098 /* clear the lower bit as its used for dynamic state */
2099 adapter->tx_itr_setting &= ~1;
2100 } else if (ec->tx_coalesce_usecs == 1) {
2101 /* 1 means dynamic mode */
2102 adapter->tx_eitr_param = 10000;
2103 adapter->tx_itr_setting = 1;
2104 } else {
2105 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2106 adapter->tx_itr_setting = 0;
30efa5a3 2107 }
9a799d71 2108
237057ad
DS		 2109 /* MSI/MSIx Interrupt Mode */
2110 if (adapter->flags &
2111 (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2112 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2113 for (i = 0; i < num_vectors; i++) {
2114 q_vector = adapter->q_vector[i];
2115 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 2116 /* tx only */
2117 q_vector->eitr = adapter->tx_eitr_param;
237057ad
DS		 2118 else
2119 /* rx only or mixed */
f7554a2b 2120 q_vector->eitr = adapter->rx_eitr_param;
237057ad
DS		 2121 ixgbe_write_eitr(q_vector);
2122 }
2123 /* Legacy Interrupt Mode */
2124 } else {
2125 q_vector = adapter->q_vector[0];
f7554a2b 2126 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 2127 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2128 }
2129
2130 return 0;
2131}
2132
f8212f97
AD		 2133static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2134{
2135 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2136
2137 ethtool_op_set_flags(netdev, data);
2138
0c19d6af 2139 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
f8212f97
AD		 2140 return 0;
2141
2142 /* if state changes we need to update adapter->flags and reset */
2143 if ((!!(data & ETH_FLAG_LRO)) !=
0c19d6af
PWJ		 2144 (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
2145 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
f8212f97
AD		 2146 if (netif_running(netdev))
2147 ixgbe_reinit_locked(adapter);
2148 else
2149 ixgbe_reset(adapter);
2150 }
2151 return 0;
2152
2153}
9a799d71 2154
b9804972 2155static const struct ethtool_ops ixgbe_ethtool_ops = {
9a799d71
AK		 2156 .get_settings = ixgbe_get_settings,
2157 .set_settings = ixgbe_set_settings,
2158 .get_drvinfo = ixgbe_get_drvinfo,
2159 .get_regs_len = ixgbe_get_regs_len,
2160 .get_regs = ixgbe_get_regs,
2161 .get_wol = ixgbe_get_wol,
e63d9762 2162 .set_wol = ixgbe_set_wol,
9a799d71
AK		 2163 .nway_reset = ixgbe_nway_reset,
2164 .get_link = ethtool_op_get_link,
2165 .get_eeprom_len = ixgbe_get_eeprom_len,
2166 .get_eeprom = ixgbe_get_eeprom,
2167 .get_ringparam = ixgbe_get_ringparam,
2168 .set_ringparam = ixgbe_set_ringparam,
2169 .get_pauseparam = ixgbe_get_pauseparam,
2170 .set_pauseparam = ixgbe_set_pauseparam,
2171 .get_rx_csum = ixgbe_get_rx_csum,
2172 .set_rx_csum = ixgbe_set_rx_csum,
2173 .get_tx_csum = ixgbe_get_tx_csum,
2174 .set_tx_csum = ixgbe_set_tx_csum,
2175 .get_sg = ethtool_op_get_sg,
2176 .set_sg = ethtool_op_set_sg,
2177 .get_msglevel = ixgbe_get_msglevel,
2178 .set_msglevel = ixgbe_set_msglevel,
2179 .get_tso = ethtool_op_get_tso,
2180 .set_tso = ixgbe_set_tso,
da4dd0f7 2181 .self_test = ixgbe_diag_test,
9a799d71
AK		 2182 .get_strings = ixgbe_get_strings,
2183 .phys_id = ixgbe_phys_id,
b4617240 2184 .get_sset_count = ixgbe_get_sset_count,
9a799d71
AK		 2185 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2186 .get_coalesce = ixgbe_get_coalesce,
2187 .set_coalesce = ixgbe_set_coalesce,
177db6ff 2188 .get_flags = ethtool_op_get_flags,
f8212f97 2189 .set_flags = ixgbe_set_flags,
9a799d71
AK		 2190};
2191
2192void ixgbe_set_ethtool_ops(struct net_device *netdev)
2193{
2194 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2195}
Clone of davem's net-next-2.6 tree