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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
3efac5a0 | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/pci.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/sched.h> | |
ccffad25 JP |
31 | #include <linux/list.h> |
32 | #include <linux/netdevice.h> | |
9a799d71 | 33 | |
11afc1b1 | 34 | #include "ixgbe.h" |
9a799d71 AK |
35 | #include "ixgbe_common.h" |
36 | #include "ixgbe_phy.h" | |
37 | ||
9a799d71 | 38 | static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw); |
c44ade9e | 39 | static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); |
9a799d71 AK |
40 | static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); |
41 | static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); | |
c44ade9e JB |
42 | static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); |
43 | static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); | |
44 | static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, | |
45 | u16 count); | |
46 | static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); | |
47 | static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); | |
48 | static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); | |
49 | static void ixgbe_release_eeprom(struct ixgbe_hw *hw); | |
9a799d71 AK |
50 | static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw); |
51 | ||
c44ade9e JB |
52 | static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index); |
53 | static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index); | |
9a799d71 | 54 | static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); |
c44ade9e | 55 | static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); |
9a799d71 AK |
56 | |
57 | /** | |
c44ade9e | 58 | * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx |
9a799d71 AK |
59 | * @hw: pointer to hardware structure |
60 | * | |
61 | * Starts the hardware by filling the bus info structure and media type, clears | |
62 | * all on chip counters, initializes receive address registers, multicast | |
63 | * table, VLAN filter table, calls routine to set up link and flow control | |
64 | * settings, and leaves transmit and receive units disabled and uninitialized | |
65 | **/ | |
c44ade9e | 66 | s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
67 | { |
68 | u32 ctrl_ext; | |
69 | ||
70 | /* Set the media type */ | |
71 | hw->phy.media_type = hw->mac.ops.get_media_type(hw); | |
72 | ||
73 | /* Identify the PHY */ | |
c44ade9e | 74 | hw->phy.ops.identify(hw); |
9a799d71 | 75 | |
9a799d71 | 76 | /* Clear the VLAN filter table */ |
c44ade9e | 77 | hw->mac.ops.clear_vfta(hw); |
9a799d71 | 78 | |
9a799d71 | 79 | /* Clear statistics registers */ |
c44ade9e | 80 | hw->mac.ops.clear_hw_cntrs(hw); |
9a799d71 AK |
81 | |
82 | /* Set No Snoop Disable */ | |
83 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
84 | ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; | |
85 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
3957d63d | 86 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
87 | |
88 | /* Clear adapter stopped flag */ | |
89 | hw->adapter_stopped = false; | |
90 | ||
91 | return 0; | |
92 | } | |
93 | ||
94 | /** | |
c44ade9e | 95 | * ixgbe_init_hw_generic - Generic hardware initialization |
9a799d71 AK |
96 | * @hw: pointer to hardware structure |
97 | * | |
c44ade9e | 98 | * Initialize the hardware by resetting the hardware, filling the bus info |
9a799d71 AK |
99 | * structure and media type, clears all on chip counters, initializes receive |
100 | * address registers, multicast table, VLAN filter table, calls routine to set | |
101 | * up link and flow control settings, and leaves transmit and receive units | |
102 | * disabled and uninitialized | |
103 | **/ | |
c44ade9e | 104 | s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
105 | { |
106 | /* Reset the hardware */ | |
c44ade9e | 107 | hw->mac.ops.reset_hw(hw); |
9a799d71 AK |
108 | |
109 | /* Start the HW */ | |
c44ade9e | 110 | hw->mac.ops.start_hw(hw); |
9a799d71 AK |
111 | |
112 | return 0; | |
113 | } | |
114 | ||
115 | /** | |
c44ade9e | 116 | * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters |
9a799d71 AK |
117 | * @hw: pointer to hardware structure |
118 | * | |
119 | * Clears all hardware statistics counters by reading them from the hardware | |
120 | * Statistics counters are clear on read. | |
121 | **/ | |
c44ade9e | 122 | s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
123 | { |
124 | u16 i = 0; | |
125 | ||
126 | IXGBE_READ_REG(hw, IXGBE_CRCERRS); | |
127 | IXGBE_READ_REG(hw, IXGBE_ILLERRC); | |
128 | IXGBE_READ_REG(hw, IXGBE_ERRBC); | |
129 | IXGBE_READ_REG(hw, IXGBE_MSPDC); | |
130 | for (i = 0; i < 8; i++) | |
131 | IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
132 | ||
133 | IXGBE_READ_REG(hw, IXGBE_MLFC); | |
134 | IXGBE_READ_REG(hw, IXGBE_MRFC); | |
135 | IXGBE_READ_REG(hw, IXGBE_RLEC); | |
136 | IXGBE_READ_REG(hw, IXGBE_LXONTXC); | |
137 | IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
138 | IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); | |
139 | IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
140 | ||
141 | for (i = 0; i < 8; i++) { | |
142 | IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); | |
143 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
144 | IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
145 | IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); | |
146 | } | |
147 | ||
148 | IXGBE_READ_REG(hw, IXGBE_PRC64); | |
149 | IXGBE_READ_REG(hw, IXGBE_PRC127); | |
150 | IXGBE_READ_REG(hw, IXGBE_PRC255); | |
151 | IXGBE_READ_REG(hw, IXGBE_PRC511); | |
152 | IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
153 | IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
154 | IXGBE_READ_REG(hw, IXGBE_GPRC); | |
155 | IXGBE_READ_REG(hw, IXGBE_BPRC); | |
156 | IXGBE_READ_REG(hw, IXGBE_MPRC); | |
157 | IXGBE_READ_REG(hw, IXGBE_GPTC); | |
158 | IXGBE_READ_REG(hw, IXGBE_GORCL); | |
159 | IXGBE_READ_REG(hw, IXGBE_GORCH); | |
160 | IXGBE_READ_REG(hw, IXGBE_GOTCL); | |
161 | IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
162 | for (i = 0; i < 8; i++) | |
163 | IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
164 | IXGBE_READ_REG(hw, IXGBE_RUC); | |
165 | IXGBE_READ_REG(hw, IXGBE_RFC); | |
166 | IXGBE_READ_REG(hw, IXGBE_ROC); | |
167 | IXGBE_READ_REG(hw, IXGBE_RJC); | |
168 | IXGBE_READ_REG(hw, IXGBE_MNGPRC); | |
169 | IXGBE_READ_REG(hw, IXGBE_MNGPDC); | |
170 | IXGBE_READ_REG(hw, IXGBE_MNGPTC); | |
171 | IXGBE_READ_REG(hw, IXGBE_TORL); | |
172 | IXGBE_READ_REG(hw, IXGBE_TORH); | |
173 | IXGBE_READ_REG(hw, IXGBE_TPR); | |
174 | IXGBE_READ_REG(hw, IXGBE_TPT); | |
175 | IXGBE_READ_REG(hw, IXGBE_PTC64); | |
176 | IXGBE_READ_REG(hw, IXGBE_PTC127); | |
177 | IXGBE_READ_REG(hw, IXGBE_PTC255); | |
178 | IXGBE_READ_REG(hw, IXGBE_PTC511); | |
179 | IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
180 | IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
181 | IXGBE_READ_REG(hw, IXGBE_MPTC); | |
182 | IXGBE_READ_REG(hw, IXGBE_BPTC); | |
183 | for (i = 0; i < 16; i++) { | |
184 | IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
185 | IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
186 | IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
187 | IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
188 | } | |
189 | ||
190 | return 0; | |
191 | } | |
192 | ||
193 | /** | |
c44ade9e JB |
194 | * ixgbe_read_pba_num_generic - Reads part number from EEPROM |
195 | * @hw: pointer to hardware structure | |
196 | * @pba_num: stores the part number from the EEPROM | |
197 | * | |
198 | * Reads the part number from the EEPROM. | |
199 | **/ | |
200 | s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) | |
201 | { | |
202 | s32 ret_val; | |
203 | u16 data; | |
204 | ||
205 | ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); | |
206 | if (ret_val) { | |
207 | hw_dbg(hw, "NVM Read Error\n"); | |
208 | return ret_val; | |
209 | } | |
210 | *pba_num = (u32)(data << 16); | |
211 | ||
212 | ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); | |
213 | if (ret_val) { | |
214 | hw_dbg(hw, "NVM Read Error\n"); | |
215 | return ret_val; | |
216 | } | |
217 | *pba_num |= data; | |
218 | ||
219 | return 0; | |
220 | } | |
221 | ||
222 | /** | |
223 | * ixgbe_get_mac_addr_generic - Generic get MAC address | |
9a799d71 AK |
224 | * @hw: pointer to hardware structure |
225 | * @mac_addr: Adapter MAC address | |
226 | * | |
227 | * Reads the adapter's MAC address from first Receive Address Register (RAR0) | |
228 | * A reset of the adapter must be performed prior to calling this function | |
229 | * in order for the MAC address to have been loaded from the EEPROM into RAR0 | |
230 | **/ | |
c44ade9e | 231 | s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) |
9a799d71 AK |
232 | { |
233 | u32 rar_high; | |
234 | u32 rar_low; | |
235 | u16 i; | |
236 | ||
237 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); | |
238 | rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); | |
239 | ||
240 | for (i = 0; i < 4; i++) | |
241 | mac_addr[i] = (u8)(rar_low >> (i*8)); | |
242 | ||
243 | for (i = 0; i < 2; i++) | |
244 | mac_addr[i+4] = (u8)(rar_high >> (i*8)); | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
11afc1b1 PW |
249 | /** |
250 | * ixgbe_get_bus_info_generic - Generic set PCI bus info | |
251 | * @hw: pointer to hardware structure | |
252 | * | |
253 | * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure | |
254 | **/ | |
255 | s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) | |
256 | { | |
257 | struct ixgbe_adapter *adapter = hw->back; | |
258 | struct ixgbe_mac_info *mac = &hw->mac; | |
259 | u16 link_status; | |
260 | ||
261 | hw->bus.type = ixgbe_bus_type_pci_express; | |
262 | ||
263 | /* Get the negotiated link width and speed from PCI config space */ | |
264 | pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS, | |
265 | &link_status); | |
266 | ||
267 | switch (link_status & IXGBE_PCI_LINK_WIDTH) { | |
268 | case IXGBE_PCI_LINK_WIDTH_1: | |
269 | hw->bus.width = ixgbe_bus_width_pcie_x1; | |
270 | break; | |
271 | case IXGBE_PCI_LINK_WIDTH_2: | |
272 | hw->bus.width = ixgbe_bus_width_pcie_x2; | |
273 | break; | |
274 | case IXGBE_PCI_LINK_WIDTH_4: | |
275 | hw->bus.width = ixgbe_bus_width_pcie_x4; | |
276 | break; | |
277 | case IXGBE_PCI_LINK_WIDTH_8: | |
278 | hw->bus.width = ixgbe_bus_width_pcie_x8; | |
279 | break; | |
280 | default: | |
281 | hw->bus.width = ixgbe_bus_width_unknown; | |
282 | break; | |
283 | } | |
284 | ||
285 | switch (link_status & IXGBE_PCI_LINK_SPEED) { | |
286 | case IXGBE_PCI_LINK_SPEED_2500: | |
287 | hw->bus.speed = ixgbe_bus_speed_2500; | |
288 | break; | |
289 | case IXGBE_PCI_LINK_SPEED_5000: | |
290 | hw->bus.speed = ixgbe_bus_speed_5000; | |
291 | break; | |
292 | default: | |
293 | hw->bus.speed = ixgbe_bus_speed_unknown; | |
294 | break; | |
295 | } | |
296 | ||
297 | mac->ops.set_lan_id(hw); | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
302 | /** | |
303 | * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices | |
304 | * @hw: pointer to the HW structure | |
305 | * | |
306 | * Determines the LAN function id by reading memory-mapped registers | |
307 | * and swaps the port value if requested. | |
308 | **/ | |
309 | void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) | |
310 | { | |
311 | struct ixgbe_bus_info *bus = &hw->bus; | |
312 | u32 reg; | |
313 | ||
314 | reg = IXGBE_READ_REG(hw, IXGBE_STATUS); | |
315 | bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; | |
316 | bus->lan_id = bus->func; | |
317 | ||
318 | /* check for a port swap */ | |
319 | reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); | |
320 | if (reg & IXGBE_FACTPS_LFS) | |
321 | bus->func ^= 0x1; | |
322 | } | |
323 | ||
9a799d71 | 324 | /** |
c44ade9e | 325 | * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units |
9a799d71 AK |
326 | * @hw: pointer to hardware structure |
327 | * | |
328 | * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, | |
329 | * disables transmit and receive units. The adapter_stopped flag is used by | |
330 | * the shared code and drivers to determine if the adapter is in a stopped | |
331 | * state and should not touch the hardware. | |
332 | **/ | |
c44ade9e | 333 | s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
334 | { |
335 | u32 number_of_queues; | |
336 | u32 reg_val; | |
337 | u16 i; | |
338 | ||
339 | /* | |
340 | * Set the adapter_stopped flag so other driver functions stop touching | |
341 | * the hardware | |
342 | */ | |
343 | hw->adapter_stopped = true; | |
344 | ||
345 | /* Disable the receive unit */ | |
346 | reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
347 | reg_val &= ~(IXGBE_RXCTRL_RXEN); | |
348 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); | |
c44ade9e | 349 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
350 | msleep(2); |
351 | ||
352 | /* Clear interrupt mask to stop from interrupts being generated */ | |
353 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
354 | ||
355 | /* Clear any pending interrupts */ | |
356 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
357 | ||
358 | /* Disable the transmit unit. Each queue must be disabled. */ | |
c44ade9e | 359 | number_of_queues = hw->mac.max_tx_queues; |
9a799d71 AK |
360 | for (i = 0; i < number_of_queues; i++) { |
361 | reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
362 | if (reg_val & IXGBE_TXDCTL_ENABLE) { | |
363 | reg_val &= ~IXGBE_TXDCTL_ENABLE; | |
364 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); | |
365 | } | |
366 | } | |
367 | ||
c44ade9e JB |
368 | /* |
369 | * Prevent the PCI-E bus from from hanging by disabling PCI-E master | |
370 | * access and verify no pending requests | |
371 | */ | |
372 | if (ixgbe_disable_pcie_master(hw) != 0) | |
373 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | |
374 | ||
9a799d71 AK |
375 | return 0; |
376 | } | |
377 | ||
378 | /** | |
c44ade9e | 379 | * ixgbe_led_on_generic - Turns on the software controllable LEDs. |
9a799d71 AK |
380 | * @hw: pointer to hardware structure |
381 | * @index: led number to turn on | |
382 | **/ | |
c44ade9e | 383 | s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) |
9a799d71 AK |
384 | { |
385 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | |
386 | ||
387 | /* To turn on the LED, set mode to ON. */ | |
388 | led_reg &= ~IXGBE_LED_MODE_MASK(index); | |
389 | led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); | |
390 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); | |
3957d63d | 391 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
392 | |
393 | return 0; | |
394 | } | |
395 | ||
396 | /** | |
c44ade9e | 397 | * ixgbe_led_off_generic - Turns off the software controllable LEDs. |
9a799d71 AK |
398 | * @hw: pointer to hardware structure |
399 | * @index: led number to turn off | |
400 | **/ | |
c44ade9e | 401 | s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) |
9a799d71 AK |
402 | { |
403 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | |
404 | ||
405 | /* To turn off the LED, set mode to OFF. */ | |
406 | led_reg &= ~IXGBE_LED_MODE_MASK(index); | |
407 | led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); | |
408 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); | |
3957d63d | 409 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
410 | |
411 | return 0; | |
412 | } | |
413 | ||
9a799d71 | 414 | /** |
c44ade9e | 415 | * ixgbe_init_eeprom_params_generic - Initialize EEPROM params |
9a799d71 AK |
416 | * @hw: pointer to hardware structure |
417 | * | |
418 | * Initializes the EEPROM parameters ixgbe_eeprom_info within the | |
419 | * ixgbe_hw struct in order to set up EEPROM access. | |
420 | **/ | |
c44ade9e | 421 | s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
422 | { |
423 | struct ixgbe_eeprom_info *eeprom = &hw->eeprom; | |
424 | u32 eec; | |
425 | u16 eeprom_size; | |
426 | ||
427 | if (eeprom->type == ixgbe_eeprom_uninitialized) { | |
428 | eeprom->type = ixgbe_eeprom_none; | |
c44ade9e JB |
429 | /* Set default semaphore delay to 10ms which is a well |
430 | * tested value */ | |
431 | eeprom->semaphore_delay = 10; | |
9a799d71 AK |
432 | |
433 | /* | |
434 | * Check for EEPROM present first. | |
435 | * If not present leave as none | |
436 | */ | |
437 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
438 | if (eec & IXGBE_EEC_PRES) { | |
439 | eeprom->type = ixgbe_eeprom_spi; | |
440 | ||
441 | /* | |
442 | * SPI EEPROM is assumed here. This code would need to | |
443 | * change if a future EEPROM is not SPI. | |
444 | */ | |
445 | eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> | |
446 | IXGBE_EEC_SIZE_SHIFT); | |
447 | eeprom->word_size = 1 << (eeprom_size + | |
448 | IXGBE_EEPROM_WORD_SIZE_SHIFT); | |
449 | } | |
450 | ||
451 | if (eec & IXGBE_EEC_ADDR_SIZE) | |
452 | eeprom->address_bits = 16; | |
453 | else | |
454 | eeprom->address_bits = 8; | |
455 | hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: " | |
456 | "%d\n", eeprom->type, eeprom->word_size, | |
457 | eeprom->address_bits); | |
458 | } | |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
11afc1b1 PW |
463 | /** |
464 | * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM | |
465 | * @hw: pointer to hardware structure | |
466 | * @offset: offset within the EEPROM to be written to | |
467 | * @data: 16 bit word to be written to the EEPROM | |
468 | * | |
469 | * If ixgbe_eeprom_update_checksum is not called after this function, the | |
470 | * EEPROM will most likely contain an invalid checksum. | |
471 | **/ | |
472 | s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) | |
473 | { | |
474 | s32 status; | |
475 | u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; | |
476 | ||
477 | hw->eeprom.ops.init_params(hw); | |
478 | ||
479 | if (offset >= hw->eeprom.word_size) { | |
480 | status = IXGBE_ERR_EEPROM; | |
481 | goto out; | |
482 | } | |
483 | ||
484 | /* Prepare the EEPROM for writing */ | |
485 | status = ixgbe_acquire_eeprom(hw); | |
486 | ||
487 | if (status == 0) { | |
488 | if (ixgbe_ready_eeprom(hw) != 0) { | |
489 | ixgbe_release_eeprom(hw); | |
490 | status = IXGBE_ERR_EEPROM; | |
491 | } | |
492 | } | |
493 | ||
494 | if (status == 0) { | |
495 | ixgbe_standby_eeprom(hw); | |
496 | ||
497 | /* Send the WRITE ENABLE command (8 bit opcode ) */ | |
498 | ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, | |
499 | IXGBE_EEPROM_OPCODE_BITS); | |
500 | ||
501 | ixgbe_standby_eeprom(hw); | |
502 | ||
503 | /* | |
504 | * Some SPI eeproms use the 8th address bit embedded in the | |
505 | * opcode | |
506 | */ | |
507 | if ((hw->eeprom.address_bits == 8) && (offset >= 128)) | |
508 | write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; | |
509 | ||
510 | /* Send the Write command (8-bit opcode + addr) */ | |
511 | ixgbe_shift_out_eeprom_bits(hw, write_opcode, | |
512 | IXGBE_EEPROM_OPCODE_BITS); | |
513 | ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), | |
514 | hw->eeprom.address_bits); | |
515 | ||
516 | /* Send the data */ | |
517 | data = (data >> 8) | (data << 8); | |
518 | ixgbe_shift_out_eeprom_bits(hw, data, 16); | |
519 | ixgbe_standby_eeprom(hw); | |
520 | ||
521 | msleep(hw->eeprom.semaphore_delay); | |
522 | /* Done with writing - release the EEPROM */ | |
523 | ixgbe_release_eeprom(hw); | |
524 | } | |
525 | ||
526 | out: | |
527 | return status; | |
528 | } | |
529 | ||
9a799d71 | 530 | /** |
c44ade9e JB |
531 | * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang |
532 | * @hw: pointer to hardware structure | |
533 | * @offset: offset within the EEPROM to be read | |
534 | * @data: read 16 bit value from EEPROM | |
535 | * | |
536 | * Reads 16 bit value from EEPROM through bit-bang method | |
537 | **/ | |
538 | s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, | |
539 | u16 *data) | |
540 | { | |
541 | s32 status; | |
542 | u16 word_in; | |
543 | u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; | |
544 | ||
545 | hw->eeprom.ops.init_params(hw); | |
546 | ||
547 | if (offset >= hw->eeprom.word_size) { | |
548 | status = IXGBE_ERR_EEPROM; | |
549 | goto out; | |
550 | } | |
551 | ||
552 | /* Prepare the EEPROM for reading */ | |
553 | status = ixgbe_acquire_eeprom(hw); | |
554 | ||
555 | if (status == 0) { | |
556 | if (ixgbe_ready_eeprom(hw) != 0) { | |
557 | ixgbe_release_eeprom(hw); | |
558 | status = IXGBE_ERR_EEPROM; | |
559 | } | |
560 | } | |
561 | ||
562 | if (status == 0) { | |
563 | ixgbe_standby_eeprom(hw); | |
564 | ||
565 | /* | |
566 | * Some SPI eeproms use the 8th address bit embedded in the | |
567 | * opcode | |
568 | */ | |
569 | if ((hw->eeprom.address_bits == 8) && (offset >= 128)) | |
570 | read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; | |
571 | ||
572 | /* Send the READ command (opcode + addr) */ | |
573 | ixgbe_shift_out_eeprom_bits(hw, read_opcode, | |
574 | IXGBE_EEPROM_OPCODE_BITS); | |
575 | ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), | |
576 | hw->eeprom.address_bits); | |
577 | ||
578 | /* Read the data. */ | |
579 | word_in = ixgbe_shift_in_eeprom_bits(hw, 16); | |
580 | *data = (word_in >> 8) | (word_in << 8); | |
581 | ||
582 | /* End this read operation */ | |
583 | ixgbe_release_eeprom(hw); | |
584 | } | |
585 | ||
586 | out: | |
587 | return status; | |
588 | } | |
589 | ||
590 | /** | |
591 | * ixgbe_read_eeprom_generic - Read EEPROM word using EERD | |
9a799d71 AK |
592 | * @hw: pointer to hardware structure |
593 | * @offset: offset of word in the EEPROM to read | |
594 | * @data: word read from the EEPROM | |
595 | * | |
596 | * Reads a 16 bit word from the EEPROM using the EERD register. | |
597 | **/ | |
c44ade9e | 598 | s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) |
9a799d71 AK |
599 | { |
600 | u32 eerd; | |
601 | s32 status; | |
602 | ||
c44ade9e JB |
603 | hw->eeprom.ops.init_params(hw); |
604 | ||
605 | if (offset >= hw->eeprom.word_size) { | |
606 | status = IXGBE_ERR_EEPROM; | |
607 | goto out; | |
608 | } | |
609 | ||
9a799d71 AK |
610 | eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) + |
611 | IXGBE_EEPROM_READ_REG_START; | |
612 | ||
613 | IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); | |
614 | status = ixgbe_poll_eeprom_eerd_done(hw); | |
615 | ||
616 | if (status == 0) | |
617 | *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> | |
b4617240 | 618 | IXGBE_EEPROM_READ_REG_DATA); |
9a799d71 AK |
619 | else |
620 | hw_dbg(hw, "Eeprom read timed out\n"); | |
621 | ||
c44ade9e | 622 | out: |
9a799d71 AK |
623 | return status; |
624 | } | |
625 | ||
626 | /** | |
627 | * ixgbe_poll_eeprom_eerd_done - Poll EERD status | |
628 | * @hw: pointer to hardware structure | |
629 | * | |
630 | * Polls the status bit (bit 1) of the EERD to determine when the read is done. | |
631 | **/ | |
632 | static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw) | |
633 | { | |
634 | u32 i; | |
635 | u32 reg; | |
636 | s32 status = IXGBE_ERR_EEPROM; | |
637 | ||
638 | for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) { | |
639 | reg = IXGBE_READ_REG(hw, IXGBE_EERD); | |
640 | if (reg & IXGBE_EEPROM_READ_REG_DONE) { | |
641 | status = 0; | |
642 | break; | |
643 | } | |
644 | udelay(5); | |
645 | } | |
646 | return status; | |
647 | } | |
648 | ||
c44ade9e JB |
649 | /** |
650 | * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang | |
651 | * @hw: pointer to hardware structure | |
652 | * | |
653 | * Prepares EEPROM for access using bit-bang method. This function should | |
654 | * be called before issuing a command to the EEPROM. | |
655 | **/ | |
656 | static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) | |
657 | { | |
658 | s32 status = 0; | |
fc1f2095 | 659 | u32 eec = 0; |
c44ade9e JB |
660 | u32 i; |
661 | ||
662 | if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) | |
663 | status = IXGBE_ERR_SWFW_SYNC; | |
664 | ||
665 | if (status == 0) { | |
666 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
667 | ||
668 | /* Request EEPROM Access */ | |
669 | eec |= IXGBE_EEC_REQ; | |
670 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
671 | ||
672 | for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { | |
673 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
674 | if (eec & IXGBE_EEC_GNT) | |
675 | break; | |
676 | udelay(5); | |
677 | } | |
678 | ||
679 | /* Release if grant not acquired */ | |
680 | if (!(eec & IXGBE_EEC_GNT)) { | |
681 | eec &= ~IXGBE_EEC_REQ; | |
682 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
683 | hw_dbg(hw, "Could not acquire EEPROM grant\n"); | |
684 | ||
685 | ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | |
686 | status = IXGBE_ERR_EEPROM; | |
687 | } | |
688 | } | |
689 | ||
690 | /* Setup EEPROM for Read/Write */ | |
691 | if (status == 0) { | |
692 | /* Clear CS and SK */ | |
693 | eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); | |
694 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
695 | IXGBE_WRITE_FLUSH(hw); | |
696 | udelay(1); | |
697 | } | |
698 | return status; | |
699 | } | |
700 | ||
9a799d71 AK |
701 | /** |
702 | * ixgbe_get_eeprom_semaphore - Get hardware semaphore | |
703 | * @hw: pointer to hardware structure | |
704 | * | |
705 | * Sets the hardware semaphores so EEPROM access can occur for bit-bang method | |
706 | **/ | |
707 | static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) | |
708 | { | |
709 | s32 status = IXGBE_ERR_EEPROM; | |
710 | u32 timeout; | |
711 | u32 i; | |
712 | u32 swsm; | |
713 | ||
714 | /* Set timeout value based on size of EEPROM */ | |
715 | timeout = hw->eeprom.word_size + 1; | |
716 | ||
717 | /* Get SMBI software semaphore between device drivers first */ | |
718 | for (i = 0; i < timeout; i++) { | |
719 | /* | |
720 | * If the SMBI bit is 0 when we read it, then the bit will be | |
721 | * set and we have the semaphore | |
722 | */ | |
723 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | |
724 | if (!(swsm & IXGBE_SWSM_SMBI)) { | |
725 | status = 0; | |
726 | break; | |
727 | } | |
728 | msleep(1); | |
729 | } | |
730 | ||
731 | /* Now get the semaphore between SW/FW through the SWESMBI bit */ | |
732 | if (status == 0) { | |
733 | for (i = 0; i < timeout; i++) { | |
734 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | |
735 | ||
736 | /* Set the SW EEPROM semaphore bit to request access */ | |
737 | swsm |= IXGBE_SWSM_SWESMBI; | |
738 | IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); | |
739 | ||
740 | /* | |
741 | * If we set the bit successfully then we got the | |
742 | * semaphore. | |
743 | */ | |
744 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | |
745 | if (swsm & IXGBE_SWSM_SWESMBI) | |
746 | break; | |
747 | ||
748 | udelay(50); | |
749 | } | |
750 | ||
751 | /* | |
752 | * Release semaphores and return error if SW EEPROM semaphore | |
753 | * was not granted because we don't have access to the EEPROM | |
754 | */ | |
755 | if (i >= timeout) { | |
756 | hw_dbg(hw, "Driver can't access the Eeprom - Semaphore " | |
b4617240 | 757 | "not granted.\n"); |
9a799d71 AK |
758 | ixgbe_release_eeprom_semaphore(hw); |
759 | status = IXGBE_ERR_EEPROM; | |
760 | } | |
761 | } | |
762 | ||
763 | return status; | |
764 | } | |
765 | ||
766 | /** | |
767 | * ixgbe_release_eeprom_semaphore - Release hardware semaphore | |
768 | * @hw: pointer to hardware structure | |
769 | * | |
770 | * This function clears hardware semaphore bits. | |
771 | **/ | |
772 | static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) | |
773 | { | |
774 | u32 swsm; | |
775 | ||
776 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | |
777 | ||
778 | /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ | |
779 | swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); | |
780 | IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); | |
3957d63d | 781 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
782 | } |
783 | ||
c44ade9e JB |
784 | /** |
785 | * ixgbe_ready_eeprom - Polls for EEPROM ready | |
786 | * @hw: pointer to hardware structure | |
787 | **/ | |
788 | static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) | |
789 | { | |
790 | s32 status = 0; | |
791 | u16 i; | |
792 | u8 spi_stat_reg; | |
793 | ||
794 | /* | |
795 | * Read "Status Register" repeatedly until the LSB is cleared. The | |
796 | * EEPROM will signal that the command has been completed by clearing | |
797 | * bit 0 of the internal status register. If it's not cleared within | |
798 | * 5 milliseconds, then error out. | |
799 | */ | |
800 | for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { | |
801 | ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, | |
802 | IXGBE_EEPROM_OPCODE_BITS); | |
803 | spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); | |
804 | if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) | |
805 | break; | |
806 | ||
807 | udelay(5); | |
808 | ixgbe_standby_eeprom(hw); | |
809 | }; | |
810 | ||
811 | /* | |
812 | * On some parts, SPI write time could vary from 0-20mSec on 3.3V | |
813 | * devices (and only 0-5mSec on 5V devices) | |
814 | */ | |
815 | if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { | |
816 | hw_dbg(hw, "SPI EEPROM Status error\n"); | |
817 | status = IXGBE_ERR_EEPROM; | |
818 | } | |
819 | ||
820 | return status; | |
821 | } | |
822 | ||
823 | /** | |
824 | * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state | |
825 | * @hw: pointer to hardware structure | |
826 | **/ | |
827 | static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) | |
828 | { | |
829 | u32 eec; | |
830 | ||
831 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
832 | ||
833 | /* Toggle CS to flush commands */ | |
834 | eec |= IXGBE_EEC_CS; | |
835 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
836 | IXGBE_WRITE_FLUSH(hw); | |
837 | udelay(1); | |
838 | eec &= ~IXGBE_EEC_CS; | |
839 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
840 | IXGBE_WRITE_FLUSH(hw); | |
841 | udelay(1); | |
842 | } | |
843 | ||
844 | /** | |
845 | * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. | |
846 | * @hw: pointer to hardware structure | |
847 | * @data: data to send to the EEPROM | |
848 | * @count: number of bits to shift out | |
849 | **/ | |
850 | static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, | |
851 | u16 count) | |
852 | { | |
853 | u32 eec; | |
854 | u32 mask; | |
855 | u32 i; | |
856 | ||
857 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
858 | ||
859 | /* | |
860 | * Mask is used to shift "count" bits of "data" out to the EEPROM | |
861 | * one bit at a time. Determine the starting bit based on count | |
862 | */ | |
863 | mask = 0x01 << (count - 1); | |
864 | ||
865 | for (i = 0; i < count; i++) { | |
866 | /* | |
867 | * A "1" is shifted out to the EEPROM by setting bit "DI" to a | |
868 | * "1", and then raising and then lowering the clock (the SK | |
869 | * bit controls the clock input to the EEPROM). A "0" is | |
870 | * shifted out to the EEPROM by setting "DI" to "0" and then | |
871 | * raising and then lowering the clock. | |
872 | */ | |
873 | if (data & mask) | |
874 | eec |= IXGBE_EEC_DI; | |
875 | else | |
876 | eec &= ~IXGBE_EEC_DI; | |
877 | ||
878 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
879 | IXGBE_WRITE_FLUSH(hw); | |
880 | ||
881 | udelay(1); | |
882 | ||
883 | ixgbe_raise_eeprom_clk(hw, &eec); | |
884 | ixgbe_lower_eeprom_clk(hw, &eec); | |
885 | ||
886 | /* | |
887 | * Shift mask to signify next bit of data to shift in to the | |
888 | * EEPROM | |
889 | */ | |
890 | mask = mask >> 1; | |
891 | }; | |
892 | ||
893 | /* We leave the "DI" bit set to "0" when we leave this routine. */ | |
894 | eec &= ~IXGBE_EEC_DI; | |
895 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
896 | IXGBE_WRITE_FLUSH(hw); | |
897 | } | |
898 | ||
899 | /** | |
900 | * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM | |
901 | * @hw: pointer to hardware structure | |
902 | **/ | |
903 | static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) | |
904 | { | |
905 | u32 eec; | |
906 | u32 i; | |
907 | u16 data = 0; | |
908 | ||
909 | /* | |
910 | * In order to read a register from the EEPROM, we need to shift | |
911 | * 'count' bits in from the EEPROM. Bits are "shifted in" by raising | |
912 | * the clock input to the EEPROM (setting the SK bit), and then reading | |
913 | * the value of the "DO" bit. During this "shifting in" process the | |
914 | * "DI" bit should always be clear. | |
915 | */ | |
916 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
917 | ||
918 | eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); | |
919 | ||
920 | for (i = 0; i < count; i++) { | |
921 | data = data << 1; | |
922 | ixgbe_raise_eeprom_clk(hw, &eec); | |
923 | ||
924 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
925 | ||
926 | eec &= ~(IXGBE_EEC_DI); | |
927 | if (eec & IXGBE_EEC_DO) | |
928 | data |= 1; | |
929 | ||
930 | ixgbe_lower_eeprom_clk(hw, &eec); | |
931 | } | |
932 | ||
933 | return data; | |
934 | } | |
935 | ||
936 | /** | |
937 | * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. | |
938 | * @hw: pointer to hardware structure | |
939 | * @eec: EEC register's current value | |
940 | **/ | |
941 | static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) | |
942 | { | |
943 | /* | |
944 | * Raise the clock input to the EEPROM | |
945 | * (setting the SK bit), then delay | |
946 | */ | |
947 | *eec = *eec | IXGBE_EEC_SK; | |
948 | IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); | |
949 | IXGBE_WRITE_FLUSH(hw); | |
950 | udelay(1); | |
951 | } | |
952 | ||
953 | /** | |
954 | * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. | |
955 | * @hw: pointer to hardware structure | |
956 | * @eecd: EECD's current value | |
957 | **/ | |
958 | static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) | |
959 | { | |
960 | /* | |
961 | * Lower the clock input to the EEPROM (clearing the SK bit), then | |
962 | * delay | |
963 | */ | |
964 | *eec = *eec & ~IXGBE_EEC_SK; | |
965 | IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); | |
966 | IXGBE_WRITE_FLUSH(hw); | |
967 | udelay(1); | |
968 | } | |
969 | ||
970 | /** | |
971 | * ixgbe_release_eeprom - Release EEPROM, release semaphores | |
972 | * @hw: pointer to hardware structure | |
973 | **/ | |
974 | static void ixgbe_release_eeprom(struct ixgbe_hw *hw) | |
975 | { | |
976 | u32 eec; | |
977 | ||
978 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
979 | ||
980 | eec |= IXGBE_EEC_CS; /* Pull CS high */ | |
981 | eec &= ~IXGBE_EEC_SK; /* Lower SCK */ | |
982 | ||
983 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
984 | IXGBE_WRITE_FLUSH(hw); | |
985 | ||
986 | udelay(1); | |
987 | ||
988 | /* Stop requesting EEPROM access */ | |
989 | eec &= ~IXGBE_EEC_REQ; | |
990 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
991 | ||
992 | ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | |
993 | } | |
994 | ||
9a799d71 AK |
995 | /** |
996 | * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum | |
997 | * @hw: pointer to hardware structure | |
998 | **/ | |
999 | static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw) | |
1000 | { | |
1001 | u16 i; | |
1002 | u16 j; | |
1003 | u16 checksum = 0; | |
1004 | u16 length = 0; | |
1005 | u16 pointer = 0; | |
1006 | u16 word = 0; | |
1007 | ||
1008 | /* Include 0x0-0x3F in the checksum */ | |
1009 | for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { | |
c44ade9e | 1010 | if (hw->eeprom.ops.read(hw, i, &word) != 0) { |
9a799d71 AK |
1011 | hw_dbg(hw, "EEPROM read failed\n"); |
1012 | break; | |
1013 | } | |
1014 | checksum += word; | |
1015 | } | |
1016 | ||
1017 | /* Include all data from pointers except for the fw pointer */ | |
1018 | for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { | |
c44ade9e | 1019 | hw->eeprom.ops.read(hw, i, &pointer); |
9a799d71 AK |
1020 | |
1021 | /* Make sure the pointer seems valid */ | |
1022 | if (pointer != 0xFFFF && pointer != 0) { | |
c44ade9e | 1023 | hw->eeprom.ops.read(hw, pointer, &length); |
9a799d71 AK |
1024 | |
1025 | if (length != 0xFFFF && length != 0) { | |
1026 | for (j = pointer+1; j <= pointer+length; j++) { | |
c44ade9e | 1027 | hw->eeprom.ops.read(hw, j, &word); |
9a799d71 AK |
1028 | checksum += word; |
1029 | } | |
1030 | } | |
1031 | } | |
1032 | } | |
1033 | ||
1034 | checksum = (u16)IXGBE_EEPROM_SUM - checksum; | |
1035 | ||
1036 | return checksum; | |
1037 | } | |
1038 | ||
1039 | /** | |
c44ade9e | 1040 | * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum |
9a799d71 AK |
1041 | * @hw: pointer to hardware structure |
1042 | * @checksum_val: calculated checksum | |
1043 | * | |
1044 | * Performs checksum calculation and validates the EEPROM checksum. If the | |
1045 | * caller does not need checksum_val, the value can be NULL. | |
1046 | **/ | |
c44ade9e JB |
1047 | s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, |
1048 | u16 *checksum_val) | |
9a799d71 AK |
1049 | { |
1050 | s32 status; | |
1051 | u16 checksum; | |
1052 | u16 read_checksum = 0; | |
1053 | ||
1054 | /* | |
1055 | * Read the first word from the EEPROM. If this times out or fails, do | |
1056 | * not continue or we could be in for a very long wait while every | |
1057 | * EEPROM read fails | |
1058 | */ | |
c44ade9e | 1059 | status = hw->eeprom.ops.read(hw, 0, &checksum); |
9a799d71 AK |
1060 | |
1061 | if (status == 0) { | |
1062 | checksum = ixgbe_calc_eeprom_checksum(hw); | |
1063 | ||
c44ade9e | 1064 | hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); |
9a799d71 AK |
1065 | |
1066 | /* | |
1067 | * Verify read checksum from EEPROM is the same as | |
1068 | * calculated checksum | |
1069 | */ | |
1070 | if (read_checksum != checksum) | |
1071 | status = IXGBE_ERR_EEPROM_CHECKSUM; | |
1072 | ||
1073 | /* If the user cares, return the calculated checksum */ | |
1074 | if (checksum_val) | |
1075 | *checksum_val = checksum; | |
1076 | } else { | |
1077 | hw_dbg(hw, "EEPROM read failed\n"); | |
1078 | } | |
1079 | ||
1080 | return status; | |
1081 | } | |
1082 | ||
c44ade9e JB |
1083 | /** |
1084 | * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum | |
1085 | * @hw: pointer to hardware structure | |
1086 | **/ | |
1087 | s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) | |
1088 | { | |
1089 | s32 status; | |
1090 | u16 checksum; | |
1091 | ||
1092 | /* | |
1093 | * Read the first word from the EEPROM. If this times out or fails, do | |
1094 | * not continue or we could be in for a very long wait while every | |
1095 | * EEPROM read fails | |
1096 | */ | |
1097 | status = hw->eeprom.ops.read(hw, 0, &checksum); | |
1098 | ||
1099 | if (status == 0) { | |
1100 | checksum = ixgbe_calc_eeprom_checksum(hw); | |
1101 | status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, | |
1102 | checksum); | |
1103 | } else { | |
1104 | hw_dbg(hw, "EEPROM read failed\n"); | |
1105 | } | |
1106 | ||
1107 | return status; | |
1108 | } | |
1109 | ||
9a799d71 AK |
1110 | /** |
1111 | * ixgbe_validate_mac_addr - Validate MAC address | |
1112 | * @mac_addr: pointer to MAC address. | |
1113 | * | |
1114 | * Tests a MAC address to ensure it is a valid Individual Address | |
1115 | **/ | |
1116 | s32 ixgbe_validate_mac_addr(u8 *mac_addr) | |
1117 | { | |
1118 | s32 status = 0; | |
1119 | ||
1120 | /* Make sure it is not a multicast address */ | |
1121 | if (IXGBE_IS_MULTICAST(mac_addr)) | |
1122 | status = IXGBE_ERR_INVALID_MAC_ADDR; | |
1123 | /* Not a broadcast address */ | |
1124 | else if (IXGBE_IS_BROADCAST(mac_addr)) | |
1125 | status = IXGBE_ERR_INVALID_MAC_ADDR; | |
1126 | /* Reject the zero address */ | |
1127 | else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && | |
c44ade9e | 1128 | mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) |
9a799d71 AK |
1129 | status = IXGBE_ERR_INVALID_MAC_ADDR; |
1130 | ||
1131 | return status; | |
1132 | } | |
1133 | ||
1134 | /** | |
c44ade9e | 1135 | * ixgbe_set_rar_generic - Set Rx address register |
9a799d71 | 1136 | * @hw: pointer to hardware structure |
9a799d71 | 1137 | * @index: Receive address register to write |
c44ade9e JB |
1138 | * @addr: Address to put into receive address register |
1139 | * @vmdq: VMDq "set" or "pool" index | |
9a799d71 AK |
1140 | * @enable_addr: set flag that address is active |
1141 | * | |
1142 | * Puts an ethernet address into a receive address register. | |
1143 | **/ | |
c44ade9e JB |
1144 | s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, |
1145 | u32 enable_addr) | |
9a799d71 AK |
1146 | { |
1147 | u32 rar_low, rar_high; | |
c44ade9e JB |
1148 | u32 rar_entries = hw->mac.num_rar_entries; |
1149 | ||
1150 | /* setup VMDq pool selection before this RAR gets enabled */ | |
1151 | hw->mac.ops.set_vmdq(hw, index, vmdq); | |
9a799d71 | 1152 | |
c44ade9e JB |
1153 | /* Make sure we are using a valid rar index range */ |
1154 | if (index < rar_entries) { | |
b4617240 | 1155 | /* |
c44ade9e JB |
1156 | * HW expects these in little endian so we reverse the byte |
1157 | * order from network order (big endian) to little endian | |
b4617240 PW |
1158 | */ |
1159 | rar_low = ((u32)addr[0] | | |
1160 | ((u32)addr[1] << 8) | | |
1161 | ((u32)addr[2] << 16) | | |
1162 | ((u32)addr[3] << 24)); | |
c44ade9e JB |
1163 | /* |
1164 | * Some parts put the VMDq setting in the extra RAH bits, | |
1165 | * so save everything except the lower 16 bits that hold part | |
1166 | * of the address and the address valid bit. | |
1167 | */ | |
1168 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); | |
1169 | rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); | |
1170 | rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); | |
9a799d71 | 1171 | |
b4617240 PW |
1172 | if (enable_addr != 0) |
1173 | rar_high |= IXGBE_RAH_AV; | |
9a799d71 | 1174 | |
b4617240 PW |
1175 | IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); |
1176 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); | |
c44ade9e JB |
1177 | } else { |
1178 | hw_dbg(hw, "RAR index %d is out of range.\n", index); | |
1179 | } | |
1180 | ||
1181 | return 0; | |
1182 | } | |
1183 | ||
1184 | /** | |
1185 | * ixgbe_clear_rar_generic - Remove Rx address register | |
1186 | * @hw: pointer to hardware structure | |
1187 | * @index: Receive address register to write | |
1188 | * | |
1189 | * Clears an ethernet address from a receive address register. | |
1190 | **/ | |
1191 | s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) | |
1192 | { | |
1193 | u32 rar_high; | |
1194 | u32 rar_entries = hw->mac.num_rar_entries; | |
1195 | ||
1196 | /* Make sure we are using a valid rar index range */ | |
1197 | if (index < rar_entries) { | |
1198 | /* | |
1199 | * Some parts put the VMDq setting in the extra RAH bits, | |
1200 | * so save everything except the lower 16 bits that hold part | |
1201 | * of the address and the address valid bit. | |
1202 | */ | |
1203 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); | |
1204 | rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); | |
1205 | ||
1206 | IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); | |
1207 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); | |
1208 | } else { | |
1209 | hw_dbg(hw, "RAR index %d is out of range.\n", index); | |
1210 | } | |
1211 | ||
1212 | /* clear VMDq pool/queue selection for this RAR */ | |
1213 | hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); | |
9a799d71 AK |
1214 | |
1215 | return 0; | |
1216 | } | |
1217 | ||
1218 | /** | |
c44ade9e JB |
1219 | * ixgbe_enable_rar - Enable Rx address register |
1220 | * @hw: pointer to hardware structure | |
1221 | * @index: index into the RAR table | |
1222 | * | |
1223 | * Enables the select receive address register. | |
1224 | **/ | |
1225 | static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index) | |
1226 | { | |
1227 | u32 rar_high; | |
1228 | ||
1229 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); | |
1230 | rar_high |= IXGBE_RAH_AV; | |
1231 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); | |
1232 | } | |
1233 | ||
1234 | /** | |
1235 | * ixgbe_disable_rar - Disable Rx address register | |
1236 | * @hw: pointer to hardware structure | |
1237 | * @index: index into the RAR table | |
1238 | * | |
1239 | * Disables the select receive address register. | |
1240 | **/ | |
1241 | static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index) | |
1242 | { | |
1243 | u32 rar_high; | |
1244 | ||
1245 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); | |
1246 | rar_high &= (~IXGBE_RAH_AV); | |
1247 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); | |
1248 | } | |
1249 | ||
1250 | /** | |
1251 | * ixgbe_init_rx_addrs_generic - Initializes receive address filters. | |
9a799d71 AK |
1252 | * @hw: pointer to hardware structure |
1253 | * | |
1254 | * Places the MAC address in receive address register 0 and clears the rest | |
c44ade9e | 1255 | * of the receive address registers. Clears the multicast table. Assumes |
9a799d71 AK |
1256 | * the receiver is in reset when the routine is called. |
1257 | **/ | |
c44ade9e | 1258 | s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
1259 | { |
1260 | u32 i; | |
2c5645cf | 1261 | u32 rar_entries = hw->mac.num_rar_entries; |
9a799d71 AK |
1262 | |
1263 | /* | |
1264 | * If the current mac address is valid, assume it is a software override | |
1265 | * to the permanent address. | |
1266 | * Otherwise, use the permanent address from the eeprom. | |
1267 | */ | |
1268 | if (ixgbe_validate_mac_addr(hw->mac.addr) == | |
1269 | IXGBE_ERR_INVALID_MAC_ADDR) { | |
1270 | /* Get the MAC address from the RAR0 for later reference */ | |
c44ade9e | 1271 | hw->mac.ops.get_mac_addr(hw, hw->mac.addr); |
9a799d71 AK |
1272 | |
1273 | hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ", | |
b4617240 PW |
1274 | hw->mac.addr[0], hw->mac.addr[1], |
1275 | hw->mac.addr[2]); | |
9a799d71 | 1276 | hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3], |
b4617240 | 1277 | hw->mac.addr[4], hw->mac.addr[5]); |
9a799d71 AK |
1278 | } else { |
1279 | /* Setup the receive address. */ | |
1280 | hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); | |
1281 | hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ", | |
b4617240 PW |
1282 | hw->mac.addr[0], hw->mac.addr[1], |
1283 | hw->mac.addr[2]); | |
9a799d71 | 1284 | hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3], |
b4617240 | 1285 | hw->mac.addr[4], hw->mac.addr[5]); |
9a799d71 | 1286 | |
c44ade9e | 1287 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 | 1288 | } |
c44ade9e | 1289 | hw->addr_ctrl.overflow_promisc = 0; |
9a799d71 AK |
1290 | |
1291 | hw->addr_ctrl.rar_used_count = 1; | |
1292 | ||
1293 | /* Zero out the other receive addresses. */ | |
c44ade9e | 1294 | hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); |
9a799d71 AK |
1295 | for (i = 1; i < rar_entries; i++) { |
1296 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); | |
1297 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); | |
1298 | } | |
1299 | ||
1300 | /* Clear the MTA */ | |
1301 | hw->addr_ctrl.mc_addr_in_rar_count = 0; | |
1302 | hw->addr_ctrl.mta_in_use = 0; | |
1303 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); | |
1304 | ||
1305 | hw_dbg(hw, " Clearing MTA\n"); | |
2c5645cf | 1306 | for (i = 0; i < hw->mac.mcft_size; i++) |
9a799d71 AK |
1307 | IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); |
1308 | ||
c44ade9e JB |
1309 | if (hw->mac.ops.init_uta_tables) |
1310 | hw->mac.ops.init_uta_tables(hw); | |
1311 | ||
9a799d71 AK |
1312 | return 0; |
1313 | } | |
1314 | ||
2c5645cf CL |
1315 | /** |
1316 | * ixgbe_add_uc_addr - Adds a secondary unicast address. | |
1317 | * @hw: pointer to hardware structure | |
1318 | * @addr: new address | |
1319 | * | |
1320 | * Adds it to unused receive address register or goes into promiscuous mode. | |
1321 | **/ | |
c44ade9e | 1322 | static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) |
2c5645cf CL |
1323 | { |
1324 | u32 rar_entries = hw->mac.num_rar_entries; | |
1325 | u32 rar; | |
1326 | ||
1327 | hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", | |
1328 | addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); | |
1329 | ||
1330 | /* | |
1331 | * Place this address in the RAR if there is room, | |
1332 | * else put the controller into promiscuous mode | |
1333 | */ | |
1334 | if (hw->addr_ctrl.rar_used_count < rar_entries) { | |
1335 | rar = hw->addr_ctrl.rar_used_count - | |
1336 | hw->addr_ctrl.mc_addr_in_rar_count; | |
c44ade9e | 1337 | hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); |
2c5645cf CL |
1338 | hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar); |
1339 | hw->addr_ctrl.rar_used_count++; | |
1340 | } else { | |
1341 | hw->addr_ctrl.overflow_promisc++; | |
1342 | } | |
1343 | ||
1344 | hw_dbg(hw, "ixgbe_add_uc_addr Complete\n"); | |
1345 | } | |
1346 | ||
1347 | /** | |
c44ade9e | 1348 | * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses |
2c5645cf CL |
1349 | * @hw: pointer to hardware structure |
1350 | * @addr_list: the list of new addresses | |
1351 | * @addr_count: number of addresses | |
1352 | * @next: iterator function to walk the address list | |
1353 | * | |
1354 | * The given list replaces any existing list. Clears the secondary addrs from | |
1355 | * receive address registers. Uses unused receive address registers for the | |
1356 | * first secondary addresses, and falls back to promiscuous mode as needed. | |
1357 | * | |
1358 | * Drivers using secondary unicast addresses must set user_set_promisc when | |
1359 | * manually putting the device into promiscuous mode. | |
1360 | **/ | |
ccffad25 JP |
1361 | s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, |
1362 | struct list_head *uc_list) | |
2c5645cf | 1363 | { |
2c5645cf CL |
1364 | u32 i; |
1365 | u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; | |
1366 | u32 uc_addr_in_use; | |
1367 | u32 fctrl; | |
ccffad25 | 1368 | struct netdev_hw_addr *ha; |
2c5645cf CL |
1369 | |
1370 | /* | |
1371 | * Clear accounting of old secondary address list, | |
1372 | * don't count RAR[0] | |
1373 | */ | |
495dce12 | 1374 | uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; |
2c5645cf CL |
1375 | hw->addr_ctrl.rar_used_count -= uc_addr_in_use; |
1376 | hw->addr_ctrl.overflow_promisc = 0; | |
1377 | ||
1378 | /* Zero out the other receive addresses */ | |
1379 | hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use); | |
1380 | for (i = 1; i <= uc_addr_in_use; i++) { | |
1381 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); | |
1382 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); | |
1383 | } | |
1384 | ||
1385 | /* Add the new addresses */ | |
ccffad25 | 1386 | list_for_each_entry(ha, uc_list, list) { |
2c5645cf | 1387 | hw_dbg(hw, " Adding the secondary addresses:\n"); |
ccffad25 | 1388 | ixgbe_add_uc_addr(hw, ha->addr, 0); |
2c5645cf CL |
1389 | } |
1390 | ||
1391 | if (hw->addr_ctrl.overflow_promisc) { | |
1392 | /* enable promisc if not already in overflow or set by user */ | |
1393 | if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { | |
1394 | hw_dbg(hw, " Entering address overflow promisc mode\n"); | |
1395 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
1396 | fctrl |= IXGBE_FCTRL_UPE; | |
1397 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
1398 | } | |
1399 | } else { | |
1400 | /* only disable if set by overflow, not by user */ | |
1401 | if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { | |
1402 | hw_dbg(hw, " Leaving address overflow promisc mode\n"); | |
1403 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
1404 | fctrl &= ~IXGBE_FCTRL_UPE; | |
1405 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
1406 | } | |
1407 | } | |
1408 | ||
c44ade9e | 1409 | hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n"); |
2c5645cf CL |
1410 | return 0; |
1411 | } | |
1412 | ||
9a799d71 AK |
1413 | /** |
1414 | * ixgbe_mta_vector - Determines bit-vector in multicast table to set | |
1415 | * @hw: pointer to hardware structure | |
1416 | * @mc_addr: the multicast address | |
1417 | * | |
1418 | * Extracts the 12 bits, from a multicast address, to determine which | |
1419 | * bit-vector to set in the multicast table. The hardware uses 12 bits, from | |
1420 | * incoming rx multicast addresses, to determine the bit-vector to check in | |
1421 | * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set | |
c44ade9e | 1422 | * by the MO field of the MCSTCTRL. The MO field is set during initialization |
9a799d71 AK |
1423 | * to mc_filter_type. |
1424 | **/ | |
1425 | static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) | |
1426 | { | |
1427 | u32 vector = 0; | |
1428 | ||
1429 | switch (hw->mac.mc_filter_type) { | |
b4617240 | 1430 | case 0: /* use bits [47:36] of the address */ |
9a799d71 AK |
1431 | vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); |
1432 | break; | |
b4617240 | 1433 | case 1: /* use bits [46:35] of the address */ |
9a799d71 AK |
1434 | vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); |
1435 | break; | |
b4617240 | 1436 | case 2: /* use bits [45:34] of the address */ |
9a799d71 AK |
1437 | vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); |
1438 | break; | |
b4617240 | 1439 | case 3: /* use bits [43:32] of the address */ |
9a799d71 AK |
1440 | vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); |
1441 | break; | |
b4617240 | 1442 | default: /* Invalid mc_filter_type */ |
9a799d71 AK |
1443 | hw_dbg(hw, "MC filter type param set incorrectly\n"); |
1444 | break; | |
1445 | } | |
1446 | ||
1447 | /* vector can only be 12-bits or boundary will be exceeded */ | |
1448 | vector &= 0xFFF; | |
1449 | return vector; | |
1450 | } | |
1451 | ||
1452 | /** | |
1453 | * ixgbe_set_mta - Set bit-vector in multicast table | |
1454 | * @hw: pointer to hardware structure | |
1455 | * @hash_value: Multicast address hash value | |
1456 | * | |
1457 | * Sets the bit-vector in the multicast table. | |
1458 | **/ | |
1459 | static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) | |
1460 | { | |
1461 | u32 vector; | |
1462 | u32 vector_bit; | |
1463 | u32 vector_reg; | |
1464 | u32 mta_reg; | |
1465 | ||
1466 | hw->addr_ctrl.mta_in_use++; | |
1467 | ||
1468 | vector = ixgbe_mta_vector(hw, mc_addr); | |
1469 | hw_dbg(hw, " bit-vector = 0x%03X\n", vector); | |
1470 | ||
1471 | /* | |
1472 | * The MTA is a register array of 128 32-bit registers. It is treated | |
1473 | * like an array of 4096 bits. We want to set bit | |
1474 | * BitArray[vector_value]. So we figure out what register the bit is | |
1475 | * in, read it, OR in the new bit, then write back the new value. The | |
1476 | * register is determined by the upper 7 bits of the vector value and | |
1477 | * the bit within that register are determined by the lower 5 bits of | |
1478 | * the value. | |
1479 | */ | |
1480 | vector_reg = (vector >> 5) & 0x7F; | |
1481 | vector_bit = vector & 0x1F; | |
1482 | mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); | |
1483 | mta_reg |= (1 << vector_bit); | |
1484 | IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); | |
1485 | } | |
1486 | ||
9a799d71 | 1487 | /** |
c44ade9e | 1488 | * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses |
9a799d71 AK |
1489 | * @hw: pointer to hardware structure |
1490 | * @mc_addr_list: the list of new multicast addresses | |
1491 | * @mc_addr_count: number of addresses | |
2c5645cf | 1492 | * @next: iterator function to walk the multicast address list |
9a799d71 AK |
1493 | * |
1494 | * The given list replaces any existing list. Clears the MC addrs from receive | |
c44ade9e | 1495 | * address registers and the multicast table. Uses unused receive address |
9a799d71 AK |
1496 | * registers for the first multicast addresses, and hashes the rest into the |
1497 | * multicast table. | |
1498 | **/ | |
c44ade9e | 1499 | s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, |
b4617240 | 1500 | u32 mc_addr_count, ixgbe_mc_addr_itr next) |
9a799d71 AK |
1501 | { |
1502 | u32 i; | |
2c5645cf | 1503 | u32 vmdq; |
9a799d71 AK |
1504 | |
1505 | /* | |
1506 | * Set the new number of MC addresses that we are being requested to | |
1507 | * use. | |
1508 | */ | |
1509 | hw->addr_ctrl.num_mc_addrs = mc_addr_count; | |
9a799d71 AK |
1510 | hw->addr_ctrl.mta_in_use = 0; |
1511 | ||
9a799d71 AK |
1512 | /* Clear the MTA */ |
1513 | hw_dbg(hw, " Clearing MTA\n"); | |
2c5645cf | 1514 | for (i = 0; i < hw->mac.mcft_size; i++) |
9a799d71 AK |
1515 | IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); |
1516 | ||
1517 | /* Add the new addresses */ | |
1518 | for (i = 0; i < mc_addr_count; i++) { | |
1519 | hw_dbg(hw, " Adding the multicast addresses:\n"); | |
495dce12 | 1520 | ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); |
9a799d71 AK |
1521 | } |
1522 | ||
1523 | /* Enable mta */ | |
1524 | if (hw->addr_ctrl.mta_in_use > 0) | |
1525 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, | |
b4617240 | 1526 | IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); |
9a799d71 | 1527 | |
c44ade9e | 1528 | hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); |
9a799d71 AK |
1529 | return 0; |
1530 | } | |
1531 | ||
1532 | /** | |
c44ade9e | 1533 | * ixgbe_enable_mc_generic - Enable multicast address in RAR |
9a799d71 AK |
1534 | * @hw: pointer to hardware structure |
1535 | * | |
c44ade9e | 1536 | * Enables multicast address in RAR and the use of the multicast hash table. |
9a799d71 | 1537 | **/ |
c44ade9e | 1538 | s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) |
9a799d71 | 1539 | { |
c44ade9e JB |
1540 | u32 i; |
1541 | u32 rar_entries = hw->mac.num_rar_entries; | |
1542 | struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; | |
9a799d71 | 1543 | |
c44ade9e JB |
1544 | if (a->mc_addr_in_rar_count > 0) |
1545 | for (i = (rar_entries - a->mc_addr_in_rar_count); | |
1546 | i < rar_entries; i++) | |
1547 | ixgbe_enable_rar(hw, i); | |
9a799d71 | 1548 | |
c44ade9e JB |
1549 | if (a->mta_in_use > 0) |
1550 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | | |
1551 | hw->mac.mc_filter_type); | |
9a799d71 AK |
1552 | |
1553 | return 0; | |
1554 | } | |
1555 | ||
1556 | /** | |
c44ade9e | 1557 | * ixgbe_disable_mc_generic - Disable multicast address in RAR |
9a799d71 | 1558 | * @hw: pointer to hardware structure |
9a799d71 | 1559 | * |
c44ade9e | 1560 | * Disables multicast address in RAR and the use of the multicast hash table. |
9a799d71 | 1561 | **/ |
c44ade9e | 1562 | s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) |
9a799d71 | 1563 | { |
c44ade9e JB |
1564 | u32 i; |
1565 | u32 rar_entries = hw->mac.num_rar_entries; | |
1566 | struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; | |
2b9ade93 | 1567 | |
c44ade9e JB |
1568 | if (a->mc_addr_in_rar_count > 0) |
1569 | for (i = (rar_entries - a->mc_addr_in_rar_count); | |
1570 | i < rar_entries; i++) | |
1571 | ixgbe_disable_rar(hw, i); | |
9a799d71 | 1572 | |
c44ade9e JB |
1573 | if (a->mta_in_use > 0) |
1574 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); | |
9a799d71 AK |
1575 | |
1576 | return 0; | |
1577 | } | |
1578 | ||
11afc1b1 PW |
1579 | /** |
1580 | * ixgbe_fc_enable - Enable flow control | |
1581 | * @hw: pointer to hardware structure | |
1582 | * @packetbuf_num: packet buffer number (0-7) | |
1583 | * | |
1584 | * Enable flow control according to the current settings. | |
1585 | **/ | |
1586 | s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num) | |
1587 | { | |
1588 | s32 ret_val = 0; | |
1589 | u32 mflcn_reg; | |
1590 | u32 fccfg_reg; | |
1591 | u32 reg; | |
70b77628 PWJ |
1592 | u32 rx_pba_size; |
1593 | ||
1594 | #ifdef CONFIG_DCB | |
1595 | if (hw->fc.requested_mode == ixgbe_fc_pfc) | |
1596 | goto out; | |
1597 | ||
1598 | #endif /* CONFIG_DCB */ | |
11afc1b1 PW |
1599 | |
1600 | mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
1601 | mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE); | |
1602 | ||
1603 | fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
1604 | fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); | |
1605 | ||
1606 | /* | |
1607 | * The possible values of fc.current_mode are: | |
1608 | * 0: Flow control is completely disabled | |
1609 | * 1: Rx flow control is enabled (we can receive pause frames, | |
1610 | * but not send pause frames). | |
bb3daa4a PW |
1611 | * 2: Tx flow control is enabled (we can send pause frames but |
1612 | * we do not support receiving pause frames). | |
11afc1b1 | 1613 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
bb3daa4a | 1614 | * 4: Priority Flow Control is enabled. |
11afc1b1 PW |
1615 | * other: Invalid. |
1616 | */ | |
1617 | switch (hw->fc.current_mode) { | |
1618 | case ixgbe_fc_none: | |
1619 | /* Flow control completely disabled by software override. */ | |
1620 | break; | |
1621 | case ixgbe_fc_rx_pause: | |
1622 | /* | |
1623 | * Rx Flow control is enabled and Tx Flow control is | |
1624 | * disabled by software override. Since there really | |
1625 | * isn't a way to advertise that we are capable of RX | |
1626 | * Pause ONLY, we will advertise that we support both | |
1627 | * symmetric and asymmetric Rx PAUSE. Later, we will | |
1628 | * disable the adapter's ability to send PAUSE frames. | |
1629 | */ | |
1630 | mflcn_reg |= IXGBE_MFLCN_RFCE; | |
1631 | break; | |
1632 | case ixgbe_fc_tx_pause: | |
1633 | /* | |
1634 | * Tx Flow control is enabled, and Rx Flow control is | |
1635 | * disabled by software override. | |
1636 | */ | |
1637 | fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; | |
1638 | break; | |
1639 | case ixgbe_fc_full: | |
1640 | /* Flow control (both Rx and Tx) is enabled by SW override. */ | |
1641 | mflcn_reg |= IXGBE_MFLCN_RFCE; | |
1642 | fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; | |
1643 | break; | |
bb3daa4a PW |
1644 | #ifdef CONFIG_DCB |
1645 | case ixgbe_fc_pfc: | |
1646 | goto out; | |
1647 | break; | |
1648 | #endif | |
11afc1b1 PW |
1649 | default: |
1650 | hw_dbg(hw, "Flow control param set incorrectly\n"); | |
1651 | ret_val = -IXGBE_ERR_CONFIG; | |
1652 | goto out; | |
1653 | break; | |
1654 | } | |
1655 | ||
1656 | /* Enable 802.3x based flow control settings. */ | |
2132d381 | 1657 | mflcn_reg |= IXGBE_MFLCN_DPF; |
11afc1b1 PW |
1658 | IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); |
1659 | IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); | |
1660 | ||
70b77628 PWJ |
1661 | reg = IXGBE_READ_REG(hw, IXGBE_MTQC); |
1662 | /* Thresholds are different for link flow control when in DCB mode */ | |
1663 | if (reg & IXGBE_MTQC_RT_ENA) { | |
70b77628 | 1664 | /* Always disable XON for LFC when in DCB mode */ |
264857b8 PWJ |
1665 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), 0); |
1666 | ||
1667 | rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num)); | |
70b77628 PWJ |
1668 | reg = (rx_pba_size >> 2) & 0xFFE0; |
1669 | if (hw->fc.current_mode & ixgbe_fc_tx_pause) | |
1670 | reg |= IXGBE_FCRTH_FCEN; | |
1671 | IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg); | |
1672 | } else { | |
1673 | /* | |
1674 | * Set up and enable Rx high/low water mark thresholds, | |
1675 | * enable XON. | |
1676 | */ | |
1677 | if (hw->fc.current_mode & ixgbe_fc_tx_pause) { | |
1678 | if (hw->fc.send_xon) { | |
1679 | IXGBE_WRITE_REG(hw, | |
1680 | IXGBE_FCRTL_82599(packetbuf_num), | |
1681 | (hw->fc.low_water | | |
1682 | IXGBE_FCRTL_XONE)); | |
1683 | } else { | |
1684 | IXGBE_WRITE_REG(hw, | |
1685 | IXGBE_FCRTL_82599(packetbuf_num), | |
1686 | hw->fc.low_water); | |
1687 | } | |
1688 | ||
1689 | IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), | |
1690 | (hw->fc.high_water | IXGBE_FCRTH_FCEN)); | |
1691 | } | |
11afc1b1 PW |
1692 | } |
1693 | ||
1694 | /* Configure pause time (2 TCs per register) */ | |
70b77628 | 1695 | reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); |
11afc1b1 PW |
1696 | if ((packetbuf_num & 1) == 0) |
1697 | reg = (reg & 0xFFFF0000) | hw->fc.pause_time; | |
1698 | else | |
1699 | reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); | |
1700 | IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); | |
1701 | ||
1702 | IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); | |
1703 | ||
1704 | out: | |
1705 | return ret_val; | |
1706 | } | |
1707 | ||
0ecc061d PWJ |
1708 | /** |
1709 | * ixgbe_fc_autoneg - Configure flow control | |
1710 | * @hw: pointer to hardware structure | |
1711 | * | |
1712 | * Negotiates flow control capabilities with link partner using autoneg and | |
1713 | * applies the results. | |
1714 | **/ | |
1715 | s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw) | |
1716 | { | |
1717 | s32 ret_val = 0; | |
1718 | u32 i, reg, pcs_anadv_reg, pcs_lpab_reg; | |
1719 | ||
1720 | reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); | |
1721 | ||
1722 | /* | |
1723 | * The possible values of fc.current_mode are: | |
1724 | * 0: Flow control is completely disabled | |
1725 | * 1: Rx flow control is enabled (we can receive pause frames, | |
1726 | * but not send pause frames). | |
1727 | * 2: Tx flow control is enabled (we can send pause frames but | |
1728 | * we do not support receiving pause frames). | |
1729 | * 3: Both Rx and Tx flow control (symmetric) are enabled. | |
bb3daa4a | 1730 | * 4: Priority Flow Control is enabled. |
0ecc061d PWJ |
1731 | * other: Invalid. |
1732 | */ | |
1733 | switch (hw->fc.current_mode) { | |
1734 | case ixgbe_fc_none: | |
1735 | /* Flow control completely disabled by software override. */ | |
1736 | reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); | |
1737 | break; | |
1738 | case ixgbe_fc_rx_pause: | |
1739 | /* | |
1740 | * Rx Flow control is enabled and Tx Flow control is | |
1741 | * disabled by software override. Since there really | |
1742 | * isn't a way to advertise that we are capable of RX | |
1743 | * Pause ONLY, we will advertise that we support both | |
1744 | * symmetric and asymmetric Rx PAUSE. Later, we will | |
1745 | * disable the adapter's ability to send PAUSE frames. | |
1746 | */ | |
1747 | reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); | |
1748 | break; | |
1749 | case ixgbe_fc_tx_pause: | |
1750 | /* | |
1751 | * Tx Flow control is enabled, and Rx Flow control is | |
1752 | * disabled by software override. | |
1753 | */ | |
1754 | reg |= (IXGBE_PCS1GANA_ASM_PAUSE); | |
1755 | reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE); | |
1756 | break; | |
1757 | case ixgbe_fc_full: | |
1758 | /* Flow control (both Rx and Tx) is enabled by SW override. */ | |
1759 | reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); | |
1760 | break; | |
bb3daa4a PW |
1761 | #ifdef CONFIG_DCB |
1762 | case ixgbe_fc_pfc: | |
1763 | goto out; | |
1764 | break; | |
1765 | #endif | |
0ecc061d PWJ |
1766 | default: |
1767 | hw_dbg(hw, "Flow control param set incorrectly\n"); | |
1768 | ret_val = -IXGBE_ERR_CONFIG; | |
1769 | goto out; | |
1770 | break; | |
1771 | } | |
1772 | ||
1773 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); | |
1774 | reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); | |
1775 | ||
1776 | /* Set PCS register for autoneg */ | |
1777 | /* Enable and restart autoneg */ | |
1778 | reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART; | |
1779 | ||
1780 | /* Disable AN timeout */ | |
1781 | if (hw->fc.strict_ieee) | |
1782 | reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; | |
1783 | ||
1784 | hw_dbg(hw, "Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg); | |
1785 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); | |
1786 | ||
1787 | /* See if autonegotiation has succeeded */ | |
1788 | hw->mac.autoneg_succeeded = 0; | |
1789 | for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { | |
1790 | msleep(10); | |
1791 | reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); | |
1792 | if ((reg & (IXGBE_PCS1GLSTA_LINK_OK | | |
1793 | IXGBE_PCS1GLSTA_AN_COMPLETE)) == | |
1794 | (IXGBE_PCS1GLSTA_LINK_OK | | |
1795 | IXGBE_PCS1GLSTA_AN_COMPLETE)) { | |
1796 | if (!(reg & IXGBE_PCS1GLSTA_AN_TIMED_OUT)) | |
1797 | hw->mac.autoneg_succeeded = 1; | |
1798 | break; | |
1799 | } | |
1800 | } | |
1801 | ||
1802 | if (!hw->mac.autoneg_succeeded) { | |
1803 | /* Autoneg failed to achieve a link, so we turn fc off */ | |
1804 | hw->fc.current_mode = ixgbe_fc_none; | |
1805 | hw_dbg(hw, "Flow Control = NONE.\n"); | |
1806 | goto out; | |
1807 | } | |
1808 | ||
1809 | /* | |
1810 | * Read the AN advertisement and LP ability registers and resolve | |
1811 | * local flow control settings accordingly | |
1812 | */ | |
1813 | pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); | |
1814 | pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); | |
1815 | if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | |
1816 | (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { | |
1817 | /* | |
1818 | * Now we need to check if the user selected Rx ONLY | |
1819 | * of pause frames. In this case, we had to advertise | |
1820 | * FULL flow control because we could not advertise RX | |
1821 | * ONLY. Hence, we must now check to see if we need to | |
1822 | * turn OFF the TRANSMISSION of PAUSE frames. | |
1823 | */ | |
1824 | if (hw->fc.requested_mode == ixgbe_fc_full) { | |
1825 | hw->fc.current_mode = ixgbe_fc_full; | |
1826 | hw_dbg(hw, "Flow Control = FULL.\n"); | |
1827 | } else { | |
1828 | hw->fc.current_mode = ixgbe_fc_rx_pause; | |
1829 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); | |
1830 | } | |
1831 | } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | |
1832 | (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && | |
1833 | (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | |
1834 | (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { | |
1835 | hw->fc.current_mode = ixgbe_fc_tx_pause; | |
1836 | hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); | |
1837 | } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | |
1838 | (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && | |
1839 | !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | |
1840 | (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { | |
1841 | hw->fc.current_mode = ixgbe_fc_rx_pause; | |
1842 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); | |
1843 | } else { | |
1844 | hw->fc.current_mode = ixgbe_fc_none; | |
1845 | hw_dbg(hw, "Flow Control = NONE.\n"); | |
1846 | } | |
1847 | ||
1848 | out: | |
1849 | return ret_val; | |
1850 | } | |
1851 | ||
11afc1b1 PW |
1852 | /** |
1853 | * ixgbe_setup_fc_generic - Set up flow control | |
1854 | * @hw: pointer to hardware structure | |
1855 | * | |
1856 | * Sets up flow control. | |
1857 | **/ | |
1858 | s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num) | |
1859 | { | |
1860 | s32 ret_val = 0; | |
1861 | ixgbe_link_speed speed; | |
1862 | bool link_up; | |
1863 | ||
bb3daa4a PW |
1864 | #ifdef CONFIG_DCB |
1865 | if (hw->fc.requested_mode == ixgbe_fc_pfc) { | |
1866 | hw->fc.current_mode = hw->fc.requested_mode; | |
1867 | goto out; | |
1868 | } | |
1869 | ||
1870 | #endif | |
11afc1b1 PW |
1871 | /* Validate the packetbuf configuration */ |
1872 | if (packetbuf_num < 0 || packetbuf_num > 7) { | |
1873 | hw_dbg(hw, "Invalid packet buffer number [%d], expected range " | |
1874 | "is 0-7\n", packetbuf_num); | |
1875 | ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; | |
1876 | goto out; | |
1877 | } | |
1878 | ||
1879 | /* | |
1880 | * Validate the water mark configuration. Zero water marks are invalid | |
1881 | * because it causes the controller to just blast out fc packets. | |
1882 | */ | |
1883 | if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { | |
d3e9c56c PW |
1884 | if (hw->fc.requested_mode != ixgbe_fc_none) { |
1885 | hw_dbg(hw, "Invalid water mark configuration\n"); | |
1886 | ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; | |
1887 | goto out; | |
1888 | } | |
11afc1b1 PW |
1889 | } |
1890 | ||
1891 | /* | |
1892 | * Validate the requested mode. Strict IEEE mode does not allow | |
1893 | * ixgbe_fc_rx_pause because it will cause testing anomalies. | |
1894 | */ | |
1895 | if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { | |
1896 | hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict " | |
1897 | "IEEE mode\n"); | |
1898 | ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; | |
1899 | goto out; | |
1900 | } | |
1901 | ||
1902 | /* | |
1903 | * 10gig parts do not have a word in the EEPROM to determine the | |
1904 | * default flow control setting, so we explicitly set it to full. | |
1905 | */ | |
1906 | if (hw->fc.requested_mode == ixgbe_fc_default) | |
1907 | hw->fc.requested_mode = ixgbe_fc_full; | |
1908 | ||
1909 | /* | |
1910 | * Save off the requested flow control mode for use later. Depending | |
1911 | * on the link partner's capabilities, we may or may not use this mode. | |
1912 | */ | |
1913 | hw->fc.current_mode = hw->fc.requested_mode; | |
1914 | ||
1915 | /* Decide whether to use autoneg or not. */ | |
1916 | hw->mac.ops.check_link(hw, &speed, &link_up, false); | |
71fd570b DS |
1917 | if (!hw->fc.disable_fc_autoneg && hw->phy.multispeed_fiber && |
1918 | (speed == IXGBE_LINK_SPEED_1GB_FULL)) | |
11afc1b1 PW |
1919 | ret_val = ixgbe_fc_autoneg(hw); |
1920 | ||
1921 | if (ret_val) | |
1922 | goto out; | |
1923 | ||
1924 | ret_val = ixgbe_fc_enable(hw, packetbuf_num); | |
1925 | ||
1926 | out: | |
1927 | return ret_val; | |
1928 | } | |
1929 | ||
9a799d71 AK |
1930 | /** |
1931 | * ixgbe_disable_pcie_master - Disable PCI-express master access | |
1932 | * @hw: pointer to hardware structure | |
1933 | * | |
1934 | * Disables PCI-Express master access and verifies there are no pending | |
1935 | * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable | |
1936 | * bit hasn't caused the master requests to be disabled, else 0 | |
1937 | * is returned signifying master requests disabled. | |
1938 | **/ | |
1939 | s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) | |
1940 | { | |
c44ade9e JB |
1941 | u32 i; |
1942 | u32 reg_val; | |
1943 | u32 number_of_queues; | |
9a799d71 AK |
1944 | s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; |
1945 | ||
c44ade9e JB |
1946 | /* Disable the receive unit by stopping each queue */ |
1947 | number_of_queues = hw->mac.max_rx_queues; | |
1948 | for (i = 0; i < number_of_queues; i++) { | |
1949 | reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
1950 | if (reg_val & IXGBE_RXDCTL_ENABLE) { | |
1951 | reg_val &= ~IXGBE_RXDCTL_ENABLE; | |
1952 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); | |
1953 | } | |
1954 | } | |
1955 | ||
1956 | reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
1957 | reg_val |= IXGBE_CTRL_GIO_DIS; | |
1958 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val); | |
9a799d71 AK |
1959 | |
1960 | for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { | |
1961 | if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { | |
1962 | status = 0; | |
1963 | break; | |
1964 | } | |
1965 | udelay(100); | |
1966 | } | |
1967 | ||
1968 | return status; | |
1969 | } | |
1970 | ||
1971 | ||
1972 | /** | |
c44ade9e | 1973 | * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore |
9a799d71 | 1974 | * @hw: pointer to hardware structure |
c44ade9e | 1975 | * @mask: Mask to specify which semaphore to acquire |
9a799d71 | 1976 | * |
c44ade9e | 1977 | * Acquires the SWFW semaphore thought the GSSR register for the specified |
9a799d71 AK |
1978 | * function (CSR, PHY0, PHY1, EEPROM, Flash) |
1979 | **/ | |
1980 | s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) | |
1981 | { | |
1982 | u32 gssr; | |
1983 | u32 swmask = mask; | |
1984 | u32 fwmask = mask << 5; | |
1985 | s32 timeout = 200; | |
1986 | ||
1987 | while (timeout) { | |
1988 | if (ixgbe_get_eeprom_semaphore(hw)) | |
1989 | return -IXGBE_ERR_SWFW_SYNC; | |
1990 | ||
1991 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); | |
1992 | if (!(gssr & (fwmask | swmask))) | |
1993 | break; | |
1994 | ||
1995 | /* | |
1996 | * Firmware currently using resource (fwmask) or other software | |
1997 | * thread currently using resource (swmask) | |
1998 | */ | |
1999 | ixgbe_release_eeprom_semaphore(hw); | |
2000 | msleep(5); | |
2001 | timeout--; | |
2002 | } | |
2003 | ||
2004 | if (!timeout) { | |
2005 | hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n"); | |
2006 | return -IXGBE_ERR_SWFW_SYNC; | |
2007 | } | |
2008 | ||
2009 | gssr |= swmask; | |
2010 | IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); | |
2011 | ||
2012 | ixgbe_release_eeprom_semaphore(hw); | |
2013 | return 0; | |
2014 | } | |
2015 | ||
2016 | /** | |
2017 | * ixgbe_release_swfw_sync - Release SWFW semaphore | |
2018 | * @hw: pointer to hardware structure | |
c44ade9e | 2019 | * @mask: Mask to specify which semaphore to release |
9a799d71 | 2020 | * |
c44ade9e | 2021 | * Releases the SWFW semaphore thought the GSSR register for the specified |
9a799d71 AK |
2022 | * function (CSR, PHY0, PHY1, EEPROM, Flash) |
2023 | **/ | |
2024 | void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) | |
2025 | { | |
2026 | u32 gssr; | |
2027 | u32 swmask = mask; | |
2028 | ||
2029 | ixgbe_get_eeprom_semaphore(hw); | |
2030 | ||
2031 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); | |
2032 | gssr &= ~swmask; | |
2033 | IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); | |
2034 | ||
2035 | ixgbe_release_eeprom_semaphore(hw); | |
2036 | } | |
2037 | ||
11afc1b1 PW |
2038 | /** |
2039 | * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit | |
2040 | * @hw: pointer to hardware structure | |
2041 | * @regval: register value to write to RXCTRL | |
2042 | * | |
2043 | * Enables the Rx DMA unit | |
2044 | **/ | |
2045 | s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) | |
2046 | { | |
2047 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); | |
2048 | ||
2049 | return 0; | |
2050 | } | |
87c12017 PW |
2051 | |
2052 | /** | |
2053 | * ixgbe_blink_led_start_generic - Blink LED based on index. | |
2054 | * @hw: pointer to hardware structure | |
2055 | * @index: led number to blink | |
2056 | **/ | |
2057 | s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) | |
2058 | { | |
2059 | ixgbe_link_speed speed = 0; | |
2060 | bool link_up = 0; | |
2061 | u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
2062 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | |
2063 | ||
2064 | /* | |
2065 | * Link must be up to auto-blink the LEDs; | |
2066 | * Force it if link is down. | |
2067 | */ | |
2068 | hw->mac.ops.check_link(hw, &speed, &link_up, false); | |
2069 | ||
2070 | if (!link_up) { | |
2071 | autoc_reg |= IXGBE_AUTOC_FLU; | |
2072 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); | |
2073 | msleep(10); | |
2074 | } | |
2075 | ||
2076 | led_reg &= ~IXGBE_LED_MODE_MASK(index); | |
2077 | led_reg |= IXGBE_LED_BLINK(index); | |
2078 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); | |
2079 | IXGBE_WRITE_FLUSH(hw); | |
2080 | ||
2081 | return 0; | |
2082 | } | |
2083 | ||
2084 | /** | |
2085 | * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. | |
2086 | * @hw: pointer to hardware structure | |
2087 | * @index: led number to stop blinking | |
2088 | **/ | |
2089 | s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) | |
2090 | { | |
2091 | u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
2092 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | |
2093 | ||
2094 | autoc_reg &= ~IXGBE_AUTOC_FLU; | |
2095 | autoc_reg |= IXGBE_AUTOC_AN_RESTART; | |
2096 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); | |
2097 | ||
2098 | led_reg &= ~IXGBE_LED_MODE_MASK(index); | |
2099 | led_reg &= ~IXGBE_LED_BLINK(index); | |
2100 | led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); | |
2101 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); | |
2102 | IXGBE_WRITE_FLUSH(hw); | |
2103 | ||
2104 | return 0; | |
2105 | } |