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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
3efac5a0 | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/pci.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/sched.h> | |
31 | ||
11afc1b1 | 32 | #include "ixgbe.h" |
9a799d71 AK |
33 | #include "ixgbe_common.h" |
34 | #include "ixgbe_phy.h" | |
35 | ||
9a799d71 | 36 | static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw); |
c44ade9e | 37 | static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); |
9a799d71 AK |
38 | static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); |
39 | static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); | |
c44ade9e JB |
40 | static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); |
41 | static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); | |
42 | static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, | |
43 | u16 count); | |
44 | static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); | |
45 | static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); | |
46 | static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); | |
47 | static void ixgbe_release_eeprom(struct ixgbe_hw *hw); | |
9a799d71 AK |
48 | static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw); |
49 | ||
c44ade9e JB |
50 | static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index); |
51 | static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index); | |
9a799d71 AK |
52 | static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); |
53 | static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr); | |
c44ade9e | 54 | static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); |
9a799d71 AK |
55 | |
56 | /** | |
c44ade9e | 57 | * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx |
9a799d71 AK |
58 | * @hw: pointer to hardware structure |
59 | * | |
60 | * Starts the hardware by filling the bus info structure and media type, clears | |
61 | * all on chip counters, initializes receive address registers, multicast | |
62 | * table, VLAN filter table, calls routine to set up link and flow control | |
63 | * settings, and leaves transmit and receive units disabled and uninitialized | |
64 | **/ | |
c44ade9e | 65 | s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
66 | { |
67 | u32 ctrl_ext; | |
68 | ||
69 | /* Set the media type */ | |
70 | hw->phy.media_type = hw->mac.ops.get_media_type(hw); | |
71 | ||
72 | /* Identify the PHY */ | |
c44ade9e | 73 | hw->phy.ops.identify(hw); |
9a799d71 AK |
74 | |
75 | /* | |
76 | * Store MAC address from RAR0, clear receive address registers, and | |
77 | * clear the multicast table | |
78 | */ | |
c44ade9e | 79 | hw->mac.ops.init_rx_addrs(hw); |
9a799d71 AK |
80 | |
81 | /* Clear the VLAN filter table */ | |
c44ade9e | 82 | hw->mac.ops.clear_vfta(hw); |
9a799d71 | 83 | |
9a799d71 | 84 | /* Clear statistics registers */ |
c44ade9e | 85 | hw->mac.ops.clear_hw_cntrs(hw); |
9a799d71 AK |
86 | |
87 | /* Set No Snoop Disable */ | |
88 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
89 | ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; | |
90 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
3957d63d | 91 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
92 | |
93 | /* Clear adapter stopped flag */ | |
94 | hw->adapter_stopped = false; | |
95 | ||
96 | return 0; | |
97 | } | |
98 | ||
99 | /** | |
c44ade9e | 100 | * ixgbe_init_hw_generic - Generic hardware initialization |
9a799d71 AK |
101 | * @hw: pointer to hardware structure |
102 | * | |
c44ade9e | 103 | * Initialize the hardware by resetting the hardware, filling the bus info |
9a799d71 AK |
104 | * structure and media type, clears all on chip counters, initializes receive |
105 | * address registers, multicast table, VLAN filter table, calls routine to set | |
106 | * up link and flow control settings, and leaves transmit and receive units | |
107 | * disabled and uninitialized | |
108 | **/ | |
c44ade9e | 109 | s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
110 | { |
111 | /* Reset the hardware */ | |
c44ade9e | 112 | hw->mac.ops.reset_hw(hw); |
9a799d71 AK |
113 | |
114 | /* Start the HW */ | |
c44ade9e | 115 | hw->mac.ops.start_hw(hw); |
9a799d71 AK |
116 | |
117 | return 0; | |
118 | } | |
119 | ||
120 | /** | |
c44ade9e | 121 | * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters |
9a799d71 AK |
122 | * @hw: pointer to hardware structure |
123 | * | |
124 | * Clears all hardware statistics counters by reading them from the hardware | |
125 | * Statistics counters are clear on read. | |
126 | **/ | |
c44ade9e | 127 | s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
128 | { |
129 | u16 i = 0; | |
130 | ||
131 | IXGBE_READ_REG(hw, IXGBE_CRCERRS); | |
132 | IXGBE_READ_REG(hw, IXGBE_ILLERRC); | |
133 | IXGBE_READ_REG(hw, IXGBE_ERRBC); | |
134 | IXGBE_READ_REG(hw, IXGBE_MSPDC); | |
135 | for (i = 0; i < 8; i++) | |
136 | IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
137 | ||
138 | IXGBE_READ_REG(hw, IXGBE_MLFC); | |
139 | IXGBE_READ_REG(hw, IXGBE_MRFC); | |
140 | IXGBE_READ_REG(hw, IXGBE_RLEC); | |
141 | IXGBE_READ_REG(hw, IXGBE_LXONTXC); | |
142 | IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
143 | IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); | |
144 | IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
145 | ||
146 | for (i = 0; i < 8; i++) { | |
147 | IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); | |
148 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
149 | IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
150 | IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); | |
151 | } | |
152 | ||
153 | IXGBE_READ_REG(hw, IXGBE_PRC64); | |
154 | IXGBE_READ_REG(hw, IXGBE_PRC127); | |
155 | IXGBE_READ_REG(hw, IXGBE_PRC255); | |
156 | IXGBE_READ_REG(hw, IXGBE_PRC511); | |
157 | IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
158 | IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
159 | IXGBE_READ_REG(hw, IXGBE_GPRC); | |
160 | IXGBE_READ_REG(hw, IXGBE_BPRC); | |
161 | IXGBE_READ_REG(hw, IXGBE_MPRC); | |
162 | IXGBE_READ_REG(hw, IXGBE_GPTC); | |
163 | IXGBE_READ_REG(hw, IXGBE_GORCL); | |
164 | IXGBE_READ_REG(hw, IXGBE_GORCH); | |
165 | IXGBE_READ_REG(hw, IXGBE_GOTCL); | |
166 | IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
167 | for (i = 0; i < 8; i++) | |
168 | IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
169 | IXGBE_READ_REG(hw, IXGBE_RUC); | |
170 | IXGBE_READ_REG(hw, IXGBE_RFC); | |
171 | IXGBE_READ_REG(hw, IXGBE_ROC); | |
172 | IXGBE_READ_REG(hw, IXGBE_RJC); | |
173 | IXGBE_READ_REG(hw, IXGBE_MNGPRC); | |
174 | IXGBE_READ_REG(hw, IXGBE_MNGPDC); | |
175 | IXGBE_READ_REG(hw, IXGBE_MNGPTC); | |
176 | IXGBE_READ_REG(hw, IXGBE_TORL); | |
177 | IXGBE_READ_REG(hw, IXGBE_TORH); | |
178 | IXGBE_READ_REG(hw, IXGBE_TPR); | |
179 | IXGBE_READ_REG(hw, IXGBE_TPT); | |
180 | IXGBE_READ_REG(hw, IXGBE_PTC64); | |
181 | IXGBE_READ_REG(hw, IXGBE_PTC127); | |
182 | IXGBE_READ_REG(hw, IXGBE_PTC255); | |
183 | IXGBE_READ_REG(hw, IXGBE_PTC511); | |
184 | IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
185 | IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
186 | IXGBE_READ_REG(hw, IXGBE_MPTC); | |
187 | IXGBE_READ_REG(hw, IXGBE_BPTC); | |
188 | for (i = 0; i < 16; i++) { | |
189 | IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
190 | IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
191 | IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
192 | IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
193 | } | |
194 | ||
195 | return 0; | |
196 | } | |
197 | ||
198 | /** | |
c44ade9e JB |
199 | * ixgbe_read_pba_num_generic - Reads part number from EEPROM |
200 | * @hw: pointer to hardware structure | |
201 | * @pba_num: stores the part number from the EEPROM | |
202 | * | |
203 | * Reads the part number from the EEPROM. | |
204 | **/ | |
205 | s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) | |
206 | { | |
207 | s32 ret_val; | |
208 | u16 data; | |
209 | ||
210 | ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); | |
211 | if (ret_val) { | |
212 | hw_dbg(hw, "NVM Read Error\n"); | |
213 | return ret_val; | |
214 | } | |
215 | *pba_num = (u32)(data << 16); | |
216 | ||
217 | ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); | |
218 | if (ret_val) { | |
219 | hw_dbg(hw, "NVM Read Error\n"); | |
220 | return ret_val; | |
221 | } | |
222 | *pba_num |= data; | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
227 | /** | |
228 | * ixgbe_get_mac_addr_generic - Generic get MAC address | |
9a799d71 AK |
229 | * @hw: pointer to hardware structure |
230 | * @mac_addr: Adapter MAC address | |
231 | * | |
232 | * Reads the adapter's MAC address from first Receive Address Register (RAR0) | |
233 | * A reset of the adapter must be performed prior to calling this function | |
234 | * in order for the MAC address to have been loaded from the EEPROM into RAR0 | |
235 | **/ | |
c44ade9e | 236 | s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) |
9a799d71 AK |
237 | { |
238 | u32 rar_high; | |
239 | u32 rar_low; | |
240 | u16 i; | |
241 | ||
242 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); | |
243 | rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); | |
244 | ||
245 | for (i = 0; i < 4; i++) | |
246 | mac_addr[i] = (u8)(rar_low >> (i*8)); | |
247 | ||
248 | for (i = 0; i < 2; i++) | |
249 | mac_addr[i+4] = (u8)(rar_high >> (i*8)); | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
11afc1b1 PW |
254 | /** |
255 | * ixgbe_get_bus_info_generic - Generic set PCI bus info | |
256 | * @hw: pointer to hardware structure | |
257 | * | |
258 | * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure | |
259 | **/ | |
260 | s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) | |
261 | { | |
262 | struct ixgbe_adapter *adapter = hw->back; | |
263 | struct ixgbe_mac_info *mac = &hw->mac; | |
264 | u16 link_status; | |
265 | ||
266 | hw->bus.type = ixgbe_bus_type_pci_express; | |
267 | ||
268 | /* Get the negotiated link width and speed from PCI config space */ | |
269 | pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS, | |
270 | &link_status); | |
271 | ||
272 | switch (link_status & IXGBE_PCI_LINK_WIDTH) { | |
273 | case IXGBE_PCI_LINK_WIDTH_1: | |
274 | hw->bus.width = ixgbe_bus_width_pcie_x1; | |
275 | break; | |
276 | case IXGBE_PCI_LINK_WIDTH_2: | |
277 | hw->bus.width = ixgbe_bus_width_pcie_x2; | |
278 | break; | |
279 | case IXGBE_PCI_LINK_WIDTH_4: | |
280 | hw->bus.width = ixgbe_bus_width_pcie_x4; | |
281 | break; | |
282 | case IXGBE_PCI_LINK_WIDTH_8: | |
283 | hw->bus.width = ixgbe_bus_width_pcie_x8; | |
284 | break; | |
285 | default: | |
286 | hw->bus.width = ixgbe_bus_width_unknown; | |
287 | break; | |
288 | } | |
289 | ||
290 | switch (link_status & IXGBE_PCI_LINK_SPEED) { | |
291 | case IXGBE_PCI_LINK_SPEED_2500: | |
292 | hw->bus.speed = ixgbe_bus_speed_2500; | |
293 | break; | |
294 | case IXGBE_PCI_LINK_SPEED_5000: | |
295 | hw->bus.speed = ixgbe_bus_speed_5000; | |
296 | break; | |
297 | default: | |
298 | hw->bus.speed = ixgbe_bus_speed_unknown; | |
299 | break; | |
300 | } | |
301 | ||
302 | mac->ops.set_lan_id(hw); | |
303 | ||
304 | return 0; | |
305 | } | |
306 | ||
307 | /** | |
308 | * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices | |
309 | * @hw: pointer to the HW structure | |
310 | * | |
311 | * Determines the LAN function id by reading memory-mapped registers | |
312 | * and swaps the port value if requested. | |
313 | **/ | |
314 | void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) | |
315 | { | |
316 | struct ixgbe_bus_info *bus = &hw->bus; | |
317 | u32 reg; | |
318 | ||
319 | reg = IXGBE_READ_REG(hw, IXGBE_STATUS); | |
320 | bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; | |
321 | bus->lan_id = bus->func; | |
322 | ||
323 | /* check for a port swap */ | |
324 | reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); | |
325 | if (reg & IXGBE_FACTPS_LFS) | |
326 | bus->func ^= 0x1; | |
327 | } | |
328 | ||
9a799d71 | 329 | /** |
c44ade9e | 330 | * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units |
9a799d71 AK |
331 | * @hw: pointer to hardware structure |
332 | * | |
333 | * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, | |
334 | * disables transmit and receive units. The adapter_stopped flag is used by | |
335 | * the shared code and drivers to determine if the adapter is in a stopped | |
336 | * state and should not touch the hardware. | |
337 | **/ | |
c44ade9e | 338 | s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
339 | { |
340 | u32 number_of_queues; | |
341 | u32 reg_val; | |
342 | u16 i; | |
343 | ||
344 | /* | |
345 | * Set the adapter_stopped flag so other driver functions stop touching | |
346 | * the hardware | |
347 | */ | |
348 | hw->adapter_stopped = true; | |
349 | ||
350 | /* Disable the receive unit */ | |
351 | reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
352 | reg_val &= ~(IXGBE_RXCTRL_RXEN); | |
353 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); | |
c44ade9e | 354 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
355 | msleep(2); |
356 | ||
357 | /* Clear interrupt mask to stop from interrupts being generated */ | |
358 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
359 | ||
360 | /* Clear any pending interrupts */ | |
361 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
362 | ||
363 | /* Disable the transmit unit. Each queue must be disabled. */ | |
c44ade9e | 364 | number_of_queues = hw->mac.max_tx_queues; |
9a799d71 AK |
365 | for (i = 0; i < number_of_queues; i++) { |
366 | reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
367 | if (reg_val & IXGBE_TXDCTL_ENABLE) { | |
368 | reg_val &= ~IXGBE_TXDCTL_ENABLE; | |
369 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); | |
370 | } | |
371 | } | |
372 | ||
c44ade9e JB |
373 | /* |
374 | * Prevent the PCI-E bus from from hanging by disabling PCI-E master | |
375 | * access and verify no pending requests | |
376 | */ | |
377 | if (ixgbe_disable_pcie_master(hw) != 0) | |
378 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | |
379 | ||
9a799d71 AK |
380 | return 0; |
381 | } | |
382 | ||
383 | /** | |
c44ade9e | 384 | * ixgbe_led_on_generic - Turns on the software controllable LEDs. |
9a799d71 AK |
385 | * @hw: pointer to hardware structure |
386 | * @index: led number to turn on | |
387 | **/ | |
c44ade9e | 388 | s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) |
9a799d71 AK |
389 | { |
390 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | |
391 | ||
392 | /* To turn on the LED, set mode to ON. */ | |
393 | led_reg &= ~IXGBE_LED_MODE_MASK(index); | |
394 | led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); | |
395 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); | |
3957d63d | 396 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
397 | |
398 | return 0; | |
399 | } | |
400 | ||
401 | /** | |
c44ade9e | 402 | * ixgbe_led_off_generic - Turns off the software controllable LEDs. |
9a799d71 AK |
403 | * @hw: pointer to hardware structure |
404 | * @index: led number to turn off | |
405 | **/ | |
c44ade9e | 406 | s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) |
9a799d71 AK |
407 | { |
408 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | |
409 | ||
410 | /* To turn off the LED, set mode to OFF. */ | |
411 | led_reg &= ~IXGBE_LED_MODE_MASK(index); | |
412 | led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); | |
413 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); | |
3957d63d | 414 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
415 | |
416 | return 0; | |
417 | } | |
418 | ||
9a799d71 | 419 | /** |
c44ade9e | 420 | * ixgbe_init_eeprom_params_generic - Initialize EEPROM params |
9a799d71 AK |
421 | * @hw: pointer to hardware structure |
422 | * | |
423 | * Initializes the EEPROM parameters ixgbe_eeprom_info within the | |
424 | * ixgbe_hw struct in order to set up EEPROM access. | |
425 | **/ | |
c44ade9e | 426 | s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
427 | { |
428 | struct ixgbe_eeprom_info *eeprom = &hw->eeprom; | |
429 | u32 eec; | |
430 | u16 eeprom_size; | |
431 | ||
432 | if (eeprom->type == ixgbe_eeprom_uninitialized) { | |
433 | eeprom->type = ixgbe_eeprom_none; | |
c44ade9e JB |
434 | /* Set default semaphore delay to 10ms which is a well |
435 | * tested value */ | |
436 | eeprom->semaphore_delay = 10; | |
9a799d71 AK |
437 | |
438 | /* | |
439 | * Check for EEPROM present first. | |
440 | * If not present leave as none | |
441 | */ | |
442 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
443 | if (eec & IXGBE_EEC_PRES) { | |
444 | eeprom->type = ixgbe_eeprom_spi; | |
445 | ||
446 | /* | |
447 | * SPI EEPROM is assumed here. This code would need to | |
448 | * change if a future EEPROM is not SPI. | |
449 | */ | |
450 | eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> | |
451 | IXGBE_EEC_SIZE_SHIFT); | |
452 | eeprom->word_size = 1 << (eeprom_size + | |
453 | IXGBE_EEPROM_WORD_SIZE_SHIFT); | |
454 | } | |
455 | ||
456 | if (eec & IXGBE_EEC_ADDR_SIZE) | |
457 | eeprom->address_bits = 16; | |
458 | else | |
459 | eeprom->address_bits = 8; | |
460 | hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: " | |
461 | "%d\n", eeprom->type, eeprom->word_size, | |
462 | eeprom->address_bits); | |
463 | } | |
464 | ||
465 | return 0; | |
466 | } | |
467 | ||
11afc1b1 PW |
468 | /** |
469 | * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM | |
470 | * @hw: pointer to hardware structure | |
471 | * @offset: offset within the EEPROM to be written to | |
472 | * @data: 16 bit word to be written to the EEPROM | |
473 | * | |
474 | * If ixgbe_eeprom_update_checksum is not called after this function, the | |
475 | * EEPROM will most likely contain an invalid checksum. | |
476 | **/ | |
477 | s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) | |
478 | { | |
479 | s32 status; | |
480 | u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; | |
481 | ||
482 | hw->eeprom.ops.init_params(hw); | |
483 | ||
484 | if (offset >= hw->eeprom.word_size) { | |
485 | status = IXGBE_ERR_EEPROM; | |
486 | goto out; | |
487 | } | |
488 | ||
489 | /* Prepare the EEPROM for writing */ | |
490 | status = ixgbe_acquire_eeprom(hw); | |
491 | ||
492 | if (status == 0) { | |
493 | if (ixgbe_ready_eeprom(hw) != 0) { | |
494 | ixgbe_release_eeprom(hw); | |
495 | status = IXGBE_ERR_EEPROM; | |
496 | } | |
497 | } | |
498 | ||
499 | if (status == 0) { | |
500 | ixgbe_standby_eeprom(hw); | |
501 | ||
502 | /* Send the WRITE ENABLE command (8 bit opcode ) */ | |
503 | ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, | |
504 | IXGBE_EEPROM_OPCODE_BITS); | |
505 | ||
506 | ixgbe_standby_eeprom(hw); | |
507 | ||
508 | /* | |
509 | * Some SPI eeproms use the 8th address bit embedded in the | |
510 | * opcode | |
511 | */ | |
512 | if ((hw->eeprom.address_bits == 8) && (offset >= 128)) | |
513 | write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; | |
514 | ||
515 | /* Send the Write command (8-bit opcode + addr) */ | |
516 | ixgbe_shift_out_eeprom_bits(hw, write_opcode, | |
517 | IXGBE_EEPROM_OPCODE_BITS); | |
518 | ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), | |
519 | hw->eeprom.address_bits); | |
520 | ||
521 | /* Send the data */ | |
522 | data = (data >> 8) | (data << 8); | |
523 | ixgbe_shift_out_eeprom_bits(hw, data, 16); | |
524 | ixgbe_standby_eeprom(hw); | |
525 | ||
526 | msleep(hw->eeprom.semaphore_delay); | |
527 | /* Done with writing - release the EEPROM */ | |
528 | ixgbe_release_eeprom(hw); | |
529 | } | |
530 | ||
531 | out: | |
532 | return status; | |
533 | } | |
534 | ||
9a799d71 | 535 | /** |
c44ade9e JB |
536 | * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang |
537 | * @hw: pointer to hardware structure | |
538 | * @offset: offset within the EEPROM to be read | |
539 | * @data: read 16 bit value from EEPROM | |
540 | * | |
541 | * Reads 16 bit value from EEPROM through bit-bang method | |
542 | **/ | |
543 | s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, | |
544 | u16 *data) | |
545 | { | |
546 | s32 status; | |
547 | u16 word_in; | |
548 | u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; | |
549 | ||
550 | hw->eeprom.ops.init_params(hw); | |
551 | ||
552 | if (offset >= hw->eeprom.word_size) { | |
553 | status = IXGBE_ERR_EEPROM; | |
554 | goto out; | |
555 | } | |
556 | ||
557 | /* Prepare the EEPROM for reading */ | |
558 | status = ixgbe_acquire_eeprom(hw); | |
559 | ||
560 | if (status == 0) { | |
561 | if (ixgbe_ready_eeprom(hw) != 0) { | |
562 | ixgbe_release_eeprom(hw); | |
563 | status = IXGBE_ERR_EEPROM; | |
564 | } | |
565 | } | |
566 | ||
567 | if (status == 0) { | |
568 | ixgbe_standby_eeprom(hw); | |
569 | ||
570 | /* | |
571 | * Some SPI eeproms use the 8th address bit embedded in the | |
572 | * opcode | |
573 | */ | |
574 | if ((hw->eeprom.address_bits == 8) && (offset >= 128)) | |
575 | read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; | |
576 | ||
577 | /* Send the READ command (opcode + addr) */ | |
578 | ixgbe_shift_out_eeprom_bits(hw, read_opcode, | |
579 | IXGBE_EEPROM_OPCODE_BITS); | |
580 | ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), | |
581 | hw->eeprom.address_bits); | |
582 | ||
583 | /* Read the data. */ | |
584 | word_in = ixgbe_shift_in_eeprom_bits(hw, 16); | |
585 | *data = (word_in >> 8) | (word_in << 8); | |
586 | ||
587 | /* End this read operation */ | |
588 | ixgbe_release_eeprom(hw); | |
589 | } | |
590 | ||
591 | out: | |
592 | return status; | |
593 | } | |
594 | ||
595 | /** | |
596 | * ixgbe_read_eeprom_generic - Read EEPROM word using EERD | |
9a799d71 AK |
597 | * @hw: pointer to hardware structure |
598 | * @offset: offset of word in the EEPROM to read | |
599 | * @data: word read from the EEPROM | |
600 | * | |
601 | * Reads a 16 bit word from the EEPROM using the EERD register. | |
602 | **/ | |
c44ade9e | 603 | s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) |
9a799d71 AK |
604 | { |
605 | u32 eerd; | |
606 | s32 status; | |
607 | ||
c44ade9e JB |
608 | hw->eeprom.ops.init_params(hw); |
609 | ||
610 | if (offset >= hw->eeprom.word_size) { | |
611 | status = IXGBE_ERR_EEPROM; | |
612 | goto out; | |
613 | } | |
614 | ||
9a799d71 AK |
615 | eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) + |
616 | IXGBE_EEPROM_READ_REG_START; | |
617 | ||
618 | IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); | |
619 | status = ixgbe_poll_eeprom_eerd_done(hw); | |
620 | ||
621 | if (status == 0) | |
622 | *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> | |
b4617240 | 623 | IXGBE_EEPROM_READ_REG_DATA); |
9a799d71 AK |
624 | else |
625 | hw_dbg(hw, "Eeprom read timed out\n"); | |
626 | ||
c44ade9e | 627 | out: |
9a799d71 AK |
628 | return status; |
629 | } | |
630 | ||
631 | /** | |
632 | * ixgbe_poll_eeprom_eerd_done - Poll EERD status | |
633 | * @hw: pointer to hardware structure | |
634 | * | |
635 | * Polls the status bit (bit 1) of the EERD to determine when the read is done. | |
636 | **/ | |
637 | static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw) | |
638 | { | |
639 | u32 i; | |
640 | u32 reg; | |
641 | s32 status = IXGBE_ERR_EEPROM; | |
642 | ||
643 | for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) { | |
644 | reg = IXGBE_READ_REG(hw, IXGBE_EERD); | |
645 | if (reg & IXGBE_EEPROM_READ_REG_DONE) { | |
646 | status = 0; | |
647 | break; | |
648 | } | |
649 | udelay(5); | |
650 | } | |
651 | return status; | |
652 | } | |
653 | ||
c44ade9e JB |
654 | /** |
655 | * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang | |
656 | * @hw: pointer to hardware structure | |
657 | * | |
658 | * Prepares EEPROM for access using bit-bang method. This function should | |
659 | * be called before issuing a command to the EEPROM. | |
660 | **/ | |
661 | static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) | |
662 | { | |
663 | s32 status = 0; | |
fc1f2095 | 664 | u32 eec = 0; |
c44ade9e JB |
665 | u32 i; |
666 | ||
667 | if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) | |
668 | status = IXGBE_ERR_SWFW_SYNC; | |
669 | ||
670 | if (status == 0) { | |
671 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
672 | ||
673 | /* Request EEPROM Access */ | |
674 | eec |= IXGBE_EEC_REQ; | |
675 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
676 | ||
677 | for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { | |
678 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
679 | if (eec & IXGBE_EEC_GNT) | |
680 | break; | |
681 | udelay(5); | |
682 | } | |
683 | ||
684 | /* Release if grant not acquired */ | |
685 | if (!(eec & IXGBE_EEC_GNT)) { | |
686 | eec &= ~IXGBE_EEC_REQ; | |
687 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
688 | hw_dbg(hw, "Could not acquire EEPROM grant\n"); | |
689 | ||
690 | ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | |
691 | status = IXGBE_ERR_EEPROM; | |
692 | } | |
693 | } | |
694 | ||
695 | /* Setup EEPROM for Read/Write */ | |
696 | if (status == 0) { | |
697 | /* Clear CS and SK */ | |
698 | eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); | |
699 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
700 | IXGBE_WRITE_FLUSH(hw); | |
701 | udelay(1); | |
702 | } | |
703 | return status; | |
704 | } | |
705 | ||
9a799d71 AK |
706 | /** |
707 | * ixgbe_get_eeprom_semaphore - Get hardware semaphore | |
708 | * @hw: pointer to hardware structure | |
709 | * | |
710 | * Sets the hardware semaphores so EEPROM access can occur for bit-bang method | |
711 | **/ | |
712 | static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) | |
713 | { | |
714 | s32 status = IXGBE_ERR_EEPROM; | |
715 | u32 timeout; | |
716 | u32 i; | |
717 | u32 swsm; | |
718 | ||
719 | /* Set timeout value based on size of EEPROM */ | |
720 | timeout = hw->eeprom.word_size + 1; | |
721 | ||
722 | /* Get SMBI software semaphore between device drivers first */ | |
723 | for (i = 0; i < timeout; i++) { | |
724 | /* | |
725 | * If the SMBI bit is 0 when we read it, then the bit will be | |
726 | * set and we have the semaphore | |
727 | */ | |
728 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | |
729 | if (!(swsm & IXGBE_SWSM_SMBI)) { | |
730 | status = 0; | |
731 | break; | |
732 | } | |
733 | msleep(1); | |
734 | } | |
735 | ||
736 | /* Now get the semaphore between SW/FW through the SWESMBI bit */ | |
737 | if (status == 0) { | |
738 | for (i = 0; i < timeout; i++) { | |
739 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | |
740 | ||
741 | /* Set the SW EEPROM semaphore bit to request access */ | |
742 | swsm |= IXGBE_SWSM_SWESMBI; | |
743 | IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); | |
744 | ||
745 | /* | |
746 | * If we set the bit successfully then we got the | |
747 | * semaphore. | |
748 | */ | |
749 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | |
750 | if (swsm & IXGBE_SWSM_SWESMBI) | |
751 | break; | |
752 | ||
753 | udelay(50); | |
754 | } | |
755 | ||
756 | /* | |
757 | * Release semaphores and return error if SW EEPROM semaphore | |
758 | * was not granted because we don't have access to the EEPROM | |
759 | */ | |
760 | if (i >= timeout) { | |
761 | hw_dbg(hw, "Driver can't access the Eeprom - Semaphore " | |
b4617240 | 762 | "not granted.\n"); |
9a799d71 AK |
763 | ixgbe_release_eeprom_semaphore(hw); |
764 | status = IXGBE_ERR_EEPROM; | |
765 | } | |
766 | } | |
767 | ||
768 | return status; | |
769 | } | |
770 | ||
771 | /** | |
772 | * ixgbe_release_eeprom_semaphore - Release hardware semaphore | |
773 | * @hw: pointer to hardware structure | |
774 | * | |
775 | * This function clears hardware semaphore bits. | |
776 | **/ | |
777 | static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) | |
778 | { | |
779 | u32 swsm; | |
780 | ||
781 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | |
782 | ||
783 | /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ | |
784 | swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); | |
785 | IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); | |
3957d63d | 786 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
787 | } |
788 | ||
c44ade9e JB |
789 | /** |
790 | * ixgbe_ready_eeprom - Polls for EEPROM ready | |
791 | * @hw: pointer to hardware structure | |
792 | **/ | |
793 | static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) | |
794 | { | |
795 | s32 status = 0; | |
796 | u16 i; | |
797 | u8 spi_stat_reg; | |
798 | ||
799 | /* | |
800 | * Read "Status Register" repeatedly until the LSB is cleared. The | |
801 | * EEPROM will signal that the command has been completed by clearing | |
802 | * bit 0 of the internal status register. If it's not cleared within | |
803 | * 5 milliseconds, then error out. | |
804 | */ | |
805 | for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { | |
806 | ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, | |
807 | IXGBE_EEPROM_OPCODE_BITS); | |
808 | spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); | |
809 | if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) | |
810 | break; | |
811 | ||
812 | udelay(5); | |
813 | ixgbe_standby_eeprom(hw); | |
814 | }; | |
815 | ||
816 | /* | |
817 | * On some parts, SPI write time could vary from 0-20mSec on 3.3V | |
818 | * devices (and only 0-5mSec on 5V devices) | |
819 | */ | |
820 | if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { | |
821 | hw_dbg(hw, "SPI EEPROM Status error\n"); | |
822 | status = IXGBE_ERR_EEPROM; | |
823 | } | |
824 | ||
825 | return status; | |
826 | } | |
827 | ||
828 | /** | |
829 | * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state | |
830 | * @hw: pointer to hardware structure | |
831 | **/ | |
832 | static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) | |
833 | { | |
834 | u32 eec; | |
835 | ||
836 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
837 | ||
838 | /* Toggle CS to flush commands */ | |
839 | eec |= IXGBE_EEC_CS; | |
840 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
841 | IXGBE_WRITE_FLUSH(hw); | |
842 | udelay(1); | |
843 | eec &= ~IXGBE_EEC_CS; | |
844 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
845 | IXGBE_WRITE_FLUSH(hw); | |
846 | udelay(1); | |
847 | } | |
848 | ||
849 | /** | |
850 | * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. | |
851 | * @hw: pointer to hardware structure | |
852 | * @data: data to send to the EEPROM | |
853 | * @count: number of bits to shift out | |
854 | **/ | |
855 | static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, | |
856 | u16 count) | |
857 | { | |
858 | u32 eec; | |
859 | u32 mask; | |
860 | u32 i; | |
861 | ||
862 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
863 | ||
864 | /* | |
865 | * Mask is used to shift "count" bits of "data" out to the EEPROM | |
866 | * one bit at a time. Determine the starting bit based on count | |
867 | */ | |
868 | mask = 0x01 << (count - 1); | |
869 | ||
870 | for (i = 0; i < count; i++) { | |
871 | /* | |
872 | * A "1" is shifted out to the EEPROM by setting bit "DI" to a | |
873 | * "1", and then raising and then lowering the clock (the SK | |
874 | * bit controls the clock input to the EEPROM). A "0" is | |
875 | * shifted out to the EEPROM by setting "DI" to "0" and then | |
876 | * raising and then lowering the clock. | |
877 | */ | |
878 | if (data & mask) | |
879 | eec |= IXGBE_EEC_DI; | |
880 | else | |
881 | eec &= ~IXGBE_EEC_DI; | |
882 | ||
883 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
884 | IXGBE_WRITE_FLUSH(hw); | |
885 | ||
886 | udelay(1); | |
887 | ||
888 | ixgbe_raise_eeprom_clk(hw, &eec); | |
889 | ixgbe_lower_eeprom_clk(hw, &eec); | |
890 | ||
891 | /* | |
892 | * Shift mask to signify next bit of data to shift in to the | |
893 | * EEPROM | |
894 | */ | |
895 | mask = mask >> 1; | |
896 | }; | |
897 | ||
898 | /* We leave the "DI" bit set to "0" when we leave this routine. */ | |
899 | eec &= ~IXGBE_EEC_DI; | |
900 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
901 | IXGBE_WRITE_FLUSH(hw); | |
902 | } | |
903 | ||
904 | /** | |
905 | * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM | |
906 | * @hw: pointer to hardware structure | |
907 | **/ | |
908 | static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) | |
909 | { | |
910 | u32 eec; | |
911 | u32 i; | |
912 | u16 data = 0; | |
913 | ||
914 | /* | |
915 | * In order to read a register from the EEPROM, we need to shift | |
916 | * 'count' bits in from the EEPROM. Bits are "shifted in" by raising | |
917 | * the clock input to the EEPROM (setting the SK bit), and then reading | |
918 | * the value of the "DO" bit. During this "shifting in" process the | |
919 | * "DI" bit should always be clear. | |
920 | */ | |
921 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
922 | ||
923 | eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); | |
924 | ||
925 | for (i = 0; i < count; i++) { | |
926 | data = data << 1; | |
927 | ixgbe_raise_eeprom_clk(hw, &eec); | |
928 | ||
929 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
930 | ||
931 | eec &= ~(IXGBE_EEC_DI); | |
932 | if (eec & IXGBE_EEC_DO) | |
933 | data |= 1; | |
934 | ||
935 | ixgbe_lower_eeprom_clk(hw, &eec); | |
936 | } | |
937 | ||
938 | return data; | |
939 | } | |
940 | ||
941 | /** | |
942 | * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. | |
943 | * @hw: pointer to hardware structure | |
944 | * @eec: EEC register's current value | |
945 | **/ | |
946 | static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) | |
947 | { | |
948 | /* | |
949 | * Raise the clock input to the EEPROM | |
950 | * (setting the SK bit), then delay | |
951 | */ | |
952 | *eec = *eec | IXGBE_EEC_SK; | |
953 | IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); | |
954 | IXGBE_WRITE_FLUSH(hw); | |
955 | udelay(1); | |
956 | } | |
957 | ||
958 | /** | |
959 | * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. | |
960 | * @hw: pointer to hardware structure | |
961 | * @eecd: EECD's current value | |
962 | **/ | |
963 | static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) | |
964 | { | |
965 | /* | |
966 | * Lower the clock input to the EEPROM (clearing the SK bit), then | |
967 | * delay | |
968 | */ | |
969 | *eec = *eec & ~IXGBE_EEC_SK; | |
970 | IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); | |
971 | IXGBE_WRITE_FLUSH(hw); | |
972 | udelay(1); | |
973 | } | |
974 | ||
975 | /** | |
976 | * ixgbe_release_eeprom - Release EEPROM, release semaphores | |
977 | * @hw: pointer to hardware structure | |
978 | **/ | |
979 | static void ixgbe_release_eeprom(struct ixgbe_hw *hw) | |
980 | { | |
981 | u32 eec; | |
982 | ||
983 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
984 | ||
985 | eec |= IXGBE_EEC_CS; /* Pull CS high */ | |
986 | eec &= ~IXGBE_EEC_SK; /* Lower SCK */ | |
987 | ||
988 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
989 | IXGBE_WRITE_FLUSH(hw); | |
990 | ||
991 | udelay(1); | |
992 | ||
993 | /* Stop requesting EEPROM access */ | |
994 | eec &= ~IXGBE_EEC_REQ; | |
995 | IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); | |
996 | ||
997 | ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | |
998 | } | |
999 | ||
9a799d71 AK |
1000 | /** |
1001 | * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum | |
1002 | * @hw: pointer to hardware structure | |
1003 | **/ | |
1004 | static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw) | |
1005 | { | |
1006 | u16 i; | |
1007 | u16 j; | |
1008 | u16 checksum = 0; | |
1009 | u16 length = 0; | |
1010 | u16 pointer = 0; | |
1011 | u16 word = 0; | |
1012 | ||
1013 | /* Include 0x0-0x3F in the checksum */ | |
1014 | for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { | |
c44ade9e | 1015 | if (hw->eeprom.ops.read(hw, i, &word) != 0) { |
9a799d71 AK |
1016 | hw_dbg(hw, "EEPROM read failed\n"); |
1017 | break; | |
1018 | } | |
1019 | checksum += word; | |
1020 | } | |
1021 | ||
1022 | /* Include all data from pointers except for the fw pointer */ | |
1023 | for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { | |
c44ade9e | 1024 | hw->eeprom.ops.read(hw, i, &pointer); |
9a799d71 AK |
1025 | |
1026 | /* Make sure the pointer seems valid */ | |
1027 | if (pointer != 0xFFFF && pointer != 0) { | |
c44ade9e | 1028 | hw->eeprom.ops.read(hw, pointer, &length); |
9a799d71 AK |
1029 | |
1030 | if (length != 0xFFFF && length != 0) { | |
1031 | for (j = pointer+1; j <= pointer+length; j++) { | |
c44ade9e | 1032 | hw->eeprom.ops.read(hw, j, &word); |
9a799d71 AK |
1033 | checksum += word; |
1034 | } | |
1035 | } | |
1036 | } | |
1037 | } | |
1038 | ||
1039 | checksum = (u16)IXGBE_EEPROM_SUM - checksum; | |
1040 | ||
1041 | return checksum; | |
1042 | } | |
1043 | ||
1044 | /** | |
c44ade9e | 1045 | * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum |
9a799d71 AK |
1046 | * @hw: pointer to hardware structure |
1047 | * @checksum_val: calculated checksum | |
1048 | * | |
1049 | * Performs checksum calculation and validates the EEPROM checksum. If the | |
1050 | * caller does not need checksum_val, the value can be NULL. | |
1051 | **/ | |
c44ade9e JB |
1052 | s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, |
1053 | u16 *checksum_val) | |
9a799d71 AK |
1054 | { |
1055 | s32 status; | |
1056 | u16 checksum; | |
1057 | u16 read_checksum = 0; | |
1058 | ||
1059 | /* | |
1060 | * Read the first word from the EEPROM. If this times out or fails, do | |
1061 | * not continue or we could be in for a very long wait while every | |
1062 | * EEPROM read fails | |
1063 | */ | |
c44ade9e | 1064 | status = hw->eeprom.ops.read(hw, 0, &checksum); |
9a799d71 AK |
1065 | |
1066 | if (status == 0) { | |
1067 | checksum = ixgbe_calc_eeprom_checksum(hw); | |
1068 | ||
c44ade9e | 1069 | hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); |
9a799d71 AK |
1070 | |
1071 | /* | |
1072 | * Verify read checksum from EEPROM is the same as | |
1073 | * calculated checksum | |
1074 | */ | |
1075 | if (read_checksum != checksum) | |
1076 | status = IXGBE_ERR_EEPROM_CHECKSUM; | |
1077 | ||
1078 | /* If the user cares, return the calculated checksum */ | |
1079 | if (checksum_val) | |
1080 | *checksum_val = checksum; | |
1081 | } else { | |
1082 | hw_dbg(hw, "EEPROM read failed\n"); | |
1083 | } | |
1084 | ||
1085 | return status; | |
1086 | } | |
1087 | ||
c44ade9e JB |
1088 | /** |
1089 | * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum | |
1090 | * @hw: pointer to hardware structure | |
1091 | **/ | |
1092 | s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) | |
1093 | { | |
1094 | s32 status; | |
1095 | u16 checksum; | |
1096 | ||
1097 | /* | |
1098 | * Read the first word from the EEPROM. If this times out or fails, do | |
1099 | * not continue or we could be in for a very long wait while every | |
1100 | * EEPROM read fails | |
1101 | */ | |
1102 | status = hw->eeprom.ops.read(hw, 0, &checksum); | |
1103 | ||
1104 | if (status == 0) { | |
1105 | checksum = ixgbe_calc_eeprom_checksum(hw); | |
1106 | status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, | |
1107 | checksum); | |
1108 | } else { | |
1109 | hw_dbg(hw, "EEPROM read failed\n"); | |
1110 | } | |
1111 | ||
1112 | return status; | |
1113 | } | |
1114 | ||
9a799d71 AK |
1115 | /** |
1116 | * ixgbe_validate_mac_addr - Validate MAC address | |
1117 | * @mac_addr: pointer to MAC address. | |
1118 | * | |
1119 | * Tests a MAC address to ensure it is a valid Individual Address | |
1120 | **/ | |
1121 | s32 ixgbe_validate_mac_addr(u8 *mac_addr) | |
1122 | { | |
1123 | s32 status = 0; | |
1124 | ||
1125 | /* Make sure it is not a multicast address */ | |
1126 | if (IXGBE_IS_MULTICAST(mac_addr)) | |
1127 | status = IXGBE_ERR_INVALID_MAC_ADDR; | |
1128 | /* Not a broadcast address */ | |
1129 | else if (IXGBE_IS_BROADCAST(mac_addr)) | |
1130 | status = IXGBE_ERR_INVALID_MAC_ADDR; | |
1131 | /* Reject the zero address */ | |
1132 | else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && | |
c44ade9e | 1133 | mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) |
9a799d71 AK |
1134 | status = IXGBE_ERR_INVALID_MAC_ADDR; |
1135 | ||
1136 | return status; | |
1137 | } | |
1138 | ||
1139 | /** | |
c44ade9e | 1140 | * ixgbe_set_rar_generic - Set Rx address register |
9a799d71 | 1141 | * @hw: pointer to hardware structure |
9a799d71 | 1142 | * @index: Receive address register to write |
c44ade9e JB |
1143 | * @addr: Address to put into receive address register |
1144 | * @vmdq: VMDq "set" or "pool" index | |
9a799d71 AK |
1145 | * @enable_addr: set flag that address is active |
1146 | * | |
1147 | * Puts an ethernet address into a receive address register. | |
1148 | **/ | |
c44ade9e JB |
1149 | s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, |
1150 | u32 enable_addr) | |
9a799d71 AK |
1151 | { |
1152 | u32 rar_low, rar_high; | |
c44ade9e JB |
1153 | u32 rar_entries = hw->mac.num_rar_entries; |
1154 | ||
1155 | /* setup VMDq pool selection before this RAR gets enabled */ | |
1156 | hw->mac.ops.set_vmdq(hw, index, vmdq); | |
9a799d71 | 1157 | |
c44ade9e JB |
1158 | /* Make sure we are using a valid rar index range */ |
1159 | if (index < rar_entries) { | |
b4617240 | 1160 | /* |
c44ade9e JB |
1161 | * HW expects these in little endian so we reverse the byte |
1162 | * order from network order (big endian) to little endian | |
b4617240 PW |
1163 | */ |
1164 | rar_low = ((u32)addr[0] | | |
1165 | ((u32)addr[1] << 8) | | |
1166 | ((u32)addr[2] << 16) | | |
1167 | ((u32)addr[3] << 24)); | |
c44ade9e JB |
1168 | /* |
1169 | * Some parts put the VMDq setting in the extra RAH bits, | |
1170 | * so save everything except the lower 16 bits that hold part | |
1171 | * of the address and the address valid bit. | |
1172 | */ | |
1173 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); | |
1174 | rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); | |
1175 | rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); | |
9a799d71 | 1176 | |
b4617240 PW |
1177 | if (enable_addr != 0) |
1178 | rar_high |= IXGBE_RAH_AV; | |
9a799d71 | 1179 | |
b4617240 PW |
1180 | IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); |
1181 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); | |
c44ade9e JB |
1182 | } else { |
1183 | hw_dbg(hw, "RAR index %d is out of range.\n", index); | |
1184 | } | |
1185 | ||
1186 | return 0; | |
1187 | } | |
1188 | ||
1189 | /** | |
1190 | * ixgbe_clear_rar_generic - Remove Rx address register | |
1191 | * @hw: pointer to hardware structure | |
1192 | * @index: Receive address register to write | |
1193 | * | |
1194 | * Clears an ethernet address from a receive address register. | |
1195 | **/ | |
1196 | s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) | |
1197 | { | |
1198 | u32 rar_high; | |
1199 | u32 rar_entries = hw->mac.num_rar_entries; | |
1200 | ||
1201 | /* Make sure we are using a valid rar index range */ | |
1202 | if (index < rar_entries) { | |
1203 | /* | |
1204 | * Some parts put the VMDq setting in the extra RAH bits, | |
1205 | * so save everything except the lower 16 bits that hold part | |
1206 | * of the address and the address valid bit. | |
1207 | */ | |
1208 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); | |
1209 | rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); | |
1210 | ||
1211 | IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); | |
1212 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); | |
1213 | } else { | |
1214 | hw_dbg(hw, "RAR index %d is out of range.\n", index); | |
1215 | } | |
1216 | ||
1217 | /* clear VMDq pool/queue selection for this RAR */ | |
1218 | hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); | |
9a799d71 AK |
1219 | |
1220 | return 0; | |
1221 | } | |
1222 | ||
1223 | /** | |
c44ade9e JB |
1224 | * ixgbe_enable_rar - Enable Rx address register |
1225 | * @hw: pointer to hardware structure | |
1226 | * @index: index into the RAR table | |
1227 | * | |
1228 | * Enables the select receive address register. | |
1229 | **/ | |
1230 | static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index) | |
1231 | { | |
1232 | u32 rar_high; | |
1233 | ||
1234 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); | |
1235 | rar_high |= IXGBE_RAH_AV; | |
1236 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); | |
1237 | } | |
1238 | ||
1239 | /** | |
1240 | * ixgbe_disable_rar - Disable Rx address register | |
1241 | * @hw: pointer to hardware structure | |
1242 | * @index: index into the RAR table | |
1243 | * | |
1244 | * Disables the select receive address register. | |
1245 | **/ | |
1246 | static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index) | |
1247 | { | |
1248 | u32 rar_high; | |
1249 | ||
1250 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); | |
1251 | rar_high &= (~IXGBE_RAH_AV); | |
1252 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); | |
1253 | } | |
1254 | ||
1255 | /** | |
1256 | * ixgbe_init_rx_addrs_generic - Initializes receive address filters. | |
9a799d71 AK |
1257 | * @hw: pointer to hardware structure |
1258 | * | |
1259 | * Places the MAC address in receive address register 0 and clears the rest | |
c44ade9e | 1260 | * of the receive address registers. Clears the multicast table. Assumes |
9a799d71 AK |
1261 | * the receiver is in reset when the routine is called. |
1262 | **/ | |
c44ade9e | 1263 | s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
1264 | { |
1265 | u32 i; | |
2c5645cf | 1266 | u32 rar_entries = hw->mac.num_rar_entries; |
9a799d71 AK |
1267 | |
1268 | /* | |
1269 | * If the current mac address is valid, assume it is a software override | |
1270 | * to the permanent address. | |
1271 | * Otherwise, use the permanent address from the eeprom. | |
1272 | */ | |
1273 | if (ixgbe_validate_mac_addr(hw->mac.addr) == | |
1274 | IXGBE_ERR_INVALID_MAC_ADDR) { | |
1275 | /* Get the MAC address from the RAR0 for later reference */ | |
c44ade9e | 1276 | hw->mac.ops.get_mac_addr(hw, hw->mac.addr); |
9a799d71 AK |
1277 | |
1278 | hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ", | |
b4617240 PW |
1279 | hw->mac.addr[0], hw->mac.addr[1], |
1280 | hw->mac.addr[2]); | |
9a799d71 | 1281 | hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3], |
b4617240 | 1282 | hw->mac.addr[4], hw->mac.addr[5]); |
9a799d71 AK |
1283 | } else { |
1284 | /* Setup the receive address. */ | |
1285 | hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); | |
1286 | hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ", | |
b4617240 PW |
1287 | hw->mac.addr[0], hw->mac.addr[1], |
1288 | hw->mac.addr[2]); | |
9a799d71 | 1289 | hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3], |
b4617240 | 1290 | hw->mac.addr[4], hw->mac.addr[5]); |
9a799d71 | 1291 | |
c44ade9e | 1292 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 | 1293 | } |
c44ade9e | 1294 | hw->addr_ctrl.overflow_promisc = 0; |
9a799d71 AK |
1295 | |
1296 | hw->addr_ctrl.rar_used_count = 1; | |
1297 | ||
1298 | /* Zero out the other receive addresses. */ | |
c44ade9e | 1299 | hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); |
9a799d71 AK |
1300 | for (i = 1; i < rar_entries; i++) { |
1301 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); | |
1302 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); | |
1303 | } | |
1304 | ||
1305 | /* Clear the MTA */ | |
1306 | hw->addr_ctrl.mc_addr_in_rar_count = 0; | |
1307 | hw->addr_ctrl.mta_in_use = 0; | |
1308 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); | |
1309 | ||
1310 | hw_dbg(hw, " Clearing MTA\n"); | |
2c5645cf | 1311 | for (i = 0; i < hw->mac.mcft_size; i++) |
9a799d71 AK |
1312 | IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); |
1313 | ||
c44ade9e JB |
1314 | if (hw->mac.ops.init_uta_tables) |
1315 | hw->mac.ops.init_uta_tables(hw); | |
1316 | ||
9a799d71 AK |
1317 | return 0; |
1318 | } | |
1319 | ||
2c5645cf CL |
1320 | /** |
1321 | * ixgbe_add_uc_addr - Adds a secondary unicast address. | |
1322 | * @hw: pointer to hardware structure | |
1323 | * @addr: new address | |
1324 | * | |
1325 | * Adds it to unused receive address register or goes into promiscuous mode. | |
1326 | **/ | |
c44ade9e | 1327 | static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) |
2c5645cf CL |
1328 | { |
1329 | u32 rar_entries = hw->mac.num_rar_entries; | |
1330 | u32 rar; | |
1331 | ||
1332 | hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", | |
1333 | addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); | |
1334 | ||
1335 | /* | |
1336 | * Place this address in the RAR if there is room, | |
1337 | * else put the controller into promiscuous mode | |
1338 | */ | |
1339 | if (hw->addr_ctrl.rar_used_count < rar_entries) { | |
1340 | rar = hw->addr_ctrl.rar_used_count - | |
1341 | hw->addr_ctrl.mc_addr_in_rar_count; | |
c44ade9e | 1342 | hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); |
2c5645cf CL |
1343 | hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar); |
1344 | hw->addr_ctrl.rar_used_count++; | |
1345 | } else { | |
1346 | hw->addr_ctrl.overflow_promisc++; | |
1347 | } | |
1348 | ||
1349 | hw_dbg(hw, "ixgbe_add_uc_addr Complete\n"); | |
1350 | } | |
1351 | ||
1352 | /** | |
c44ade9e | 1353 | * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses |
2c5645cf CL |
1354 | * @hw: pointer to hardware structure |
1355 | * @addr_list: the list of new addresses | |
1356 | * @addr_count: number of addresses | |
1357 | * @next: iterator function to walk the address list | |
1358 | * | |
1359 | * The given list replaces any existing list. Clears the secondary addrs from | |
1360 | * receive address registers. Uses unused receive address registers for the | |
1361 | * first secondary addresses, and falls back to promiscuous mode as needed. | |
1362 | * | |
1363 | * Drivers using secondary unicast addresses must set user_set_promisc when | |
1364 | * manually putting the device into promiscuous mode. | |
1365 | **/ | |
c44ade9e | 1366 | s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, |
2c5645cf CL |
1367 | u32 addr_count, ixgbe_mc_addr_itr next) |
1368 | { | |
1369 | u8 *addr; | |
1370 | u32 i; | |
1371 | u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; | |
1372 | u32 uc_addr_in_use; | |
1373 | u32 fctrl; | |
1374 | u32 vmdq; | |
1375 | ||
1376 | /* | |
1377 | * Clear accounting of old secondary address list, | |
1378 | * don't count RAR[0] | |
1379 | */ | |
1380 | uc_addr_in_use = hw->addr_ctrl.rar_used_count - | |
1381 | hw->addr_ctrl.mc_addr_in_rar_count - 1; | |
1382 | hw->addr_ctrl.rar_used_count -= uc_addr_in_use; | |
1383 | hw->addr_ctrl.overflow_promisc = 0; | |
1384 | ||
1385 | /* Zero out the other receive addresses */ | |
1386 | hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use); | |
1387 | for (i = 1; i <= uc_addr_in_use; i++) { | |
1388 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); | |
1389 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); | |
1390 | } | |
1391 | ||
1392 | /* Add the new addresses */ | |
1393 | for (i = 0; i < addr_count; i++) { | |
1394 | hw_dbg(hw, " Adding the secondary addresses:\n"); | |
1395 | addr = next(hw, &addr_list, &vmdq); | |
c44ade9e | 1396 | ixgbe_add_uc_addr(hw, addr, vmdq); |
2c5645cf CL |
1397 | } |
1398 | ||
1399 | if (hw->addr_ctrl.overflow_promisc) { | |
1400 | /* enable promisc if not already in overflow or set by user */ | |
1401 | if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { | |
1402 | hw_dbg(hw, " Entering address overflow promisc mode\n"); | |
1403 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
1404 | fctrl |= IXGBE_FCTRL_UPE; | |
1405 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
1406 | } | |
1407 | } else { | |
1408 | /* only disable if set by overflow, not by user */ | |
1409 | if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { | |
1410 | hw_dbg(hw, " Leaving address overflow promisc mode\n"); | |
1411 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
1412 | fctrl &= ~IXGBE_FCTRL_UPE; | |
1413 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
1414 | } | |
1415 | } | |
1416 | ||
c44ade9e | 1417 | hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n"); |
2c5645cf CL |
1418 | return 0; |
1419 | } | |
1420 | ||
9a799d71 AK |
1421 | /** |
1422 | * ixgbe_mta_vector - Determines bit-vector in multicast table to set | |
1423 | * @hw: pointer to hardware structure | |
1424 | * @mc_addr: the multicast address | |
1425 | * | |
1426 | * Extracts the 12 bits, from a multicast address, to determine which | |
1427 | * bit-vector to set in the multicast table. The hardware uses 12 bits, from | |
1428 | * incoming rx multicast addresses, to determine the bit-vector to check in | |
1429 | * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set | |
c44ade9e | 1430 | * by the MO field of the MCSTCTRL. The MO field is set during initialization |
9a799d71 AK |
1431 | * to mc_filter_type. |
1432 | **/ | |
1433 | static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) | |
1434 | { | |
1435 | u32 vector = 0; | |
1436 | ||
1437 | switch (hw->mac.mc_filter_type) { | |
b4617240 | 1438 | case 0: /* use bits [47:36] of the address */ |
9a799d71 AK |
1439 | vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); |
1440 | break; | |
b4617240 | 1441 | case 1: /* use bits [46:35] of the address */ |
9a799d71 AK |
1442 | vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); |
1443 | break; | |
b4617240 | 1444 | case 2: /* use bits [45:34] of the address */ |
9a799d71 AK |
1445 | vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); |
1446 | break; | |
b4617240 | 1447 | case 3: /* use bits [43:32] of the address */ |
9a799d71 AK |
1448 | vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); |
1449 | break; | |
b4617240 | 1450 | default: /* Invalid mc_filter_type */ |
9a799d71 AK |
1451 | hw_dbg(hw, "MC filter type param set incorrectly\n"); |
1452 | break; | |
1453 | } | |
1454 | ||
1455 | /* vector can only be 12-bits or boundary will be exceeded */ | |
1456 | vector &= 0xFFF; | |
1457 | return vector; | |
1458 | } | |
1459 | ||
1460 | /** | |
1461 | * ixgbe_set_mta - Set bit-vector in multicast table | |
1462 | * @hw: pointer to hardware structure | |
1463 | * @hash_value: Multicast address hash value | |
1464 | * | |
1465 | * Sets the bit-vector in the multicast table. | |
1466 | **/ | |
1467 | static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) | |
1468 | { | |
1469 | u32 vector; | |
1470 | u32 vector_bit; | |
1471 | u32 vector_reg; | |
1472 | u32 mta_reg; | |
1473 | ||
1474 | hw->addr_ctrl.mta_in_use++; | |
1475 | ||
1476 | vector = ixgbe_mta_vector(hw, mc_addr); | |
1477 | hw_dbg(hw, " bit-vector = 0x%03X\n", vector); | |
1478 | ||
1479 | /* | |
1480 | * The MTA is a register array of 128 32-bit registers. It is treated | |
1481 | * like an array of 4096 bits. We want to set bit | |
1482 | * BitArray[vector_value]. So we figure out what register the bit is | |
1483 | * in, read it, OR in the new bit, then write back the new value. The | |
1484 | * register is determined by the upper 7 bits of the vector value and | |
1485 | * the bit within that register are determined by the lower 5 bits of | |
1486 | * the value. | |
1487 | */ | |
1488 | vector_reg = (vector >> 5) & 0x7F; | |
1489 | vector_bit = vector & 0x1F; | |
1490 | mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); | |
1491 | mta_reg |= (1 << vector_bit); | |
1492 | IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); | |
1493 | } | |
1494 | ||
1495 | /** | |
1496 | * ixgbe_add_mc_addr - Adds a multicast address. | |
1497 | * @hw: pointer to hardware structure | |
1498 | * @mc_addr: new multicast address | |
1499 | * | |
1500 | * Adds it to unused receive address register or to the multicast table. | |
1501 | **/ | |
1502 | static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr) | |
1503 | { | |
2c5645cf | 1504 | u32 rar_entries = hw->mac.num_rar_entries; |
ce94bf46 | 1505 | u32 rar; |
9a799d71 AK |
1506 | |
1507 | hw_dbg(hw, " MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n", | |
b4617240 PW |
1508 | mc_addr[0], mc_addr[1], mc_addr[2], |
1509 | mc_addr[3], mc_addr[4], mc_addr[5]); | |
9a799d71 AK |
1510 | |
1511 | /* | |
1512 | * Place this multicast address in the RAR if there is room, | |
1513 | * else put it in the MTA | |
1514 | */ | |
1515 | if (hw->addr_ctrl.rar_used_count < rar_entries) { | |
c44ade9e | 1516 | /* use RAR from the end up for multicast */ |
ce94bf46 | 1517 | rar = rar_entries - hw->addr_ctrl.mc_addr_in_rar_count - 1; |
c44ade9e JB |
1518 | hw->mac.ops.set_rar(hw, rar, mc_addr, 0, IXGBE_RAH_AV); |
1519 | hw_dbg(hw, "Added a multicast address to RAR[%d]\n", rar); | |
9a799d71 AK |
1520 | hw->addr_ctrl.rar_used_count++; |
1521 | hw->addr_ctrl.mc_addr_in_rar_count++; | |
1522 | } else { | |
1523 | ixgbe_set_mta(hw, mc_addr); | |
1524 | } | |
1525 | ||
1526 | hw_dbg(hw, "ixgbe_add_mc_addr Complete\n"); | |
1527 | } | |
1528 | ||
1529 | /** | |
c44ade9e | 1530 | * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses |
9a799d71 AK |
1531 | * @hw: pointer to hardware structure |
1532 | * @mc_addr_list: the list of new multicast addresses | |
1533 | * @mc_addr_count: number of addresses | |
2c5645cf | 1534 | * @next: iterator function to walk the multicast address list |
9a799d71 AK |
1535 | * |
1536 | * The given list replaces any existing list. Clears the MC addrs from receive | |
c44ade9e | 1537 | * address registers and the multicast table. Uses unused receive address |
9a799d71 AK |
1538 | * registers for the first multicast addresses, and hashes the rest into the |
1539 | * multicast table. | |
1540 | **/ | |
c44ade9e | 1541 | s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, |
b4617240 | 1542 | u32 mc_addr_count, ixgbe_mc_addr_itr next) |
9a799d71 AK |
1543 | { |
1544 | u32 i; | |
2c5645cf CL |
1545 | u32 rar_entries = hw->mac.num_rar_entries; |
1546 | u32 vmdq; | |
9a799d71 AK |
1547 | |
1548 | /* | |
1549 | * Set the new number of MC addresses that we are being requested to | |
1550 | * use. | |
1551 | */ | |
1552 | hw->addr_ctrl.num_mc_addrs = mc_addr_count; | |
1553 | hw->addr_ctrl.rar_used_count -= hw->addr_ctrl.mc_addr_in_rar_count; | |
1554 | hw->addr_ctrl.mc_addr_in_rar_count = 0; | |
1555 | hw->addr_ctrl.mta_in_use = 0; | |
1556 | ||
1557 | /* Zero out the other receive addresses. */ | |
c44ade9e JB |
1558 | hw_dbg(hw, "Clearing RAR[%d-%d]\n", hw->addr_ctrl.rar_used_count, |
1559 | rar_entries - 1); | |
9a799d71 AK |
1560 | for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) { |
1561 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); | |
1562 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); | |
1563 | } | |
1564 | ||
1565 | /* Clear the MTA */ | |
1566 | hw_dbg(hw, " Clearing MTA\n"); | |
2c5645cf | 1567 | for (i = 0; i < hw->mac.mcft_size; i++) |
9a799d71 AK |
1568 | IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); |
1569 | ||
1570 | /* Add the new addresses */ | |
1571 | for (i = 0; i < mc_addr_count; i++) { | |
1572 | hw_dbg(hw, " Adding the multicast addresses:\n"); | |
2c5645cf | 1573 | ixgbe_add_mc_addr(hw, next(hw, &mc_addr_list, &vmdq)); |
9a799d71 AK |
1574 | } |
1575 | ||
1576 | /* Enable mta */ | |
1577 | if (hw->addr_ctrl.mta_in_use > 0) | |
1578 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, | |
b4617240 | 1579 | IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); |
9a799d71 | 1580 | |
c44ade9e | 1581 | hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); |
9a799d71 AK |
1582 | return 0; |
1583 | } | |
1584 | ||
1585 | /** | |
c44ade9e | 1586 | * ixgbe_enable_mc_generic - Enable multicast address in RAR |
9a799d71 AK |
1587 | * @hw: pointer to hardware structure |
1588 | * | |
c44ade9e | 1589 | * Enables multicast address in RAR and the use of the multicast hash table. |
9a799d71 | 1590 | **/ |
c44ade9e | 1591 | s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) |
9a799d71 | 1592 | { |
c44ade9e JB |
1593 | u32 i; |
1594 | u32 rar_entries = hw->mac.num_rar_entries; | |
1595 | struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; | |
9a799d71 | 1596 | |
c44ade9e JB |
1597 | if (a->mc_addr_in_rar_count > 0) |
1598 | for (i = (rar_entries - a->mc_addr_in_rar_count); | |
1599 | i < rar_entries; i++) | |
1600 | ixgbe_enable_rar(hw, i); | |
9a799d71 | 1601 | |
c44ade9e JB |
1602 | if (a->mta_in_use > 0) |
1603 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | | |
1604 | hw->mac.mc_filter_type); | |
9a799d71 AK |
1605 | |
1606 | return 0; | |
1607 | } | |
1608 | ||
1609 | /** | |
c44ade9e | 1610 | * ixgbe_disable_mc_generic - Disable multicast address in RAR |
9a799d71 | 1611 | * @hw: pointer to hardware structure |
9a799d71 | 1612 | * |
c44ade9e | 1613 | * Disables multicast address in RAR and the use of the multicast hash table. |
9a799d71 | 1614 | **/ |
c44ade9e | 1615 | s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) |
9a799d71 | 1616 | { |
c44ade9e JB |
1617 | u32 i; |
1618 | u32 rar_entries = hw->mac.num_rar_entries; | |
1619 | struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; | |
2b9ade93 | 1620 | |
c44ade9e JB |
1621 | if (a->mc_addr_in_rar_count > 0) |
1622 | for (i = (rar_entries - a->mc_addr_in_rar_count); | |
1623 | i < rar_entries; i++) | |
1624 | ixgbe_disable_rar(hw, i); | |
9a799d71 | 1625 | |
c44ade9e JB |
1626 | if (a->mta_in_use > 0) |
1627 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); | |
9a799d71 AK |
1628 | |
1629 | return 0; | |
1630 | } | |
1631 | ||
11afc1b1 PW |
1632 | /** |
1633 | * ixgbe_fc_enable - Enable flow control | |
1634 | * @hw: pointer to hardware structure | |
1635 | * @packetbuf_num: packet buffer number (0-7) | |
1636 | * | |
1637 | * Enable flow control according to the current settings. | |
1638 | **/ | |
1639 | s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num) | |
1640 | { | |
1641 | s32 ret_val = 0; | |
1642 | u32 mflcn_reg; | |
1643 | u32 fccfg_reg; | |
1644 | u32 reg; | |
1645 | ||
1646 | mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
1647 | mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE); | |
1648 | ||
1649 | fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
1650 | fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); | |
1651 | ||
1652 | /* | |
1653 | * The possible values of fc.current_mode are: | |
1654 | * 0: Flow control is completely disabled | |
1655 | * 1: Rx flow control is enabled (we can receive pause frames, | |
1656 | * but not send pause frames). | |
bb3daa4a PW |
1657 | * 2: Tx flow control is enabled (we can send pause frames but |
1658 | * we do not support receiving pause frames). | |
11afc1b1 | 1659 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
bb3daa4a | 1660 | * 4: Priority Flow Control is enabled. |
11afc1b1 PW |
1661 | * other: Invalid. |
1662 | */ | |
1663 | switch (hw->fc.current_mode) { | |
1664 | case ixgbe_fc_none: | |
1665 | /* Flow control completely disabled by software override. */ | |
1666 | break; | |
1667 | case ixgbe_fc_rx_pause: | |
1668 | /* | |
1669 | * Rx Flow control is enabled and Tx Flow control is | |
1670 | * disabled by software override. Since there really | |
1671 | * isn't a way to advertise that we are capable of RX | |
1672 | * Pause ONLY, we will advertise that we support both | |
1673 | * symmetric and asymmetric Rx PAUSE. Later, we will | |
1674 | * disable the adapter's ability to send PAUSE frames. | |
1675 | */ | |
1676 | mflcn_reg |= IXGBE_MFLCN_RFCE; | |
1677 | break; | |
1678 | case ixgbe_fc_tx_pause: | |
1679 | /* | |
1680 | * Tx Flow control is enabled, and Rx Flow control is | |
1681 | * disabled by software override. | |
1682 | */ | |
1683 | fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; | |
1684 | break; | |
1685 | case ixgbe_fc_full: | |
1686 | /* Flow control (both Rx and Tx) is enabled by SW override. */ | |
1687 | mflcn_reg |= IXGBE_MFLCN_RFCE; | |
1688 | fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; | |
1689 | break; | |
bb3daa4a PW |
1690 | #ifdef CONFIG_DCB |
1691 | case ixgbe_fc_pfc: | |
1692 | goto out; | |
1693 | break; | |
1694 | #endif | |
11afc1b1 PW |
1695 | default: |
1696 | hw_dbg(hw, "Flow control param set incorrectly\n"); | |
1697 | ret_val = -IXGBE_ERR_CONFIG; | |
1698 | goto out; | |
1699 | break; | |
1700 | } | |
1701 | ||
1702 | /* Enable 802.3x based flow control settings. */ | |
1703 | IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); | |
1704 | IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); | |
1705 | ||
1706 | /* Set up and enable Rx high/low water mark thresholds, enable XON. */ | |
1707 | if (hw->fc.current_mode & ixgbe_fc_tx_pause) { | |
1708 | if (hw->fc.send_xon) | |
1709 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), | |
1710 | (hw->fc.low_water | IXGBE_FCRTL_XONE)); | |
1711 | else | |
1712 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), | |
1713 | hw->fc.low_water); | |
1714 | ||
1715 | IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), | |
1716 | (hw->fc.high_water | IXGBE_FCRTH_FCEN)); | |
1717 | } | |
1718 | ||
1719 | /* Configure pause time (2 TCs per register) */ | |
1720 | reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num)); | |
1721 | if ((packetbuf_num & 1) == 0) | |
1722 | reg = (reg & 0xFFFF0000) | hw->fc.pause_time; | |
1723 | else | |
1724 | reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); | |
1725 | IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); | |
1726 | ||
1727 | IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); | |
1728 | ||
1729 | out: | |
1730 | return ret_val; | |
1731 | } | |
1732 | ||
0ecc061d PWJ |
1733 | /** |
1734 | * ixgbe_fc_autoneg - Configure flow control | |
1735 | * @hw: pointer to hardware structure | |
1736 | * | |
1737 | * Negotiates flow control capabilities with link partner using autoneg and | |
1738 | * applies the results. | |
1739 | **/ | |
1740 | s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw) | |
1741 | { | |
1742 | s32 ret_val = 0; | |
1743 | u32 i, reg, pcs_anadv_reg, pcs_lpab_reg; | |
1744 | ||
1745 | reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); | |
1746 | ||
1747 | /* | |
1748 | * The possible values of fc.current_mode are: | |
1749 | * 0: Flow control is completely disabled | |
1750 | * 1: Rx flow control is enabled (we can receive pause frames, | |
1751 | * but not send pause frames). | |
1752 | * 2: Tx flow control is enabled (we can send pause frames but | |
1753 | * we do not support receiving pause frames). | |
1754 | * 3: Both Rx and Tx flow control (symmetric) are enabled. | |
bb3daa4a | 1755 | * 4: Priority Flow Control is enabled. |
0ecc061d PWJ |
1756 | * other: Invalid. |
1757 | */ | |
1758 | switch (hw->fc.current_mode) { | |
1759 | case ixgbe_fc_none: | |
1760 | /* Flow control completely disabled by software override. */ | |
1761 | reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); | |
1762 | break; | |
1763 | case ixgbe_fc_rx_pause: | |
1764 | /* | |
1765 | * Rx Flow control is enabled and Tx Flow control is | |
1766 | * disabled by software override. Since there really | |
1767 | * isn't a way to advertise that we are capable of RX | |
1768 | * Pause ONLY, we will advertise that we support both | |
1769 | * symmetric and asymmetric Rx PAUSE. Later, we will | |
1770 | * disable the adapter's ability to send PAUSE frames. | |
1771 | */ | |
1772 | reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); | |
1773 | break; | |
1774 | case ixgbe_fc_tx_pause: | |
1775 | /* | |
1776 | * Tx Flow control is enabled, and Rx Flow control is | |
1777 | * disabled by software override. | |
1778 | */ | |
1779 | reg |= (IXGBE_PCS1GANA_ASM_PAUSE); | |
1780 | reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE); | |
1781 | break; | |
1782 | case ixgbe_fc_full: | |
1783 | /* Flow control (both Rx and Tx) is enabled by SW override. */ | |
1784 | reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); | |
1785 | break; | |
bb3daa4a PW |
1786 | #ifdef CONFIG_DCB |
1787 | case ixgbe_fc_pfc: | |
1788 | goto out; | |
1789 | break; | |
1790 | #endif | |
0ecc061d PWJ |
1791 | default: |
1792 | hw_dbg(hw, "Flow control param set incorrectly\n"); | |
1793 | ret_val = -IXGBE_ERR_CONFIG; | |
1794 | goto out; | |
1795 | break; | |
1796 | } | |
1797 | ||
1798 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); | |
1799 | reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); | |
1800 | ||
1801 | /* Set PCS register for autoneg */ | |
1802 | /* Enable and restart autoneg */ | |
1803 | reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART; | |
1804 | ||
1805 | /* Disable AN timeout */ | |
1806 | if (hw->fc.strict_ieee) | |
1807 | reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; | |
1808 | ||
1809 | hw_dbg(hw, "Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg); | |
1810 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); | |
1811 | ||
1812 | /* See if autonegotiation has succeeded */ | |
1813 | hw->mac.autoneg_succeeded = 0; | |
1814 | for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { | |
1815 | msleep(10); | |
1816 | reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); | |
1817 | if ((reg & (IXGBE_PCS1GLSTA_LINK_OK | | |
1818 | IXGBE_PCS1GLSTA_AN_COMPLETE)) == | |
1819 | (IXGBE_PCS1GLSTA_LINK_OK | | |
1820 | IXGBE_PCS1GLSTA_AN_COMPLETE)) { | |
1821 | if (!(reg & IXGBE_PCS1GLSTA_AN_TIMED_OUT)) | |
1822 | hw->mac.autoneg_succeeded = 1; | |
1823 | break; | |
1824 | } | |
1825 | } | |
1826 | ||
1827 | if (!hw->mac.autoneg_succeeded) { | |
1828 | /* Autoneg failed to achieve a link, so we turn fc off */ | |
1829 | hw->fc.current_mode = ixgbe_fc_none; | |
1830 | hw_dbg(hw, "Flow Control = NONE.\n"); | |
1831 | goto out; | |
1832 | } | |
1833 | ||
1834 | /* | |
1835 | * Read the AN advertisement and LP ability registers and resolve | |
1836 | * local flow control settings accordingly | |
1837 | */ | |
1838 | pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); | |
1839 | pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); | |
1840 | if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | |
1841 | (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { | |
1842 | /* | |
1843 | * Now we need to check if the user selected Rx ONLY | |
1844 | * of pause frames. In this case, we had to advertise | |
1845 | * FULL flow control because we could not advertise RX | |
1846 | * ONLY. Hence, we must now check to see if we need to | |
1847 | * turn OFF the TRANSMISSION of PAUSE frames. | |
1848 | */ | |
1849 | if (hw->fc.requested_mode == ixgbe_fc_full) { | |
1850 | hw->fc.current_mode = ixgbe_fc_full; | |
1851 | hw_dbg(hw, "Flow Control = FULL.\n"); | |
1852 | } else { | |
1853 | hw->fc.current_mode = ixgbe_fc_rx_pause; | |
1854 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); | |
1855 | } | |
1856 | } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | |
1857 | (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && | |
1858 | (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | |
1859 | (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { | |
1860 | hw->fc.current_mode = ixgbe_fc_tx_pause; | |
1861 | hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); | |
1862 | } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | |
1863 | (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && | |
1864 | !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | |
1865 | (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { | |
1866 | hw->fc.current_mode = ixgbe_fc_rx_pause; | |
1867 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); | |
1868 | } else { | |
1869 | hw->fc.current_mode = ixgbe_fc_none; | |
1870 | hw_dbg(hw, "Flow Control = NONE.\n"); | |
1871 | } | |
1872 | ||
1873 | out: | |
1874 | return ret_val; | |
1875 | } | |
1876 | ||
11afc1b1 PW |
1877 | /** |
1878 | * ixgbe_setup_fc_generic - Set up flow control | |
1879 | * @hw: pointer to hardware structure | |
1880 | * | |
1881 | * Sets up flow control. | |
1882 | **/ | |
1883 | s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num) | |
1884 | { | |
1885 | s32 ret_val = 0; | |
1886 | ixgbe_link_speed speed; | |
1887 | bool link_up; | |
1888 | ||
bb3daa4a PW |
1889 | #ifdef CONFIG_DCB |
1890 | if (hw->fc.requested_mode == ixgbe_fc_pfc) { | |
1891 | hw->fc.current_mode = hw->fc.requested_mode; | |
1892 | goto out; | |
1893 | } | |
1894 | ||
1895 | #endif | |
11afc1b1 PW |
1896 | /* Validate the packetbuf configuration */ |
1897 | if (packetbuf_num < 0 || packetbuf_num > 7) { | |
1898 | hw_dbg(hw, "Invalid packet buffer number [%d], expected range " | |
1899 | "is 0-7\n", packetbuf_num); | |
1900 | ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; | |
1901 | goto out; | |
1902 | } | |
1903 | ||
1904 | /* | |
1905 | * Validate the water mark configuration. Zero water marks are invalid | |
1906 | * because it causes the controller to just blast out fc packets. | |
1907 | */ | |
1908 | if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { | |
1909 | hw_dbg(hw, "Invalid water mark configuration\n"); | |
1910 | ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; | |
1911 | goto out; | |
1912 | } | |
1913 | ||
1914 | /* | |
1915 | * Validate the requested mode. Strict IEEE mode does not allow | |
1916 | * ixgbe_fc_rx_pause because it will cause testing anomalies. | |
1917 | */ | |
1918 | if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { | |
1919 | hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict " | |
1920 | "IEEE mode\n"); | |
1921 | ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; | |
1922 | goto out; | |
1923 | } | |
1924 | ||
1925 | /* | |
1926 | * 10gig parts do not have a word in the EEPROM to determine the | |
1927 | * default flow control setting, so we explicitly set it to full. | |
1928 | */ | |
1929 | if (hw->fc.requested_mode == ixgbe_fc_default) | |
1930 | hw->fc.requested_mode = ixgbe_fc_full; | |
1931 | ||
1932 | /* | |
1933 | * Save off the requested flow control mode for use later. Depending | |
1934 | * on the link partner's capabilities, we may or may not use this mode. | |
1935 | */ | |
1936 | hw->fc.current_mode = hw->fc.requested_mode; | |
1937 | ||
1938 | /* Decide whether to use autoneg or not. */ | |
1939 | hw->mac.ops.check_link(hw, &speed, &link_up, false); | |
71fd570b DS |
1940 | if (!hw->fc.disable_fc_autoneg && hw->phy.multispeed_fiber && |
1941 | (speed == IXGBE_LINK_SPEED_1GB_FULL)) | |
11afc1b1 PW |
1942 | ret_val = ixgbe_fc_autoneg(hw); |
1943 | ||
1944 | if (ret_val) | |
1945 | goto out; | |
1946 | ||
1947 | ret_val = ixgbe_fc_enable(hw, packetbuf_num); | |
1948 | ||
1949 | out: | |
1950 | return ret_val; | |
1951 | } | |
1952 | ||
9a799d71 AK |
1953 | /** |
1954 | * ixgbe_disable_pcie_master - Disable PCI-express master access | |
1955 | * @hw: pointer to hardware structure | |
1956 | * | |
1957 | * Disables PCI-Express master access and verifies there are no pending | |
1958 | * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable | |
1959 | * bit hasn't caused the master requests to be disabled, else 0 | |
1960 | * is returned signifying master requests disabled. | |
1961 | **/ | |
1962 | s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) | |
1963 | { | |
c44ade9e JB |
1964 | u32 i; |
1965 | u32 reg_val; | |
1966 | u32 number_of_queues; | |
9a799d71 AK |
1967 | s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; |
1968 | ||
c44ade9e JB |
1969 | /* Disable the receive unit by stopping each queue */ |
1970 | number_of_queues = hw->mac.max_rx_queues; | |
1971 | for (i = 0; i < number_of_queues; i++) { | |
1972 | reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
1973 | if (reg_val & IXGBE_RXDCTL_ENABLE) { | |
1974 | reg_val &= ~IXGBE_RXDCTL_ENABLE; | |
1975 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); | |
1976 | } | |
1977 | } | |
1978 | ||
1979 | reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
1980 | reg_val |= IXGBE_CTRL_GIO_DIS; | |
1981 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val); | |
9a799d71 AK |
1982 | |
1983 | for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { | |
1984 | if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { | |
1985 | status = 0; | |
1986 | break; | |
1987 | } | |
1988 | udelay(100); | |
1989 | } | |
1990 | ||
1991 | return status; | |
1992 | } | |
1993 | ||
1994 | ||
1995 | /** | |
c44ade9e | 1996 | * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore |
9a799d71 | 1997 | * @hw: pointer to hardware structure |
c44ade9e | 1998 | * @mask: Mask to specify which semaphore to acquire |
9a799d71 | 1999 | * |
c44ade9e | 2000 | * Acquires the SWFW semaphore thought the GSSR register for the specified |
9a799d71 AK |
2001 | * function (CSR, PHY0, PHY1, EEPROM, Flash) |
2002 | **/ | |
2003 | s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) | |
2004 | { | |
2005 | u32 gssr; | |
2006 | u32 swmask = mask; | |
2007 | u32 fwmask = mask << 5; | |
2008 | s32 timeout = 200; | |
2009 | ||
2010 | while (timeout) { | |
2011 | if (ixgbe_get_eeprom_semaphore(hw)) | |
2012 | return -IXGBE_ERR_SWFW_SYNC; | |
2013 | ||
2014 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); | |
2015 | if (!(gssr & (fwmask | swmask))) | |
2016 | break; | |
2017 | ||
2018 | /* | |
2019 | * Firmware currently using resource (fwmask) or other software | |
2020 | * thread currently using resource (swmask) | |
2021 | */ | |
2022 | ixgbe_release_eeprom_semaphore(hw); | |
2023 | msleep(5); | |
2024 | timeout--; | |
2025 | } | |
2026 | ||
2027 | if (!timeout) { | |
2028 | hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n"); | |
2029 | return -IXGBE_ERR_SWFW_SYNC; | |
2030 | } | |
2031 | ||
2032 | gssr |= swmask; | |
2033 | IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); | |
2034 | ||
2035 | ixgbe_release_eeprom_semaphore(hw); | |
2036 | return 0; | |
2037 | } | |
2038 | ||
2039 | /** | |
2040 | * ixgbe_release_swfw_sync - Release SWFW semaphore | |
2041 | * @hw: pointer to hardware structure | |
c44ade9e | 2042 | * @mask: Mask to specify which semaphore to release |
9a799d71 | 2043 | * |
c44ade9e | 2044 | * Releases the SWFW semaphore thought the GSSR register for the specified |
9a799d71 AK |
2045 | * function (CSR, PHY0, PHY1, EEPROM, Flash) |
2046 | **/ | |
2047 | void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) | |
2048 | { | |
2049 | u32 gssr; | |
2050 | u32 swmask = mask; | |
2051 | ||
2052 | ixgbe_get_eeprom_semaphore(hw); | |
2053 | ||
2054 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); | |
2055 | gssr &= ~swmask; | |
2056 | IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); | |
2057 | ||
2058 | ixgbe_release_eeprom_semaphore(hw); | |
2059 | } | |
2060 | ||
11afc1b1 PW |
2061 | /** |
2062 | * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit | |
2063 | * @hw: pointer to hardware structure | |
2064 | * @regval: register value to write to RXCTRL | |
2065 | * | |
2066 | * Enables the Rx DMA unit | |
2067 | **/ | |
2068 | s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) | |
2069 | { | |
2070 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); | |
2071 | ||
2072 | return 0; | |
2073 | } |