]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/ixgbe/ixgbe_common.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgbe: bump version
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
32
33#include "ixgbe_common.h"
34#include "ixgbe_phy.h"
35
9a799d71 36static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
c44ade9e 37static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 38static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 40static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
43 u16 count);
44static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 48static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
49
c44ade9e
JB		 50static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
51static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
9a799d71
AK		 52static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
53static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr);
c44ade9e 54static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
9a799d71
AK		 55
56/**
c44ade9e 57 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 58 * @hw: pointer to hardware structure
59 *
60 * Starts the hardware by filling the bus info structure and media type, clears
61 * all on chip counters, initializes receive address registers, multicast
62 * table, VLAN filter table, calls routine to set up link and flow control
63 * settings, and leaves transmit and receive units disabled and uninitialized
64 **/
c44ade9e 65s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71
AK		 66{
67 u32 ctrl_ext;
68
69 /* Set the media type */
70 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
71
72 /* Identify the PHY */
c44ade9e 73 hw->phy.ops.identify(hw);
9a799d71
AK		 74
75 /*
76 * Store MAC address from RAR0, clear receive address registers, and
77 * clear the multicast table
78 */
c44ade9e 79 hw->mac.ops.init_rx_addrs(hw);
9a799d71
AK		 80
81 /* Clear the VLAN filter table */
c44ade9e 82 hw->mac.ops.clear_vfta(hw);
9a799d71
AK		 83
84 /* Set up link */
3957d63d 85 hw->mac.ops.setup_link(hw);
9a799d71
AK		 86
87 /* Clear statistics registers */
c44ade9e 88 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 89
90 /* Set No Snoop Disable */
91 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
92 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
93 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 94 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 95
96 /* Clear adapter stopped flag */
97 hw->adapter_stopped = false;
98
99 return 0;
100}
101
102/**
c44ade9e 103 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 104 * @hw: pointer to hardware structure
105 *
c44ade9e 106 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 107 * structure and media type, clears all on chip counters, initializes receive
108 * address registers, multicast table, VLAN filter table, calls routine to set
109 * up link and flow control settings, and leaves transmit and receive units
110 * disabled and uninitialized
111 **/
c44ade9e 112s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71
AK		 113{
114 /* Reset the hardware */
c44ade9e 115 hw->mac.ops.reset_hw(hw);
9a799d71
AK		 116
117 /* Start the HW */
c44ade9e 118 hw->mac.ops.start_hw(hw);
9a799d71
AK		 119
120 return 0;
121}
122
123/**
c44ade9e 124 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 125 * @hw: pointer to hardware structure
126 *
127 * Clears all hardware statistics counters by reading them from the hardware
128 * Statistics counters are clear on read.
129 **/
c44ade9e 130s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 131{
132 u16 i = 0;
133
134 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
135 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
136 IXGBE_READ_REG(hw, IXGBE_ERRBC);
137 IXGBE_READ_REG(hw, IXGBE_MSPDC);
138 for (i = 0; i < 8; i++)
139 IXGBE_READ_REG(hw, IXGBE_MPC(i));
140
141 IXGBE_READ_REG(hw, IXGBE_MLFC);
142 IXGBE_READ_REG(hw, IXGBE_MRFC);
143 IXGBE_READ_REG(hw, IXGBE_RLEC);
144 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
145 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
146 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
147 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
148
149 for (i = 0; i < 8; i++) {
150 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
151 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
152 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
153 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
154 }
155
156 IXGBE_READ_REG(hw, IXGBE_PRC64);
157 IXGBE_READ_REG(hw, IXGBE_PRC127);
158 IXGBE_READ_REG(hw, IXGBE_PRC255);
159 IXGBE_READ_REG(hw, IXGBE_PRC511);
160 IXGBE_READ_REG(hw, IXGBE_PRC1023);
161 IXGBE_READ_REG(hw, IXGBE_PRC1522);
162 IXGBE_READ_REG(hw, IXGBE_GPRC);
163 IXGBE_READ_REG(hw, IXGBE_BPRC);
164 IXGBE_READ_REG(hw, IXGBE_MPRC);
165 IXGBE_READ_REG(hw, IXGBE_GPTC);
166 IXGBE_READ_REG(hw, IXGBE_GORCL);
167 IXGBE_READ_REG(hw, IXGBE_GORCH);
168 IXGBE_READ_REG(hw, IXGBE_GOTCL);
169 IXGBE_READ_REG(hw, IXGBE_GOTCH);
170 for (i = 0; i < 8; i++)
171 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
172 IXGBE_READ_REG(hw, IXGBE_RUC);
173 IXGBE_READ_REG(hw, IXGBE_RFC);
174 IXGBE_READ_REG(hw, IXGBE_ROC);
175 IXGBE_READ_REG(hw, IXGBE_RJC);
176 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
177 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
178 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
179 IXGBE_READ_REG(hw, IXGBE_TORL);
180 IXGBE_READ_REG(hw, IXGBE_TORH);
181 IXGBE_READ_REG(hw, IXGBE_TPR);
182 IXGBE_READ_REG(hw, IXGBE_TPT);
183 IXGBE_READ_REG(hw, IXGBE_PTC64);
184 IXGBE_READ_REG(hw, IXGBE_PTC127);
185 IXGBE_READ_REG(hw, IXGBE_PTC255);
186 IXGBE_READ_REG(hw, IXGBE_PTC511);
187 IXGBE_READ_REG(hw, IXGBE_PTC1023);
188 IXGBE_READ_REG(hw, IXGBE_PTC1522);
189 IXGBE_READ_REG(hw, IXGBE_MPTC);
190 IXGBE_READ_REG(hw, IXGBE_BPTC);
191 for (i = 0; i < 16; i++) {
192 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
193 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
194 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
195 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
196 }
197
198 return 0;
199}
200
201/**
c44ade9e
JB		 202 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
203 * @hw: pointer to hardware structure
204 * @pba_num: stores the part number from the EEPROM
205 *
206 * Reads the part number from the EEPROM.
207 **/
208s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
209{
210 s32 ret_val;
211 u16 data;
212
213 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
214 if (ret_val) {
215 hw_dbg(hw, "NVM Read Error\n");
216 return ret_val;
217 }
218 *pba_num = (u32)(data << 16);
219
220 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
221 if (ret_val) {
222 hw_dbg(hw, "NVM Read Error\n");
223 return ret_val;
224 }
225 *pba_num |= data;
226
227 return 0;
228}
229
230/**
231 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 232 * @hw: pointer to hardware structure
233 * @mac_addr: Adapter MAC address
234 *
235 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
236 * A reset of the adapter must be performed prior to calling this function
237 * in order for the MAC address to have been loaded from the EEPROM into RAR0
238 **/
c44ade9e 239s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 240{
241 u32 rar_high;
242 u32 rar_low;
243 u16 i;
244
245 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
246 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
247
248 for (i = 0; i < 4; i++)
249 mac_addr[i] = (u8)(rar_low >> (i*8));
250
251 for (i = 0; i < 2; i++)
252 mac_addr[i+4] = (u8)(rar_high >> (i*8));
253
254 return 0;
255}
256
9a799d71 257/**
c44ade9e 258 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 259 * @hw: pointer to hardware structure
260 *
261 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
262 * disables transmit and receive units. The adapter_stopped flag is used by
263 * the shared code and drivers to determine if the adapter is in a stopped
264 * state and should not touch the hardware.
265 **/
c44ade9e 266s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71
AK		 267{
268 u32 number_of_queues;
269 u32 reg_val;
270 u16 i;
271
272 /*
273 * Set the adapter_stopped flag so other driver functions stop touching
274 * the hardware
275 */
276 hw->adapter_stopped = true;
277
278 /* Disable the receive unit */
279 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
280 reg_val &= ~(IXGBE_RXCTRL_RXEN);
281 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
c44ade9e 282 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 283 msleep(2);
284
285 /* Clear interrupt mask to stop from interrupts being generated */
286 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
287
288 /* Clear any pending interrupts */
289 IXGBE_READ_REG(hw, IXGBE_EICR);
290
291 /* Disable the transmit unit. Each queue must be disabled. */
c44ade9e 292 number_of_queues = hw->mac.max_tx_queues;
9a799d71
AK		 293 for (i = 0; i < number_of_queues; i++) {
294 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
295 if (reg_val & IXGBE_TXDCTL_ENABLE) {
296 reg_val &= ~IXGBE_TXDCTL_ENABLE;
297 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
298 }
299 }
300
c44ade9e
JB		 301 /*
302 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
303 * access and verify no pending requests
304 */
305 if (ixgbe_disable_pcie_master(hw) != 0)
306 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
307
9a799d71
AK		 308 return 0;
309}
310
311/**
c44ade9e 312 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 313 * @hw: pointer to hardware structure
314 * @index: led number to turn on
315 **/
c44ade9e 316s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 317{
318 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
319
320 /* To turn on the LED, set mode to ON. */
321 led_reg &= ~IXGBE_LED_MODE_MASK(index);
322 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
323 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 324 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 325
326 return 0;
327}
328
329/**
c44ade9e 330 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 331 * @hw: pointer to hardware structure
332 * @index: led number to turn off
333 **/
c44ade9e 334s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 335{
336 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
337
338 /* To turn off the LED, set mode to OFF. */
339 led_reg &= ~IXGBE_LED_MODE_MASK(index);
340 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
341 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 342 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 343
344 return 0;
345}
346
9a799d71 347/**
c44ade9e 348 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 349 * @hw: pointer to hardware structure
350 *
351 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
352 * ixgbe_hw struct in order to set up EEPROM access.
353 **/
c44ade9e 354s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 355{
356 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
357 u32 eec;
358 u16 eeprom_size;
359
360 if (eeprom->type == ixgbe_eeprom_uninitialized) {
361 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 362 /* Set default semaphore delay to 10ms which is a well
363 * tested value */
364 eeprom->semaphore_delay = 10;
9a799d71
AK		 365
366 /*
367 * Check for EEPROM present first.
368 * If not present leave as none
369 */
370 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
371 if (eec & IXGBE_EEC_PRES) {
372 eeprom->type = ixgbe_eeprom_spi;
373
374 /*
375 * SPI EEPROM is assumed here. This code would need to
376 * change if a future EEPROM is not SPI.
377 */
378 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
379 IXGBE_EEC_SIZE_SHIFT);
380 eeprom->word_size = 1 << (eeprom_size +
381 IXGBE_EEPROM_WORD_SIZE_SHIFT);
382 }
383
384 if (eec & IXGBE_EEC_ADDR_SIZE)
385 eeprom->address_bits = 16;
386 else
387 eeprom->address_bits = 8;
388 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
389 "%d\n", eeprom->type, eeprom->word_size,
390 eeprom->address_bits);
391 }
392
393 return 0;
394}
395
396/**
c44ade9e
JB		 397 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
398 * @hw: pointer to hardware structure
399 * @offset: offset within the EEPROM to be read
400 * @data: read 16 bit value from EEPROM
401 *
402 * Reads 16 bit value from EEPROM through bit-bang method
403 **/
404s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
405 u16 *data)
406{
407 s32 status;
408 u16 word_in;
409 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
410
411 hw->eeprom.ops.init_params(hw);
412
413 if (offset >= hw->eeprom.word_size) {
414 status = IXGBE_ERR_EEPROM;
415 goto out;
416 }
417
418 /* Prepare the EEPROM for reading */
419 status = ixgbe_acquire_eeprom(hw);
420
421 if (status == 0) {
422 if (ixgbe_ready_eeprom(hw) != 0) {
423 ixgbe_release_eeprom(hw);
424 status = IXGBE_ERR_EEPROM;
425 }
426 }
427
428 if (status == 0) {
429 ixgbe_standby_eeprom(hw);
430
431 /*
432 * Some SPI eeproms use the 8th address bit embedded in the
433 * opcode
434 */
435 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
436 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
437
438 /* Send the READ command (opcode + addr) */
439 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
440 IXGBE_EEPROM_OPCODE_BITS);
441 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
442 hw->eeprom.address_bits);
443
444 /* Read the data. */
445 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
446 *data = (word_in >> 8) | (word_in << 8);
447
448 /* End this read operation */
449 ixgbe_release_eeprom(hw);
450 }
451
452out:
453 return status;
454}
455
456/**
457 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD
9a799d71
AK		 458 * @hw: pointer to hardware structure
459 * @offset: offset of word in the EEPROM to read
460 * @data: word read from the EEPROM
461 *
462 * Reads a 16 bit word from the EEPROM using the EERD register.
463 **/
c44ade9e 464s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
9a799d71
AK		 465{
466 u32 eerd;
467 s32 status;
468
c44ade9e
JB		 469 hw->eeprom.ops.init_params(hw);
470
471 if (offset >= hw->eeprom.word_size) {
472 status = IXGBE_ERR_EEPROM;
473 goto out;
474 }
475
9a799d71
AK		 476 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) +
477 IXGBE_EEPROM_READ_REG_START;
478
479 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
480 status = ixgbe_poll_eeprom_eerd_done(hw);
481
482 if (status == 0)
483 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
484 IXGBE_EEPROM_READ_REG_DATA);
485 else
486 hw_dbg(hw, "Eeprom read timed out\n");
487
c44ade9e 488out:
9a799d71
AK		 489 return status;
490}
491
492/**
493 * ixgbe_poll_eeprom_eerd_done - Poll EERD status
494 * @hw: pointer to hardware structure
495 *
496 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
497 **/
498static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
499{
500 u32 i;
501 u32 reg;
502 s32 status = IXGBE_ERR_EEPROM;
503
504 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) {
505 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
506 if (reg & IXGBE_EEPROM_READ_REG_DONE) {
507 status = 0;
508 break;
509 }
510 udelay(5);
511 }
512 return status;
513}
514
c44ade9e
JB		 515/**
516 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
517 * @hw: pointer to hardware structure
518 *
519 * Prepares EEPROM for access using bit-bang method. This function should
520 * be called before issuing a command to the EEPROM.
521 **/
522static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
523{
524 s32 status = 0;
525 u32 eec;
526 u32 i;
527
528 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
529 status = IXGBE_ERR_SWFW_SYNC;
530
531 if (status == 0) {
532 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
533
534 /* Request EEPROM Access */
535 eec |= IXGBE_EEC_REQ;
536 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
537
538 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
539 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
540 if (eec & IXGBE_EEC_GNT)
541 break;
542 udelay(5);
543 }
544
545 /* Release if grant not acquired */
546 if (!(eec & IXGBE_EEC_GNT)) {
547 eec &= ~IXGBE_EEC_REQ;
548 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
549 hw_dbg(hw, "Could not acquire EEPROM grant\n");
550
551 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
552 status = IXGBE_ERR_EEPROM;
553 }
554 }
555
556 /* Setup EEPROM for Read/Write */
557 if (status == 0) {
558 /* Clear CS and SK */
559 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
560 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
561 IXGBE_WRITE_FLUSH(hw);
562 udelay(1);
563 }
564 return status;
565}
566
9a799d71
AK		 567/**
568 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
569 * @hw: pointer to hardware structure
570 *
571 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
572 **/
573static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
574{
575 s32 status = IXGBE_ERR_EEPROM;
576 u32 timeout;
577 u32 i;
578 u32 swsm;
579
580 /* Set timeout value based on size of EEPROM */
581 timeout = hw->eeprom.word_size + 1;
582
583 /* Get SMBI software semaphore between device drivers first */
584 for (i = 0; i < timeout; i++) {
585 /*
586 * If the SMBI bit is 0 when we read it, then the bit will be
587 * set and we have the semaphore
588 */
589 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
590 if (!(swsm & IXGBE_SWSM_SMBI)) {
591 status = 0;
592 break;
593 }
594 msleep(1);
595 }
596
597 /* Now get the semaphore between SW/FW through the SWESMBI bit */
598 if (status == 0) {
599 for (i = 0; i < timeout; i++) {
600 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
601
602 /* Set the SW EEPROM semaphore bit to request access */
603 swsm |= IXGBE_SWSM_SWESMBI;
604 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
605
606 /*
607 * If we set the bit successfully then we got the
608 * semaphore.
609 */
610 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
611 if (swsm & IXGBE_SWSM_SWESMBI)
612 break;
613
614 udelay(50);
615 }
616
617 /*
618 * Release semaphores and return error if SW EEPROM semaphore
619 * was not granted because we don't have access to the EEPROM
620 */
621 if (i >= timeout) {
622 hw_dbg(hw, "Driver can't access the Eeprom - Semaphore "
623 "not granted.\n");
624 ixgbe_release_eeprom_semaphore(hw);
625 status = IXGBE_ERR_EEPROM;
626 }
627 }
628
629 return status;
630}
631
632/**
633 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
634 * @hw: pointer to hardware structure
635 *
636 * This function clears hardware semaphore bits.
637 **/
638static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
639{
640 u32 swsm;
641
642 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
643
644 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
645 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
646 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
3957d63d 647 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 648}
649
c44ade9e
JB		 650/**
651 * ixgbe_ready_eeprom - Polls for EEPROM ready
652 * @hw: pointer to hardware structure
653 **/
654static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
655{
656 s32 status = 0;
657 u16 i;
658 u8 spi_stat_reg;
659
660 /*
661 * Read "Status Register" repeatedly until the LSB is cleared. The
662 * EEPROM will signal that the command has been completed by clearing
663 * bit 0 of the internal status register. If it's not cleared within
664 * 5 milliseconds, then error out.
665 */
666 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
667 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
668 IXGBE_EEPROM_OPCODE_BITS);
669 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
670 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
671 break;
672
673 udelay(5);
674 ixgbe_standby_eeprom(hw);
675 };
676
677 /*
678 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
679 * devices (and only 0-5mSec on 5V devices)
680 */
681 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
682 hw_dbg(hw, "SPI EEPROM Status error\n");
683 status = IXGBE_ERR_EEPROM;
684 }
685
686 return status;
687}
688
689/**
690 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
691 * @hw: pointer to hardware structure
692 **/
693static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
694{
695 u32 eec;
696
697 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
698
699 /* Toggle CS to flush commands */
700 eec |= IXGBE_EEC_CS;
701 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
702 IXGBE_WRITE_FLUSH(hw);
703 udelay(1);
704 eec &= ~IXGBE_EEC_CS;
705 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
706 IXGBE_WRITE_FLUSH(hw);
707 udelay(1);
708}
709
710/**
711 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
712 * @hw: pointer to hardware structure
713 * @data: data to send to the EEPROM
714 * @count: number of bits to shift out
715 **/
716static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
717 u16 count)
718{
719 u32 eec;
720 u32 mask;
721 u32 i;
722
723 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
724
725 /*
726 * Mask is used to shift "count" bits of "data" out to the EEPROM
727 * one bit at a time. Determine the starting bit based on count
728 */
729 mask = 0x01 << (count - 1);
730
731 for (i = 0; i < count; i++) {
732 /*
733 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
734 * "1", and then raising and then lowering the clock (the SK
735 * bit controls the clock input to the EEPROM). A "0" is
736 * shifted out to the EEPROM by setting "DI" to "0" and then
737 * raising and then lowering the clock.
738 */
739 if (data & mask)
740 eec |= IXGBE_EEC_DI;
741 else
742 eec &= ~IXGBE_EEC_DI;
743
744 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
745 IXGBE_WRITE_FLUSH(hw);
746
747 udelay(1);
748
749 ixgbe_raise_eeprom_clk(hw, &eec);
750 ixgbe_lower_eeprom_clk(hw, &eec);
751
752 /*
753 * Shift mask to signify next bit of data to shift in to the
754 * EEPROM
755 */
756 mask = mask >> 1;
757 };
758
759 /* We leave the "DI" bit set to "0" when we leave this routine. */
760 eec &= ~IXGBE_EEC_DI;
761 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
762 IXGBE_WRITE_FLUSH(hw);
763}
764
765/**
766 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
767 * @hw: pointer to hardware structure
768 **/
769static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
770{
771 u32 eec;
772 u32 i;
773 u16 data = 0;
774
775 /*
776 * In order to read a register from the EEPROM, we need to shift
777 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
778 * the clock input to the EEPROM (setting the SK bit), and then reading
779 * the value of the "DO" bit. During this "shifting in" process the
780 * "DI" bit should always be clear.
781 */
782 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
783
784 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
785
786 for (i = 0; i < count; i++) {
787 data = data << 1;
788 ixgbe_raise_eeprom_clk(hw, &eec);
789
790 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
791
792 eec &= ~(IXGBE_EEC_DI);
793 if (eec & IXGBE_EEC_DO)
794 data |= 1;
795
796 ixgbe_lower_eeprom_clk(hw, &eec);
797 }
798
799 return data;
800}
801
802/**
803 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
804 * @hw: pointer to hardware structure
805 * @eec: EEC register's current value
806 **/
807static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
808{
809 /*
810 * Raise the clock input to the EEPROM
811 * (setting the SK bit), then delay
812 */
813 *eec = *eec | IXGBE_EEC_SK;
814 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
815 IXGBE_WRITE_FLUSH(hw);
816 udelay(1);
817}
818
819/**
820 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
821 * @hw: pointer to hardware structure
822 * @eecd: EECD's current value
823 **/
824static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
825{
826 /*
827 * Lower the clock input to the EEPROM (clearing the SK bit), then
828 * delay
829 */
830 *eec = *eec & ~IXGBE_EEC_SK;
831 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
832 IXGBE_WRITE_FLUSH(hw);
833 udelay(1);
834}
835
836/**
837 * ixgbe_release_eeprom - Release EEPROM, release semaphores
838 * @hw: pointer to hardware structure
839 **/
840static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
841{
842 u32 eec;
843
844 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
845
846 eec |= IXGBE_EEC_CS; /* Pull CS high */
847 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
848
849 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
850 IXGBE_WRITE_FLUSH(hw);
851
852 udelay(1);
853
854 /* Stop requesting EEPROM access */
855 eec &= ~IXGBE_EEC_REQ;
856 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
857
858 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
859}
860
9a799d71
AK		 861/**
862 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
863 * @hw: pointer to hardware structure
864 **/
865static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
866{
867 u16 i;
868 u16 j;
869 u16 checksum = 0;
870 u16 length = 0;
871 u16 pointer = 0;
872 u16 word = 0;
873
874 /* Include 0x0-0x3F in the checksum */
875 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
c44ade9e 876 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
9a799d71
AK		 877 hw_dbg(hw, "EEPROM read failed\n");
878 break;
879 }
880 checksum += word;
881 }
882
883 /* Include all data from pointers except for the fw pointer */
884 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
c44ade9e 885 hw->eeprom.ops.read(hw, i, &pointer);
9a799d71
AK		 886
887 /* Make sure the pointer seems valid */
888 if (pointer != 0xFFFF && pointer != 0) {
c44ade9e 889 hw->eeprom.ops.read(hw, pointer, &length);
9a799d71
AK		 890
891 if (length != 0xFFFF && length != 0) {
892 for (j = pointer+1; j <= pointer+length; j++) {
c44ade9e 893 hw->eeprom.ops.read(hw, j, &word);
9a799d71
AK		 894 checksum += word;
895 }
896 }
897 }
898 }
899
900 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
901
902 return checksum;
903}
904
905/**
c44ade9e 906 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 907 * @hw: pointer to hardware structure
908 * @checksum_val: calculated checksum
909 *
910 * Performs checksum calculation and validates the EEPROM checksum. If the
911 * caller does not need checksum_val, the value can be NULL.
912 **/
c44ade9e
JB		 913s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
914 u16 *checksum_val)
9a799d71
AK		 915{
916 s32 status;
917 u16 checksum;
918 u16 read_checksum = 0;
919
920 /*
921 * Read the first word from the EEPROM. If this times out or fails, do
922 * not continue or we could be in for a very long wait while every
923 * EEPROM read fails
924 */
c44ade9e 925 status = hw->eeprom.ops.read(hw, 0, &checksum);
9a799d71
AK		 926
927 if (status == 0) {
928 checksum = ixgbe_calc_eeprom_checksum(hw);
929
c44ade9e 930 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
9a799d71
AK		 931
932 /*
933 * Verify read checksum from EEPROM is the same as
934 * calculated checksum
935 */
936 if (read_checksum != checksum)
937 status = IXGBE_ERR_EEPROM_CHECKSUM;
938
939 /* If the user cares, return the calculated checksum */
940 if (checksum_val)
941 *checksum_val = checksum;
942 } else {
943 hw_dbg(hw, "EEPROM read failed\n");
944 }
945
946 return status;
947}
948
c44ade9e
JB		 949/**
950 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
951 * @hw: pointer to hardware structure
952 **/
953s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
954{
955 s32 status;
956 u16 checksum;
957
958 /*
959 * Read the first word from the EEPROM. If this times out or fails, do
960 * not continue or we could be in for a very long wait while every
961 * EEPROM read fails
962 */
963 status = hw->eeprom.ops.read(hw, 0, &checksum);
964
965 if (status == 0) {
966 checksum = ixgbe_calc_eeprom_checksum(hw);
967 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
968 checksum);
969 } else {
970 hw_dbg(hw, "EEPROM read failed\n");
971 }
972
973 return status;
974}
975
9a799d71
AK		 976/**
977 * ixgbe_validate_mac_addr - Validate MAC address
978 * @mac_addr: pointer to MAC address.
979 *
980 * Tests a MAC address to ensure it is a valid Individual Address
981 **/
982s32 ixgbe_validate_mac_addr(u8 *mac_addr)
983{
984 s32 status = 0;
985
986 /* Make sure it is not a multicast address */
987 if (IXGBE_IS_MULTICAST(mac_addr))
988 status = IXGBE_ERR_INVALID_MAC_ADDR;
989 /* Not a broadcast address */
990 else if (IXGBE_IS_BROADCAST(mac_addr))
991 status = IXGBE_ERR_INVALID_MAC_ADDR;
992 /* Reject the zero address */
993 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
c44ade9e 994 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
9a799d71
AK		 995 status = IXGBE_ERR_INVALID_MAC_ADDR;
996
997 return status;
998}
999
1000/**
c44ade9e 1001 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1002 * @hw: pointer to hardware structure
9a799d71 1003 * @index: Receive address register to write
c44ade9e
JB		 1004 * @addr: Address to put into receive address register
1005 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1006 * @enable_addr: set flag that address is active
1007 *
1008 * Puts an ethernet address into a receive address register.
1009 **/
c44ade9e
JB		 1010s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1011 u32 enable_addr)
9a799d71
AK		 1012{
1013 u32 rar_low, rar_high;
c44ade9e
JB		 1014 u32 rar_entries = hw->mac.num_rar_entries;
1015
1016 /* setup VMDq pool selection before this RAR gets enabled */
1017 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1018
c44ade9e
JB		 1019 /* Make sure we are using a valid rar index range */
1020 if (index < rar_entries) {
9a799d71 1021 /*
c44ade9e
JB		 1022 * HW expects these in little endian so we reverse the byte
1023 * order from network order (big endian) to little endian
9a799d71
AK		 1024 */
1025 rar_low = ((u32)addr[0] |
1026 ((u32)addr[1] << 8) |
1027 ((u32)addr[2] << 16) |
1028 ((u32)addr[3] << 24));
c44ade9e
JB		 1029 /*
1030 * Some parts put the VMDq setting in the extra RAH bits,
1031 * so save everything except the lower 16 bits that hold part
1032 * of the address and the address valid bit.
1033 */
1034 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1035 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1036 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71
AK		 1037
1038 if (enable_addr != 0)
1039 rar_high |= IXGBE_RAH_AV;
1040
1041 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1042 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1043 } else {
1044 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1045 }
1046
1047 return 0;
1048}
1049
1050/**
1051 * ixgbe_clear_rar_generic - Remove Rx address register
1052 * @hw: pointer to hardware structure
1053 * @index: Receive address register to write
1054 *
1055 * Clears an ethernet address from a receive address register.
1056 **/
1057s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1058{
1059 u32 rar_high;
1060 u32 rar_entries = hw->mac.num_rar_entries;
1061
1062 /* Make sure we are using a valid rar index range */
1063 if (index < rar_entries) {
1064 /*
1065 * Some parts put the VMDq setting in the extra RAH bits,
1066 * so save everything except the lower 16 bits that hold part
1067 * of the address and the address valid bit.
1068 */
1069 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1070 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1071
1072 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1073 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1074 } else {
1075 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1076 }
1077
1078 /* clear VMDq pool/queue selection for this RAR */
1079 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1080
1081 return 0;
1082}
1083
1084/**
c44ade9e
JB		 1085 * ixgbe_enable_rar - Enable Rx address register
1086 * @hw: pointer to hardware structure
1087 * @index: index into the RAR table
1088 *
1089 * Enables the select receive address register.
1090 **/
1091static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
1092{
1093 u32 rar_high;
1094
1095 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1096 rar_high |= IXGBE_RAH_AV;
1097 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1098}
1099
1100/**
1101 * ixgbe_disable_rar - Disable Rx address register
1102 * @hw: pointer to hardware structure
1103 * @index: index into the RAR table
1104 *
1105 * Disables the select receive address register.
1106 **/
1107static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
1108{
1109 u32 rar_high;
1110
1111 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1112 rar_high &= (~IXGBE_RAH_AV);
1113 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1114}
1115
1116/**
1117 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1118 * @hw: pointer to hardware structure
1119 *
1120 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1121 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1122 * the receiver is in reset when the routine is called.
1123 **/
c44ade9e 1124s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1125{
1126 u32 i;
2c5645cf 1127 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1128
1129 /*
1130 * If the current mac address is valid, assume it is a software override
1131 * to the permanent address.
1132 * Otherwise, use the permanent address from the eeprom.
1133 */
1134 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1135 IXGBE_ERR_INVALID_MAC_ADDR) {
1136 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1137 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71
AK		 1138
1139 hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
1140 hw->mac.addr[0], hw->mac.addr[1],
1141 hw->mac.addr[2]);
1142 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
1143 hw->mac.addr[4], hw->mac.addr[5]);
1144 } else {
1145 /* Setup the receive address. */
1146 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1147 hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ",
1148 hw->mac.addr[0], hw->mac.addr[1],
1149 hw->mac.addr[2]);
1150 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
1151 hw->mac.addr[4], hw->mac.addr[5]);
1152
c44ade9e 1153 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71 1154 }
c44ade9e 1155 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1156
1157 hw->addr_ctrl.rar_used_count = 1;
1158
1159 /* Zero out the other receive addresses. */
c44ade9e 1160 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1161 for (i = 1; i < rar_entries; i++) {
1162 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1163 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1164 }
1165
1166 /* Clear the MTA */
1167 hw->addr_ctrl.mc_addr_in_rar_count = 0;
1168 hw->addr_ctrl.mta_in_use = 0;
1169 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1170
1171 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1172 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1173 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1174
c44ade9e
JB		 1175 if (hw->mac.ops.init_uta_tables)
1176 hw->mac.ops.init_uta_tables(hw);
1177
9a799d71
AK		 1178 return 0;
1179}
1180
2c5645cf
CL		 1181/**
1182 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1183 * @hw: pointer to hardware structure
1184 * @addr: new address
1185 *
1186 * Adds it to unused receive address register or goes into promiscuous mode.
1187 **/
c44ade9e 1188static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2c5645cf
CL		 1189{
1190 u32 rar_entries = hw->mac.num_rar_entries;
1191 u32 rar;
1192
1193 hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1194 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1195
1196 /*
1197 * Place this address in the RAR if there is room,
1198 * else put the controller into promiscuous mode
1199 */
1200 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1201 rar = hw->addr_ctrl.rar_used_count -
1202 hw->addr_ctrl.mc_addr_in_rar_count;
c44ade9e 1203 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2c5645cf
CL		 1204 hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
1205 hw->addr_ctrl.rar_used_count++;
1206 } else {
1207 hw->addr_ctrl.overflow_promisc++;
1208 }
1209
1210 hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
1211}
1212
1213/**
c44ade9e 1214 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2c5645cf
CL		 1215 * @hw: pointer to hardware structure
1216 * @addr_list: the list of new addresses
1217 * @addr_count: number of addresses
1218 * @next: iterator function to walk the address list
1219 *
1220 * The given list replaces any existing list. Clears the secondary addrs from
1221 * receive address registers. Uses unused receive address registers for the
1222 * first secondary addresses, and falls back to promiscuous mode as needed.
1223 *
1224 * Drivers using secondary unicast addresses must set user_set_promisc when
1225 * manually putting the device into promiscuous mode.
1226 **/
c44ade9e 1227s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2c5645cf
CL		 1228 u32 addr_count, ixgbe_mc_addr_itr next)
1229{
1230 u8 *addr;
1231 u32 i;
1232 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1233 u32 uc_addr_in_use;
1234 u32 fctrl;
1235 u32 vmdq;
1236
1237 /*
1238 * Clear accounting of old secondary address list,
1239 * don't count RAR[0]
1240 */
1241 uc_addr_in_use = hw->addr_ctrl.rar_used_count -
1242 hw->addr_ctrl.mc_addr_in_rar_count - 1;
1243 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1244 hw->addr_ctrl.overflow_promisc = 0;
1245
1246 /* Zero out the other receive addresses */
1247 hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use);
1248 for (i = 1; i <= uc_addr_in_use; i++) {
1249 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1250 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1251 }
1252
1253 /* Add the new addresses */
1254 for (i = 0; i < addr_count; i++) {
1255 hw_dbg(hw, " Adding the secondary addresses:\n");
1256 addr = next(hw, &addr_list, &vmdq);
c44ade9e 1257 ixgbe_add_uc_addr(hw, addr, vmdq);
2c5645cf
CL		 1258 }
1259
1260 if (hw->addr_ctrl.overflow_promisc) {
1261 /* enable promisc if not already in overflow or set by user */
1262 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1263 hw_dbg(hw, " Entering address overflow promisc mode\n");
1264 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1265 fctrl |= IXGBE_FCTRL_UPE;
1266 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1267 }
1268 } else {
1269 /* only disable if set by overflow, not by user */
1270 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1271 hw_dbg(hw, " Leaving address overflow promisc mode\n");
1272 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1273 fctrl &= ~IXGBE_FCTRL_UPE;
1274 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1275 }
1276 }
1277
c44ade9e 1278 hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
2c5645cf
CL		 1279 return 0;
1280}
1281
9a799d71
AK		 1282/**
1283 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1284 * @hw: pointer to hardware structure
1285 * @mc_addr: the multicast address
1286 *
1287 * Extracts the 12 bits, from a multicast address, to determine which
1288 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1289 * incoming rx multicast addresses, to determine the bit-vector to check in
1290 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1291 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1292 * to mc_filter_type.
1293 **/
1294static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1295{
1296 u32 vector = 0;
1297
1298 switch (hw->mac.mc_filter_type) {
1299 case 0: /* use bits [47:36] of the address */
1300 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1301 break;
1302 case 1: /* use bits [46:35] of the address */
1303 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1304 break;
1305 case 2: /* use bits [45:34] of the address */
1306 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1307 break;
1308 case 3: /* use bits [43:32] of the address */
1309 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1310 break;
1311 default: /* Invalid mc_filter_type */
1312 hw_dbg(hw, "MC filter type param set incorrectly\n");
1313 break;
1314 }
1315
1316 /* vector can only be 12-bits or boundary will be exceeded */
1317 vector &= 0xFFF;
1318 return vector;
1319}
1320
1321/**
1322 * ixgbe_set_mta - Set bit-vector in multicast table
1323 * @hw: pointer to hardware structure
1324 * @hash_value: Multicast address hash value
1325 *
1326 * Sets the bit-vector in the multicast table.
1327 **/
1328static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1329{
1330 u32 vector;
1331 u32 vector_bit;
1332 u32 vector_reg;
1333 u32 mta_reg;
1334
1335 hw->addr_ctrl.mta_in_use++;
1336
1337 vector = ixgbe_mta_vector(hw, mc_addr);
1338 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1339
1340 /*
1341 * The MTA is a register array of 128 32-bit registers. It is treated
1342 * like an array of 4096 bits. We want to set bit
1343 * BitArray[vector_value]. So we figure out what register the bit is
1344 * in, read it, OR in the new bit, then write back the new value. The
1345 * register is determined by the upper 7 bits of the vector value and
1346 * the bit within that register are determined by the lower 5 bits of
1347 * the value.
1348 */
1349 vector_reg = (vector >> 5) & 0x7F;
1350 vector_bit = vector & 0x1F;
1351 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
1352 mta_reg |= (1 << vector_bit);
1353 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
1354}
1355
1356/**
1357 * ixgbe_add_mc_addr - Adds a multicast address.
1358 * @hw: pointer to hardware structure
1359 * @mc_addr: new multicast address
1360 *
1361 * Adds it to unused receive address register or to the multicast table.
1362 **/
1363static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr)
1364{
2c5645cf 1365 u32 rar_entries = hw->mac.num_rar_entries;
ce94bf46 1366 u32 rar;
9a799d71
AK		 1367
1368 hw_dbg(hw, " MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n",
1369 mc_addr[0], mc_addr[1], mc_addr[2],
1370 mc_addr[3], mc_addr[4], mc_addr[5]);
1371
1372 /*
1373 * Place this multicast address in the RAR if there is room,
1374 * else put it in the MTA
1375 */
1376 if (hw->addr_ctrl.rar_used_count < rar_entries) {
c44ade9e 1377 /* use RAR from the end up for multicast */
ce94bf46 1378 rar = rar_entries - hw->addr_ctrl.mc_addr_in_rar_count - 1;
c44ade9e
JB		 1379 hw->mac.ops.set_rar(hw, rar, mc_addr, 0, IXGBE_RAH_AV);
1380 hw_dbg(hw, "Added a multicast address to RAR[%d]\n", rar);
9a799d71
AK		 1381 hw->addr_ctrl.rar_used_count++;
1382 hw->addr_ctrl.mc_addr_in_rar_count++;
1383 } else {
1384 ixgbe_set_mta(hw, mc_addr);
1385 }
1386
1387 hw_dbg(hw, "ixgbe_add_mc_addr Complete\n");
1388}
1389
1390/**
c44ade9e 1391 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71
AK		 1392 * @hw: pointer to hardware structure
1393 * @mc_addr_list: the list of new multicast addresses
1394 * @mc_addr_count: number of addresses
2c5645cf 1395 * @next: iterator function to walk the multicast address list
9a799d71
AK		 1396 *
1397 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 1398 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 1399 * registers for the first multicast addresses, and hashes the rest into the
1400 * multicast table.
1401 **/
c44ade9e 1402s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2c5645cf 1403 u32 mc_addr_count, ixgbe_mc_addr_itr next)
9a799d71
AK		 1404{
1405 u32 i;
2c5645cf
CL		 1406 u32 rar_entries = hw->mac.num_rar_entries;
1407 u32 vmdq;
9a799d71
AK		 1408
1409 /*
1410 * Set the new number of MC addresses that we are being requested to
1411 * use.
1412 */
1413 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
1414 hw->addr_ctrl.rar_used_count -= hw->addr_ctrl.mc_addr_in_rar_count;
1415 hw->addr_ctrl.mc_addr_in_rar_count = 0;
1416 hw->addr_ctrl.mta_in_use = 0;
1417
1418 /* Zero out the other receive addresses. */
c44ade9e
JB		 1419 hw_dbg(hw, "Clearing RAR[%d-%d]\n", hw->addr_ctrl.rar_used_count,
1420 rar_entries - 1);
9a799d71
AK		 1421 for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) {
1422 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1423 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1424 }
1425
1426 /* Clear the MTA */
1427 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1428 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1429 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1430
1431 /* Add the new addresses */
1432 for (i = 0; i < mc_addr_count; i++) {
1433 hw_dbg(hw, " Adding the multicast addresses:\n");
2c5645cf 1434 ixgbe_add_mc_addr(hw, next(hw, &mc_addr_list, &vmdq));
9a799d71
AK		 1435 }
1436
1437 /* Enable mta */
1438 if (hw->addr_ctrl.mta_in_use > 0)
1439 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
1440 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
1441
c44ade9e 1442 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 1443 return 0;
1444}
1445
1446/**
c44ade9e 1447 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 1448 * @hw: pointer to hardware structure
1449 *
c44ade9e 1450 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 1451 **/
c44ade9e 1452s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1453{
c44ade9e
JB		 1454 u32 i;
1455 u32 rar_entries = hw->mac.num_rar_entries;
1456 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 1457
c44ade9e
JB		 1458 if (a->mc_addr_in_rar_count > 0)
1459 for (i = (rar_entries - a->mc_addr_in_rar_count);
1460 i < rar_entries; i++)
1461 ixgbe_enable_rar(hw, i);
9a799d71 1462
c44ade9e
JB		 1463 if (a->mta_in_use > 0)
1464 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1465 hw->mac.mc_filter_type);
9a799d71
AK		 1466
1467 return 0;
1468}
1469
1470/**
c44ade9e 1471 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 1472 * @hw: pointer to hardware structure
9a799d71 1473 *
c44ade9e 1474 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 1475 **/
c44ade9e 1476s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1477{
c44ade9e
JB		 1478 u32 i;
1479 u32 rar_entries = hw->mac.num_rar_entries;
1480 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 1481
c44ade9e
JB		 1482 if (a->mc_addr_in_rar_count > 0)
1483 for (i = (rar_entries - a->mc_addr_in_rar_count);
1484 i < rar_entries; i++)
1485 ixgbe_disable_rar(hw, i);
9a799d71 1486
c44ade9e
JB		 1487 if (a->mta_in_use > 0)
1488 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 1489
1490 return 0;
1491}
1492
1493/**
1494 * ixgbe_disable_pcie_master - Disable PCI-express master access
1495 * @hw: pointer to hardware structure
1496 *
1497 * Disables PCI-Express master access and verifies there are no pending
1498 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
1499 * bit hasn't caused the master requests to be disabled, else 0
1500 * is returned signifying master requests disabled.
1501 **/
1502s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
1503{
c44ade9e
JB		 1504 u32 i;
1505 u32 reg_val;
1506 u32 number_of_queues;
9a799d71
AK		 1507 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
1508
c44ade9e
JB		 1509 /* Disable the receive unit by stopping each queue */
1510 number_of_queues = hw->mac.max_rx_queues;
1511 for (i = 0; i < number_of_queues; i++) {
1512 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1513 if (reg_val & IXGBE_RXDCTL_ENABLE) {
1514 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1515 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1516 }
1517 }
1518
1519 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
1520 reg_val |= IXGBE_CTRL_GIO_DIS;
1521 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
9a799d71
AK		 1522
1523 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
1524 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
1525 status = 0;
1526 break;
1527 }
1528 udelay(100);
1529 }
1530
1531 return status;
1532}
1533
1534
1535/**
c44ade9e 1536 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 1537 * @hw: pointer to hardware structure
c44ade9e 1538 * @mask: Mask to specify which semaphore to acquire
9a799d71 1539 *
c44ade9e 1540 * Acquires the SWFW semaphore thought the GSSR register for the specified
9a799d71
AK		 1541 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1542 **/
1543s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
1544{
1545 u32 gssr;
1546 u32 swmask = mask;
1547 u32 fwmask = mask << 5;
1548 s32 timeout = 200;
1549
1550 while (timeout) {
1551 if (ixgbe_get_eeprom_semaphore(hw))
1552 return -IXGBE_ERR_SWFW_SYNC;
1553
1554 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
1555 if (!(gssr & (fwmask | swmask)))
1556 break;
1557
1558 /*
1559 * Firmware currently using resource (fwmask) or other software
1560 * thread currently using resource (swmask)
1561 */
1562 ixgbe_release_eeprom_semaphore(hw);
1563 msleep(5);
1564 timeout--;
1565 }
1566
1567 if (!timeout) {
1568 hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
1569 return -IXGBE_ERR_SWFW_SYNC;
1570 }
1571
1572 gssr |= swmask;
1573 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
1574
1575 ixgbe_release_eeprom_semaphore(hw);
1576 return 0;
1577}
1578
1579/**
1580 * ixgbe_release_swfw_sync - Release SWFW semaphore
1581 * @hw: pointer to hardware structure
c44ade9e 1582 * @mask: Mask to specify which semaphore to release
9a799d71 1583 *
c44ade9e 1584 * Releases the SWFW semaphore thought the GSSR register for the specified
9a799d71
AK		 1585 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1586 **/
1587void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
1588{
1589 u32 gssr;
1590 u32 swmask = mask;
1591
1592 ixgbe_get_eeprom_semaphore(hw);
1593
1594 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
1595 gssr &= ~swmask;
1596 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
1597
1598 ixgbe_release_eeprom_semaphore(hw);
1599}
1600
Clone of davem's net-next-2.6 tree