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ixgbe: Add hardware defines for Flow Director for 82599
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
34
35#define IXGBE_82599_MAX_TX_QUEUES 128
36#define IXGBE_82599_MAX_RX_QUEUES 128
37#define IXGBE_82599_RAR_ENTRIES 128
38#define IXGBE_82599_MC_TBL_SIZE 128
39#define IXGBE_82599_VFT_TBL_SIZE 128
40
41s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
45s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw);
46s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed, bool autoneg,
48 bool autoneg_wait_to_complete);
49s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw);
50s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
51 ixgbe_link_speed *speed,
52 bool *link_up, bool link_up_wait_to_complete);
53s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
54 ixgbe_link_speed speed,
55 bool autoneg,
56 bool autoneg_wait_to_complete);
57static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
58 ixgbe_link_speed *speed,
59 bool *autoneg);
60static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw);
61static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
62 ixgbe_link_speed speed,
63 bool autoneg,
64 bool autoneg_wait_to_complete);
65s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
66s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
67s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
68s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan,
69 u32 vind, bool vlan_on);
70s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw);
11afc1b1
PW		 71s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw);
72s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
73s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
74s32 ixgbe_start_hw_rev_0_82599(struct ixgbe_hw *hw);
75s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
76s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
77u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
78
79void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
80{
81 struct ixgbe_mac_info *mac = &hw->mac;
82 if (hw->phy.multispeed_fiber) {
83 /* Set up dual speed SFP+ support */
84 mac->ops.setup_link =
85 &ixgbe_setup_mac_link_multispeed_fiber;
86 mac->ops.setup_link_speed =
87 &ixgbe_setup_mac_link_speed_multispeed_fiber;
88 } else {
89 mac->ops.setup_link =
90 &ixgbe_setup_mac_link_82599;
91 mac->ops.setup_link_speed =
92 &ixgbe_setup_mac_link_speed_82599;
93 }
94}
95
96s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
97{
98 s32 ret_val = 0;
99 u16 list_offset, data_offset, data_value;
100
101 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
102 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 103
104 hw->phy.ops.reset = NULL;
105
11afc1b1
PW		 106 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
107 &data_offset);
108
109 if (ret_val != 0)
110 goto setup_sfp_out;
111
aa5aec88
PWJ		 112 /* PHY config will finish before releasing the semaphore */
113 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
114 if (ret_val != 0) {
115 ret_val = IXGBE_ERR_SWFW_SYNC;
116 goto setup_sfp_out;
117 }
118
11afc1b1
PW		 119 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
120 while (data_value != 0xffff) {
121 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
122 IXGBE_WRITE_FLUSH(hw);
123 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
124 }
1479ad4f
PWJ		 125 /* Now restart DSP by setting Restart_AN */
126 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
127 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
aa5aec88
PWJ		 128
129 /* Release the semaphore */
130 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
131 /* Delay obtaining semaphore again to allow FW access */
132 msleep(hw->eeprom.semaphore_delay);
11afc1b1
PW		 133 }
134
135setup_sfp_out:
136 return ret_val;
137}
138
139/**
140 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
141 * @hw: pointer to hardware structure
142 *
143 * Read PCIe configuration space, and get the MSI-X vector count from
144 * the capabilities table.
145 **/
146u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
147{
148 struct ixgbe_adapter *adapter = hw->back;
149 u16 msix_count;
150 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
151 &msix_count);
152 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
153
154 /* MSI-X count is zero-based in HW, so increment to give proper value */
155 msix_count++;
156
157 return msix_count;
158}
159
160static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
161{
162 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 163
04f165ef 164 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 165
04f165ef
PW		 166 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
167 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
168 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
169 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
170 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
171 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
11afc1b1 172
04f165ef
PW		 173 return 0;
174}
11afc1b1 175
04f165ef
PW		 176/**
177 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
178 * @hw: pointer to hardware structure
179 *
180 * Initialize any function pointers that were not able to be
181 * set during get_invariants because the PHY/SFP type was
182 * not known. Perform the SFP init if necessary.
183 *
184 **/
185s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
186{
187 struct ixgbe_mac_info *mac = &hw->mac;
188 struct ixgbe_phy_info *phy = &hw->phy;
189 s32 ret_val = 0;
11afc1b1 190
04f165ef
PW		 191 /* Identify the PHY or SFP module */
192 ret_val = phy->ops.identify(hw);
193
194 /* Setup function pointers based on detected SFP module and speeds */
195 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 196
197 /* If copper media, overwrite with copper function pointers */
198 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
199 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
200 mac->ops.setup_link_speed =
04f165ef 201 &ixgbe_setup_copper_link_speed_82599;
11afc1b1
PW		 202 mac->ops.get_link_capabilities =
203 &ixgbe_get_copper_link_capabilities_82599;
204 }
205
04f165ef 206 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 207 switch (hw->phy.type) {
208 case ixgbe_phy_tn:
209 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
210 phy->ops.get_firmware_version =
04f165ef 211 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1
PW		 212 break;
213 default:
214 break;
215 }
216
11afc1b1
PW		 217 return ret_val;
218}
219
220/**
221 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
222 * @hw: pointer to hardware structure
223 * @speed: pointer to link speed
224 * @negotiation: true when autoneg or autotry is enabled
225 *
226 * Determines the link capabilities by reading the AUTOC register.
227 **/
228s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
229 ixgbe_link_speed *speed,
230 bool *negotiation)
231{
232 s32 status = 0;
1eb99d5a 233 u32 autoc = 0;
11afc1b1 234
1eb99d5a
PW		 235 /*
236 * Determine link capabilities based on the stored value of AUTOC,
237 * which represents EEPROM defaults. If AUTOC value has not been
238 * stored, use the current register value.
239 */
240 if (hw->mac.orig_link_settings_stored)
241 autoc = hw->mac.orig_autoc;
242 else
243 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
244
245 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 246 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
247 *speed = IXGBE_LINK_SPEED_1GB_FULL;
248 *negotiation = false;
249 break;
250
251 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
252 *speed = IXGBE_LINK_SPEED_10GB_FULL;
253 *negotiation = false;
254 break;
255
256 case IXGBE_AUTOC_LMS_1G_AN:
257 *speed = IXGBE_LINK_SPEED_1GB_FULL;
258 *negotiation = true;
259 break;
260
261 case IXGBE_AUTOC_LMS_10G_SERIAL:
262 *speed = IXGBE_LINK_SPEED_10GB_FULL;
263 *negotiation = false;
264 break;
265
266 case IXGBE_AUTOC_LMS_KX4_KX_KR:
267 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
268 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 269 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 270 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 271 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 272 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 273 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 274 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
275 *negotiation = true;
276 break;
277
278 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
279 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 280 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 281 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 282 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 283 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 284 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 285 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
286 *negotiation = true;
287 break;
288
289 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
290 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
291 *negotiation = false;
292 break;
293
294 default:
295 status = IXGBE_ERR_LINK_SETUP;
296 goto out;
297 break;
298 }
299
300 if (hw->phy.multispeed_fiber) {
301 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
302 IXGBE_LINK_SPEED_1GB_FULL;
303 *negotiation = true;
304 }
305
306out:
307 return status;
308}
309
310/**
311 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
312 * @hw: pointer to hardware structure
313 * @speed: pointer to link speed
314 * @autoneg: boolean auto-negotiation value
315 *
316 * Determines the link capabilities by reading the AUTOC register.
317 **/
318static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
319 ixgbe_link_speed *speed,
320 bool *autoneg)
321{
322 s32 status = IXGBE_ERR_LINK_SETUP;
323 u16 speed_ability;
324
325 *speed = 0;
326 *autoneg = true;
327
6b73e10d 328 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
11afc1b1
PW		 329 &speed_ability);
330
331 if (status == 0) {
6b73e10d 332 if (speed_ability & MDIO_SPEED_10G)
11afc1b1 333 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
6b73e10d 334 if (speed_ability & MDIO_PMA_SPEED_1000)
11afc1b1
PW		 335 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
336 }
337
338 return status;
339}
340
341/**
342 * ixgbe_get_media_type_82599 - Get media type
343 * @hw: pointer to hardware structure
344 *
345 * Returns the media type (fiber, copper, backplane)
346 **/
347enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
348{
349 enum ixgbe_media_type media_type;
350
351 /* Detect if there is a copper PHY attached. */
352 if (hw->phy.type == ixgbe_phy_cu_unknown ||
353 hw->phy.type == ixgbe_phy_tn) {
354 media_type = ixgbe_media_type_copper;
355 goto out;
356 }
357
358 switch (hw->device_id) {
11afc1b1 359 case IXGBE_DEV_ID_82599_KX4:
1fcf03e6 360 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 361 /* Default device ID is mezzanine card KX/KX4 */
362 media_type = ixgbe_media_type_backplane;
363 break;
364 case IXGBE_DEV_ID_82599_SFP:
365 media_type = ixgbe_media_type_fiber;
366 break;
367 default:
368 media_type = ixgbe_media_type_unknown;
369 break;
370 }
371out:
372 return media_type;
373}
374
375/**
376 * ixgbe_setup_mac_link_82599 - Setup MAC link settings
377 * @hw: pointer to hardware structure
378 *
379 * Configures link settings based on values in the ixgbe_hw struct.
380 * Restarts the link. Performs autonegotiation if needed.
381 **/
382s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
383{
384 u32 autoc_reg;
385 u32 links_reg;
386 u32 i;
387 s32 status = 0;
388
389 /* Restart link */
390 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
391 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
392 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
393
394 /* Only poll for autoneg to complete if specified to do so */
395 if (hw->phy.autoneg_wait_to_complete) {
396 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
397 IXGBE_AUTOC_LMS_KX4_KX_KR ||
398 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
399 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
400 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
401 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
402 links_reg = 0; /* Just in case Autoneg time = 0 */
403 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
404 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
405 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
406 break;
407 msleep(100);
408 }
409 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
410 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
411 hw_dbg(hw, "Autoneg did not complete.\n");
412 }
413 }
414 }
415
11afc1b1
PW		 416 /* Add delay to filter out noises during initial link setup */
417 msleep(50);
418
419 return status;
420}
421
422/**
423 * ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings
424 * @hw: pointer to hardware structure
425 *
426 * Configures link settings based on values in the ixgbe_hw struct.
427 * Restarts the link for multi-speed fiber at 1G speed, if link
428 * fails at 10G.
429 * Performs autonegotiation if needed.
430 **/
431s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw)
432{
433 s32 status = 0;
434 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG;
4df10466 435 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, link_speed,
11afc1b1
PW		 436 true, true);
437 return status;
438}
439
440/**
441 * ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed
442 * @hw: pointer to hardware structure
443 * @speed: new link speed
444 * @autoneg: true if autonegotiation enabled
445 * @autoneg_wait_to_complete: true when waiting for completion is needed
446 *
447 * Set the link speed in the AUTOC register and restarts link.
448 **/
449s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
450 ixgbe_link_speed speed,
451 bool autoneg,
452 bool autoneg_wait_to_complete)
453{
454 s32 status = 0;
455 ixgbe_link_speed phy_link_speed;
456 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
457 u32 speedcnt = 0;
458 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
459 bool link_up = false;
460 bool negotiation;
50ac58ba 461 int i;
11afc1b1
PW		 462
463 /* Mask off requested but non-supported speeds */
464 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
465 speed &= phy_link_speed;
466
74766013
MC		 467 /* Set autoneg_advertised value based on input link speed */
468 hw->phy.autoneg_advertised = 0;
469
470 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
471 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
472
473 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
474 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
475
50ac58ba
PWJ		 476 /*
477 * When the driver changes the link speeds that it can support,
478 * it sets autotry_restart to true to indicate that we need to
479 * initiate a new autotry session with the link partner. To do
480 * so, we set the speed then disable and re-enable the tx laser, to
481 * alert the link partner that it also needs to restart autotry on its
482 * end. This is consistent with true clause 37 autoneg, which also
483 * involves a loss of signal.
484 */
485
11afc1b1
PW		 486 /*
487 * Try each speed one by one, highest priority first. We do this in
488 * software because 10gb fiber doesn't support speed autonegotiation.
489 */
490 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
491 speedcnt++;
492 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
493
50ac58ba
PWJ		 494 /* If we already have link at this speed, just jump out */
495 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
496
497 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
498 goto out;
499
500 /* Set the module link speed */
11afc1b1
PW		 501 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
502 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
503
50ac58ba
PWJ		 504 /* Allow module to change analog characteristics (1G->10G) */
505 msleep(40);
11afc1b1 506
50ac58ba
PWJ		 507 status = ixgbe_setup_mac_link_speed_82599(hw,
508 IXGBE_LINK_SPEED_10GB_FULL,
509 autoneg,
510 autoneg_wait_to_complete);
511 if (status != 0)
11afc1b1 512 goto out;
50ac58ba
PWJ		 513
514 /* Flap the tx laser if it has not already been done */
515 if (hw->mac.autotry_restart) {
516 /* Disable tx laser; allow 100us to go dark per spec */
517 esdp_reg |= IXGBE_ESDP_SDP3;
518 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
519 udelay(100);
520
521 /* Enable tx laser; allow 2ms to light up per spec */
522 esdp_reg &= ~IXGBE_ESDP_SDP3;
523 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
524 msleep(2);
525
526 hw->mac.autotry_restart = false;
527 }
528
529 /* The controller may take up to 500ms at 10g to acquire link */
530 for (i = 0; i < 5; i++) {
531 /* Wait for the link partner to also set speed */
532 msleep(100);
533
534 /* If we have link, just jump out */
535 hw->mac.ops.check_link(hw, &phy_link_speed,
536 &link_up, false);
537 if (link_up)
538 goto out;
539 }
11afc1b1
PW		 540 }
541
542 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
543 speedcnt++;
544 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
545 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
546
50ac58ba
PWJ		 547 /* If we already have link at this speed, just jump out */
548 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
549
550 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
551 goto out;
552
553 /* Set the module link speed */
11afc1b1
PW		 554 esdp_reg &= ~IXGBE_ESDP_SDP5;
555 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
556 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
557
50ac58ba
PWJ		 558 /* Allow module to change analog characteristics (10G->1G) */
559 msleep(40);
11afc1b1 560
50ac58ba
PWJ		 561 status = ixgbe_setup_mac_link_speed_82599(hw,
562 IXGBE_LINK_SPEED_1GB_FULL,
563 autoneg,
564 autoneg_wait_to_complete);
565 if (status != 0)
566 goto out;
567
568 /* Flap the tx laser if it has not already been done */
569 if (hw->mac.autotry_restart) {
570 /* Disable tx laser; allow 100us to go dark per spec */
571 esdp_reg |= IXGBE_ESDP_SDP3;
572 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
573 udelay(100);
574
575 /* Enable tx laser; allow 2ms to light up per spec */
576 esdp_reg &= ~IXGBE_ESDP_SDP3;
577 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
578 msleep(2);
579
580 hw->mac.autotry_restart = false;
581 }
582
583 /* Wait for the link partner to also set speed */
584 msleep(100);
11afc1b1
PW		 585
586 /* If we have link, just jump out */
587 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
588 if (link_up)
589 goto out;
590 }
591
592 /*
593 * We didn't get link. Configure back to the highest speed we tried,
594 * (if there was more than one). We call ourselves back with just the
595 * single highest speed that the user requested.
596 */
597 if (speedcnt > 1)
598 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
599 highest_link_speed,
600 autoneg,
601 autoneg_wait_to_complete);
602
603out:
604 return status;
605}
606
607/**
608 * ixgbe_check_mac_link_82599 - Determine link and speed status
609 * @hw: pointer to hardware structure
610 * @speed: pointer to link speed
611 * @link_up: true when link is up
612 * @link_up_wait_to_complete: bool used to wait for link up or not
613 *
614 * Reads the links register to determine if link is up and the current speed
615 **/
616s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
617 bool *link_up, bool link_up_wait_to_complete)
618{
619 u32 links_reg;
620 u32 i;
621
622 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
623 if (link_up_wait_to_complete) {
624 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
625 if (links_reg & IXGBE_LINKS_UP) {
626 *link_up = true;
627 break;
628 } else {
629 *link_up = false;
630 }
631 msleep(100);
632 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
633 }
634 } else {
635 if (links_reg & IXGBE_LINKS_UP)
636 *link_up = true;
637 else
638 *link_up = false;
639 }
640
641 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
642 IXGBE_LINKS_SPEED_10G_82599)
643 *speed = IXGBE_LINK_SPEED_10GB_FULL;
644 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
645 IXGBE_LINKS_SPEED_1G_82599)
646 *speed = IXGBE_LINK_SPEED_1GB_FULL;
647 else
648 *speed = IXGBE_LINK_SPEED_100_FULL;
649
620fa036
MC		 650 /* if link is down, zero out the current_mode */
651 if (*link_up == false) {
652 hw->fc.current_mode = ixgbe_fc_none;
653 hw->fc.fc_was_autonegged = false;
654 }
11afc1b1
PW		 655
656 return 0;
657}
658
659/**
660 * ixgbe_setup_mac_link_speed_82599 - Set MAC link speed
661 * @hw: pointer to hardware structure
662 * @speed: new link speed
663 * @autoneg: true if autonegotiation enabled
664 * @autoneg_wait_to_complete: true when waiting for completion is needed
665 *
666 * Set the link speed in the AUTOC register and restarts link.
667 **/
668s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
669 ixgbe_link_speed speed, bool autoneg,
670 bool autoneg_wait_to_complete)
671{
672 s32 status = 0;
673 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
674 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
50ac58ba 675 u32 start_autoc = autoc;
1eb99d5a 676 u32 orig_autoc = 0;
11afc1b1
PW		 677 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
678 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
679 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
680 u32 links_reg;
681 u32 i;
682 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
683
684 /* Check to see if speed passed in is supported. */
685 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
686 speed &= link_capabilities;
687
50ac58ba
PWJ		 688 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
689 status = IXGBE_ERR_LINK_SETUP;
690 goto out;
691 }
692
1eb99d5a
PW		 693 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
694 if (hw->mac.orig_link_settings_stored)
695 orig_autoc = hw->mac.orig_autoc;
696 else
697 orig_autoc = autoc;
698
699
50ac58ba
PWJ		 700 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
701 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
702 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
11afc1b1
PW		 703 /* Set KX4/KX/KR support according to speed requested */
704 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
705 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1eb99d5a 706 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 707 autoc |= IXGBE_AUTOC_KX4_SUPP;
1eb99d5a 708 if (orig_autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1
PW		 709 autoc |= IXGBE_AUTOC_KR_SUPP;
710 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
711 autoc |= IXGBE_AUTOC_KX_SUPP;
712 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
713 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
714 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
715 /* Switch from 1G SFI to 10G SFI if requested */
716 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
717 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
718 autoc &= ~IXGBE_AUTOC_LMS_MASK;
719 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
720 }
721 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
722 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
723 /* Switch from 10G SFI to 1G SFI if requested */
724 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
725 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
726 autoc &= ~IXGBE_AUTOC_LMS_MASK;
727 if (autoneg)
728 autoc |= IXGBE_AUTOC_LMS_1G_AN;
729 else
730 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
731 }
732 }
733
50ac58ba 734 if (autoc != start_autoc) {
11afc1b1
PW		 735 /* Restart link */
736 autoc |= IXGBE_AUTOC_AN_RESTART;
737 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
738
739 /* Only poll for autoneg to complete if specified to do so */
740 if (autoneg_wait_to_complete) {
741 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
742 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
743 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
744 links_reg = 0; /*Just in case Autoneg time=0*/
745 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
746 links_reg =
747 IXGBE_READ_REG(hw, IXGBE_LINKS);
748 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
749 break;
750 msleep(100);
751 }
752 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
753 status =
754 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
755 hw_dbg(hw, "Autoneg did not "
756 "complete.\n");
757 }
758 }
759 }
760
11afc1b1
PW		 761 /* Add delay to filter out noises during initial link setup */
762 msleep(50);
763 }
764
50ac58ba 765out:
11afc1b1
PW		 766 return status;
767}
768
769/**
770 * ixgbe_setup_copper_link_82599 - Setup copper link settings
771 * @hw: pointer to hardware structure
772 *
773 * Restarts the link on PHY and then MAC. Performs autonegotiation if needed.
774 **/
775static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw)
776{
777 s32 status;
778
779 /* Restart autonegotiation on PHY */
780 status = hw->phy.ops.setup_link(hw);
781
782 /* Set up MAC */
783 ixgbe_setup_mac_link_82599(hw);
784
785 return status;
786}
787
788/**
789 * ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field
790 * @hw: pointer to hardware structure
791 * @speed: new link speed
792 * @autoneg: true if autonegotiation enabled
793 * @autoneg_wait_to_complete: true if waiting is needed to complete
794 *
795 * Restarts link on PHY and MAC based on settings passed in.
796 **/
797static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
798 ixgbe_link_speed speed,
799 bool autoneg,
800 bool autoneg_wait_to_complete)
801{
802 s32 status;
803
804 /* Setup the PHY according to input speed */
805 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
806 autoneg_wait_to_complete);
807 /* Set up MAC */
808 ixgbe_setup_mac_link_82599(hw);
809
810 return status;
811}
812
813/**
814 * ixgbe_reset_hw_82599 - Perform hardware reset
815 * @hw: pointer to hardware structure
816 *
817 * Resets the hardware by resetting the transmit and receive units, masks
818 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
819 * reset.
820 **/
821s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
822{
823 s32 status = 0;
824 u32 ctrl, ctrl_ext;
825 u32 i;
826 u32 autoc;
827 u32 autoc2;
828
829 /* Call adapter stop to disable tx/rx and clear interrupts */
830 hw->mac.ops.stop_adapter(hw);
831
553b4497 832 /* PHY ops must be identified and initialized prior to reset */
04f165ef 833
553b4497
PW		 834 /* Init PHY and function pointers, perform SFP setup */
835 status = hw->phy.ops.init(hw);
04f165ef 836
553b4497
PW		 837 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
838 goto reset_hw_out;
04f165ef 839
553b4497
PW		 840 /* Setup SFP module if there is one present. */
841 if (hw->phy.sfp_setup_needed) {
842 status = hw->mac.ops.setup_sfp(hw);
843 hw->phy.sfp_setup_needed = false;
04f165ef 844 }
11afc1b1 845
553b4497
PW		 846 /* Reset PHY */
847 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
848 hw->phy.ops.reset(hw);
849
11afc1b1
PW		 850 /*
851 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
852 * access and verify no pending requests before reset
853 */
04f165ef
PW		 854 status = ixgbe_disable_pcie_master(hw);
855 if (status != 0) {
11afc1b1
PW		 856 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
857 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
858 }
859
860 /*
861 * Issue global reset to the MAC. This needs to be a SW reset.
862 * If link reset is used, it might reset the MAC when mng is using it
863 */
864 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
865 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
866 IXGBE_WRITE_FLUSH(hw);
867
868 /* Poll for reset bit to self-clear indicating reset is complete */
869 for (i = 0; i < 10; i++) {
870 udelay(1);
871 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
872 if (!(ctrl & IXGBE_CTRL_RST))
873 break;
874 }
875 if (ctrl & IXGBE_CTRL_RST) {
876 status = IXGBE_ERR_RESET_FAILED;
877 hw_dbg(hw, "Reset polling failed to complete.\n");
878 }
879 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
880 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
881 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
882 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
883
884 msleep(50);
885
886
887
888 /*
889 * Store the original AUTOC/AUTOC2 values if they have not been
890 * stored off yet. Otherwise restore the stored original
891 * values since the reset operation sets back to defaults.
892 */
893 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
894 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
895 if (hw->mac.orig_link_settings_stored == false) {
896 hw->mac.orig_autoc = autoc;
897 hw->mac.orig_autoc2 = autoc2;
898 hw->mac.orig_link_settings_stored = true;
4df10466 899 } else {
11afc1b1
PW		 900 if (autoc != hw->mac.orig_autoc)
901 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
902 IXGBE_AUTOC_AN_RESTART));
903
904 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
905 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
906 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
907 autoc2 |= (hw->mac.orig_autoc2 &
908 IXGBE_AUTOC2_UPPER_MASK);
909 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
910 }
911 }
912
aca6bee7
WJP		 913 /*
914 * Store MAC address from RAR0, clear receive address registers, and
915 * clear the multicast table. Also reset num_rar_entries to 128,
916 * since we modify this value when programming the SAN MAC address.
917 */
918 hw->mac.num_rar_entries = 128;
919 hw->mac.ops.init_rx_addrs(hw);
920
11afc1b1
PW		 921 /* Store the permanent mac address */
922 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
923
0365e6e4
PW		 924 /* Store the permanent SAN mac address */
925 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
926
aca6bee7
WJP		 927 /* Add the SAN MAC address to the RAR only if it's a valid address */
928 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
929 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
930 hw->mac.san_addr, 0, IXGBE_RAH_AV);
931
932 /* Reserve the last RAR for the SAN MAC address */
933 hw->mac.num_rar_entries--;
934 }
935
04f165ef 936reset_hw_out:
11afc1b1
PW		 937 return status;
938}
939
940/**
941 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
942 * @hw: pointer to hardware struct
943 * @rar: receive address register index to disassociate
944 * @vmdq: VMDq pool index to remove from the rar
945 **/
946s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
947{
948 u32 mpsar_lo, mpsar_hi;
949 u32 rar_entries = hw->mac.num_rar_entries;
950
951 if (rar < rar_entries) {
952 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
953 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
954
955 if (!mpsar_lo && !mpsar_hi)
956 goto done;
957
958 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
959 if (mpsar_lo) {
960 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
961 mpsar_lo = 0;
962 }
963 if (mpsar_hi) {
964 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
965 mpsar_hi = 0;
966 }
967 } else if (vmdq < 32) {
968 mpsar_lo &= ~(1 << vmdq);
969 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
970 } else {
971 mpsar_hi &= ~(1 << (vmdq - 32));
972 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
973 }
974
975 /* was that the last pool using this rar? */
976 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
977 hw->mac.ops.clear_rar(hw, rar);
978 } else {
979 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
980 }
981
982done:
983 return 0;
984}
985
986/**
987 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
988 * @hw: pointer to hardware struct
989 * @rar: receive address register index to associate with a VMDq index
990 * @vmdq: VMDq pool index
991 **/
992s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
993{
994 u32 mpsar;
995 u32 rar_entries = hw->mac.num_rar_entries;
996
997 if (rar < rar_entries) {
998 if (vmdq < 32) {
999 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1000 mpsar |= 1 << vmdq;
1001 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
1002 } else {
1003 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1004 mpsar |= 1 << (vmdq - 32);
1005 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
1006 }
1007 } else {
1008 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1009 }
1010 return 0;
1011}
1012
1013/**
1014 * ixgbe_set_vfta_82599 - Set VLAN filter table
1015 * @hw: pointer to hardware structure
1016 * @vlan: VLAN id to write to VLAN filter
1017 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1018 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1019 *
1020 * Turn on/off specified VLAN in the VLAN filter table.
1021 **/
1022s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1023 bool vlan_on)
1024{
1025 u32 regindex;
1026 u32 bitindex;
1027 u32 bits;
1028 u32 first_empty_slot;
1029
1030 if (vlan > 4095)
1031 return IXGBE_ERR_PARAM;
1032
1033 /*
1034 * this is a 2 part operation - first the VFTA, then the
1035 * VLVF and VLVFB if vind is set
1036 */
1037
1038 /* Part 1
1039 * The VFTA is a bitstring made up of 128 32-bit registers
1040 * that enable the particular VLAN id, much like the MTA:
1041 * bits[11-5]: which register
1042 * bits[4-0]: which bit in the register
1043 */
1044 regindex = (vlan >> 5) & 0x7F;
1045 bitindex = vlan & 0x1F;
1046 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1047 if (vlan_on)
1048 bits |= (1 << bitindex);
1049 else
1050 bits &= ~(1 << bitindex);
1051 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1052
1053
1054 /* Part 2
1055 * If the vind is set
1056 * Either vlan_on
1057 * make sure the vlan is in VLVF
1058 * set the vind bit in the matching VLVFB
1059 * Or !vlan_on
1060 * clear the pool bit and possibly the vind
1061 */
1062 if (vind) {
1063 /* find the vlanid or the first empty slot */
1064 first_empty_slot = 0;
1065
1066 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
1067 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
1068 if (!bits && !first_empty_slot)
1069 first_empty_slot = regindex;
1070 else if ((bits & 0x0FFF) == vlan)
1071 break;
1072 }
1073
1074 if (regindex >= IXGBE_VLVF_ENTRIES) {
1075 if (first_empty_slot)
1076 regindex = first_empty_slot;
1077 else {
1078 hw_dbg(hw, "No space in VLVF.\n");
1079 goto out;
1080 }
1081 }
1082
1083 if (vlan_on) {
1084 /* set the pool bit */
1085 if (vind < 32) {
1086 bits = IXGBE_READ_REG(hw,
1087 IXGBE_VLVFB(regindex * 2));
1088 bits |= (1 << vind);
1089 IXGBE_WRITE_REG(hw,
1090 IXGBE_VLVFB(regindex * 2), bits);
1091 } else {
1092 bits = IXGBE_READ_REG(hw,
1093 IXGBE_VLVFB((regindex * 2) + 1));
1094 bits |= (1 << vind);
1095 IXGBE_WRITE_REG(hw,
1096 IXGBE_VLVFB((regindex * 2) + 1), bits);
1097 }
1098 } else {
1099 /* clear the pool bit */
1100 if (vind < 32) {
1101 bits = IXGBE_READ_REG(hw,
1102 IXGBE_VLVFB(regindex * 2));
1103 bits &= ~(1 << vind);
1104 IXGBE_WRITE_REG(hw,
1105 IXGBE_VLVFB(regindex * 2), bits);
1106 bits |= IXGBE_READ_REG(hw,
1107 IXGBE_VLVFB((regindex * 2) + 1));
1108 } else {
1109 bits = IXGBE_READ_REG(hw,
1110 IXGBE_VLVFB((regindex * 2) + 1));
1111 bits &= ~(1 << vind);
1112 IXGBE_WRITE_REG(hw,
1113 IXGBE_VLVFB((regindex * 2) + 1), bits);
1114 bits |= IXGBE_READ_REG(hw,
1115 IXGBE_VLVFB(regindex * 2));
1116 }
1117 }
1118
1119 if (bits)
1120 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
1121 (IXGBE_VLVF_VIEN | vlan));
1122 else
1123 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
1124 }
1125
1126out:
1127 return 0;
1128}
1129
1130/**
1131 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1132 * @hw: pointer to hardware structure
1133 *
1134 * Clears the VLAN filer table, and the VMDq index associated with the filter
1135 **/
1136s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
1137{
1138 u32 offset;
1139
1140 for (offset = 0; offset < hw->mac.vft_size; offset++)
1141 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1142
1143 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1144 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1145 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1146 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1147 }
1148
1149 return 0;
1150}
1151
11afc1b1
PW		 1152/**
1153 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1154 * @hw: pointer to hardware structure
1155 **/
1156s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1157{
1158 int i;
1159 hw_dbg(hw, " Clearing UTA\n");
1160
1161 for (i = 0; i < 128; i++)
1162 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1163
1164 return 0;
1165}
1166
1167/**
1168 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1169 * @hw: pointer to hardware structure
1170 * @reg: analog register to read
1171 * @val: read value
1172 *
1173 * Performs read operation to Omer analog register specified.
1174 **/
1175s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1176{
1177 u32 core_ctl;
1178
1179 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1180 (reg << 8));
1181 IXGBE_WRITE_FLUSH(hw);
1182 udelay(10);
1183 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1184 *val = (u8)core_ctl;
1185
1186 return 0;
1187}
1188
1189/**
1190 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1191 * @hw: pointer to hardware structure
1192 * @reg: atlas register to write
1193 * @val: value to write
1194 *
1195 * Performs write operation to Omer analog register specified.
1196 **/
1197s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1198{
1199 u32 core_ctl;
1200
1201 core_ctl = (reg << 8) | val;
1202 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1203 IXGBE_WRITE_FLUSH(hw);
1204 udelay(10);
1205
1206 return 0;
1207}
1208
1209/**
1210 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1211 * @hw: pointer to hardware structure
1212 *
1213 * Starts the hardware using the generic start_hw function.
1214 * Then performs device-specific:
1215 * Clears the rate limiter registers.
1216 **/
1217s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1218{
1219 u32 q_num;
1220
1221 ixgbe_start_hw_generic(hw);
1222
1223 /* Clear the rate limiters */
1224 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1225 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1226 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1227 }
1228 IXGBE_WRITE_FLUSH(hw);
1229
50ac58ba
PWJ		 1230 /* We need to run link autotry after the driver loads */
1231 hw->mac.autotry_restart = true;
1232
11afc1b1
PW		 1233 return 0;
1234}
1235
1236/**
1237 * ixgbe_identify_phy_82599 - Get physical layer module
1238 * @hw: pointer to hardware structure
1239 *
1240 * Determines the physical layer module found on the current adapter.
1241 **/
1242s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1243{
1244 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1245 status = ixgbe_identify_phy_generic(hw);
1246 if (status != 0)
1247 status = ixgbe_identify_sfp_module_generic(hw);
1248 return status;
1249}
1250
1251/**
1252 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1253 * @hw: pointer to hardware structure
1254 *
1255 * Determines physical layer capabilities of the current configuration.
1256 **/
1257u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1258{
1259 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 1260 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1261 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1262 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1263 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1264 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1265 u16 ext_ability = 0;
1339b9e9 1266 u8 comp_codes_10g = 0;
11afc1b1 1267
04193058
PWJ		 1268 hw->phy.ops.identify(hw);
1269
1270 if (hw->phy.type == ixgbe_phy_tn ||
1271 hw->phy.type == ixgbe_phy_cu_unknown) {
6b73e10d
BH		 1272 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1273 &ext_ability);
1274 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 1275 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 1276 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 1277 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 1278 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 1279 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1280 goto out;
1281 }
1282
1283 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1284 case IXGBE_AUTOC_LMS_1G_AN:
1285 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1286 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1287 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1288 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1289 goto out;
1290 } else
1291 /* SFI mode so read SFP module */
1292 goto sfp_check;
11afc1b1 1293 break;
04193058
PWJ		 1294 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1295 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1296 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1297 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1298 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 1299 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1300 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 1301 goto out;
1302 break;
1303 case IXGBE_AUTOC_LMS_10G_SERIAL:
1304 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1305 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1306 goto out;
1307 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1308 goto sfp_check;
1309 break;
1310 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1311 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1312 if (autoc & IXGBE_AUTOC_KX_SUPP)
1313 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1314 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1315 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1316 if (autoc & IXGBE_AUTOC_KR_SUPP)
1317 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1318 goto out;
1319 break;
1320 default:
1321 goto out;
1322 break;
1323 }
11afc1b1 1324
04193058
PWJ		 1325sfp_check:
1326 /* SFP check must be done last since DA modules are sometimes used to
1327 * test KR mode - we need to id KR mode correctly before SFP module.
1328 * Call identify_sfp because the pluggable module may have changed */
1329 hw->phy.ops.identify_sfp(hw);
1330 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1331 goto out;
1332
1333 switch (hw->phy.type) {
1334 case ixgbe_phy_tw_tyco:
1335 case ixgbe_phy_tw_unknown:
1336 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1337 break;
1338 case ixgbe_phy_sfp_avago:
1339 case ixgbe_phy_sfp_ftl:
1340 case ixgbe_phy_sfp_intel:
1341 case ixgbe_phy_sfp_unknown:
1342 hw->phy.ops.read_i2c_eeprom(hw,
1343 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1344 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 1345 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 1346 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 1347 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
11afc1b1
PW		 1348 break;
1349 default:
11afc1b1
PW		 1350 break;
1351 }
1352
04193058 1353out:
11afc1b1
PW		 1354 return physical_layer;
1355}
1356
1357/**
1358 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1359 * @hw: pointer to hardware structure
1360 * @regval: register value to write to RXCTRL
1361 *
1362 * Enables the Rx DMA unit for 82599
1363 **/
1364s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1365{
1366#define IXGBE_MAX_SECRX_POLL 30
1367 int i;
1368 int secrxreg;
1369
1370 /*
1371 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1372 * If traffic is incoming before we enable the Rx unit, it could hang
1373 * the Rx DMA unit. Therefore, make sure the security engine is
1374 * completely disabled prior to enabling the Rx unit.
1375 */
1376 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1377 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1378 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1379 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1380 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1381 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1382 break;
1383 else
1384 udelay(10);
1385 }
1386
1387 /* For informational purposes only */
1388 if (i >= IXGBE_MAX_SECRX_POLL)
1389 hw_dbg(hw, "Rx unit being enabled before security "
1390 "path fully disabled. Continuing with init.\n");
1391
1392 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1393 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1394 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1395 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1396 IXGBE_WRITE_FLUSH(hw);
1397
1398 return 0;
1399}
1400
04193058
PWJ		 1401/**
1402 * ixgbe_get_device_caps_82599 - Get additional device capabilities
1403 * @hw: pointer to hardware structure
1404 * @device_caps: the EEPROM word with the extra device capabilities
1405 *
1406 * This function will read the EEPROM location for the device capabilities,
1407 * and return the word through device_caps.
1408 **/
1409s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
1410{
1411 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
1412
1413 return 0;
1414}
1415
0365e6e4
PW		 1416/**
1417 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
1418 * @hw: pointer to hardware structure
1419 * @san_mac_offset: SAN MAC address offset
1420 *
1421 * This function will read the EEPROM location for the SAN MAC address
1422 * pointer, and returns the value at that location. This is used in both
1423 * get and set mac_addr routines.
1424 **/
1425s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
1426 u16 *san_mac_offset)
1427{
1428 /*
1429 * First read the EEPROM pointer to see if the MAC addresses are
1430 * available.
1431 */
1432 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
1433
1434 return 0;
1435}
1436
1437/**
1438 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
1439 * @hw: pointer to hardware structure
1440 * @san_mac_addr: SAN MAC address
1441 *
1442 * Reads the SAN MAC address from the EEPROM, if it's available. This is
1443 * per-port, so set_lan_id() must be called before reading the addresses.
1444 * set_lan_id() is called by identify_sfp(), but this cannot be relied
1445 * upon for non-SFP connections, so we must call it here.
1446 **/
1447s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
1448{
1449 u16 san_mac_data, san_mac_offset;
1450 u8 i;
1451
1452 /*
1453 * First read the EEPROM pointer to see if the MAC addresses are
1454 * available. If they're not, no point in calling set_lan_id() here.
1455 */
1456 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
1457
1458 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
1459 /*
1460 * No addresses available in this EEPROM. It's not an
1461 * error though, so just wipe the local address and return.
1462 */
1463 for (i = 0; i < 6; i++)
1464 san_mac_addr[i] = 0xFF;
1465
1466 goto san_mac_addr_out;
1467 }
1468
1469 /* make sure we know which port we need to program */
1470 hw->mac.ops.set_lan_id(hw);
1471 /* apply the port offset to the address offset */
1472 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1473 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1474 for (i = 0; i < 3; i++) {
1475 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
1476 san_mac_addr[i * 2] = (u8)(san_mac_data);
1477 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
1478 san_mac_offset++;
1479 }
1480
1481san_mac_addr_out:
1482 return 0;
1483}
1484
11afc1b1
PW		 1485static struct ixgbe_mac_operations mac_ops_82599 = {
1486 .init_hw = &ixgbe_init_hw_generic,
1487 .reset_hw = &ixgbe_reset_hw_82599,
1488 .start_hw = &ixgbe_start_hw_82599,
1489 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1490 .get_media_type = &ixgbe_get_media_type_82599,
1491 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
1492 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
1493 .get_mac_addr = &ixgbe_get_mac_addr_generic,
0365e6e4 1494 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
04193058 1495 .get_device_caps = &ixgbe_get_device_caps_82599,
11afc1b1
PW		 1496 .stop_adapter = &ixgbe_stop_adapter_generic,
1497 .get_bus_info = &ixgbe_get_bus_info_generic,
1498 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
1499 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
1500 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
1501 .setup_link = &ixgbe_setup_mac_link_82599,
1502 .setup_link_speed = &ixgbe_setup_mac_link_speed_82599,
1503 .check_link = &ixgbe_check_mac_link_82599,
1504 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
1505 .led_on = &ixgbe_led_on_generic,
1506 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 1507 .blink_led_start = &ixgbe_blink_led_start_generic,
1508 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 1509 .set_rar = &ixgbe_set_rar_generic,
1510 .clear_rar = &ixgbe_clear_rar_generic,
1511 .set_vmdq = &ixgbe_set_vmdq_82599,
1512 .clear_vmdq = &ixgbe_clear_vmdq_82599,
1513 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1514 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1515 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1516 .enable_mc = &ixgbe_enable_mc_generic,
1517 .disable_mc = &ixgbe_disable_mc_generic,
1518 .clear_vfta = &ixgbe_clear_vfta_82599,
1519 .set_vfta = &ixgbe_set_vfta_82599,
620fa036 1520 .fc_enable = &ixgbe_fc_enable_generic,
11afc1b1
PW		 1521 .init_uta_tables = &ixgbe_init_uta_tables_82599,
1522 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
1523};
1524
1525static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
1526 .init_params = &ixgbe_init_eeprom_params_generic,
1527 .read = &ixgbe_read_eeprom_generic,
1528 .write = &ixgbe_write_eeprom_generic,
1529 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1530 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1531};
1532
1533static struct ixgbe_phy_operations phy_ops_82599 = {
1534 .identify = &ixgbe_identify_phy_82599,
1535 .identify_sfp = &ixgbe_identify_sfp_module_generic,
04f165ef 1536 .init = &ixgbe_init_phy_ops_82599,
11afc1b1
PW		 1537 .reset = &ixgbe_reset_phy_generic,
1538 .read_reg = &ixgbe_read_phy_reg_generic,
1539 .write_reg = &ixgbe_write_phy_reg_generic,
1540 .setup_link = &ixgbe_setup_phy_link_generic,
1541 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1542 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
1543 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
1544 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
1545 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
1546};
1547
1548struct ixgbe_info ixgbe_82599_info = {
1549 .mac = ixgbe_mac_82599EB,
1550 .get_invariants = &ixgbe_get_invariants_82599,
1551 .mac_ops = &mac_ops_82599,
1552 .eeprom_ops = &eeprom_ops_82599,
1553 .phy_ops = &phy_ops_82599,
1554};
Clone of davem's net-next-2.6 tree