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ixgbe: Fix TX stats accounting
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
34
35#define IXGBE_82599_MAX_TX_QUEUES 128
36#define IXGBE_82599_MAX_RX_QUEUES 128
37#define IXGBE_82599_RAR_ENTRIES 128
38#define IXGBE_82599_MC_TBL_SIZE 128
39#define IXGBE_82599_VFT_TBL_SIZE 128
40
8620a103
MC		 41s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
42 ixgbe_link_speed speed,
43 bool autoneg,
44 bool autoneg_wait_to_complete);
cd7e1f0b
DS		 45static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
8620a103
MC		 49s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
50 bool autoneg_wait_to_complete);
51s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
52 ixgbe_link_speed speed,
53 bool autoneg,
54 bool autoneg_wait_to_complete);
11afc1b1
PW		 55static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed *speed,
57 bool *autoneg);
8620a103
MC		 58static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
59 ixgbe_link_speed speed,
60 bool autoneg,
61 bool autoneg_wait_to_complete);
794caeb2 62static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
11afc1b1 63
7b25cdba 64static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 65{
66 struct ixgbe_mac_info *mac = &hw->mac;
67 if (hw->phy.multispeed_fiber) {
68 /* Set up dual speed SFP+ support */
8620a103 69 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
11afc1b1 70 } else {
cd7e1f0b
DS		 71 if ((mac->ops.get_media_type(hw) ==
72 ixgbe_media_type_backplane) &&
73 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
74 hw->phy.smart_speed == ixgbe_smart_speed_on))
75 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
76 else
77 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
11afc1b1
PW		 78 }
79}
80
7b25cdba 81static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 82{
83 s32 ret_val = 0;
84 u16 list_offset, data_offset, data_value;
85
86 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
87 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 88
89 hw->phy.ops.reset = NULL;
90
11afc1b1
PW		 91 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
92 &data_offset);
93
94 if (ret_val != 0)
95 goto setup_sfp_out;
96
aa5aec88
PWJ		 97 /* PHY config will finish before releasing the semaphore */
98 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
99 if (ret_val != 0) {
100 ret_val = IXGBE_ERR_SWFW_SYNC;
101 goto setup_sfp_out;
102 }
103
11afc1b1
PW		 104 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
105 while (data_value != 0xffff) {
106 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
107 IXGBE_WRITE_FLUSH(hw);
108 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
109 }
1479ad4f
PWJ		 110 /* Now restart DSP by setting Restart_AN */
111 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
112 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
aa5aec88
PWJ		 113
114 /* Release the semaphore */
115 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
116 /* Delay obtaining semaphore again to allow FW access */
117 msleep(hw->eeprom.semaphore_delay);
11afc1b1
PW		 118 }
119
120setup_sfp_out:
121 return ret_val;
122}
123
124/**
125 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
126 * @hw: pointer to hardware structure
127 *
128 * Read PCIe configuration space, and get the MSI-X vector count from
129 * the capabilities table.
130 **/
7b25cdba 131static u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 132{
133 struct ixgbe_adapter *adapter = hw->back;
134 u16 msix_count;
135 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
136 &msix_count);
137 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
138
139 /* MSI-X count is zero-based in HW, so increment to give proper value */
140 msix_count++;
141
142 return msix_count;
143}
144
145static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
146{
147 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 148
04f165ef 149 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 150
04f165ef
PW		 151 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
152 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
153 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
154 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
155 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
156 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
11afc1b1 157
04f165ef
PW		 158 return 0;
159}
11afc1b1 160
04f165ef
PW		 161/**
162 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
163 * @hw: pointer to hardware structure
164 *
165 * Initialize any function pointers that were not able to be
166 * set during get_invariants because the PHY/SFP type was
167 * not known. Perform the SFP init if necessary.
168 *
169 **/
7b25cdba 170static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
04f165ef
PW		 171{
172 struct ixgbe_mac_info *mac = &hw->mac;
173 struct ixgbe_phy_info *phy = &hw->phy;
174 s32 ret_val = 0;
11afc1b1 175
04f165ef
PW		 176 /* Identify the PHY or SFP module */
177 ret_val = phy->ops.identify(hw);
178
179 /* Setup function pointers based on detected SFP module and speeds */
180 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 181
182 /* If copper media, overwrite with copper function pointers */
183 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
184 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
11afc1b1
PW		 185 mac->ops.get_link_capabilities =
186 &ixgbe_get_copper_link_capabilities_82599;
187 }
188
04f165ef 189 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 190 switch (hw->phy.type) {
191 case ixgbe_phy_tn:
192 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
193 phy->ops.get_firmware_version =
04f165ef 194 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1
PW		 195 break;
196 default:
197 break;
198 }
199
11afc1b1
PW		 200 return ret_val;
201}
202
203/**
204 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
205 * @hw: pointer to hardware structure
206 * @speed: pointer to link speed
207 * @negotiation: true when autoneg or autotry is enabled
208 *
209 * Determines the link capabilities by reading the AUTOC register.
210 **/
7b25cdba
DS		 211static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
212 ixgbe_link_speed *speed,
213 bool *negotiation)
11afc1b1
PW		 214{
215 s32 status = 0;
1eb99d5a 216 u32 autoc = 0;
11afc1b1 217
1eb99d5a
PW		 218 /*
219 * Determine link capabilities based on the stored value of AUTOC,
220 * which represents EEPROM defaults. If AUTOC value has not been
221 * stored, use the current register value.
222 */
223 if (hw->mac.orig_link_settings_stored)
224 autoc = hw->mac.orig_autoc;
225 else
226 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
227
228 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 229 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
230 *speed = IXGBE_LINK_SPEED_1GB_FULL;
231 *negotiation = false;
232 break;
233
234 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
235 *speed = IXGBE_LINK_SPEED_10GB_FULL;
236 *negotiation = false;
237 break;
238
239 case IXGBE_AUTOC_LMS_1G_AN:
240 *speed = IXGBE_LINK_SPEED_1GB_FULL;
241 *negotiation = true;
242 break;
243
244 case IXGBE_AUTOC_LMS_10G_SERIAL:
245 *speed = IXGBE_LINK_SPEED_10GB_FULL;
246 *negotiation = false;
247 break;
248
249 case IXGBE_AUTOC_LMS_KX4_KX_KR:
250 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
251 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 252 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 253 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 254 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 255 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 256 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 257 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
258 *negotiation = true;
259 break;
260
261 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
262 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 263 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 264 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 265 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 266 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 267 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 268 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
269 *negotiation = true;
270 break;
271
272 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
273 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
274 *negotiation = false;
275 break;
276
277 default:
278 status = IXGBE_ERR_LINK_SETUP;
279 goto out;
280 break;
281 }
282
283 if (hw->phy.multispeed_fiber) {
284 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
285 IXGBE_LINK_SPEED_1GB_FULL;
286 *negotiation = true;
287 }
288
289out:
290 return status;
291}
292
293/**
294 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
295 * @hw: pointer to hardware structure
296 * @speed: pointer to link speed
297 * @autoneg: boolean auto-negotiation value
298 *
299 * Determines the link capabilities by reading the AUTOC register.
300 **/
301static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
302 ixgbe_link_speed *speed,
303 bool *autoneg)
304{
305 s32 status = IXGBE_ERR_LINK_SETUP;
306 u16 speed_ability;
307
308 *speed = 0;
309 *autoneg = true;
310
6b73e10d 311 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
11afc1b1
PW		 312 &speed_ability);
313
314 if (status == 0) {
6b73e10d 315 if (speed_ability & MDIO_SPEED_10G)
11afc1b1 316 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
6b73e10d 317 if (speed_ability & MDIO_PMA_SPEED_1000)
11afc1b1
PW		 318 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
319 }
320
321 return status;
322}
323
324/**
325 * ixgbe_get_media_type_82599 - Get media type
326 * @hw: pointer to hardware structure
327 *
328 * Returns the media type (fiber, copper, backplane)
329 **/
7b25cdba 330static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 331{
332 enum ixgbe_media_type media_type;
333
334 /* Detect if there is a copper PHY attached. */
335 if (hw->phy.type == ixgbe_phy_cu_unknown ||
336 hw->phy.type == ixgbe_phy_tn) {
337 media_type = ixgbe_media_type_copper;
338 goto out;
339 }
340
341 switch (hw->device_id) {
11afc1b1 342 case IXGBE_DEV_ID_82599_KX4:
dbfec662 343 case IXGBE_DEV_ID_82599_KX4_MEZZ:
312eb931 344 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
1fcf03e6 345 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 346 /* Default device ID is mezzanine card KX/KX4 */
347 media_type = ixgbe_media_type_backplane;
348 break;
349 case IXGBE_DEV_ID_82599_SFP:
38ad1c8e 350 case IXGBE_DEV_ID_82599_SFP_EM:
11afc1b1
PW		 351 media_type = ixgbe_media_type_fiber;
352 break;
8911184f 353 case IXGBE_DEV_ID_82599_CX4:
6b1be199 354 media_type = ixgbe_media_type_cx4;
8911184f 355 break;
11afc1b1
PW		 356 default:
357 media_type = ixgbe_media_type_unknown;
358 break;
359 }
360out:
361 return media_type;
362}
363
364/**
8620a103 365 * ixgbe_start_mac_link_82599 - Setup MAC link settings
11afc1b1 366 * @hw: pointer to hardware structure
8620a103 367 * @autoneg_wait_to_complete: true when waiting for completion is needed
11afc1b1
PW		 368 *
369 * Configures link settings based on values in the ixgbe_hw struct.
370 * Restarts the link. Performs autonegotiation if needed.
371 **/
8620a103
MC		 372s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
373 bool autoneg_wait_to_complete)
11afc1b1
PW		 374{
375 u32 autoc_reg;
376 u32 links_reg;
377 u32 i;
378 s32 status = 0;
379
380 /* Restart link */
381 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
382 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
383 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
384
385 /* Only poll for autoneg to complete if specified to do so */
8620a103 386 if (autoneg_wait_to_complete) {
11afc1b1
PW		 387 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
388 IXGBE_AUTOC_LMS_KX4_KX_KR ||
389 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
390 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
391 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
392 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
393 links_reg = 0; /* Just in case Autoneg time = 0 */
394 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
395 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
396 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
397 break;
398 msleep(100);
399 }
400 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
401 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
402 hw_dbg(hw, "Autoneg did not complete.\n");
403 }
404 }
405 }
406
11afc1b1
PW		 407 /* Add delay to filter out noises during initial link setup */
408 msleep(50);
409
410 return status;
411}
412
413/**
8620a103 414 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
11afc1b1
PW		 415 * @hw: pointer to hardware structure
416 * @speed: new link speed
417 * @autoneg: true if autonegotiation enabled
418 * @autoneg_wait_to_complete: true when waiting for completion is needed
419 *
420 * Set the link speed in the AUTOC register and restarts link.
421 **/
8620a103
MC		 422s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
423 ixgbe_link_speed speed,
424 bool autoneg,
425 bool autoneg_wait_to_complete)
11afc1b1
PW		 426{
427 s32 status = 0;
428 ixgbe_link_speed phy_link_speed;
429 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
430 u32 speedcnt = 0;
431 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
432 bool link_up = false;
433 bool negotiation;
50ac58ba 434 int i;
11afc1b1
PW		 435
436 /* Mask off requested but non-supported speeds */
437 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
438 speed &= phy_link_speed;
439
50ac58ba
PWJ		 440 /*
441 * When the driver changes the link speeds that it can support,
442 * it sets autotry_restart to true to indicate that we need to
443 * initiate a new autotry session with the link partner. To do
444 * so, we set the speed then disable and re-enable the tx laser, to
445 * alert the link partner that it also needs to restart autotry on its
446 * end. This is consistent with true clause 37 autoneg, which also
447 * involves a loss of signal.
448 */
449
11afc1b1
PW		 450 /*
451 * Try each speed one by one, highest priority first. We do this in
452 * software because 10gb fiber doesn't support speed autonegotiation.
453 */
454 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
455 speedcnt++;
456 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
457
50ac58ba
PWJ		 458 /* If we already have link at this speed, just jump out */
459 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
460
461 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
462 goto out;
463
464 /* Set the module link speed */
11afc1b1
PW		 465 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
466 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
467
50ac58ba
PWJ		 468 /* Allow module to change analog characteristics (1G->10G) */
469 msleep(40);
11afc1b1 470
8620a103
MC		 471 status = ixgbe_setup_mac_link_82599(hw,
472 IXGBE_LINK_SPEED_10GB_FULL,
473 autoneg,
474 autoneg_wait_to_complete);
50ac58ba 475 if (status != 0)
c3c74327 476 return status;
50ac58ba
PWJ		 477
478 /* Flap the tx laser if it has not already been done */
479 if (hw->mac.autotry_restart) {
480 /* Disable tx laser; allow 100us to go dark per spec */
481 esdp_reg |= IXGBE_ESDP_SDP3;
482 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
483 udelay(100);
484
485 /* Enable tx laser; allow 2ms to light up per spec */
486 esdp_reg &= ~IXGBE_ESDP_SDP3;
487 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
488 msleep(2);
489
490 hw->mac.autotry_restart = false;
491 }
492
cd7e1f0b
DS		 493 /*
494 * Wait for the controller to acquire link. Per IEEE 802.3ap,
495 * Section 73.10.2, we may have to wait up to 500ms if KR is
496 * attempted. 82599 uses the same timing for 10g SFI.
497 */
498
50ac58ba
PWJ		 499 for (i = 0; i < 5; i++) {
500 /* Wait for the link partner to also set speed */
501 msleep(100);
502
503 /* If we have link, just jump out */
504 hw->mac.ops.check_link(hw, &phy_link_speed,
505 &link_up, false);
506 if (link_up)
507 goto out;
508 }
11afc1b1
PW		 509 }
510
511 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
512 speedcnt++;
513 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
514 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
515
50ac58ba
PWJ		 516 /* If we already have link at this speed, just jump out */
517 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
518
519 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
520 goto out;
521
522 /* Set the module link speed */
11afc1b1
PW		 523 esdp_reg &= ~IXGBE_ESDP_SDP5;
524 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
525 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
526
50ac58ba
PWJ		 527 /* Allow module to change analog characteristics (10G->1G) */
528 msleep(40);
11afc1b1 529
8620a103 530 status = ixgbe_setup_mac_link_82599(hw,
50ac58ba
PWJ		 531 IXGBE_LINK_SPEED_1GB_FULL,
532 autoneg,
533 autoneg_wait_to_complete);
534 if (status != 0)
c3c74327 535 return status;
50ac58ba
PWJ		 536
537 /* Flap the tx laser if it has not already been done */
538 if (hw->mac.autotry_restart) {
539 /* Disable tx laser; allow 100us to go dark per spec */
540 esdp_reg |= IXGBE_ESDP_SDP3;
541 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
542 udelay(100);
543
544 /* Enable tx laser; allow 2ms to light up per spec */
545 esdp_reg &= ~IXGBE_ESDP_SDP3;
546 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
547 msleep(2);
548
549 hw->mac.autotry_restart = false;
550 }
551
552 /* Wait for the link partner to also set speed */
553 msleep(100);
11afc1b1
PW		 554
555 /* If we have link, just jump out */
556 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
557 if (link_up)
558 goto out;
559 }
560
561 /*
562 * We didn't get link. Configure back to the highest speed we tried,
563 * (if there was more than one). We call ourselves back with just the
564 * single highest speed that the user requested.
565 */
566 if (speedcnt > 1)
8620a103
MC		 567 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
568 highest_link_speed,
569 autoneg,
570 autoneg_wait_to_complete);
11afc1b1
PW		 571
572out:
c3c74327
MC		 573 /* Set autoneg_advertised value based on input link speed */
574 hw->phy.autoneg_advertised = 0;
575
576 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
577 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
578
579 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
580 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
581
11afc1b1
PW		 582 return status;
583}
584
cd7e1f0b
DS		 585/**
586 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
587 * @hw: pointer to hardware structure
588 * @speed: new link speed
589 * @autoneg: true if autonegotiation enabled
590 * @autoneg_wait_to_complete: true when waiting for completion is needed
591 *
592 * Implements the Intel SmartSpeed algorithm.
593 **/
594static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
595 ixgbe_link_speed speed, bool autoneg,
596 bool autoneg_wait_to_complete)
597{
598 s32 status = 0;
599 ixgbe_link_speed link_speed;
600 s32 i, j;
601 bool link_up = false;
602 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
603
604 hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n");
605
606 /* Set autoneg_advertised value based on input link speed */
607 hw->phy.autoneg_advertised = 0;
608
609 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
610 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
611
612 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
613 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
614
615 if (speed & IXGBE_LINK_SPEED_100_FULL)
616 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
617
618 /*
619 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
620 * autoneg advertisement if link is unable to be established at the
621 * highest negotiated rate. This can sometimes happen due to integrity
622 * issues with the physical media connection.
623 */
624
625 /* First, try to get link with full advertisement */
626 hw->phy.smart_speed_active = false;
627 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
628 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
629 autoneg_wait_to_complete);
630 if (status)
631 goto out;
632
633 /*
634 * Wait for the controller to acquire link. Per IEEE 802.3ap,
635 * Section 73.10.2, we may have to wait up to 500ms if KR is
636 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
637 * Table 9 in the AN MAS.
638 */
639 for (i = 0; i < 5; i++) {
640 mdelay(100);
641
642 /* If we have link, just jump out */
643 hw->mac.ops.check_link(hw, &link_speed,
644 &link_up, false);
645 if (link_up)
646 goto out;
647 }
648 }
649
650 /*
651 * We didn't get link. If we advertised KR plus one of KX4/KX
652 * (or BX4/BX), then disable KR and try again.
653 */
654 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
655 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
656 goto out;
657
658 /* Turn SmartSpeed on to disable KR support */
659 hw->phy.smart_speed_active = true;
660 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
661 autoneg_wait_to_complete);
662 if (status)
663 goto out;
664
665 /*
666 * Wait for the controller to acquire link. 600ms will allow for
667 * the AN link_fail_inhibit_timer as well for multiple cycles of
668 * parallel detect, both 10g and 1g. This allows for the maximum
669 * connect attempts as defined in the AN MAS table 73-7.
670 */
671 for (i = 0; i < 6; i++) {
672 mdelay(100);
673
674 /* If we have link, just jump out */
675 hw->mac.ops.check_link(hw, &link_speed,
676 &link_up, false);
677 if (link_up)
678 goto out;
679 }
680
681 /* We didn't get link. Turn SmartSpeed back off. */
682 hw->phy.smart_speed_active = false;
683 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
684 autoneg_wait_to_complete);
685
686out:
687 return status;
688}
689
11afc1b1
PW		 690/**
691 * ixgbe_check_mac_link_82599 - Determine link and speed status
692 * @hw: pointer to hardware structure
693 * @speed: pointer to link speed
694 * @link_up: true when link is up
695 * @link_up_wait_to_complete: bool used to wait for link up or not
696 *
697 * Reads the links register to determine if link is up and the current speed
698 **/
7b25cdba
DS		 699static s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
700 ixgbe_link_speed *speed,
701 bool *link_up,
702 bool link_up_wait_to_complete)
11afc1b1
PW		 703{
704 u32 links_reg;
705 u32 i;
706
707 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
708 if (link_up_wait_to_complete) {
709 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
710 if (links_reg & IXGBE_LINKS_UP) {
711 *link_up = true;
712 break;
713 } else {
714 *link_up = false;
715 }
716 msleep(100);
717 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
718 }
719 } else {
720 if (links_reg & IXGBE_LINKS_UP)
721 *link_up = true;
722 else
723 *link_up = false;
724 }
725
726 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
727 IXGBE_LINKS_SPEED_10G_82599)
728 *speed = IXGBE_LINK_SPEED_10GB_FULL;
729 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
730 IXGBE_LINKS_SPEED_1G_82599)
731 *speed = IXGBE_LINK_SPEED_1GB_FULL;
732 else
733 *speed = IXGBE_LINK_SPEED_100_FULL;
734
620fa036
MC		 735 /* if link is down, zero out the current_mode */
736 if (*link_up == false) {
737 hw->fc.current_mode = ixgbe_fc_none;
738 hw->fc.fc_was_autonegged = false;
739 }
11afc1b1
PW		 740
741 return 0;
742}
743
744/**
8620a103 745 * ixgbe_setup_mac_link_82599 - Set MAC link speed
11afc1b1
PW		 746 * @hw: pointer to hardware structure
747 * @speed: new link speed
748 * @autoneg: true if autonegotiation enabled
749 * @autoneg_wait_to_complete: true when waiting for completion is needed
750 *
751 * Set the link speed in the AUTOC register and restarts link.
752 **/
8620a103
MC		 753s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
754 ixgbe_link_speed speed, bool autoneg,
755 bool autoneg_wait_to_complete)
11afc1b1
PW		 756{
757 s32 status = 0;
758 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
759 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
50ac58ba 760 u32 start_autoc = autoc;
1eb99d5a 761 u32 orig_autoc = 0;
11afc1b1
PW		 762 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
763 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
764 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
765 u32 links_reg;
766 u32 i;
767 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
768
769 /* Check to see if speed passed in is supported. */
770 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
771 speed &= link_capabilities;
772
50ac58ba
PWJ		 773 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
774 status = IXGBE_ERR_LINK_SETUP;
775 goto out;
776 }
777
1eb99d5a
PW		 778 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
779 if (hw->mac.orig_link_settings_stored)
780 orig_autoc = hw->mac.orig_autoc;
781 else
782 orig_autoc = autoc;
783
784
50ac58ba
PWJ		 785 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
786 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
787 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
11afc1b1
PW		 788 /* Set KX4/KX/KR support according to speed requested */
789 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
790 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1eb99d5a 791 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 792 autoc |= IXGBE_AUTOC_KX4_SUPP;
cd7e1f0b
DS		 793 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
794 (hw->phy.smart_speed_active == false))
11afc1b1
PW		 795 autoc |= IXGBE_AUTOC_KR_SUPP;
796 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
797 autoc |= IXGBE_AUTOC_KX_SUPP;
798 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
799 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
800 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
801 /* Switch from 1G SFI to 10G SFI if requested */
802 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
803 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
804 autoc &= ~IXGBE_AUTOC_LMS_MASK;
805 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
806 }
807 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
808 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
809 /* Switch from 10G SFI to 1G SFI if requested */
810 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
811 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
812 autoc &= ~IXGBE_AUTOC_LMS_MASK;
813 if (autoneg)
814 autoc |= IXGBE_AUTOC_LMS_1G_AN;
815 else
816 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
817 }
818 }
819
50ac58ba 820 if (autoc != start_autoc) {
11afc1b1
PW		 821 /* Restart link */
822 autoc |= IXGBE_AUTOC_AN_RESTART;
823 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
824
825 /* Only poll for autoneg to complete if specified to do so */
826 if (autoneg_wait_to_complete) {
827 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
828 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
829 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
830 links_reg = 0; /*Just in case Autoneg time=0*/
831 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
832 links_reg =
833 IXGBE_READ_REG(hw, IXGBE_LINKS);
834 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
835 break;
836 msleep(100);
837 }
838 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
839 status =
840 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
841 hw_dbg(hw, "Autoneg did not "
842 "complete.\n");
843 }
844 }
845 }
846
11afc1b1
PW		 847 /* Add delay to filter out noises during initial link setup */
848 msleep(50);
849 }
850
50ac58ba 851out:
11afc1b1
PW		 852 return status;
853}
854
855/**
8620a103 856 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
11afc1b1
PW		 857 * @hw: pointer to hardware structure
858 * @speed: new link speed
859 * @autoneg: true if autonegotiation enabled
860 * @autoneg_wait_to_complete: true if waiting is needed to complete
861 *
862 * Restarts link on PHY and MAC based on settings passed in.
863 **/
8620a103
MC		 864static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
865 ixgbe_link_speed speed,
866 bool autoneg,
867 bool autoneg_wait_to_complete)
11afc1b1
PW		 868{
869 s32 status;
870
871 /* Setup the PHY according to input speed */
872 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
873 autoneg_wait_to_complete);
874 /* Set up MAC */
8620a103 875 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
11afc1b1
PW		 876
877 return status;
878}
879
880/**
881 * ixgbe_reset_hw_82599 - Perform hardware reset
882 * @hw: pointer to hardware structure
883 *
884 * Resets the hardware by resetting the transmit and receive units, masks
885 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
886 * reset.
887 **/
7b25cdba 888static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 889{
890 s32 status = 0;
891 u32 ctrl, ctrl_ext;
892 u32 i;
893 u32 autoc;
894 u32 autoc2;
895
896 /* Call adapter stop to disable tx/rx and clear interrupts */
897 hw->mac.ops.stop_adapter(hw);
898
553b4497 899 /* PHY ops must be identified and initialized prior to reset */
04f165ef 900
553b4497
PW		 901 /* Init PHY and function pointers, perform SFP setup */
902 status = hw->phy.ops.init(hw);
04f165ef 903
553b4497
PW		 904 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
905 goto reset_hw_out;
04f165ef 906
553b4497
PW		 907 /* Setup SFP module if there is one present. */
908 if (hw->phy.sfp_setup_needed) {
909 status = hw->mac.ops.setup_sfp(hw);
910 hw->phy.sfp_setup_needed = false;
04f165ef 911 }
11afc1b1 912
553b4497
PW		 913 /* Reset PHY */
914 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
915 hw->phy.ops.reset(hw);
916
11afc1b1
PW		 917 /*
918 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
919 * access and verify no pending requests before reset
920 */
04f165ef
PW		 921 status = ixgbe_disable_pcie_master(hw);
922 if (status != 0) {
11afc1b1
PW		 923 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
924 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
925 }
926
927 /*
928 * Issue global reset to the MAC. This needs to be a SW reset.
929 * If link reset is used, it might reset the MAC when mng is using it
930 */
931 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
932 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
933 IXGBE_WRITE_FLUSH(hw);
934
935 /* Poll for reset bit to self-clear indicating reset is complete */
936 for (i = 0; i < 10; i++) {
937 udelay(1);
938 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
939 if (!(ctrl & IXGBE_CTRL_RST))
940 break;
941 }
942 if (ctrl & IXGBE_CTRL_RST) {
943 status = IXGBE_ERR_RESET_FAILED;
944 hw_dbg(hw, "Reset polling failed to complete.\n");
945 }
946 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
947 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
948 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
949 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
950
951 msleep(50);
952
953
954
955 /*
956 * Store the original AUTOC/AUTOC2 values if they have not been
957 * stored off yet. Otherwise restore the stored original
958 * values since the reset operation sets back to defaults.
959 */
960 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
961 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
962 if (hw->mac.orig_link_settings_stored == false) {
963 hw->mac.orig_autoc = autoc;
964 hw->mac.orig_autoc2 = autoc2;
965 hw->mac.orig_link_settings_stored = true;
4df10466 966 } else {
11afc1b1
PW		 967 if (autoc != hw->mac.orig_autoc)
968 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
969 IXGBE_AUTOC_AN_RESTART));
970
971 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
972 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
973 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
974 autoc2 |= (hw->mac.orig_autoc2 &
975 IXGBE_AUTOC2_UPPER_MASK);
976 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
977 }
978 }
979
aca6bee7
WJP		 980 /*
981 * Store MAC address from RAR0, clear receive address registers, and
982 * clear the multicast table. Also reset num_rar_entries to 128,
983 * since we modify this value when programming the SAN MAC address.
984 */
985 hw->mac.num_rar_entries = 128;
986 hw->mac.ops.init_rx_addrs(hw);
987
11afc1b1
PW		 988 /* Store the permanent mac address */
989 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
990
0365e6e4
PW		 991 /* Store the permanent SAN mac address */
992 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
993
aca6bee7
WJP		 994 /* Add the SAN MAC address to the RAR only if it's a valid address */
995 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
996 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
997 hw->mac.san_addr, 0, IXGBE_RAH_AV);
998
999 /* Reserve the last RAR for the SAN MAC address */
1000 hw->mac.num_rar_entries--;
1001 }
1002
383ff34b
YZ		 1003 /* Store the alternative WWNN/WWPN prefix */
1004 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1005 &hw->mac.wwpn_prefix);
1006
04f165ef 1007reset_hw_out:
11afc1b1
PW		 1008 return status;
1009}
1010
1011/**
1012 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
1013 * @hw: pointer to hardware struct
1014 * @rar: receive address register index to disassociate
1015 * @vmdq: VMDq pool index to remove from the rar
1016 **/
7b25cdba 1017static s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
11afc1b1
PW		 1018{
1019 u32 mpsar_lo, mpsar_hi;
1020 u32 rar_entries = hw->mac.num_rar_entries;
1021
1022 if (rar < rar_entries) {
1023 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1024 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1025
1026 if (!mpsar_lo && !mpsar_hi)
1027 goto done;
1028
1029 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
1030 if (mpsar_lo) {
1031 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
1032 mpsar_lo = 0;
1033 }
1034 if (mpsar_hi) {
1035 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
1036 mpsar_hi = 0;
1037 }
1038 } else if (vmdq < 32) {
1039 mpsar_lo &= ~(1 << vmdq);
1040 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
1041 } else {
1042 mpsar_hi &= ~(1 << (vmdq - 32));
1043 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
1044 }
1045
1046 /* was that the last pool using this rar? */
1047 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
1048 hw->mac.ops.clear_rar(hw, rar);
1049 } else {
1050 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1051 }
1052
1053done:
1054 return 0;
1055}
1056
1057/**
1058 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
1059 * @hw: pointer to hardware struct
1060 * @rar: receive address register index to associate with a VMDq index
1061 * @vmdq: VMDq pool index
1062 **/
7b25cdba 1063static s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
11afc1b1
PW		 1064{
1065 u32 mpsar;
1066 u32 rar_entries = hw->mac.num_rar_entries;
1067
1068 if (rar < rar_entries) {
1069 if (vmdq < 32) {
1070 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1071 mpsar |= 1 << vmdq;
1072 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
1073 } else {
1074 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1075 mpsar |= 1 << (vmdq - 32);
1076 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
1077 }
1078 } else {
1079 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1080 }
1081 return 0;
1082}
1083
1084/**
1085 * ixgbe_set_vfta_82599 - Set VLAN filter table
1086 * @hw: pointer to hardware structure
1087 * @vlan: VLAN id to write to VLAN filter
1088 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1089 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1090 *
1091 * Turn on/off specified VLAN in the VLAN filter table.
1092 **/
7b25cdba
DS		 1093static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1094 bool vlan_on)
11afc1b1
PW		 1095{
1096 u32 regindex;
1097 u32 bitindex;
1098 u32 bits;
1099 u32 first_empty_slot;
1100
1101 if (vlan > 4095)
1102 return IXGBE_ERR_PARAM;
1103
1104 /*
1105 * this is a 2 part operation - first the VFTA, then the
1106 * VLVF and VLVFB if vind is set
1107 */
1108
1109 /* Part 1
1110 * The VFTA is a bitstring made up of 128 32-bit registers
1111 * that enable the particular VLAN id, much like the MTA:
1112 * bits[11-5]: which register
1113 * bits[4-0]: which bit in the register
1114 */
1115 regindex = (vlan >> 5) & 0x7F;
1116 bitindex = vlan & 0x1F;
1117 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1118 if (vlan_on)
1119 bits |= (1 << bitindex);
1120 else
1121 bits &= ~(1 << bitindex);
1122 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1123
1124
1125 /* Part 2
1126 * If the vind is set
1127 * Either vlan_on
1128 * make sure the vlan is in VLVF
1129 * set the vind bit in the matching VLVFB
1130 * Or !vlan_on
1131 * clear the pool bit and possibly the vind
1132 */
1133 if (vind) {
1134 /* find the vlanid or the first empty slot */
1135 first_empty_slot = 0;
1136
1137 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
1138 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
1139 if (!bits && !first_empty_slot)
1140 first_empty_slot = regindex;
1141 else if ((bits & 0x0FFF) == vlan)
1142 break;
1143 }
1144
1145 if (regindex >= IXGBE_VLVF_ENTRIES) {
1146 if (first_empty_slot)
1147 regindex = first_empty_slot;
1148 else {
1149 hw_dbg(hw, "No space in VLVF.\n");
1150 goto out;
1151 }
1152 }
1153
1154 if (vlan_on) {
1155 /* set the pool bit */
1156 if (vind < 32) {
1157 bits = IXGBE_READ_REG(hw,
1158 IXGBE_VLVFB(regindex * 2));
1159 bits |= (1 << vind);
1160 IXGBE_WRITE_REG(hw,
1161 IXGBE_VLVFB(regindex * 2), bits);
1162 } else {
1163 bits = IXGBE_READ_REG(hw,
1164 IXGBE_VLVFB((regindex * 2) + 1));
1165 bits |= (1 << vind);
1166 IXGBE_WRITE_REG(hw,
1167 IXGBE_VLVFB((regindex * 2) + 1), bits);
1168 }
1169 } else {
1170 /* clear the pool bit */
1171 if (vind < 32) {
1172 bits = IXGBE_READ_REG(hw,
1173 IXGBE_VLVFB(regindex * 2));
1174 bits &= ~(1 << vind);
1175 IXGBE_WRITE_REG(hw,
1176 IXGBE_VLVFB(regindex * 2), bits);
1177 bits |= IXGBE_READ_REG(hw,
1178 IXGBE_VLVFB((regindex * 2) + 1));
1179 } else {
1180 bits = IXGBE_READ_REG(hw,
1181 IXGBE_VLVFB((regindex * 2) + 1));
1182 bits &= ~(1 << vind);
1183 IXGBE_WRITE_REG(hw,
1184 IXGBE_VLVFB((regindex * 2) + 1), bits);
1185 bits |= IXGBE_READ_REG(hw,
1186 IXGBE_VLVFB(regindex * 2));
1187 }
1188 }
1189
1190 if (bits)
1191 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
1192 (IXGBE_VLVF_VIEN | vlan));
1193 else
1194 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
1195 }
1196
1197out:
1198 return 0;
1199}
1200
1201/**
1202 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1203 * @hw: pointer to hardware structure
1204 *
1205 * Clears the VLAN filer table, and the VMDq index associated with the filter
1206 **/
7b25cdba 1207static s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1208{
1209 u32 offset;
1210
1211 for (offset = 0; offset < hw->mac.vft_size; offset++)
1212 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1213
1214 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1215 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1216 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1217 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1218 }
1219
1220 return 0;
1221}
1222
11afc1b1
PW		 1223/**
1224 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1225 * @hw: pointer to hardware structure
1226 **/
7b25cdba 1227static s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1228{
1229 int i;
1230 hw_dbg(hw, " Clearing UTA\n");
1231
1232 for (i = 0; i < 128; i++)
1233 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1234
1235 return 0;
1236}
1237
ffff4772
PWJ		 1238/**
1239 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1240 * @hw: pointer to hardware structure
1241 **/
1242s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1243{
1244 int i;
1245 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1246 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1247
1248 /*
1249 * Before starting reinitialization process,
1250 * FDIRCMD.CMD must be zero.
1251 */
1252 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1253 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1254 IXGBE_FDIRCMD_CMD_MASK))
1255 break;
1256 udelay(10);
1257 }
1258 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1259 hw_dbg(hw ,"Flow Director previous command isn't complete, "
1260 "aborting table re-initialization. \n");
1261 return IXGBE_ERR_FDIR_REINIT_FAILED;
1262 }
1263
1264 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1265 IXGBE_WRITE_FLUSH(hw);
1266 /*
1267 * 82599 adapters flow director init flow cannot be restarted,
1268 * Workaround 82599 silicon errata by performing the following steps
1269 * before re-writing the FDIRCTRL control register with the same value.
1270 * - write 1 to bit 8 of FDIRCMD register &
1271 * - write 0 to bit 8 of FDIRCMD register
1272 */
1273 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1274 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1275 IXGBE_FDIRCMD_CLEARHT));
1276 IXGBE_WRITE_FLUSH(hw);
1277 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1278 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1279 ~IXGBE_FDIRCMD_CLEARHT));
1280 IXGBE_WRITE_FLUSH(hw);
1281 /*
1282 * Clear FDIR Hash register to clear any leftover hashes
1283 * waiting to be programmed.
1284 */
1285 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1286 IXGBE_WRITE_FLUSH(hw);
1287
1288 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1289 IXGBE_WRITE_FLUSH(hw);
1290
1291 /* Poll init-done after we write FDIRCTRL register */
1292 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1293 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1294 IXGBE_FDIRCTRL_INIT_DONE)
1295 break;
1296 udelay(10);
1297 }
1298 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1299 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1300 return IXGBE_ERR_FDIR_REINIT_FAILED;
1301 }
1302
1303 /* Clear FDIR statistics registers (read to clear) */
1304 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1305 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1306 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1307 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1308 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1309
1310 return 0;
1311}
1312
1313/**
1314 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1315 * @hw: pointer to hardware structure
1316 * @pballoc: which mode to allocate filters with
1317 **/
1318s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1319{
1320 u32 fdirctrl = 0;
1321 u32 pbsize;
1322 int i;
1323
1324 /*
1325 * Before enabling Flow Director, the Rx Packet Buffer size
1326 * must be reduced. The new value is the current size minus
1327 * flow director memory usage size.
1328 */
1329 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1330 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1331 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1332
1333 /*
1334 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1335 * intialized to zero for non DCB mode otherwise actual total RX PB
1336 * would be bigger than programmed and filter space would run into
1337 * the PB 0 region.
1338 */
1339 for (i = 1; i < 8; i++)
1340 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1341
1342 /* Send interrupt when 64 filters are left */
1343 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1344
1345 /* Set the maximum length per hash bucket to 0xA filters */
1346 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1347
1348 switch (pballoc) {
1349 case IXGBE_FDIR_PBALLOC_64K:
1350 /* 8k - 1 signature filters */
1351 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1352 break;
1353 case IXGBE_FDIR_PBALLOC_128K:
1354 /* 16k - 1 signature filters */
1355 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1356 break;
1357 case IXGBE_FDIR_PBALLOC_256K:
1358 /* 32k - 1 signature filters */
1359 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1360 break;
1361 default:
1362 /* bad value */
1363 return IXGBE_ERR_CONFIG;
1364 };
1365
1366 /* Move the flexible bytes to use the ethertype - shift 6 words */
1367 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1368
1369 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1370
1371 /* Prime the keys for hashing */
1372 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1373 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1374 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1375 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1376
1377 /*
1378 * Poll init-done after we write the register. Estimated times:
1379 * 10G: PBALLOC = 11b, timing is 60us
1380 * 1G: PBALLOC = 11b, timing is 600us
1381 * 100M: PBALLOC = 11b, timing is 6ms
1382 *
1383 * Multiple these timings by 4 if under full Rx load
1384 *
1385 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1386 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1387 * this might not finish in our poll time, but we can live with that
1388 * for now.
1389 */
1390 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1391 IXGBE_WRITE_FLUSH(hw);
1392 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1393 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1394 IXGBE_FDIRCTRL_INIT_DONE)
1395 break;
1396 msleep(1);
1397 }
1398 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1399 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1400
1401 return 0;
1402}
1403
1404/**
1405 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1406 * @hw: pointer to hardware structure
1407 * @pballoc: which mode to allocate filters with
1408 **/
1409s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1410{
1411 u32 fdirctrl = 0;
1412 u32 pbsize;
1413 int i;
1414
1415 /*
1416 * Before enabling Flow Director, the Rx Packet Buffer size
1417 * must be reduced. The new value is the current size minus
1418 * flow director memory usage size.
1419 */
1420 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1421 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1422 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1423
1424 /*
1425 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1426 * intialized to zero for non DCB mode otherwise actual total RX PB
1427 * would be bigger than programmed and filter space would run into
1428 * the PB 0 region.
1429 */
1430 for (i = 1; i < 8; i++)
1431 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1432
1433 /* Send interrupt when 64 filters are left */
1434 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1435
1436 switch (pballoc) {
1437 case IXGBE_FDIR_PBALLOC_64K:
1438 /* 2k - 1 perfect filters */
1439 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1440 break;
1441 case IXGBE_FDIR_PBALLOC_128K:
1442 /* 4k - 1 perfect filters */
1443 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1444 break;
1445 case IXGBE_FDIR_PBALLOC_256K:
1446 /* 8k - 1 perfect filters */
1447 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1448 break;
1449 default:
1450 /* bad value */
1451 return IXGBE_ERR_CONFIG;
1452 };
1453
1454 /* Turn perfect match filtering on */
1455 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1456 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1457
1458 /* Move the flexible bytes to use the ethertype - shift 6 words */
1459 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1460
1461 /* Prime the keys for hashing */
1462 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1463 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1464 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1465 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1466
1467 /*
1468 * Poll init-done after we write the register. Estimated times:
1469 * 10G: PBALLOC = 11b, timing is 60us
1470 * 1G: PBALLOC = 11b, timing is 600us
1471 * 100M: PBALLOC = 11b, timing is 6ms
1472 *
1473 * Multiple these timings by 4 if under full Rx load
1474 *
1475 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1476 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1477 * this might not finish in our poll time, but we can live with that
1478 * for now.
1479 */
1480
1481 /* Set the maximum length per hash bucket to 0xA filters */
1482 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1483
1484 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1485 IXGBE_WRITE_FLUSH(hw);
1486 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1487 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1488 IXGBE_FDIRCTRL_INIT_DONE)
1489 break;
1490 msleep(1);
1491 }
1492 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1493 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1494
1495 return 0;
1496}
1497
1498
1499/**
1500 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1501 * @stream: input bitstream to compute the hash on
1502 * @key: 32-bit hash key
1503 **/
7b25cdba
DS		 1504static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1505 u32 key)
ffff4772
PWJ		 1506{
1507 /*
1508 * The algorithm is as follows:
1509 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1510 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1511 * and A[n] x B[n] is bitwise AND between same length strings
1512 *
1513 * K[n] is 16 bits, defined as:
1514 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1515 * for n modulo 32 < 15, K[n] =
1516 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1517 *
1518 * S[n] is 16 bits, defined as:
1519 * for n >= 15, S[n] = S[n:n - 15]
1520 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1521 *
1522 * To simplify for programming, the algorithm is implemented
1523 * in software this way:
1524 *
1525 * Key[31:0], Stream[335:0]
1526 *
1527 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1528 * int_key[350:0] = tmp_key[351:1]
1529 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1530 *
1531 * hash[15:0] = 0;
1532 * for (i = 0; i < 351; i++) {
1533 * if (int_key[i])
1534 * hash ^= int_stream[(i + 15):i];
1535 * }
1536 */
1537
1538 union {
1539 u64 fill[6];
1540 u32 key[11];
1541 u8 key_stream[44];
1542 } tmp_key;
1543
1544 u8 *stream = (u8 *)atr_input;
1545 u8 int_key[44]; /* upper-most bit unused */
1546 u8 hash_str[46]; /* upper-most 2 bits unused */
1547 u16 hash_result = 0;
1548 int i, j, k, h;
1549
1550 /*
1551 * Initialize the fill member to prevent warnings
1552 * on some compilers
1553 */
1554 tmp_key.fill[0] = 0;
1555
1556 /* First load the temporary key stream */
1557 for (i = 0; i < 6; i++) {
1558 u64 fillkey = ((u64)key << 32) | key;
1559 tmp_key.fill[i] = fillkey;
1560 }
1561
1562 /*
1563 * Set the interim key for the hashing. Bit 352 is unused, so we must
1564 * shift and compensate when building the key.
1565 */
1566
1567 int_key[0] = tmp_key.key_stream[0] >> 1;
1568 for (i = 1, j = 0; i < 44; i++) {
1569 unsigned int this_key = tmp_key.key_stream[j] << 7;
1570 j++;
1571 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1572 }
1573
1574 /*
1575 * Set the interim bit string for the hashing. Bits 368 and 367 are
1576 * unused, so shift and compensate when building the string.
1577 */
1578 hash_str[0] = (stream[40] & 0x7f) >> 1;
1579 for (i = 1, j = 40; i < 46; i++) {
1580 unsigned int this_str = stream[j] << 7;
1581 j++;
1582 if (j > 41)
1583 j = 0;
1584 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1585 }
1586
1587 /*
1588 * Now compute the hash. i is the index into hash_str, j is into our
1589 * key stream, k is counting the number of bits, and h interates within
1590 * each byte.
1591 */
1592 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1593 for (h = 0; h < 8 && k < 351; h++, k++) {
1594 if (int_key[j] & (1 << h)) {
1595 /*
1596 * Key bit is set, XOR in the current 16-bit
1597 * string. Example of processing:
1598 * h = 0,
1599 * tmp = (hash_str[i - 2] & 0 << 16) |
1600 * (hash_str[i - 1] & 0xff << 8) |
1601 * (hash_str[i] & 0xff >> 0)
1602 * So tmp = hash_str[15 + k:k], since the
1603 * i + 2 clause rolls off the 16-bit value
1604 * h = 7,
1605 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1606 * (hash_str[i - 1] & 0xff << 1) |
1607 * (hash_str[i] & 0x80 >> 7)
1608 */
1609 int tmp = (hash_str[i] >> h);
1610 tmp |= (hash_str[i - 1] << (8 - h));
1611 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1612 << (16 - h);
1613 hash_result ^= (u16)tmp;
1614 }
1615 }
1616 }
1617
1618 return hash_result;
1619}
1620
1621/**
1622 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1623 * @input: input stream to modify
1624 * @vlan: the VLAN id to load
1625 **/
1626s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1627{
1628 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1629 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1630
1631 return 0;
1632}
1633
1634/**
1635 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1636 * @input: input stream to modify
1637 * @src_addr: the IP address to load
1638 **/
1639s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1640{
1641 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1642 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1643 (src_addr >> 16) & 0xff;
1644 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1645 (src_addr >> 8) & 0xff;
1646 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1647
1648 return 0;
1649}
1650
1651/**
1652 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1653 * @input: input stream to modify
1654 * @dst_addr: the IP address to load
1655 **/
1656s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1657{
1658 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1659 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1660 (dst_addr >> 16) & 0xff;
1661 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1662 (dst_addr >> 8) & 0xff;
1663 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1664
1665 return 0;
1666}
1667
1668/**
1669 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1670 * @input: input stream to modify
1671 * @src_addr_1: the first 4 bytes of the IP address to load
1672 * @src_addr_2: the second 4 bytes of the IP address to load
1673 * @src_addr_3: the third 4 bytes of the IP address to load
1674 * @src_addr_4: the fourth 4 bytes of the IP address to load
1675 **/
1676s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1677 u32 src_addr_1, u32 src_addr_2,
1678 u32 src_addr_3, u32 src_addr_4)
ffff4772
PWJ		 1679{
1680 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1681 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1682 (src_addr_4 >> 8) & 0xff;
1683 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1684 (src_addr_4 >> 16) & 0xff;
1685 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1686
1687 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1688 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1689 (src_addr_3 >> 8) & 0xff;
1690 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1691 (src_addr_3 >> 16) & 0xff;
1692 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1693
1694 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1695 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1696 (src_addr_2 >> 8) & 0xff;
1697 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1698 (src_addr_2 >> 16) & 0xff;
1699 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1700
1701 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1702 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1703 (src_addr_1 >> 8) & 0xff;
1704 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1705 (src_addr_1 >> 16) & 0xff;
1706 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1707
1708 return 0;
1709}
1710
1711/**
1712 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1713 * @input: input stream to modify
1714 * @dst_addr_1: the first 4 bytes of the IP address to load
1715 * @dst_addr_2: the second 4 bytes of the IP address to load
1716 * @dst_addr_3: the third 4 bytes of the IP address to load
1717 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1718 **/
1719s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1720 u32 dst_addr_1, u32 dst_addr_2,
1721 u32 dst_addr_3, u32 dst_addr_4)
ffff4772
PWJ		 1722{
1723 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1724 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1725 (dst_addr_4 >> 8) & 0xff;
1726 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1727 (dst_addr_4 >> 16) & 0xff;
1728 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1729
1730 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1731 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1732 (dst_addr_3 >> 8) & 0xff;
1733 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1734 (dst_addr_3 >> 16) & 0xff;
1735 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1736
1737 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1738 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1739 (dst_addr_2 >> 8) & 0xff;
1740 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1741 (dst_addr_2 >> 16) & 0xff;
1742 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1743
1744 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1745 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1746 (dst_addr_1 >> 8) & 0xff;
1747 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1748 (dst_addr_1 >> 16) & 0xff;
1749 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1750
1751 return 0;
1752}
1753
1754/**
1755 * ixgbe_atr_set_src_port_82599 - Sets the source port
1756 * @input: input stream to modify
1757 * @src_port: the source port to load
1758 **/
1759s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1760{
1761 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1762 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1763
1764 return 0;
1765}
1766
1767/**
1768 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1769 * @input: input stream to modify
1770 * @dst_port: the destination port to load
1771 **/
1772s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1773{
1774 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1775 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1776
1777 return 0;
1778}
1779
1780/**
1781 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1782 * @input: input stream to modify
1783 * @flex_bytes: the flexible bytes to load
1784 **/
1785s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1786{
1787 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1788 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1789
1790 return 0;
1791}
1792
1793/**
1794 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1795 * @input: input stream to modify
1796 * @vm_pool: the Virtual Machine pool to load
1797 **/
7b25cdba
DS		 1798s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
1799 u8 vm_pool)
ffff4772
PWJ		 1800{
1801 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1802
1803 return 0;
1804}
1805
1806/**
1807 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1808 * @input: input stream to modify
1809 * @l4type: the layer 4 type value to load
1810 **/
1811s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1812{
1813 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1814
1815 return 0;
1816}
1817
1818/**
1819 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1820 * @input: input stream to search
1821 * @vlan: the VLAN id to load
1822 **/
7b25cdba
DS		 1823static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input,
1824 u16 *vlan)
ffff4772
PWJ		 1825{
1826 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1827 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1828
1829 return 0;
1830}
1831
1832/**
1833 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1834 * @input: input stream to search
1835 * @src_addr: the IP address to load
1836 **/
7b25cdba
DS		 1837static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1838 u32 *src_addr)
ffff4772
PWJ		 1839{
1840 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1841 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1842 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1843 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1844
1845 return 0;
1846}
1847
1848/**
1849 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1850 * @input: input stream to search
1851 * @dst_addr: the IP address to load
1852 **/
7b25cdba
DS		 1853static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1854 u32 *dst_addr)
ffff4772
PWJ		 1855{
1856 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1857 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1858 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1859 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1860
1861 return 0;
1862}
1863
1864/**
1865 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1866 * @input: input stream to search
1867 * @src_addr_1: the first 4 bytes of the IP address to load
1868 * @src_addr_2: the second 4 bytes of the IP address to load
1869 * @src_addr_3: the third 4 bytes of the IP address to load
1870 * @src_addr_4: the fourth 4 bytes of the IP address to load
1871 **/
7b25cdba
DS		 1872static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1873 u32 *src_addr_1, u32 *src_addr_2,
1874 u32 *src_addr_3, u32 *src_addr_4)
ffff4772
PWJ		 1875{
1876 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1877 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1878 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1879 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1880
1881 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1882 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1883 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1884 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1885
1886 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1887 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1888 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1889 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1890
1891 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1892 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1893 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1894 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1895
1896 return 0;
1897}
1898
1899/**
1900 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1901 * @input: input stream to search
1902 * @dst_addr_1: the first 4 bytes of the IP address to load
1903 * @dst_addr_2: the second 4 bytes of the IP address to load
1904 * @dst_addr_3: the third 4 bytes of the IP address to load
1905 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1906 **/
1907s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1908 u32 *dst_addr_1, u32 *dst_addr_2,
1909 u32 *dst_addr_3, u32 *dst_addr_4)
ffff4772
PWJ		 1910{
1911 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
1912 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
1913 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
1914 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
1915
1916 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
1917 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
1918 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
1919 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
1920
1921 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
1922 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1923 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1924 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1925
1926 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1927 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1928 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1929 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1930
1931 return 0;
1932}
1933
1934/**
1935 * ixgbe_atr_get_src_port_82599 - Gets the source port
1936 * @input: input stream to modify
1937 * @src_port: the source port to load
1938 *
1939 * Even though the input is given in big-endian, the FDIRPORT registers
1940 * expect the ports to be programmed in little-endian. Hence the need to swap
1941 * endianness when retrieving the data. This can be confusing since the
1942 * internal hash engine expects it to be big-endian.
1943 **/
7b25cdba
DS		 1944static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1945 u16 *src_port)
ffff4772
PWJ		 1946{
1947 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1948 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1949
1950 return 0;
1951}
1952
1953/**
1954 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1955 * @input: input stream to modify
1956 * @dst_port: the destination port to load
1957 *
1958 * Even though the input is given in big-endian, the FDIRPORT registers
1959 * expect the ports to be programmed in little-endian. Hence the need to swap
1960 * endianness when retrieving the data. This can be confusing since the
1961 * internal hash engine expects it to be big-endian.
1962 **/
7b25cdba
DS		 1963static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1964 u16 *dst_port)
ffff4772
PWJ		 1965{
1966 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1967 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1968
1969 return 0;
1970}
1971
1972/**
1973 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1974 * @input: input stream to modify
1975 * @flex_bytes: the flexible bytes to load
1976 **/
7b25cdba
DS		 1977static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1978 u16 *flex_byte)
ffff4772
PWJ		 1979{
1980 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1981 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1982
1983 return 0;
1984}
1985
1986/**
1987 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
1988 * @input: input stream to modify
1989 * @vm_pool: the Virtual Machine pool to load
1990 **/
7b25cdba
DS		 1991s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
1992 u8 *vm_pool)
ffff4772
PWJ		 1993{
1994 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
1995
1996 return 0;
1997}
1998
1999/**
2000 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
2001 * @input: input stream to modify
2002 * @l4type: the layer 4 type value to load
2003 **/
7b25cdba
DS		 2004static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
2005 u8 *l4type)
ffff4772
PWJ		 2006{
2007 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
2008
2009 return 0;
2010}
2011
2012/**
2013 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
2014 * @hw: pointer to hardware structure
2015 * @stream: input bitstream
2016 * @queue: queue index to direct traffic to
2017 **/
2018s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
2019 struct ixgbe_atr_input *input,
2020 u8 queue)
2021{
2022 u64 fdirhashcmd;
2023 u64 fdircmd;
2024 u32 fdirhash;
2025 u16 bucket_hash, sig_hash;
2026 u8 l4type;
2027
2028 bucket_hash = ixgbe_atr_compute_hash_82599(input,
2029 IXGBE_ATR_BUCKET_HASH_KEY);
2030
2031 /* bucket_hash is only 15 bits */
2032 bucket_hash &= IXGBE_ATR_HASH_MASK;
2033
2034 sig_hash = ixgbe_atr_compute_hash_82599(input,
2035 IXGBE_ATR_SIGNATURE_HASH_KEY);
2036
2037 /* Get the l4type in order to program FDIRCMD properly */
2038 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
2039 ixgbe_atr_get_l4type_82599(input, &l4type);
2040
2041 /*
2042 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
2043 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
2044 */
2045 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2046
2047 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
2048 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
2049
2050 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2051 case IXGBE_ATR_L4TYPE_TCP:
2052 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
2053 break;
2054 case IXGBE_ATR_L4TYPE_UDP:
2055 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
2056 break;
2057 case IXGBE_ATR_L4TYPE_SCTP:
2058 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
2059 break;
2060 default:
2061 hw_dbg(hw, "Error on l4type input\n");
2062 return IXGBE_ERR_CONFIG;
2063 }
2064
2065 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
2066 fdircmd |= IXGBE_FDIRCMD_IPV6;
2067
2068 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
2069 fdirhashcmd = ((fdircmd << 32) | fdirhash);
2070
2071 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
2072
2073 return 0;
2074}
2075
2076/**
2077 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
2078 * @hw: pointer to hardware structure
2079 * @input: input bitstream
2080 * @queue: queue index to direct traffic to
2081 *
2082 * Note that the caller to this function must lock before calling, since the
2083 * hardware writes must be protected from one another.
2084 **/
2085s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
7b25cdba
DS		 2086 struct ixgbe_atr_input *input,
2087 u16 soft_id,
2088 u8 queue)
ffff4772
PWJ		 2089{
2090 u32 fdircmd = 0;
2091 u32 fdirhash;
2092 u32 src_ipv4, dst_ipv4;
2093 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
2094 u16 src_port, dst_port, vlan_id, flex_bytes;
2095 u16 bucket_hash;
2096 u8 l4type;
2097
2098 /* Get our input values */
2099 ixgbe_atr_get_l4type_82599(input, &l4type);
2100
2101 /*
2102 * Check l4type formatting, and bail out before we touch the hardware
2103 * if there's a configuration issue
2104 */
2105 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2106 case IXGBE_ATR_L4TYPE_TCP:
2107 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
2108 break;
2109 case IXGBE_ATR_L4TYPE_UDP:
2110 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
2111 break;
2112 case IXGBE_ATR_L4TYPE_SCTP:
2113 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
2114 break;
2115 default:
2116 hw_dbg(hw, "Error on l4type input\n");
2117 return IXGBE_ERR_CONFIG;
2118 }
2119
2120 bucket_hash = ixgbe_atr_compute_hash_82599(input,
2121 IXGBE_ATR_BUCKET_HASH_KEY);
2122
2123 /* bucket_hash is only 15 bits */
2124 bucket_hash &= IXGBE_ATR_HASH_MASK;
2125
2126 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
2127 ixgbe_atr_get_src_port_82599(input, &src_port);
2128 ixgbe_atr_get_dst_port_82599(input, &dst_port);
2129 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
2130
2131 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2132
2133 /* Now figure out if we're IPv4 or IPv6 */
2134 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
2135 /* IPv6 */
2136 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
2137 &src_ipv6_3, &src_ipv6_4);
2138
2139 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
2140 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
2141 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
2142 /* The last 4 bytes is the same register as IPv4 */
2143 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
2144
2145 fdircmd |= IXGBE_FDIRCMD_IPV6;
2146 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
2147 } else {
2148 /* IPv4 */
2149 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
2150 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
2151
2152 }
2153
2154 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
2155 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
2156
2157 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
2158 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
2159 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
2160 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
2161
2162 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
2163 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
2164 fdircmd |= IXGBE_FDIRCMD_LAST;
2165 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
2166 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
2167
2168 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2169 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
2170
2171 return 0;
2172}
11afc1b1
PW		 2173/**
2174 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2175 * @hw: pointer to hardware structure
2176 * @reg: analog register to read
2177 * @val: read value
2178 *
2179 * Performs read operation to Omer analog register specified.
2180 **/
7b25cdba 2181static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
11afc1b1
PW		 2182{
2183 u32 core_ctl;
2184
2185 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2186 (reg << 8));
2187 IXGBE_WRITE_FLUSH(hw);
2188 udelay(10);
2189 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2190 *val = (u8)core_ctl;
2191
2192 return 0;
2193}
2194
2195/**
2196 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2197 * @hw: pointer to hardware structure
2198 * @reg: atlas register to write
2199 * @val: value to write
2200 *
2201 * Performs write operation to Omer analog register specified.
2202 **/
7b25cdba 2203static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
11afc1b1
PW		 2204{
2205 u32 core_ctl;
2206
2207 core_ctl = (reg << 8) | val;
2208 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2209 IXGBE_WRITE_FLUSH(hw);
2210 udelay(10);
2211
2212 return 0;
2213}
2214
2215/**
2216 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2217 * @hw: pointer to hardware structure
2218 *
2219 * Starts the hardware using the generic start_hw function.
2220 * Then performs device-specific:
2221 * Clears the rate limiter registers.
2222 **/
7b25cdba 2223static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2224{
2225 u32 q_num;
794caeb2 2226 s32 ret_val;
11afc1b1 2227
794caeb2 2228 ret_val = ixgbe_start_hw_generic(hw);
11afc1b1
PW		 2229
2230 /* Clear the rate limiters */
2231 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2232 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2233 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2234 }
2235 IXGBE_WRITE_FLUSH(hw);
2236
50ac58ba
PWJ		 2237 /* We need to run link autotry after the driver loads */
2238 hw->mac.autotry_restart = true;
2239
794caeb2
PWJ		 2240 if (ret_val == 0)
2241 ret_val = ixgbe_verify_fw_version_82599(hw);
2242
2243 return ret_val;
11afc1b1
PW		 2244}
2245
2246/**
2247 * ixgbe_identify_phy_82599 - Get physical layer module
2248 * @hw: pointer to hardware structure
2249 *
2250 * Determines the physical layer module found on the current adapter.
2251 **/
7b25cdba 2252static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2253{
2254 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2255 status = ixgbe_identify_phy_generic(hw);
2256 if (status != 0)
2257 status = ixgbe_identify_sfp_module_generic(hw);
2258 return status;
2259}
2260
2261/**
2262 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2263 * @hw: pointer to hardware structure
2264 *
2265 * Determines physical layer capabilities of the current configuration.
2266 **/
7b25cdba 2267static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2268{
2269 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 2270 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2271 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2272 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2273 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2274 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2275 u16 ext_ability = 0;
1339b9e9 2276 u8 comp_codes_10g = 0;
11afc1b1 2277
04193058
PWJ		 2278 hw->phy.ops.identify(hw);
2279
2280 if (hw->phy.type == ixgbe_phy_tn ||
2281 hw->phy.type == ixgbe_phy_cu_unknown) {
6b73e10d
BH		 2282 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2283 &ext_ability);
2284 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 2285 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 2286 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 2287 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 2288 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 2289 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2290 goto out;
2291 }
2292
2293 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2294 case IXGBE_AUTOC_LMS_1G_AN:
2295 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2296 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2297 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2298 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2299 goto out;
2300 } else
2301 /* SFI mode so read SFP module */
2302 goto sfp_check;
11afc1b1 2303 break;
04193058
PWJ		 2304 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2305 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2306 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2307 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2308 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 2309 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2310 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 2311 goto out;
2312 break;
2313 case IXGBE_AUTOC_LMS_10G_SERIAL:
2314 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2315 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2316 goto out;
2317 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2318 goto sfp_check;
2319 break;
2320 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2321 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2322 if (autoc & IXGBE_AUTOC_KX_SUPP)
2323 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2324 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2325 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2326 if (autoc & IXGBE_AUTOC_KR_SUPP)
2327 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2328 goto out;
2329 break;
2330 default:
2331 goto out;
2332 break;
2333 }
11afc1b1 2334
04193058
PWJ		 2335sfp_check:
2336 /* SFP check must be done last since DA modules are sometimes used to
2337 * test KR mode - we need to id KR mode correctly before SFP module.
2338 * Call identify_sfp because the pluggable module may have changed */
2339 hw->phy.ops.identify_sfp(hw);
2340 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2341 goto out;
2342
2343 switch (hw->phy.type) {
2344 case ixgbe_phy_tw_tyco:
2345 case ixgbe_phy_tw_unknown:
2346 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2347 break;
2348 case ixgbe_phy_sfp_avago:
2349 case ixgbe_phy_sfp_ftl:
2350 case ixgbe_phy_sfp_intel:
2351 case ixgbe_phy_sfp_unknown:
2352 hw->phy.ops.read_i2c_eeprom(hw,
2353 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2354 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 2355 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 2356 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 2357 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
11afc1b1
PW		 2358 break;
2359 default:
11afc1b1
PW		 2360 break;
2361 }
2362
04193058 2363out:
11afc1b1
PW		 2364 return physical_layer;
2365}
2366
2367/**
2368 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2369 * @hw: pointer to hardware structure
2370 * @regval: register value to write to RXCTRL
2371 *
2372 * Enables the Rx DMA unit for 82599
2373 **/
7b25cdba 2374static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
11afc1b1
PW		 2375{
2376#define IXGBE_MAX_SECRX_POLL 30
2377 int i;
2378 int secrxreg;
2379
2380 /*
2381 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2382 * If traffic is incoming before we enable the Rx unit, it could hang
2383 * the Rx DMA unit. Therefore, make sure the security engine is
2384 * completely disabled prior to enabling the Rx unit.
2385 */
2386 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2387 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2388 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2389 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2390 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2391 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2392 break;
2393 else
2394 udelay(10);
2395 }
2396
2397 /* For informational purposes only */
2398 if (i >= IXGBE_MAX_SECRX_POLL)
2399 hw_dbg(hw, "Rx unit being enabled before security "
2400 "path fully disabled. Continuing with init.\n");
2401
2402 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2403 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2404 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2405 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2406 IXGBE_WRITE_FLUSH(hw);
2407
2408 return 0;
2409}
2410
04193058
PWJ		 2411/**
2412 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2413 * @hw: pointer to hardware structure
2414 * @device_caps: the EEPROM word with the extra device capabilities
2415 *
2416 * This function will read the EEPROM location for the device capabilities,
2417 * and return the word through device_caps.
2418 **/
7b25cdba 2419static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
04193058
PWJ		 2420{
2421 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2422
2423 return 0;
2424}
2425
0365e6e4
PW		 2426/**
2427 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2428 * @hw: pointer to hardware structure
2429 * @san_mac_offset: SAN MAC address offset
2430 *
2431 * This function will read the EEPROM location for the SAN MAC address
2432 * pointer, and returns the value at that location. This is used in both
2433 * get and set mac_addr routines.
2434 **/
7b25cdba
DS		 2435static s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
2436 u16 *san_mac_offset)
0365e6e4
PW		 2437{
2438 /*
2439 * First read the EEPROM pointer to see if the MAC addresses are
2440 * available.
2441 */
2442 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2443
2444 return 0;
2445}
2446
2447/**
2448 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2449 * @hw: pointer to hardware structure
2450 * @san_mac_addr: SAN MAC address
2451 *
2452 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2453 * per-port, so set_lan_id() must be called before reading the addresses.
2454 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2455 * upon for non-SFP connections, so we must call it here.
2456 **/
7b25cdba 2457static s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
0365e6e4
PW		 2458{
2459 u16 san_mac_data, san_mac_offset;
2460 u8 i;
2461
2462 /*
2463 * First read the EEPROM pointer to see if the MAC addresses are
2464 * available. If they're not, no point in calling set_lan_id() here.
2465 */
2466 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
2467
2468 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2469 /*
2470 * No addresses available in this EEPROM. It's not an
2471 * error though, so just wipe the local address and return.
2472 */
2473 for (i = 0; i < 6; i++)
2474 san_mac_addr[i] = 0xFF;
2475
2476 goto san_mac_addr_out;
2477 }
2478
2479 /* make sure we know which port we need to program */
2480 hw->mac.ops.set_lan_id(hw);
2481 /* apply the port offset to the address offset */
2482 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2483 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2484 for (i = 0; i < 3; i++) {
2485 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2486 san_mac_addr[i * 2] = (u8)(san_mac_data);
2487 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2488 san_mac_offset++;
2489 }
2490
2491san_mac_addr_out:
2492 return 0;
2493}
2494
794caeb2
PWJ		 2495/**
2496 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2497 * @hw: pointer to hardware structure
2498 *
2499 * Verifies that installed the firmware version is 0.6 or higher
2500 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2501 *
2502 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2503 * if the FW version is not supported.
2504 **/
2505static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2506{
2507 s32 status = IXGBE_ERR_EEPROM_VERSION;
2508 u16 fw_offset, fw_ptp_cfg_offset;
2509 u16 fw_version = 0;
2510
2511 /* firmware check is only necessary for SFI devices */
2512 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2513 status = 0;
2514 goto fw_version_out;
2515 }
2516
2517 /* get the offset to the Firmware Module block */
2518 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2519
2520 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2521 goto fw_version_out;
2522
2523 /* get the offset to the Pass Through Patch Configuration block */
2524 hw->eeprom.ops.read(hw, (fw_offset +
2525 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2526 &fw_ptp_cfg_offset);
2527
2528 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2529 goto fw_version_out;
2530
2531 /* get the firmware version */
2532 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2533 IXGBE_FW_PATCH_VERSION_4),
2534 &fw_version);
2535
2536 if (fw_version > 0x5)
2537 status = 0;
2538
2539fw_version_out:
2540 return status;
2541}
2542
383ff34b
YZ		 2543/**
2544 * ixgbe_get_wwn_prefix_82599 - Get alternative WWNN/WWPN prefix from
2545 * the EEPROM
2546 * @hw: pointer to hardware structure
2547 * @wwnn_prefix: the alternative WWNN prefix
2548 * @wwpn_prefix: the alternative WWPN prefix
2549 *
2550 * This function will read the EEPROM from the alternative SAN MAC address
2551 * block to check the support for the alternative WWNN/WWPN prefix support.
2552 **/
2553static s32 ixgbe_get_wwn_prefix_82599(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2554 u16 *wwpn_prefix)
2555{
2556 u16 offset, caps;
2557 u16 alt_san_mac_blk_offset;
2558
2559 /* clear output first */
2560 *wwnn_prefix = 0xFFFF;
2561 *wwpn_prefix = 0xFFFF;
2562
2563 /* check if alternative SAN MAC is supported */
2564 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2565 &alt_san_mac_blk_offset);
2566
2567 if ((alt_san_mac_blk_offset == 0) ||
2568 (alt_san_mac_blk_offset == 0xFFFF))
2569 goto wwn_prefix_out;
2570
2571 /* check capability in alternative san mac address block */
2572 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2573 hw->eeprom.ops.read(hw, offset, &caps);
2574 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2575 goto wwn_prefix_out;
2576
2577 /* get the corresponding prefix for WWNN/WWPN */
2578 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2579 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2580
2581 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2582 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2583
2584wwn_prefix_out:
2585 return 0;
2586}
2587
11afc1b1
PW		 2588static struct ixgbe_mac_operations mac_ops_82599 = {
2589 .init_hw = &ixgbe_init_hw_generic,
2590 .reset_hw = &ixgbe_reset_hw_82599,
2591 .start_hw = &ixgbe_start_hw_82599,
2592 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2593 .get_media_type = &ixgbe_get_media_type_82599,
2594 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2595 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2596 .get_mac_addr = &ixgbe_get_mac_addr_generic,
0365e6e4 2597 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
04193058 2598 .get_device_caps = &ixgbe_get_device_caps_82599,
383ff34b 2599 .get_wwn_prefix = &ixgbe_get_wwn_prefix_82599,
11afc1b1
PW		 2600 .stop_adapter = &ixgbe_stop_adapter_generic,
2601 .get_bus_info = &ixgbe_get_bus_info_generic,
2602 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2603 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2604 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2605 .setup_link = &ixgbe_setup_mac_link_82599,
11afc1b1
PW		 2606 .check_link = &ixgbe_check_mac_link_82599,
2607 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2608 .led_on = &ixgbe_led_on_generic,
2609 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 2610 .blink_led_start = &ixgbe_blink_led_start_generic,
2611 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 2612 .set_rar = &ixgbe_set_rar_generic,
2613 .clear_rar = &ixgbe_clear_rar_generic,
2614 .set_vmdq = &ixgbe_set_vmdq_82599,
2615 .clear_vmdq = &ixgbe_clear_vmdq_82599,
2616 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2617 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2618 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2619 .enable_mc = &ixgbe_enable_mc_generic,
2620 .disable_mc = &ixgbe_disable_mc_generic,
2621 .clear_vfta = &ixgbe_clear_vfta_82599,
2622 .set_vfta = &ixgbe_set_vfta_82599,
620fa036 2623 .fc_enable = &ixgbe_fc_enable_generic,
11afc1b1
PW		 2624 .init_uta_tables = &ixgbe_init_uta_tables_82599,
2625 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2626};
2627
2628static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2629 .init_params = &ixgbe_init_eeprom_params_generic,
2630 .read = &ixgbe_read_eeprom_generic,
2631 .write = &ixgbe_write_eeprom_generic,
2632 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2633 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2634};
2635
2636static struct ixgbe_phy_operations phy_ops_82599 = {
2637 .identify = &ixgbe_identify_phy_82599,
2638 .identify_sfp = &ixgbe_identify_sfp_module_generic,
04f165ef 2639 .init = &ixgbe_init_phy_ops_82599,
11afc1b1
PW		 2640 .reset = &ixgbe_reset_phy_generic,
2641 .read_reg = &ixgbe_read_phy_reg_generic,
2642 .write_reg = &ixgbe_write_phy_reg_generic,
2643 .setup_link = &ixgbe_setup_phy_link_generic,
2644 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2645 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2646 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2647 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2648 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2649};
2650
2651struct ixgbe_info ixgbe_82599_info = {
2652 .mac = ixgbe_mac_82599EB,
2653 .get_invariants = &ixgbe_get_invariants_82599,
2654 .mac_ops = &mac_ops_82599,
2655 .eeprom_ops = &eeprom_ops_82599,
2656 .phy_ops = &phy_ops_82599,
2657};
Clone of davem's net-next-2.6 tree