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[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
11afc1b1
PW		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
096a58fd 34#include "ixgbe_mbx.h"
11afc1b1
PW		 35
36#define IXGBE_82599_MAX_TX_QUEUES 128
37#define IXGBE_82599_MAX_RX_QUEUES 128
38#define IXGBE_82599_RAR_ENTRIES 128
39#define IXGBE_82599_MC_TBL_SIZE 128
40#define IXGBE_82599_VFT_TBL_SIZE 128
41
61fac744
PW		 42void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
43void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
1097cd17 44void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
8620a103
MC		 45s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
cd7e1f0b
DS		 49static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg,
52 bool autoneg_wait_to_complete);
8620a103
MC		 53s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed speed,
57 bool autoneg,
58 bool autoneg_wait_to_complete);
11afc1b1
PW		 59static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed *speed,
61 bool *autoneg);
8620a103
MC		 62static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
63 ixgbe_link_speed speed,
64 bool autoneg,
65 bool autoneg_wait_to_complete);
794caeb2 66static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
11afc1b1 67
7b25cdba 68static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 69{
70 struct ixgbe_mac_info *mac = &hw->mac;
71 if (hw->phy.multispeed_fiber) {
72 /* Set up dual speed SFP+ support */
8620a103 73 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
61fac744
PW		 74 mac->ops.disable_tx_laser =
75 &ixgbe_disable_tx_laser_multispeed_fiber;
76 mac->ops.enable_tx_laser =
77 &ixgbe_enable_tx_laser_multispeed_fiber;
1097cd17 78 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
11afc1b1 79 } else {
61fac744
PW		 80 mac->ops.disable_tx_laser = NULL;
81 mac->ops.enable_tx_laser = NULL;
1097cd17 82 mac->ops.flap_tx_laser = NULL;
cd7e1f0b
DS		 83 if ((mac->ops.get_media_type(hw) ==
84 ixgbe_media_type_backplane) &&
85 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
86 hw->phy.smart_speed == ixgbe_smart_speed_on))
87 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
88 else
89 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
11afc1b1
PW		 90 }
91}
92
7b25cdba 93static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 94{
95 s32 ret_val = 0;
96 u16 list_offset, data_offset, data_value;
97
98 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
99 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 100
101 hw->phy.ops.reset = NULL;
102
11afc1b1
PW		 103 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
104 &data_offset);
105
106 if (ret_val != 0)
107 goto setup_sfp_out;
108
aa5aec88
PWJ		 109 /* PHY config will finish before releasing the semaphore */
110 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
111 if (ret_val != 0) {
112 ret_val = IXGBE_ERR_SWFW_SYNC;
113 goto setup_sfp_out;
114 }
115
11afc1b1
PW		 116 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
117 while (data_value != 0xffff) {
118 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
119 IXGBE_WRITE_FLUSH(hw);
120 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
121 }
1479ad4f
PWJ		 122 /* Now restart DSP by setting Restart_AN */
123 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
124 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
aa5aec88
PWJ		 125
126 /* Release the semaphore */
127 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
128 /* Delay obtaining semaphore again to allow FW access */
129 msleep(hw->eeprom.semaphore_delay);
11afc1b1
PW		 130 }
131
132setup_sfp_out:
133 return ret_val;
134}
135
11afc1b1
PW		 136static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
137{
138 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 139
04f165ef 140 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 141
04f165ef
PW		 142 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
143 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
144 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
145 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
146 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
21ce849b 147 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
11afc1b1 148
04f165ef
PW		 149 return 0;
150}
11afc1b1 151
04f165ef
PW		 152/**
153 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
154 * @hw: pointer to hardware structure
155 *
156 * Initialize any function pointers that were not able to be
157 * set during get_invariants because the PHY/SFP type was
158 * not known. Perform the SFP init if necessary.
159 *
160 **/
7b25cdba 161static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
04f165ef
PW		 162{
163 struct ixgbe_mac_info *mac = &hw->mac;
164 struct ixgbe_phy_info *phy = &hw->phy;
165 s32 ret_val = 0;
11afc1b1 166
04f165ef
PW		 167 /* Identify the PHY or SFP module */
168 ret_val = phy->ops.identify(hw);
169
170 /* Setup function pointers based on detected SFP module and speeds */
171 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 172
173 /* If copper media, overwrite with copper function pointers */
174 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
175 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
11afc1b1
PW		 176 mac->ops.get_link_capabilities =
177 &ixgbe_get_copper_link_capabilities_82599;
178 }
179
04f165ef 180 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 181 switch (hw->phy.type) {
182 case ixgbe_phy_tn:
183 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
184 phy->ops.get_firmware_version =
04f165ef 185 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1
PW		 186 break;
187 default:
188 break;
189 }
190
11afc1b1
PW		 191 return ret_val;
192}
193
194/**
195 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
196 * @hw: pointer to hardware structure
197 * @speed: pointer to link speed
198 * @negotiation: true when autoneg or autotry is enabled
199 *
200 * Determines the link capabilities by reading the AUTOC register.
201 **/
7b25cdba
DS		 202static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
203 ixgbe_link_speed *speed,
204 bool *negotiation)
11afc1b1
PW		 205{
206 s32 status = 0;
1eb99d5a 207 u32 autoc = 0;
11afc1b1 208
cb836a97
DS		 209 /* Determine 1G link capabilities off of SFP+ type */
210 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
211 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
212 *speed = IXGBE_LINK_SPEED_1GB_FULL;
213 *negotiation = true;
214 goto out;
215 }
216
1eb99d5a
PW		 217 /*
218 * Determine link capabilities based on the stored value of AUTOC,
219 * which represents EEPROM defaults. If AUTOC value has not been
220 * stored, use the current register value.
221 */
222 if (hw->mac.orig_link_settings_stored)
223 autoc = hw->mac.orig_autoc;
224 else
225 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
226
227 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 228 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
229 *speed = IXGBE_LINK_SPEED_1GB_FULL;
230 *negotiation = false;
231 break;
232
233 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
234 *speed = IXGBE_LINK_SPEED_10GB_FULL;
235 *negotiation = false;
236 break;
237
238 case IXGBE_AUTOC_LMS_1G_AN:
239 *speed = IXGBE_LINK_SPEED_1GB_FULL;
240 *negotiation = true;
241 break;
242
243 case IXGBE_AUTOC_LMS_10G_SERIAL:
244 *speed = IXGBE_LINK_SPEED_10GB_FULL;
245 *negotiation = false;
246 break;
247
248 case IXGBE_AUTOC_LMS_KX4_KX_KR:
249 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
250 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 251 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 252 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 253 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 254 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 255 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 256 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
257 *negotiation = true;
258 break;
259
260 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
261 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 262 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 263 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 264 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 265 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 266 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 267 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
268 *negotiation = true;
269 break;
270
271 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
272 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
273 *negotiation = false;
274 break;
275
276 default:
277 status = IXGBE_ERR_LINK_SETUP;
278 goto out;
279 break;
280 }
281
282 if (hw->phy.multispeed_fiber) {
283 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
284 IXGBE_LINK_SPEED_1GB_FULL;
285 *negotiation = true;
286 }
287
288out:
289 return status;
290}
291
292/**
293 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
294 * @hw: pointer to hardware structure
295 * @speed: pointer to link speed
296 * @autoneg: boolean auto-negotiation value
297 *
298 * Determines the link capabilities by reading the AUTOC register.
299 **/
300static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
301 ixgbe_link_speed *speed,
302 bool *autoneg)
303{
304 s32 status = IXGBE_ERR_LINK_SETUP;
305 u16 speed_ability;
306
307 *speed = 0;
308 *autoneg = true;
309
6b73e10d 310 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
11afc1b1
PW		 311 &speed_ability);
312
313 if (status == 0) {
6b73e10d 314 if (speed_ability & MDIO_SPEED_10G)
11afc1b1 315 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
6b73e10d 316 if (speed_ability & MDIO_PMA_SPEED_1000)
11afc1b1
PW		 317 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
318 }
319
320 return status;
321}
322
323/**
324 * ixgbe_get_media_type_82599 - Get media type
325 * @hw: pointer to hardware structure
326 *
327 * Returns the media type (fiber, copper, backplane)
328 **/
7b25cdba 329static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 330{
331 enum ixgbe_media_type media_type;
332
333 /* Detect if there is a copper PHY attached. */
334 if (hw->phy.type == ixgbe_phy_cu_unknown ||
335 hw->phy.type == ixgbe_phy_tn) {
336 media_type = ixgbe_media_type_copper;
337 goto out;
338 }
339
340 switch (hw->device_id) {
11afc1b1 341 case IXGBE_DEV_ID_82599_KX4:
dbfec662 342 case IXGBE_DEV_ID_82599_KX4_MEZZ:
312eb931 343 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
74757d49 344 case IXGBE_DEV_ID_82599_KR:
1fcf03e6 345 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 346 /* Default device ID is mezzanine card KX/KX4 */
347 media_type = ixgbe_media_type_backplane;
348 break;
349 case IXGBE_DEV_ID_82599_SFP:
38ad1c8e 350 case IXGBE_DEV_ID_82599_SFP_EM:
11afc1b1
PW		 351 media_type = ixgbe_media_type_fiber;
352 break;
8911184f 353 case IXGBE_DEV_ID_82599_CX4:
6b1be199 354 media_type = ixgbe_media_type_cx4;
8911184f 355 break;
11afc1b1
PW		 356 default:
357 media_type = ixgbe_media_type_unknown;
358 break;
359 }
360out:
361 return media_type;
362}
363
364/**
8620a103 365 * ixgbe_start_mac_link_82599 - Setup MAC link settings
11afc1b1 366 * @hw: pointer to hardware structure
8620a103 367 * @autoneg_wait_to_complete: true when waiting for completion is needed
11afc1b1
PW		 368 *
369 * Configures link settings based on values in the ixgbe_hw struct.
370 * Restarts the link. Performs autonegotiation if needed.
371 **/
8620a103
MC		 372s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
373 bool autoneg_wait_to_complete)
11afc1b1
PW		 374{
375 u32 autoc_reg;
376 u32 links_reg;
377 u32 i;
378 s32 status = 0;
379
380 /* Restart link */
381 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
382 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
383 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
384
385 /* Only poll for autoneg to complete if specified to do so */
8620a103 386 if (autoneg_wait_to_complete) {
11afc1b1
PW		 387 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
388 IXGBE_AUTOC_LMS_KX4_KX_KR ||
389 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
390 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
391 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
392 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
393 links_reg = 0; /* Just in case Autoneg time = 0 */
394 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
395 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
396 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
397 break;
398 msleep(100);
399 }
400 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
401 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
402 hw_dbg(hw, "Autoneg did not complete.\n");
403 }
404 }
405 }
406
11afc1b1
PW		 407 /* Add delay to filter out noises during initial link setup */
408 msleep(50);
409
410 return status;
411}
412
61fac744
PW		 413 /**
414 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
415 * @hw: pointer to hardware structure
416 *
417 * The base drivers may require better control over SFP+ module
418 * PHY states. This includes selectively shutting down the Tx
419 * laser on the PHY, effectively halting physical link.
420 **/
421void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
422{
423 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
424
425 /* Disable tx laser; allow 100us to go dark per spec */
426 esdp_reg |= IXGBE_ESDP_SDP3;
427 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
428 IXGBE_WRITE_FLUSH(hw);
429 udelay(100);
430}
431
432/**
433 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
434 * @hw: pointer to hardware structure
435 *
436 * The base drivers may require better control over SFP+ module
437 * PHY states. This includes selectively turning on the Tx
438 * laser on the PHY, effectively starting physical link.
439 **/
440void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
441{
442 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
443
444 /* Enable tx laser; allow 100ms to light up */
445 esdp_reg &= ~IXGBE_ESDP_SDP3;
446 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
447 IXGBE_WRITE_FLUSH(hw);
448 msleep(100);
449}
450
1097cd17
MC		 451/**
452 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
453 * @hw: pointer to hardware structure
454 *
455 * When the driver changes the link speeds that it can support,
456 * it sets autotry_restart to true to indicate that we need to
457 * initiate a new autotry session with the link partner. To do
458 * so, we set the speed then disable and re-enable the tx laser, to
459 * alert the link partner that it also needs to restart autotry on its
460 * end. This is consistent with true clause 37 autoneg, which also
461 * involves a loss of signal.
462 **/
463void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
464{
1097cd17
MC		 465 hw_dbg(hw, "ixgbe_flap_tx_laser_multispeed_fiber\n");
466
467 if (hw->mac.autotry_restart) {
61fac744
PW		 468 ixgbe_disable_tx_laser_multispeed_fiber(hw);
469 ixgbe_enable_tx_laser_multispeed_fiber(hw);
1097cd17
MC		 470 hw->mac.autotry_restart = false;
471 }
472}
473
11afc1b1 474/**
8620a103 475 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
11afc1b1
PW		 476 * @hw: pointer to hardware structure
477 * @speed: new link speed
478 * @autoneg: true if autonegotiation enabled
479 * @autoneg_wait_to_complete: true when waiting for completion is needed
480 *
481 * Set the link speed in the AUTOC register and restarts link.
482 **/
8620a103
MC		 483s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
484 ixgbe_link_speed speed,
485 bool autoneg,
486 bool autoneg_wait_to_complete)
11afc1b1
PW		 487{
488 s32 status = 0;
489 ixgbe_link_speed phy_link_speed;
490 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
491 u32 speedcnt = 0;
492 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
493 bool link_up = false;
494 bool negotiation;
50ac58ba 495 int i;
11afc1b1
PW		 496
497 /* Mask off requested but non-supported speeds */
498 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
499 speed &= phy_link_speed;
500
501 /*
502 * Try each speed one by one, highest priority first. We do this in
503 * software because 10gb fiber doesn't support speed autonegotiation.
504 */
505 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
506 speedcnt++;
507 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
508
50ac58ba
PWJ		 509 /* If we already have link at this speed, just jump out */
510 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
511
512 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
513 goto out;
514
515 /* Set the module link speed */
11afc1b1
PW		 516 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
517 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
1097cd17 518 IXGBE_WRITE_FLUSH(hw);
11afc1b1 519
50ac58ba
PWJ		 520 /* Allow module to change analog characteristics (1G->10G) */
521 msleep(40);
11afc1b1 522
8620a103
MC		 523 status = ixgbe_setup_mac_link_82599(hw,
524 IXGBE_LINK_SPEED_10GB_FULL,
525 autoneg,
526 autoneg_wait_to_complete);
50ac58ba 527 if (status != 0)
c3c74327 528 return status;
50ac58ba
PWJ		 529
530 /* Flap the tx laser if it has not already been done */
1097cd17 531 hw->mac.ops.flap_tx_laser(hw);
50ac58ba 532
cd7e1f0b
DS		 533 /*
534 * Wait for the controller to acquire link. Per IEEE 802.3ap,
535 * Section 73.10.2, we may have to wait up to 500ms if KR is
536 * attempted. 82599 uses the same timing for 10g SFI.
537 */
538
50ac58ba
PWJ		 539 for (i = 0; i < 5; i++) {
540 /* Wait for the link partner to also set speed */
541 msleep(100);
542
543 /* If we have link, just jump out */
544 hw->mac.ops.check_link(hw, &phy_link_speed,
545 &link_up, false);
546 if (link_up)
547 goto out;
548 }
11afc1b1
PW		 549 }
550
551 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
552 speedcnt++;
553 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
554 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
555
50ac58ba
PWJ		 556 /* If we already have link at this speed, just jump out */
557 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
558
559 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
560 goto out;
561
562 /* Set the module link speed */
11afc1b1
PW		 563 esdp_reg &= ~IXGBE_ESDP_SDP5;
564 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
565 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
1097cd17 566 IXGBE_WRITE_FLUSH(hw);
11afc1b1 567
50ac58ba
PWJ		 568 /* Allow module to change analog characteristics (10G->1G) */
569 msleep(40);
11afc1b1 570
8620a103 571 status = ixgbe_setup_mac_link_82599(hw,
50ac58ba
PWJ		 572 IXGBE_LINK_SPEED_1GB_FULL,
573 autoneg,
574 autoneg_wait_to_complete);
575 if (status != 0)
c3c74327 576 return status;
50ac58ba
PWJ		 577
578 /* Flap the tx laser if it has not already been done */
1097cd17 579 hw->mac.ops.flap_tx_laser(hw);
50ac58ba
PWJ		 580
581 /* Wait for the link partner to also set speed */
582 msleep(100);
11afc1b1
PW		 583
584 /* If we have link, just jump out */
585 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
586 if (link_up)
587 goto out;
588 }
589
590 /*
591 * We didn't get link. Configure back to the highest speed we tried,
592 * (if there was more than one). We call ourselves back with just the
593 * single highest speed that the user requested.
594 */
595 if (speedcnt > 1)
8620a103
MC		 596 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
597 highest_link_speed,
598 autoneg,
599 autoneg_wait_to_complete);
11afc1b1
PW		 600
601out:
c3c74327
MC		 602 /* Set autoneg_advertised value based on input link speed */
603 hw->phy.autoneg_advertised = 0;
604
605 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
606 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
607
608 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
609 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
610
11afc1b1
PW		 611 return status;
612}
613
cd7e1f0b
DS		 614/**
615 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
616 * @hw: pointer to hardware structure
617 * @speed: new link speed
618 * @autoneg: true if autonegotiation enabled
619 * @autoneg_wait_to_complete: true when waiting for completion is needed
620 *
621 * Implements the Intel SmartSpeed algorithm.
622 **/
623static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
624 ixgbe_link_speed speed, bool autoneg,
625 bool autoneg_wait_to_complete)
626{
627 s32 status = 0;
628 ixgbe_link_speed link_speed;
629 s32 i, j;
630 bool link_up = false;
631 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
c4ee6a53 632 struct ixgbe_adapter *adapter = hw->back;
cd7e1f0b
DS		 633
634 hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n");
635
636 /* Set autoneg_advertised value based on input link speed */
637 hw->phy.autoneg_advertised = 0;
638
639 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
640 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
641
642 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
643 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
644
645 if (speed & IXGBE_LINK_SPEED_100_FULL)
646 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
647
648 /*
649 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
650 * autoneg advertisement if link is unable to be established at the
651 * highest negotiated rate. This can sometimes happen due to integrity
652 * issues with the physical media connection.
653 */
654
655 /* First, try to get link with full advertisement */
656 hw->phy.smart_speed_active = false;
657 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
658 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
659 autoneg_wait_to_complete);
660 if (status)
661 goto out;
662
663 /*
664 * Wait for the controller to acquire link. Per IEEE 802.3ap,
665 * Section 73.10.2, we may have to wait up to 500ms if KR is
666 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
667 * Table 9 in the AN MAS.
668 */
669 for (i = 0; i < 5; i++) {
670 mdelay(100);
671
672 /* If we have link, just jump out */
673 hw->mac.ops.check_link(hw, &link_speed,
674 &link_up, false);
675 if (link_up)
676 goto out;
677 }
678 }
679
680 /*
681 * We didn't get link. If we advertised KR plus one of KX4/KX
682 * (or BX4/BX), then disable KR and try again.
683 */
684 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
685 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
686 goto out;
687
688 /* Turn SmartSpeed on to disable KR support */
689 hw->phy.smart_speed_active = true;
690 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
691 autoneg_wait_to_complete);
692 if (status)
693 goto out;
694
695 /*
696 * Wait for the controller to acquire link. 600ms will allow for
697 * the AN link_fail_inhibit_timer as well for multiple cycles of
698 * parallel detect, both 10g and 1g. This allows for the maximum
699 * connect attempts as defined in the AN MAS table 73-7.
700 */
701 for (i = 0; i < 6; i++) {
702 mdelay(100);
703
704 /* If we have link, just jump out */
705 hw->mac.ops.check_link(hw, &link_speed,
706 &link_up, false);
707 if (link_up)
708 goto out;
709 }
710
711 /* We didn't get link. Turn SmartSpeed back off. */
712 hw->phy.smart_speed_active = false;
713 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
714 autoneg_wait_to_complete);
715
716out:
c4ee6a53 717 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
396e799c 718 e_info(hw, "Smartspeed has downgraded the link speed from "
849c4542 719 "the maximum advertised\n");
cd7e1f0b
DS		 720 return status;
721}
722
11afc1b1 723/**
8620a103 724 * ixgbe_setup_mac_link_82599 - Set MAC link speed
11afc1b1
PW		 725 * @hw: pointer to hardware structure
726 * @speed: new link speed
727 * @autoneg: true if autonegotiation enabled
728 * @autoneg_wait_to_complete: true when waiting for completion is needed
729 *
730 * Set the link speed in the AUTOC register and restarts link.
731 **/
8620a103
MC		 732s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
733 ixgbe_link_speed speed, bool autoneg,
734 bool autoneg_wait_to_complete)
11afc1b1
PW		 735{
736 s32 status = 0;
737 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
738 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
50ac58ba 739 u32 start_autoc = autoc;
1eb99d5a 740 u32 orig_autoc = 0;
11afc1b1
PW		 741 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
742 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
743 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
744 u32 links_reg;
745 u32 i;
746 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
747
748 /* Check to see if speed passed in is supported. */
749 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
750 speed &= link_capabilities;
751
50ac58ba
PWJ		 752 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
753 status = IXGBE_ERR_LINK_SETUP;
754 goto out;
755 }
756
1eb99d5a
PW		 757 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
758 if (hw->mac.orig_link_settings_stored)
759 orig_autoc = hw->mac.orig_autoc;
760 else
761 orig_autoc = autoc;
762
763
50ac58ba
PWJ		 764 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
765 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
766 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
11afc1b1
PW		 767 /* Set KX4/KX/KR support according to speed requested */
768 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
769 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1eb99d5a 770 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 771 autoc |= IXGBE_AUTOC_KX4_SUPP;
cd7e1f0b
DS		 772 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
773 (hw->phy.smart_speed_active == false))
11afc1b1
PW		 774 autoc |= IXGBE_AUTOC_KR_SUPP;
775 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
776 autoc |= IXGBE_AUTOC_KX_SUPP;
777 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
778 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
779 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
780 /* Switch from 1G SFI to 10G SFI if requested */
781 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
782 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
783 autoc &= ~IXGBE_AUTOC_LMS_MASK;
784 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
785 }
786 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
787 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
788 /* Switch from 10G SFI to 1G SFI if requested */
789 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
790 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
791 autoc &= ~IXGBE_AUTOC_LMS_MASK;
792 if (autoneg)
793 autoc |= IXGBE_AUTOC_LMS_1G_AN;
794 else
795 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
796 }
797 }
798
50ac58ba 799 if (autoc != start_autoc) {
11afc1b1
PW		 800 /* Restart link */
801 autoc |= IXGBE_AUTOC_AN_RESTART;
802 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
803
804 /* Only poll for autoneg to complete if specified to do so */
805 if (autoneg_wait_to_complete) {
806 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
807 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
808 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
809 links_reg = 0; /*Just in case Autoneg time=0*/
810 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
811 links_reg =
812 IXGBE_READ_REG(hw, IXGBE_LINKS);
813 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
814 break;
815 msleep(100);
816 }
817 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
818 status =
819 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
820 hw_dbg(hw, "Autoneg did not "
821 "complete.\n");
822 }
823 }
824 }
825
11afc1b1
PW		 826 /* Add delay to filter out noises during initial link setup */
827 msleep(50);
828 }
829
50ac58ba 830out:
11afc1b1
PW		 831 return status;
832}
833
834/**
8620a103 835 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
11afc1b1
PW		 836 * @hw: pointer to hardware structure
837 * @speed: new link speed
838 * @autoneg: true if autonegotiation enabled
839 * @autoneg_wait_to_complete: true if waiting is needed to complete
840 *
841 * Restarts link on PHY and MAC based on settings passed in.
842 **/
8620a103
MC		 843static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
844 ixgbe_link_speed speed,
845 bool autoneg,
846 bool autoneg_wait_to_complete)
11afc1b1
PW		 847{
848 s32 status;
849
850 /* Setup the PHY according to input speed */
851 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
852 autoneg_wait_to_complete);
853 /* Set up MAC */
8620a103 854 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
11afc1b1
PW		 855
856 return status;
857}
858
859/**
860 * ixgbe_reset_hw_82599 - Perform hardware reset
861 * @hw: pointer to hardware structure
862 *
863 * Resets the hardware by resetting the transmit and receive units, masks
864 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
865 * reset.
866 **/
7b25cdba 867static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 868{
869 s32 status = 0;
c9205697 870 u32 ctrl;
11afc1b1
PW		 871 u32 i;
872 u32 autoc;
873 u32 autoc2;
874
875 /* Call adapter stop to disable tx/rx and clear interrupts */
876 hw->mac.ops.stop_adapter(hw);
877
553b4497 878 /* PHY ops must be identified and initialized prior to reset */
04f165ef 879
553b4497
PW		 880 /* Init PHY and function pointers, perform SFP setup */
881 status = hw->phy.ops.init(hw);
04f165ef 882
553b4497
PW		 883 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
884 goto reset_hw_out;
04f165ef 885
553b4497
PW		 886 /* Setup SFP module if there is one present. */
887 if (hw->phy.sfp_setup_needed) {
888 status = hw->mac.ops.setup_sfp(hw);
889 hw->phy.sfp_setup_needed = false;
04f165ef 890 }
11afc1b1 891
553b4497
PW		 892 /* Reset PHY */
893 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
894 hw->phy.ops.reset(hw);
895
11afc1b1
PW		 896 /*
897 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
898 * access and verify no pending requests before reset
899 */
04f165ef
PW		 900 status = ixgbe_disable_pcie_master(hw);
901 if (status != 0) {
11afc1b1
PW		 902 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
903 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
904 }
905
906 /*
907 * Issue global reset to the MAC. This needs to be a SW reset.
908 * If link reset is used, it might reset the MAC when mng is using it
909 */
910 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
911 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
912 IXGBE_WRITE_FLUSH(hw);
913
914 /* Poll for reset bit to self-clear indicating reset is complete */
915 for (i = 0; i < 10; i++) {
916 udelay(1);
917 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
918 if (!(ctrl & IXGBE_CTRL_RST))
919 break;
920 }
921 if (ctrl & IXGBE_CTRL_RST) {
922 status = IXGBE_ERR_RESET_FAILED;
923 hw_dbg(hw, "Reset polling failed to complete.\n");
924 }
11afc1b1
PW		 925
926 msleep(50);
927
11afc1b1
PW		 928 /*
929 * Store the original AUTOC/AUTOC2 values if they have not been
930 * stored off yet. Otherwise restore the stored original
931 * values since the reset operation sets back to defaults.
932 */
933 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
934 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
935 if (hw->mac.orig_link_settings_stored == false) {
936 hw->mac.orig_autoc = autoc;
937 hw->mac.orig_autoc2 = autoc2;
938 hw->mac.orig_link_settings_stored = true;
4df10466 939 } else {
11afc1b1
PW		 940 if (autoc != hw->mac.orig_autoc)
941 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
942 IXGBE_AUTOC_AN_RESTART));
943
944 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
945 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
946 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
947 autoc2 |= (hw->mac.orig_autoc2 &
948 IXGBE_AUTOC2_UPPER_MASK);
949 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
950 }
951 }
952
aca6bee7
WJP		 953 /*
954 * Store MAC address from RAR0, clear receive address registers, and
955 * clear the multicast table. Also reset num_rar_entries to 128,
956 * since we modify this value when programming the SAN MAC address.
957 */
958 hw->mac.num_rar_entries = 128;
959 hw->mac.ops.init_rx_addrs(hw);
960
11afc1b1
PW		 961 /* Store the permanent mac address */
962 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
963
0365e6e4
PW		 964 /* Store the permanent SAN mac address */
965 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
966
aca6bee7
WJP		 967 /* Add the SAN MAC address to the RAR only if it's a valid address */
968 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
969 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
970 hw->mac.san_addr, 0, IXGBE_RAH_AV);
971
972 /* Reserve the last RAR for the SAN MAC address */
973 hw->mac.num_rar_entries--;
974 }
975
383ff34b
YZ		 976 /* Store the alternative WWNN/WWPN prefix */
977 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
978 &hw->mac.wwpn_prefix);
979
04f165ef 980reset_hw_out:
11afc1b1
PW		 981 return status;
982}
983
ffff4772
PWJ		 984/**
985 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
986 * @hw: pointer to hardware structure
987 **/
988s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
989{
990 int i;
991 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
992 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
993
994 /*
995 * Before starting reinitialization process,
996 * FDIRCMD.CMD must be zero.
997 */
998 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
999 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1000 IXGBE_FDIRCMD_CMD_MASK))
1001 break;
1002 udelay(10);
1003 }
1004 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1005 hw_dbg(hw ,"Flow Director previous command isn't complete, "
d6dbee86 1006 "aborting table re-initialization.\n");
ffff4772
PWJ		 1007 return IXGBE_ERR_FDIR_REINIT_FAILED;
1008 }
1009
1010 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1011 IXGBE_WRITE_FLUSH(hw);
1012 /*
1013 * 82599 adapters flow director init flow cannot be restarted,
1014 * Workaround 82599 silicon errata by performing the following steps
1015 * before re-writing the FDIRCTRL control register with the same value.
1016 * - write 1 to bit 8 of FDIRCMD register &
1017 * - write 0 to bit 8 of FDIRCMD register
1018 */
1019 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1020 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1021 IXGBE_FDIRCMD_CLEARHT));
1022 IXGBE_WRITE_FLUSH(hw);
1023 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1024 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1025 ~IXGBE_FDIRCMD_CLEARHT));
1026 IXGBE_WRITE_FLUSH(hw);
1027 /*
1028 * Clear FDIR Hash register to clear any leftover hashes
1029 * waiting to be programmed.
1030 */
1031 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1032 IXGBE_WRITE_FLUSH(hw);
1033
1034 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1035 IXGBE_WRITE_FLUSH(hw);
1036
1037 /* Poll init-done after we write FDIRCTRL register */
1038 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1039 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1040 IXGBE_FDIRCTRL_INIT_DONE)
1041 break;
1042 udelay(10);
1043 }
1044 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1045 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1046 return IXGBE_ERR_FDIR_REINIT_FAILED;
1047 }
1048
1049 /* Clear FDIR statistics registers (read to clear) */
1050 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1051 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1052 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1053 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1054 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1055
1056 return 0;
1057}
1058
1059/**
1060 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1061 * @hw: pointer to hardware structure
1062 * @pballoc: which mode to allocate filters with
1063 **/
1064s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1065{
1066 u32 fdirctrl = 0;
1067 u32 pbsize;
1068 int i;
1069
1070 /*
1071 * Before enabling Flow Director, the Rx Packet Buffer size
1072 * must be reduced. The new value is the current size minus
1073 * flow director memory usage size.
1074 */
1075 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1076 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1077 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1078
1079 /*
1080 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1081 * intialized to zero for non DCB mode otherwise actual total RX PB
1082 * would be bigger than programmed and filter space would run into
1083 * the PB 0 region.
1084 */
1085 for (i = 1; i < 8; i++)
1086 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1087
1088 /* Send interrupt when 64 filters are left */
1089 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1090
1091 /* Set the maximum length per hash bucket to 0xA filters */
1092 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1093
1094 switch (pballoc) {
1095 case IXGBE_FDIR_PBALLOC_64K:
1096 /* 8k - 1 signature filters */
1097 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1098 break;
1099 case IXGBE_FDIR_PBALLOC_128K:
1100 /* 16k - 1 signature filters */
1101 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1102 break;
1103 case IXGBE_FDIR_PBALLOC_256K:
1104 /* 32k - 1 signature filters */
1105 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1106 break;
1107 default:
1108 /* bad value */
1109 return IXGBE_ERR_CONFIG;
1110 };
1111
1112 /* Move the flexible bytes to use the ethertype - shift 6 words */
1113 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1114
1115 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1116
1117 /* Prime the keys for hashing */
1118 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1119 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1120 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1121 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1122
1123 /*
1124 * Poll init-done after we write the register. Estimated times:
1125 * 10G: PBALLOC = 11b, timing is 60us
1126 * 1G: PBALLOC = 11b, timing is 600us
1127 * 100M: PBALLOC = 11b, timing is 6ms
1128 *
1129 * Multiple these timings by 4 if under full Rx load
1130 *
1131 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1132 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1133 * this might not finish in our poll time, but we can live with that
1134 * for now.
1135 */
1136 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1137 IXGBE_WRITE_FLUSH(hw);
1138 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1139 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1140 IXGBE_FDIRCTRL_INIT_DONE)
1141 break;
1142 msleep(1);
1143 }
1144 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1145 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1146
1147 return 0;
1148}
1149
1150/**
1151 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1152 * @hw: pointer to hardware structure
1153 * @pballoc: which mode to allocate filters with
1154 **/
1155s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1156{
1157 u32 fdirctrl = 0;
1158 u32 pbsize;
1159 int i;
1160
1161 /*
1162 * Before enabling Flow Director, the Rx Packet Buffer size
1163 * must be reduced. The new value is the current size minus
1164 * flow director memory usage size.
1165 */
1166 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1167 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1168 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1169
1170 /*
1171 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1172 * intialized to zero for non DCB mode otherwise actual total RX PB
1173 * would be bigger than programmed and filter space would run into
1174 * the PB 0 region.
1175 */
1176 for (i = 1; i < 8; i++)
1177 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1178
1179 /* Send interrupt when 64 filters are left */
1180 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1181
9a713e7c
PW		 1182 /* Initialize the drop queue to Rx queue 127 */
1183 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1184
ffff4772
PWJ		 1185 switch (pballoc) {
1186 case IXGBE_FDIR_PBALLOC_64K:
1187 /* 2k - 1 perfect filters */
1188 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1189 break;
1190 case IXGBE_FDIR_PBALLOC_128K:
1191 /* 4k - 1 perfect filters */
1192 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1193 break;
1194 case IXGBE_FDIR_PBALLOC_256K:
1195 /* 8k - 1 perfect filters */
1196 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1197 break;
1198 default:
1199 /* bad value */
1200 return IXGBE_ERR_CONFIG;
1201 };
1202
1203 /* Turn perfect match filtering on */
1204 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1205 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1206
1207 /* Move the flexible bytes to use the ethertype - shift 6 words */
1208 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1209
1210 /* Prime the keys for hashing */
1211 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1212 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1213 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1214 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1215
1216 /*
1217 * Poll init-done after we write the register. Estimated times:
1218 * 10G: PBALLOC = 11b, timing is 60us
1219 * 1G: PBALLOC = 11b, timing is 600us
1220 * 100M: PBALLOC = 11b, timing is 6ms
1221 *
1222 * Multiple these timings by 4 if under full Rx load
1223 *
1224 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1225 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1226 * this might not finish in our poll time, but we can live with that
1227 * for now.
1228 */
1229
1230 /* Set the maximum length per hash bucket to 0xA filters */
1231 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1232
1233 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1234 IXGBE_WRITE_FLUSH(hw);
1235 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1236 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1237 IXGBE_FDIRCTRL_INIT_DONE)
1238 break;
1239 msleep(1);
1240 }
1241 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1242 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1243
1244 return 0;
1245}
1246
1247
1248/**
1249 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1250 * @stream: input bitstream to compute the hash on
1251 * @key: 32-bit hash key
1252 **/
7b25cdba
DS		 1253static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1254 u32 key)
ffff4772
PWJ		 1255{
1256 /*
1257 * The algorithm is as follows:
1258 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1259 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1260 * and A[n] x B[n] is bitwise AND between same length strings
1261 *
1262 * K[n] is 16 bits, defined as:
1263 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1264 * for n modulo 32 < 15, K[n] =
1265 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1266 *
1267 * S[n] is 16 bits, defined as:
1268 * for n >= 15, S[n] = S[n:n - 15]
1269 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1270 *
1271 * To simplify for programming, the algorithm is implemented
1272 * in software this way:
1273 *
1274 * Key[31:0], Stream[335:0]
1275 *
1276 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1277 * int_key[350:0] = tmp_key[351:1]
1278 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1279 *
1280 * hash[15:0] = 0;
1281 * for (i = 0; i < 351; i++) {
1282 * if (int_key[i])
1283 * hash ^= int_stream[(i + 15):i];
1284 * }
1285 */
1286
1287 union {
1288 u64 fill[6];
1289 u32 key[11];
1290 u8 key_stream[44];
1291 } tmp_key;
1292
1293 u8 *stream = (u8 *)atr_input;
1294 u8 int_key[44]; /* upper-most bit unused */
1295 u8 hash_str[46]; /* upper-most 2 bits unused */
1296 u16 hash_result = 0;
1297 int i, j, k, h;
1298
1299 /*
1300 * Initialize the fill member to prevent warnings
1301 * on some compilers
1302 */
1303 tmp_key.fill[0] = 0;
1304
1305 /* First load the temporary key stream */
1306 for (i = 0; i < 6; i++) {
1307 u64 fillkey = ((u64)key << 32) | key;
1308 tmp_key.fill[i] = fillkey;
1309 }
1310
1311 /*
1312 * Set the interim key for the hashing. Bit 352 is unused, so we must
1313 * shift and compensate when building the key.
1314 */
1315
1316 int_key[0] = tmp_key.key_stream[0] >> 1;
1317 for (i = 1, j = 0; i < 44; i++) {
1318 unsigned int this_key = tmp_key.key_stream[j] << 7;
1319 j++;
1320 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1321 }
1322
1323 /*
1324 * Set the interim bit string for the hashing. Bits 368 and 367 are
1325 * unused, so shift and compensate when building the string.
1326 */
1327 hash_str[0] = (stream[40] & 0x7f) >> 1;
1328 for (i = 1, j = 40; i < 46; i++) {
1329 unsigned int this_str = stream[j] << 7;
1330 j++;
1331 if (j > 41)
1332 j = 0;
1333 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1334 }
1335
1336 /*
1337 * Now compute the hash. i is the index into hash_str, j is into our
1338 * key stream, k is counting the number of bits, and h interates within
1339 * each byte.
1340 */
1341 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1342 for (h = 0; h < 8 && k < 351; h++, k++) {
1343 if (int_key[j] & (1 << h)) {
1344 /*
1345 * Key bit is set, XOR in the current 16-bit
1346 * string. Example of processing:
1347 * h = 0,
1348 * tmp = (hash_str[i - 2] & 0 << 16) |
1349 * (hash_str[i - 1] & 0xff << 8) |
1350 * (hash_str[i] & 0xff >> 0)
1351 * So tmp = hash_str[15 + k:k], since the
1352 * i + 2 clause rolls off the 16-bit value
1353 * h = 7,
1354 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1355 * (hash_str[i - 1] & 0xff << 1) |
1356 * (hash_str[i] & 0x80 >> 7)
1357 */
1358 int tmp = (hash_str[i] >> h);
1359 tmp |= (hash_str[i - 1] << (8 - h));
1360 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1361 << (16 - h);
1362 hash_result ^= (u16)tmp;
1363 }
1364 }
1365 }
1366
1367 return hash_result;
1368}
1369
1370/**
1371 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1372 * @input: input stream to modify
1373 * @vlan: the VLAN id to load
1374 **/
1375s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1376{
1377 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1378 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1379
1380 return 0;
1381}
1382
1383/**
1384 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1385 * @input: input stream to modify
1386 * @src_addr: the IP address to load
1387 **/
1388s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1389{
1390 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1391 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1392 (src_addr >> 16) & 0xff;
1393 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1394 (src_addr >> 8) & 0xff;
1395 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1396
1397 return 0;
1398}
1399
1400/**
1401 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1402 * @input: input stream to modify
1403 * @dst_addr: the IP address to load
1404 **/
1405s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1406{
1407 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1408 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1409 (dst_addr >> 16) & 0xff;
1410 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1411 (dst_addr >> 8) & 0xff;
1412 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1413
1414 return 0;
1415}
1416
1417/**
1418 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1419 * @input: input stream to modify
1420 * @src_addr_1: the first 4 bytes of the IP address to load
1421 * @src_addr_2: the second 4 bytes of the IP address to load
1422 * @src_addr_3: the third 4 bytes of the IP address to load
1423 * @src_addr_4: the fourth 4 bytes of the IP address to load
1424 **/
1425s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
9a713e7c
PW		 1426 u32 src_addr_1, u32 src_addr_2,
1427 u32 src_addr_3, u32 src_addr_4)
ffff4772
PWJ		 1428{
1429 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1430 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1431 (src_addr_4 >> 8) & 0xff;
1432 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1433 (src_addr_4 >> 16) & 0xff;
1434 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1435
1436 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1437 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1438 (src_addr_3 >> 8) & 0xff;
1439 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1440 (src_addr_3 >> 16) & 0xff;
1441 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1442
1443 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1444 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1445 (src_addr_2 >> 8) & 0xff;
1446 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1447 (src_addr_2 >> 16) & 0xff;
1448 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1449
1450 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1451 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1452 (src_addr_1 >> 8) & 0xff;
1453 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1454 (src_addr_1 >> 16) & 0xff;
1455 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1456
1457 return 0;
1458}
1459
1460/**
1461 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1462 * @input: input stream to modify
1463 * @dst_addr_1: the first 4 bytes of the IP address to load
1464 * @dst_addr_2: the second 4 bytes of the IP address to load
1465 * @dst_addr_3: the third 4 bytes of the IP address to load
1466 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1467 **/
1468s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
9a713e7c
PW		 1469 u32 dst_addr_1, u32 dst_addr_2,
1470 u32 dst_addr_3, u32 dst_addr_4)
ffff4772
PWJ		 1471{
1472 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1473 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1474 (dst_addr_4 >> 8) & 0xff;
1475 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1476 (dst_addr_4 >> 16) & 0xff;
1477 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1478
1479 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1480 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1481 (dst_addr_3 >> 8) & 0xff;
1482 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1483 (dst_addr_3 >> 16) & 0xff;
1484 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1485
1486 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1487 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1488 (dst_addr_2 >> 8) & 0xff;
1489 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1490 (dst_addr_2 >> 16) & 0xff;
1491 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1492
1493 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1494 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1495 (dst_addr_1 >> 8) & 0xff;
1496 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1497 (dst_addr_1 >> 16) & 0xff;
1498 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1499
1500 return 0;
1501}
1502
1503/**
1504 * ixgbe_atr_set_src_port_82599 - Sets the source port
1505 * @input: input stream to modify
1506 * @src_port: the source port to load
1507 **/
1508s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1509{
1510 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1511 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1512
1513 return 0;
1514}
1515
1516/**
1517 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1518 * @input: input stream to modify
1519 * @dst_port: the destination port to load
1520 **/
1521s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1522{
1523 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1524 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1525
1526 return 0;
1527}
1528
1529/**
1530 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1531 * @input: input stream to modify
1532 * @flex_bytes: the flexible bytes to load
1533 **/
1534s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1535{
1536 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1537 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1538
1539 return 0;
1540}
1541
1542/**
1543 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1544 * @input: input stream to modify
1545 * @vm_pool: the Virtual Machine pool to load
1546 **/
7b25cdba 1547s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
9a713e7c 1548 u8 vm_pool)
ffff4772
PWJ		 1549{
1550 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1551
1552 return 0;
1553}
1554
1555/**
1556 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1557 * @input: input stream to modify
1558 * @l4type: the layer 4 type value to load
1559 **/
1560s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1561{
1562 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1563
1564 return 0;
1565}
1566
1567/**
1568 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1569 * @input: input stream to search
1570 * @vlan: the VLAN id to load
1571 **/
9a713e7c 1572static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan)
ffff4772
PWJ		 1573{
1574 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1575 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1576
1577 return 0;
1578}
1579
1580/**
1581 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1582 * @input: input stream to search
1583 * @src_addr: the IP address to load
1584 **/
7b25cdba
DS		 1585static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1586 u32 *src_addr)
ffff4772
PWJ		 1587{
1588 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1589 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1590 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1591 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1592
1593 return 0;
1594}
1595
1596/**
1597 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1598 * @input: input stream to search
1599 * @dst_addr: the IP address to load
1600 **/
7b25cdba
DS		 1601static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1602 u32 *dst_addr)
ffff4772
PWJ		 1603{
1604 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1605 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1606 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1607 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1608
1609 return 0;
1610}
1611
1612/**
1613 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1614 * @input: input stream to search
1615 * @src_addr_1: the first 4 bytes of the IP address to load
1616 * @src_addr_2: the second 4 bytes of the IP address to load
1617 * @src_addr_3: the third 4 bytes of the IP address to load
1618 * @src_addr_4: the fourth 4 bytes of the IP address to load
1619 **/
7b25cdba
DS		 1620static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1621 u32 *src_addr_1, u32 *src_addr_2,
1622 u32 *src_addr_3, u32 *src_addr_4)
ffff4772
PWJ		 1623{
1624 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1625 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1626 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1627 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1628
1629 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1630 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1631 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1632 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1633
1634 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1635 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1636 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1637 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1638
1639 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1640 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1641 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1642 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1643
1644 return 0;
1645}
1646
1647/**
1648 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1649 * @input: input stream to search
1650 * @dst_addr_1: the first 4 bytes of the IP address to load
1651 * @dst_addr_2: the second 4 bytes of the IP address to load
1652 * @dst_addr_3: the third 4 bytes of the IP address to load
1653 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1654 **/
1655s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
7b25cdba
DS		 1656 u32 *dst_addr_1, u32 *dst_addr_2,
1657 u32 *dst_addr_3, u32 *dst_addr_4)
ffff4772
PWJ		 1658{
1659 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
1660 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
1661 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
1662 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
1663
1664 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
1665 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
1666 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
1667 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
1668
1669 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
1670 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1671 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1672 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1673
1674 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1675 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1676 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1677 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1678
1679 return 0;
1680}
1681
1682/**
1683 * ixgbe_atr_get_src_port_82599 - Gets the source port
1684 * @input: input stream to modify
1685 * @src_port: the source port to load
1686 *
1687 * Even though the input is given in big-endian, the FDIRPORT registers
1688 * expect the ports to be programmed in little-endian. Hence the need to swap
1689 * endianness when retrieving the data. This can be confusing since the
1690 * internal hash engine expects it to be big-endian.
1691 **/
7b25cdba
DS		 1692static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1693 u16 *src_port)
ffff4772
PWJ		 1694{
1695 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1696 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1697
1698 return 0;
1699}
1700
1701/**
1702 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1703 * @input: input stream to modify
1704 * @dst_port: the destination port to load
1705 *
1706 * Even though the input is given in big-endian, the FDIRPORT registers
1707 * expect the ports to be programmed in little-endian. Hence the need to swap
1708 * endianness when retrieving the data. This can be confusing since the
1709 * internal hash engine expects it to be big-endian.
1710 **/
7b25cdba
DS		 1711static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1712 u16 *dst_port)
ffff4772
PWJ		 1713{
1714 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1715 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1716
1717 return 0;
1718}
1719
1720/**
1721 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1722 * @input: input stream to modify
1723 * @flex_bytes: the flexible bytes to load
1724 **/
7b25cdba
DS		 1725static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1726 u16 *flex_byte)
ffff4772
PWJ		 1727{
1728 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1729 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1730
1731 return 0;
1732}
1733
1734/**
1735 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
1736 * @input: input stream to modify
1737 * @vm_pool: the Virtual Machine pool to load
1738 **/
7b25cdba
DS		 1739s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
1740 u8 *vm_pool)
ffff4772
PWJ		 1741{
1742 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
1743
1744 return 0;
1745}
1746
1747/**
1748 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
1749 * @input: input stream to modify
1750 * @l4type: the layer 4 type value to load
1751 **/
7b25cdba
DS		 1752static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
1753 u8 *l4type)
ffff4772
PWJ		 1754{
1755 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
1756
1757 return 0;
1758}
1759
1760/**
1761 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1762 * @hw: pointer to hardware structure
1763 * @stream: input bitstream
1764 * @queue: queue index to direct traffic to
1765 **/
1766s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1767 struct ixgbe_atr_input *input,
1768 u8 queue)
1769{
1770 u64 fdirhashcmd;
1771 u64 fdircmd;
1772 u32 fdirhash;
1773 u16 bucket_hash, sig_hash;
1774 u8 l4type;
1775
1776 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1777 IXGBE_ATR_BUCKET_HASH_KEY);
1778
1779 /* bucket_hash is only 15 bits */
1780 bucket_hash &= IXGBE_ATR_HASH_MASK;
1781
1782 sig_hash = ixgbe_atr_compute_hash_82599(input,
1783 IXGBE_ATR_SIGNATURE_HASH_KEY);
1784
1785 /* Get the l4type in order to program FDIRCMD properly */
1786 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
1787 ixgbe_atr_get_l4type_82599(input, &l4type);
1788
1789 /*
1790 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1791 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1792 */
1793 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1794
1795 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1796 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
1797
1798 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1799 case IXGBE_ATR_L4TYPE_TCP:
1800 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1801 break;
1802 case IXGBE_ATR_L4TYPE_UDP:
1803 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1804 break;
1805 case IXGBE_ATR_L4TYPE_SCTP:
1806 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1807 break;
1808 default:
1809 hw_dbg(hw, "Error on l4type input\n");
1810 return IXGBE_ERR_CONFIG;
1811 }
1812
1813 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
1814 fdircmd |= IXGBE_FDIRCMD_IPV6;
1815
1816 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
1817 fdirhashcmd = ((fdircmd << 32) | fdirhash);
1818
1819 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1820
1821 return 0;
1822}
1823
1824/**
1825 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1826 * @hw: pointer to hardware structure
1827 * @input: input bitstream
9a713e7c
PW		 1828 * @input_masks: bitwise masks for relevant fields
1829 * @soft_id: software index into the silicon hash tables for filter storage
ffff4772
PWJ		 1830 * @queue: queue index to direct traffic to
1831 *
1832 * Note that the caller to this function must lock before calling, since the
1833 * hardware writes must be protected from one another.
1834 **/
1835s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
9a713e7c
PW		 1836 struct ixgbe_atr_input *input,
1837 struct ixgbe_atr_input_masks *input_masks,
1838 u16 soft_id, u8 queue)
ffff4772
PWJ		 1839{
1840 u32 fdircmd = 0;
1841 u32 fdirhash;
9a713e7c 1842 u32 src_ipv4 = 0, dst_ipv4 = 0;
ffff4772
PWJ		 1843 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
1844 u16 src_port, dst_port, vlan_id, flex_bytes;
1845 u16 bucket_hash;
1846 u8 l4type;
9a713e7c 1847 u8 fdirm = 0;
ffff4772
PWJ		 1848
1849 /* Get our input values */
1850 ixgbe_atr_get_l4type_82599(input, &l4type);
1851
1852 /*
1853 * Check l4type formatting, and bail out before we touch the hardware
1854 * if there's a configuration issue
1855 */
1856 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1857 case IXGBE_ATR_L4TYPE_TCP:
1858 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1859 break;
1860 case IXGBE_ATR_L4TYPE_UDP:
1861 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1862 break;
1863 case IXGBE_ATR_L4TYPE_SCTP:
1864 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1865 break;
1866 default:
1867 hw_dbg(hw, "Error on l4type input\n");
1868 return IXGBE_ERR_CONFIG;
1869 }
1870
1871 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1872 IXGBE_ATR_BUCKET_HASH_KEY);
1873
1874 /* bucket_hash is only 15 bits */
1875 bucket_hash &= IXGBE_ATR_HASH_MASK;
1876
1877 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
1878 ixgbe_atr_get_src_port_82599(input, &src_port);
1879 ixgbe_atr_get_dst_port_82599(input, &dst_port);
1880 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
1881
1882 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1883
1884 /* Now figure out if we're IPv4 or IPv6 */
1885 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
1886 /* IPv6 */
1887 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
1888 &src_ipv6_3, &src_ipv6_4);
1889
1890 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
1891 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
1892 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
1893 /* The last 4 bytes is the same register as IPv4 */
1894 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
1895
1896 fdircmd |= IXGBE_FDIRCMD_IPV6;
1897 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
1898 } else {
1899 /* IPv4 */
1900 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
1901 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
ffff4772
PWJ		 1902 }
1903
1904 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
1905 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
1906
1907 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
1908 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
1909 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
9a713e7c
PW		 1910 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
1911
1912 /*
1913 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1914 * are zero, then assume a full mask for that field. Also assume that
1915 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1916 * cannot be masked out in this implementation.
1917 *
1918 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1919 * point in time.
1920 */
1921 if (src_ipv4 == 0)
1922 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xffffffff);
1923 else
1924 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
1925
1926 if (dst_ipv4 == 0)
1927 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xffffffff);
1928 else
1929 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask);
1930
1931 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1932 case IXGBE_ATR_L4TYPE_TCP:
1933 if (src_port == 0)
1934 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xffff);
1935 else
1936 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1937 input_masks->src_port_mask);
1938
1939 if (dst_port == 0)
1940 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1941 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
1942 (0xffff << 16)));
1943 else
1944 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1945 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
1946 (input_masks->dst_port_mask << 16)));
1947 break;
1948 case IXGBE_ATR_L4TYPE_UDP:
1949 if (src_port == 0)
1950 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xffff);
1951 else
1952 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1953 input_masks->src_port_mask);
1954
1955 if (dst_port == 0)
1956 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1957 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
1958 (0xffff << 16)));
1959 else
1960 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1961 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
1962 (input_masks->src_port_mask << 16)));
1963 break;
1964 default:
1965 /* this already would have failed above */
1966 break;
1967 }
1968
1969 /* Program the last mask register, FDIRM */
1970 if (input_masks->vlan_id_mask || !vlan_id)
1971 /* Mask both VLAN and VLANP - bits 0 and 1 */
1972 fdirm |= 0x3;
1973
1974 if (input_masks->data_mask || !flex_bytes)
1975 /* Flex bytes need masking, so mask the whole thing - bit 4 */
1976 fdirm |= 0x10;
1977
1978 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1979 fdirm |= 0x24;
1980
1981 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
ffff4772
PWJ		 1982
1983 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
1984 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
1985 fdircmd |= IXGBE_FDIRCMD_LAST;
1986 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
1987 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1988
1989 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1990 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1991
1992 return 0;
1993}
11afc1b1
PW		 1994/**
1995 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1996 * @hw: pointer to hardware structure
1997 * @reg: analog register to read
1998 * @val: read value
1999 *
2000 * Performs read operation to Omer analog register specified.
2001 **/
7b25cdba 2002static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
11afc1b1
PW		 2003{
2004 u32 core_ctl;
2005
2006 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2007 (reg << 8));
2008 IXGBE_WRITE_FLUSH(hw);
2009 udelay(10);
2010 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2011 *val = (u8)core_ctl;
2012
2013 return 0;
2014}
2015
2016/**
2017 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2018 * @hw: pointer to hardware structure
2019 * @reg: atlas register to write
2020 * @val: value to write
2021 *
2022 * Performs write operation to Omer analog register specified.
2023 **/
7b25cdba 2024static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
11afc1b1
PW		 2025{
2026 u32 core_ctl;
2027
2028 core_ctl = (reg << 8) | val;
2029 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2030 IXGBE_WRITE_FLUSH(hw);
2031 udelay(10);
2032
2033 return 0;
2034}
2035
2036/**
2037 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2038 * @hw: pointer to hardware structure
2039 *
2040 * Starts the hardware using the generic start_hw function.
2041 * Then performs device-specific:
2042 * Clears the rate limiter registers.
2043 **/
7b25cdba 2044static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2045{
2046 u32 q_num;
794caeb2 2047 s32 ret_val;
11afc1b1 2048
794caeb2 2049 ret_val = ixgbe_start_hw_generic(hw);
11afc1b1
PW		 2050
2051 /* Clear the rate limiters */
2052 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2053 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2054 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2055 }
2056 IXGBE_WRITE_FLUSH(hw);
2057
50ac58ba
PWJ		 2058 /* We need to run link autotry after the driver loads */
2059 hw->mac.autotry_restart = true;
2060
794caeb2
PWJ		 2061 if (ret_val == 0)
2062 ret_val = ixgbe_verify_fw_version_82599(hw);
2063
2064 return ret_val;
11afc1b1
PW		 2065}
2066
2067/**
2068 * ixgbe_identify_phy_82599 - Get physical layer module
2069 * @hw: pointer to hardware structure
2070 *
2071 * Determines the physical layer module found on the current adapter.
2072 **/
7b25cdba 2073static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2074{
2075 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2076 status = ixgbe_identify_phy_generic(hw);
2077 if (status != 0)
2078 status = ixgbe_identify_sfp_module_generic(hw);
2079 return status;
2080}
2081
2082/**
2083 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2084 * @hw: pointer to hardware structure
2085 *
2086 * Determines physical layer capabilities of the current configuration.
2087 **/
7b25cdba 2088static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 2089{
2090 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 2091 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2092 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2093 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2094 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2095 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2096 u16 ext_ability = 0;
1339b9e9 2097 u8 comp_codes_10g = 0;
cb836a97 2098 u8 comp_codes_1g = 0;
11afc1b1 2099
04193058
PWJ		 2100 hw->phy.ops.identify(hw);
2101
2102 if (hw->phy.type == ixgbe_phy_tn ||
2103 hw->phy.type == ixgbe_phy_cu_unknown) {
6b73e10d
BH		 2104 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2105 &ext_ability);
2106 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 2107 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 2108 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 2109 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 2110 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 2111 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2112 goto out;
2113 }
2114
2115 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2116 case IXGBE_AUTOC_LMS_1G_AN:
2117 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2118 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2119 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2120 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2121 goto out;
2122 } else
2123 /* SFI mode so read SFP module */
2124 goto sfp_check;
11afc1b1 2125 break;
04193058
PWJ		 2126 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2127 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2128 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2129 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2130 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 2131 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2132 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 2133 goto out;
2134 break;
2135 case IXGBE_AUTOC_LMS_10G_SERIAL:
2136 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2137 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2138 goto out;
2139 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2140 goto sfp_check;
2141 break;
2142 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2143 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2144 if (autoc & IXGBE_AUTOC_KX_SUPP)
2145 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2146 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2147 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2148 if (autoc & IXGBE_AUTOC_KR_SUPP)
2149 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2150 goto out;
2151 break;
2152 default:
2153 goto out;
2154 break;
2155 }
11afc1b1 2156
04193058
PWJ		 2157sfp_check:
2158 /* SFP check must be done last since DA modules are sometimes used to
2159 * test KR mode - we need to id KR mode correctly before SFP module.
2160 * Call identify_sfp because the pluggable module may have changed */
2161 hw->phy.ops.identify_sfp(hw);
2162 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2163 goto out;
2164
2165 switch (hw->phy.type) {
ea0a04df
DS		 2166 case ixgbe_phy_sfp_passive_tyco:
2167 case ixgbe_phy_sfp_passive_unknown:
04193058
PWJ		 2168 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2169 break;
ea0a04df
DS		 2170 case ixgbe_phy_sfp_ftl_active:
2171 case ixgbe_phy_sfp_active_unknown:
2172 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2173 break;
04193058
PWJ		 2174 case ixgbe_phy_sfp_avago:
2175 case ixgbe_phy_sfp_ftl:
2176 case ixgbe_phy_sfp_intel:
2177 case ixgbe_phy_sfp_unknown:
cb836a97
DS		 2178 hw->phy.ops.read_i2c_eeprom(hw,
2179 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
04193058
PWJ		 2180 hw->phy.ops.read_i2c_eeprom(hw,
2181 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2182 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 2183 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 2184 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 2185 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
cb836a97
DS		 2186 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2187 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
11afc1b1
PW		 2188 break;
2189 default:
11afc1b1
PW		 2190 break;
2191 }
2192
04193058 2193out:
11afc1b1
PW		 2194 return physical_layer;
2195}
2196
2197/**
2198 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2199 * @hw: pointer to hardware structure
2200 * @regval: register value to write to RXCTRL
2201 *
2202 * Enables the Rx DMA unit for 82599
2203 **/
7b25cdba 2204static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
11afc1b1
PW		 2205{
2206#define IXGBE_MAX_SECRX_POLL 30
2207 int i;
2208 int secrxreg;
2209
2210 /*
2211 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2212 * If traffic is incoming before we enable the Rx unit, it could hang
2213 * the Rx DMA unit. Therefore, make sure the security engine is
2214 * completely disabled prior to enabling the Rx unit.
2215 */
2216 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2217 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2218 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2219 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2220 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2221 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2222 break;
2223 else
2224 udelay(10);
2225 }
2226
2227 /* For informational purposes only */
2228 if (i >= IXGBE_MAX_SECRX_POLL)
2229 hw_dbg(hw, "Rx unit being enabled before security "
2230 "path fully disabled. Continuing with init.\n");
2231
2232 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2233 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2234 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2235 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2236 IXGBE_WRITE_FLUSH(hw);
2237
2238 return 0;
2239}
2240
04193058
PWJ		 2241/**
2242 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2243 * @hw: pointer to hardware structure
2244 * @device_caps: the EEPROM word with the extra device capabilities
2245 *
2246 * This function will read the EEPROM location for the device capabilities,
2247 * and return the word through device_caps.
2248 **/
7b25cdba 2249static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
04193058
PWJ		 2250{
2251 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2252
2253 return 0;
2254}
2255
794caeb2
PWJ		 2256/**
2257 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2258 * @hw: pointer to hardware structure
2259 *
2260 * Verifies that installed the firmware version is 0.6 or higher
2261 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2262 *
2263 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2264 * if the FW version is not supported.
2265 **/
2266static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2267{
2268 s32 status = IXGBE_ERR_EEPROM_VERSION;
2269 u16 fw_offset, fw_ptp_cfg_offset;
2270 u16 fw_version = 0;
2271
2272 /* firmware check is only necessary for SFI devices */
2273 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2274 status = 0;
2275 goto fw_version_out;
2276 }
2277
2278 /* get the offset to the Firmware Module block */
2279 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2280
2281 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2282 goto fw_version_out;
2283
2284 /* get the offset to the Pass Through Patch Configuration block */
2285 hw->eeprom.ops.read(hw, (fw_offset +
2286 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2287 &fw_ptp_cfg_offset);
2288
2289 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2290 goto fw_version_out;
2291
2292 /* get the firmware version */
2293 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2294 IXGBE_FW_PATCH_VERSION_4),
2295 &fw_version);
2296
2297 if (fw_version > 0x5)
2298 status = 0;
2299
2300fw_version_out:
2301 return status;
2302}
2303
383ff34b
YZ		 2304/**
2305 * ixgbe_get_wwn_prefix_82599 - Get alternative WWNN/WWPN prefix from
2306 * the EEPROM
2307 * @hw: pointer to hardware structure
2308 * @wwnn_prefix: the alternative WWNN prefix
2309 * @wwpn_prefix: the alternative WWPN prefix
2310 *
2311 * This function will read the EEPROM from the alternative SAN MAC address
2312 * block to check the support for the alternative WWNN/WWPN prefix support.
2313 **/
2314static s32 ixgbe_get_wwn_prefix_82599(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2315 u16 *wwpn_prefix)
2316{
2317 u16 offset, caps;
2318 u16 alt_san_mac_blk_offset;
2319
2320 /* clear output first */
2321 *wwnn_prefix = 0xFFFF;
2322 *wwpn_prefix = 0xFFFF;
2323
2324 /* check if alternative SAN MAC is supported */
2325 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2326 &alt_san_mac_blk_offset);
2327
2328 if ((alt_san_mac_blk_offset == 0) ||
2329 (alt_san_mac_blk_offset == 0xFFFF))
2330 goto wwn_prefix_out;
2331
2332 /* check capability in alternative san mac address block */
2333 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2334 hw->eeprom.ops.read(hw, offset, &caps);
2335 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2336 goto wwn_prefix_out;
2337
2338 /* get the corresponding prefix for WWNN/WWPN */
2339 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2340 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2341
2342 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2343 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2344
2345wwn_prefix_out:
2346 return 0;
2347}
2348
11afc1b1
PW		 2349static struct ixgbe_mac_operations mac_ops_82599 = {
2350 .init_hw = &ixgbe_init_hw_generic,
2351 .reset_hw = &ixgbe_reset_hw_82599,
2352 .start_hw = &ixgbe_start_hw_82599,
2353 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2354 .get_media_type = &ixgbe_get_media_type_82599,
2355 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2356 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2357 .get_mac_addr = &ixgbe_get_mac_addr_generic,
21ce849b 2358 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
04193058 2359 .get_device_caps = &ixgbe_get_device_caps_82599,
383ff34b 2360 .get_wwn_prefix = &ixgbe_get_wwn_prefix_82599,
11afc1b1
PW		 2361 .stop_adapter = &ixgbe_stop_adapter_generic,
2362 .get_bus_info = &ixgbe_get_bus_info_generic,
2363 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2364 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2365 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2366 .setup_link = &ixgbe_setup_mac_link_82599,
21ce849b 2367 .check_link = &ixgbe_check_mac_link_generic,
11afc1b1
PW		 2368 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2369 .led_on = &ixgbe_led_on_generic,
2370 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 2371 .blink_led_start = &ixgbe_blink_led_start_generic,
2372 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 2373 .set_rar = &ixgbe_set_rar_generic,
2374 .clear_rar = &ixgbe_clear_rar_generic,
21ce849b
MC		 2375 .set_vmdq = &ixgbe_set_vmdq_generic,
2376 .clear_vmdq = &ixgbe_clear_vmdq_generic,
11afc1b1
PW		 2377 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2378 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2379 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2380 .enable_mc = &ixgbe_enable_mc_generic,
2381 .disable_mc = &ixgbe_disable_mc_generic,
21ce849b
MC		 2382 .clear_vfta = &ixgbe_clear_vfta_generic,
2383 .set_vfta = &ixgbe_set_vfta_generic,
2384 .fc_enable = &ixgbe_fc_enable_generic,
2385 .init_uta_tables = &ixgbe_init_uta_tables_generic,
11afc1b1
PW		 2386 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2387};
2388
2389static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2390 .init_params = &ixgbe_init_eeprom_params_generic,
21ce849b 2391 .read = &ixgbe_read_eerd_generic,
11afc1b1
PW		 2392 .write = &ixgbe_write_eeprom_generic,
2393 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2394 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2395};
2396
2397static struct ixgbe_phy_operations phy_ops_82599 = {
2398 .identify = &ixgbe_identify_phy_82599,
2399 .identify_sfp = &ixgbe_identify_sfp_module_generic,
21ce849b 2400 .init = &ixgbe_init_phy_ops_82599,
11afc1b1
PW		 2401 .reset = &ixgbe_reset_phy_generic,
2402 .read_reg = &ixgbe_read_phy_reg_generic,
2403 .write_reg = &ixgbe_write_phy_reg_generic,
2404 .setup_link = &ixgbe_setup_phy_link_generic,
2405 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2406 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2407 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2408 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2409 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
119fc60a 2410 .check_overtemp = &ixgbe_tn_check_overtemp,
11afc1b1
PW		 2411};
2412
2413struct ixgbe_info ixgbe_82599_info = {
2414 .mac = ixgbe_mac_82599EB,
2415 .get_invariants = &ixgbe_get_invariants_82599,
2416 .mac_ops = &mac_ops_82599,
2417 .eeprom_ops = &eeprom_ops_82599,
2418 .phy_ops = &phy_ops_82599,
096a58fd 2419 .mbx_ops = &mbx_ops_82599,
11afc1b1 2420};
Clone of davem's net-next-2.6 tree