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[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_82598.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
32
9c8eb720 33#include "ixgbe.h"
9a799d71
AK		 34#include "ixgbe_phy.h"
35
36#define IXGBE_82598_MAX_TX_QUEUES 32
37#define IXGBE_82598_MAX_RX_QUEUES 64
38#define IXGBE_82598_RAR_ENTRIES 16
2c5645cf
CL		 39#define IXGBE_82598_MC_TBL_SIZE 128
40#define IXGBE_82598_VFT_TBL_SIZE 128
9a799d71
AK		 41
42static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw);
43static s32 ixgbe_get_link_settings_82598(struct ixgbe_hw *hw, u32 *speed,
44 bool *autoneg);
45static s32 ixgbe_get_copper_link_settings_82598(struct ixgbe_hw *hw,
46 u32 *speed, bool *autoneg);
47static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
48static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw);
49static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, u32 *speed,
cf8280ee
JB		 50 bool *link_up,
51 bool link_up_wait_to_complete);
9a799d71
AK		 52static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, u32 speed,
53 bool autoneg,
54 bool autoneg_wait_to_complete);
55static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
9a799d71
AK		 56static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, u32 speed,
57 bool autoneg,
58 bool autoneg_wait_to_complete);
59static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
60
61
62static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
63{
ff68cdbf
JK		 64 hw->mac.num_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
65 hw->mac.num_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
2c5645cf
CL		 66 hw->mac.mcft_size = IXGBE_82598_MC_TBL_SIZE;
67 hw->mac.vft_size = IXGBE_82598_VFT_TBL_SIZE;
68 hw->mac.num_rar_entries = IXGBE_82598_RAR_ENTRIES;
9a799d71 69
3957d63d
AK		 70 /* PHY ops are filled in by default properly for Fiber only */
71 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
72 hw->mac.ops.setup_link = &ixgbe_setup_copper_link_82598;
73 hw->mac.ops.setup_link_speed = &ixgbe_setup_copper_link_speed_82598;
74 hw->mac.ops.get_link_settings =
75 &ixgbe_get_copper_link_settings_82598;
76
77 /* Call PHY identify routine to get the phy type */
78 ixgbe_identify_phy(hw);
79
80 switch (hw->phy.type) {
81 case ixgbe_phy_tn:
82 hw->phy.ops.setup_link = &ixgbe_setup_tnx_phy_link;
83 hw->phy.ops.check_link = &ixgbe_check_tnx_phy_link;
84 hw->phy.ops.setup_link_speed =
85 &ixgbe_setup_tnx_phy_link_speed;
86 break;
87 default:
88 break;
89 }
90 }
91
9a799d71
AK		 92 return 0;
93}
94
95/**
96 * ixgbe_get_link_settings_82598 - Determines default link settings
97 * @hw: pointer to hardware structure
98 * @speed: pointer to link speed
99 * @autoneg: boolean auto-negotiation value
100 *
101 * Determines the default link settings by reading the AUTOC register.
102 **/
103static s32 ixgbe_get_link_settings_82598(struct ixgbe_hw *hw, u32 *speed,
104 bool *autoneg)
105{
106 s32 status = 0;
107 s32 autoc_reg;
108
109 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
110
111 if (hw->mac.link_settings_loaded) {
112 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;
113 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK;
114 autoc_reg |= hw->mac.link_attach_type;
115 autoc_reg |= hw->mac.link_mode_select;
116 }
117
118 switch (autoc_reg & IXGBE_AUTOC_LMS_MASK) {
119 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
120 *speed = IXGBE_LINK_SPEED_1GB_FULL;
121 *autoneg = false;
122 break;
123
124 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
125 *speed = IXGBE_LINK_SPEED_10GB_FULL;
126 *autoneg = false;
127 break;
128
129 case IXGBE_AUTOC_LMS_1G_AN:
130 *speed = IXGBE_LINK_SPEED_1GB_FULL;
131 *autoneg = true;
132 break;
133
134 case IXGBE_AUTOC_LMS_KX4_AN:
135 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
136 *speed = IXGBE_LINK_SPEED_UNKNOWN;
137 if (autoc_reg & IXGBE_AUTOC_KX4_SUPP)
138 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
139 if (autoc_reg & IXGBE_AUTOC_KX_SUPP)
140 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
141 *autoneg = true;
142 break;
143
144 default:
145 status = IXGBE_ERR_LINK_SETUP;
146 break;
147 }
148
149 return status;
150}
151
152/**
153 * ixgbe_get_copper_link_settings_82598 - Determines default link settings
154 * @hw: pointer to hardware structure
155 * @speed: pointer to link speed
156 * @autoneg: boolean auto-negotiation value
157 *
158 * Determines the default link settings by reading the AUTOC register.
159 **/
160static s32 ixgbe_get_copper_link_settings_82598(struct ixgbe_hw *hw,
161 u32 *speed, bool *autoneg)
162{
163 s32 status = IXGBE_ERR_LINK_SETUP;
164 u16 speed_ability;
165
166 *speed = 0;
167 *autoneg = true;
168
169 status = ixgbe_read_phy_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
170 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
171 &speed_ability);
172
173 if (status == 0) {
174 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
175 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
176 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
177 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
178 }
179
180 return status;
181}
182
183/**
184 * ixgbe_get_media_type_82598 - Determines media type
185 * @hw: pointer to hardware structure
186 *
187 * Returns the media type (fiber, copper, backplane)
188 **/
189static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
190{
191 enum ixgbe_media_type media_type;
192
193 /* Media type for I82598 is based on device ID */
194 switch (hw->device_id) {
195 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
196 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
197 case IXGBE_DEV_ID_82598EB_CX4:
8d792cd9 198 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
9a799d71
AK		 199 media_type = ixgbe_media_type_fiber;
200 break;
201 case IXGBE_DEV_ID_82598AT_DUAL_PORT:
202 media_type = ixgbe_media_type_copper;
203 break;
204 default:
205 media_type = ixgbe_media_type_unknown;
206 break;
207 }
208
209 return media_type;
210}
211
212/**
213 * ixgbe_setup_mac_link_82598 - Configures MAC link settings
214 * @hw: pointer to hardware structure
215 *
216 * Configures link settings based on values in the ixgbe_hw struct.
217 * Restarts the link. Performs autonegotiation if needed.
218 **/
219static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
220{
221 u32 autoc_reg;
222 u32 links_reg;
223 u32 i;
224 s32 status = 0;
225
226 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
227
228 if (hw->mac.link_settings_loaded) {
229 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;
230 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK;
231 autoc_reg |= hw->mac.link_attach_type;
232 autoc_reg |= hw->mac.link_mode_select;
233
234 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3957d63d 235 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 236 msleep(50);
237 }
238
239 /* Restart link */
240 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
241 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
242
243 /* Only poll for autoneg to complete if specified to do so */
244 if (hw->phy.autoneg_wait_to_complete) {
245 if (hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN ||
246 hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
247 links_reg = 0; /* Just in case Autoneg time = 0 */
248 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
249 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
250 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
251 break;
252 msleep(100);
253 }
254 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
255 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
256 hw_dbg(hw,
257 "Autonegotiation did not complete.\n");
258 }
259 }
260 }
261
262 /*
263 * We want to save off the original Flow Control configuration just in
264 * case we get disconnected and then reconnected into a different hub
265 * or switch with different Flow Control capabilities.
266 */
267 hw->fc.type = hw->fc.original_type;
268 ixgbe_setup_fc(hw, 0);
269
270 /* Add delay to filter out noises during initial link setup */
271 msleep(50);
272
273 return status;
274}
275
276/**
277 * ixgbe_check_mac_link_82598 - Get link/speed status
278 * @hw: pointer to hardware structure
279 * @speed: pointer to link speed
280 * @link_up: true is link is up, false otherwise
cf8280ee 281 * @link_up_wait_to_complete: bool used to wait for link up or not
9a799d71
AK		 282 *
283 * Reads the links register to determine if link is up and the current speed
284 **/
285static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, u32 *speed,
cf8280ee
JB		 286 bool *link_up,
287 bool link_up_wait_to_complete)
9a799d71
AK		 288{
289 u32 links_reg;
cf8280ee 290 u32 i;
9a799d71
AK		 291
292 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
293
cf8280ee
JB		 294 if (link_up_wait_to_complete) {
295 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
296 if (links_reg & IXGBE_LINKS_UP) {
297 *link_up = true;
298 break;
299 } else {
300 *link_up = false;
301 }
302 msleep(100);
303 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
304 }
305 } else {
306 if (links_reg & IXGBE_LINKS_UP)
307 *link_up = true;
308 else
309 *link_up = false;
310 }
9a799d71
AK		 311
312 if (links_reg & IXGBE_LINKS_SPEED)
313 *speed = IXGBE_LINK_SPEED_10GB_FULL;
314 else
315 *speed = IXGBE_LINK_SPEED_1GB_FULL;
316
317 return 0;
318}
319
320/**
321 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
322 * @hw: pointer to hardware structure
323 * @speed: new link speed
324 * @autoneg: true if auto-negotiation enabled
325 * @autoneg_wait_to_complete: true if waiting is needed to complete
326 *
327 * Set the link speed in the AUTOC register and restarts link.
328 **/
329static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
330 u32 speed, bool autoneg,
331 bool autoneg_wait_to_complete)
332{
333 s32 status = 0;
334
335 /* If speed is 10G, then check for CX4 or XAUI. */
336 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
337 (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4)))
338 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
339 else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg))
340 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
341 else if (autoneg) {
342 /* BX mode - Autonegotiate 1G */
343 if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD))
344 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN;
345 else /* KX/KX4 mode */
346 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN_1G_AN;
347 } else {
348 status = IXGBE_ERR_LINK_SETUP;
349 }
350
351 if (status == 0) {
352 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
353
354 hw->mac.link_settings_loaded = true;
355 /*
356 * Setup and restart the link based on the new values in
357 * ixgbe_hw This will write the AUTOC register based on the new
358 * stored values
359 */
3957d63d 360 hw->mac.ops.setup_link(hw);
9a799d71
AK		 361 }
362
363 return status;
364}
365
366
367/**
368 * ixgbe_setup_copper_link_82598 - Setup copper link settings
369 * @hw: pointer to hardware structure
370 *
371 * Configures link settings based on values in the ixgbe_hw struct.
372 * Restarts the link. Performs autonegotiation if needed. Restart
373 * phy and wait for autonegotiate to finish. Then synchronize the
374 * MAC and PHY.
375 **/
376static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
377{
3957d63d 378 s32 status = 0;
9a799d71
AK		 379
380 /* Restart autonegotiation on PHY */
3957d63d
AK		 381 if (hw->phy.ops.setup_link)
382 status = hw->phy.ops.setup_link(hw);
9a799d71 383
3957d63d
AK		 384 /* Set MAC to KX/KX4 autoneg, which defaultis to Parallel detection */
385 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);
386 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN;
9a799d71 387
3957d63d
AK		 388 /* Set up MAC */
389 hw->mac.ops.setup_link(hw);
9a799d71
AK		 390
391 return status;
392}
393
394/**
395 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
396 * @hw: pointer to hardware structure
397 * @speed: new link speed
398 * @autoneg: true if autonegotiation enabled
399 * @autoneg_wait_to_complete: true if waiting is needed to complete
400 *
401 * Sets the link speed in the AUTOC register in the MAC and restarts link.
402 **/
403static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, u32 speed,
404 bool autoneg,
405 bool autoneg_wait_to_complete)
406{
3957d63d 407 s32 status = 0;
9a799d71
AK		 408
409 /* Setup the PHY according to input speed */
3957d63d
AK		 410 if (hw->phy.ops.setup_link_speed)
411 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
412 autoneg_wait_to_complete);
413
414 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
415 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);
416 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN;
9a799d71 417
3957d63d
AK		 418 /* Set up MAC */
419 hw->mac.ops.setup_link(hw);
9a799d71
AK		 420
421 return status;
422}
423
424/**
425 * ixgbe_reset_hw_82598 - Performs hardware reset
426 * @hw: pointer to hardware structure
427 *
428 * Resets the hardware by reseting the transmit and receive units, masks and
429 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
430 * reset.
431 **/
432static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
433{
434 s32 status = 0;
435 u32 ctrl;
436 u32 gheccr;
437 u32 i;
438 u32 autoc;
439 u8 analog_val;
440
441 /* Call adapter stop to disable tx/rx and clear interrupts */
442 ixgbe_stop_adapter(hw);
443
444 /*
445 * Power up the Atlas TX lanes if they are currently powered down.
446 * Atlas TX lanes are powered down for MAC loopback tests, but
447 * they are not automatically restored on reset.
448 */
449 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
450 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
451 /* Enable TX Atlas so packets can be transmitted again */
452 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
453 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
454 ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, analog_val);
455
456 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &analog_val);
457 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
458 ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, analog_val);
459
460 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &analog_val);
461 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
462 ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, analog_val);
463
464 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &analog_val);
465 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
466 ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, analog_val);
467 }
468
469 /* Reset PHY */
470 ixgbe_reset_phy(hw);
471
472 /*
473 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
474 * access and verify no pending requests before reset
475 */
476 if (ixgbe_disable_pcie_master(hw) != 0) {
477 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
478 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
479 }
480
481 /*
482 * Issue global reset to the MAC. This needs to be a SW reset.
483 * If link reset is used, it might reset the MAC when mng is using it
484 */
485 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
486 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
487 IXGBE_WRITE_FLUSH(hw);
488
489 /* Poll for reset bit to self-clear indicating reset is complete */
490 for (i = 0; i < 10; i++) {
491 udelay(1);
492 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
493 if (!(ctrl & IXGBE_CTRL_RST))
494 break;
495 }
496 if (ctrl & IXGBE_CTRL_RST) {
497 status = IXGBE_ERR_RESET_FAILED;
498 hw_dbg(hw, "Reset polling failed to complete.\n");
499 }
500
501 msleep(50);
502
503 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
504 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
505 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
506
507 /*
508 * AUTOC register which stores link settings gets cleared
509 * and reloaded from EEPROM after reset. We need to restore
510 * our stored value from init in case SW changed the attach
511 * type or speed. If this is the first time and link settings
512 * have not been stored, store default settings from AUTOC.
513 */
514 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
515 if (hw->mac.link_settings_loaded) {
516 autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE);
517 autoc &= ~(IXGBE_AUTOC_LMS_MASK);
518 autoc |= hw->mac.link_attach_type;
519 autoc |= hw->mac.link_mode_select;
520 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
521 } else {
522 hw->mac.link_attach_type =
523 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE);
524 hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK);
525 hw->mac.link_settings_loaded = true;
526 }
527
528 /* Store the permanent mac address */
529 ixgbe_get_mac_addr(hw, hw->mac.perm_addr);
530
531 return status;
532}
533
534static struct ixgbe_mac_operations mac_ops_82598 = {
535 .reset = &ixgbe_reset_hw_82598,
536 .get_media_type = &ixgbe_get_media_type_82598,
3957d63d
AK		 537 .setup_link = &ixgbe_setup_mac_link_82598,
538 .check_link = &ixgbe_check_mac_link_82598,
539 .setup_link_speed = &ixgbe_setup_mac_link_speed_82598,
540 .get_link_settings = &ixgbe_get_link_settings_82598,
9a799d71
AK		 541};
542
3957d63d 543struct ixgbe_info ixgbe_82598_info = {
9a799d71
AK		 544 .mac = ixgbe_mac_82598EB,
545 .get_invariants = &ixgbe_get_invariants_82598,
546 .mac_ops = &mac_ops_82598,
9a799d71
AK		 547};
548
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