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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
3efac5a0 | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/pci.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/sched.h> | |
31 | ||
9c8eb720 | 32 | #include "ixgbe.h" |
9a799d71 AK |
33 | #include "ixgbe_phy.h" |
34 | ||
35 | #define IXGBE_82598_MAX_TX_QUEUES 32 | |
36 | #define IXGBE_82598_MAX_RX_QUEUES 64 | |
37 | #define IXGBE_82598_RAR_ENTRIES 16 | |
2c5645cf CL |
38 | #define IXGBE_82598_MC_TBL_SIZE 128 |
39 | #define IXGBE_82598_VFT_TBL_SIZE 128 | |
9a799d71 | 40 | |
c44ade9e JB |
41 | static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, |
42 | ixgbe_link_speed *speed, | |
43 | bool *autoneg); | |
9a799d71 | 44 | static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw); |
c44ade9e JB |
45 | static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, |
46 | ixgbe_link_speed speed, | |
47 | bool autoneg, | |
48 | bool autoneg_wait_to_complete); | |
c4900be0 DS |
49 | static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, |
50 | u8 *eeprom_data); | |
9a799d71 | 51 | |
202ff1ec MC |
52 | /** |
53 | * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout | |
54 | * @hw: pointer to the HW structure | |
55 | * | |
56 | * The defaults for 82598 should be in the range of 50us to 50ms, | |
57 | * however the hardware default for these parts is 500us to 1ms which is less | |
58 | * than the 10ms recommended by the pci-e spec. To address this we need to | |
59 | * increase the value to either 10ms to 250ms for capability version 1 config, | |
60 | * or 16ms to 55ms for version 2. | |
61 | **/ | |
62 | void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) | |
63 | { | |
64 | struct ixgbe_adapter *adapter = hw->back; | |
65 | u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); | |
66 | u16 pcie_devctl2; | |
67 | ||
68 | /* only take action if timeout value is defaulted to 0 */ | |
69 | if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) | |
70 | goto out; | |
71 | ||
72 | /* | |
73 | * if capababilities version is type 1 we can write the | |
74 | * timeout of 10ms to 250ms through the GCR register | |
75 | */ | |
76 | if (!(gcr & IXGBE_GCR_CAP_VER2)) { | |
77 | gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; | |
78 | goto out; | |
79 | } | |
80 | ||
81 | /* | |
82 | * for version 2 capabilities we need to write the config space | |
83 | * directly in order to set the completion timeout value for | |
84 | * 16ms to 55ms | |
85 | */ | |
86 | pci_read_config_word(adapter->pdev, | |
87 | IXGBE_PCI_DEVICE_CONTROL2, &pcie_devctl2); | |
88 | pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; | |
89 | pci_write_config_word(adapter->pdev, | |
90 | IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); | |
91 | out: | |
92 | /* disable completion timeout resend */ | |
93 | gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; | |
94 | IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); | |
95 | } | |
96 | ||
eb7f139c PWJ |
97 | /** |
98 | * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count | |
99 | * @hw: pointer to hardware structure | |
100 | * | |
101 | * Read PCIe configuration space, and get the MSI-X vector count from | |
102 | * the capabilities table. | |
103 | **/ | |
1aef47c4 | 104 | static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw) |
eb7f139c PWJ |
105 | { |
106 | struct ixgbe_adapter *adapter = hw->back; | |
107 | u16 msix_count; | |
108 | pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS, | |
109 | &msix_count); | |
110 | msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; | |
111 | ||
112 | /* MSI-X count is zero-based in HW, so increment to give proper value */ | |
113 | msix_count++; | |
114 | ||
115 | return msix_count; | |
116 | } | |
117 | ||
c44ade9e JB |
118 | /** |
119 | */ | |
9a799d71 | 120 | static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) |
04f165ef PW |
121 | { |
122 | struct ixgbe_mac_info *mac = &hw->mac; | |
123 | ||
124 | /* Call PHY identify routine to get the phy type */ | |
125 | ixgbe_identify_phy_generic(hw); | |
126 | ||
127 | mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; | |
128 | mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; | |
129 | mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; | |
130 | mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; | |
131 | mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; | |
132 | mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw); | |
133 | ||
134 | return 0; | |
135 | } | |
136 | ||
137 | /** | |
138 | * ixgbe_init_phy_ops_82598 - PHY/SFP specific init | |
139 | * @hw: pointer to hardware structure | |
140 | * | |
141 | * Initialize any function pointers that were not able to be | |
142 | * set during get_invariants because the PHY/SFP type was | |
143 | * not known. Perform the SFP init if necessary. | |
144 | * | |
145 | **/ | |
146 | s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) | |
9a799d71 | 147 | { |
c44ade9e JB |
148 | struct ixgbe_mac_info *mac = &hw->mac; |
149 | struct ixgbe_phy_info *phy = &hw->phy; | |
c4900be0 DS |
150 | s32 ret_val = 0; |
151 | u16 list_offset, data_offset; | |
c44ade9e | 152 | |
04f165ef PW |
153 | /* Identify the PHY */ |
154 | phy->ops.identify(hw); | |
03cfa205 | 155 | |
04f165ef PW |
156 | /* Overwrite the link function pointers if copper PHY */ |
157 | if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { | |
158 | mac->ops.setup_link = &ixgbe_setup_copper_link_82598; | |
159 | mac->ops.setup_link_speed = | |
160 | &ixgbe_setup_copper_link_speed_82598; | |
161 | mac->ops.get_link_capabilities = | |
162 | &ixgbe_get_copper_link_capabilities_82598; | |
163 | } | |
c44ade9e | 164 | |
04f165ef | 165 | switch (hw->phy.type) { |
0befdb3e JB |
166 | case ixgbe_phy_tn: |
167 | phy->ops.check_link = &ixgbe_check_phy_link_tnx; | |
168 | phy->ops.get_firmware_version = | |
169 | &ixgbe_get_phy_firmware_version_tnx; | |
170 | break; | |
c4900be0 DS |
171 | case ixgbe_phy_nl: |
172 | phy->ops.reset = &ixgbe_reset_phy_nl; | |
173 | ||
174 | /* Call SFP+ identify routine to get the SFP+ module type */ | |
175 | ret_val = phy->ops.identify_sfp(hw); | |
176 | if (ret_val != 0) | |
177 | goto out; | |
178 | else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { | |
179 | ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; | |
180 | goto out; | |
181 | } | |
182 | ||
183 | /* Check to see if SFP+ module is supported */ | |
184 | ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, | |
04f165ef PW |
185 | &list_offset, |
186 | &data_offset); | |
c4900be0 DS |
187 | if (ret_val != 0) { |
188 | ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; | |
189 | goto out; | |
190 | } | |
191 | break; | |
c44ade9e JB |
192 | default: |
193 | break; | |
194 | } | |
195 | ||
c4900be0 DS |
196 | out: |
197 | return ret_val; | |
9a799d71 AK |
198 | } |
199 | ||
202ff1ec MC |
200 | /** |
201 | * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx | |
202 | * @hw: pointer to hardware structure | |
203 | * | |
204 | * Starts the hardware using the generic start_hw function. | |
205 | * Then set pcie completion timeout | |
206 | **/ | |
207 | s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) | |
208 | { | |
209 | s32 ret_val = 0; | |
210 | ||
211 | ret_val = ixgbe_start_hw_generic(hw); | |
212 | ||
213 | /* set the completion timeout for interface */ | |
214 | if (ret_val == 0) | |
215 | ixgbe_set_pcie_completion_timeout(hw); | |
216 | ||
217 | return ret_val; | |
218 | } | |
219 | ||
9a799d71 | 220 | /** |
c44ade9e | 221 | * ixgbe_get_link_capabilities_82598 - Determines link capabilities |
9a799d71 AK |
222 | * @hw: pointer to hardware structure |
223 | * @speed: pointer to link speed | |
224 | * @autoneg: boolean auto-negotiation value | |
225 | * | |
c44ade9e | 226 | * Determines the link capabilities by reading the AUTOC register. |
9a799d71 | 227 | **/ |
c44ade9e | 228 | static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, |
b4617240 PW |
229 | ixgbe_link_speed *speed, |
230 | bool *autoneg) | |
9a799d71 AK |
231 | { |
232 | s32 status = 0; | |
1eb99d5a | 233 | u32 autoc = 0; |
9a799d71 | 234 | |
3201d313 PWJ |
235 | /* |
236 | * Determine link capabilities based on the stored value of AUTOC, | |
1eb99d5a PW |
237 | * which represents EEPROM defaults. If AUTOC value has not been |
238 | * stored, use the current register value. | |
3201d313 | 239 | */ |
1eb99d5a PW |
240 | if (hw->mac.orig_link_settings_stored) |
241 | autoc = hw->mac.orig_autoc; | |
242 | else | |
243 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
244 | ||
245 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { | |
9a799d71 AK |
246 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: |
247 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
248 | *autoneg = false; | |
249 | break; | |
250 | ||
251 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: | |
252 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
253 | *autoneg = false; | |
254 | break; | |
255 | ||
256 | case IXGBE_AUTOC_LMS_1G_AN: | |
257 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
258 | *autoneg = true; | |
259 | break; | |
260 | ||
261 | case IXGBE_AUTOC_LMS_KX4_AN: | |
262 | case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: | |
263 | *speed = IXGBE_LINK_SPEED_UNKNOWN; | |
1eb99d5a | 264 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
9a799d71 | 265 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
1eb99d5a | 266 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
9a799d71 AK |
267 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
268 | *autoneg = true; | |
269 | break; | |
270 | ||
271 | default: | |
272 | status = IXGBE_ERR_LINK_SETUP; | |
273 | break; | |
274 | } | |
275 | ||
276 | return status; | |
277 | } | |
278 | ||
279 | /** | |
c44ade9e | 280 | * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities |
9a799d71 AK |
281 | * @hw: pointer to hardware structure |
282 | * @speed: pointer to link speed | |
283 | * @autoneg: boolean auto-negotiation value | |
284 | * | |
c44ade9e | 285 | * Determines the link capabilities by reading the AUTOC register. |
9a799d71 | 286 | **/ |
e855aac8 HE |
287 | static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw, |
288 | ixgbe_link_speed *speed, | |
289 | bool *autoneg) | |
9a799d71 AK |
290 | { |
291 | s32 status = IXGBE_ERR_LINK_SETUP; | |
292 | u16 speed_ability; | |
293 | ||
294 | *speed = 0; | |
295 | *autoneg = true; | |
296 | ||
6b73e10d | 297 | status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, |
b4617240 | 298 | &speed_ability); |
9a799d71 AK |
299 | |
300 | if (status == 0) { | |
6b73e10d | 301 | if (speed_ability & MDIO_SPEED_10G) |
9a799d71 | 302 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
6b73e10d | 303 | if (speed_ability & MDIO_PMA_SPEED_1000) |
9a799d71 AK |
304 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
305 | } | |
306 | ||
307 | return status; | |
308 | } | |
309 | ||
310 | /** | |
311 | * ixgbe_get_media_type_82598 - Determines media type | |
312 | * @hw: pointer to hardware structure | |
313 | * | |
314 | * Returns the media type (fiber, copper, backplane) | |
315 | **/ | |
316 | static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) | |
317 | { | |
318 | enum ixgbe_media_type media_type; | |
319 | ||
320 | /* Media type for I82598 is based on device ID */ | |
321 | switch (hw->device_id) { | |
1e336d0f | 322 | case IXGBE_DEV_ID_82598: |
2f21bdd3 | 323 | case IXGBE_DEV_ID_82598_BX: |
1e336d0f DS |
324 | media_type = ixgbe_media_type_backplane; |
325 | break; | |
9a799d71 AK |
326 | case IXGBE_DEV_ID_82598AF_DUAL_PORT: |
327 | case IXGBE_DEV_ID_82598AF_SINGLE_PORT: | |
328 | case IXGBE_DEV_ID_82598EB_CX4: | |
8d792cd9 | 329 | case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: |
c4900be0 DS |
330 | case IXGBE_DEV_ID_82598_DA_DUAL_PORT: |
331 | case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: | |
b95f5fcb | 332 | case IXGBE_DEV_ID_82598EB_XF_LR: |
c4900be0 | 333 | case IXGBE_DEV_ID_82598EB_SFP_LOM: |
9a799d71 AK |
334 | media_type = ixgbe_media_type_fiber; |
335 | break; | |
0befdb3e | 336 | case IXGBE_DEV_ID_82598AT: |
3845bec0 | 337 | case IXGBE_DEV_ID_82598AT2: |
0befdb3e JB |
338 | media_type = ixgbe_media_type_copper; |
339 | break; | |
9a799d71 AK |
340 | default: |
341 | media_type = ixgbe_media_type_unknown; | |
342 | break; | |
343 | } | |
344 | ||
345 | return media_type; | |
346 | } | |
347 | ||
c44ade9e | 348 | /** |
0ecc061d | 349 | * ixgbe_fc_enable_82598 - Enable flow control |
c44ade9e JB |
350 | * @hw: pointer to hardware structure |
351 | * @packetbuf_num: packet buffer number (0-7) | |
352 | * | |
0ecc061d | 353 | * Enable flow control according to the current settings. |
c44ade9e | 354 | **/ |
0ecc061d | 355 | static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) |
c44ade9e | 356 | { |
0ecc061d PWJ |
357 | s32 ret_val = 0; |
358 | u32 fctrl_reg; | |
c44ade9e | 359 | u32 rmcs_reg; |
0ecc061d | 360 | u32 reg; |
c44ade9e | 361 | |
620fa036 MC |
362 | #ifdef CONFIG_DCB |
363 | if (hw->fc.requested_mode == ixgbe_fc_pfc) | |
364 | goto out; | |
365 | ||
366 | #endif /* CONFIG_DCB */ | |
367 | /* Negotiate the fc mode to use */ | |
368 | ret_val = ixgbe_fc_autoneg(hw); | |
369 | if (ret_val) | |
370 | goto out; | |
371 | ||
372 | /* Disable any previous flow control settings */ | |
0ecc061d PWJ |
373 | fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
374 | fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); | |
c44ade9e JB |
375 | |
376 | rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
377 | rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); | |
378 | ||
379 | /* | |
0ecc061d | 380 | * The possible values of fc.current_mode are: |
c44ade9e | 381 | * 0: Flow control is completely disabled |
0ecc061d PWJ |
382 | * 1: Rx flow control is enabled (we can receive pause frames, |
383 | * but not send pause frames). | |
620fa036 | 384 | * 2: Tx flow control is enabled (we can send pause frames but |
0ecc061d | 385 | * we do not support receiving pause frames). |
c44ade9e JB |
386 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
387 | * other: Invalid. | |
620fa036 MC |
388 | #ifdef CONFIG_DCB |
389 | * 4: Priority Flow Control is enabled. | |
390 | #endif | |
c44ade9e | 391 | */ |
0ecc061d | 392 | switch (hw->fc.current_mode) { |
c44ade9e | 393 | case ixgbe_fc_none: |
620fa036 MC |
394 | /* |
395 | * Flow control is disabled by software override or autoneg. | |
396 | * The code below will actually disable it in the HW. | |
397 | */ | |
c44ade9e JB |
398 | break; |
399 | case ixgbe_fc_rx_pause: | |
400 | /* | |
0ecc061d PWJ |
401 | * Rx Flow control is enabled and Tx Flow control is |
402 | * disabled by software override. Since there really | |
403 | * isn't a way to advertise that we are capable of RX | |
404 | * Pause ONLY, we will advertise that we support both | |
405 | * symmetric and asymmetric Rx PAUSE. Later, we will | |
406 | * disable the adapter's ability to send PAUSE frames. | |
c44ade9e | 407 | */ |
0ecc061d | 408 | fctrl_reg |= IXGBE_FCTRL_RFCE; |
c44ade9e JB |
409 | break; |
410 | case ixgbe_fc_tx_pause: | |
411 | /* | |
0ecc061d PWJ |
412 | * Tx Flow control is enabled, and Rx Flow control is |
413 | * disabled by software override. | |
c44ade9e JB |
414 | */ |
415 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; | |
416 | break; | |
417 | case ixgbe_fc_full: | |
0ecc061d PWJ |
418 | /* Flow control (both Rx and Tx) is enabled by SW override. */ |
419 | fctrl_reg |= IXGBE_FCTRL_RFCE; | |
c44ade9e JB |
420 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; |
421 | break; | |
620fa036 MC |
422 | #ifdef CONFIG_DCB |
423 | case ixgbe_fc_pfc: | |
424 | goto out; | |
425 | break; | |
426 | #endif /* CONFIG_DCB */ | |
c44ade9e | 427 | default: |
c44ade9e | 428 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
0ecc061d PWJ |
429 | ret_val = -IXGBE_ERR_CONFIG; |
430 | goto out; | |
c44ade9e JB |
431 | break; |
432 | } | |
433 | ||
620fa036 | 434 | /* Set 802.3x based flow control settings. */ |
2132d381 | 435 | fctrl_reg |= IXGBE_FCTRL_DPF; |
0ecc061d | 436 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); |
c44ade9e JB |
437 | IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); |
438 | ||
0ecc061d PWJ |
439 | /* Set up and enable Rx high/low water mark thresholds, enable XON. */ |
440 | if (hw->fc.current_mode & ixgbe_fc_tx_pause) { | |
c44ade9e JB |
441 | if (hw->fc.send_xon) { |
442 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), | |
443 | (hw->fc.low_water | IXGBE_FCRTL_XONE)); | |
444 | } else { | |
445 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), | |
446 | hw->fc.low_water); | |
447 | } | |
0ecc061d | 448 | |
c44ade9e | 449 | IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), |
0ecc061d | 450 | (hw->fc.high_water | IXGBE_FCRTH_FCEN)); |
c44ade9e JB |
451 | } |
452 | ||
0ecc061d | 453 | /* Configure pause time (2 TCs per register) */ |
264857b8 | 454 | reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); |
0ecc061d PWJ |
455 | if ((packetbuf_num & 1) == 0) |
456 | reg = (reg & 0xFFFF0000) | hw->fc.pause_time; | |
457 | else | |
458 | reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); | |
459 | IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); | |
460 | ||
c44ade9e JB |
461 | IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); |
462 | ||
0ecc061d PWJ |
463 | out: |
464 | return ret_val; | |
465 | } | |
466 | ||
9a799d71 AK |
467 | /** |
468 | * ixgbe_setup_mac_link_82598 - Configures MAC link settings | |
469 | * @hw: pointer to hardware structure | |
470 | * | |
471 | * Configures link settings based on values in the ixgbe_hw struct. | |
472 | * Restarts the link. Performs autonegotiation if needed. | |
473 | **/ | |
474 | static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw) | |
475 | { | |
476 | u32 autoc_reg; | |
477 | u32 links_reg; | |
478 | u32 i; | |
479 | s32 status = 0; | |
480 | ||
9a799d71 | 481 | /* Restart link */ |
3201d313 | 482 | autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
9a799d71 AK |
483 | autoc_reg |= IXGBE_AUTOC_AN_RESTART; |
484 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); | |
485 | ||
486 | /* Only poll for autoneg to complete if specified to do so */ | |
487 | if (hw->phy.autoneg_wait_to_complete) { | |
3201d313 PWJ |
488 | if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
489 | IXGBE_AUTOC_LMS_KX4_AN || | |
490 | (autoc_reg & IXGBE_AUTOC_LMS_MASK) == | |
491 | IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { | |
9a799d71 AK |
492 | links_reg = 0; /* Just in case Autoneg time = 0 */ |
493 | for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { | |
494 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
495 | if (links_reg & IXGBE_LINKS_KX_AN_COMP) | |
496 | break; | |
497 | msleep(100); | |
498 | } | |
499 | if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { | |
500 | status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; | |
c44ade9e | 501 | hw_dbg(hw, "Autonegotiation did not complete.\n"); |
9a799d71 AK |
502 | } |
503 | } | |
504 | } | |
505 | ||
9a799d71 AK |
506 | /* Add delay to filter out noises during initial link setup */ |
507 | msleep(50); | |
508 | ||
509 | return status; | |
510 | } | |
511 | ||
512 | /** | |
513 | * ixgbe_check_mac_link_82598 - Get link/speed status | |
514 | * @hw: pointer to hardware structure | |
515 | * @speed: pointer to link speed | |
516 | * @link_up: true is link is up, false otherwise | |
cf8280ee | 517 | * @link_up_wait_to_complete: bool used to wait for link up or not |
9a799d71 AK |
518 | * |
519 | * Reads the links register to determine if link is up and the current speed | |
520 | **/ | |
b4617240 PW |
521 | static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, |
522 | ixgbe_link_speed *speed, bool *link_up, | |
523 | bool link_up_wait_to_complete) | |
9a799d71 AK |
524 | { |
525 | u32 links_reg; | |
cf8280ee | 526 | u32 i; |
c4900be0 DS |
527 | u16 link_reg, adapt_comp_reg; |
528 | ||
529 | /* | |
530 | * SERDES PHY requires us to read link status from register 0xC79F. | |
531 | * Bit 0 set indicates link is up/ready; clear indicates link down. | |
532 | * 0xC00C is read to check that the XAUI lanes are active. Bit 0 | |
533 | * clear indicates active; set indicates inactive. | |
534 | */ | |
535 | if (hw->phy.type == ixgbe_phy_nl) { | |
6b73e10d BH |
536 | hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); |
537 | hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg); | |
538 | hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD, | |
c4900be0 DS |
539 | &adapt_comp_reg); |
540 | if (link_up_wait_to_complete) { | |
541 | for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { | |
542 | if ((link_reg & 1) && | |
543 | ((adapt_comp_reg & 1) == 0)) { | |
544 | *link_up = true; | |
545 | break; | |
546 | } else { | |
547 | *link_up = false; | |
548 | } | |
549 | msleep(100); | |
550 | hw->phy.ops.read_reg(hw, 0xC79F, | |
6b73e10d | 551 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
552 | &link_reg); |
553 | hw->phy.ops.read_reg(hw, 0xC00C, | |
6b73e10d | 554 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
555 | &adapt_comp_reg); |
556 | } | |
557 | } else { | |
558 | if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) | |
559 | *link_up = true; | |
560 | else | |
561 | *link_up = false; | |
562 | } | |
563 | ||
564 | if (*link_up == false) | |
565 | goto out; | |
566 | } | |
9a799d71 AK |
567 | |
568 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
cf8280ee JB |
569 | if (link_up_wait_to_complete) { |
570 | for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { | |
571 | if (links_reg & IXGBE_LINKS_UP) { | |
572 | *link_up = true; | |
573 | break; | |
574 | } else { | |
575 | *link_up = false; | |
576 | } | |
577 | msleep(100); | |
578 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
579 | } | |
580 | } else { | |
581 | if (links_reg & IXGBE_LINKS_UP) | |
582 | *link_up = true; | |
583 | else | |
584 | *link_up = false; | |
585 | } | |
9a799d71 AK |
586 | |
587 | if (links_reg & IXGBE_LINKS_SPEED) | |
588 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
589 | else | |
590 | *speed = IXGBE_LINK_SPEED_1GB_FULL; | |
591 | ||
620fa036 MC |
592 | /* if link is down, zero out the current_mode */ |
593 | if (*link_up == false) { | |
594 | hw->fc.current_mode = ixgbe_fc_none; | |
595 | hw->fc.fc_was_autonegged = false; | |
596 | } | |
c4900be0 | 597 | out: |
9a799d71 AK |
598 | return 0; |
599 | } | |
600 | ||
c44ade9e | 601 | |
9a799d71 AK |
602 | /** |
603 | * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed | |
604 | * @hw: pointer to hardware structure | |
605 | * @speed: new link speed | |
606 | * @autoneg: true if auto-negotiation enabled | |
607 | * @autoneg_wait_to_complete: true if waiting is needed to complete | |
608 | * | |
609 | * Set the link speed in the AUTOC register and restarts link. | |
610 | **/ | |
611 | static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, | |
3201d313 PWJ |
612 | ixgbe_link_speed speed, bool autoneg, |
613 | bool autoneg_wait_to_complete) | |
9a799d71 | 614 | { |
3201d313 PWJ |
615 | s32 status = 0; |
616 | ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; | |
617 | u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
618 | u32 autoc = curr_autoc; | |
619 | u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; | |
9a799d71 | 620 | |
3201d313 PWJ |
621 | /* Check to see if speed passed in is supported. */ |
622 | ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg); | |
623 | speed &= link_capabilities; | |
624 | ||
625 | if (speed == IXGBE_LINK_SPEED_UNKNOWN) | |
9a799d71 | 626 | status = IXGBE_ERR_LINK_SETUP; |
3201d313 PWJ |
627 | |
628 | /* Set KX4/KX support according to speed requested */ | |
629 | else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || | |
630 | link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { | |
631 | autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; | |
632 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) | |
633 | autoc |= IXGBE_AUTOC_KX4_SUPP; | |
634 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) | |
635 | autoc |= IXGBE_AUTOC_KX_SUPP; | |
636 | if (autoc != curr_autoc) | |
637 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); | |
9a799d71 AK |
638 | } |
639 | ||
640 | if (status == 0) { | |
641 | hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete; | |
642 | ||
9a799d71 AK |
643 | /* |
644 | * Setup and restart the link based on the new values in | |
645 | * ixgbe_hw This will write the AUTOC register based on the new | |
646 | * stored values | |
647 | */ | |
3201d313 | 648 | status = ixgbe_setup_mac_link_82598(hw); |
9a799d71 AK |
649 | } |
650 | ||
651 | return status; | |
652 | } | |
653 | ||
654 | ||
655 | /** | |
656 | * ixgbe_setup_copper_link_82598 - Setup copper link settings | |
657 | * @hw: pointer to hardware structure | |
658 | * | |
659 | * Configures link settings based on values in the ixgbe_hw struct. | |
660 | * Restarts the link. Performs autonegotiation if needed. Restart | |
661 | * phy and wait for autonegotiate to finish. Then synchronize the | |
662 | * MAC and PHY. | |
663 | **/ | |
664 | static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw) | |
665 | { | |
c44ade9e | 666 | s32 status; |
9a799d71 AK |
667 | |
668 | /* Restart autonegotiation on PHY */ | |
c44ade9e | 669 | status = hw->phy.ops.setup_link(hw); |
9a799d71 | 670 | |
3957d63d | 671 | /* Set up MAC */ |
c44ade9e | 672 | ixgbe_setup_mac_link_82598(hw); |
9a799d71 AK |
673 | |
674 | return status; | |
675 | } | |
676 | ||
677 | /** | |
678 | * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field | |
679 | * @hw: pointer to hardware structure | |
680 | * @speed: new link speed | |
681 | * @autoneg: true if autonegotiation enabled | |
682 | * @autoneg_wait_to_complete: true if waiting is needed to complete | |
683 | * | |
684 | * Sets the link speed in the AUTOC register in the MAC and restarts link. | |
685 | **/ | |
c44ade9e | 686 | static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, |
b4617240 PW |
687 | ixgbe_link_speed speed, |
688 | bool autoneg, | |
689 | bool autoneg_wait_to_complete) | |
9a799d71 | 690 | { |
c44ade9e | 691 | s32 status; |
9a799d71 AK |
692 | |
693 | /* Setup the PHY according to input speed */ | |
b4617240 PW |
694 | status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, |
695 | autoneg_wait_to_complete); | |
3957d63d | 696 | |
3957d63d | 697 | /* Set up MAC */ |
c44ade9e | 698 | ixgbe_setup_mac_link_82598(hw); |
9a799d71 AK |
699 | |
700 | return status; | |
701 | } | |
702 | ||
703 | /** | |
704 | * ixgbe_reset_hw_82598 - Performs hardware reset | |
705 | * @hw: pointer to hardware structure | |
706 | * | |
c44ade9e | 707 | * Resets the hardware by resetting the transmit and receive units, masks and |
9a799d71 AK |
708 | * clears all interrupts, performing a PHY reset, and performing a link (MAC) |
709 | * reset. | |
710 | **/ | |
711 | static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) | |
712 | { | |
713 | s32 status = 0; | |
8ca783ab | 714 | s32 phy_status = 0; |
9a799d71 AK |
715 | u32 ctrl; |
716 | u32 gheccr; | |
717 | u32 i; | |
718 | u32 autoc; | |
719 | u8 analog_val; | |
720 | ||
721 | /* Call adapter stop to disable tx/rx and clear interrupts */ | |
c44ade9e | 722 | hw->mac.ops.stop_adapter(hw); |
9a799d71 AK |
723 | |
724 | /* | |
c44ade9e JB |
725 | * Power up the Atlas Tx lanes if they are currently powered down. |
726 | * Atlas Tx lanes are powered down for MAC loopback tests, but | |
9a799d71 AK |
727 | * they are not automatically restored on reset. |
728 | */ | |
c44ade9e | 729 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); |
9a799d71 | 730 | if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { |
c44ade9e JB |
731 | /* Enable Tx Atlas so packets can be transmitted again */ |
732 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, | |
733 | &analog_val); | |
9a799d71 | 734 | analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; |
c44ade9e JB |
735 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, |
736 | analog_val); | |
9a799d71 | 737 | |
c44ade9e JB |
738 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, |
739 | &analog_val); | |
9a799d71 | 740 | analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; |
c44ade9e JB |
741 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, |
742 | analog_val); | |
9a799d71 | 743 | |
c44ade9e JB |
744 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, |
745 | &analog_val); | |
9a799d71 | 746 | analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; |
c44ade9e JB |
747 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, |
748 | analog_val); | |
9a799d71 | 749 | |
c44ade9e JB |
750 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, |
751 | &analog_val); | |
9a799d71 | 752 | analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; |
c44ade9e JB |
753 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, |
754 | analog_val); | |
9a799d71 AK |
755 | } |
756 | ||
757 | /* Reset PHY */ | |
04f165ef PW |
758 | if (hw->phy.reset_disable == false) { |
759 | /* PHY ops must be identified and initialized prior to reset */ | |
760 | ||
761 | /* Init PHY and function pointers, perform SFP setup */ | |
8ca783ab DS |
762 | phy_status = hw->phy.ops.init(hw); |
763 | if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
04f165ef | 764 | goto reset_hw_out; |
8ca783ab DS |
765 | else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT) |
766 | goto no_phy_reset; | |
767 | ||
04f165ef | 768 | |
c44ade9e | 769 | hw->phy.ops.reset(hw); |
04f165ef | 770 | } |
9a799d71 | 771 | |
8ca783ab | 772 | no_phy_reset: |
9a799d71 AK |
773 | /* |
774 | * Prevent the PCI-E bus from from hanging by disabling PCI-E master | |
775 | * access and verify no pending requests before reset | |
776 | */ | |
04f165ef PW |
777 | status = ixgbe_disable_pcie_master(hw); |
778 | if (status != 0) { | |
9a799d71 AK |
779 | status = IXGBE_ERR_MASTER_REQUESTS_PENDING; |
780 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | |
781 | } | |
782 | ||
783 | /* | |
784 | * Issue global reset to the MAC. This needs to be a SW reset. | |
785 | * If link reset is used, it might reset the MAC when mng is using it | |
786 | */ | |
787 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
788 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); | |
789 | IXGBE_WRITE_FLUSH(hw); | |
790 | ||
791 | /* Poll for reset bit to self-clear indicating reset is complete */ | |
792 | for (i = 0; i < 10; i++) { | |
793 | udelay(1); | |
794 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
795 | if (!(ctrl & IXGBE_CTRL_RST)) | |
796 | break; | |
797 | } | |
798 | if (ctrl & IXGBE_CTRL_RST) { | |
799 | status = IXGBE_ERR_RESET_FAILED; | |
800 | hw_dbg(hw, "Reset polling failed to complete.\n"); | |
801 | } | |
802 | ||
803 | msleep(50); | |
804 | ||
805 | gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); | |
806 | gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); | |
807 | IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); | |
808 | ||
809 | /* | |
3201d313 PWJ |
810 | * Store the original AUTOC value if it has not been |
811 | * stored off yet. Otherwise restore the stored original | |
812 | * AUTOC value since the reset operation sets back to deaults. | |
9a799d71 AK |
813 | */ |
814 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
3201d313 PWJ |
815 | if (hw->mac.orig_link_settings_stored == false) { |
816 | hw->mac.orig_autoc = autoc; | |
817 | hw->mac.orig_link_settings_stored = true; | |
818 | } else if (autoc != hw->mac.orig_autoc) { | |
819 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); | |
9a799d71 AK |
820 | } |
821 | ||
aca6bee7 WJP |
822 | /* |
823 | * Store MAC address from RAR0, clear receive address registers, and | |
824 | * clear the multicast table | |
825 | */ | |
826 | hw->mac.ops.init_rx_addrs(hw); | |
827 | ||
9a799d71 | 828 | /* Store the permanent mac address */ |
c44ade9e | 829 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); |
9a799d71 | 830 | |
04f165ef | 831 | reset_hw_out: |
8ca783ab DS |
832 | if (phy_status) |
833 | status = phy_status; | |
834 | ||
9a799d71 AK |
835 | return status; |
836 | } | |
837 | ||
c44ade9e JB |
838 | /** |
839 | * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address | |
840 | * @hw: pointer to hardware struct | |
841 | * @rar: receive address register index to associate with a VMDq index | |
842 | * @vmdq: VMDq set index | |
843 | **/ | |
e855aac8 | 844 | static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) |
c44ade9e JB |
845 | { |
846 | u32 rar_high; | |
847 | ||
848 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); | |
849 | rar_high &= ~IXGBE_RAH_VIND_MASK; | |
850 | rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); | |
851 | IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); | |
852 | return 0; | |
853 | } | |
854 | ||
855 | /** | |
856 | * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address | |
857 | * @hw: pointer to hardware struct | |
858 | * @rar: receive address register index to associate with a VMDq index | |
859 | * @vmdq: VMDq clear index (not used in 82598, but elsewhere) | |
860 | **/ | |
861 | static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) | |
862 | { | |
863 | u32 rar_high; | |
864 | u32 rar_entries = hw->mac.num_rar_entries; | |
865 | ||
866 | if (rar < rar_entries) { | |
867 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); | |
868 | if (rar_high & IXGBE_RAH_VIND_MASK) { | |
869 | rar_high &= ~IXGBE_RAH_VIND_MASK; | |
870 | IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); | |
871 | } | |
872 | } else { | |
873 | hw_dbg(hw, "RAR index %d is out of range.\n", rar); | |
874 | } | |
875 | ||
876 | return 0; | |
877 | } | |
878 | ||
879 | /** | |
880 | * ixgbe_set_vfta_82598 - Set VLAN filter table | |
881 | * @hw: pointer to hardware structure | |
882 | * @vlan: VLAN id to write to VLAN filter | |
883 | * @vind: VMDq output index that maps queue to VLAN id in VFTA | |
884 | * @vlan_on: boolean flag to turn on/off VLAN in VFTA | |
885 | * | |
886 | * Turn on/off specified VLAN in the VLAN filter table. | |
887 | **/ | |
e855aac8 HE |
888 | static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, |
889 | bool vlan_on) | |
c44ade9e JB |
890 | { |
891 | u32 regindex; | |
892 | u32 bitindex; | |
893 | u32 bits; | |
894 | u32 vftabyte; | |
895 | ||
896 | if (vlan > 4095) | |
897 | return IXGBE_ERR_PARAM; | |
898 | ||
899 | /* Determine 32-bit word position in array */ | |
900 | regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ | |
901 | ||
902 | /* Determine the location of the (VMD) queue index */ | |
903 | vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ | |
904 | bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ | |
905 | ||
906 | /* Set the nibble for VMD queue index */ | |
907 | bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); | |
908 | bits &= (~(0x0F << bitindex)); | |
909 | bits |= (vind << bitindex); | |
910 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); | |
911 | ||
912 | /* Determine the location of the bit for this VLAN id */ | |
913 | bitindex = vlan & 0x1F; /* lower five bits */ | |
914 | ||
915 | bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); | |
916 | if (vlan_on) | |
917 | /* Turn on this VLAN id */ | |
918 | bits |= (1 << bitindex); | |
919 | else | |
920 | /* Turn off this VLAN id */ | |
921 | bits &= ~(1 << bitindex); | |
922 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); | |
923 | ||
924 | return 0; | |
925 | } | |
926 | ||
927 | /** | |
928 | * ixgbe_clear_vfta_82598 - Clear VLAN filter table | |
929 | * @hw: pointer to hardware structure | |
930 | * | |
931 | * Clears the VLAN filer table, and the VMDq index associated with the filter | |
932 | **/ | |
933 | static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) | |
934 | { | |
935 | u32 offset; | |
936 | u32 vlanbyte; | |
937 | ||
938 | for (offset = 0; offset < hw->mac.vft_size; offset++) | |
939 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); | |
940 | ||
941 | for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) | |
942 | for (offset = 0; offset < hw->mac.vft_size; offset++) | |
943 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), | |
b4617240 | 944 | 0); |
c44ade9e JB |
945 | |
946 | return 0; | |
947 | } | |
948 | ||
c44ade9e JB |
949 | /** |
950 | * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register | |
951 | * @hw: pointer to hardware structure | |
952 | * @reg: analog register to read | |
953 | * @val: read value | |
954 | * | |
955 | * Performs read operation to Atlas analog register specified. | |
956 | **/ | |
e855aac8 | 957 | static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) |
c44ade9e JB |
958 | { |
959 | u32 atlas_ctl; | |
960 | ||
961 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, | |
962 | IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); | |
963 | IXGBE_WRITE_FLUSH(hw); | |
964 | udelay(10); | |
965 | atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); | |
966 | *val = (u8)atlas_ctl; | |
967 | ||
968 | return 0; | |
969 | } | |
970 | ||
971 | /** | |
972 | * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register | |
973 | * @hw: pointer to hardware structure | |
974 | * @reg: atlas register to write | |
975 | * @val: value to write | |
976 | * | |
977 | * Performs write operation to Atlas analog register specified. | |
978 | **/ | |
e855aac8 | 979 | static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) |
c44ade9e JB |
980 | { |
981 | u32 atlas_ctl; | |
982 | ||
983 | atlas_ctl = (reg << 8) | val; | |
984 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); | |
985 | IXGBE_WRITE_FLUSH(hw); | |
986 | udelay(10); | |
987 | ||
988 | return 0; | |
989 | } | |
990 | ||
c4900be0 DS |
991 | /** |
992 | * ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module | |
993 | * over I2C interface through an intermediate phy. | |
994 | * @hw: pointer to hardware structure | |
995 | * @byte_offset: EEPROM byte offset to read | |
996 | * @eeprom_data: value read | |
997 | * | |
998 | * Performs byte read operation to SFP module's EEPROM over I2C interface. | |
999 | **/ | |
e855aac8 HE |
1000 | static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, |
1001 | u8 *eeprom_data) | |
c4900be0 DS |
1002 | { |
1003 | s32 status = 0; | |
1004 | u16 sfp_addr = 0; | |
1005 | u16 sfp_data = 0; | |
1006 | u16 sfp_stat = 0; | |
1007 | u32 i; | |
1008 | ||
1009 | if (hw->phy.type == ixgbe_phy_nl) { | |
1010 | /* | |
1011 | * phy SDA/SCL registers are at addresses 0xC30A to | |
1012 | * 0xC30D. These registers are used to talk to the SFP+ | |
1013 | * module's EEPROM through the SDA/SCL (I2C) interface. | |
1014 | */ | |
1015 | sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; | |
1016 | sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); | |
1017 | hw->phy.ops.write_reg(hw, | |
1018 | IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, | |
6b73e10d | 1019 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
1020 | sfp_addr); |
1021 | ||
1022 | /* Poll status */ | |
1023 | for (i = 0; i < 100; i++) { | |
1024 | hw->phy.ops.read_reg(hw, | |
1025 | IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, | |
6b73e10d | 1026 | MDIO_MMD_PMAPMD, |
c4900be0 DS |
1027 | &sfp_stat); |
1028 | sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; | |
1029 | if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) | |
1030 | break; | |
1031 | msleep(10); | |
1032 | } | |
1033 | ||
1034 | if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { | |
1035 | hw_dbg(hw, "EEPROM read did not pass.\n"); | |
1036 | status = IXGBE_ERR_SFP_NOT_PRESENT; | |
1037 | goto out; | |
1038 | } | |
1039 | ||
1040 | /* Read data */ | |
1041 | hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, | |
6b73e10d | 1042 | MDIO_MMD_PMAPMD, &sfp_data); |
c4900be0 DS |
1043 | |
1044 | *eeprom_data = (u8)(sfp_data >> 8); | |
1045 | } else { | |
1046 | status = IXGBE_ERR_PHY; | |
1047 | goto out; | |
1048 | } | |
1049 | ||
1050 | out: | |
1051 | return status; | |
1052 | } | |
1053 | ||
c44ade9e JB |
1054 | /** |
1055 | * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type | |
1056 | * @hw: pointer to hardware structure | |
1057 | * | |
1058 | * Determines physical layer capabilities of the current configuration. | |
1059 | **/ | |
11afc1b1 | 1060 | static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) |
c44ade9e | 1061 | { |
11afc1b1 | 1062 | u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; |
04193058 PWJ |
1063 | u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
1064 | u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; | |
1065 | u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; | |
1066 | u16 ext_ability = 0; | |
1067 | ||
1068 | hw->phy.ops.identify(hw); | |
1069 | ||
1070 | /* Copper PHY must be checked before AUTOC LMS to determine correct | |
1071 | * physical layer because 10GBase-T PHYs use LMS = KX4/KX */ | |
1072 | if (hw->phy.type == ixgbe_phy_tn || | |
1073 | hw->phy.type == ixgbe_phy_cu_unknown) { | |
6b73e10d BH |
1074 | hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, |
1075 | &ext_ability); | |
1076 | if (ext_ability & MDIO_PMA_EXTABLE_10GBT) | |
04193058 | 1077 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; |
6b73e10d | 1078 | if (ext_ability & MDIO_PMA_EXTABLE_1000BT) |
04193058 | 1079 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; |
6b73e10d | 1080 | if (ext_ability & MDIO_PMA_EXTABLE_100BTX) |
04193058 PWJ |
1081 | physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; |
1082 | goto out; | |
1083 | } | |
c44ade9e | 1084 | |
04193058 PWJ |
1085 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { |
1086 | case IXGBE_AUTOC_LMS_1G_AN: | |
1087 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: | |
1088 | if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) | |
1089 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; | |
1090 | else | |
1091 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; | |
c4900be0 | 1092 | break; |
04193058 PWJ |
1093 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: |
1094 | if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) | |
1095 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; | |
1096 | else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) | |
1097 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; | |
1098 | else /* XAUI */ | |
1099 | physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; | |
c44ade9e | 1100 | break; |
04193058 PWJ |
1101 | case IXGBE_AUTOC_LMS_KX4_AN: |
1102 | case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: | |
1103 | if (autoc & IXGBE_AUTOC_KX_SUPP) | |
1104 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; | |
1105 | if (autoc & IXGBE_AUTOC_KX4_SUPP) | |
1106 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; | |
c44ade9e | 1107 | break; |
04193058 | 1108 | default: |
0befdb3e | 1109 | break; |
04193058 PWJ |
1110 | } |
1111 | ||
1112 | if (hw->phy.type == ixgbe_phy_nl) { | |
c4900be0 DS |
1113 | hw->phy.ops.identify_sfp(hw); |
1114 | ||
1115 | switch (hw->phy.sfp_type) { | |
1116 | case ixgbe_sfp_type_da_cu: | |
1117 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; | |
1118 | break; | |
1119 | case ixgbe_sfp_type_sr: | |
1120 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; | |
1121 | break; | |
1122 | case ixgbe_sfp_type_lr: | |
1123 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; | |
1124 | break; | |
1125 | default: | |
1126 | physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; | |
1127 | break; | |
1128 | } | |
04193058 | 1129 | } |
c44ade9e | 1130 | |
04193058 PWJ |
1131 | switch (hw->device_id) { |
1132 | case IXGBE_DEV_ID_82598_DA_DUAL_PORT: | |
1133 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; | |
1134 | break; | |
1135 | case IXGBE_DEV_ID_82598AF_DUAL_PORT: | |
1136 | case IXGBE_DEV_ID_82598AF_SINGLE_PORT: | |
1137 | case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: | |
1138 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; | |
1139 | break; | |
1140 | case IXGBE_DEV_ID_82598EB_XF_LR: | |
1141 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; | |
1142 | break; | |
c44ade9e | 1143 | default: |
c44ade9e JB |
1144 | break; |
1145 | } | |
1146 | ||
04193058 | 1147 | out: |
c44ade9e JB |
1148 | return physical_layer; |
1149 | } | |
1150 | ||
9a799d71 | 1151 | static struct ixgbe_mac_operations mac_ops_82598 = { |
c44ade9e JB |
1152 | .init_hw = &ixgbe_init_hw_generic, |
1153 | .reset_hw = &ixgbe_reset_hw_82598, | |
202ff1ec | 1154 | .start_hw = &ixgbe_start_hw_82598, |
c44ade9e | 1155 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, |
9a799d71 | 1156 | .get_media_type = &ixgbe_get_media_type_82598, |
c44ade9e | 1157 | .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598, |
11afc1b1 | 1158 | .enable_rx_dma = &ixgbe_enable_rx_dma_generic, |
c44ade9e JB |
1159 | .get_mac_addr = &ixgbe_get_mac_addr_generic, |
1160 | .stop_adapter = &ixgbe_stop_adapter_generic, | |
11afc1b1 PW |
1161 | .get_bus_info = &ixgbe_get_bus_info_generic, |
1162 | .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, | |
c44ade9e JB |
1163 | .read_analog_reg8 = &ixgbe_read_analog_reg8_82598, |
1164 | .write_analog_reg8 = &ixgbe_write_analog_reg8_82598, | |
3957d63d | 1165 | .setup_link = &ixgbe_setup_mac_link_82598, |
3957d63d | 1166 | .setup_link_speed = &ixgbe_setup_mac_link_speed_82598, |
c44ade9e JB |
1167 | .check_link = &ixgbe_check_mac_link_82598, |
1168 | .get_link_capabilities = &ixgbe_get_link_capabilities_82598, | |
1169 | .led_on = &ixgbe_led_on_generic, | |
1170 | .led_off = &ixgbe_led_off_generic, | |
87c12017 PW |
1171 | .blink_led_start = &ixgbe_blink_led_start_generic, |
1172 | .blink_led_stop = &ixgbe_blink_led_stop_generic, | |
c44ade9e JB |
1173 | .set_rar = &ixgbe_set_rar_generic, |
1174 | .clear_rar = &ixgbe_clear_rar_generic, | |
1175 | .set_vmdq = &ixgbe_set_vmdq_82598, | |
1176 | .clear_vmdq = &ixgbe_clear_vmdq_82598, | |
1177 | .init_rx_addrs = &ixgbe_init_rx_addrs_generic, | |
1178 | .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic, | |
1179 | .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, | |
1180 | .enable_mc = &ixgbe_enable_mc_generic, | |
1181 | .disable_mc = &ixgbe_disable_mc_generic, | |
1182 | .clear_vfta = &ixgbe_clear_vfta_82598, | |
1183 | .set_vfta = &ixgbe_set_vfta_82598, | |
620fa036 | 1184 | .fc_enable = &ixgbe_fc_enable_82598, |
c44ade9e JB |
1185 | }; |
1186 | ||
1187 | static struct ixgbe_eeprom_operations eeprom_ops_82598 = { | |
1188 | .init_params = &ixgbe_init_eeprom_params_generic, | |
1189 | .read = &ixgbe_read_eeprom_generic, | |
1190 | .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, | |
1191 | .update_checksum = &ixgbe_update_eeprom_checksum_generic, | |
1192 | }; | |
1193 | ||
1194 | static struct ixgbe_phy_operations phy_ops_82598 = { | |
1195 | .identify = &ixgbe_identify_phy_generic, | |
c4900be0 | 1196 | .identify_sfp = &ixgbe_identify_sfp_module_generic, |
04f165ef | 1197 | .init = &ixgbe_init_phy_ops_82598, |
c44ade9e JB |
1198 | .reset = &ixgbe_reset_phy_generic, |
1199 | .read_reg = &ixgbe_read_phy_reg_generic, | |
1200 | .write_reg = &ixgbe_write_phy_reg_generic, | |
1201 | .setup_link = &ixgbe_setup_phy_link_generic, | |
1202 | .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, | |
c4900be0 | 1203 | .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598, |
9a799d71 AK |
1204 | }; |
1205 | ||
3957d63d | 1206 | struct ixgbe_info ixgbe_82598_info = { |
9a799d71 AK |
1207 | .mac = ixgbe_mac_82598EB, |
1208 | .get_invariants = &ixgbe_get_invariants_82598, | |
1209 | .mac_ops = &mac_ops_82598, | |
c44ade9e JB |
1210 | .eeprom_ops = &eeprom_ops_82598, |
1211 | .phy_ops = &phy_ops_82598, | |
9a799d71 AK |
1212 | }; |
1213 |