[net-next-2.6.git] / drivers / net / ixgbe / ixgbe.h

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2007 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  Linux NICS <linux.nics@intel.com>
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _IXGBE_H_
#define _IXGBE_H_

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/inet_lro.h>

#include "ixgbe_type.h"
#include "ixgbe_common.h"

#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
#include <linux/dca.h>
#endif

#define IXGBE_ERR(args...) printk(KERN_ERR "ixgbe: " args)

#define PFX "ixgbe: "
#define DPRINTK(nlevel, klevel, fmt, args...) \
	((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
	printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
		__FUNCTION__ , ## args)))

/* TX/RX descriptor defines */
#define IXGBE_DEFAULT_TXD		   1024
#define IXGBE_MAX_TXD			   4096
#define IXGBE_MIN_TXD			     64

#define IXGBE_DEFAULT_RXD		   1024
#define IXGBE_MAX_RXD			   4096
#define IXGBE_MIN_RXD			     64

#define IXGBE_DEFAULT_RXQ			   1
#define IXGBE_MAX_RXQ				   1
#define IXGBE_MIN_RXQ				   1

/* flow control */
#define IXGBE_DEFAULT_FCRTL		0x10000
#define IXGBE_MIN_FCRTL			   0x40
#define IXGBE_MAX_FCRTL			0x7FF80
#define IXGBE_DEFAULT_FCRTH		0x20000
#define IXGBE_MIN_FCRTH			  0x600
#define IXGBE_MAX_FCRTH			0x7FFF0
#define IXGBE_DEFAULT_FCPAUSE		 0xFFFF
#define IXGBE_MIN_FCPAUSE		      0
#define IXGBE_MAX_FCPAUSE		 0xFFFF

/* Supported Rx Buffer Sizes */
#define IXGBE_RXBUFFER_64    64     /* Used for packet split */
#define IXGBE_RXBUFFER_128   128    /* Used for packet split */
#define IXGBE_RXBUFFER_256   256    /* Used for packet split */
#define IXGBE_RXBUFFER_2048  2048

#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256

#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)

/* How many Tx Descriptors do we need to call netif_wake_queue? */
#define IXGBE_TX_QUEUE_WAKE 16

/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IXGBE_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define IXGBE_TX_FLAGS_CSUM		(u32)(1)
#define IXGBE_TX_FLAGS_VLAN		(u32)(1 << 1)
#define IXGBE_TX_FLAGS_TSO		(u32)(1 << 2)
#define IXGBE_TX_FLAGS_IPV4		(u32)(1 << 3)
#define IXGBE_TX_FLAGS_VLAN_MASK	0xffff0000
#define IXGBE_TX_FLAGS_VLAN_SHIFT	16

#define IXGBE_MAX_LRO_DESCRIPTORS       8
#define IXGBE_MAX_LRO_AGGREGATE         32

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct ixgbe_tx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	unsigned long time_stamp;
	u16 length;
	u16 next_to_watch;
};

struct ixgbe_rx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	struct page *page;
	dma_addr_t page_dma;
};

struct ixgbe_queue_stats {
	u64 packets;
	u64 bytes;
};

struct ixgbe_ring {
	void *desc;			/* descriptor ring memory */
	dma_addr_t dma;			/* phys. address of descriptor ring */
	unsigned int size;		/* length in bytes */
	unsigned int count;		/* amount of descriptors */
	unsigned int next_to_use;
	unsigned int next_to_clean;

	int queue_index; /* needed for multiqueue queue management */
	union {
		struct ixgbe_tx_buffer *tx_buffer_info;
		struct ixgbe_rx_buffer *rx_buffer_info;
	};

	u16 head;
	u16 tail;

	unsigned int total_bytes;
	unsigned int total_packets;

	u16 reg_idx; /* holds the special value that gets the hardware register
		      * offset associated with this ring, which is different
		      * for DCE and RSS modes */

#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
	/* cpu for tx queue */
	int cpu;
#endif
	struct net_lro_mgr lro_mgr;
	bool lro_used;
	struct ixgbe_queue_stats stats;
	u16 v_idx; /* maps directly to the index for this ring in the hardware
	           * vector array, can also be used for finding the bit in EICR
	           * and friends that represents the vector for this ring */


	u16 work_limit;                /* max work per interrupt */
	u16 rx_buf_len;
};

#define RING_F_VMDQ 1
#define RING_F_RSS  2
#define IXGBE_MAX_RSS_INDICES  16
#define IXGBE_MAX_VMDQ_INDICES 16
struct ixgbe_ring_feature {
	int indices;
	int mask;
};

#define MAX_RX_QUEUES 64
#define MAX_TX_QUEUES 32

/* MAX_MSIX_Q_VECTORS of these are allocated,
 * but we only use one per queue-specific vector.
 */
struct ixgbe_q_vector {
	struct ixgbe_adapter *adapter;
	struct napi_struct napi;
	DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
	DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
	u8 rxr_count;     /* Rx ring count assigned to this vector */
	u8 txr_count;     /* Tx ring count assigned to this vector */
	u8 tx_itr;
	u8 rx_itr;
	u32 eitr;
};

/* Helper macros to switch between ints/sec and what the register uses.
 * And yes, it's the same math going both ways.
 */
#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG

#define IXGBE_DESC_UNUSED(R) \
	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	(R)->next_to_clean - (R)->next_to_use - 1)

#define IXGBE_RX_DESC_ADV(R, i)	    \
	(&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
#define IXGBE_TX_DESC_ADV(R, i)	    \
	(&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
#define IXGBE_TX_CTXTDESC_ADV(R, i)	    \
	(&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))

#define IXGBE_MAX_JUMBO_FRAME_SIZE        16128

#define OTHER_VECTOR 1
#define NON_Q_VECTORS (OTHER_VECTOR)

#define MAX_MSIX_Q_VECTORS 16
#define MIN_MSIX_Q_VECTORS 2
#define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)

/* board specific private data structure */
struct ixgbe_adapter {
	struct timer_list watchdog_timer;
	struct vlan_group *vlgrp;
	u16 bd_number;
	struct work_struct reset_task;
	struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
	char name[MAX_MSIX_COUNT][IFNAMSIZ + 5];

	/* Interrupt Throttle Rate */
	u32 itr_setting;
	u16 eitr_low;
	u16 eitr_high;

	/* TX */
	struct ixgbe_ring *tx_ring;	/* One per active queue */
	int num_tx_queues;
	u64 restart_queue;
	u64 hw_csum_tx_good;
	u64 lsc_int;
	u64 hw_tso_ctxt;
	u64 hw_tso6_ctxt;
	u32 tx_timeout_count;
	bool detect_tx_hung;

	/* RX */
	struct ixgbe_ring *rx_ring;	/* One per active queue */
	int num_rx_queues;
	u64 hw_csum_rx_error;
	u64 hw_csum_rx_good;
	u64 non_eop_descs;
	int num_msix_vectors;
	struct ixgbe_ring_feature ring_feature[3];
	struct msix_entry *msix_entries;

	u64 rx_hdr_split;
	u32 alloc_rx_page_failed;
	u32 alloc_rx_buff_failed;

	/* Some features need tri-state capability,
	 * thus the additional *_CAPABLE flags.
	 */
	u32 flags;
#define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
#define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
#define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
#define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
#define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
#define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
#define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
#define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
#define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
#define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
#define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
#define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
#define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
#define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
#define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
#define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
#define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
#define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
#define IXGBE_FLAG_IN_WATCHDOG_TASK             (u32)(1 << 23)

/* default to trying for four seconds */
#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)

	/* OS defined structs */
	struct net_device *netdev;
	struct pci_dev *pdev;
	struct net_device_stats net_stats;

	/* structs defined in ixgbe_hw.h */
	struct ixgbe_hw hw;
	u16 msg_enable;
	struct ixgbe_hw_stats stats;

	/* Interrupt Throttle Rate */
	u32 eitr_param;

	unsigned long state;
	u64 tx_busy;
	u64 lro_aggregated;
	u64 lro_flushed;
	u64 lro_no_desc;
	unsigned int tx_ring_count;
	unsigned int rx_ring_count;

	u32 link_speed;
	bool link_up;
	unsigned long link_check_timeout;

	struct work_struct watchdog_task;
};

enum ixbge_state_t {
	__IXGBE_TESTING,
	__IXGBE_RESETTING,
	__IXGBE_DOWN
};

enum ixgbe_boards {
	board_82598,
};

extern struct ixgbe_info ixgbe_82598_info;

extern char ixgbe_driver_name[];
extern const char ixgbe_driver_version[];

extern int ixgbe_up(struct ixgbe_adapter *adapter);
extern void ixgbe_down(struct ixgbe_adapter *adapter);
extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
extern void ixgbe_reset(struct ixgbe_adapter *adapter);
extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
				    struct ixgbe_ring *rxdr);
extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
				    struct ixgbe_ring *txdr);

#endif /* _IXGBE_H_ */
Commit	Line	Data
9a799d71 AK	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
	4	Copyright(c) 1999 - 2007 Intel Corporation.
	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	Linux NICS <linux.nics@intel.com>
	24	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	25	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	26
	27	*******************************************************************************/
	28
	29	#ifndef _IXGBE_H_
	30	#define _IXGBE_H_
	31
	32	#include <linux/types.h>
	33	#include <linux/pci.h>
	34	#include <linux/netdevice.h>
177db6ff	35	#include <linux/inet_lro.h>
9a799d71 AK	36
	37	#include "ixgbe_type.h"
	38	#include "ixgbe_common.h"
	39
96b0e0f6	40	#if defined(CONFIG_DCA) \|\| defined(CONFIG_DCA_MODULE)
bd0362dd JC	41	#include <linux/dca.h>
bd0362dd JC	42	#endif
9a799d71 AK	43
	44	#define IXGBE_ERR(args...) printk(KERN_ERR "ixgbe: " args)
	45
	46	#define PFX "ixgbe: "
	47	#define DPRINTK(nlevel, klevel, fmt, args...) \
	48	((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
	49	printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
	50	__FUNCTION__ , ## args)))
	51
	52	/* TX/RX descriptor defines */
	53	#define IXGBE_DEFAULT_TXD 1024
	54	#define IXGBE_MAX_TXD 4096
	55	#define IXGBE_MIN_TXD 64
	56
	57	#define IXGBE_DEFAULT_RXD 1024
	58	#define IXGBE_MAX_RXD 4096
	59	#define IXGBE_MIN_RXD 64
	60
	61	#define IXGBE_DEFAULT_RXQ 1
	62	#define IXGBE_MAX_RXQ 1
	63	#define IXGBE_MIN_RXQ 1
	64
9a799d71 AK	65	/* flow control */
9a799d71 AK	66	#define IXGBE_DEFAULT_FCRTL 0x10000
2b9ade93	67	#define IXGBE_MIN_FCRTL 0x40
9a799d71 AK	68	#define IXGBE_MAX_FCRTL 0x7FF80
9a799d71 AK	69	#define IXGBE_DEFAULT_FCRTH 0x20000
2b9ade93	70	#define IXGBE_MIN_FCRTH 0x600
9a799d71	71	#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93	72	#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71 AK	73	#define IXGBE_MIN_FCPAUSE 0
	74	#define IXGBE_MAX_FCPAUSE 0xFFFF
	75
	76	/* Supported Rx Buffer Sizes */
	77	#define IXGBE_RXBUFFER_64 64 /* Used for packet split */
	78	#define IXGBE_RXBUFFER_128 128 /* Used for packet split */
	79	#define IXGBE_RXBUFFER_256 256 /* Used for packet split */
	80	#define IXGBE_RXBUFFER_2048 2048
	81
	82	#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
	83
	84	#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
	85
	86	/* How many Tx Descriptors do we need to call netif_wake_queue? */
	87	#define IXGBE_TX_QUEUE_WAKE 16
	88
	89	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	90	#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	91
	92	#define IXGBE_TX_FLAGS_CSUM (u32)(1)
	93	#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
	94	#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
	95	#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
	96	#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
	97	#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
	98
177db6ff MC	99	#define IXGBE_MAX_LRO_DESCRIPTORS 8
	100	#define IXGBE_MAX_LRO_AGGREGATE 32
	101
9a799d71 AK	102	/* wrapper around a pointer to a socket buffer,
	103	* so a DMA handle can be stored along with the buffer */
	104	struct ixgbe_tx_buffer {
	105	struct sk_buff *skb;
	106	dma_addr_t dma;
	107	unsigned long time_stamp;
	108	u16 length;
	109	u16 next_to_watch;
	110	};
	111
	112	struct ixgbe_rx_buffer {
	113	struct sk_buff *skb;
	114	dma_addr_t dma;
	115	struct page *page;
	116	dma_addr_t page_dma;
	117	};
	118
	119	struct ixgbe_queue_stats {
	120	u64 packets;
	121	u64 bytes;
	122	};
	123
	124	struct ixgbe_ring {
9a799d71 AK	125	void desc; / descriptor ring memory */
	126	dma_addr_t dma; /* phys. address of descriptor ring */
	127	unsigned int size; /* length in bytes */
	128	unsigned int count; /* amount of descriptors */
	129	unsigned int next_to_use;
	130	unsigned int next_to_clean;
	131
021230d4	132	int queue_index; /* needed for multiqueue queue management */
9a799d71 AK	133	union {
	134	struct ixgbe_tx_buffer *tx_buffer_info;
	135	struct ixgbe_rx_buffer *rx_buffer_info;
	136	};
	137
	138	u16 head;
	139	u16 tail;
	140
f494e8fa AV	141	unsigned int total_bytes;
f494e8fa AV	142	unsigned int total_packets;
9a799d71	143
021230d4 AV	144	u16 reg_idx; /* holds the special value that gets the hardware register
	145	* offset associated with this ring, which is different
	146	* for DCE and RSS modes */
bd0362dd	147
96b0e0f6	148	#if defined(CONFIG_DCA) \|\| defined(CONFIG_DCA_MODULE)
bd0362dd JC	149	/* cpu for tx queue */
	150	int cpu;
	151	#endif
177db6ff MC	152	struct net_lro_mgr lro_mgr;
177db6ff MC	153	bool lro_used;
9a799d71	154	struct ixgbe_queue_stats stats;
ff819cfb JB	155	u16 v_idx; /* maps directly to the index for this ring in the hardware
	156	* vector array, can also be used for finding the bit in EICR
	157	* and friends that represents the vector for this ring */
9a799d71	158
9a799d71	159
9a799d71	160	u16 work_limit; /* max work per interrupt */
7c6e0a43	161	u16 rx_buf_len;
9a799d71 AK	162	};
9a799d71 AK	163
021230d4 AV	164	#define RING_F_VMDQ 1
	165	#define RING_F_RSS 2
	166	#define IXGBE_MAX_RSS_INDICES 16
	167	#define IXGBE_MAX_VMDQ_INDICES 16
	168	struct ixgbe_ring_feature {
	169	int indices;
	170	int mask;
	171	};
	172
	173	#define MAX_RX_QUEUES 64
	174	#define MAX_TX_QUEUES 32
	175
	176	/* MAX_MSIX_Q_VECTORS of these are allocated,
	177	* but we only use one per queue-specific vector.
	178	*/
	179	struct ixgbe_q_vector {
	180	struct ixgbe_adapter *adapter;
	181	struct napi_struct napi;
	182	DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
	183	DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
	184	u8 rxr_count; /* Rx ring count assigned to this vector */
	185	u8 txr_count; /* Tx ring count assigned to this vector */
30efa5a3 JB	186	u8 tx_itr;
30efa5a3 JB	187	u8 rx_itr;
021230d4 AV	188	u32 eitr;
	189	};
	190
9a799d71 AK	191	/* Helper macros to switch between ints/sec and what the register uses.
	192	* And yes, it's the same math going both ways.
	193	*/
	194	#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
	195	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
	196	#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
	197
	198	#define IXGBE_DESC_UNUSED(R) \
	199	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	200	(R)->next_to_clean - (R)->next_to_use - 1)
	201
	202	#define IXGBE_RX_DESC_ADV(R, i) \
	203	(&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
	204	#define IXGBE_TX_DESC_ADV(R, i) \
	205	(&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
	206	#define IXGBE_TX_CTXTDESC_ADV(R, i) \
	207	(&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
	208
	209	#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
	210
021230d4 AV	211	#define OTHER_VECTOR 1
	212	#define NON_Q_VECTORS (OTHER_VECTOR)
	213
	214	#define MAX_MSIX_Q_VECTORS 16
	215	#define MIN_MSIX_Q_VECTORS 2
	216	#define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
	217	#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
	218
9a799d71 AK	219	/* board specific private data structure */
	220	struct ixgbe_adapter {
	221	struct timer_list watchdog_timer;
	222	struct vlan_group *vlgrp;
	223	u16 bd_number;
9a799d71	224	struct work_struct reset_task;
021230d4 AV	225	struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
021230d4 AV	226	char name[MAX_MSIX_COUNT][IFNAMSIZ + 5];
9a799d71	227
f494e8fa AV	228	/* Interrupt Throttle Rate */
	229	u32 itr_setting;
	230	u16 eitr_low;
	231	u16 eitr_high;
	232
9a799d71 AK	233	/* TX */
9a799d71 AK	234	struct ixgbe_ring tx_ring; / One per active queue */
30efa5a3	235	int num_tx_queues;
9a799d71	236	u64 restart_queue;
30efa5a3	237	u64 hw_csum_tx_good;
9a799d71 AK	238	u64 lsc_int;
	239	u64 hw_tso_ctxt;
	240	u64 hw_tso6_ctxt;
	241	u32 tx_timeout_count;
	242	bool detect_tx_hung;
	243
	244	/* RX */
	245	struct ixgbe_ring rx_ring; / One per active queue */
30efa5a3	246	int num_rx_queues;
9a799d71 AK	247	u64 hw_csum_rx_error;
	248	u64 hw_csum_rx_good;
	249	u64 non_eop_descs;
021230d4 AV	250	int num_msix_vectors;
021230d4 AV	251	struct ixgbe_ring_feature ring_feature[3];
9a799d71 AK	252	struct msix_entry *msix_entries;
	253
	254	u64 rx_hdr_split;
	255	u32 alloc_rx_page_failed;
	256	u32 alloc_rx_buff_failed;
	257
021230d4 AV	258	/* Some features need tri-state capability,
	259	* thus the additional *_CAPABLE flags.
	260	*/
9a799d71	261	u32 flags;
96b0e0f6 JB	262	#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
	263	#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
	264	#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
	265	#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
	266	#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
	267	#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
	268	#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
	269	#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
	270	#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
	271	#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
	272	#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
	273	#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
	274	#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
	275	#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
	276	#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
	277	#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
	278	#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
	279	#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
	280	#define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 23)
	281
	282	/* default to trying for four seconds */
	283	#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71 AK	284
	285	/* OS defined structs */
	286	struct net_device *netdev;
	287	struct pci_dev *pdev;
	288	struct net_device_stats net_stats;
	289
	290	/* structs defined in ixgbe_hw.h */
	291	struct ixgbe_hw hw;
	292	u16 msg_enable;
	293	struct ixgbe_hw_stats stats;
021230d4 AV	294
021230d4 AV	295	/* Interrupt Throttle Rate */
30efa5a3	296	u32 eitr_param;
9a799d71 AK	297
	298	unsigned long state;
	299	u64 tx_busy;
177db6ff MC	300	u64 lro_aggregated;
	301	u64 lro_flushed;
	302	u64 lro_no_desc;
30efa5a3 JB	303	unsigned int tx_ring_count;
30efa5a3 JB	304	unsigned int rx_ring_count;
cf8280ee JB	305
	306	u32 link_speed;
	307	bool link_up;
	308	unsigned long link_check_timeout;
	309
	310	struct work_struct watchdog_task;
9a799d71 AK	311	};
	312
	313	enum ixbge_state_t {
	314	__IXGBE_TESTING,
	315	__IXGBE_RESETTING,
	316	__IXGBE_DOWN
	317	};
	318
	319	enum ixgbe_boards {
3957d63d	320	board_82598,
9a799d71 AK	321	};
9a799d71 AK	322
3957d63d	323	extern struct ixgbe_info ixgbe_82598_info;
9a799d71 AK	324
9a799d71 AK	325	extern char ixgbe_driver_name[];
9c8eb720	326	extern const char ixgbe_driver_version[];
9a799d71 AK	327
	328	extern int ixgbe_up(struct ixgbe_adapter *adapter);
	329	extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882	330	extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71 AK	331	extern void ixgbe_reset(struct ixgbe_adapter *adapter);
	332	extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
	333	extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
	334	extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
	335	struct ixgbe_ring *rxdr);
	336	extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
	337	struct ixgbe_ring *txdr);
	338
	339	#endif /* _IXGBE_H_ */