[net-next-2.6.git] / drivers / net / ixgbe / ixgbe.h

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2007 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  Linux NICS <linux.nics@intel.com>
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _IXGBE_H_
#define _IXGBE_H_

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/netdevice.h>

#include "ixgbe_type.h"
#include "ixgbe_common.h"


#define IXGBE_ERR(args...) printk(KERN_ERR "ixgbe: " args)

#define PFX "ixgbe: "
#define DPRINTK(nlevel, klevel, fmt, args...) \
	((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
	printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
		__FUNCTION__ , ## args)))

/* TX/RX descriptor defines */
#define IXGBE_DEFAULT_TXD		   1024
#define IXGBE_MAX_TXD			   4096
#define IXGBE_MIN_TXD			     64

#define IXGBE_DEFAULT_RXD		   1024
#define IXGBE_MAX_RXD			   4096
#define IXGBE_MIN_RXD			     64

#define IXGBE_DEFAULT_RXQ			   1
#define IXGBE_MAX_RXQ				   1
#define IXGBE_MIN_RXQ				   1

#define IXGBE_DEFAULT_ITR_RX_USECS	    125  /*   8k irqs/sec */
#define IXGBE_DEFAULT_ITR_TX_USECS	    250  /*   4k irqs/sec */
#define IXGBE_MIN_ITR_USECS		    100  /* 500k irqs/sec */
#define IXGBE_MAX_ITR_USECS		  10000  /* 100  irqs/sec */

/* flow control */
#define IXGBE_DEFAULT_FCRTL		0x10000
#define IXGBE_MIN_FCRTL			      0
#define IXGBE_MAX_FCRTL			0x7FF80
#define IXGBE_DEFAULT_FCRTH		0x20000
#define IXGBE_MIN_FCRTH			      0
#define IXGBE_MAX_FCRTH			0x7FFF0
#define IXGBE_DEFAULT_FCPAUSE		 0x6800  /* may be too long */
#define IXGBE_MIN_FCPAUSE		      0
#define IXGBE_MAX_FCPAUSE		 0xFFFF

/* Supported Rx Buffer Sizes */
#define IXGBE_RXBUFFER_64    64     /* Used for packet split */
#define IXGBE_RXBUFFER_128   128    /* Used for packet split */
#define IXGBE_RXBUFFER_256   256    /* Used for packet split */
#define IXGBE_RXBUFFER_2048  2048

#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256

#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)

/* How many Tx Descriptors do we need to call netif_wake_queue? */
#define IXGBE_TX_QUEUE_WAKE 16

/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IXGBE_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define IXGBE_TX_FLAGS_CSUM		(u32)(1)
#define IXGBE_TX_FLAGS_VLAN		(u32)(1 << 1)
#define IXGBE_TX_FLAGS_TSO		(u32)(1 << 2)
#define IXGBE_TX_FLAGS_IPV4		(u32)(1 << 3)
#define IXGBE_TX_FLAGS_VLAN_MASK	0xffff0000
#define IXGBE_TX_FLAGS_VLAN_SHIFT	16

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct ixgbe_tx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	unsigned long time_stamp;
	u16 length;
	u16 next_to_watch;
};

struct ixgbe_rx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	struct page *page;
	dma_addr_t page_dma;
};

struct ixgbe_queue_stats {
	u64 packets;
	u64 bytes;
};

struct ixgbe_ring {
	void *desc;			/* descriptor ring memory */
	dma_addr_t dma;			/* phys. address of descriptor ring */
	unsigned int size;		/* length in bytes */
	unsigned int count;		/* amount of descriptors */
	unsigned int next_to_use;
	unsigned int next_to_clean;

	int queue_index; /* needed for multiqueue queue management */
	union {
		struct ixgbe_tx_buffer *tx_buffer_info;
		struct ixgbe_rx_buffer *rx_buffer_info;
	};

	u16 head;
	u16 tail;

	unsigned int total_bytes;
	unsigned int total_packets;

	u16 reg_idx; /* holds the special value that gets the hardware register
		      * offset associated with this ring, which is different
		      * for DCE and RSS modes */
	struct ixgbe_queue_stats stats;
	u8 v_idx; /* maps directly to the index for this ring in the hardware
		   * vector array, can also be used for finding the bit in EICR
		   * and friends that represents the vector for this ring */

	u32 eims_value;
	u16 itr_register;

	char name[IFNAMSIZ + 5];
	u16 work_limit;                /* max work per interrupt */
};

#define RING_F_VMDQ 1
#define RING_F_RSS  2
#define IXGBE_MAX_RSS_INDICES  16
#define IXGBE_MAX_VMDQ_INDICES 16
struct ixgbe_ring_feature {
	int indices;
	int mask;
};

#define MAX_RX_QUEUES 64
#define MAX_TX_QUEUES 32

/* MAX_MSIX_Q_VECTORS of these are allocated,
 * but we only use one per queue-specific vector.
 */
struct ixgbe_q_vector {
	struct ixgbe_adapter *adapter;
	struct napi_struct napi;
	DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
	DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
	u8 rxr_count;     /* Rx ring count assigned to this vector */
	u8 txr_count;     /* Tx ring count assigned to this vector */
	u8 tx_eitr;
	u8 rx_eitr;
	u32 eitr;
};

/* Helper macros to switch between ints/sec and what the register uses.
 * And yes, it's the same math going both ways.
 */
#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG

#define IXGBE_DESC_UNUSED(R) \
	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	(R)->next_to_clean - (R)->next_to_use - 1)

#define IXGBE_RX_DESC_ADV(R, i)	    \
	(&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
#define IXGBE_TX_DESC_ADV(R, i)	    \
	(&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
#define IXGBE_TX_CTXTDESC_ADV(R, i)	    \
	(&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))

#define IXGBE_MAX_JUMBO_FRAME_SIZE        16128

#define OTHER_VECTOR 1
#define NON_Q_VECTORS (OTHER_VECTOR)

#define MAX_MSIX_Q_VECTORS 16
#define MIN_MSIX_Q_VECTORS 2
#define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)

/* board specific private data structure */
struct ixgbe_adapter {
	struct timer_list watchdog_timer;
	struct vlan_group *vlgrp;
	u16 bd_number;
	u16 rx_buf_len;
	struct work_struct reset_task;
	struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
	char name[MAX_MSIX_COUNT][IFNAMSIZ + 5];

	/* Interrupt Throttle Rate */
	u32 itr_setting;
	u16 eitr_low;
	u16 eitr_high;

	/* TX */
	struct ixgbe_ring *tx_ring;	/* One per active queue */
	u64 restart_queue;
	u64 lsc_int;
	u64 hw_tso_ctxt;
	u64 hw_tso6_ctxt;
	u32 tx_timeout_count;
	bool detect_tx_hung;

	/* RX */
	struct ixgbe_ring *rx_ring;	/* One per active queue */
	u64 hw_csum_tx_good;
	u64 hw_csum_rx_error;
	u64 hw_csum_rx_good;
	u64 non_eop_descs;
	int num_tx_queues;
	int num_rx_queues;
	int num_msix_vectors;
	struct ixgbe_ring_feature ring_feature[3];
	struct msix_entry *msix_entries;

	u64 rx_hdr_split;
	u32 alloc_rx_page_failed;
	u32 alloc_rx_buff_failed;

	/* Some features need tri-state capability,
	 * thus the additional *_CAPABLE flags.
	 */
	u32 flags;
#define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1 << 0)
#define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 1)
#define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 2)
#define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 3)
#define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 4)
#define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 5)
#define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 6)
#define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 7)

	/* OS defined structs */
	struct net_device *netdev;
	struct pci_dev *pdev;
	struct net_device_stats net_stats;

	/* structs defined in ixgbe_hw.h */
	struct ixgbe_hw hw;
	u16 msg_enable;
	struct ixgbe_hw_stats stats;

	/* Interrupt Throttle Rate */
	u32 rx_eitr;
	u32 tx_eitr;

	unsigned long state;
	u64 tx_busy;
};

enum ixbge_state_t {
	__IXGBE_TESTING,
	__IXGBE_RESETTING,
	__IXGBE_DOWN
};

enum ixgbe_boards {
	board_82598,
};

extern struct ixgbe_info ixgbe_82598_info;

extern char ixgbe_driver_name[];
extern const char ixgbe_driver_version[];

extern int ixgbe_up(struct ixgbe_adapter *adapter);
extern void ixgbe_down(struct ixgbe_adapter *adapter);
extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
extern void ixgbe_reset(struct ixgbe_adapter *adapter);
extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
				    struct ixgbe_ring *rxdr);
extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
				    struct ixgbe_ring *txdr);

#endif /* _IXGBE_H_ */
Commit	Line	Data
9a799d71 AK	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
	4	Copyright(c) 1999 - 2007 Intel Corporation.
	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	Linux NICS <linux.nics@intel.com>
	24	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	25	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	26
	27	*******************************************************************************/
	28
	29	#ifndef _IXGBE_H_
	30	#define _IXGBE_H_
	31
	32	#include <linux/types.h>
	33	#include <linux/pci.h>
	34	#include <linux/netdevice.h>
	35
	36	#include "ixgbe_type.h"
	37	#include "ixgbe_common.h"
	38
	39
	40	#define IXGBE_ERR(args...) printk(KERN_ERR "ixgbe: " args)
	41
	42	#define PFX "ixgbe: "
	43	#define DPRINTK(nlevel, klevel, fmt, args...) \
	44	((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
	45	printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
	46	__FUNCTION__ , ## args)))
	47
	48	/* TX/RX descriptor defines */
	49	#define IXGBE_DEFAULT_TXD 1024
	50	#define IXGBE_MAX_TXD 4096
	51	#define IXGBE_MIN_TXD 64
	52
	53	#define IXGBE_DEFAULT_RXD 1024
	54	#define IXGBE_MAX_RXD 4096
	55	#define IXGBE_MIN_RXD 64
	56
	57	#define IXGBE_DEFAULT_RXQ 1
	58	#define IXGBE_MAX_RXQ 1
	59	#define IXGBE_MIN_RXQ 1
	60
	61	#define IXGBE_DEFAULT_ITR_RX_USECS 125 /* 8k irqs/sec */
	62	#define IXGBE_DEFAULT_ITR_TX_USECS 250 /* 4k irqs/sec */
	63	#define IXGBE_MIN_ITR_USECS 100 /* 500k irqs/sec */
	64	#define IXGBE_MAX_ITR_USECS 10000 /* 100 irqs/sec */
65
66	/* flow control */
67	#define IXGBE_DEFAULT_FCRTL 0x10000
68	#define IXGBE_MIN_FCRTL 0
69	#define IXGBE_MAX_FCRTL 0x7FF80
70	#define IXGBE_DEFAULT_FCRTH 0x20000
71	#define IXGBE_MIN_FCRTH 0
72	#define IXGBE_MAX_FCRTH 0x7FFF0
73	#define IXGBE_DEFAULT_FCPAUSE 0x6800 /* may be too long */
74	#define IXGBE_MIN_FCPAUSE 0
75	#define IXGBE_MAX_FCPAUSE 0xFFFF
76
77	/* Supported Rx Buffer Sizes */
78	#define IXGBE_RXBUFFER_64 64 /* Used for packet split */
79	#define IXGBE_RXBUFFER_128 128 /* Used for packet split */
80	#define IXGBE_RXBUFFER_256 256 /* Used for packet split */
81	#define IXGBE_RXBUFFER_2048 2048
82
83	#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
84
85	#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
86
87	/* How many Tx Descriptors do we need to call netif_wake_queue? */
88	#define IXGBE_TX_QUEUE_WAKE 16
89
90	/* How many Rx Buffers do we bundle into one write to the hardware ? */
91	#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
92
93	#define IXGBE_TX_FLAGS_CSUM (u32)(1)
94	#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
95	#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
96	#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
97	#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
98	#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
99
100	/* wrapper around a pointer to a socket buffer,
101	* so a DMA handle can be stored along with the buffer */
102	struct ixgbe_tx_buffer {
103	struct sk_buff *skb;
104	dma_addr_t dma;
105	unsigned long time_stamp;
106	u16 length;
107	u16 next_to_watch;
108	};
109
110	struct ixgbe_rx_buffer {
111	struct sk_buff *skb;
112	dma_addr_t dma;
113	struct page *page;
114	dma_addr_t page_dma;
115	};
116
117	struct ixgbe_queue_stats {
118	u64 packets;
119	u64 bytes;
120	};
121
122	struct ixgbe_ring {
9a799d71 AK	123	void desc; / descriptor ring memory */
	124	dma_addr_t dma; /* phys. address of descriptor ring */
	125	unsigned int size; /* length in bytes */
	126	unsigned int count; /* amount of descriptors */
	127	unsigned int next_to_use;
	128	unsigned int next_to_clean;
	129
021230d4	130	int queue_index; /* needed for multiqueue queue management */
9a799d71 AK	131	union {
	132	struct ixgbe_tx_buffer *tx_buffer_info;
	133	struct ixgbe_rx_buffer *rx_buffer_info;
	134	};
	135
	136	u16 head;
	137	u16 tail;
	138
f494e8fa AV	139	unsigned int total_bytes;
f494e8fa AV	140	unsigned int total_packets;
9a799d71	141
021230d4 AV	142	u16 reg_idx; /* holds the special value that gets the hardware register
	143	* offset associated with this ring, which is different
	144	* for DCE and RSS modes */
9a799d71	145	struct ixgbe_queue_stats stats;
021230d4 AV	146	u8 v_idx; /* maps directly to the index for this ring in the hardware
	147	* vector array, can also be used for finding the bit in EICR
	148	* and friends that represents the vector for this ring */
9a799d71 AK	149
	150	u32 eims_value;
	151	u16 itr_register;
	152
	153	char name[IFNAMSIZ + 5];
	154	u16 work_limit; /* max work per interrupt */
	155	};
	156
021230d4 AV	157	#define RING_F_VMDQ 1
	158	#define RING_F_RSS 2
	159	#define IXGBE_MAX_RSS_INDICES 16
	160	#define IXGBE_MAX_VMDQ_INDICES 16
	161	struct ixgbe_ring_feature {
	162	int indices;
	163	int mask;
	164	};
	165
	166	#define MAX_RX_QUEUES 64
	167	#define MAX_TX_QUEUES 32
	168
	169	/* MAX_MSIX_Q_VECTORS of these are allocated,
	170	* but we only use one per queue-specific vector.
	171	*/
	172	struct ixgbe_q_vector {
	173	struct ixgbe_adapter *adapter;
	174	struct napi_struct napi;
	175	DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
	176	DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
	177	u8 rxr_count; /* Rx ring count assigned to this vector */
	178	u8 txr_count; /* Tx ring count assigned to this vector */
f494e8fa AV	179	u8 tx_eitr;
f494e8fa AV	180	u8 rx_eitr;
021230d4 AV	181	u32 eitr;
	182	};
	183
9a799d71 AK	184	/* Helper macros to switch between ints/sec and what the register uses.
	185	* And yes, it's the same math going both ways.
	186	*/
	187	#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
	188	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
	189	#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
	190
	191	#define IXGBE_DESC_UNUSED(R) \
	192	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	193	(R)->next_to_clean - (R)->next_to_use - 1)
	194
	195	#define IXGBE_RX_DESC_ADV(R, i) \
	196	(&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
	197	#define IXGBE_TX_DESC_ADV(R, i) \
	198	(&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
	199	#define IXGBE_TX_CTXTDESC_ADV(R, i) \
	200	(&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
	201
	202	#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
	203
021230d4 AV	204	#define OTHER_VECTOR 1
	205	#define NON_Q_VECTORS (OTHER_VECTOR)
	206
	207	#define MAX_MSIX_Q_VECTORS 16
	208	#define MIN_MSIX_Q_VECTORS 2
	209	#define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
	210	#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
	211
9a799d71 AK	212	/* board specific private data structure */
	213	struct ixgbe_adapter {
	214	struct timer_list watchdog_timer;
	215	struct vlan_group *vlgrp;
	216	u16 bd_number;
	217	u16 rx_buf_len;
9a799d71	218	struct work_struct reset_task;
021230d4 AV	219	struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
021230d4 AV	220	char name[MAX_MSIX_COUNT][IFNAMSIZ + 5];
9a799d71	221
f494e8fa AV	222	/* Interrupt Throttle Rate */
	223	u32 itr_setting;
	224	u16 eitr_low;
	225	u16 eitr_high;
	226
9a799d71 AK	227	/* TX */
9a799d71 AK	228	struct ixgbe_ring tx_ring; / One per active queue */
9a799d71 AK	229	u64 restart_queue;
	230	u64 lsc_int;
	231	u64 hw_tso_ctxt;
	232	u64 hw_tso6_ctxt;
	233	u32 tx_timeout_count;
	234	bool detect_tx_hung;
	235
	236	/* RX */
	237	struct ixgbe_ring rx_ring; / One per active queue */
	238	u64 hw_csum_tx_good;
	239	u64 hw_csum_rx_error;
	240	u64 hw_csum_rx_good;
	241	u64 non_eop_descs;
	242	int num_tx_queues;
	243	int num_rx_queues;
021230d4 AV	244	int num_msix_vectors;
021230d4 AV	245	struct ixgbe_ring_feature ring_feature[3];
9a799d71 AK	246	struct msix_entry *msix_entries;
	247
	248	u64 rx_hdr_split;
	249	u32 alloc_rx_page_failed;
	250	u32 alloc_rx_buff_failed;
	251
021230d4 AV	252	/* Some features need tri-state capability,
	253	* thus the additional *_CAPABLE flags.
	254	*/
9a799d71	255	u32 flags;
021230d4	256	#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1 << 0)
9a799d71	257	#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1)
021230d4 AV	258	#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 2)
	259	#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 3)
	260	#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 4)
	261	#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 5)
	262	#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 6)
	263	#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7)
9a799d71 AK	264
	265	/* OS defined structs */
	266	struct net_device *netdev;
	267	struct pci_dev *pdev;
	268	struct net_device_stats net_stats;
	269
	270	/* structs defined in ixgbe_hw.h */
	271	struct ixgbe_hw hw;
	272	u16 msg_enable;
	273	struct ixgbe_hw_stats stats;
021230d4 AV	274
	275	/* Interrupt Throttle Rate */
	276	u32 rx_eitr;
	277	u32 tx_eitr;
9a799d71 AK	278
	279	unsigned long state;
	280	u64 tx_busy;
	281	};
	282
	283	enum ixbge_state_t {
	284	__IXGBE_TESTING,
	285	__IXGBE_RESETTING,
	286	__IXGBE_DOWN
	287	};
	288
	289	enum ixgbe_boards {
3957d63d	290	board_82598,
9a799d71 AK	291	};
9a799d71 AK	292
3957d63d	293	extern struct ixgbe_info ixgbe_82598_info;
9a799d71 AK	294
9a799d71 AK	295	extern char ixgbe_driver_name[];
9c8eb720	296	extern const char ixgbe_driver_version[];
9a799d71 AK	297
	298	extern int ixgbe_up(struct ixgbe_adapter *adapter);
	299	extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882	300	extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71 AK	301	extern void ixgbe_reset(struct ixgbe_adapter *adapter);
	302	extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
	303	extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
	304	extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
	305	struct ixgbe_ring *rxdr);
	306	extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
	307	struct ixgbe_ring *txdr);
	308
	309	#endif /* _IXGBE_H_ */