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[net-next-2.6.git] / drivers / net / ixgbe / ixgbe.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
31#include <linux/types.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
6fabd715 34#include <linux/aer.h>
9a799d71
AK		 35
36#include "ixgbe_type.h"
37#include "ixgbe_common.h"
2f90b865 38#include "ixgbe_dcb.h"
eacd73f7
YZ		 39#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
40#define IXGBE_FCOE
41#include "ixgbe_fcoe.h"
42#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332 43#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 44#include <linux/dca.h>
45#endif
9a799d71 46
9a799d71
AK		 47#define PFX "ixgbe: "
48#define DPRINTK(nlevel, klevel, fmt, args...) \
49 ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
50 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
b39d66a8 51 __func__ , ## args)))
9a799d71
AK		 52
53/* TX/RX descriptor defines */
54#define IXGBE_DEFAULT_TXD 1024
55#define IXGBE_MAX_TXD 4096
56#define IXGBE_MIN_TXD 64
57
58#define IXGBE_DEFAULT_RXD 1024
59#define IXGBE_MAX_RXD 4096
60#define IXGBE_MIN_RXD 64
61
9a799d71
AK		 62/* flow control */
63#define IXGBE_DEFAULT_FCRTL 0x10000
2b9ade93 64#define IXGBE_MIN_FCRTL 0x40
9a799d71
AK		 65#define IXGBE_MAX_FCRTL 0x7FF80
66#define IXGBE_DEFAULT_FCRTH 0x20000
2b9ade93 67#define IXGBE_MIN_FCRTH 0x600
9a799d71 68#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93 69#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71
AK		 70#define IXGBE_MIN_FCPAUSE 0
71#define IXGBE_MAX_FCPAUSE 0xFFFF
72
73/* Supported Rx Buffer Sizes */
74#define IXGBE_RXBUFFER_64 64 /* Used for packet split */
75#define IXGBE_RXBUFFER_128 128 /* Used for packet split */
76#define IXGBE_RXBUFFER_256 256 /* Used for packet split */
77#define IXGBE_RXBUFFER_2048 2048
e76678dd
AD		 78#define IXGBE_RXBUFFER_4096 4096
79#define IXGBE_RXBUFFER_8192 8192
32344a39 80#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71
AK		 81
82#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
83
84#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
85
9a799d71
AK		 86/* How many Rx Buffers do we bundle into one write to the hardware ? */
87#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
88
89#define IXGBE_TX_FLAGS_CSUM (u32)(1)
90#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
91#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
92#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
eacd73f7
YZ		 93#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
94#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
9a799d71 95#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
2f90b865 96#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
9a799d71
AK		 97#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
98
99/* wrapper around a pointer to a socket buffer,
100 * so a DMA handle can be stored along with the buffer */
101struct ixgbe_tx_buffer {
102 struct sk_buff *skb;
103 dma_addr_t dma;
104 unsigned long time_stamp;
105 u16 length;
106 u16 next_to_watch;
107};
108
109struct ixgbe_rx_buffer {
110 struct sk_buff *skb;
111 dma_addr_t dma;
112 struct page *page;
113 dma_addr_t page_dma;
762f4c57 114 unsigned int page_offset;
9a799d71
AK		 115};
116
117struct ixgbe_queue_stats {
118 u64 packets;
119 u64 bytes;
120};
121
122struct ixgbe_ring {
9a799d71
AK		 123 void *desc; /* descriptor ring memory */
124 dma_addr_t dma; /* phys. address of descriptor ring */
125 unsigned int size; /* length in bytes */
126 unsigned int count; /* amount of descriptors */
127 unsigned int next_to_use;
128 unsigned int next_to_clean;
c4cf55e5
PWJ		 129 u8 atr_sample_rate;
130 u8 atr_count;
9a799d71 131
021230d4 132 int queue_index; /* needed for multiqueue queue management */
9a799d71
AK		 133 union {
134 struct ixgbe_tx_buffer *tx_buffer_info;
135 struct ixgbe_rx_buffer *rx_buffer_info;
136 };
137
138 u16 head;
139 u16 tail;
140
f494e8fa
AV		 141 unsigned int total_bytes;
142 unsigned int total_packets;
9a799d71 143
021230d4
AV		 144 u16 reg_idx; /* holds the special value that gets the hardware register
145 * offset associated with this ring, which is different
2f90b865 146 * for DCB and RSS modes */
bd0362dd 147
5dd2d332 148#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 149 /* cpu for tx queue */
150 int cpu;
151#endif
9a799d71 152 struct ixgbe_queue_stats stats;
c4cf55e5 153 unsigned long reinit_state;
9a799d71 154
9a799d71 155 u16 work_limit; /* max work per interrupt */
7c6e0a43 156 u16 rx_buf_len;
f8212f97 157 u64 rsc_count; /* stat for coalesced packets */
9a799d71
AK		 158};
159
c7e4358a
SN		 160enum ixgbe_ring_f_enum {
161 RING_F_NONE = 0,
162 RING_F_DCB,
163 RING_F_VMDQ,
164 RING_F_RSS,
c4cf55e5 165 RING_F_FDIR,
0331a832
YZ		 166#ifdef IXGBE_FCOE
167 RING_F_FCOE,
168#endif /* IXGBE_FCOE */
c7e4358a
SN		 169
170 RING_F_ARRAY_SIZE /* must be last in enum set */
171};
172
2f90b865 173#define IXGBE_MAX_DCB_INDICES 8
021230d4
AV		 174#define IXGBE_MAX_RSS_INDICES 16
175#define IXGBE_MAX_VMDQ_INDICES 16
c4cf55e5 176#define IXGBE_MAX_FDIR_INDICES 64
0331a832
YZ		 177#ifdef IXGBE_FCOE
178#define IXGBE_MAX_FCOE_INDICES 8
179#endif /* IXGBE_FCOE */
021230d4
AV		 180struct ixgbe_ring_feature {
181 int indices;
182 int mask;
183};
184
e8e26350
PW		 185#define MAX_RX_QUEUES 128
186#define MAX_TX_QUEUES 128
021230d4 187
2f90b865
AD		 188#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
189 ? 8 : 1)
190#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
191
021230d4
AV		 192/* MAX_MSIX_Q_VECTORS of these are allocated,
193 * but we only use one per queue-specific vector.
194 */
195struct ixgbe_q_vector {
196 struct ixgbe_adapter *adapter;
fe49f04a
AD		 197 unsigned int v_idx; /* index of q_vector within array, also used for
198 * finding the bit in EICR and friends that
199 * represents the vector for this ring */
021230d4
AV		 200 struct napi_struct napi;
201 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
202 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
203 u8 rxr_count; /* Rx ring count assigned to this vector */
204 u8 txr_count; /* Tx ring count assigned to this vector */
30efa5a3
JB		 205 u8 tx_itr;
206 u8 rx_itr;
021230d4
AV		 207 u32 eitr;
208};
209
9a799d71 210/* Helper macros to switch between ints/sec and what the register uses.
509ee935
JB		 211 * And yes, it's the same math going both ways. The lowest value
212 * supported by all of the ixgbe hardware is 8.
9a799d71
AK		 213 */
214#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
509ee935 215 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
9a799d71
AK		 216#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
217
218#define IXGBE_DESC_UNUSED(R) \
219 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
220 (R)->next_to_clean - (R)->next_to_use - 1)
221
222#define IXGBE_RX_DESC_ADV(R, i) \
223 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
224#define IXGBE_TX_DESC_ADV(R, i) \
225 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
226#define IXGBE_TX_CTXTDESC_ADV(R, i) \
227 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
228
da4dd0f7
PWJ		 229#define IXGBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
230#define IXGBE_TX_DESC(R, i) IXGBE_GET_DESC(R, i, ixgbe_legacy_tx_desc)
231#define IXGBE_RX_DESC(R, i) IXGBE_GET_DESC(R, i, ixgbe_legacy_rx_desc)
232
9a799d71 233#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
63f39bd1
YZ		 234#ifdef IXGBE_FCOE
235/* Use 3K as the baby jumbo frame size for FCoE */
236#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
237#endif /* IXGBE_FCOE */
9a799d71 238
021230d4
AV		 239#define OTHER_VECTOR 1
240#define NON_Q_VECTORS (OTHER_VECTOR)
241
e8e26350
PW		 242#define MAX_MSIX_VECTORS_82599 64
243#define MAX_MSIX_Q_VECTORS_82599 64
eb7f139c
PWJ		 244#define MAX_MSIX_VECTORS_82598 18
245#define MAX_MSIX_Q_VECTORS_82598 16
246
e8e26350
PW		 247#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
248#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c 249
021230d4 250#define MIN_MSIX_Q_VECTORS 2
021230d4
AV		 251#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
252
9a799d71
AK		 253/* board specific private data structure */
254struct ixgbe_adapter {
255 struct timer_list watchdog_timer;
256 struct vlan_group *vlgrp;
257 u16 bd_number;
9a799d71 258 struct work_struct reset_task;
7a921c93 259 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
e8e26350 260 char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
2f90b865
AD		 261 struct ixgbe_dcb_config dcb_cfg;
262 struct ixgbe_dcb_config temp_dcb_cfg;
263 u8 dcb_set_bitmap;
264857b8 264 enum ixgbe_fc_mode last_lfc_mode;
9a799d71 265
f494e8fa
AV		 266 /* Interrupt Throttle Rate */
267 u32 itr_setting;
268 u16 eitr_low;
269 u16 eitr_high;
270
9a799d71
AK		 271 /* TX */
272 struct ixgbe_ring *tx_ring; /* One per active queue */
30efa5a3 273 int num_tx_queues;
9a799d71 274 u64 restart_queue;
30efa5a3 275 u64 hw_csum_tx_good;
9a799d71
AK		 276 u64 lsc_int;
277 u64 hw_tso_ctxt;
278 u64 hw_tso6_ctxt;
279 u32 tx_timeout_count;
280 bool detect_tx_hung;
281
282 /* RX */
283 struct ixgbe_ring *rx_ring; /* One per active queue */
30efa5a3 284 int num_rx_queues;
9a799d71 285 u64 hw_csum_rx_error;
e8e26350 286 u64 hw_rx_no_dma_resources;
9a799d71
AK		 287 u64 hw_csum_rx_good;
288 u64 non_eop_descs;
021230d4 289 int num_msix_vectors;
eb7f139c 290 int max_msix_q_vectors; /* true count of q_vectors for device */
c7e4358a 291 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
9a799d71
AK		 292 struct msix_entry *msix_entries;
293
294 u64 rx_hdr_split;
295 u32 alloc_rx_page_failed;
296 u32 alloc_rx_buff_failed;
297
021230d4
AV		 298 /* Some features need tri-state capability,
299 * thus the additional *_CAPABLE flags.
300 */
9a799d71 301 u32 flags;
96b0e0f6
JB		 302#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
303#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
304#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
305#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
306#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
307#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
308#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
309#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
310#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
311#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
312#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
313#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
314#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
e8e26350 315#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
96b0e0f6
JB		 316#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
317#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
318#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
319#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
0befdb3e 320#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
96b0e0f6
JB		 321#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
322#define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 23)
e8e26350
PW		 323#define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 24)
324#define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 25)
c4cf55e5
PWJ		 325#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 26)
326#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 27)
eacd73f7 327#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 29)
96b0e0f6 328
df647b5c
PWJ		 329 u32 flags2;
330#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
331#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
96b0e0f6
JB		 332/* default to trying for four seconds */
333#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71
AK		 334
335 /* OS defined structs */
336 struct net_device *netdev;
337 struct pci_dev *pdev;
338 struct net_device_stats net_stats;
339
da4dd0f7
PWJ		 340 u32 test_icr;
341 struct ixgbe_ring test_tx_ring;
342 struct ixgbe_ring test_rx_ring;
343
9a799d71
AK		 344 /* structs defined in ixgbe_hw.h */
345 struct ixgbe_hw hw;
346 u16 msg_enable;
347 struct ixgbe_hw_stats stats;
021230d4
AV		 348
349 /* Interrupt Throttle Rate */
30efa5a3 350 u32 eitr_param;
9a799d71
AK		 351
352 unsigned long state;
353 u64 tx_busy;
30efa5a3
JB		 354 unsigned int tx_ring_count;
355 unsigned int rx_ring_count;
cf8280ee
JB		 356
357 u32 link_speed;
358 bool link_up;
359 unsigned long link_check_timeout;
360
361 struct work_struct watchdog_task;
c4900be0
DS		 362 struct work_struct sfp_task;
363 struct timer_list sfp_timer;
e8e26350
PW		 364 struct work_struct multispeed_fiber_task;
365 struct work_struct sfp_config_module_task;
c4cf55e5
PWJ		 366 u32 fdir_pballoc;
367 u32 atr_sample_rate;
368 spinlock_t fdir_perfect_lock;
369 struct work_struct fdir_reinit_task;
d0ed8937
YZ		 370#ifdef IXGBE_FCOE
371 struct ixgbe_fcoe fcoe;
372#endif /* IXGBE_FCOE */
f8212f97 373 u64 rsc_count;
e8e26350 374 u32 wol;
34b0368c 375 u16 eeprom_version;
9a799d71
AK		 376};
377
378enum ixbge_state_t {
379 __IXGBE_TESTING,
380 __IXGBE_RESETTING,
c4900be0 381 __IXGBE_DOWN,
c4cf55e5 382 __IXGBE_FDIR_INIT_DONE,
c4900be0 383 __IXGBE_SFP_MODULE_NOT_FOUND
9a799d71
AK		 384};
385
386enum ixgbe_boards {
3957d63d 387 board_82598,
e8e26350 388 board_82599,
9a799d71
AK		 389};
390
3957d63d 391extern struct ixgbe_info ixgbe_82598_info;
e8e26350 392extern struct ixgbe_info ixgbe_82599_info;
7a6b6f51 393#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 394extern struct dcbnl_rtnl_ops dcbnl_ops;
395extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
396 struct ixgbe_dcb_config *dst_dcb_cfg,
397 int tc_max);
398#endif
9a799d71
AK		 399
400extern char ixgbe_driver_name[];
9c8eb720 401extern const char ixgbe_driver_version[];
9a799d71
AK		 402
403extern int ixgbe_up(struct ixgbe_adapter *adapter);
404extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882 405extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71 406extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71 407extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b4617240
PW		 408extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
409extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
410extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
411extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
412extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865 413extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
7a921c93 414extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
fe49f04a
AD		 415extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
416extern int ethtool_ioctl(struct ifreq *ifr);
ffff4772
PWJ		 417extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
418extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
419extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
420extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
421 struct ixgbe_atr_input *input,
422 u8 queue);
423extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
424 struct ixgbe_atr_input *input,
425 u16 soft_id,
426 u8 queue);
427extern u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *input, u32 key);
428extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
429 u16 vlan_id);
430extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
431 u32 src_addr);
432extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
433 u32 dst_addr);
434extern s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
435 u32 src_addr_1, u32 src_addr_2,
436 u32 src_addr_3, u32 src_addr_4);
437extern s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
438 u32 dst_addr_1, u32 dst_addr_2,
439 u32 dst_addr_3, u32 dst_addr_4);
440extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
441 u16 src_port);
442extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
443 u16 dst_port);
444extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
445 u16 flex_byte);
446extern s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
447 u8 vm_pool);
448extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
449 u8 l4type);
450extern s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input,
451 u16 *vlan_id);
452extern s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
453 u32 *src_addr);
454extern s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
455 u32 *dst_addr);
456extern s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
457 u32 *src_addr_1, u32 *src_addr_2,
458 u32 *src_addr_3, u32 *src_addr_4);
459extern s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
460 u32 *dst_addr_1, u32 *dst_addr_2,
461 u32 *dst_addr_3, u32 *dst_addr_4);
462extern s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
463 u16 *src_port);
464extern s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
465 u16 *dst_port);
466extern s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
467 u16 *flex_byte);
468extern s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
469 u8 *vm_pool);
470extern s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
471 u8 *l4type);
eacd73f7
YZ		 472#ifdef IXGBE_FCOE
473extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
474extern int ixgbe_fso(struct ixgbe_adapter *adapter,
475 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
476 u32 tx_flags, u8 *hdr_len);
332d4a7d
YZ		 477extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
478extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
479 union ixgbe_adv_rx_desc *rx_desc,
480 struct sk_buff *skb);
481extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
482 struct scatterlist *sgl, unsigned int sgc);
483extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
eacd73f7 484#endif /* IXGBE_FCOE */
9a799d71
AK		 485
486#endif /* _IXGBE_H_ */
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