[net-next-2.6.git] / drivers / net / ixgbe / ixgbe.h

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2008 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _IXGBE_H_
#define _IXGBE_H_

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/inet_lro.h>

#include "ixgbe_type.h"
#include "ixgbe_common.h"
#include "ixgbe_dcb.h"
#ifdef CONFIG_IXGBE_DCA
#include <linux/dca.h>
#endif

#define PFX "ixgbe: "
#define DPRINTK(nlevel, klevel, fmt, args...) \
	((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
	printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
		__func__ , ## args)))

/* TX/RX descriptor defines */
#define IXGBE_DEFAULT_TXD		   1024
#define IXGBE_MAX_TXD			   4096
#define IXGBE_MIN_TXD			     64

#define IXGBE_DEFAULT_RXD		   1024
#define IXGBE_MAX_RXD			   4096
#define IXGBE_MIN_RXD			     64

/* flow control */
#define IXGBE_DEFAULT_FCRTL		0x10000
#define IXGBE_MIN_FCRTL			   0x40
#define IXGBE_MAX_FCRTL			0x7FF80
#define IXGBE_DEFAULT_FCRTH		0x20000
#define IXGBE_MIN_FCRTH			  0x600
#define IXGBE_MAX_FCRTH			0x7FFF0
#define IXGBE_DEFAULT_FCPAUSE		 0xFFFF
#define IXGBE_MIN_FCPAUSE		      0
#define IXGBE_MAX_FCPAUSE		 0xFFFF

/* Supported Rx Buffer Sizes */
#define IXGBE_RXBUFFER_64    64     /* Used for packet split */
#define IXGBE_RXBUFFER_128   128    /* Used for packet split */
#define IXGBE_RXBUFFER_256   256    /* Used for packet split */
#define IXGBE_RXBUFFER_2048  2048

#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256

#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)

/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IXGBE_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define IXGBE_TX_FLAGS_CSUM		(u32)(1)
#define IXGBE_TX_FLAGS_VLAN		(u32)(1 << 1)
#define IXGBE_TX_FLAGS_TSO		(u32)(1 << 2)
#define IXGBE_TX_FLAGS_IPV4		(u32)(1 << 3)
#define IXGBE_TX_FLAGS_VLAN_MASK	0xffff0000
#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0x0000e000
#define IXGBE_TX_FLAGS_VLAN_SHIFT	16

#define IXGBE_MAX_LRO_DESCRIPTORS       8
#define IXGBE_MAX_LRO_AGGREGATE         32

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct ixgbe_tx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	unsigned long time_stamp;
	u16 length;
	u16 next_to_watch;
};

struct ixgbe_rx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	struct page *page;
	dma_addr_t page_dma;
	unsigned int page_offset;
};

struct ixgbe_queue_stats {
	u64 packets;
	u64 bytes;
};

struct ixgbe_ring {
	void *desc;			/* descriptor ring memory */
	dma_addr_t dma;			/* phys. address of descriptor ring */
	unsigned int size;		/* length in bytes */
	unsigned int count;		/* amount of descriptors */
	unsigned int next_to_use;
	unsigned int next_to_clean;

	int queue_index; /* needed for multiqueue queue management */
	union {
		struct ixgbe_tx_buffer *tx_buffer_info;
		struct ixgbe_rx_buffer *rx_buffer_info;
	};

	u16 head;
	u16 tail;

	unsigned int total_bytes;
	unsigned int total_packets;

	u16 reg_idx; /* holds the special value that gets the hardware register
		      * offset associated with this ring, which is different
		      * for DCB and RSS modes */

#ifdef CONFIG_IXGBE_DCA
	/* cpu for tx queue */
	int cpu;
#endif
	struct net_lro_mgr lro_mgr;
	bool lro_used;
	struct ixgbe_queue_stats stats;
	u16 v_idx; /* maps directly to the index for this ring in the hardware
	           * vector array, can also be used for finding the bit in EICR
	           * and friends that represents the vector for this ring */


	u16 work_limit;                /* max work per interrupt */
	u16 rx_buf_len;
};

#define RING_F_DCB  0
#define RING_F_VMDQ 1
#define RING_F_RSS  2
#define IXGBE_MAX_DCB_INDICES   8
#define IXGBE_MAX_RSS_INDICES  16
#define IXGBE_MAX_VMDQ_INDICES 16
struct ixgbe_ring_feature {
	int indices;
	int mask;
};

#define MAX_RX_QUEUES 64
#define MAX_TX_QUEUES 32

#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
                              ? 8 : 1)
#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS

/* MAX_MSIX_Q_VECTORS of these are allocated,
 * but we only use one per queue-specific vector.
 */
struct ixgbe_q_vector {
	struct ixgbe_adapter *adapter;
	struct napi_struct napi;
	DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
	DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
	u8 rxr_count;     /* Rx ring count assigned to this vector */
	u8 txr_count;     /* Tx ring count assigned to this vector */
	u8 tx_itr;
	u8 rx_itr;
	u32 eitr;
};

/* Helper macros to switch between ints/sec and what the register uses.
 * And yes, it's the same math going both ways.
 */
#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG

#define IXGBE_DESC_UNUSED(R) \
	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	(R)->next_to_clean - (R)->next_to_use - 1)

#define IXGBE_RX_DESC_ADV(R, i)	    \
	(&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
#define IXGBE_TX_DESC_ADV(R, i)	    \
	(&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
#define IXGBE_TX_CTXTDESC_ADV(R, i)	    \
	(&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))

#define IXGBE_MAX_JUMBO_FRAME_SIZE        16128

#define OTHER_VECTOR 1
#define NON_Q_VECTORS (OTHER_VECTOR)

#define MAX_MSIX_Q_VECTORS 16
#define MIN_MSIX_Q_VECTORS 2
#define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)

/* board specific private data structure */
struct ixgbe_adapter {
	struct timer_list watchdog_timer;
	struct vlan_group *vlgrp;
	u16 bd_number;
	struct work_struct reset_task;
	struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
	char name[MAX_MSIX_COUNT][IFNAMSIZ + 5];
	struct ixgbe_dcb_config dcb_cfg;
	struct ixgbe_dcb_config temp_dcb_cfg;
	u8 dcb_set_bitmap;

	/* Interrupt Throttle Rate */
	u32 itr_setting;
	u16 eitr_low;
	u16 eitr_high;

	/* TX */
	struct ixgbe_ring *tx_ring;	/* One per active queue */
	int num_tx_queues;
	u64 restart_queue;
	u64 hw_csum_tx_good;
	u64 lsc_int;
	u64 hw_tso_ctxt;
	u64 hw_tso6_ctxt;
	u32 tx_timeout_count;
	bool detect_tx_hung;

	/* RX */
	struct ixgbe_ring *rx_ring;	/* One per active queue */
	int num_rx_queues;
	u64 hw_csum_rx_error;
	u64 hw_csum_rx_good;
	u64 non_eop_descs;
	int num_msix_vectors;
	struct ixgbe_ring_feature ring_feature[3];
	struct msix_entry *msix_entries;

	u64 rx_hdr_split;
	u32 alloc_rx_page_failed;
	u32 alloc_rx_buff_failed;

	/* Some features need tri-state capability,
	 * thus the additional *_CAPABLE flags.
	 */
	u32 flags;
#define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
#define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
#define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
#define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
#define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
#define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
#define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
#define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
#define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
#define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
#define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
#define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
#define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
#define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
#define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
#define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
#define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
#define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 20)
#define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
#define IXGBE_FLAG_IN_WATCHDOG_TASK             (u32)(1 << 23)
#define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 24)

/* default to trying for four seconds */
#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)

	/* OS defined structs */
	struct net_device *netdev;
	struct pci_dev *pdev;
	struct net_device_stats net_stats;

	/* structs defined in ixgbe_hw.h */
	struct ixgbe_hw hw;
	u16 msg_enable;
	struct ixgbe_hw_stats stats;

	/* Interrupt Throttle Rate */
	u32 eitr_param;

	unsigned long state;
	u64 tx_busy;
	u64 lro_aggregated;
	u64 lro_flushed;
	u64 lro_no_desc;
	unsigned int tx_ring_count;
	unsigned int rx_ring_count;

	u32 link_speed;
	bool link_up;
	unsigned long link_check_timeout;

	struct work_struct watchdog_task;
	struct work_struct sfp_task;
	struct timer_list sfp_timer;
};

enum ixbge_state_t {
	__IXGBE_TESTING,
	__IXGBE_RESETTING,
	__IXGBE_DOWN,
	__IXGBE_SFP_MODULE_NOT_FOUND
};

enum ixgbe_boards {
	board_82598,
};

extern struct ixgbe_info ixgbe_82598_info;
#ifdef CONFIG_IXGBE_DCBNL
extern struct dcbnl_rtnl_ops dcbnl_ops;
extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
                              struct ixgbe_dcb_config *dst_dcb_cfg,
                              int tc_max);
#endif

extern char ixgbe_driver_name[];
extern const char ixgbe_driver_version[];

extern int ixgbe_up(struct ixgbe_adapter *adapter);
extern void ixgbe_down(struct ixgbe_adapter *adapter);
extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
extern void ixgbe_reset(struct ixgbe_adapter *adapter);
extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
extern void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter);
extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
void ixgbe_napi_add_all(struct ixgbe_adapter *adapter);
void ixgbe_napi_del_all(struct ixgbe_adapter *adapter);

#endif /* _IXGBE_H_ */
Commit	Line	Data
9a799d71 AK	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
b4617240	4	Copyright(c) 1999 - 2008 Intel Corporation.
9a799d71 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
9a799d71 AK	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#ifndef _IXGBE_H_
	29	#define _IXGBE_H_
	30
	31	#include <linux/types.h>
	32	#include <linux/pci.h>
	33	#include <linux/netdevice.h>
177db6ff	34	#include <linux/inet_lro.h>
9a799d71 AK	35
	36	#include "ixgbe_type.h"
	37	#include "ixgbe_common.h"
2f90b865	38	#include "ixgbe_dcb.h"
5dd2d332	39	#ifdef CONFIG_IXGBE_DCA
bd0362dd JC	40	#include <linux/dca.h>
bd0362dd JC	41	#endif
9a799d71	42
9a799d71 AK	43	#define PFX "ixgbe: "
	44	#define DPRINTK(nlevel, klevel, fmt, args...) \
	45	((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
	46	printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
b39d66a8	47	__func__ , ## args)))
9a799d71 AK	48
	49	/* TX/RX descriptor defines */
	50	#define IXGBE_DEFAULT_TXD 1024
	51	#define IXGBE_MAX_TXD 4096
	52	#define IXGBE_MIN_TXD 64
	53
	54	#define IXGBE_DEFAULT_RXD 1024
	55	#define IXGBE_MAX_RXD 4096
	56	#define IXGBE_MIN_RXD 64
	57
9a799d71 AK	58	/* flow control */
9a799d71 AK	59	#define IXGBE_DEFAULT_FCRTL 0x10000
2b9ade93	60	#define IXGBE_MIN_FCRTL 0x40
9a799d71 AK	61	#define IXGBE_MAX_FCRTL 0x7FF80
9a799d71 AK	62	#define IXGBE_DEFAULT_FCRTH 0x20000
2b9ade93	63	#define IXGBE_MIN_FCRTH 0x600
9a799d71	64	#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93	65	#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71 AK	66	#define IXGBE_MIN_FCPAUSE 0
	67	#define IXGBE_MAX_FCPAUSE 0xFFFF
	68
	69	/* Supported Rx Buffer Sizes */
	70	#define IXGBE_RXBUFFER_64 64 /* Used for packet split */
	71	#define IXGBE_RXBUFFER_128 128 /* Used for packet split */
	72	#define IXGBE_RXBUFFER_256 256 /* Used for packet split */
	73	#define IXGBE_RXBUFFER_2048 2048
	74
	75	#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
	76
	77	#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
	78
9a799d71 AK	79	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	80	#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	81
	82	#define IXGBE_TX_FLAGS_CSUM (u32)(1)
	83	#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
	84	#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
	85	#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
	86	#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
2f90b865	87	#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
9a799d71 AK	88	#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
9a799d71 AK	89
177db6ff MC	90	#define IXGBE_MAX_LRO_DESCRIPTORS 8
	91	#define IXGBE_MAX_LRO_AGGREGATE 32
	92
9a799d71 AK	93	/* wrapper around a pointer to a socket buffer,
	94	* so a DMA handle can be stored along with the buffer */
	95	struct ixgbe_tx_buffer {
	96	struct sk_buff *skb;
	97	dma_addr_t dma;
	98	unsigned long time_stamp;
	99	u16 length;
	100	u16 next_to_watch;
	101	};
	102
	103	struct ixgbe_rx_buffer {
	104	struct sk_buff *skb;
	105	dma_addr_t dma;
	106	struct page *page;
	107	dma_addr_t page_dma;
762f4c57	108	unsigned int page_offset;
9a799d71 AK	109	};
	110
	111	struct ixgbe_queue_stats {
	112	u64 packets;
	113	u64 bytes;
	114	};
	115
	116	struct ixgbe_ring {
9a799d71 AK	117	void desc; / descriptor ring memory */
	118	dma_addr_t dma; /* phys. address of descriptor ring */
	119	unsigned int size; /* length in bytes */
	120	unsigned int count; /* amount of descriptors */
	121	unsigned int next_to_use;
	122	unsigned int next_to_clean;
	123
021230d4	124	int queue_index; /* needed for multiqueue queue management */
9a799d71 AK	125	union {
	126	struct ixgbe_tx_buffer *tx_buffer_info;
	127	struct ixgbe_rx_buffer *rx_buffer_info;
	128	};
	129
	130	u16 head;
	131	u16 tail;
	132
f494e8fa AV	133	unsigned int total_bytes;
f494e8fa AV	134	unsigned int total_packets;
9a799d71	135
021230d4 AV	136	u16 reg_idx; /* holds the special value that gets the hardware register
021230d4 AV	137	* offset associated with this ring, which is different
2f90b865	138	* for DCB and RSS modes */
bd0362dd	139
5dd2d332	140	#ifdef CONFIG_IXGBE_DCA
bd0362dd JC	141	/* cpu for tx queue */
	142	int cpu;
	143	#endif
177db6ff MC	144	struct net_lro_mgr lro_mgr;
177db6ff MC	145	bool lro_used;
9a799d71	146	struct ixgbe_queue_stats stats;
ff819cfb JB	147	u16 v_idx; /* maps directly to the index for this ring in the hardware
	148	* vector array, can also be used for finding the bit in EICR
	149	* and friends that represents the vector for this ring */
9a799d71	150
9a799d71	151
9a799d71	152	u16 work_limit; /* max work per interrupt */
7c6e0a43	153	u16 rx_buf_len;
9a799d71 AK	154	};
9a799d71 AK	155
2f90b865	156	#define RING_F_DCB 0
021230d4 AV	157	#define RING_F_VMDQ 1
021230d4 AV	158	#define RING_F_RSS 2
2f90b865	159	#define IXGBE_MAX_DCB_INDICES 8
021230d4 AV	160	#define IXGBE_MAX_RSS_INDICES 16
	161	#define IXGBE_MAX_VMDQ_INDICES 16
	162	struct ixgbe_ring_feature {
	163	int indices;
	164	int mask;
	165	};
	166
	167	#define MAX_RX_QUEUES 64
	168	#define MAX_TX_QUEUES 32
	169
2f90b865 AD	170	#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
	171	? 8 : 1)
	172	#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
	173
021230d4 AV	174	/* MAX_MSIX_Q_VECTORS of these are allocated,
	175	* but we only use one per queue-specific vector.
	176	*/
	177	struct ixgbe_q_vector {
	178	struct ixgbe_adapter *adapter;
	179	struct napi_struct napi;
	180	DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
	181	DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
	182	u8 rxr_count; /* Rx ring count assigned to this vector */
	183	u8 txr_count; /* Tx ring count assigned to this vector */
30efa5a3 JB	184	u8 tx_itr;
30efa5a3 JB	185	u8 rx_itr;
021230d4 AV	186	u32 eitr;
	187	};
	188
9a799d71 AK	189	/* Helper macros to switch between ints/sec and what the register uses.
	190	* And yes, it's the same math going both ways.
	191	*/
	192	#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
	193	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
	194	#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
	195
	196	#define IXGBE_DESC_UNUSED(R) \
	197	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	198	(R)->next_to_clean - (R)->next_to_use - 1)
	199
	200	#define IXGBE_RX_DESC_ADV(R, i) \
	201	(&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
	202	#define IXGBE_TX_DESC_ADV(R, i) \
	203	(&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
	204	#define IXGBE_TX_CTXTDESC_ADV(R, i) \
	205	(&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
	206
	207	#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
	208
021230d4 AV	209	#define OTHER_VECTOR 1
	210	#define NON_Q_VECTORS (OTHER_VECTOR)
	211
	212	#define MAX_MSIX_Q_VECTORS 16
	213	#define MIN_MSIX_Q_VECTORS 2
	214	#define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
	215	#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
	216
9a799d71 AK	217	/* board specific private data structure */
	218	struct ixgbe_adapter {
	219	struct timer_list watchdog_timer;
	220	struct vlan_group *vlgrp;
	221	u16 bd_number;
9a799d71	222	struct work_struct reset_task;
021230d4 AV	223	struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
021230d4 AV	224	char name[MAX_MSIX_COUNT][IFNAMSIZ + 5];
2f90b865 AD	225	struct ixgbe_dcb_config dcb_cfg;
	226	struct ixgbe_dcb_config temp_dcb_cfg;
	227	u8 dcb_set_bitmap;
9a799d71	228
f494e8fa AV	229	/* Interrupt Throttle Rate */
	230	u32 itr_setting;
	231	u16 eitr_low;
	232	u16 eitr_high;
	233
9a799d71 AK	234	/* TX */
9a799d71 AK	235	struct ixgbe_ring tx_ring; / One per active queue */
30efa5a3	236	int num_tx_queues;
9a799d71	237	u64 restart_queue;
30efa5a3	238	u64 hw_csum_tx_good;
9a799d71 AK	239	u64 lsc_int;
	240	u64 hw_tso_ctxt;
	241	u64 hw_tso6_ctxt;
	242	u32 tx_timeout_count;
	243	bool detect_tx_hung;
	244
	245	/* RX */
	246	struct ixgbe_ring rx_ring; / One per active queue */
30efa5a3	247	int num_rx_queues;
9a799d71 AK	248	u64 hw_csum_rx_error;
	249	u64 hw_csum_rx_good;
	250	u64 non_eop_descs;
021230d4 AV	251	int num_msix_vectors;
021230d4 AV	252	struct ixgbe_ring_feature ring_feature[3];
9a799d71 AK	253	struct msix_entry *msix_entries;
	254
	255	u64 rx_hdr_split;
	256	u32 alloc_rx_page_failed;
	257	u32 alloc_rx_buff_failed;
	258
021230d4 AV	259	/* Some features need tri-state capability,
	260	* thus the additional *_CAPABLE flags.
	261	*/
9a799d71	262	u32 flags;
96b0e0f6 JB	263	#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
	264	#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
	265	#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
	266	#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
	267	#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
	268	#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
	269	#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
	270	#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
	271	#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
	272	#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
	273	#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
	274	#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
	275	#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
	276	#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
	277	#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
	278	#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
	279	#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
0befdb3e	280	#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
96b0e0f6 JB	281	#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
96b0e0f6 JB	282	#define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 23)
2f90b865	283	#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 24)
96b0e0f6 JB	284
	285	/* default to trying for four seconds */
	286	#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71 AK	287
	288	/* OS defined structs */
	289	struct net_device *netdev;
	290	struct pci_dev *pdev;
	291	struct net_device_stats net_stats;
	292
	293	/* structs defined in ixgbe_hw.h */
	294	struct ixgbe_hw hw;
	295	u16 msg_enable;
	296	struct ixgbe_hw_stats stats;
021230d4 AV	297
021230d4 AV	298	/* Interrupt Throttle Rate */
30efa5a3	299	u32 eitr_param;
9a799d71 AK	300
	301	unsigned long state;
	302	u64 tx_busy;
177db6ff MC	303	u64 lro_aggregated;
	304	u64 lro_flushed;
	305	u64 lro_no_desc;
30efa5a3 JB	306	unsigned int tx_ring_count;
30efa5a3 JB	307	unsigned int rx_ring_count;
cf8280ee JB	308
	309	u32 link_speed;
	310	bool link_up;
	311	unsigned long link_check_timeout;
	312
	313	struct work_struct watchdog_task;
c4900be0 DS	314	struct work_struct sfp_task;
c4900be0 DS	315	struct timer_list sfp_timer;
9a799d71 AK	316	};
	317
	318	enum ixbge_state_t {
	319	__IXGBE_TESTING,
	320	__IXGBE_RESETTING,
c4900be0 DS	321	__IXGBE_DOWN,
c4900be0 DS	322	__IXGBE_SFP_MODULE_NOT_FOUND
9a799d71 AK	323	};
	324
	325	enum ixgbe_boards {
3957d63d	326	board_82598,
9a799d71 AK	327	};
9a799d71 AK	328
3957d63d	329	extern struct ixgbe_info ixgbe_82598_info;
2f90b865 AD	330	#ifdef CONFIG_IXGBE_DCBNL
	331	extern struct dcbnl_rtnl_ops dcbnl_ops;
	332	extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
	333	struct ixgbe_dcb_config *dst_dcb_cfg,
	334	int tc_max);
	335	#endif
9a799d71 AK	336
9a799d71 AK	337	extern char ixgbe_driver_name[];
9c8eb720	338	extern const char ixgbe_driver_version[];
9a799d71 AK	339
	340	extern int ixgbe_up(struct ixgbe_adapter *adapter);
	341	extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882	342	extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71	343	extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71	344	extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b4617240 PW	345	extern int ixgbe_setup_rx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	346	extern int ixgbe_setup_tx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	347	extern void ixgbe_free_rx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	348	extern void ixgbe_free_tx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	349	extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865 AD	350	extern void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter);
	351	extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
	352	void ixgbe_napi_add_all(struct ixgbe_adapter *adapter);
	353	void ixgbe_napi_del_all(struct ixgbe_adapter *adapter);
9a799d71 AK	354
9a799d71 AK	355	#endif /* _IXGBE_H_ */