[net-next-2.6.git] / drivers / net / ixgbe / ixgbe.h

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2009 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _IXGBE_H_
#define _IXGBE_H_

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/aer.h>

#include "ixgbe_type.h"
#include "ixgbe_common.h"
#include "ixgbe_dcb.h"
#ifdef CONFIG_IXGBE_DCA
#include <linux/dca.h>
#endif

#define PFX "ixgbe: "
#define DPRINTK(nlevel, klevel, fmt, args...) \
	((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
	printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
		__func__ , ## args)))

/* TX/RX descriptor defines */
#define IXGBE_DEFAULT_TXD		   1024
#define IXGBE_MAX_TXD			   4096
#define IXGBE_MIN_TXD			     64

#define IXGBE_DEFAULT_RXD		   1024
#define IXGBE_MAX_RXD			   4096
#define IXGBE_MIN_RXD			     64

/* flow control */
#define IXGBE_DEFAULT_FCRTL		0x10000
#define IXGBE_MIN_FCRTL			   0x40
#define IXGBE_MAX_FCRTL			0x7FF80
#define IXGBE_DEFAULT_FCRTH		0x20000
#define IXGBE_MIN_FCRTH			  0x600
#define IXGBE_MAX_FCRTH			0x7FFF0
#define IXGBE_DEFAULT_FCPAUSE		 0xFFFF
#define IXGBE_MIN_FCPAUSE		      0
#define IXGBE_MAX_FCPAUSE		 0xFFFF

/* Supported Rx Buffer Sizes */
#define IXGBE_RXBUFFER_64    64     /* Used for packet split */
#define IXGBE_RXBUFFER_128   128    /* Used for packet split */
#define IXGBE_RXBUFFER_256   256    /* Used for packet split */
#define IXGBE_RXBUFFER_2048  2048
#define IXGBE_MAX_RXBUFFER   16384  /* largest size for a single descriptor */

#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256

#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)

/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IXGBE_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define IXGBE_TX_FLAGS_CSUM		(u32)(1)
#define IXGBE_TX_FLAGS_VLAN		(u32)(1 << 1)
#define IXGBE_TX_FLAGS_TSO		(u32)(1 << 2)
#define IXGBE_TX_FLAGS_IPV4		(u32)(1 << 3)
#define IXGBE_TX_FLAGS_VLAN_MASK	0xffff0000
#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0x0000e000
#define IXGBE_TX_FLAGS_VLAN_SHIFT	16

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct ixgbe_tx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	unsigned long time_stamp;
	u16 length;
	u16 next_to_watch;
};

struct ixgbe_rx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	struct page *page;
	dma_addr_t page_dma;
	unsigned int page_offset;
};

struct ixgbe_queue_stats {
	u64 packets;
	u64 bytes;
};

struct ixgbe_ring {
	void *desc;			/* descriptor ring memory */
	dma_addr_t dma;			/* phys. address of descriptor ring */
	unsigned int size;		/* length in bytes */
	unsigned int count;		/* amount of descriptors */
	unsigned int next_to_use;
	unsigned int next_to_clean;

	int queue_index; /* needed for multiqueue queue management */
	union {
		struct ixgbe_tx_buffer *tx_buffer_info;
		struct ixgbe_rx_buffer *rx_buffer_info;
	};

	u16 head;
	u16 tail;

	unsigned int total_bytes;
	unsigned int total_packets;

	u16 reg_idx; /* holds the special value that gets the hardware register
		      * offset associated with this ring, which is different
		      * for DCB and RSS modes */

#ifdef CONFIG_IXGBE_DCA
	/* cpu for tx queue */
	int cpu;
#endif
	struct ixgbe_queue_stats stats;
	u64 v_idx; /* maps directly to the index for this ring in the hardware
	            * vector array, can also be used for finding the bit in EICR
	            * and friends that represents the vector for this ring */


	u16 work_limit;                /* max work per interrupt */
	u16 rx_buf_len;
};

enum ixgbe_ring_f_enum {
	RING_F_NONE = 0,
	RING_F_DCB,
	RING_F_VMDQ,
	RING_F_RSS,

	RING_F_ARRAY_SIZE      /* must be last in enum set */
};

#define IXGBE_MAX_DCB_INDICES   8
#define IXGBE_MAX_RSS_INDICES  16
#define IXGBE_MAX_VMDQ_INDICES 16
struct ixgbe_ring_feature {
	int indices;
	int mask;
};

#define MAX_RX_QUEUES 128
#define MAX_TX_QUEUES 128

#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
                              ? 8 : 1)
#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS

/* MAX_MSIX_Q_VECTORS of these are allocated,
 * but we only use one per queue-specific vector.
 */
struct ixgbe_q_vector {
	struct ixgbe_adapter *adapter;
	struct napi_struct napi;
	DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
	DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
	u8 rxr_count;     /* Rx ring count assigned to this vector */
	u8 txr_count;     /* Tx ring count assigned to this vector */
	u8 tx_itr;
	u8 rx_itr;
	u32 eitr;
};

/* Helper macros to switch between ints/sec and what the register uses.
 * And yes, it's the same math going both ways.
 */
#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG

#define IXGBE_DESC_UNUSED(R) \
	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	(R)->next_to_clean - (R)->next_to_use - 1)

#define IXGBE_RX_DESC_ADV(R, i)	    \
	(&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
#define IXGBE_TX_DESC_ADV(R, i)	    \
	(&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
#define IXGBE_TX_CTXTDESC_ADV(R, i)	    \
	(&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))

#define IXGBE_MAX_JUMBO_FRAME_SIZE        16128

#define OTHER_VECTOR 1
#define NON_Q_VECTORS (OTHER_VECTOR)

#define MAX_MSIX_VECTORS_82599 64
#define MAX_MSIX_Q_VECTORS_82599 64
#define MAX_MSIX_VECTORS_82598 18
#define MAX_MSIX_Q_VECTORS_82598 16

#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599

#define MIN_MSIX_Q_VECTORS 2
#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)

/* board specific private data structure */
struct ixgbe_adapter {
	struct timer_list watchdog_timer;
	struct vlan_group *vlgrp;
	u16 bd_number;
	struct work_struct reset_task;
	struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
	char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
	struct ixgbe_dcb_config dcb_cfg;
	struct ixgbe_dcb_config temp_dcb_cfg;
	u8 dcb_set_bitmap;

	/* Interrupt Throttle Rate */
	u32 itr_setting;
	u16 eitr_low;
	u16 eitr_high;

	/* TX */
	struct ixgbe_ring *tx_ring;	/* One per active queue */
	int num_tx_queues;
	u64 restart_queue;
	u64 hw_csum_tx_good;
	u64 lsc_int;
	u64 hw_tso_ctxt;
	u64 hw_tso6_ctxt;
	u32 tx_timeout_count;
	bool detect_tx_hung;

	/* RX */
	struct ixgbe_ring *rx_ring;	/* One per active queue */
	int num_rx_queues;
	u64 hw_csum_rx_error;
	u64 hw_rx_no_dma_resources;
	u64 hw_csum_rx_good;
	u64 non_eop_descs;
	int num_msix_vectors;
	int max_msix_q_vectors;         /* true count of q_vectors for device */
	struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
	struct msix_entry *msix_entries;

	u64 rx_hdr_split;
	u32 alloc_rx_page_failed;
	u32 alloc_rx_buff_failed;

	/* Some features need tri-state capability,
	 * thus the additional *_CAPABLE flags.
	 */
	u32 flags;
#define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
#define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
#define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
#define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
#define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
#define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
#define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
#define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
#define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
#define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
#define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
#define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
#define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
#define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 14)
#define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
#define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
#define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
#define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
#define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 20)
#define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
#define IXGBE_FLAG_IN_WATCHDOG_TASK             (u32)(1 << 23)
#define IXGBE_FLAG_IN_SFP_LINK_TASK             (u32)(1 << 24)
#define IXGBE_FLAG_IN_SFP_MOD_TASK              (u32)(1 << 25)

/* default to trying for four seconds */
#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)

	/* OS defined structs */
	struct net_device *netdev;
	struct pci_dev *pdev;
	struct net_device_stats net_stats;

	/* structs defined in ixgbe_hw.h */
	struct ixgbe_hw hw;
	u16 msg_enable;
	struct ixgbe_hw_stats stats;

	/* Interrupt Throttle Rate */
	u32 eitr_param;

	unsigned long state;
	u64 tx_busy;
	unsigned int tx_ring_count;
	unsigned int rx_ring_count;

	u32 link_speed;
	bool link_up;
	unsigned long link_check_timeout;

	struct work_struct watchdog_task;
	struct work_struct sfp_task;
	struct timer_list sfp_timer;
	struct work_struct multispeed_fiber_task;
	struct work_struct sfp_config_module_task;
	u32 wol;
	u16 eeprom_version;
};

enum ixbge_state_t {
	__IXGBE_TESTING,
	__IXGBE_RESETTING,
	__IXGBE_DOWN,
	__IXGBE_SFP_MODULE_NOT_FOUND
};

enum ixgbe_boards {
	board_82598,
	board_82599,
};

extern struct ixgbe_info ixgbe_82598_info;
extern struct ixgbe_info ixgbe_82599_info;
#ifdef CONFIG_IXGBE_DCB
extern struct dcbnl_rtnl_ops dcbnl_ops;
extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
                              struct ixgbe_dcb_config *dst_dcb_cfg,
                              int tc_max);
#endif

extern char ixgbe_driver_name[];
extern const char ixgbe_driver_version[];

extern int ixgbe_up(struct ixgbe_adapter *adapter);
extern void ixgbe_down(struct ixgbe_adapter *adapter);
extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
extern void ixgbe_reset(struct ixgbe_adapter *adapter);
extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
extern void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter);
extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
void ixgbe_napi_add_all(struct ixgbe_adapter *adapter);
void ixgbe_napi_del_all(struct ixgbe_adapter *adapter);

#endif /* _IXGBE_H_ */
Commit	Line	Data
9a799d71 AK	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
3efac5a0	4	Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
9a799d71 AK	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#ifndef _IXGBE_H_
	29	#define _IXGBE_H_
	30
	31	#include <linux/types.h>
	32	#include <linux/pci.h>
	33	#include <linux/netdevice.h>
6fabd715	34	#include <linux/aer.h>
9a799d71 AK	35
	36	#include "ixgbe_type.h"
	37	#include "ixgbe_common.h"
2f90b865	38	#include "ixgbe_dcb.h"
5dd2d332	39	#ifdef CONFIG_IXGBE_DCA
bd0362dd JC	40	#include <linux/dca.h>
bd0362dd JC	41	#endif
9a799d71	42
9a799d71 AK	43	#define PFX "ixgbe: "
	44	#define DPRINTK(nlevel, klevel, fmt, args...) \
	45	((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
	46	printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
b39d66a8	47	__func__ , ## args)))
9a799d71 AK	48
	49	/* TX/RX descriptor defines */
	50	#define IXGBE_DEFAULT_TXD 1024
	51	#define IXGBE_MAX_TXD 4096
	52	#define IXGBE_MIN_TXD 64
	53
	54	#define IXGBE_DEFAULT_RXD 1024
	55	#define IXGBE_MAX_RXD 4096
	56	#define IXGBE_MIN_RXD 64
	57
9a799d71 AK	58	/* flow control */
9a799d71 AK	59	#define IXGBE_DEFAULT_FCRTL 0x10000
2b9ade93	60	#define IXGBE_MIN_FCRTL 0x40
9a799d71 AK	61	#define IXGBE_MAX_FCRTL 0x7FF80
9a799d71 AK	62	#define IXGBE_DEFAULT_FCRTH 0x20000
2b9ade93	63	#define IXGBE_MIN_FCRTH 0x600
9a799d71	64	#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93	65	#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71 AK	66	#define IXGBE_MIN_FCPAUSE 0
	67	#define IXGBE_MAX_FCPAUSE 0xFFFF
	68
	69	/* Supported Rx Buffer Sizes */
	70	#define IXGBE_RXBUFFER_64 64 /* Used for packet split */
	71	#define IXGBE_RXBUFFER_128 128 /* Used for packet split */
	72	#define IXGBE_RXBUFFER_256 256 /* Used for packet split */
	73	#define IXGBE_RXBUFFER_2048 2048
32344a39	74	#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71 AK	75
	76	#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
	77
	78	#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
	79
9a799d71 AK	80	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	81	#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	82
	83	#define IXGBE_TX_FLAGS_CSUM (u32)(1)
	84	#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
	85	#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
	86	#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
	87	#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
2f90b865	88	#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
9a799d71 AK	89	#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
	90
	91	/* wrapper around a pointer to a socket buffer,
	92	* so a DMA handle can be stored along with the buffer */
	93	struct ixgbe_tx_buffer {
	94	struct sk_buff *skb;
	95	dma_addr_t dma;
	96	unsigned long time_stamp;
	97	u16 length;
	98	u16 next_to_watch;
	99	};
	100
	101	struct ixgbe_rx_buffer {
	102	struct sk_buff *skb;
	103	dma_addr_t dma;
	104	struct page *page;
	105	dma_addr_t page_dma;
762f4c57	106	unsigned int page_offset;
9a799d71 AK	107	};
	108
	109	struct ixgbe_queue_stats {
	110	u64 packets;
	111	u64 bytes;
	112	};
	113
	114	struct ixgbe_ring {
9a799d71 AK	115	void desc; / descriptor ring memory */
	116	dma_addr_t dma; /* phys. address of descriptor ring */
	117	unsigned int size; /* length in bytes */
	118	unsigned int count; /* amount of descriptors */
	119	unsigned int next_to_use;
	120	unsigned int next_to_clean;
	121
021230d4	122	int queue_index; /* needed for multiqueue queue management */
9a799d71 AK	123	union {
	124	struct ixgbe_tx_buffer *tx_buffer_info;
	125	struct ixgbe_rx_buffer *rx_buffer_info;
	126	};
	127
	128	u16 head;
	129	u16 tail;
	130
f494e8fa AV	131	unsigned int total_bytes;
f494e8fa AV	132	unsigned int total_packets;
9a799d71	133
021230d4 AV	134	u16 reg_idx; /* holds the special value that gets the hardware register
021230d4 AV	135	* offset associated with this ring, which is different
2f90b865	136	* for DCB and RSS modes */
bd0362dd	137
5dd2d332	138	#ifdef CONFIG_IXGBE_DCA
bd0362dd JC	139	/* cpu for tx queue */
	140	int cpu;
	141	#endif
9a799d71	142	struct ixgbe_queue_stats stats;
e8e26350 PW	143	u64 v_idx; /* maps directly to the index for this ring in the hardware
	144	* vector array, can also be used for finding the bit in EICR
	145	* and friends that represents the vector for this ring */
9a799d71	146
9a799d71	147
9a799d71	148	u16 work_limit; /* max work per interrupt */
7c6e0a43	149	u16 rx_buf_len;
9a799d71 AK	150	};
9a799d71 AK	151
c7e4358a SN	152	enum ixgbe_ring_f_enum {
	153	RING_F_NONE = 0,
	154	RING_F_DCB,
	155	RING_F_VMDQ,
	156	RING_F_RSS,
	157
	158	RING_F_ARRAY_SIZE /* must be last in enum set */
	159	};
	160
2f90b865	161	#define IXGBE_MAX_DCB_INDICES 8
021230d4 AV	162	#define IXGBE_MAX_RSS_INDICES 16
	163	#define IXGBE_MAX_VMDQ_INDICES 16
	164	struct ixgbe_ring_feature {
	165	int indices;
	166	int mask;
	167	};
	168
e8e26350 PW	169	#define MAX_RX_QUEUES 128
e8e26350 PW	170	#define MAX_TX_QUEUES 128
021230d4	171
2f90b865 AD	172	#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
	173	? 8 : 1)
	174	#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
	175
021230d4 AV	176	/* MAX_MSIX_Q_VECTORS of these are allocated,
	177	* but we only use one per queue-specific vector.
	178	*/
	179	struct ixgbe_q_vector {
	180	struct ixgbe_adapter *adapter;
	181	struct napi_struct napi;
	182	DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
	183	DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
	184	u8 rxr_count; /* Rx ring count assigned to this vector */
	185	u8 txr_count; /* Tx ring count assigned to this vector */
30efa5a3 JB	186	u8 tx_itr;
30efa5a3 JB	187	u8 rx_itr;
021230d4 AV	188	u32 eitr;
	189	};
	190
9a799d71 AK	191	/* Helper macros to switch between ints/sec and what the register uses.
	192	* And yes, it's the same math going both ways.
	193	*/
	194	#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
	195	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
	196	#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
	197
	198	#define IXGBE_DESC_UNUSED(R) \
	199	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	200	(R)->next_to_clean - (R)->next_to_use - 1)
	201
	202	#define IXGBE_RX_DESC_ADV(R, i) \
	203	(&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
	204	#define IXGBE_TX_DESC_ADV(R, i) \
	205	(&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
	206	#define IXGBE_TX_CTXTDESC_ADV(R, i) \
	207	(&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
	208
	209	#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
	210
021230d4 AV	211	#define OTHER_VECTOR 1
	212	#define NON_Q_VECTORS (OTHER_VECTOR)
	213
e8e26350 PW	214	#define MAX_MSIX_VECTORS_82599 64
e8e26350 PW	215	#define MAX_MSIX_Q_VECTORS_82599 64
eb7f139c PWJ	216	#define MAX_MSIX_VECTORS_82598 18
	217	#define MAX_MSIX_Q_VECTORS_82598 16
	218
e8e26350 PW	219	#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
e8e26350 PW	220	#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c	221
021230d4	222	#define MIN_MSIX_Q_VECTORS 2
021230d4 AV	223	#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
021230d4 AV	224
9a799d71 AK	225	/* board specific private data structure */
	226	struct ixgbe_adapter {
	227	struct timer_list watchdog_timer;
	228	struct vlan_group *vlgrp;
	229	u16 bd_number;
9a799d71	230	struct work_struct reset_task;
021230d4	231	struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
e8e26350	232	char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
2f90b865 AD	233	struct ixgbe_dcb_config dcb_cfg;
	234	struct ixgbe_dcb_config temp_dcb_cfg;
	235	u8 dcb_set_bitmap;
9a799d71	236
f494e8fa AV	237	/* Interrupt Throttle Rate */
	238	u32 itr_setting;
	239	u16 eitr_low;
	240	u16 eitr_high;
	241
9a799d71 AK	242	/* TX */
9a799d71 AK	243	struct ixgbe_ring tx_ring; / One per active queue */
30efa5a3	244	int num_tx_queues;
9a799d71	245	u64 restart_queue;
30efa5a3	246	u64 hw_csum_tx_good;
9a799d71 AK	247	u64 lsc_int;
	248	u64 hw_tso_ctxt;
	249	u64 hw_tso6_ctxt;
	250	u32 tx_timeout_count;
	251	bool detect_tx_hung;
	252
	253	/* RX */
	254	struct ixgbe_ring rx_ring; / One per active queue */
30efa5a3	255	int num_rx_queues;
9a799d71	256	u64 hw_csum_rx_error;
e8e26350	257	u64 hw_rx_no_dma_resources;
9a799d71 AK	258	u64 hw_csum_rx_good;
9a799d71 AK	259	u64 non_eop_descs;
021230d4	260	int num_msix_vectors;
eb7f139c	261	int max_msix_q_vectors; /* true count of q_vectors for device */
c7e4358a	262	struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
9a799d71 AK	263	struct msix_entry *msix_entries;
	264
	265	u64 rx_hdr_split;
	266	u32 alloc_rx_page_failed;
	267	u32 alloc_rx_buff_failed;
	268
021230d4 AV	269	/* Some features need tri-state capability,
	270	* thus the additional *_CAPABLE flags.
	271	*/
9a799d71	272	u32 flags;
96b0e0f6 JB	273	#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
	274	#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
	275	#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
	276	#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
	277	#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
	278	#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
	279	#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
	280	#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
	281	#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
	282	#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
	283	#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
	284	#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
	285	#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
e8e26350	286	#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
96b0e0f6 JB	287	#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
	288	#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
	289	#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
	290	#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
0befdb3e	291	#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
96b0e0f6 JB	292	#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
96b0e0f6 JB	293	#define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 23)
e8e26350 PW	294	#define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 24)
e8e26350 PW	295	#define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 25)
96b0e0f6 JB	296
	297	/* default to trying for four seconds */
	298	#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71 AK	299
	300	/* OS defined structs */
	301	struct net_device *netdev;
	302	struct pci_dev *pdev;
	303	struct net_device_stats net_stats;
	304
	305	/* structs defined in ixgbe_hw.h */
	306	struct ixgbe_hw hw;
	307	u16 msg_enable;
	308	struct ixgbe_hw_stats stats;
021230d4 AV	309
021230d4 AV	310	/* Interrupt Throttle Rate */
30efa5a3	311	u32 eitr_param;
9a799d71 AK	312
	313	unsigned long state;
	314	u64 tx_busy;
30efa5a3 JB	315	unsigned int tx_ring_count;
30efa5a3 JB	316	unsigned int rx_ring_count;
cf8280ee JB	317
	318	u32 link_speed;
	319	bool link_up;
	320	unsigned long link_check_timeout;
	321
	322	struct work_struct watchdog_task;
c4900be0 DS	323	struct work_struct sfp_task;
c4900be0 DS	324	struct timer_list sfp_timer;
e8e26350 PW	325	struct work_struct multispeed_fiber_task;
	326	struct work_struct sfp_config_module_task;
	327	u32 wol;
34b0368c	328	u16 eeprom_version;
9a799d71 AK	329	};
	330
	331	enum ixbge_state_t {
	332	__IXGBE_TESTING,
	333	__IXGBE_RESETTING,
c4900be0 DS	334	__IXGBE_DOWN,
c4900be0 DS	335	__IXGBE_SFP_MODULE_NOT_FOUND
9a799d71 AK	336	};
	337
	338	enum ixgbe_boards {
3957d63d	339	board_82598,
e8e26350	340	board_82599,
9a799d71 AK	341	};
9a799d71 AK	342
3957d63d	343	extern struct ixgbe_info ixgbe_82598_info;
e8e26350	344	extern struct ixgbe_info ixgbe_82599_info;
7a6b6f51	345	#ifdef CONFIG_IXGBE_DCB
2f90b865 AD	346	extern struct dcbnl_rtnl_ops dcbnl_ops;
	347	extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
	348	struct ixgbe_dcb_config *dst_dcb_cfg,
	349	int tc_max);
	350	#endif
9a799d71 AK	351
9a799d71 AK	352	extern char ixgbe_driver_name[];
9c8eb720	353	extern const char ixgbe_driver_version[];
9a799d71 AK	354
	355	extern int ixgbe_up(struct ixgbe_adapter *adapter);
	356	extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882	357	extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71	358	extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71	359	extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b4617240 PW	360	extern int ixgbe_setup_rx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	361	extern int ixgbe_setup_tx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	362	extern void ixgbe_free_rx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	363	extern void ixgbe_free_tx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	364	extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865 AD	365	extern void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter);
	366	extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
	367	void ixgbe_napi_add_all(struct ixgbe_adapter *adapter);
	368	void ixgbe_napi_del_all(struct ixgbe_adapter *adapter);
9a799d71 AK	369
9a799d71 AK	370	#endif /* _IXGBE_H_ */